1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <stddef.h> 6 #include <errno.h> 7 #include <stdbool.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <unistd.h> 11 #include <inttypes.h> 12 #include <sys/queue.h> 13 14 #include "mlx5_autoconf.h" 15 16 #include <rte_mbuf.h> 17 #include <rte_malloc.h> 18 #include <rte_ethdev_driver.h> 19 #include <rte_common.h> 20 21 #include <mlx5_glue.h> 22 #include <mlx5_common.h> 23 #include <mlx5_common_mr.h> 24 #include <mlx5_rxtx.h> 25 #include <mlx5_verbs.h> 26 #include <mlx5_utils.h> 27 #include <mlx5_malloc.h> 28 29 /** 30 * Register mr. Given protection domain pointer, pointer to addr and length 31 * register the memory region. 32 * 33 * @param[in] pd 34 * Pointer to protection domain context. 35 * @param[in] addr 36 * Pointer to memory start address. 37 * @param[in] length 38 * Length of the memory to register. 39 * @param[out] pmd_mr 40 * pmd_mr struct set with lkey, address, length and pointer to mr object 41 * 42 * @return 43 * 0 on successful registration, -1 otherwise 44 */ 45 static int 46 mlx5_reg_mr(void *pd, void *addr, size_t length, 47 struct mlx5_pmd_mr *pmd_mr) 48 { 49 return mlx5_common_verbs_reg_mr(pd, addr, length, pmd_mr); 50 } 51 52 /** 53 * Deregister mr. Given the mlx5 pmd MR - deregister the MR 54 * 55 * @param[in] pmd_mr 56 * pmd_mr struct set with lkey, address, length and pointer to mr object 57 * 58 */ 59 static void 60 mlx5_dereg_mr(struct mlx5_pmd_mr *pmd_mr) 61 { 62 mlx5_common_verbs_dereg_mr(pmd_mr); 63 } 64 65 /* verbs operations. */ 66 const struct mlx5_verbs_ops mlx5_verbs_ops = { 67 .reg_mr = mlx5_reg_mr, 68 .dereg_mr = mlx5_dereg_mr, 69 }; 70 71 /** 72 * Modify Rx WQ vlan stripping offload 73 * 74 * @param rxq_obj 75 * Rx queue object. 76 * 77 * @return 0 on success, non-0 otherwise 78 */ 79 static int 80 mlx5_rxq_obj_modify_wq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on) 81 { 82 uint16_t vlan_offloads = 83 (on ? IBV_WQ_FLAGS_CVLAN_STRIPPING : 0) | 84 0; 85 struct ibv_wq_attr mod; 86 mod = (struct ibv_wq_attr){ 87 .attr_mask = IBV_WQ_ATTR_FLAGS, 88 .flags_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING, 89 .flags = vlan_offloads, 90 }; 91 92 return mlx5_glue->modify_wq(rxq_obj->wq, &mod); 93 } 94 95 /** 96 * Modifies the attributes for the specified WQ. 97 * 98 * @param rxq_obj 99 * Verbs Rx queue object. 100 * 101 * @return 102 * 0 on success, a negative errno value otherwise and rte_errno is set. 103 */ 104 static int 105 mlx5_ibv_modify_wq(struct mlx5_rxq_obj *rxq_obj, bool is_start) 106 { 107 struct ibv_wq_attr mod = { 108 .attr_mask = IBV_WQ_ATTR_STATE, 109 .wq_state = is_start ? IBV_WQS_RDY : IBV_WQS_RESET, 110 }; 111 112 return mlx5_glue->modify_wq(rxq_obj->wq, &mod); 113 } 114 115 /** 116 * Create a CQ Verbs object. 117 * 118 * @param dev 119 * Pointer to Ethernet device. 120 * @param idx 121 * Queue index in DPDK Rx queue array. 122 * 123 * @return 124 * The Verbs CQ object initialized, NULL otherwise and rte_errno is set. 125 */ 126 static struct ibv_cq * 127 mlx5_rxq_ibv_cq_create(struct rte_eth_dev *dev, uint16_t idx) 128 { 129 struct mlx5_priv *priv = dev->data->dev_private; 130 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx]; 131 struct mlx5_rxq_ctrl *rxq_ctrl = 132 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); 133 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj; 134 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data); 135 struct { 136 struct ibv_cq_init_attr_ex ibv; 137 struct mlx5dv_cq_init_attr mlx5; 138 } cq_attr; 139 140 cq_attr.ibv = (struct ibv_cq_init_attr_ex){ 141 .cqe = cqe_n, 142 .channel = rxq_obj->ibv_channel, 143 .comp_mask = 0, 144 }; 145 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){ 146 .comp_mask = 0, 147 }; 148 if (priv->config.cqe_comp && !rxq_data->hw_timestamp) { 149 cq_attr.mlx5.comp_mask |= 150 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE; 151 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 152 cq_attr.mlx5.cqe_comp_res_format = 153 mlx5_rxq_mprq_enabled(rxq_data) ? 154 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX : 155 MLX5DV_CQE_RES_FORMAT_HASH; 156 #else 157 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH; 158 #endif 159 /* 160 * For vectorized Rx, it must not be doubled in order to 161 * make cq_ci and rq_ci aligned. 162 */ 163 if (mlx5_rxq_check_vec_support(rxq_data) < 0) 164 cq_attr.ibv.cqe *= 2; 165 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) { 166 DRV_LOG(DEBUG, 167 "Port %u Rx CQE compression is disabled for HW" 168 " timestamp.", 169 dev->data->port_id); 170 } 171 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 172 if (priv->config.cqe_pad) { 173 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS; 174 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD; 175 } 176 #endif 177 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx, 178 &cq_attr.ibv, 179 &cq_attr.mlx5)); 180 } 181 182 /** 183 * Create a WQ Verbs object. 184 * 185 * @param dev 186 * Pointer to Ethernet device. 187 * @param idx 188 * Queue index in DPDK Rx queue array. 189 * 190 * @return 191 * The Verbs WQ object initialized, NULL otherwise and rte_errno is set. 192 */ 193 static struct ibv_wq * 194 mlx5_rxq_ibv_wq_create(struct rte_eth_dev *dev, uint16_t idx) 195 { 196 struct mlx5_priv *priv = dev->data->dev_private; 197 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx]; 198 struct mlx5_rxq_ctrl *rxq_ctrl = 199 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); 200 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj; 201 unsigned int wqe_n = 1 << rxq_data->elts_n; 202 struct { 203 struct ibv_wq_init_attr ibv; 204 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 205 struct mlx5dv_wq_init_attr mlx5; 206 #endif 207 } wq_attr; 208 209 wq_attr.ibv = (struct ibv_wq_init_attr){ 210 .wq_context = NULL, /* Could be useful in the future. */ 211 .wq_type = IBV_WQT_RQ, 212 /* Max number of outstanding WRs. */ 213 .max_wr = wqe_n >> rxq_data->sges_n, 214 /* Max number of scatter/gather elements in a WR. */ 215 .max_sge = 1 << rxq_data->sges_n, 216 .pd = priv->sh->pd, 217 .cq = rxq_obj->ibv_cq, 218 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0, 219 .create_flags = (rxq_data->vlan_strip ? 220 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0), 221 }; 222 /* By default, FCS (CRC) is stripped by hardware. */ 223 if (rxq_data->crc_present) { 224 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS; 225 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS; 226 } 227 if (priv->config.hw_padding) { 228 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 229 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING; 230 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS; 231 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 232 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING; 233 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS; 234 #endif 235 } 236 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 237 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){ 238 .comp_mask = 0, 239 }; 240 if (mlx5_rxq_mprq_enabled(rxq_data)) { 241 struct mlx5dv_striding_rq_init_attr *mprq_attr = 242 &wq_attr.mlx5.striding_rq_attrs; 243 244 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ; 245 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){ 246 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n, 247 .single_wqe_log_num_of_strides = rxq_data->strd_num_n, 248 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT, 249 }; 250 } 251 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv, 252 &wq_attr.mlx5); 253 #else 254 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv); 255 #endif 256 if (rxq_obj->wq) { 257 /* 258 * Make sure number of WRs*SGEs match expectations since a queue 259 * cannot allocate more than "desc" buffers. 260 */ 261 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) || 262 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) { 263 DRV_LOG(ERR, 264 "Port %u Rx queue %u requested %u*%u but got" 265 " %u*%u WRs*SGEs.", 266 dev->data->port_id, idx, 267 wqe_n >> rxq_data->sges_n, 268 (1 << rxq_data->sges_n), 269 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge); 270 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq)); 271 rxq_obj->wq = NULL; 272 rte_errno = EINVAL; 273 } 274 } 275 return rxq_obj->wq; 276 } 277 278 /** 279 * Create the Rx queue Verbs object. 280 * 281 * @param dev 282 * Pointer to Ethernet device. 283 * @param idx 284 * Queue index in DPDK Rx queue array. 285 * 286 * @return 287 * 0 on success, a negative errno value otherwise and rte_errno is set. 288 */ 289 static int 290 mlx5_rxq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx) 291 { 292 struct mlx5_priv *priv = dev->data->dev_private; 293 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx]; 294 struct mlx5_rxq_ctrl *rxq_ctrl = 295 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); 296 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj; 297 struct mlx5dv_cq cq_info; 298 struct mlx5dv_rwq rwq; 299 int ret = 0; 300 struct mlx5dv_obj obj; 301 302 MLX5_ASSERT(rxq_data); 303 MLX5_ASSERT(tmpl); 304 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE; 305 priv->verbs_alloc_ctx.obj = rxq_ctrl; 306 tmpl->type = MLX5_RXQ_OBJ_TYPE_IBV; 307 tmpl->rxq_ctrl = rxq_ctrl; 308 if (rxq_ctrl->irq) { 309 tmpl->ibv_channel = 310 mlx5_glue->create_comp_channel(priv->sh->ctx); 311 if (!tmpl->ibv_channel) { 312 DRV_LOG(ERR, "Port %u: comp channel creation failure.", 313 dev->data->port_id); 314 rte_errno = ENOMEM; 315 goto error; 316 } 317 tmpl->fd = ((struct ibv_comp_channel *)(tmpl->ibv_channel))->fd; 318 } 319 /* Create CQ using Verbs API. */ 320 tmpl->ibv_cq = mlx5_rxq_ibv_cq_create(dev, idx); 321 if (!tmpl->ibv_cq) { 322 DRV_LOG(ERR, "Port %u Rx queue %u CQ creation failure.", 323 dev->data->port_id, idx); 324 rte_errno = ENOMEM; 325 goto error; 326 } 327 obj.cq.in = tmpl->ibv_cq; 328 obj.cq.out = &cq_info; 329 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ); 330 if (ret) { 331 rte_errno = ret; 332 goto error; 333 } 334 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) { 335 DRV_LOG(ERR, 336 "Port %u wrong MLX5_CQE_SIZE environment " 337 "variable value: it should be set to %u.", 338 dev->data->port_id, RTE_CACHE_LINE_SIZE); 339 rte_errno = EINVAL; 340 goto error; 341 } 342 /* Fill the rings. */ 343 rxq_data->cqe_n = log2above(cq_info.cqe_cnt); 344 rxq_data->cq_db = cq_info.dbrec; 345 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf; 346 rxq_data->cq_uar = cq_info.cq_uar; 347 rxq_data->cqn = cq_info.cqn; 348 /* Create WQ (RQ) using Verbs API. */ 349 tmpl->wq = mlx5_rxq_ibv_wq_create(dev, idx); 350 if (!tmpl->wq) { 351 DRV_LOG(ERR, "Port %u Rx queue %u WQ creation failure.", 352 dev->data->port_id, idx); 353 rte_errno = ENOMEM; 354 goto error; 355 } 356 /* Change queue state to ready. */ 357 ret = mlx5_ibv_modify_wq(tmpl, true); 358 if (ret) { 359 DRV_LOG(ERR, 360 "Port %u Rx queue %u WQ state to IBV_WQS_RDY failed.", 361 dev->data->port_id, idx); 362 rte_errno = ret; 363 goto error; 364 } 365 obj.rwq.in = tmpl->wq; 366 obj.rwq.out = &rwq; 367 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ); 368 if (ret) { 369 rte_errno = ret; 370 goto error; 371 } 372 rxq_data->wqes = rwq.buf; 373 rxq_data->rq_db = rwq.dbrec; 374 rxq_data->cq_arm_sn = 0; 375 mlx5_rxq_initialize(rxq_data); 376 rxq_data->cq_ci = 0; 377 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; 378 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED; 379 rxq_ctrl->wqn = ((struct ibv_wq *)(tmpl->wq))->wq_num; 380 return 0; 381 error: 382 ret = rte_errno; /* Save rte_errno before cleanup. */ 383 if (tmpl->wq) 384 claim_zero(mlx5_glue->destroy_wq(tmpl->wq)); 385 if (tmpl->ibv_cq) 386 claim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq)); 387 if (tmpl->ibv_channel) 388 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->ibv_channel)); 389 rte_errno = ret; /* Restore rte_errno. */ 390 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; 391 return -rte_errno; 392 } 393 394 /** 395 * Release an Rx verbs queue object. 396 * 397 * @param rxq_obj 398 * Verbs Rx queue object. 399 */ 400 static void 401 mlx5_rxq_ibv_obj_release(struct mlx5_rxq_obj *rxq_obj) 402 { 403 MLX5_ASSERT(rxq_obj); 404 MLX5_ASSERT(rxq_obj->wq); 405 MLX5_ASSERT(rxq_obj->ibv_cq); 406 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq)); 407 claim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq)); 408 if (rxq_obj->ibv_channel) 409 claim_zero(mlx5_glue->destroy_comp_channel 410 (rxq_obj->ibv_channel)); 411 } 412 413 /** 414 * Get event for an Rx verbs queue object. 415 * 416 * @param rxq_obj 417 * Verbs Rx queue object. 418 * 419 * @return 420 * 0 on success, a negative errno value otherwise and rte_errno is set. 421 */ 422 static int 423 mlx5_rx_ibv_get_event(struct mlx5_rxq_obj *rxq_obj) 424 { 425 struct ibv_cq *ev_cq; 426 void *ev_ctx; 427 int ret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel, 428 &ev_cq, &ev_ctx); 429 430 if (ret < 0 || ev_cq != rxq_obj->ibv_cq) 431 goto exit; 432 mlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1); 433 return 0; 434 exit: 435 if (ret < 0) 436 rte_errno = errno; 437 else 438 rte_errno = EINVAL; 439 return -rte_errno; 440 } 441 442 /** 443 * Creates a receive work queue as a filed of indirection table. 444 * 445 * @param dev 446 * Pointer to Ethernet device. 447 * @param log_n 448 * Log of number of queues in the array. 449 * @param ind_tbl 450 * Verbs indirection table object. 451 * 452 * @return 453 * 0 on success, a negative errno value otherwise and rte_errno is set. 454 */ 455 static int 456 mlx5_ibv_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n, 457 struct mlx5_ind_table_obj *ind_tbl) 458 { 459 struct mlx5_priv *priv = dev->data->dev_private; 460 struct ibv_wq *wq[1 << log_n]; 461 unsigned int i, j; 462 463 MLX5_ASSERT(ind_tbl); 464 for (i = 0; i != ind_tbl->queues_n; ++i) { 465 struct mlx5_rxq_data *rxq = (*priv->rxqs)[ind_tbl->queues[i]]; 466 struct mlx5_rxq_ctrl *rxq_ctrl = 467 container_of(rxq, struct mlx5_rxq_ctrl, rxq); 468 469 wq[i] = rxq_ctrl->obj->wq; 470 } 471 MLX5_ASSERT(i > 0); 472 /* Finalise indirection table. */ 473 for (j = 0; i != (unsigned int)(1 << log_n); ++j, ++i) 474 wq[i] = wq[j]; 475 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table(priv->sh->ctx, 476 &(struct ibv_rwq_ind_table_init_attr){ 477 .log_ind_tbl_size = log_n, 478 .ind_tbl = wq, 479 .comp_mask = 0, 480 }); 481 if (!ind_tbl->ind_table) { 482 rte_errno = errno; 483 return -rte_errno; 484 } 485 return 0; 486 } 487 488 /** 489 * Destroys the specified Indirection Table. 490 * 491 * @param ind_table 492 * Indirection table to release. 493 */ 494 static void 495 mlx5_ibv_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl) 496 { 497 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table)); 498 } 499 500 /** 501 * Create an Rx Hash queue. 502 * 503 * @param dev 504 * Pointer to Ethernet device. 505 * @param hrxq 506 * Pointer to Rx Hash queue. 507 * @param tunnel 508 * Tunnel type. 509 * 510 * @return 511 * 0 on success, a negative errno value otherwise and rte_errno is set. 512 */ 513 static int 514 mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 515 int tunnel __rte_unused) 516 { 517 struct mlx5_priv *priv = dev->data->dev_private; 518 struct ibv_qp *qp = NULL; 519 struct mlx5_ind_table_obj *ind_tbl = hrxq->ind_table; 520 const uint8_t *rss_key = hrxq->rss_key; 521 uint64_t hash_fields = hrxq->hash_fields; 522 int err; 523 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 524 struct mlx5dv_qp_init_attr qp_init_attr; 525 526 memset(&qp_init_attr, 0, sizeof(qp_init_attr)); 527 if (tunnel) { 528 qp_init_attr.comp_mask = 529 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS; 530 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS; 531 } 532 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 533 if (dev->data->dev_conf.lpbk_mode) { 534 /* Allow packet sent from NIC loop back w/o source MAC check. */ 535 qp_init_attr.comp_mask |= 536 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS; 537 qp_init_attr.create_flags |= 538 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC; 539 } 540 #endif 541 qp = mlx5_glue->dv_create_qp 542 (priv->sh->ctx, 543 &(struct ibv_qp_init_attr_ex){ 544 .qp_type = IBV_QPT_RAW_PACKET, 545 .comp_mask = 546 IBV_QP_INIT_ATTR_PD | 547 IBV_QP_INIT_ATTR_IND_TABLE | 548 IBV_QP_INIT_ATTR_RX_HASH, 549 .rx_hash_conf = (struct ibv_rx_hash_conf){ 550 .rx_hash_function = 551 IBV_RX_HASH_FUNC_TOEPLITZ, 552 .rx_hash_key_len = hrxq->rss_key_len, 553 .rx_hash_key = 554 (void *)(uintptr_t)rss_key, 555 .rx_hash_fields_mask = hash_fields, 556 }, 557 .rwq_ind_tbl = ind_tbl->ind_table, 558 .pd = priv->sh->pd, 559 }, 560 &qp_init_attr); 561 #else 562 qp = mlx5_glue->create_qp_ex 563 (priv->sh->ctx, 564 &(struct ibv_qp_init_attr_ex){ 565 .qp_type = IBV_QPT_RAW_PACKET, 566 .comp_mask = 567 IBV_QP_INIT_ATTR_PD | 568 IBV_QP_INIT_ATTR_IND_TABLE | 569 IBV_QP_INIT_ATTR_RX_HASH, 570 .rx_hash_conf = (struct ibv_rx_hash_conf){ 571 .rx_hash_function = 572 IBV_RX_HASH_FUNC_TOEPLITZ, 573 .rx_hash_key_len = hrxq->rss_key_len, 574 .rx_hash_key = 575 (void *)(uintptr_t)rss_key, 576 .rx_hash_fields_mask = hash_fields, 577 }, 578 .rwq_ind_tbl = ind_tbl->ind_table, 579 .pd = priv->sh->pd, 580 }); 581 #endif 582 if (!qp) { 583 rte_errno = errno; 584 goto error; 585 } 586 hrxq->qp = qp; 587 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 588 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp); 589 if (!hrxq->action) { 590 rte_errno = errno; 591 goto error; 592 } 593 #endif 594 return 0; 595 error: 596 err = rte_errno; /* Save rte_errno before cleanup. */ 597 if (qp) 598 claim_zero(mlx5_glue->destroy_qp(qp)); 599 rte_errno = err; /* Restore rte_errno. */ 600 return -rte_errno; 601 } 602 603 /** 604 * Destroy a Verbs queue pair. 605 * 606 * @param hrxq 607 * Hash Rx queue to release its qp. 608 */ 609 static void 610 mlx5_ibv_qp_destroy(struct mlx5_hrxq *hrxq) 611 { 612 claim_zero(mlx5_glue->destroy_qp(hrxq->qp)); 613 } 614 615 /** 616 * Release a drop Rx queue Verbs object. 617 * 618 * @param dev 619 * Pointer to Ethernet device. 620 */ 621 static void 622 mlx5_rxq_ibv_obj_drop_release(struct rte_eth_dev *dev) 623 { 624 struct mlx5_priv *priv = dev->data->dev_private; 625 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq; 626 627 if (rxq->wq) 628 claim_zero(mlx5_glue->destroy_wq(rxq->wq)); 629 if (rxq->ibv_cq) 630 claim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq)); 631 mlx5_free(rxq); 632 priv->drop_queue.rxq = NULL; 633 } 634 635 /** 636 * Create a drop Rx queue Verbs object. 637 * 638 * @param dev 639 * Pointer to Ethernet device. 640 * 641 * @return 642 * 0 on success, a negative errno value otherwise and rte_errno is set. 643 */ 644 static int 645 mlx5_rxq_ibv_obj_drop_create(struct rte_eth_dev *dev) 646 { 647 struct mlx5_priv *priv = dev->data->dev_private; 648 struct ibv_context *ctx = priv->sh->ctx; 649 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq; 650 651 if (rxq) 652 return 0; 653 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY); 654 if (!rxq) { 655 DEBUG("Port %u cannot allocate drop Rx queue memory.", 656 dev->data->port_id); 657 rte_errno = ENOMEM; 658 return -rte_errno; 659 } 660 priv->drop_queue.rxq = rxq; 661 rxq->ibv_cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 662 if (!rxq->ibv_cq) { 663 DEBUG("Port %u cannot allocate CQ for drop queue.", 664 dev->data->port_id); 665 rte_errno = errno; 666 goto error; 667 } 668 rxq->wq = mlx5_glue->create_wq(ctx, &(struct ibv_wq_init_attr){ 669 .wq_type = IBV_WQT_RQ, 670 .max_wr = 1, 671 .max_sge = 1, 672 .pd = priv->sh->pd, 673 .cq = rxq->ibv_cq, 674 }); 675 if (!rxq->wq) { 676 DEBUG("Port %u cannot allocate WQ for drop queue.", 677 dev->data->port_id); 678 rte_errno = errno; 679 goto error; 680 } 681 priv->drop_queue.rxq = rxq; 682 return 0; 683 error: 684 mlx5_rxq_ibv_obj_drop_release(dev); 685 return -rte_errno; 686 } 687 688 /** 689 * Create a Verbs drop action for Rx Hash queue. 690 * 691 * @param dev 692 * Pointer to Ethernet device. 693 * 694 * @return 695 * 0 on success, a negative errno value otherwise and rte_errno is set. 696 */ 697 static int 698 mlx5_ibv_drop_action_create(struct rte_eth_dev *dev) 699 { 700 struct mlx5_priv *priv = dev->data->dev_private; 701 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq; 702 struct ibv_rwq_ind_table *ind_tbl = NULL; 703 struct mlx5_rxq_obj *rxq; 704 int ret; 705 706 MLX5_ASSERT(hrxq && hrxq->ind_table); 707 ret = mlx5_rxq_ibv_obj_drop_create(dev); 708 if (ret < 0) 709 goto error; 710 rxq = priv->drop_queue.rxq; 711 ind_tbl = mlx5_glue->create_rwq_ind_table 712 (priv->sh->ctx, 713 &(struct ibv_rwq_ind_table_init_attr){ 714 .log_ind_tbl_size = 0, 715 .ind_tbl = (struct ibv_wq **)&rxq->wq, 716 .comp_mask = 0, 717 }); 718 if (!ind_tbl) { 719 DEBUG("Port %u cannot allocate indirection table for drop" 720 " queue.", dev->data->port_id); 721 rte_errno = errno; 722 goto error; 723 } 724 hrxq->qp = mlx5_glue->create_qp_ex(priv->sh->ctx, 725 &(struct ibv_qp_init_attr_ex){ 726 .qp_type = IBV_QPT_RAW_PACKET, 727 .comp_mask = IBV_QP_INIT_ATTR_PD | 728 IBV_QP_INIT_ATTR_IND_TABLE | 729 IBV_QP_INIT_ATTR_RX_HASH, 730 .rx_hash_conf = (struct ibv_rx_hash_conf){ 731 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ, 732 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN, 733 .rx_hash_key = rss_hash_default_key, 734 .rx_hash_fields_mask = 0, 735 }, 736 .rwq_ind_tbl = ind_tbl, 737 .pd = priv->sh->pd 738 }); 739 if (!hrxq->qp) { 740 DEBUG("Port %u cannot allocate QP for drop queue.", 741 dev->data->port_id); 742 rte_errno = errno; 743 goto error; 744 } 745 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 746 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp); 747 if (!hrxq->action) { 748 rte_errno = errno; 749 goto error; 750 } 751 #endif 752 hrxq->ind_table->ind_table = ind_tbl; 753 return 0; 754 error: 755 if (hrxq->qp) 756 claim_zero(mlx5_glue->destroy_qp(hrxq->qp)); 757 if (ind_tbl) 758 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl)); 759 if (priv->drop_queue.rxq) 760 mlx5_rxq_ibv_obj_drop_release(dev); 761 return -rte_errno; 762 } 763 764 /** 765 * Release a drop hash Rx queue. 766 * 767 * @param dev 768 * Pointer to Ethernet device. 769 */ 770 static void 771 mlx5_ibv_drop_action_destroy(struct rte_eth_dev *dev) 772 { 773 struct mlx5_priv *priv = dev->data->dev_private; 774 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq; 775 struct ibv_rwq_ind_table *ind_tbl = hrxq->ind_table->ind_table; 776 777 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 778 claim_zero(mlx5_glue->destroy_flow_action(hrxq->action)); 779 #endif 780 claim_zero(mlx5_glue->destroy_qp(hrxq->qp)); 781 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl)); 782 mlx5_rxq_ibv_obj_drop_release(dev); 783 } 784 785 /** 786 * Create a QP Verbs object. 787 * 788 * @param dev 789 * Pointer to Ethernet device. 790 * @param idx 791 * Queue index in DPDK Tx queue array. 792 * @param rxq_obj 793 * Pointer to Tx queue object data. 794 * 795 * @return 796 * The QP Verbs object initialized, NULL otherwise and rte_errno is set. 797 */ 798 static struct ibv_qp * 799 mlx5_ibv_qp_new(struct rte_eth_dev *dev, uint16_t idx, 800 struct mlx5_txq_obj *txq_obj) 801 { 802 struct mlx5_priv *priv = dev->data->dev_private; 803 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 804 struct mlx5_txq_ctrl *txq_ctrl = 805 container_of(txq_data, struct mlx5_txq_ctrl, txq); 806 struct ibv_qp *qp_obj = NULL; 807 struct ibv_qp_init_attr_ex qp_attr = { 0 }; 808 const int desc = 1 << txq_data->elts_n; 809 810 MLX5_ASSERT(txq_ctrl->obj); 811 /* CQ to be associated with the send queue. */ 812 qp_attr.send_cq = txq_obj->cq; 813 /* CQ to be associated with the receive queue. */ 814 qp_attr.recv_cq = txq_obj->cq; 815 /* Max number of outstanding WRs. */ 816 qp_attr.cap.max_send_wr = ((priv->sh->device_attr.max_qp_wr < desc) ? 817 priv->sh->device_attr.max_qp_wr : desc); 818 /* 819 * Max number of scatter/gather elements in a WR, must be 1 to prevent 820 * libmlx5 from trying to affect must be 1 to prevent libmlx5 from 821 * trying to affect too much memory. TX gather is not impacted by the 822 * device_attr.max_sge limit and will still work properly. 823 */ 824 qp_attr.cap.max_send_sge = 1; 825 qp_attr.qp_type = IBV_QPT_RAW_PACKET, 826 /* Do *NOT* enable this, completions events are managed per Tx burst. */ 827 qp_attr.sq_sig_all = 0; 828 qp_attr.pd = priv->sh->pd; 829 qp_attr.comp_mask = IBV_QP_INIT_ATTR_PD; 830 if (txq_data->inlen_send) 831 qp_attr.cap.max_inline_data = txq_ctrl->max_inline_data; 832 if (txq_data->tso_en) { 833 qp_attr.max_tso_header = txq_ctrl->max_tso_header; 834 qp_attr.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER; 835 } 836 qp_obj = mlx5_glue->create_qp_ex(priv->sh->ctx, &qp_attr); 837 if (qp_obj == NULL) { 838 DRV_LOG(ERR, "Port %u Tx queue %u QP creation failure.", 839 dev->data->port_id, idx); 840 rte_errno = errno; 841 } 842 return qp_obj; 843 } 844 845 /** 846 * Create the Tx queue Verbs object. 847 * 848 * @param dev 849 * Pointer to Ethernet device. 850 * @param idx 851 * Queue index in DPDK Tx queue array. 852 * 853 * @return 854 * 0 on success, a negative errno value otherwise and rte_errno is set. 855 */ 856 int 857 mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx) 858 { 859 struct mlx5_priv *priv = dev->data->dev_private; 860 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 861 struct mlx5_txq_ctrl *txq_ctrl = 862 container_of(txq_data, struct mlx5_txq_ctrl, txq); 863 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj; 864 struct ibv_qp_attr mod; 865 unsigned int cqe_n; 866 struct mlx5dv_qp qp; 867 struct mlx5dv_cq cq_info; 868 struct mlx5dv_obj obj; 869 const int desc = 1 << txq_data->elts_n; 870 int ret = 0; 871 872 MLX5_ASSERT(txq_data); 873 MLX5_ASSERT(txq_obj); 874 txq_obj->type = MLX5_TXQ_OBJ_TYPE_IBV; 875 txq_obj->txq_ctrl = txq_ctrl; 876 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE; 877 priv->verbs_alloc_ctx.obj = txq_ctrl; 878 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) { 879 DRV_LOG(ERR, "Port %u MLX5_ENABLE_CQE_COMPRESSION " 880 "must never be set.", dev->data->port_id); 881 rte_errno = EINVAL; 882 return -rte_errno; 883 } 884 cqe_n = desc / MLX5_TX_COMP_THRESH + 885 1 + MLX5_TX_COMP_THRESH_INLINE_DIV; 886 txq_obj->cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0); 887 if (txq_obj->cq == NULL) { 888 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.", 889 dev->data->port_id, idx); 890 rte_errno = errno; 891 goto error; 892 } 893 txq_obj->qp = mlx5_ibv_qp_new(dev, idx, txq_obj); 894 if (txq_obj->qp == NULL) { 895 rte_errno = errno; 896 goto error; 897 } 898 mod = (struct ibv_qp_attr){ 899 /* Move the QP to this state. */ 900 .qp_state = IBV_QPS_INIT, 901 /* IB device port number. */ 902 .port_num = (uint8_t)priv->dev_port, 903 }; 904 ret = mlx5_glue->modify_qp(txq_obj->qp, &mod, 905 (IBV_QP_STATE | IBV_QP_PORT)); 906 if (ret) { 907 DRV_LOG(ERR, 908 "Port %u Tx queue %u QP state to IBV_QPS_INIT failed.", 909 dev->data->port_id, idx); 910 rte_errno = errno; 911 goto error; 912 } 913 mod = (struct ibv_qp_attr){ 914 .qp_state = IBV_QPS_RTR 915 }; 916 ret = mlx5_glue->modify_qp(txq_obj->qp, &mod, IBV_QP_STATE); 917 if (ret) { 918 DRV_LOG(ERR, 919 "Port %u Tx queue %u QP state to IBV_QPS_RTR failed.", 920 dev->data->port_id, idx); 921 rte_errno = errno; 922 goto error; 923 } 924 mod.qp_state = IBV_QPS_RTS; 925 ret = mlx5_glue->modify_qp(txq_obj->qp, &mod, IBV_QP_STATE); 926 if (ret) { 927 DRV_LOG(ERR, 928 "Port %u Tx queue %u QP state to IBV_QPS_RTS failed.", 929 dev->data->port_id, idx); 930 rte_errno = errno; 931 goto error; 932 } 933 qp.comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET; 934 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 935 /* If using DevX, need additional mask to read tisn value. */ 936 if (priv->sh->devx && !priv->sh->tdn) 937 qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES; 938 #endif 939 obj.cq.in = txq_obj->cq; 940 obj.cq.out = &cq_info; 941 obj.qp.in = txq_obj->qp; 942 obj.qp.out = &qp; 943 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP); 944 if (ret != 0) { 945 rte_errno = errno; 946 goto error; 947 } 948 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) { 949 DRV_LOG(ERR, 950 "Port %u wrong MLX5_CQE_SIZE environment variable" 951 " value: it should be set to %u.", 952 dev->data->port_id, RTE_CACHE_LINE_SIZE); 953 rte_errno = EINVAL; 954 goto error; 955 } 956 txq_data->cqe_n = log2above(cq_info.cqe_cnt); 957 txq_data->cqe_s = 1 << txq_data->cqe_n; 958 txq_data->cqe_m = txq_data->cqe_s - 1; 959 txq_data->qp_num_8s = ((struct ibv_qp *)txq_obj->qp)->qp_num << 8; 960 txq_data->wqes = qp.sq.buf; 961 txq_data->wqe_n = log2above(qp.sq.wqe_cnt); 962 txq_data->wqe_s = 1 << txq_data->wqe_n; 963 txq_data->wqe_m = txq_data->wqe_s - 1; 964 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s; 965 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR]; 966 txq_data->cq_db = cq_info.dbrec; 967 txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf; 968 txq_data->cq_ci = 0; 969 txq_data->cq_pi = 0; 970 txq_data->wqe_ci = 0; 971 txq_data->wqe_pi = 0; 972 txq_data->wqe_comp = 0; 973 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV; 974 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 975 /* 976 * If using DevX need to query and store TIS transport domain value. 977 * This is done once per port. 978 * Will use this value on Rx, when creating matching TIR. 979 */ 980 if (priv->sh->devx && !priv->sh->tdn) { 981 ret = mlx5_devx_cmd_qp_query_tis_td(txq_obj->qp, qp.tisn, 982 &priv->sh->tdn); 983 if (ret) { 984 DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS " 985 "transport domain.", dev->data->port_id, idx); 986 rte_errno = EINVAL; 987 goto error; 988 } else { 989 DRV_LOG(DEBUG, "Port %u Tx queue %u TIS number %d " 990 "transport domain %d.", dev->data->port_id, 991 idx, qp.tisn, priv->sh->tdn); 992 } 993 } 994 #endif 995 txq_ctrl->bf_reg = qp.bf.reg; 996 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) { 997 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset; 998 DRV_LOG(DEBUG, "Port %u: uar_mmap_offset 0x%" PRIx64 ".", 999 dev->data->port_id, txq_ctrl->uar_mmap_offset); 1000 } else { 1001 DRV_LOG(ERR, 1002 "Port %u failed to retrieve UAR info, invalid" 1003 " libmlx5.so", 1004 dev->data->port_id); 1005 rte_errno = EINVAL; 1006 goto error; 1007 } 1008 txq_uar_init(txq_ctrl); 1009 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; 1010 return 0; 1011 error: 1012 ret = rte_errno; /* Save rte_errno before cleanup. */ 1013 if (txq_obj->cq) 1014 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq)); 1015 if (txq_obj->qp) 1016 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp)); 1017 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; 1018 rte_errno = ret; /* Restore rte_errno. */ 1019 return -rte_errno; 1020 } 1021 1022 /** 1023 * Release an Tx verbs queue object. 1024 * 1025 * @param txq_obj 1026 * Verbs Tx queue object.. 1027 */ 1028 void 1029 mlx5_txq_ibv_obj_release(struct mlx5_txq_obj *txq_obj) 1030 { 1031 MLX5_ASSERT(txq_obj); 1032 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp)); 1033 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq)); 1034 } 1035 1036 struct mlx5_obj_ops ibv_obj_ops = { 1037 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_wq_vlan_strip, 1038 .rxq_obj_new = mlx5_rxq_ibv_obj_new, 1039 .rxq_event_get = mlx5_rx_ibv_get_event, 1040 .rxq_obj_modify = mlx5_ibv_modify_wq, 1041 .rxq_obj_release = mlx5_rxq_ibv_obj_release, 1042 .ind_table_new = mlx5_ibv_ind_table_new, 1043 .ind_table_destroy = mlx5_ibv_ind_table_destroy, 1044 .hrxq_new = mlx5_ibv_hrxq_new, 1045 .hrxq_destroy = mlx5_ibv_qp_destroy, 1046 .drop_action_create = mlx5_ibv_drop_action_create, 1047 .drop_action_destroy = mlx5_ibv_drop_action_destroy, 1048 .txq_obj_new = mlx5_txq_ibv_obj_new, 1049 .txq_obj_release = mlx5_txq_ibv_obj_release, 1050 }; 1051