110f3581dSOphir Munk /* SPDX-License-Identifier: BSD-3-Clause 210f3581dSOphir Munk * Copyright 2015 6WIND S.A. 310f3581dSOphir Munk * Copyright 2020 Mellanox Technologies, Ltd 410f3581dSOphir Munk */ 510f3581dSOphir Munk 610f3581dSOphir Munk #ifndef RTE_PMD_MLX5_OS_H_ 710f3581dSOphir Munk #define RTE_PMD_MLX5_OS_H_ 810f3581dSOphir Munk 9e9c0b96eSOphir Munk #include <net/if.h> 10e9c0b96eSOphir Munk 1110f3581dSOphir Munk /* verb enumerations translations to local enums. */ 1210f3581dSOphir Munk enum { 13d0b3ef1aSTal Shnaiderman MLX5_FS_NAME_MAX = IBV_SYSFS_NAME_MAX + 1, 14d0b3ef1aSTal Shnaiderman MLX5_FS_PATH_MAX = IBV_SYSFS_PATH_MAX + 1 1510f3581dSOphir Munk }; 1610f3581dSOphir Munk 17bd0a9315SHaifei Luo /* Maximal data of sendmsg message(in bytes). */ 18bd0a9315SHaifei Luo #define MLX5_SENDMSG_MAX 64 19bd0a9315SHaifei Luo 2028743807STal Shnaiderman #define MLX5_NAMESIZE IF_NAMESIZE 2128743807STal Shnaiderman 22919488fbSXueming Li int mlx5_auxiliary_get_ifindex(const char *sf_name); 23919488fbSXueming Li 24accf3cfcSTal Shnaiderman 25accf3cfcSTal Shnaiderman enum mlx5_sw_parsing_offloads { 26accf3cfcSTal Shnaiderman #ifdef HAVE_IBV_MLX5_MOD_SWP 27accf3cfcSTal Shnaiderman MLX5_SW_PARSING_CAP = MLX5DV_SW_PARSING, 28accf3cfcSTal Shnaiderman MLX5_SW_PARSING_CSUM_CAP = MLX5DV_SW_PARSING_CSUM, 29accf3cfcSTal Shnaiderman MLX5_SW_PARSING_TSO_CAP = MLX5DV_SW_PARSING_LSO, 30accf3cfcSTal Shnaiderman #else 31accf3cfcSTal Shnaiderman MLX5_SW_PARSING_CAP = 0, 32accf3cfcSTal Shnaiderman MLX5_SW_PARSING_CSUM_CAP = 0, 33accf3cfcSTal Shnaiderman MLX5_SW_PARSING_TSO_CAP = 0, 34accf3cfcSTal Shnaiderman #endif 35accf3cfcSTal Shnaiderman }; 36*c1a320bfSTal Shnaiderman 37*c1a320bfSTal Shnaiderman enum mlx5_tunnel_offloads { 38*c1a320bfSTal Shnaiderman #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 39*c1a320bfSTal Shnaiderman MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 40*c1a320bfSTal Shnaiderman MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN, 41*c1a320bfSTal Shnaiderman MLX5_TUNNELED_OFFLOADS_GRE_CAP = 42*c1a320bfSTal Shnaiderman MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE, 43*c1a320bfSTal Shnaiderman MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 44*c1a320bfSTal Shnaiderman MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE, 45*c1a320bfSTal Shnaiderman #else 46*c1a320bfSTal Shnaiderman MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 0, 47*c1a320bfSTal Shnaiderman MLX5_TUNNELED_OFFLOADS_GRE_CAP = 0, 48*c1a320bfSTal Shnaiderman MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 0, 49*c1a320bfSTal Shnaiderman #endif 50*c1a320bfSTal Shnaiderman }; 5110f3581dSOphir Munk #endif /* RTE_PMD_MLX5_OS_H_ */ 52