1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_qp = attr_ex.orig_attr.max_qp; 120 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 121 device_attr->max_rwq_indirection_table_size = 122 attr_ex.rss_caps.max_rwq_indirection_table_size; 123 device_attr->max_tso = attr_ex.tso_caps.max_tso; 124 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 125 126 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 127 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 128 if (err) 129 return err; 130 131 device_attr->flags = dv_attr.flags; 132 device_attr->comp_mask = dv_attr.comp_mask; 133 #ifdef HAVE_IBV_MLX5_MOD_SWP 134 device_attr->sw_parsing_offloads = 135 dv_attr.sw_parsing_caps.sw_parsing_offloads; 136 #endif 137 device_attr->min_single_stride_log_num_of_bytes = 138 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 139 device_attr->max_single_stride_log_num_of_bytes = 140 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 141 device_attr->min_single_wqe_log_num_of_strides = 142 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 143 device_attr->max_single_wqe_log_num_of_strides = 144 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 145 device_attr->stride_supported_qpts = 146 dv_attr.striding_rq_caps.supported_qpts; 147 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 148 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 149 #endif 150 151 return err; 152 } 153 154 /** 155 * Verbs callback to allocate a memory. This function should allocate the space 156 * according to the size provided residing inside a huge page. 157 * Please note that all allocation must respect the alignment from libmlx5 158 * (i.e. currently rte_mem_page_size()). 159 * 160 * @param[in] size 161 * The size in bytes of the memory to allocate. 162 * @param[in] data 163 * A pointer to the callback data. 164 * 165 * @return 166 * Allocated buffer, NULL otherwise and rte_errno is set. 167 */ 168 static void * 169 mlx5_alloc_verbs_buf(size_t size, void *data) 170 { 171 struct mlx5_priv *priv = data; 172 void *ret; 173 unsigned int socket = SOCKET_ID_ANY; 174 size_t alignment = rte_mem_page_size(); 175 if (alignment == (size_t)-1) { 176 DRV_LOG(ERR, "Failed to get mem page size"); 177 rte_errno = ENOMEM; 178 return NULL; 179 } 180 181 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 182 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 183 184 socket = ctrl->socket; 185 } else if (priv->verbs_alloc_ctx.type == 186 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 187 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 188 189 socket = ctrl->socket; 190 } 191 MLX5_ASSERT(data != NULL); 192 ret = mlx5_malloc(0, size, alignment, socket); 193 if (!ret && size) 194 rte_errno = ENOMEM; 195 return ret; 196 } 197 198 /** 199 * Verbs callback to free a memory. 200 * 201 * @param[in] ptr 202 * A pointer to the memory to free. 203 * @param[in] data 204 * A pointer to the callback data. 205 */ 206 static void 207 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 208 { 209 MLX5_ASSERT(data != NULL); 210 mlx5_free(ptr); 211 } 212 213 /** 214 * Initialize DR related data within private structure. 215 * Routine checks the reference counter and does actual 216 * resources creation/initialization only if counter is zero. 217 * 218 * @param[in] priv 219 * Pointer to the private device data structure. 220 * 221 * @return 222 * Zero on success, positive error code otherwise. 223 */ 224 static int 225 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 226 { 227 struct mlx5_dev_ctx_shared *sh = priv->sh; 228 char s[MLX5_HLIST_NAMESIZE] __rte_unused; 229 int err; 230 231 MLX5_ASSERT(sh && sh->refcnt); 232 if (sh->refcnt > 1) 233 return 0; 234 err = mlx5_alloc_table_hash_list(priv); 235 if (err) 236 goto error; 237 /* The resources below are only valid with DV support. */ 238 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 239 /* Init port id action cache list. */ 240 snprintf(s, sizeof(s), "%s_port_id_action_cache", sh->ibdev_name); 241 mlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh, 242 flow_dv_port_id_create_cb, 243 flow_dv_port_id_match_cb, 244 flow_dv_port_id_remove_cb); 245 /* Init push vlan action cache list. */ 246 snprintf(s, sizeof(s), "%s_push_vlan_action_cache", sh->ibdev_name); 247 mlx5_cache_list_init(&sh->push_vlan_action_list, s, 0, sh, 248 flow_dv_push_vlan_create_cb, 249 flow_dv_push_vlan_match_cb, 250 flow_dv_push_vlan_remove_cb); 251 /* Init sample action cache list. */ 252 snprintf(s, sizeof(s), "%s_sample_action_cache", sh->ibdev_name); 253 mlx5_cache_list_init(&sh->sample_action_list, s, 0, 254 &rte_eth_devices[priv->dev_data->port_id], 255 flow_dv_sample_create_cb, 256 flow_dv_sample_match_cb, 257 flow_dv_sample_remove_cb); 258 /* Init dest array action cache list. */ 259 snprintf(s, sizeof(s), "%s_dest_array_cache", sh->ibdev_name); 260 mlx5_cache_list_init(&sh->dest_array_list, s, 0, 261 &rte_eth_devices[priv->dev_data->port_id], 262 flow_dv_dest_array_create_cb, 263 flow_dv_dest_array_match_cb, 264 flow_dv_dest_array_remove_cb); 265 /* Create tags hash list table. */ 266 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 267 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0, 268 MLX5_HLIST_WRITE_MOST, 269 flow_dv_tag_create_cb, NULL, 270 flow_dv_tag_remove_cb); 271 if (!sh->tag_table) { 272 DRV_LOG(ERR, "tags with hash creation failed."); 273 err = ENOMEM; 274 goto error; 275 } 276 sh->tag_table->ctx = sh; 277 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 278 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ, 279 0, MLX5_HLIST_WRITE_MOST | 280 MLX5_HLIST_DIRECT_KEY, 281 flow_dv_modify_create_cb, 282 flow_dv_modify_match_cb, 283 flow_dv_modify_remove_cb); 284 if (!sh->modify_cmds) { 285 DRV_LOG(ERR, "hdr modify hash creation failed"); 286 err = ENOMEM; 287 goto error; 288 } 289 sh->modify_cmds->ctx = sh; 290 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 291 sh->encaps_decaps = mlx5_hlist_create(s, 292 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ, 293 0, MLX5_HLIST_DIRECT_KEY | 294 MLX5_HLIST_WRITE_MOST, 295 flow_dv_encap_decap_create_cb, 296 flow_dv_encap_decap_match_cb, 297 flow_dv_encap_decap_remove_cb); 298 if (!sh->encaps_decaps) { 299 DRV_LOG(ERR, "encap decap hash creation failed"); 300 err = ENOMEM; 301 goto error; 302 } 303 sh->encaps_decaps->ctx = sh; 304 #endif 305 #ifdef HAVE_MLX5DV_DR 306 void *domain; 307 308 /* Reference counter is zero, we should initialize structures. */ 309 domain = mlx5_glue->dr_create_domain(sh->ctx, 310 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 311 if (!domain) { 312 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 313 err = errno; 314 goto error; 315 } 316 sh->rx_domain = domain; 317 domain = mlx5_glue->dr_create_domain(sh->ctx, 318 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 319 if (!domain) { 320 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 321 err = errno; 322 goto error; 323 } 324 sh->tx_domain = domain; 325 #ifdef HAVE_MLX5DV_DR_ESWITCH 326 if (priv->config.dv_esw_en) { 327 domain = mlx5_glue->dr_create_domain 328 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 329 if (!domain) { 330 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 331 err = errno; 332 goto error; 333 } 334 sh->fdb_domain = domain; 335 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 336 } 337 #endif 338 if (!sh->tunnel_hub) 339 err = mlx5_alloc_tunnel_hub(sh); 340 if (err) { 341 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 342 goto error; 343 } 344 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 345 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 346 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 347 if (sh->fdb_domain) 348 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 349 } 350 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 351 #endif /* HAVE_MLX5DV_DR */ 352 sh->default_miss_action = 353 mlx5_glue->dr_create_flow_action_default_miss(); 354 if (!sh->default_miss_action) 355 DRV_LOG(WARNING, "Default miss action is not supported."); 356 return 0; 357 error: 358 /* Rollback the created objects. */ 359 if (sh->rx_domain) { 360 mlx5_glue->dr_destroy_domain(sh->rx_domain); 361 sh->rx_domain = NULL; 362 } 363 if (sh->tx_domain) { 364 mlx5_glue->dr_destroy_domain(sh->tx_domain); 365 sh->tx_domain = NULL; 366 } 367 if (sh->fdb_domain) { 368 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 369 sh->fdb_domain = NULL; 370 } 371 if (sh->esw_drop_action) { 372 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 373 sh->esw_drop_action = NULL; 374 } 375 if (sh->pop_vlan_action) { 376 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 377 sh->pop_vlan_action = NULL; 378 } 379 if (sh->encaps_decaps) { 380 mlx5_hlist_destroy(sh->encaps_decaps); 381 sh->encaps_decaps = NULL; 382 } 383 if (sh->modify_cmds) { 384 mlx5_hlist_destroy(sh->modify_cmds); 385 sh->modify_cmds = NULL; 386 } 387 if (sh->tag_table) { 388 /* tags should be destroyed with flow before. */ 389 mlx5_hlist_destroy(sh->tag_table); 390 sh->tag_table = NULL; 391 } 392 if (sh->tunnel_hub) { 393 mlx5_release_tunnel_hub(sh, priv->dev_port); 394 sh->tunnel_hub = NULL; 395 } 396 mlx5_free_table_hash_list(priv); 397 return err; 398 } 399 400 /** 401 * Destroy DR related data within private structure. 402 * 403 * @param[in] priv 404 * Pointer to the private device data structure. 405 */ 406 void 407 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 408 { 409 struct mlx5_dev_ctx_shared *sh = priv->sh; 410 411 MLX5_ASSERT(sh && sh->refcnt); 412 if (sh->refcnt > 1) 413 return; 414 #ifdef HAVE_MLX5DV_DR 415 if (sh->rx_domain) { 416 mlx5_glue->dr_destroy_domain(sh->rx_domain); 417 sh->rx_domain = NULL; 418 } 419 if (sh->tx_domain) { 420 mlx5_glue->dr_destroy_domain(sh->tx_domain); 421 sh->tx_domain = NULL; 422 } 423 #ifdef HAVE_MLX5DV_DR_ESWITCH 424 if (sh->fdb_domain) { 425 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 426 sh->fdb_domain = NULL; 427 } 428 if (sh->esw_drop_action) { 429 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 430 sh->esw_drop_action = NULL; 431 } 432 #endif 433 if (sh->pop_vlan_action) { 434 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 435 sh->pop_vlan_action = NULL; 436 } 437 #endif /* HAVE_MLX5DV_DR */ 438 if (sh->default_miss_action) 439 mlx5_glue->destroy_flow_action 440 (sh->default_miss_action); 441 if (sh->encaps_decaps) { 442 mlx5_hlist_destroy(sh->encaps_decaps); 443 sh->encaps_decaps = NULL; 444 } 445 if (sh->modify_cmds) { 446 mlx5_hlist_destroy(sh->modify_cmds); 447 sh->modify_cmds = NULL; 448 } 449 if (sh->tag_table) { 450 /* tags should be destroyed with flow before. */ 451 mlx5_hlist_destroy(sh->tag_table); 452 sh->tag_table = NULL; 453 } 454 if (sh->tunnel_hub) { 455 mlx5_release_tunnel_hub(sh, priv->dev_port); 456 sh->tunnel_hub = NULL; 457 } 458 mlx5_cache_list_destroy(&sh->port_id_action_list); 459 mlx5_cache_list_destroy(&sh->push_vlan_action_list); 460 mlx5_free_table_hash_list(priv); 461 } 462 463 /** 464 * Initialize shared data between primary and secondary process. 465 * 466 * A memzone is reserved by primary process and secondary processes attach to 467 * the memzone. 468 * 469 * @return 470 * 0 on success, a negative errno value otherwise and rte_errno is set. 471 */ 472 static int 473 mlx5_init_shared_data(void) 474 { 475 const struct rte_memzone *mz; 476 int ret = 0; 477 478 rte_spinlock_lock(&mlx5_shared_data_lock); 479 if (mlx5_shared_data == NULL) { 480 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 481 /* Allocate shared memory. */ 482 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 483 sizeof(*mlx5_shared_data), 484 SOCKET_ID_ANY, 0); 485 if (mz == NULL) { 486 DRV_LOG(ERR, 487 "Cannot allocate mlx5 shared data"); 488 ret = -rte_errno; 489 goto error; 490 } 491 mlx5_shared_data = mz->addr; 492 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 493 rte_spinlock_init(&mlx5_shared_data->lock); 494 } else { 495 /* Lookup allocated shared memory. */ 496 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 497 if (mz == NULL) { 498 DRV_LOG(ERR, 499 "Cannot attach mlx5 shared data"); 500 ret = -rte_errno; 501 goto error; 502 } 503 mlx5_shared_data = mz->addr; 504 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 505 } 506 } 507 error: 508 rte_spinlock_unlock(&mlx5_shared_data_lock); 509 return ret; 510 } 511 512 /** 513 * PMD global initialization. 514 * 515 * Independent from individual device, this function initializes global 516 * per-PMD data structures distinguishing primary and secondary processes. 517 * Hence, each initialization is called once per a process. 518 * 519 * @return 520 * 0 on success, a negative errno value otherwise and rte_errno is set. 521 */ 522 static int 523 mlx5_init_once(void) 524 { 525 struct mlx5_shared_data *sd; 526 struct mlx5_local_data *ld = &mlx5_local_data; 527 int ret = 0; 528 529 if (mlx5_init_shared_data()) 530 return -rte_errno; 531 sd = mlx5_shared_data; 532 MLX5_ASSERT(sd); 533 rte_spinlock_lock(&sd->lock); 534 switch (rte_eal_process_type()) { 535 case RTE_PROC_PRIMARY: 536 if (sd->init_done) 537 break; 538 LIST_INIT(&sd->mem_event_cb_list); 539 rte_rwlock_init(&sd->mem_event_rwlock); 540 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 541 mlx5_mr_mem_event_cb, NULL); 542 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 543 mlx5_mp_os_primary_handle); 544 if (ret) 545 goto out; 546 sd->init_done = true; 547 break; 548 case RTE_PROC_SECONDARY: 549 if (ld->init_done) 550 break; 551 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 552 mlx5_mp_os_secondary_handle); 553 if (ret) 554 goto out; 555 ++sd->secondary_cnt; 556 ld->init_done = true; 557 break; 558 default: 559 break; 560 } 561 out: 562 rte_spinlock_unlock(&sd->lock); 563 return ret; 564 } 565 566 /** 567 * Create the Tx queue DevX/Verbs object. 568 * 569 * @param dev 570 * Pointer to Ethernet device. 571 * @param idx 572 * Queue index in DPDK Tx queue array. 573 * 574 * @return 575 * 0 on success, a negative errno value otherwise and rte_errno is set. 576 */ 577 static int 578 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 579 { 580 struct mlx5_priv *priv = dev->data->dev_private; 581 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 582 struct mlx5_txq_ctrl *txq_ctrl = 583 container_of(txq_data, struct mlx5_txq_ctrl, txq); 584 585 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 586 return mlx5_txq_devx_obj_new(dev, idx); 587 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 588 if (!priv->config.dv_esw_en) 589 return mlx5_txq_devx_obj_new(dev, idx); 590 #endif 591 return mlx5_txq_ibv_obj_new(dev, idx); 592 } 593 594 /** 595 * Release an Tx DevX/verbs queue object. 596 * 597 * @param txq_obj 598 * DevX/Verbs Tx queue object. 599 */ 600 static void 601 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 602 { 603 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 604 mlx5_txq_devx_obj_release(txq_obj); 605 return; 606 } 607 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 608 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 609 mlx5_txq_devx_obj_release(txq_obj); 610 return; 611 } 612 #endif 613 mlx5_txq_ibv_obj_release(txq_obj); 614 } 615 616 /** 617 * DV flow counter mode detect and config. 618 * 619 * @param dev 620 * Pointer to rte_eth_dev structure. 621 * 622 */ 623 static void 624 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 625 { 626 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 627 struct mlx5_priv *priv = dev->data->dev_private; 628 struct mlx5_dev_ctx_shared *sh = priv->sh; 629 bool fallback; 630 631 #ifndef HAVE_IBV_DEVX_ASYNC 632 fallback = true; 633 #else 634 fallback = false; 635 if (!priv->config.devx || !priv->config.dv_flow_en || 636 !priv->config.hca_attr.flow_counters_dump || 637 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 638 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 639 fallback = true; 640 #endif 641 if (fallback) 642 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 643 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 644 priv->config.hca_attr.flow_counters_dump, 645 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 646 /* Initialize fallback mode only on the port initializes sh. */ 647 if (sh->refcnt == 1) 648 sh->cmng.counter_fallback = fallback; 649 else if (fallback != sh->cmng.counter_fallback) 650 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 651 "with others:%d.", PORT_ID(priv), fallback); 652 #endif 653 } 654 655 /** 656 * Spawn an Ethernet device from Verbs information. 657 * 658 * @param dpdk_dev 659 * Backing DPDK device. 660 * @param spawn 661 * Verbs device parameters (name, port, switch_info) to spawn. 662 * @param config 663 * Device configuration parameters. 664 * 665 * @return 666 * A valid Ethernet device object on success, NULL otherwise and rte_errno 667 * is set. The following errors are defined: 668 * 669 * EBUSY: device is not supposed to be spawned. 670 * EEXIST: device is already spawned 671 */ 672 static struct rte_eth_dev * 673 mlx5_dev_spawn(struct rte_device *dpdk_dev, 674 struct mlx5_dev_spawn_data *spawn, 675 struct mlx5_dev_config *config) 676 { 677 const struct mlx5_switch_info *switch_info = &spawn->info; 678 struct mlx5_dev_ctx_shared *sh = NULL; 679 struct ibv_port_attr port_attr; 680 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 681 struct rte_eth_dev *eth_dev = NULL; 682 struct mlx5_priv *priv = NULL; 683 int err = 0; 684 unsigned int hw_padding = 0; 685 unsigned int mps; 686 unsigned int cqe_comp; 687 unsigned int cqe_pad = 0; 688 unsigned int tunnel_en = 0; 689 unsigned int mpls_en = 0; 690 unsigned int swp = 0; 691 unsigned int mprq = 0; 692 unsigned int mprq_min_stride_size_n = 0; 693 unsigned int mprq_max_stride_size_n = 0; 694 unsigned int mprq_min_stride_num_n = 0; 695 unsigned int mprq_max_stride_num_n = 0; 696 struct rte_ether_addr mac; 697 char name[RTE_ETH_NAME_MAX_LEN]; 698 int own_domain_id = 0; 699 uint16_t port_id; 700 unsigned int i; 701 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 702 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 703 #endif 704 705 /* Determine if this port representor is supposed to be spawned. */ 706 if (switch_info->representor && dpdk_dev->devargs) { 707 struct rte_eth_devargs eth_da; 708 709 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 710 if (err) { 711 rte_errno = -err; 712 DRV_LOG(ERR, "failed to process device arguments: %s", 713 strerror(rte_errno)); 714 return NULL; 715 } 716 for (i = 0; i < eth_da.nb_representor_ports; ++i) 717 if (eth_da.representor_ports[i] == 718 (uint16_t)switch_info->port_name) 719 break; 720 if (i == eth_da.nb_representor_ports) { 721 rte_errno = EBUSY; 722 return NULL; 723 } 724 } 725 /* Build device name. */ 726 if (spawn->pf_bond < 0) { 727 /* Single device. */ 728 if (!switch_info->representor) 729 strlcpy(name, dpdk_dev->name, sizeof(name)); 730 else 731 snprintf(name, sizeof(name), "%s_representor_%u", 732 dpdk_dev->name, switch_info->port_name); 733 } else { 734 /* Bonding device. */ 735 if (!switch_info->representor) 736 snprintf(name, sizeof(name), "%s_%s", 737 dpdk_dev->name, 738 mlx5_os_get_dev_device_name(spawn->phys_dev)); 739 else 740 snprintf(name, sizeof(name), "%s_%s_representor_%u", 741 dpdk_dev->name, 742 mlx5_os_get_dev_device_name(spawn->phys_dev), 743 switch_info->port_name); 744 } 745 /* check if the device is already spawned */ 746 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 747 rte_errno = EEXIST; 748 return NULL; 749 } 750 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 751 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 752 struct mlx5_mp_id mp_id; 753 754 eth_dev = rte_eth_dev_attach_secondary(name); 755 if (eth_dev == NULL) { 756 DRV_LOG(ERR, "can not attach rte ethdev"); 757 rte_errno = ENOMEM; 758 return NULL; 759 } 760 eth_dev->device = dpdk_dev; 761 eth_dev->dev_ops = &mlx5_os_dev_sec_ops; 762 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 763 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 764 err = mlx5_proc_priv_init(eth_dev); 765 if (err) 766 return NULL; 767 mp_id.port_id = eth_dev->data->port_id; 768 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 769 /* Receive command fd from primary process */ 770 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 771 if (err < 0) 772 goto err_secondary; 773 /* Remap UAR for Tx queues. */ 774 err = mlx5_tx_uar_init_secondary(eth_dev, err); 775 if (err) 776 goto err_secondary; 777 /* 778 * Ethdev pointer is still required as input since 779 * the primary device is not accessible from the 780 * secondary process. 781 */ 782 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 783 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 784 return eth_dev; 785 err_secondary: 786 mlx5_dev_close(eth_dev); 787 return NULL; 788 } 789 /* 790 * Some parameters ("tx_db_nc" in particularly) are needed in 791 * advance to create dv/verbs device context. We proceed the 792 * devargs here to get ones, and later proceed devargs again 793 * to override some hardware settings. 794 */ 795 err = mlx5_args(config, dpdk_dev->devargs); 796 if (err) { 797 err = rte_errno; 798 DRV_LOG(ERR, "failed to process device arguments: %s", 799 strerror(rte_errno)); 800 goto error; 801 } 802 if (config->dv_miss_info) { 803 if (switch_info->master || switch_info->representor) 804 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 805 } 806 mlx5_malloc_mem_select(config->sys_mem_en); 807 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 808 if (!sh) 809 return NULL; 810 config->devx = sh->devx; 811 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 812 config->dest_tir = 1; 813 #endif 814 #ifdef HAVE_IBV_MLX5_MOD_SWP 815 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 816 #endif 817 /* 818 * Multi-packet send is supported by ConnectX-4 Lx PF as well 819 * as all ConnectX-5 devices. 820 */ 821 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 822 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 823 #endif 824 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 825 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 826 #endif 827 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 828 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 829 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 830 DRV_LOG(DEBUG, "enhanced MPW is supported"); 831 mps = MLX5_MPW_ENHANCED; 832 } else { 833 DRV_LOG(DEBUG, "MPW is supported"); 834 mps = MLX5_MPW; 835 } 836 } else { 837 DRV_LOG(DEBUG, "MPW isn't supported"); 838 mps = MLX5_MPW_DISABLED; 839 } 840 #ifdef HAVE_IBV_MLX5_MOD_SWP 841 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 842 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 843 DRV_LOG(DEBUG, "SWP support: %u", swp); 844 #endif 845 config->swp = !!swp; 846 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 847 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 848 struct mlx5dv_striding_rq_caps mprq_caps = 849 dv_attr.striding_rq_caps; 850 851 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 852 mprq_caps.min_single_stride_log_num_of_bytes); 853 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 854 mprq_caps.max_single_stride_log_num_of_bytes); 855 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 856 mprq_caps.min_single_wqe_log_num_of_strides); 857 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 858 mprq_caps.max_single_wqe_log_num_of_strides); 859 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 860 mprq_caps.supported_qpts); 861 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 862 mprq = 1; 863 mprq_min_stride_size_n = 864 mprq_caps.min_single_stride_log_num_of_bytes; 865 mprq_max_stride_size_n = 866 mprq_caps.max_single_stride_log_num_of_bytes; 867 mprq_min_stride_num_n = 868 mprq_caps.min_single_wqe_log_num_of_strides; 869 mprq_max_stride_num_n = 870 mprq_caps.max_single_wqe_log_num_of_strides; 871 } 872 #endif 873 if (RTE_CACHE_LINE_SIZE == 128 && 874 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 875 cqe_comp = 0; 876 else 877 cqe_comp = 1; 878 config->cqe_comp = cqe_comp; 879 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 880 /* Whether device supports 128B Rx CQE padding. */ 881 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 882 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 883 #endif 884 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 885 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 886 tunnel_en = ((dv_attr.tunnel_offloads_caps & 887 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 888 (dv_attr.tunnel_offloads_caps & 889 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 890 (dv_attr.tunnel_offloads_caps & 891 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 892 } 893 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 894 tunnel_en ? "" : "not "); 895 #else 896 DRV_LOG(WARNING, 897 "tunnel offloading disabled due to old OFED/rdma-core version"); 898 #endif 899 config->tunnel_en = tunnel_en; 900 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 901 mpls_en = ((dv_attr.tunnel_offloads_caps & 902 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 903 (dv_attr.tunnel_offloads_caps & 904 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 905 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 906 mpls_en ? "" : "not "); 907 #else 908 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 909 " old OFED/rdma-core version or firmware configuration"); 910 #endif 911 config->mpls_en = mpls_en; 912 /* Check port status. */ 913 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 914 if (err) { 915 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 916 goto error; 917 } 918 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 919 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 920 err = EINVAL; 921 goto error; 922 } 923 if (port_attr.state != IBV_PORT_ACTIVE) 924 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 925 mlx5_glue->port_state_str(port_attr.state), 926 port_attr.state); 927 /* Allocate private eth device data. */ 928 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 929 sizeof(*priv), 930 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 931 if (priv == NULL) { 932 DRV_LOG(ERR, "priv allocation failure"); 933 err = ENOMEM; 934 goto error; 935 } 936 priv->sh = sh; 937 priv->dev_port = spawn->phys_port; 938 priv->pci_dev = spawn->pci_dev; 939 priv->mtu = RTE_ETHER_MTU; 940 priv->mp_id.port_id = port_id; 941 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 942 /* Some internal functions rely on Netlink sockets, open them now. */ 943 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 944 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 945 priv->representor = !!switch_info->representor; 946 priv->master = !!switch_info->master; 947 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 948 priv->vport_meta_tag = 0; 949 priv->vport_meta_mask = 0; 950 priv->pf_bond = spawn->pf_bond; 951 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 952 /* 953 * The DevX port query API is implemented. E-Switch may use 954 * either vport or reg_c[0] metadata register to match on 955 * vport index. The engaged part of metadata register is 956 * defined by mask. 957 */ 958 if (switch_info->representor || switch_info->master) { 959 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 960 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 961 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 962 &devx_port); 963 if (err) { 964 DRV_LOG(WARNING, 965 "can't query devx port %d on device %s", 966 spawn->phys_port, 967 mlx5_os_get_dev_device_name(spawn->phys_dev)); 968 devx_port.comp_mask = 0; 969 } 970 } 971 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 972 priv->vport_meta_tag = devx_port.reg_c_0.value; 973 priv->vport_meta_mask = devx_port.reg_c_0.mask; 974 if (!priv->vport_meta_mask) { 975 DRV_LOG(ERR, "vport zero mask for port %d" 976 " on bonding device %s", 977 spawn->phys_port, 978 mlx5_os_get_dev_device_name 979 (spawn->phys_dev)); 980 err = ENOTSUP; 981 goto error; 982 } 983 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 984 DRV_LOG(ERR, "invalid vport tag for port %d" 985 " on bonding device %s", 986 spawn->phys_port, 987 mlx5_os_get_dev_device_name 988 (spawn->phys_dev)); 989 err = ENOTSUP; 990 goto error; 991 } 992 } 993 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 994 priv->vport_id = devx_port.vport_num; 995 } else if (spawn->pf_bond >= 0) { 996 DRV_LOG(ERR, "can't deduce vport index for port %d" 997 " on bonding device %s", 998 spawn->phys_port, 999 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1000 err = ENOTSUP; 1001 goto error; 1002 } else { 1003 /* Suppose vport index in compatible way. */ 1004 priv->vport_id = switch_info->representor ? 1005 switch_info->port_name + 1 : -1; 1006 } 1007 #else 1008 /* 1009 * Kernel/rdma_core support single E-Switch per PF configurations 1010 * only and vport_id field contains the vport index for 1011 * associated VF, which is deduced from representor port name. 1012 * For example, let's have the IB device port 10, it has 1013 * attached network device eth0, which has port name attribute 1014 * pf0vf2, we can deduce the VF number as 2, and set vport index 1015 * as 3 (2+1). This assigning schema should be changed if the 1016 * multiple E-Switch instances per PF configurations or/and PCI 1017 * subfunctions are added. 1018 */ 1019 priv->vport_id = switch_info->representor ? 1020 switch_info->port_name + 1 : -1; 1021 #endif 1022 /* representor_id field keeps the unmodified VF index. */ 1023 priv->representor_id = switch_info->representor ? 1024 switch_info->port_name : -1; 1025 /* 1026 * Look for sibling devices in order to reuse their switch domain 1027 * if any, otherwise allocate one. 1028 */ 1029 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1030 const struct mlx5_priv *opriv = 1031 rte_eth_devices[port_id].data->dev_private; 1032 1033 if (!opriv || 1034 opriv->sh != priv->sh || 1035 opriv->domain_id == 1036 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1037 continue; 1038 priv->domain_id = opriv->domain_id; 1039 break; 1040 } 1041 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1042 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1043 if (err) { 1044 err = rte_errno; 1045 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1046 strerror(rte_errno)); 1047 goto error; 1048 } 1049 own_domain_id = 1; 1050 } 1051 /* Override some values set by hardware configuration. */ 1052 mlx5_args(config, dpdk_dev->devargs); 1053 err = mlx5_dev_check_sibling_config(priv, config); 1054 if (err) 1055 goto error; 1056 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1057 IBV_DEVICE_RAW_IP_CSUM); 1058 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1059 (config->hw_csum ? "" : "not ")); 1060 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1061 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1062 DRV_LOG(DEBUG, "counters are not supported"); 1063 #endif 1064 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1065 if (config->dv_flow_en) { 1066 DRV_LOG(WARNING, "DV flow is not supported"); 1067 config->dv_flow_en = 0; 1068 } 1069 #endif 1070 config->ind_table_max_size = 1071 sh->device_attr.max_rwq_indirection_table_size; 1072 /* 1073 * Remove this check once DPDK supports larger/variable 1074 * indirection tables. 1075 */ 1076 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1077 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1078 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1079 config->ind_table_max_size); 1080 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1081 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1082 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1083 (config->hw_vlan_strip ? "" : "not ")); 1084 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1085 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1086 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1087 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1088 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1089 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1090 IBV_DEVICE_PCI_WRITE_END_PADDING); 1091 #endif 1092 if (config->hw_padding && !hw_padding) { 1093 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1094 config->hw_padding = 0; 1095 } else if (config->hw_padding) { 1096 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1097 } 1098 config->tso = (sh->device_attr.max_tso > 0 && 1099 (sh->device_attr.tso_supported_qpts & 1100 (1 << IBV_QPT_RAW_PACKET))); 1101 if (config->tso) 1102 config->tso_max_payload_sz = sh->device_attr.max_tso; 1103 /* 1104 * MPW is disabled by default, while the Enhanced MPW is enabled 1105 * by default. 1106 */ 1107 if (config->mps == MLX5_ARG_UNSET) 1108 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1109 MLX5_MPW_DISABLED; 1110 else 1111 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1112 DRV_LOG(INFO, "%sMPS is %s", 1113 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1114 config->mps == MLX5_MPW ? "legacy " : "", 1115 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1116 if (config->cqe_comp && !cqe_comp) { 1117 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1118 config->cqe_comp = 0; 1119 } 1120 if (config->cqe_pad && !cqe_pad) { 1121 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1122 config->cqe_pad = 0; 1123 } else if (config->cqe_pad) { 1124 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1125 } 1126 if (config->devx) { 1127 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1128 if (err) { 1129 err = -err; 1130 goto error; 1131 } 1132 #ifdef HAVE_MLX5DV_DR_ACTION_FLOW_HIT 1133 if (config->hca_attr.flow_hit_aso) { 1134 sh->flow_hit_aso_en = 1; 1135 err = mlx5_flow_aso_age_mng_init(sh); 1136 if (err) { 1137 err = -err; 1138 goto error; 1139 } 1140 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1141 } 1142 #endif /* HAVE_MLX5DV_DR_ACTION_FLOW_HIT */ 1143 /* Check relax ordering support. */ 1144 if (config->hca_attr.relaxed_ordering_write && 1145 config->hca_attr.relaxed_ordering_read && 1146 !haswell_broadwell_cpu) 1147 sh->cmng.relaxed_ordering = 1; 1148 /* Check for LRO support. */ 1149 if (config->dest_tir && config->hca_attr.lro_cap && 1150 config->dv_flow_en) { 1151 /* TBD check tunnel lro caps. */ 1152 config->lro.supported = config->hca_attr.lro_cap; 1153 DRV_LOG(DEBUG, "Device supports LRO"); 1154 /* 1155 * If LRO timeout is not configured by application, 1156 * use the minimal supported value. 1157 */ 1158 if (!config->lro.timeout) 1159 config->lro.timeout = 1160 config->hca_attr.lro_timer_supported_periods[0]; 1161 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1162 config->lro.timeout); 1163 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1164 "required for coalescing is %d bytes", 1165 config->hca_attr.lro_min_mss_size); 1166 } 1167 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1168 if (config->hca_attr.qos.sup && 1169 config->hca_attr.qos.srtcm_sup && 1170 config->dv_flow_en) { 1171 uint8_t reg_c_mask = 1172 config->hca_attr.qos.flow_meter_reg_c_ids; 1173 /* 1174 * Meter needs two REG_C's for color match and pre-sfx 1175 * flow match. Here get the REG_C for color match. 1176 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1177 */ 1178 reg_c_mask &= 0xfc; 1179 if (__builtin_popcount(reg_c_mask) < 1) { 1180 priv->mtr_en = 0; 1181 DRV_LOG(WARNING, "No available register for" 1182 " meter."); 1183 } else { 1184 priv->mtr_color_reg = ffs(reg_c_mask) - 1 + 1185 REG_C_0; 1186 priv->mtr_en = 1; 1187 priv->mtr_reg_share = 1188 config->hca_attr.qos.flow_meter_reg_share; 1189 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1190 priv->mtr_color_reg); 1191 } 1192 } 1193 #endif 1194 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1195 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1196 config->dv_flow_en) { 1197 priv->sampler_en = 1; 1198 DRV_LOG(DEBUG, "The Sampler enabled!\n"); 1199 } else { 1200 priv->sampler_en = 0; 1201 if (!config->hca_attr.log_max_ft_sampler_num) 1202 DRV_LOG(WARNING, "No available register for" 1203 " Sampler."); 1204 else 1205 DRV_LOG(DEBUG, "DV flow is not supported!\n"); 1206 } 1207 #endif 1208 } 1209 if (config->tx_pp) { 1210 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1211 config->hca_attr.dev_freq_khz); 1212 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1213 config->hca_attr.qos.packet_pacing ? "" : "not "); 1214 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1215 config->hca_attr.cross_channel ? "" : "not "); 1216 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1217 config->hca_attr.wqe_index_ignore ? "" : "not "); 1218 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1219 config->hca_attr.non_wire_sq ? "" : "not "); 1220 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1221 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1222 config->hca_attr.log_max_static_sq_wq); 1223 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1224 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1225 if (!config->devx) { 1226 DRV_LOG(ERR, "DevX is required for packet pacing"); 1227 err = ENODEV; 1228 goto error; 1229 } 1230 if (!config->hca_attr.qos.packet_pacing) { 1231 DRV_LOG(ERR, "Packet pacing is not supported"); 1232 err = ENODEV; 1233 goto error; 1234 } 1235 if (!config->hca_attr.cross_channel) { 1236 DRV_LOG(ERR, "Cross channel operations are" 1237 " required for packet pacing"); 1238 err = ENODEV; 1239 goto error; 1240 } 1241 if (!config->hca_attr.wqe_index_ignore) { 1242 DRV_LOG(ERR, "WQE index ignore feature is" 1243 " required for packet pacing"); 1244 err = ENODEV; 1245 goto error; 1246 } 1247 if (!config->hca_attr.non_wire_sq) { 1248 DRV_LOG(ERR, "Non-wire SQ feature is" 1249 " required for packet pacing"); 1250 err = ENODEV; 1251 goto error; 1252 } 1253 if (!config->hca_attr.log_max_static_sq_wq) { 1254 DRV_LOG(ERR, "Static WQE SQ feature is" 1255 " required for packet pacing"); 1256 err = ENODEV; 1257 goto error; 1258 } 1259 if (!config->hca_attr.qos.wqe_rate_pp) { 1260 DRV_LOG(ERR, "WQE rate mode is required" 1261 " for packet pacing"); 1262 err = ENODEV; 1263 goto error; 1264 } 1265 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1266 DRV_LOG(ERR, "DevX does not provide UAR offset," 1267 " can't create queues for packet pacing"); 1268 err = ENODEV; 1269 goto error; 1270 #endif 1271 } 1272 if (config->devx) { 1273 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1274 1275 err = config->hca_attr.access_register_user ? 1276 mlx5_devx_cmd_register_read 1277 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1278 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1279 if (!err) { 1280 uint32_t ts_mode; 1281 1282 /* MTUTC register is read successfully. */ 1283 ts_mode = MLX5_GET(register_mtutc, reg, 1284 time_stamp_mode); 1285 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1286 config->rt_timestamp = 1; 1287 } else { 1288 /* Kernel does not support register reading. */ 1289 if (config->hca_attr.dev_freq_khz == 1290 (NS_PER_S / MS_PER_S)) 1291 config->rt_timestamp = 1; 1292 } 1293 } 1294 /* 1295 * If HW has bug working with tunnel packet decapsulation and 1296 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1297 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1298 */ 1299 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1300 config->hw_fcs_strip = 0; 1301 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1302 (config->hw_fcs_strip ? "" : "not ")); 1303 if (config->mprq.enabled && mprq) { 1304 if (config->mprq.stride_num_n && 1305 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1306 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1307 config->mprq.stride_num_n = 1308 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1309 mprq_min_stride_num_n), 1310 mprq_max_stride_num_n); 1311 DRV_LOG(WARNING, 1312 "the number of strides" 1313 " for Multi-Packet RQ is out of range," 1314 " setting default value (%u)", 1315 1 << config->mprq.stride_num_n); 1316 } 1317 if (config->mprq.stride_size_n && 1318 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1319 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1320 config->mprq.stride_size_n = 1321 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1322 mprq_min_stride_size_n), 1323 mprq_max_stride_size_n); 1324 DRV_LOG(WARNING, 1325 "the size of a stride" 1326 " for Multi-Packet RQ is out of range," 1327 " setting default value (%u)", 1328 1 << config->mprq.stride_size_n); 1329 } 1330 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1331 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1332 } else if (config->mprq.enabled && !mprq) { 1333 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1334 config->mprq.enabled = 0; 1335 } 1336 if (config->max_dump_files_num == 0) 1337 config->max_dump_files_num = 128; 1338 eth_dev = rte_eth_dev_allocate(name); 1339 if (eth_dev == NULL) { 1340 DRV_LOG(ERR, "can not allocate rte ethdev"); 1341 err = ENOMEM; 1342 goto error; 1343 } 1344 if (priv->representor) { 1345 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1346 eth_dev->data->representor_id = priv->representor_id; 1347 } 1348 /* 1349 * Store associated network device interface index. This index 1350 * is permanent throughout the lifetime of device. So, we may store 1351 * the ifindex here and use the cached value further. 1352 */ 1353 MLX5_ASSERT(spawn->ifindex); 1354 priv->if_index = spawn->ifindex; 1355 if (priv->pf_bond >= 0 && priv->master) { 1356 /* Get bond interface info */ 1357 err = mlx5_sysfs_bond_info(priv->if_index, 1358 &priv->bond_ifindex, 1359 priv->bond_name); 1360 if (err) 1361 DRV_LOG(ERR, "unable to get bond info: %s", 1362 strerror(rte_errno)); 1363 else 1364 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1365 priv->if_index, priv->bond_ifindex, 1366 priv->bond_name); 1367 } 1368 eth_dev->data->dev_private = priv; 1369 priv->dev_data = eth_dev->data; 1370 eth_dev->data->mac_addrs = priv->mac; 1371 eth_dev->device = dpdk_dev; 1372 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1373 /* Configure the first MAC address by default. */ 1374 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1375 DRV_LOG(ERR, 1376 "port %u cannot get MAC address, is mlx5_en" 1377 " loaded? (errno: %s)", 1378 eth_dev->data->port_id, strerror(rte_errno)); 1379 err = ENODEV; 1380 goto error; 1381 } 1382 DRV_LOG(INFO, 1383 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1384 eth_dev->data->port_id, 1385 mac.addr_bytes[0], mac.addr_bytes[1], 1386 mac.addr_bytes[2], mac.addr_bytes[3], 1387 mac.addr_bytes[4], mac.addr_bytes[5]); 1388 #ifdef RTE_LIBRTE_MLX5_DEBUG 1389 { 1390 char ifname[IF_NAMESIZE]; 1391 1392 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1393 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1394 eth_dev->data->port_id, ifname); 1395 else 1396 DRV_LOG(DEBUG, "port %u ifname is unknown", 1397 eth_dev->data->port_id); 1398 } 1399 #endif 1400 /* Get actual MTU if possible. */ 1401 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1402 if (err) { 1403 err = rte_errno; 1404 goto error; 1405 } 1406 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1407 priv->mtu); 1408 /* Initialize burst functions to prevent crashes before link-up. */ 1409 eth_dev->rx_pkt_burst = removed_rx_burst; 1410 eth_dev->tx_pkt_burst = removed_tx_burst; 1411 eth_dev->dev_ops = &mlx5_os_dev_ops; 1412 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1413 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1414 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1415 /* Register MAC address. */ 1416 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1417 if (config->vf && config->vf_nl_en) 1418 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1419 mlx5_ifindex(eth_dev), 1420 eth_dev->data->mac_addrs, 1421 MLX5_MAX_MAC_ADDRESSES); 1422 priv->flows = 0; 1423 priv->ctrl_flows = 0; 1424 rte_spinlock_init(&priv->flow_list_lock); 1425 TAILQ_INIT(&priv->flow_meters); 1426 TAILQ_INIT(&priv->flow_meter_profiles); 1427 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1428 mlx5_glue->dv_set_context_attr(sh->ctx, 1429 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1430 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1431 .alloc = &mlx5_alloc_verbs_buf, 1432 .free = &mlx5_free_verbs_buf, 1433 .data = priv, 1434 })); 1435 /* Bring Ethernet device up. */ 1436 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1437 eth_dev->data->port_id); 1438 mlx5_set_link_up(eth_dev); 1439 /* 1440 * Even though the interrupt handler is not installed yet, 1441 * interrupts will still trigger on the async_fd from 1442 * Verbs context returned by ibv_open_device(). 1443 */ 1444 mlx5_link_update(eth_dev, 0); 1445 #ifdef HAVE_MLX5DV_DR_ESWITCH 1446 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1447 (switch_info->representor || switch_info->master))) 1448 config->dv_esw_en = 0; 1449 #else 1450 config->dv_esw_en = 0; 1451 #endif 1452 /* Detect minimal data bytes to inline. */ 1453 mlx5_set_min_inline(spawn, config); 1454 /* Store device configuration on private structure. */ 1455 priv->config = *config; 1456 /* Create context for virtual machine VLAN workaround. */ 1457 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1458 if (config->dv_flow_en) { 1459 err = mlx5_alloc_shared_dr(priv); 1460 if (err) 1461 goto error; 1462 } 1463 if (config->devx && config->dv_flow_en && config->dest_tir) { 1464 priv->obj_ops = devx_obj_ops; 1465 priv->obj_ops.drop_action_create = 1466 ibv_obj_ops.drop_action_create; 1467 priv->obj_ops.drop_action_destroy = 1468 ibv_obj_ops.drop_action_destroy; 1469 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1470 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1471 #else 1472 if (config->dv_esw_en) 1473 priv->obj_ops.txq_obj_modify = 1474 ibv_obj_ops.txq_obj_modify; 1475 #endif 1476 /* Use specific wrappers for Tx object. */ 1477 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1478 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1479 1480 } else { 1481 priv->obj_ops = ibv_obj_ops; 1482 } 1483 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1484 if (!priv->drop_queue.hrxq) 1485 goto error; 1486 /* Supported Verbs flow priority number detection. */ 1487 err = mlx5_flow_discover_priorities(eth_dev); 1488 if (err < 0) { 1489 err = -err; 1490 goto error; 1491 } 1492 priv->config.flow_prio = err; 1493 if (!priv->config.dv_esw_en && 1494 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1495 DRV_LOG(WARNING, "metadata mode %u is not supported " 1496 "(no E-Switch)", priv->config.dv_xmeta_en); 1497 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1498 } 1499 mlx5_set_metadata_mask(eth_dev); 1500 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1501 !priv->sh->dv_regc0_mask) { 1502 DRV_LOG(ERR, "metadata mode %u is not supported " 1503 "(no metadata reg_c[0] is available)", 1504 priv->config.dv_xmeta_en); 1505 err = ENOTSUP; 1506 goto error; 1507 } 1508 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 1509 mlx5_hrxq_create_cb, 1510 mlx5_hrxq_match_cb, 1511 mlx5_hrxq_remove_cb); 1512 /* Query availability of metadata reg_c's. */ 1513 err = mlx5_flow_discover_mreg_c(eth_dev); 1514 if (err < 0) { 1515 err = -err; 1516 goto error; 1517 } 1518 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1519 DRV_LOG(DEBUG, 1520 "port %u extensive metadata register is not supported", 1521 eth_dev->data->port_id); 1522 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1523 DRV_LOG(ERR, "metadata mode %u is not supported " 1524 "(no metadata registers available)", 1525 priv->config.dv_xmeta_en); 1526 err = ENOTSUP; 1527 goto error; 1528 } 1529 } 1530 if (priv->config.dv_flow_en && 1531 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1532 mlx5_flow_ext_mreg_supported(eth_dev) && 1533 priv->sh->dv_regc0_mask) { 1534 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1535 MLX5_FLOW_MREG_HTABLE_SZ, 1536 0, 0, 1537 flow_dv_mreg_create_cb, 1538 NULL, 1539 flow_dv_mreg_remove_cb); 1540 if (!priv->mreg_cp_tbl) { 1541 err = ENOMEM; 1542 goto error; 1543 } 1544 priv->mreg_cp_tbl->ctx = eth_dev; 1545 } 1546 rte_spinlock_init(&priv->shared_act_sl); 1547 mlx5_flow_counter_mode_config(eth_dev); 1548 if (priv->config.dv_flow_en) 1549 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1550 return eth_dev; 1551 error: 1552 if (priv) { 1553 if (priv->mreg_cp_tbl) 1554 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1555 if (priv->sh) 1556 mlx5_os_free_shared_dr(priv); 1557 if (priv->nl_socket_route >= 0) 1558 close(priv->nl_socket_route); 1559 if (priv->nl_socket_rdma >= 0) 1560 close(priv->nl_socket_rdma); 1561 if (priv->vmwa_context) 1562 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1563 if (eth_dev && priv->drop_queue.hrxq) 1564 mlx5_drop_action_destroy(eth_dev); 1565 if (own_domain_id) 1566 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1567 mlx5_cache_list_destroy(&priv->hrxqs); 1568 mlx5_free(priv); 1569 if (eth_dev != NULL) 1570 eth_dev->data->dev_private = NULL; 1571 } 1572 if (eth_dev != NULL) { 1573 /* mac_addrs must not be freed alone because part of 1574 * dev_private 1575 **/ 1576 eth_dev->data->mac_addrs = NULL; 1577 rte_eth_dev_release_port(eth_dev); 1578 } 1579 if (sh) 1580 mlx5_free_shared_dev_ctx(sh); 1581 MLX5_ASSERT(err > 0); 1582 rte_errno = err; 1583 return NULL; 1584 } 1585 1586 /** 1587 * Comparison callback to sort device data. 1588 * 1589 * This is meant to be used with qsort(). 1590 * 1591 * @param a[in] 1592 * Pointer to pointer to first data object. 1593 * @param b[in] 1594 * Pointer to pointer to second data object. 1595 * 1596 * @return 1597 * 0 if both objects are equal, less than 0 if the first argument is less 1598 * than the second, greater than 0 otherwise. 1599 */ 1600 static int 1601 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1602 { 1603 const struct mlx5_switch_info *si_a = 1604 &((const struct mlx5_dev_spawn_data *)a)->info; 1605 const struct mlx5_switch_info *si_b = 1606 &((const struct mlx5_dev_spawn_data *)b)->info; 1607 int ret; 1608 1609 /* Master device first. */ 1610 ret = si_b->master - si_a->master; 1611 if (ret) 1612 return ret; 1613 /* Then representor devices. */ 1614 ret = si_b->representor - si_a->representor; 1615 if (ret) 1616 return ret; 1617 /* Unidentified devices come last in no specific order. */ 1618 if (!si_a->representor) 1619 return 0; 1620 /* Order representors by name. */ 1621 return si_a->port_name - si_b->port_name; 1622 } 1623 1624 /** 1625 * Match PCI information for possible slaves of bonding device. 1626 * 1627 * @param[in] ibv_dev 1628 * Pointer to Infiniband device structure. 1629 * @param[in] pci_dev 1630 * Pointer to PCI device structure to match PCI address. 1631 * @param[in] nl_rdma 1632 * Netlink RDMA group socket handle. 1633 * 1634 * @return 1635 * negative value if no bonding device found, otherwise 1636 * positive index of slave PF in bonding. 1637 */ 1638 static int 1639 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1640 const struct rte_pci_device *pci_dev, 1641 int nl_rdma) 1642 { 1643 char ifname[IF_NAMESIZE + 1]; 1644 unsigned int ifindex; 1645 unsigned int np, i; 1646 FILE *file = NULL; 1647 int pf = -1; 1648 1649 /* 1650 * Try to get master device name. If something goes 1651 * wrong suppose the lack of kernel support and no 1652 * bonding devices. 1653 */ 1654 if (nl_rdma < 0) 1655 return -1; 1656 if (!strstr(ibv_dev->name, "bond")) 1657 return -1; 1658 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1659 if (!np) 1660 return -1; 1661 /* 1662 * The Master device might not be on the predefined 1663 * port (not on port index 1, it is not garanted), 1664 * we have to scan all Infiniband device port and 1665 * find master. 1666 */ 1667 for (i = 1; i <= np; ++i) { 1668 /* Check whether Infiniband port is populated. */ 1669 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1670 if (!ifindex) 1671 continue; 1672 if (!if_indextoname(ifindex, ifname)) 1673 continue; 1674 /* Try to read bonding slave names from sysfs. */ 1675 MKSTR(slaves, 1676 "/sys/class/net/%s/master/bonding/slaves", ifname); 1677 file = fopen(slaves, "r"); 1678 if (file) 1679 break; 1680 } 1681 if (!file) 1682 return -1; 1683 /* Use safe format to check maximal buffer length. */ 1684 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1685 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1686 char tmp_str[IF_NAMESIZE + 32]; 1687 struct rte_pci_addr pci_addr; 1688 struct mlx5_switch_info info; 1689 1690 /* Process slave interface names in the loop. */ 1691 snprintf(tmp_str, sizeof(tmp_str), 1692 "/sys/class/net/%s", ifname); 1693 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1694 DRV_LOG(WARNING, "can not get PCI address" 1695 " for netdev \"%s\"", ifname); 1696 continue; 1697 } 1698 if (pci_dev->addr.domain != pci_addr.domain || 1699 pci_dev->addr.bus != pci_addr.bus || 1700 pci_dev->addr.devid != pci_addr.devid || 1701 pci_dev->addr.function != pci_addr.function) 1702 continue; 1703 /* Slave interface PCI address match found. */ 1704 fclose(file); 1705 snprintf(tmp_str, sizeof(tmp_str), 1706 "/sys/class/net/%s/phys_port_name", ifname); 1707 file = fopen(tmp_str, "rb"); 1708 if (!file) 1709 break; 1710 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1711 if (fscanf(file, "%32s", tmp_str) == 1) 1712 mlx5_translate_port_name(tmp_str, &info); 1713 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 1714 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1715 pf = info.port_name; 1716 break; 1717 } 1718 if (file) 1719 fclose(file); 1720 return pf; 1721 } 1722 1723 /** 1724 * DPDK callback to register a PCI device. 1725 * 1726 * This function spawns Ethernet devices out of a given PCI device. 1727 * 1728 * @param[in] pci_drv 1729 * PCI driver structure (mlx5_driver). 1730 * @param[in] pci_dev 1731 * PCI device information. 1732 * 1733 * @return 1734 * 0 on success, a negative errno value otherwise and rte_errno is set. 1735 */ 1736 int 1737 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1738 struct rte_pci_device *pci_dev) 1739 { 1740 struct ibv_device **ibv_list; 1741 /* 1742 * Number of found IB Devices matching with requested PCI BDF. 1743 * nd != 1 means there are multiple IB devices over the same 1744 * PCI device and we have representors and master. 1745 */ 1746 unsigned int nd = 0; 1747 /* 1748 * Number of found IB device Ports. nd = 1 and np = 1..n means 1749 * we have the single multiport IB device, and there may be 1750 * representors attached to some of found ports. 1751 */ 1752 unsigned int np = 0; 1753 /* 1754 * Number of DPDK ethernet devices to Spawn - either over 1755 * multiple IB devices or multiple ports of single IB device. 1756 * Actually this is the number of iterations to spawn. 1757 */ 1758 unsigned int ns = 0; 1759 /* 1760 * Bonding device 1761 * < 0 - no bonding device (single one) 1762 * >= 0 - bonding device (value is slave PF index) 1763 */ 1764 int bd = -1; 1765 struct mlx5_dev_spawn_data *list = NULL; 1766 struct mlx5_dev_config dev_config; 1767 unsigned int dev_config_vf; 1768 int ret; 1769 1770 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1771 mlx5_pmd_socket_init(); 1772 ret = mlx5_init_once(); 1773 if (ret) { 1774 DRV_LOG(ERR, "unable to init PMD global data: %s", 1775 strerror(rte_errno)); 1776 return -rte_errno; 1777 } 1778 errno = 0; 1779 ibv_list = mlx5_glue->get_device_list(&ret); 1780 if (!ibv_list) { 1781 rte_errno = errno ? errno : ENOSYS; 1782 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1783 return -rte_errno; 1784 } 1785 /* 1786 * First scan the list of all Infiniband devices to find 1787 * matching ones, gathering into the list. 1788 */ 1789 struct ibv_device *ibv_match[ret + 1]; 1790 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1791 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1792 unsigned int i; 1793 1794 while (ret-- > 0) { 1795 struct rte_pci_addr pci_addr; 1796 1797 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1798 bd = mlx5_device_bond_pci_match 1799 (ibv_list[ret], pci_dev, nl_rdma); 1800 if (bd >= 0) { 1801 /* 1802 * Bonding device detected. Only one match is allowed, 1803 * the bonding is supported over multi-port IB device, 1804 * there should be no matches on representor PCI 1805 * functions or non VF LAG bonding devices with 1806 * specified address. 1807 */ 1808 if (nd) { 1809 DRV_LOG(ERR, 1810 "multiple PCI match on bonding device" 1811 "\"%s\" found", ibv_list[ret]->name); 1812 rte_errno = ENOENT; 1813 ret = -rte_errno; 1814 goto exit; 1815 } 1816 DRV_LOG(INFO, "PCI information matches for" 1817 " slave %d bonding device \"%s\"", 1818 bd, ibv_list[ret]->name); 1819 ibv_match[nd++] = ibv_list[ret]; 1820 break; 1821 } 1822 if (mlx5_dev_to_pci_addr 1823 (ibv_list[ret]->ibdev_path, &pci_addr)) 1824 continue; 1825 if (pci_dev->addr.domain != pci_addr.domain || 1826 pci_dev->addr.bus != pci_addr.bus || 1827 pci_dev->addr.devid != pci_addr.devid || 1828 pci_dev->addr.function != pci_addr.function) 1829 continue; 1830 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1831 ibv_list[ret]->name); 1832 ibv_match[nd++] = ibv_list[ret]; 1833 } 1834 ibv_match[nd] = NULL; 1835 if (!nd) { 1836 /* No device matches, just complain and bail out. */ 1837 DRV_LOG(WARNING, 1838 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1839 " are kernel drivers loaded?", 1840 pci_dev->addr.domain, pci_dev->addr.bus, 1841 pci_dev->addr.devid, pci_dev->addr.function); 1842 rte_errno = ENOENT; 1843 ret = -rte_errno; 1844 goto exit; 1845 } 1846 if (nd == 1) { 1847 /* 1848 * Found single matching device may have multiple ports. 1849 * Each port may be representor, we have to check the port 1850 * number and check the representors existence. 1851 */ 1852 if (nl_rdma >= 0) 1853 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1854 if (!np) 1855 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1856 " ports number", ibv_match[0]->name); 1857 if (bd >= 0 && !np) { 1858 DRV_LOG(ERR, "can not get ports" 1859 " for bonding device"); 1860 rte_errno = ENOENT; 1861 ret = -rte_errno; 1862 goto exit; 1863 } 1864 } 1865 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 1866 if (bd >= 0) { 1867 /* 1868 * This may happen if there is VF LAG kernel support and 1869 * application is compiled with older rdma_core library. 1870 */ 1871 DRV_LOG(ERR, 1872 "No kernel/verbs support for VF LAG bonding found."); 1873 rte_errno = ENOTSUP; 1874 ret = -rte_errno; 1875 goto exit; 1876 } 1877 #endif 1878 /* 1879 * Now we can determine the maximal 1880 * amount of devices to be spawned. 1881 */ 1882 list = mlx5_malloc(MLX5_MEM_ZERO, 1883 sizeof(struct mlx5_dev_spawn_data) * 1884 (np ? np : nd), 1885 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1886 if (!list) { 1887 DRV_LOG(ERR, "spawn data array allocation failure"); 1888 rte_errno = ENOMEM; 1889 ret = -rte_errno; 1890 goto exit; 1891 } 1892 if (bd >= 0 || np > 1) { 1893 /* 1894 * Single IB device with multiple ports found, 1895 * it may be E-Switch master device and representors. 1896 * We have to perform identification through the ports. 1897 */ 1898 MLX5_ASSERT(nl_rdma >= 0); 1899 MLX5_ASSERT(ns == 0); 1900 MLX5_ASSERT(nd == 1); 1901 MLX5_ASSERT(np); 1902 for (i = 1; i <= np; ++i) { 1903 list[ns].max_port = np; 1904 list[ns].phys_port = i; 1905 list[ns].phys_dev = ibv_match[0]; 1906 list[ns].eth_dev = NULL; 1907 list[ns].pci_dev = pci_dev; 1908 list[ns].pf_bond = bd; 1909 list[ns].ifindex = mlx5_nl_ifindex 1910 (nl_rdma, 1911 mlx5_os_get_dev_device_name 1912 (list[ns].phys_dev), i); 1913 if (!list[ns].ifindex) { 1914 /* 1915 * No network interface index found for the 1916 * specified port, it means there is no 1917 * representor on this port. It's OK, 1918 * there can be disabled ports, for example 1919 * if sriov_numvfs < sriov_totalvfs. 1920 */ 1921 continue; 1922 } 1923 ret = -1; 1924 if (nl_route >= 0) 1925 ret = mlx5_nl_switch_info 1926 (nl_route, 1927 list[ns].ifindex, 1928 &list[ns].info); 1929 if (ret || (!list[ns].info.representor && 1930 !list[ns].info.master)) { 1931 /* 1932 * We failed to recognize representors with 1933 * Netlink, let's try to perform the task 1934 * with sysfs. 1935 */ 1936 ret = mlx5_sysfs_switch_info 1937 (list[ns].ifindex, 1938 &list[ns].info); 1939 } 1940 if (!ret && bd >= 0) { 1941 switch (list[ns].info.name_type) { 1942 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 1943 if (list[ns].info.port_name == bd) 1944 ns++; 1945 break; 1946 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 1947 /* Fallthrough */ 1948 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 1949 if (list[ns].info.pf_num == bd) 1950 ns++; 1951 break; 1952 default: 1953 break; 1954 } 1955 continue; 1956 } 1957 if (!ret && (list[ns].info.representor ^ 1958 list[ns].info.master)) 1959 ns++; 1960 } 1961 if (!ns) { 1962 DRV_LOG(ERR, 1963 "unable to recognize master/representors" 1964 " on the IB device with multiple ports"); 1965 rte_errno = ENOENT; 1966 ret = -rte_errno; 1967 goto exit; 1968 } 1969 } else { 1970 /* 1971 * The existence of several matching entries (nd > 1) means 1972 * port representors have been instantiated. No existing Verbs 1973 * call nor sysfs entries can tell them apart, this can only 1974 * be done through Netlink calls assuming kernel drivers are 1975 * recent enough to support them. 1976 * 1977 * In the event of identification failure through Netlink, 1978 * try again through sysfs, then: 1979 * 1980 * 1. A single IB device matches (nd == 1) with single 1981 * port (np=0/1) and is not a representor, assume 1982 * no switch support. 1983 * 1984 * 2. Otherwise no safe assumptions can be made; 1985 * complain louder and bail out. 1986 */ 1987 for (i = 0; i != nd; ++i) { 1988 memset(&list[ns].info, 0, sizeof(list[ns].info)); 1989 list[ns].max_port = 1; 1990 list[ns].phys_port = 1; 1991 list[ns].phys_dev = ibv_match[i]; 1992 list[ns].eth_dev = NULL; 1993 list[ns].pci_dev = pci_dev; 1994 list[ns].pf_bond = -1; 1995 list[ns].ifindex = 0; 1996 if (nl_rdma >= 0) 1997 list[ns].ifindex = mlx5_nl_ifindex 1998 (nl_rdma, 1999 mlx5_os_get_dev_device_name 2000 (list[ns].phys_dev), 1); 2001 if (!list[ns].ifindex) { 2002 char ifname[IF_NAMESIZE]; 2003 2004 /* 2005 * Netlink failed, it may happen with old 2006 * ib_core kernel driver (before 4.16). 2007 * We can assume there is old driver because 2008 * here we are processing single ports IB 2009 * devices. Let's try sysfs to retrieve 2010 * the ifindex. The method works for 2011 * master device only. 2012 */ 2013 if (nd > 1) { 2014 /* 2015 * Multiple devices found, assume 2016 * representors, can not distinguish 2017 * master/representor and retrieve 2018 * ifindex via sysfs. 2019 */ 2020 continue; 2021 } 2022 ret = mlx5_get_ifname_sysfs 2023 (ibv_match[i]->ibdev_path, ifname); 2024 if (!ret) 2025 list[ns].ifindex = 2026 if_nametoindex(ifname); 2027 if (!list[ns].ifindex) { 2028 /* 2029 * No network interface index found 2030 * for the specified device, it means 2031 * there it is neither representor 2032 * nor master. 2033 */ 2034 continue; 2035 } 2036 } 2037 ret = -1; 2038 if (nl_route >= 0) 2039 ret = mlx5_nl_switch_info 2040 (nl_route, 2041 list[ns].ifindex, 2042 &list[ns].info); 2043 if (ret || (!list[ns].info.representor && 2044 !list[ns].info.master)) { 2045 /* 2046 * We failed to recognize representors with 2047 * Netlink, let's try to perform the task 2048 * with sysfs. 2049 */ 2050 ret = mlx5_sysfs_switch_info 2051 (list[ns].ifindex, 2052 &list[ns].info); 2053 } 2054 if (!ret && (list[ns].info.representor ^ 2055 list[ns].info.master)) { 2056 ns++; 2057 } else if ((nd == 1) && 2058 !list[ns].info.representor && 2059 !list[ns].info.master) { 2060 /* 2061 * Single IB device with 2062 * one physical port and 2063 * attached network device. 2064 * May be SRIOV is not enabled 2065 * or there is no representors. 2066 */ 2067 DRV_LOG(INFO, "no E-Switch support detected"); 2068 ns++; 2069 break; 2070 } 2071 } 2072 if (!ns) { 2073 DRV_LOG(ERR, 2074 "unable to recognize master/representors" 2075 " on the multiple IB devices"); 2076 rte_errno = ENOENT; 2077 ret = -rte_errno; 2078 goto exit; 2079 } 2080 } 2081 MLX5_ASSERT(ns); 2082 /* 2083 * Sort list to probe devices in natural order for users convenience 2084 * (i.e. master first, then representors from lowest to highest ID). 2085 */ 2086 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2087 /* Device specific configuration. */ 2088 switch (pci_dev->id.device_id) { 2089 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2090 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2091 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2092 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2093 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2094 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2095 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF: 2096 dev_config_vf = 1; 2097 break; 2098 default: 2099 dev_config_vf = 0; 2100 break; 2101 } 2102 for (i = 0; i != ns; ++i) { 2103 uint32_t restore; 2104 2105 /* Default configuration. */ 2106 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2107 dev_config.vf = dev_config_vf; 2108 dev_config.mps = MLX5_ARG_UNSET; 2109 dev_config.dbnc = MLX5_ARG_UNSET; 2110 dev_config.rx_vec_en = 1; 2111 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2112 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2113 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2114 dev_config.txqs_inline = MLX5_ARG_UNSET; 2115 dev_config.vf_nl_en = 1; 2116 dev_config.mr_ext_memseg_en = 1; 2117 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2118 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2119 dev_config.dv_esw_en = 1; 2120 dev_config.dv_flow_en = 1; 2121 dev_config.decap_en = 1; 2122 dev_config.log_hp_size = MLX5_ARG_UNSET; 2123 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2124 &list[i], 2125 &dev_config); 2126 if (!list[i].eth_dev) { 2127 if (rte_errno != EBUSY && rte_errno != EEXIST) 2128 break; 2129 /* Device is disabled or already spawned. Ignore it. */ 2130 continue; 2131 } 2132 restore = list[i].eth_dev->data->dev_flags; 2133 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2134 /* Restore non-PCI flags cleared by the above call. */ 2135 list[i].eth_dev->data->dev_flags |= restore; 2136 rte_eth_dev_probing_finish(list[i].eth_dev); 2137 } 2138 if (i != ns) { 2139 DRV_LOG(ERR, 2140 "probe of PCI device " PCI_PRI_FMT " aborted after" 2141 " encountering an error: %s", 2142 pci_dev->addr.domain, pci_dev->addr.bus, 2143 pci_dev->addr.devid, pci_dev->addr.function, 2144 strerror(rte_errno)); 2145 ret = -rte_errno; 2146 /* Roll back. */ 2147 while (i--) { 2148 if (!list[i].eth_dev) 2149 continue; 2150 mlx5_dev_close(list[i].eth_dev); 2151 /* mac_addrs must not be freed because in dev_private */ 2152 list[i].eth_dev->data->mac_addrs = NULL; 2153 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2154 } 2155 /* Restore original error. */ 2156 rte_errno = -ret; 2157 } else { 2158 ret = 0; 2159 } 2160 exit: 2161 /* 2162 * Do the routine cleanup: 2163 * - close opened Netlink sockets 2164 * - free allocated spawn data array 2165 * - free the Infiniband device list 2166 */ 2167 if (nl_rdma >= 0) 2168 close(nl_rdma); 2169 if (nl_route >= 0) 2170 close(nl_route); 2171 if (list) 2172 mlx5_free(list); 2173 MLX5_ASSERT(ibv_list); 2174 mlx5_glue->free_device_list(ibv_list); 2175 return ret; 2176 } 2177 2178 static int 2179 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2180 { 2181 char *env; 2182 int value; 2183 2184 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2185 /* Get environment variable to store. */ 2186 env = getenv(MLX5_SHUT_UP_BF); 2187 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2188 if (config->dbnc == MLX5_ARG_UNSET) 2189 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2190 else 2191 setenv(MLX5_SHUT_UP_BF, 2192 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2193 return value; 2194 } 2195 2196 static void 2197 mlx5_restore_doorbell_mapping_env(int value) 2198 { 2199 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2200 /* Restore the original environment variable state. */ 2201 if (value == MLX5_ARG_UNSET) 2202 unsetenv(MLX5_SHUT_UP_BF); 2203 else 2204 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2205 } 2206 2207 /** 2208 * Extract pdn of PD object using DV API. 2209 * 2210 * @param[in] pd 2211 * Pointer to the verbs PD object. 2212 * @param[out] pdn 2213 * Pointer to the PD object number variable. 2214 * 2215 * @return 2216 * 0 on success, error value otherwise. 2217 */ 2218 int 2219 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2220 { 2221 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2222 struct mlx5dv_obj obj; 2223 struct mlx5dv_pd pd_info; 2224 int ret = 0; 2225 2226 obj.pd.in = pd; 2227 obj.pd.out = &pd_info; 2228 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2229 if (ret) { 2230 DRV_LOG(DEBUG, "Fail to get PD object info"); 2231 return ret; 2232 } 2233 *pdn = pd_info.pdn; 2234 return 0; 2235 #else 2236 (void)pd; 2237 (void)pdn; 2238 return -ENOTSUP; 2239 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2240 } 2241 2242 /** 2243 * Function API to open IB device. 2244 * 2245 * This function calls the Linux glue APIs to open a device. 2246 * 2247 * @param[in] spawn 2248 * Pointer to the IB device attributes (name, port, etc). 2249 * @param[out] config 2250 * Pointer to device configuration structure. 2251 * @param[out] sh 2252 * Pointer to shared context structure. 2253 * 2254 * @return 2255 * 0 on success, a positive error value otherwise. 2256 */ 2257 int 2258 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2259 const struct mlx5_dev_config *config, 2260 struct mlx5_dev_ctx_shared *sh) 2261 { 2262 int dbmap_env; 2263 int err = 0; 2264 2265 sh->numa_node = spawn->pci_dev->device.numa_node; 2266 pthread_mutex_init(&sh->txpp.mutex, NULL); 2267 /* 2268 * Configure environment variable "MLX5_BF_SHUT_UP" 2269 * before the device creation. The rdma_core library 2270 * checks the variable at device creation and 2271 * stores the result internally. 2272 */ 2273 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2274 /* Try to open IB device with DV first, then usual Verbs. */ 2275 errno = 0; 2276 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2277 if (sh->ctx) { 2278 sh->devx = 1; 2279 DRV_LOG(DEBUG, "DevX is supported"); 2280 /* The device is created, no need for environment. */ 2281 mlx5_restore_doorbell_mapping_env(dbmap_env); 2282 } else { 2283 /* The environment variable is still configured. */ 2284 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2285 err = errno ? errno : ENODEV; 2286 /* 2287 * The environment variable is not needed anymore, 2288 * all device creation attempts are completed. 2289 */ 2290 mlx5_restore_doorbell_mapping_env(dbmap_env); 2291 if (!sh->ctx) 2292 return err; 2293 DRV_LOG(DEBUG, "DevX is NOT supported"); 2294 err = 0; 2295 } 2296 return err; 2297 } 2298 2299 /** 2300 * Install shared asynchronous device events handler. 2301 * This function is implemented to support event sharing 2302 * between multiple ports of single IB device. 2303 * 2304 * @param sh 2305 * Pointer to mlx5_dev_ctx_shared object. 2306 */ 2307 void 2308 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2309 { 2310 int ret; 2311 int flags; 2312 2313 sh->intr_handle.fd = -1; 2314 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2315 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2316 F_SETFL, flags | O_NONBLOCK); 2317 if (ret) { 2318 DRV_LOG(INFO, "failed to change file descriptor async event" 2319 " queue"); 2320 } else { 2321 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2322 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2323 if (rte_intr_callback_register(&sh->intr_handle, 2324 mlx5_dev_interrupt_handler, sh)) { 2325 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2326 sh->intr_handle.fd = -1; 2327 } 2328 } 2329 if (sh->devx) { 2330 #ifdef HAVE_IBV_DEVX_ASYNC 2331 sh->intr_handle_devx.fd = -1; 2332 sh->devx_comp = 2333 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2334 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2335 if (!devx_comp) { 2336 DRV_LOG(INFO, "failed to allocate devx_comp."); 2337 return; 2338 } 2339 flags = fcntl(devx_comp->fd, F_GETFL); 2340 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2341 if (ret) { 2342 DRV_LOG(INFO, "failed to change file descriptor" 2343 " devx comp"); 2344 return; 2345 } 2346 sh->intr_handle_devx.fd = devx_comp->fd; 2347 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2348 if (rte_intr_callback_register(&sh->intr_handle_devx, 2349 mlx5_dev_interrupt_handler_devx, sh)) { 2350 DRV_LOG(INFO, "Fail to install the devx shared" 2351 " interrupt."); 2352 sh->intr_handle_devx.fd = -1; 2353 } 2354 #endif /* HAVE_IBV_DEVX_ASYNC */ 2355 } 2356 } 2357 2358 /** 2359 * Uninstall shared asynchronous device events handler. 2360 * This function is implemented to support event sharing 2361 * between multiple ports of single IB device. 2362 * 2363 * @param dev 2364 * Pointer to mlx5_dev_ctx_shared object. 2365 */ 2366 void 2367 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2368 { 2369 if (sh->intr_handle.fd >= 0) 2370 mlx5_intr_callback_unregister(&sh->intr_handle, 2371 mlx5_dev_interrupt_handler, sh); 2372 #ifdef HAVE_IBV_DEVX_ASYNC 2373 if (sh->intr_handle_devx.fd >= 0) 2374 rte_intr_callback_unregister(&sh->intr_handle_devx, 2375 mlx5_dev_interrupt_handler_devx, sh); 2376 if (sh->devx_comp) 2377 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2378 #endif 2379 } 2380 2381 /** 2382 * Read statistics by a named counter. 2383 * 2384 * @param[in] priv 2385 * Pointer to the private device data structure. 2386 * @param[in] ctr_name 2387 * Pointer to the name of the statistic counter to read 2388 * @param[out] stat 2389 * Pointer to read statistic value. 2390 * @return 2391 * 0 on success and stat is valud, 1 if failed to read the value 2392 * rte_errno is set. 2393 * 2394 */ 2395 int 2396 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2397 uint64_t *stat) 2398 { 2399 int fd; 2400 2401 if (priv->sh) { 2402 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2403 priv->sh->ibdev_path, 2404 priv->dev_port, 2405 ctr_name); 2406 fd = open(path, O_RDONLY); 2407 /* 2408 * in switchdev the file location is not per port 2409 * but rather in <ibdev_path>/hw_counters/<file_name>. 2410 */ 2411 if (fd == -1) { 2412 MKSTR(path1, "%s/hw_counters/%s", 2413 priv->sh->ibdev_path, 2414 ctr_name); 2415 fd = open(path1, O_RDONLY); 2416 } 2417 if (fd != -1) { 2418 char buf[21] = {'\0'}; 2419 ssize_t n = read(fd, buf, sizeof(buf)); 2420 2421 close(fd); 2422 if (n != -1) { 2423 *stat = strtoull(buf, NULL, 10); 2424 return 0; 2425 } 2426 } 2427 } 2428 *stat = 0; 2429 return 1; 2430 } 2431 2432 /** 2433 * Set the reg_mr and dereg_mr call backs 2434 * 2435 * @param reg_mr_cb[out] 2436 * Pointer to reg_mr func 2437 * @param dereg_mr_cb[out] 2438 * Pointer to dereg_mr func 2439 * 2440 */ 2441 void 2442 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2443 mlx5_dereg_mr_t *dereg_mr_cb) 2444 { 2445 *reg_mr_cb = mlx5_verbs_ops.reg_mr; 2446 *dereg_mr_cb = mlx5_verbs_ops.dereg_mr; 2447 } 2448 2449 /** 2450 * Remove a MAC address from device 2451 * 2452 * @param dev 2453 * Pointer to Ethernet device structure. 2454 * @param index 2455 * MAC address index. 2456 */ 2457 void 2458 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2459 { 2460 struct mlx5_priv *priv = dev->data->dev_private; 2461 const int vf = priv->config.vf; 2462 2463 if (vf) 2464 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2465 mlx5_ifindex(dev), priv->mac_own, 2466 &dev->data->mac_addrs[index], index); 2467 } 2468 2469 /** 2470 * Adds a MAC address to the device 2471 * 2472 * @param dev 2473 * Pointer to Ethernet device structure. 2474 * @param mac_addr 2475 * MAC address to register. 2476 * @param index 2477 * MAC address index. 2478 * 2479 * @return 2480 * 0 on success, a negative errno value otherwise 2481 */ 2482 int 2483 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2484 uint32_t index) 2485 { 2486 struct mlx5_priv *priv = dev->data->dev_private; 2487 const int vf = priv->config.vf; 2488 int ret = 0; 2489 2490 if (vf) 2491 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2492 mlx5_ifindex(dev), priv->mac_own, 2493 mac, index); 2494 return ret; 2495 } 2496 2497 /** 2498 * Modify a VF MAC address 2499 * 2500 * @param priv 2501 * Pointer to device private data. 2502 * @param mac_addr 2503 * MAC address to modify into. 2504 * @param iface_idx 2505 * Net device interface index 2506 * @param vf_index 2507 * VF index 2508 * 2509 * @return 2510 * 0 on success, a negative errno value otherwise 2511 */ 2512 int 2513 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2514 unsigned int iface_idx, 2515 struct rte_ether_addr *mac_addr, 2516 int vf_index) 2517 { 2518 return mlx5_nl_vf_mac_addr_modify 2519 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2520 } 2521 2522 /** 2523 * Set device promiscuous mode 2524 * 2525 * @param dev 2526 * Pointer to Ethernet device structure. 2527 * @param enable 2528 * 0 - promiscuous is disabled, otherwise - enabled 2529 * 2530 * @return 2531 * 0 on success, a negative error value otherwise 2532 */ 2533 int 2534 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2535 { 2536 struct mlx5_priv *priv = dev->data->dev_private; 2537 2538 return mlx5_nl_promisc(priv->nl_socket_route, 2539 mlx5_ifindex(dev), !!enable); 2540 } 2541 2542 /** 2543 * Set device promiscuous mode 2544 * 2545 * @param dev 2546 * Pointer to Ethernet device structure. 2547 * @param enable 2548 * 0 - all multicase is disabled, otherwise - enabled 2549 * 2550 * @return 2551 * 0 on success, a negative error value otherwise 2552 */ 2553 int 2554 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2555 { 2556 struct mlx5_priv *priv = dev->data->dev_private; 2557 2558 return mlx5_nl_allmulti(priv->nl_socket_route, 2559 mlx5_ifindex(dev), !!enable); 2560 } 2561 2562 /** 2563 * Flush device MAC addresses 2564 * 2565 * @param dev 2566 * Pointer to Ethernet device structure. 2567 * 2568 */ 2569 void 2570 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2571 { 2572 struct mlx5_priv *priv = dev->data->dev_private; 2573 2574 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2575 dev->data->mac_addrs, 2576 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2577 } 2578 2579 const struct eth_dev_ops mlx5_os_dev_ops = { 2580 .dev_configure = mlx5_dev_configure, 2581 .dev_start = mlx5_dev_start, 2582 .dev_stop = mlx5_dev_stop, 2583 .dev_set_link_down = mlx5_set_link_down, 2584 .dev_set_link_up = mlx5_set_link_up, 2585 .dev_close = mlx5_dev_close, 2586 .promiscuous_enable = mlx5_promiscuous_enable, 2587 .promiscuous_disable = mlx5_promiscuous_disable, 2588 .allmulticast_enable = mlx5_allmulticast_enable, 2589 .allmulticast_disable = mlx5_allmulticast_disable, 2590 .link_update = mlx5_link_update, 2591 .stats_get = mlx5_stats_get, 2592 .stats_reset = mlx5_stats_reset, 2593 .xstats_get = mlx5_xstats_get, 2594 .xstats_reset = mlx5_xstats_reset, 2595 .xstats_get_names = mlx5_xstats_get_names, 2596 .fw_version_get = mlx5_fw_version_get, 2597 .dev_infos_get = mlx5_dev_infos_get, 2598 .read_clock = mlx5_txpp_read_clock, 2599 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2600 .vlan_filter_set = mlx5_vlan_filter_set, 2601 .rx_queue_setup = mlx5_rx_queue_setup, 2602 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2603 .tx_queue_setup = mlx5_tx_queue_setup, 2604 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2605 .rx_queue_release = mlx5_rx_queue_release, 2606 .tx_queue_release = mlx5_tx_queue_release, 2607 .rx_queue_start = mlx5_rx_queue_start, 2608 .rx_queue_stop = mlx5_rx_queue_stop, 2609 .tx_queue_start = mlx5_tx_queue_start, 2610 .tx_queue_stop = mlx5_tx_queue_stop, 2611 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2612 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2613 .mac_addr_remove = mlx5_mac_addr_remove, 2614 .mac_addr_add = mlx5_mac_addr_add, 2615 .mac_addr_set = mlx5_mac_addr_set, 2616 .set_mc_addr_list = mlx5_set_mc_addr_list, 2617 .mtu_set = mlx5_dev_set_mtu, 2618 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2619 .vlan_offload_set = mlx5_vlan_offload_set, 2620 .reta_update = mlx5_dev_rss_reta_update, 2621 .reta_query = mlx5_dev_rss_reta_query, 2622 .rss_hash_update = mlx5_rss_hash_update, 2623 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2624 .filter_ctrl = mlx5_dev_filter_ctrl, 2625 .rxq_info_get = mlx5_rxq_info_get, 2626 .txq_info_get = mlx5_txq_info_get, 2627 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2628 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2629 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2630 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2631 .is_removed = mlx5_is_removed, 2632 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2633 .get_module_info = mlx5_get_module_info, 2634 .get_module_eeprom = mlx5_get_module_eeprom, 2635 .hairpin_cap_get = mlx5_hairpin_cap_get, 2636 .mtr_ops_get = mlx5_flow_meter_ops_get, 2637 .hairpin_bind = mlx5_hairpin_bind, 2638 .hairpin_unbind = mlx5_hairpin_unbind, 2639 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2640 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2641 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2642 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2643 }; 2644 2645 /* Available operations from secondary process. */ 2646 const struct eth_dev_ops mlx5_os_dev_sec_ops = { 2647 .stats_get = mlx5_stats_get, 2648 .stats_reset = mlx5_stats_reset, 2649 .xstats_get = mlx5_xstats_get, 2650 .xstats_reset = mlx5_xstats_reset, 2651 .xstats_get_names = mlx5_xstats_get_names, 2652 .fw_version_get = mlx5_fw_version_get, 2653 .dev_infos_get = mlx5_dev_infos_get, 2654 .read_clock = mlx5_txpp_read_clock, 2655 .rx_queue_start = mlx5_rx_queue_start, 2656 .rx_queue_stop = mlx5_rx_queue_stop, 2657 .tx_queue_start = mlx5_tx_queue_start, 2658 .tx_queue_stop = mlx5_tx_queue_stop, 2659 .rxq_info_get = mlx5_rxq_info_get, 2660 .txq_info_get = mlx5_txq_info_get, 2661 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2662 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2663 .get_module_info = mlx5_get_module_info, 2664 .get_module_eeprom = mlx5_get_module_eeprom, 2665 }; 2666 2667 /* Available operations in flow isolated mode. */ 2668 const struct eth_dev_ops mlx5_os_dev_ops_isolate = { 2669 .dev_configure = mlx5_dev_configure, 2670 .dev_start = mlx5_dev_start, 2671 .dev_stop = mlx5_dev_stop, 2672 .dev_set_link_down = mlx5_set_link_down, 2673 .dev_set_link_up = mlx5_set_link_up, 2674 .dev_close = mlx5_dev_close, 2675 .promiscuous_enable = mlx5_promiscuous_enable, 2676 .promiscuous_disable = mlx5_promiscuous_disable, 2677 .allmulticast_enable = mlx5_allmulticast_enable, 2678 .allmulticast_disable = mlx5_allmulticast_disable, 2679 .link_update = mlx5_link_update, 2680 .stats_get = mlx5_stats_get, 2681 .stats_reset = mlx5_stats_reset, 2682 .xstats_get = mlx5_xstats_get, 2683 .xstats_reset = mlx5_xstats_reset, 2684 .xstats_get_names = mlx5_xstats_get_names, 2685 .fw_version_get = mlx5_fw_version_get, 2686 .dev_infos_get = mlx5_dev_infos_get, 2687 .read_clock = mlx5_txpp_read_clock, 2688 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2689 .vlan_filter_set = mlx5_vlan_filter_set, 2690 .rx_queue_setup = mlx5_rx_queue_setup, 2691 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2692 .tx_queue_setup = mlx5_tx_queue_setup, 2693 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2694 .rx_queue_release = mlx5_rx_queue_release, 2695 .tx_queue_release = mlx5_tx_queue_release, 2696 .rx_queue_start = mlx5_rx_queue_start, 2697 .rx_queue_stop = mlx5_rx_queue_stop, 2698 .tx_queue_start = mlx5_tx_queue_start, 2699 .tx_queue_stop = mlx5_tx_queue_stop, 2700 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2701 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2702 .mac_addr_remove = mlx5_mac_addr_remove, 2703 .mac_addr_add = mlx5_mac_addr_add, 2704 .mac_addr_set = mlx5_mac_addr_set, 2705 .set_mc_addr_list = mlx5_set_mc_addr_list, 2706 .mtu_set = mlx5_dev_set_mtu, 2707 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2708 .vlan_offload_set = mlx5_vlan_offload_set, 2709 .filter_ctrl = mlx5_dev_filter_ctrl, 2710 .rxq_info_get = mlx5_rxq_info_get, 2711 .txq_info_get = mlx5_txq_info_get, 2712 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2713 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2714 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2715 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2716 .is_removed = mlx5_is_removed, 2717 .get_module_info = mlx5_get_module_info, 2718 .get_module_eeprom = mlx5_get_module_eeprom, 2719 .hairpin_cap_get = mlx5_hairpin_cap_get, 2720 .mtr_ops_get = mlx5_flow_meter_ops_get, 2721 .hairpin_bind = mlx5_hairpin_bind, 2722 .hairpin_unbind = mlx5_hairpin_unbind, 2723 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2724 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2725 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2726 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2727 }; 2728