1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 120 device_attr->max_mr = attr_ex.orig_attr.max_mr; 121 device_attr->max_pd = attr_ex.orig_attr.max_pd; 122 device_attr->max_qp = attr_ex.orig_attr.max_qp; 123 device_attr->max_srq = attr_ex.orig_attr.max_srq; 124 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 125 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 126 device_attr->max_rwq_indirection_table_size = 127 attr_ex.rss_caps.max_rwq_indirection_table_size; 128 device_attr->max_tso = attr_ex.tso_caps.max_tso; 129 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 130 131 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 132 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 133 if (err) 134 return err; 135 136 device_attr->flags = dv_attr.flags; 137 device_attr->comp_mask = dv_attr.comp_mask; 138 #ifdef HAVE_IBV_MLX5_MOD_SWP 139 device_attr->sw_parsing_offloads = 140 dv_attr.sw_parsing_caps.sw_parsing_offloads; 141 #endif 142 device_attr->min_single_stride_log_num_of_bytes = 143 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 144 device_attr->max_single_stride_log_num_of_bytes = 145 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 146 device_attr->min_single_wqe_log_num_of_strides = 147 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 148 device_attr->max_single_wqe_log_num_of_strides = 149 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 150 device_attr->stride_supported_qpts = 151 dv_attr.striding_rq_caps.supported_qpts; 152 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 153 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 154 #endif 155 156 return err; 157 } 158 159 /** 160 * Verbs callback to allocate a memory. This function should allocate the space 161 * according to the size provided residing inside a huge page. 162 * Please note that all allocation must respect the alignment from libmlx5 163 * (i.e. currently rte_mem_page_size()). 164 * 165 * @param[in] size 166 * The size in bytes of the memory to allocate. 167 * @param[in] data 168 * A pointer to the callback data. 169 * 170 * @return 171 * Allocated buffer, NULL otherwise and rte_errno is set. 172 */ 173 static void * 174 mlx5_alloc_verbs_buf(size_t size, void *data) 175 { 176 struct mlx5_dev_ctx_shared *sh = data; 177 void *ret; 178 size_t alignment = rte_mem_page_size(); 179 if (alignment == (size_t)-1) { 180 DRV_LOG(ERR, "Failed to get mem page size"); 181 rte_errno = ENOMEM; 182 return NULL; 183 } 184 185 MLX5_ASSERT(data != NULL); 186 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 187 if (!ret && size) 188 rte_errno = ENOMEM; 189 return ret; 190 } 191 192 /** 193 * Verbs callback to free a memory. 194 * 195 * @param[in] ptr 196 * A pointer to the memory to free. 197 * @param[in] data 198 * A pointer to the callback data. 199 */ 200 static void 201 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 202 { 203 MLX5_ASSERT(data != NULL); 204 mlx5_free(ptr); 205 } 206 207 /** 208 * Initialize DR related data within private structure. 209 * Routine checks the reference counter and does actual 210 * resources creation/initialization only if counter is zero. 211 * 212 * @param[in] priv 213 * Pointer to the private device data structure. 214 * 215 * @return 216 * Zero on success, positive error code otherwise. 217 */ 218 static int 219 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 220 { 221 struct mlx5_dev_ctx_shared *sh = priv->sh; 222 char s[MLX5_HLIST_NAMESIZE] __rte_unused; 223 int err; 224 225 MLX5_ASSERT(sh && sh->refcnt); 226 if (sh->refcnt > 1) 227 return 0; 228 err = mlx5_alloc_table_hash_list(priv); 229 if (err) 230 goto error; 231 /* The resources below are only valid with DV support. */ 232 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 233 /* Init port id action cache list. */ 234 snprintf(s, sizeof(s), "%s_port_id_action_cache", sh->ibdev_name); 235 mlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh, 236 flow_dv_port_id_create_cb, 237 flow_dv_port_id_match_cb, 238 flow_dv_port_id_remove_cb); 239 /* Init push vlan action cache list. */ 240 snprintf(s, sizeof(s), "%s_push_vlan_action_cache", sh->ibdev_name); 241 mlx5_cache_list_init(&sh->push_vlan_action_list, s, 0, sh, 242 flow_dv_push_vlan_create_cb, 243 flow_dv_push_vlan_match_cb, 244 flow_dv_push_vlan_remove_cb); 245 /* Init sample action cache list. */ 246 snprintf(s, sizeof(s), "%s_sample_action_cache", sh->ibdev_name); 247 mlx5_cache_list_init(&sh->sample_action_list, s, 0, sh, 248 flow_dv_sample_create_cb, 249 flow_dv_sample_match_cb, 250 flow_dv_sample_remove_cb); 251 /* Init dest array action cache list. */ 252 snprintf(s, sizeof(s), "%s_dest_array_cache", sh->ibdev_name); 253 mlx5_cache_list_init(&sh->dest_array_list, s, 0, sh, 254 flow_dv_dest_array_create_cb, 255 flow_dv_dest_array_match_cb, 256 flow_dv_dest_array_remove_cb); 257 /* Create tags hash list table. */ 258 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 259 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0, 260 MLX5_HLIST_WRITE_MOST, 261 flow_dv_tag_create_cb, 262 flow_dv_tag_match_cb, 263 flow_dv_tag_remove_cb); 264 if (!sh->tag_table) { 265 DRV_LOG(ERR, "tags with hash creation failed."); 266 err = ENOMEM; 267 goto error; 268 } 269 sh->tag_table->ctx = sh; 270 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 271 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ, 272 0, MLX5_HLIST_WRITE_MOST | 273 MLX5_HLIST_DIRECT_KEY, 274 flow_dv_modify_create_cb, 275 flow_dv_modify_match_cb, 276 flow_dv_modify_remove_cb); 277 if (!sh->modify_cmds) { 278 DRV_LOG(ERR, "hdr modify hash creation failed"); 279 err = ENOMEM; 280 goto error; 281 } 282 sh->modify_cmds->ctx = sh; 283 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 284 sh->encaps_decaps = mlx5_hlist_create(s, 285 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ, 286 0, MLX5_HLIST_DIRECT_KEY | 287 MLX5_HLIST_WRITE_MOST, 288 flow_dv_encap_decap_create_cb, 289 flow_dv_encap_decap_match_cb, 290 flow_dv_encap_decap_remove_cb); 291 if (!sh->encaps_decaps) { 292 DRV_LOG(ERR, "encap decap hash creation failed"); 293 err = ENOMEM; 294 goto error; 295 } 296 sh->encaps_decaps->ctx = sh; 297 #endif 298 #ifdef HAVE_MLX5DV_DR 299 void *domain; 300 301 /* Reference counter is zero, we should initialize structures. */ 302 domain = mlx5_glue->dr_create_domain(sh->ctx, 303 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 304 if (!domain) { 305 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 306 err = errno; 307 goto error; 308 } 309 sh->rx_domain = domain; 310 domain = mlx5_glue->dr_create_domain(sh->ctx, 311 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 312 if (!domain) { 313 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 314 err = errno; 315 goto error; 316 } 317 sh->tx_domain = domain; 318 #ifdef HAVE_MLX5DV_DR_ESWITCH 319 if (priv->config.dv_esw_en) { 320 domain = mlx5_glue->dr_create_domain 321 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 322 if (!domain) { 323 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 324 err = errno; 325 goto error; 326 } 327 sh->fdb_domain = domain; 328 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 329 } 330 #endif 331 if (!sh->tunnel_hub) 332 err = mlx5_alloc_tunnel_hub(sh); 333 if (err) { 334 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 335 goto error; 336 } 337 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 338 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 339 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 340 if (sh->fdb_domain) 341 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 342 } 343 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 344 #endif /* HAVE_MLX5DV_DR */ 345 sh->default_miss_action = 346 mlx5_glue->dr_create_flow_action_default_miss(); 347 if (!sh->default_miss_action) 348 DRV_LOG(WARNING, "Default miss action is not supported."); 349 return 0; 350 error: 351 /* Rollback the created objects. */ 352 if (sh->rx_domain) { 353 mlx5_glue->dr_destroy_domain(sh->rx_domain); 354 sh->rx_domain = NULL; 355 } 356 if (sh->tx_domain) { 357 mlx5_glue->dr_destroy_domain(sh->tx_domain); 358 sh->tx_domain = NULL; 359 } 360 if (sh->fdb_domain) { 361 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 362 sh->fdb_domain = NULL; 363 } 364 if (sh->esw_drop_action) { 365 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 366 sh->esw_drop_action = NULL; 367 } 368 if (sh->pop_vlan_action) { 369 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 370 sh->pop_vlan_action = NULL; 371 } 372 if (sh->encaps_decaps) { 373 mlx5_hlist_destroy(sh->encaps_decaps); 374 sh->encaps_decaps = NULL; 375 } 376 if (sh->modify_cmds) { 377 mlx5_hlist_destroy(sh->modify_cmds); 378 sh->modify_cmds = NULL; 379 } 380 if (sh->tag_table) { 381 /* tags should be destroyed with flow before. */ 382 mlx5_hlist_destroy(sh->tag_table); 383 sh->tag_table = NULL; 384 } 385 if (sh->tunnel_hub) { 386 mlx5_release_tunnel_hub(sh, priv->dev_port); 387 sh->tunnel_hub = NULL; 388 } 389 mlx5_free_table_hash_list(priv); 390 return err; 391 } 392 393 /** 394 * Destroy DR related data within private structure. 395 * 396 * @param[in] priv 397 * Pointer to the private device data structure. 398 */ 399 void 400 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 401 { 402 struct mlx5_dev_ctx_shared *sh = priv->sh; 403 404 MLX5_ASSERT(sh && sh->refcnt); 405 if (sh->refcnt > 1) 406 return; 407 #ifdef HAVE_MLX5DV_DR 408 if (sh->rx_domain) { 409 mlx5_glue->dr_destroy_domain(sh->rx_domain); 410 sh->rx_domain = NULL; 411 } 412 if (sh->tx_domain) { 413 mlx5_glue->dr_destroy_domain(sh->tx_domain); 414 sh->tx_domain = NULL; 415 } 416 #ifdef HAVE_MLX5DV_DR_ESWITCH 417 if (sh->fdb_domain) { 418 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 419 sh->fdb_domain = NULL; 420 } 421 if (sh->esw_drop_action) { 422 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 423 sh->esw_drop_action = NULL; 424 } 425 #endif 426 if (sh->pop_vlan_action) { 427 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 428 sh->pop_vlan_action = NULL; 429 } 430 #endif /* HAVE_MLX5DV_DR */ 431 if (sh->default_miss_action) 432 mlx5_glue->destroy_flow_action 433 (sh->default_miss_action); 434 if (sh->encaps_decaps) { 435 mlx5_hlist_destroy(sh->encaps_decaps); 436 sh->encaps_decaps = NULL; 437 } 438 if (sh->modify_cmds) { 439 mlx5_hlist_destroy(sh->modify_cmds); 440 sh->modify_cmds = NULL; 441 } 442 if (sh->tag_table) { 443 /* tags should be destroyed with flow before. */ 444 mlx5_hlist_destroy(sh->tag_table); 445 sh->tag_table = NULL; 446 } 447 if (sh->tunnel_hub) { 448 mlx5_release_tunnel_hub(sh, priv->dev_port); 449 sh->tunnel_hub = NULL; 450 } 451 mlx5_cache_list_destroy(&sh->port_id_action_list); 452 mlx5_cache_list_destroy(&sh->push_vlan_action_list); 453 mlx5_free_table_hash_list(priv); 454 } 455 456 /** 457 * Initialize shared data between primary and secondary process. 458 * 459 * A memzone is reserved by primary process and secondary processes attach to 460 * the memzone. 461 * 462 * @return 463 * 0 on success, a negative errno value otherwise and rte_errno is set. 464 */ 465 static int 466 mlx5_init_shared_data(void) 467 { 468 const struct rte_memzone *mz; 469 int ret = 0; 470 471 rte_spinlock_lock(&mlx5_shared_data_lock); 472 if (mlx5_shared_data == NULL) { 473 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 474 /* Allocate shared memory. */ 475 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 476 sizeof(*mlx5_shared_data), 477 SOCKET_ID_ANY, 0); 478 if (mz == NULL) { 479 DRV_LOG(ERR, 480 "Cannot allocate mlx5 shared data"); 481 ret = -rte_errno; 482 goto error; 483 } 484 mlx5_shared_data = mz->addr; 485 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 486 rte_spinlock_init(&mlx5_shared_data->lock); 487 } else { 488 /* Lookup allocated shared memory. */ 489 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 490 if (mz == NULL) { 491 DRV_LOG(ERR, 492 "Cannot attach mlx5 shared data"); 493 ret = -rte_errno; 494 goto error; 495 } 496 mlx5_shared_data = mz->addr; 497 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 498 } 499 } 500 error: 501 rte_spinlock_unlock(&mlx5_shared_data_lock); 502 return ret; 503 } 504 505 /** 506 * PMD global initialization. 507 * 508 * Independent from individual device, this function initializes global 509 * per-PMD data structures distinguishing primary and secondary processes. 510 * Hence, each initialization is called once per a process. 511 * 512 * @return 513 * 0 on success, a negative errno value otherwise and rte_errno is set. 514 */ 515 static int 516 mlx5_init_once(void) 517 { 518 struct mlx5_shared_data *sd; 519 struct mlx5_local_data *ld = &mlx5_local_data; 520 int ret = 0; 521 522 if (mlx5_init_shared_data()) 523 return -rte_errno; 524 sd = mlx5_shared_data; 525 MLX5_ASSERT(sd); 526 rte_spinlock_lock(&sd->lock); 527 switch (rte_eal_process_type()) { 528 case RTE_PROC_PRIMARY: 529 if (sd->init_done) 530 break; 531 LIST_INIT(&sd->mem_event_cb_list); 532 rte_rwlock_init(&sd->mem_event_rwlock); 533 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 534 mlx5_mr_mem_event_cb, NULL); 535 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 536 mlx5_mp_os_primary_handle); 537 if (ret) 538 goto out; 539 sd->init_done = true; 540 break; 541 case RTE_PROC_SECONDARY: 542 if (ld->init_done) 543 break; 544 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 545 mlx5_mp_os_secondary_handle); 546 if (ret) 547 goto out; 548 ++sd->secondary_cnt; 549 ld->init_done = true; 550 break; 551 default: 552 break; 553 } 554 out: 555 rte_spinlock_unlock(&sd->lock); 556 return ret; 557 } 558 559 /** 560 * Create the Tx queue DevX/Verbs object. 561 * 562 * @param dev 563 * Pointer to Ethernet device. 564 * @param idx 565 * Queue index in DPDK Tx queue array. 566 * 567 * @return 568 * 0 on success, a negative errno value otherwise and rte_errno is set. 569 */ 570 static int 571 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 572 { 573 struct mlx5_priv *priv = dev->data->dev_private; 574 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 575 struct mlx5_txq_ctrl *txq_ctrl = 576 container_of(txq_data, struct mlx5_txq_ctrl, txq); 577 578 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 579 return mlx5_txq_devx_obj_new(dev, idx); 580 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 581 if (!priv->config.dv_esw_en) 582 return mlx5_txq_devx_obj_new(dev, idx); 583 #endif 584 return mlx5_txq_ibv_obj_new(dev, idx); 585 } 586 587 /** 588 * Release an Tx DevX/verbs queue object. 589 * 590 * @param txq_obj 591 * DevX/Verbs Tx queue object. 592 */ 593 static void 594 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 595 { 596 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 597 mlx5_txq_devx_obj_release(txq_obj); 598 return; 599 } 600 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 601 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 602 mlx5_txq_devx_obj_release(txq_obj); 603 return; 604 } 605 #endif 606 mlx5_txq_ibv_obj_release(txq_obj); 607 } 608 609 /** 610 * DV flow counter mode detect and config. 611 * 612 * @param dev 613 * Pointer to rte_eth_dev structure. 614 * 615 */ 616 static void 617 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 618 { 619 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 620 struct mlx5_priv *priv = dev->data->dev_private; 621 struct mlx5_dev_ctx_shared *sh = priv->sh; 622 bool fallback; 623 624 #ifndef HAVE_IBV_DEVX_ASYNC 625 fallback = true; 626 #else 627 fallback = false; 628 if (!priv->config.devx || !priv->config.dv_flow_en || 629 !priv->config.hca_attr.flow_counters_dump || 630 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 631 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 632 fallback = true; 633 #endif 634 if (fallback) 635 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 636 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 637 priv->config.hca_attr.flow_counters_dump, 638 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 639 /* Initialize fallback mode only on the port initializes sh. */ 640 if (sh->refcnt == 1) 641 sh->cmng.counter_fallback = fallback; 642 else if (fallback != sh->cmng.counter_fallback) 643 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 644 "with others:%d.", PORT_ID(priv), fallback); 645 #endif 646 } 647 648 /** 649 * Spawn an Ethernet device from Verbs information. 650 * 651 * @param dpdk_dev 652 * Backing DPDK device. 653 * @param spawn 654 * Verbs device parameters (name, port, switch_info) to spawn. 655 * @param config 656 * Device configuration parameters. 657 * 658 * @return 659 * A valid Ethernet device object on success, NULL otherwise and rte_errno 660 * is set. The following errors are defined: 661 * 662 * EBUSY: device is not supposed to be spawned. 663 * EEXIST: device is already spawned 664 */ 665 static struct rte_eth_dev * 666 mlx5_dev_spawn(struct rte_device *dpdk_dev, 667 struct mlx5_dev_spawn_data *spawn, 668 struct mlx5_dev_config *config) 669 { 670 const struct mlx5_switch_info *switch_info = &spawn->info; 671 struct mlx5_dev_ctx_shared *sh = NULL; 672 struct ibv_port_attr port_attr; 673 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 674 struct rte_eth_dev *eth_dev = NULL; 675 struct mlx5_priv *priv = NULL; 676 int err = 0; 677 unsigned int hw_padding = 0; 678 unsigned int mps; 679 unsigned int cqe_comp; 680 unsigned int cqe_pad = 0; 681 unsigned int tunnel_en = 0; 682 unsigned int mpls_en = 0; 683 unsigned int swp = 0; 684 unsigned int mprq = 0; 685 unsigned int mprq_min_stride_size_n = 0; 686 unsigned int mprq_max_stride_size_n = 0; 687 unsigned int mprq_min_stride_num_n = 0; 688 unsigned int mprq_max_stride_num_n = 0; 689 struct rte_ether_addr mac; 690 char name[RTE_ETH_NAME_MAX_LEN]; 691 int own_domain_id = 0; 692 uint16_t port_id; 693 unsigned int i; 694 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 695 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 696 #endif 697 698 /* Determine if this port representor is supposed to be spawned. */ 699 if (switch_info->representor && dpdk_dev->devargs) { 700 struct rte_eth_devargs eth_da; 701 702 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 703 if (err) { 704 rte_errno = -err; 705 DRV_LOG(ERR, "failed to process device arguments: %s", 706 strerror(rte_errno)); 707 return NULL; 708 } 709 for (i = 0; i < eth_da.nb_representor_ports; ++i) 710 if (eth_da.representor_ports[i] == 711 (uint16_t)switch_info->port_name) 712 break; 713 if (i == eth_da.nb_representor_ports) { 714 rte_errno = EBUSY; 715 return NULL; 716 } 717 } 718 /* Build device name. */ 719 if (spawn->pf_bond < 0) { 720 /* Single device. */ 721 if (!switch_info->representor) 722 strlcpy(name, dpdk_dev->name, sizeof(name)); 723 else 724 snprintf(name, sizeof(name), "%s_representor_%u", 725 dpdk_dev->name, switch_info->port_name); 726 } else { 727 /* Bonding device. */ 728 if (!switch_info->representor) 729 snprintf(name, sizeof(name), "%s_%s", 730 dpdk_dev->name, 731 mlx5_os_get_dev_device_name(spawn->phys_dev)); 732 else 733 snprintf(name, sizeof(name), "%s_%s_representor_%u", 734 dpdk_dev->name, 735 mlx5_os_get_dev_device_name(spawn->phys_dev), 736 switch_info->port_name); 737 } 738 /* check if the device is already spawned */ 739 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 740 rte_errno = EEXIST; 741 return NULL; 742 } 743 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 744 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 745 struct mlx5_mp_id mp_id; 746 747 eth_dev = rte_eth_dev_attach_secondary(name); 748 if (eth_dev == NULL) { 749 DRV_LOG(ERR, "can not attach rte ethdev"); 750 rte_errno = ENOMEM; 751 return NULL; 752 } 753 priv = eth_dev->data->dev_private; 754 if (priv->sh->bond_dev != UINT16_MAX) 755 /* For bonding port, use primary PCI device. */ 756 eth_dev->device = 757 rte_eth_devices[priv->sh->bond_dev].device; 758 else 759 eth_dev->device = dpdk_dev; 760 eth_dev->dev_ops = &mlx5_os_dev_sec_ops; 761 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 762 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 763 err = mlx5_proc_priv_init(eth_dev); 764 if (err) 765 return NULL; 766 mp_id.port_id = eth_dev->data->port_id; 767 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 768 /* Receive command fd from primary process */ 769 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 770 if (err < 0) 771 goto err_secondary; 772 /* Remap UAR for Tx queues. */ 773 err = mlx5_tx_uar_init_secondary(eth_dev, err); 774 if (err) 775 goto err_secondary; 776 /* 777 * Ethdev pointer is still required as input since 778 * the primary device is not accessible from the 779 * secondary process. 780 */ 781 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 782 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 783 return eth_dev; 784 err_secondary: 785 mlx5_dev_close(eth_dev); 786 return NULL; 787 } 788 /* 789 * Some parameters ("tx_db_nc" in particularly) are needed in 790 * advance to create dv/verbs device context. We proceed the 791 * devargs here to get ones, and later proceed devargs again 792 * to override some hardware settings. 793 */ 794 err = mlx5_args(config, dpdk_dev->devargs); 795 if (err) { 796 err = rte_errno; 797 DRV_LOG(ERR, "failed to process device arguments: %s", 798 strerror(rte_errno)); 799 goto error; 800 } 801 if (config->dv_miss_info) { 802 if (switch_info->master || switch_info->representor) 803 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 804 } 805 mlx5_malloc_mem_select(config->sys_mem_en); 806 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 807 if (!sh) 808 return NULL; 809 config->devx = sh->devx; 810 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 811 config->dest_tir = 1; 812 #endif 813 #ifdef HAVE_IBV_MLX5_MOD_SWP 814 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 815 #endif 816 /* 817 * Multi-packet send is supported by ConnectX-4 Lx PF as well 818 * as all ConnectX-5 devices. 819 */ 820 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 821 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 822 #endif 823 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 824 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 825 #endif 826 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 827 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 828 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 829 DRV_LOG(DEBUG, "enhanced MPW is supported"); 830 mps = MLX5_MPW_ENHANCED; 831 } else { 832 DRV_LOG(DEBUG, "MPW is supported"); 833 mps = MLX5_MPW; 834 } 835 } else { 836 DRV_LOG(DEBUG, "MPW isn't supported"); 837 mps = MLX5_MPW_DISABLED; 838 } 839 #ifdef HAVE_IBV_MLX5_MOD_SWP 840 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 841 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 842 DRV_LOG(DEBUG, "SWP support: %u", swp); 843 #endif 844 config->swp = !!swp; 845 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 846 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 847 struct mlx5dv_striding_rq_caps mprq_caps = 848 dv_attr.striding_rq_caps; 849 850 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 851 mprq_caps.min_single_stride_log_num_of_bytes); 852 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 853 mprq_caps.max_single_stride_log_num_of_bytes); 854 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 855 mprq_caps.min_single_wqe_log_num_of_strides); 856 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 857 mprq_caps.max_single_wqe_log_num_of_strides); 858 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 859 mprq_caps.supported_qpts); 860 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 861 mprq = 1; 862 mprq_min_stride_size_n = 863 mprq_caps.min_single_stride_log_num_of_bytes; 864 mprq_max_stride_size_n = 865 mprq_caps.max_single_stride_log_num_of_bytes; 866 mprq_min_stride_num_n = 867 mprq_caps.min_single_wqe_log_num_of_strides; 868 mprq_max_stride_num_n = 869 mprq_caps.max_single_wqe_log_num_of_strides; 870 } 871 #endif 872 if (RTE_CACHE_LINE_SIZE == 128 && 873 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 874 cqe_comp = 0; 875 else 876 cqe_comp = 1; 877 config->cqe_comp = cqe_comp; 878 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 879 /* Whether device supports 128B Rx CQE padding. */ 880 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 881 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 882 #endif 883 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 884 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 885 tunnel_en = ((dv_attr.tunnel_offloads_caps & 886 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 887 (dv_attr.tunnel_offloads_caps & 888 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 889 (dv_attr.tunnel_offloads_caps & 890 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 891 } 892 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 893 tunnel_en ? "" : "not "); 894 #else 895 DRV_LOG(WARNING, 896 "tunnel offloading disabled due to old OFED/rdma-core version"); 897 #endif 898 config->tunnel_en = tunnel_en; 899 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 900 mpls_en = ((dv_attr.tunnel_offloads_caps & 901 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 902 (dv_attr.tunnel_offloads_caps & 903 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 904 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 905 mpls_en ? "" : "not "); 906 #else 907 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 908 " old OFED/rdma-core version or firmware configuration"); 909 #endif 910 config->mpls_en = mpls_en; 911 /* Check port status. */ 912 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 913 if (err) { 914 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 915 goto error; 916 } 917 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 918 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 919 err = EINVAL; 920 goto error; 921 } 922 if (port_attr.state != IBV_PORT_ACTIVE) 923 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 924 mlx5_glue->port_state_str(port_attr.state), 925 port_attr.state); 926 /* Allocate private eth device data. */ 927 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 928 sizeof(*priv), 929 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 930 if (priv == NULL) { 931 DRV_LOG(ERR, "priv allocation failure"); 932 err = ENOMEM; 933 goto error; 934 } 935 priv->sh = sh; 936 priv->dev_port = spawn->phys_port; 937 priv->pci_dev = spawn->pci_dev; 938 priv->mtu = RTE_ETHER_MTU; 939 priv->mp_id.port_id = port_id; 940 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 941 /* Some internal functions rely on Netlink sockets, open them now. */ 942 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 943 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 944 priv->representor = !!switch_info->representor; 945 priv->master = !!switch_info->master; 946 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 947 priv->vport_meta_tag = 0; 948 priv->vport_meta_mask = 0; 949 priv->pf_bond = spawn->pf_bond; 950 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 951 /* 952 * The DevX port query API is implemented. E-Switch may use 953 * either vport or reg_c[0] metadata register to match on 954 * vport index. The engaged part of metadata register is 955 * defined by mask. 956 */ 957 if (switch_info->representor || switch_info->master) { 958 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 959 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 960 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 961 &devx_port); 962 if (err) { 963 DRV_LOG(WARNING, 964 "can't query devx port %d on device %s", 965 spawn->phys_port, 966 mlx5_os_get_dev_device_name(spawn->phys_dev)); 967 devx_port.comp_mask = 0; 968 } 969 } 970 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 971 priv->vport_meta_tag = devx_port.reg_c_0.value; 972 priv->vport_meta_mask = devx_port.reg_c_0.mask; 973 if (!priv->vport_meta_mask) { 974 DRV_LOG(ERR, "vport zero mask for port %d" 975 " on bonding device %s", 976 spawn->phys_port, 977 mlx5_os_get_dev_device_name 978 (spawn->phys_dev)); 979 err = ENOTSUP; 980 goto error; 981 } 982 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 983 DRV_LOG(ERR, "invalid vport tag for port %d" 984 " on bonding device %s", 985 spawn->phys_port, 986 mlx5_os_get_dev_device_name 987 (spawn->phys_dev)); 988 err = ENOTSUP; 989 goto error; 990 } 991 } 992 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 993 priv->vport_id = devx_port.vport_num; 994 } else if (spawn->pf_bond >= 0) { 995 DRV_LOG(ERR, "can't deduce vport index for port %d" 996 " on bonding device %s", 997 spawn->phys_port, 998 mlx5_os_get_dev_device_name(spawn->phys_dev)); 999 err = ENOTSUP; 1000 goto error; 1001 } else { 1002 /* Suppose vport index in compatible way. */ 1003 priv->vport_id = switch_info->representor ? 1004 switch_info->port_name + 1 : -1; 1005 } 1006 #else 1007 /* 1008 * Kernel/rdma_core support single E-Switch per PF configurations 1009 * only and vport_id field contains the vport index for 1010 * associated VF, which is deduced from representor port name. 1011 * For example, let's have the IB device port 10, it has 1012 * attached network device eth0, which has port name attribute 1013 * pf0vf2, we can deduce the VF number as 2, and set vport index 1014 * as 3 (2+1). This assigning schema should be changed if the 1015 * multiple E-Switch instances per PF configurations or/and PCI 1016 * subfunctions are added. 1017 */ 1018 priv->vport_id = switch_info->representor ? 1019 switch_info->port_name + 1 : -1; 1020 #endif 1021 /* representor_id field keeps the unmodified VF index. */ 1022 priv->representor_id = switch_info->representor ? 1023 switch_info->port_name : -1; 1024 /* 1025 * Look for sibling devices in order to reuse their switch domain 1026 * if any, otherwise allocate one. 1027 */ 1028 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1029 const struct mlx5_priv *opriv = 1030 rte_eth_devices[port_id].data->dev_private; 1031 1032 if (!opriv || 1033 opriv->sh != priv->sh || 1034 opriv->domain_id == 1035 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1036 continue; 1037 priv->domain_id = opriv->domain_id; 1038 break; 1039 } 1040 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1041 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1042 if (err) { 1043 err = rte_errno; 1044 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1045 strerror(rte_errno)); 1046 goto error; 1047 } 1048 own_domain_id = 1; 1049 } 1050 /* Override some values set by hardware configuration. */ 1051 mlx5_args(config, dpdk_dev->devargs); 1052 err = mlx5_dev_check_sibling_config(priv, config); 1053 if (err) 1054 goto error; 1055 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1056 IBV_DEVICE_RAW_IP_CSUM); 1057 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1058 (config->hw_csum ? "" : "not ")); 1059 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1060 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1061 DRV_LOG(DEBUG, "counters are not supported"); 1062 #endif 1063 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1064 if (config->dv_flow_en) { 1065 DRV_LOG(WARNING, "DV flow is not supported"); 1066 config->dv_flow_en = 0; 1067 } 1068 #endif 1069 config->ind_table_max_size = 1070 sh->device_attr.max_rwq_indirection_table_size; 1071 /* 1072 * Remove this check once DPDK supports larger/variable 1073 * indirection tables. 1074 */ 1075 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1076 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1077 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1078 config->ind_table_max_size); 1079 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1080 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1081 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1082 (config->hw_vlan_strip ? "" : "not ")); 1083 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1084 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1085 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1086 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1087 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1088 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1089 IBV_DEVICE_PCI_WRITE_END_PADDING); 1090 #endif 1091 if (config->hw_padding && !hw_padding) { 1092 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1093 config->hw_padding = 0; 1094 } else if (config->hw_padding) { 1095 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1096 } 1097 config->tso = (sh->device_attr.max_tso > 0 && 1098 (sh->device_attr.tso_supported_qpts & 1099 (1 << IBV_QPT_RAW_PACKET))); 1100 if (config->tso) 1101 config->tso_max_payload_sz = sh->device_attr.max_tso; 1102 /* 1103 * MPW is disabled by default, while the Enhanced MPW is enabled 1104 * by default. 1105 */ 1106 if (config->mps == MLX5_ARG_UNSET) 1107 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1108 MLX5_MPW_DISABLED; 1109 else 1110 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1111 DRV_LOG(INFO, "%sMPS is %s", 1112 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1113 config->mps == MLX5_MPW ? "legacy " : "", 1114 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1115 if (config->cqe_comp && !cqe_comp) { 1116 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1117 config->cqe_comp = 0; 1118 } 1119 if (config->cqe_pad && !cqe_pad) { 1120 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1121 config->cqe_pad = 0; 1122 } else if (config->cqe_pad) { 1123 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1124 } 1125 if (config->devx) { 1126 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1127 if (err) { 1128 err = -err; 1129 goto error; 1130 } 1131 /* Check relax ordering support. */ 1132 if (!haswell_broadwell_cpu) { 1133 sh->cmng.relaxed_ordering_write = 1134 config->hca_attr.relaxed_ordering_write; 1135 sh->cmng.relaxed_ordering_read = 1136 config->hca_attr.relaxed_ordering_read; 1137 } else { 1138 sh->cmng.relaxed_ordering_read = 0; 1139 sh->cmng.relaxed_ordering_write = 0; 1140 } 1141 /* Check for LRO support. */ 1142 if (config->dest_tir && config->hca_attr.lro_cap && 1143 config->dv_flow_en) { 1144 /* TBD check tunnel lro caps. */ 1145 config->lro.supported = config->hca_attr.lro_cap; 1146 DRV_LOG(DEBUG, "Device supports LRO"); 1147 /* 1148 * If LRO timeout is not configured by application, 1149 * use the minimal supported value. 1150 */ 1151 if (!config->lro.timeout) 1152 config->lro.timeout = 1153 config->hca_attr.lro_timer_supported_periods[0]; 1154 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1155 config->lro.timeout); 1156 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1157 "required for coalescing is %d bytes", 1158 config->hca_attr.lro_min_mss_size); 1159 } 1160 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1161 if (config->hca_attr.qos.sup && 1162 config->hca_attr.qos.srtcm_sup && 1163 config->dv_flow_en) { 1164 uint8_t reg_c_mask = 1165 config->hca_attr.qos.flow_meter_reg_c_ids; 1166 /* 1167 * Meter needs two REG_C's for color match and pre-sfx 1168 * flow match. Here get the REG_C for color match. 1169 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1170 */ 1171 reg_c_mask &= 0xfc; 1172 if (__builtin_popcount(reg_c_mask) < 1) { 1173 priv->mtr_en = 0; 1174 DRV_LOG(WARNING, "No available register for" 1175 " meter."); 1176 } else { 1177 /* 1178 * The meter color register is used by the 1179 * flow-hit feature as well. 1180 * The flow-hit feature must use REG_C_3 1181 * Prefer REG_C_3 if it is available. 1182 */ 1183 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1184 priv->mtr_color_reg = REG_C_3; 1185 else 1186 priv->mtr_color_reg = ffs(reg_c_mask) 1187 - 1 + REG_C_0; 1188 priv->mtr_en = 1; 1189 priv->mtr_reg_share = 1190 config->hca_attr.qos.flow_meter_reg_share; 1191 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1192 priv->mtr_color_reg); 1193 } 1194 } 1195 #endif 1196 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1197 if (config->hca_attr.flow_hit_aso && 1198 priv->mtr_color_reg == REG_C_3) { 1199 sh->flow_hit_aso_en = 1; 1200 err = mlx5_flow_aso_age_mng_init(sh); 1201 if (err) { 1202 err = -err; 1203 goto error; 1204 } 1205 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1206 } 1207 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1208 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1209 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1210 config->dv_flow_en) { 1211 priv->sampler_en = 1; 1212 DRV_LOG(DEBUG, "The Sampler enabled!\n"); 1213 } else { 1214 priv->sampler_en = 0; 1215 if (!config->hca_attr.log_max_ft_sampler_num) 1216 DRV_LOG(WARNING, "No available register for" 1217 " Sampler."); 1218 else 1219 DRV_LOG(DEBUG, "DV flow is not supported!\n"); 1220 } 1221 #endif 1222 } 1223 if (config->tx_pp) { 1224 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1225 config->hca_attr.dev_freq_khz); 1226 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1227 config->hca_attr.qos.packet_pacing ? "" : "not "); 1228 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1229 config->hca_attr.cross_channel ? "" : "not "); 1230 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1231 config->hca_attr.wqe_index_ignore ? "" : "not "); 1232 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1233 config->hca_attr.non_wire_sq ? "" : "not "); 1234 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1235 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1236 config->hca_attr.log_max_static_sq_wq); 1237 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1238 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1239 if (!config->devx) { 1240 DRV_LOG(ERR, "DevX is required for packet pacing"); 1241 err = ENODEV; 1242 goto error; 1243 } 1244 if (!config->hca_attr.qos.packet_pacing) { 1245 DRV_LOG(ERR, "Packet pacing is not supported"); 1246 err = ENODEV; 1247 goto error; 1248 } 1249 if (!config->hca_attr.cross_channel) { 1250 DRV_LOG(ERR, "Cross channel operations are" 1251 " required for packet pacing"); 1252 err = ENODEV; 1253 goto error; 1254 } 1255 if (!config->hca_attr.wqe_index_ignore) { 1256 DRV_LOG(ERR, "WQE index ignore feature is" 1257 " required for packet pacing"); 1258 err = ENODEV; 1259 goto error; 1260 } 1261 if (!config->hca_attr.non_wire_sq) { 1262 DRV_LOG(ERR, "Non-wire SQ feature is" 1263 " required for packet pacing"); 1264 err = ENODEV; 1265 goto error; 1266 } 1267 if (!config->hca_attr.log_max_static_sq_wq) { 1268 DRV_LOG(ERR, "Static WQE SQ feature is" 1269 " required for packet pacing"); 1270 err = ENODEV; 1271 goto error; 1272 } 1273 if (!config->hca_attr.qos.wqe_rate_pp) { 1274 DRV_LOG(ERR, "WQE rate mode is required" 1275 " for packet pacing"); 1276 err = ENODEV; 1277 goto error; 1278 } 1279 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1280 DRV_LOG(ERR, "DevX does not provide UAR offset," 1281 " can't create queues for packet pacing"); 1282 err = ENODEV; 1283 goto error; 1284 #endif 1285 } 1286 if (config->devx) { 1287 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1288 1289 err = config->hca_attr.access_register_user ? 1290 mlx5_devx_cmd_register_read 1291 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1292 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1293 if (!err) { 1294 uint32_t ts_mode; 1295 1296 /* MTUTC register is read successfully. */ 1297 ts_mode = MLX5_GET(register_mtutc, reg, 1298 time_stamp_mode); 1299 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1300 config->rt_timestamp = 1; 1301 } else { 1302 /* Kernel does not support register reading. */ 1303 if (config->hca_attr.dev_freq_khz == 1304 (NS_PER_S / MS_PER_S)) 1305 config->rt_timestamp = 1; 1306 } 1307 } 1308 /* 1309 * If HW has bug working with tunnel packet decapsulation and 1310 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1311 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1312 */ 1313 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1314 config->hw_fcs_strip = 0; 1315 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1316 (config->hw_fcs_strip ? "" : "not ")); 1317 if (config->mprq.enabled && mprq) { 1318 if (config->mprq.stride_num_n && 1319 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1320 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1321 config->mprq.stride_num_n = 1322 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1323 mprq_min_stride_num_n), 1324 mprq_max_stride_num_n); 1325 DRV_LOG(WARNING, 1326 "the number of strides" 1327 " for Multi-Packet RQ is out of range," 1328 " setting default value (%u)", 1329 1 << config->mprq.stride_num_n); 1330 } 1331 if (config->mprq.stride_size_n && 1332 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1333 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1334 config->mprq.stride_size_n = 1335 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1336 mprq_min_stride_size_n), 1337 mprq_max_stride_size_n); 1338 DRV_LOG(WARNING, 1339 "the size of a stride" 1340 " for Multi-Packet RQ is out of range," 1341 " setting default value (%u)", 1342 1 << config->mprq.stride_size_n); 1343 } 1344 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1345 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1346 } else if (config->mprq.enabled && !mprq) { 1347 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1348 config->mprq.enabled = 0; 1349 } 1350 if (config->max_dump_files_num == 0) 1351 config->max_dump_files_num = 128; 1352 eth_dev = rte_eth_dev_allocate(name); 1353 if (eth_dev == NULL) { 1354 DRV_LOG(ERR, "can not allocate rte ethdev"); 1355 err = ENOMEM; 1356 goto error; 1357 } 1358 if (priv->representor) { 1359 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1360 eth_dev->data->representor_id = priv->representor_id; 1361 } 1362 /* 1363 * Store associated network device interface index. This index 1364 * is permanent throughout the lifetime of device. So, we may store 1365 * the ifindex here and use the cached value further. 1366 */ 1367 MLX5_ASSERT(spawn->ifindex); 1368 priv->if_index = spawn->ifindex; 1369 if (priv->pf_bond >= 0 && priv->master) { 1370 /* Get bond interface info */ 1371 err = mlx5_sysfs_bond_info(priv->if_index, 1372 &priv->bond_ifindex, 1373 priv->bond_name); 1374 if (err) 1375 DRV_LOG(ERR, "unable to get bond info: %s", 1376 strerror(rte_errno)); 1377 else 1378 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1379 priv->if_index, priv->bond_ifindex, 1380 priv->bond_name); 1381 } 1382 eth_dev->data->dev_private = priv; 1383 priv->dev_data = eth_dev->data; 1384 eth_dev->data->mac_addrs = priv->mac; 1385 if (spawn->pf_bond < 0) { 1386 eth_dev->device = dpdk_dev; 1387 } else { 1388 /* Use primary bond PCI as device. */ 1389 if (sh->bond_dev == UINT16_MAX) { 1390 sh->bond_dev = eth_dev->data->port_id; 1391 eth_dev->device = dpdk_dev; 1392 } else { 1393 eth_dev->device = rte_eth_devices[sh->bond_dev].device; 1394 } 1395 } 1396 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1397 /* Configure the first MAC address by default. */ 1398 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1399 DRV_LOG(ERR, 1400 "port %u cannot get MAC address, is mlx5_en" 1401 " loaded? (errno: %s)", 1402 eth_dev->data->port_id, strerror(rte_errno)); 1403 err = ENODEV; 1404 goto error; 1405 } 1406 DRV_LOG(INFO, 1407 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1408 eth_dev->data->port_id, 1409 mac.addr_bytes[0], mac.addr_bytes[1], 1410 mac.addr_bytes[2], mac.addr_bytes[3], 1411 mac.addr_bytes[4], mac.addr_bytes[5]); 1412 #ifdef RTE_LIBRTE_MLX5_DEBUG 1413 { 1414 char ifname[IF_NAMESIZE]; 1415 1416 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1417 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1418 eth_dev->data->port_id, ifname); 1419 else 1420 DRV_LOG(DEBUG, "port %u ifname is unknown", 1421 eth_dev->data->port_id); 1422 } 1423 #endif 1424 /* Get actual MTU if possible. */ 1425 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1426 if (err) { 1427 err = rte_errno; 1428 goto error; 1429 } 1430 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1431 priv->mtu); 1432 /* Initialize burst functions to prevent crashes before link-up. */ 1433 eth_dev->rx_pkt_burst = removed_rx_burst; 1434 eth_dev->tx_pkt_burst = removed_tx_burst; 1435 eth_dev->dev_ops = &mlx5_os_dev_ops; 1436 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1437 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1438 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1439 /* Register MAC address. */ 1440 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1441 if (config->vf && config->vf_nl_en) 1442 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1443 mlx5_ifindex(eth_dev), 1444 eth_dev->data->mac_addrs, 1445 MLX5_MAX_MAC_ADDRESSES); 1446 priv->flows = 0; 1447 priv->ctrl_flows = 0; 1448 rte_spinlock_init(&priv->flow_list_lock); 1449 TAILQ_INIT(&priv->flow_meters); 1450 TAILQ_INIT(&priv->flow_meter_profiles); 1451 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1452 mlx5_glue->dv_set_context_attr(sh->ctx, 1453 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1454 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1455 .alloc = &mlx5_alloc_verbs_buf, 1456 .free = &mlx5_free_verbs_buf, 1457 .data = sh, 1458 })); 1459 /* Bring Ethernet device up. */ 1460 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1461 eth_dev->data->port_id); 1462 mlx5_set_link_up(eth_dev); 1463 /* 1464 * Even though the interrupt handler is not installed yet, 1465 * interrupts will still trigger on the async_fd from 1466 * Verbs context returned by ibv_open_device(). 1467 */ 1468 mlx5_link_update(eth_dev, 0); 1469 #ifdef HAVE_MLX5DV_DR_ESWITCH 1470 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1471 (switch_info->representor || switch_info->master))) 1472 config->dv_esw_en = 0; 1473 #else 1474 config->dv_esw_en = 0; 1475 #endif 1476 /* Detect minimal data bytes to inline. */ 1477 mlx5_set_min_inline(spawn, config); 1478 /* Store device configuration on private structure. */ 1479 priv->config = *config; 1480 /* Create context for virtual machine VLAN workaround. */ 1481 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1482 if (config->dv_flow_en) { 1483 err = mlx5_alloc_shared_dr(priv); 1484 if (err) 1485 goto error; 1486 } 1487 if (config->devx && config->dv_flow_en && config->dest_tir) { 1488 priv->obj_ops = devx_obj_ops; 1489 priv->obj_ops.drop_action_create = 1490 ibv_obj_ops.drop_action_create; 1491 priv->obj_ops.drop_action_destroy = 1492 ibv_obj_ops.drop_action_destroy; 1493 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1494 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1495 #else 1496 if (config->dv_esw_en) 1497 priv->obj_ops.txq_obj_modify = 1498 ibv_obj_ops.txq_obj_modify; 1499 #endif 1500 /* Use specific wrappers for Tx object. */ 1501 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1502 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1503 1504 } else { 1505 priv->obj_ops = ibv_obj_ops; 1506 } 1507 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1508 if (!priv->drop_queue.hrxq) 1509 goto error; 1510 /* Supported Verbs flow priority number detection. */ 1511 err = mlx5_flow_discover_priorities(eth_dev); 1512 if (err < 0) { 1513 err = -err; 1514 goto error; 1515 } 1516 priv->config.flow_prio = err; 1517 if (!priv->config.dv_esw_en && 1518 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1519 DRV_LOG(WARNING, "metadata mode %u is not supported " 1520 "(no E-Switch)", priv->config.dv_xmeta_en); 1521 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1522 } 1523 mlx5_set_metadata_mask(eth_dev); 1524 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1525 !priv->sh->dv_regc0_mask) { 1526 DRV_LOG(ERR, "metadata mode %u is not supported " 1527 "(no metadata reg_c[0] is available)", 1528 priv->config.dv_xmeta_en); 1529 err = ENOTSUP; 1530 goto error; 1531 } 1532 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 1533 mlx5_hrxq_create_cb, 1534 mlx5_hrxq_match_cb, 1535 mlx5_hrxq_remove_cb); 1536 /* Query availability of metadata reg_c's. */ 1537 err = mlx5_flow_discover_mreg_c(eth_dev); 1538 if (err < 0) { 1539 err = -err; 1540 goto error; 1541 } 1542 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1543 DRV_LOG(DEBUG, 1544 "port %u extensive metadata register is not supported", 1545 eth_dev->data->port_id); 1546 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1547 DRV_LOG(ERR, "metadata mode %u is not supported " 1548 "(no metadata registers available)", 1549 priv->config.dv_xmeta_en); 1550 err = ENOTSUP; 1551 goto error; 1552 } 1553 } 1554 if (priv->config.dv_flow_en && 1555 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1556 mlx5_flow_ext_mreg_supported(eth_dev) && 1557 priv->sh->dv_regc0_mask) { 1558 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1559 MLX5_FLOW_MREG_HTABLE_SZ, 1560 0, 0, 1561 flow_dv_mreg_create_cb, 1562 flow_dv_mreg_match_cb, 1563 flow_dv_mreg_remove_cb); 1564 if (!priv->mreg_cp_tbl) { 1565 err = ENOMEM; 1566 goto error; 1567 } 1568 priv->mreg_cp_tbl->ctx = eth_dev; 1569 } 1570 rte_spinlock_init(&priv->shared_act_sl); 1571 mlx5_flow_counter_mode_config(eth_dev); 1572 if (priv->config.dv_flow_en) 1573 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1574 return eth_dev; 1575 error: 1576 if (priv) { 1577 if (priv->mreg_cp_tbl) 1578 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1579 if (priv->sh) 1580 mlx5_os_free_shared_dr(priv); 1581 if (priv->nl_socket_route >= 0) 1582 close(priv->nl_socket_route); 1583 if (priv->nl_socket_rdma >= 0) 1584 close(priv->nl_socket_rdma); 1585 if (priv->vmwa_context) 1586 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1587 if (eth_dev && priv->drop_queue.hrxq) 1588 mlx5_drop_action_destroy(eth_dev); 1589 if (own_domain_id) 1590 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1591 mlx5_cache_list_destroy(&priv->hrxqs); 1592 mlx5_free(priv); 1593 if (eth_dev != NULL) 1594 eth_dev->data->dev_private = NULL; 1595 } 1596 if (eth_dev != NULL) { 1597 /* mac_addrs must not be freed alone because part of 1598 * dev_private 1599 **/ 1600 eth_dev->data->mac_addrs = NULL; 1601 rte_eth_dev_release_port(eth_dev); 1602 } 1603 if (sh) 1604 mlx5_free_shared_dev_ctx(sh); 1605 MLX5_ASSERT(err > 0); 1606 rte_errno = err; 1607 return NULL; 1608 } 1609 1610 /** 1611 * Comparison callback to sort device data. 1612 * 1613 * This is meant to be used with qsort(). 1614 * 1615 * @param a[in] 1616 * Pointer to pointer to first data object. 1617 * @param b[in] 1618 * Pointer to pointer to second data object. 1619 * 1620 * @return 1621 * 0 if both objects are equal, less than 0 if the first argument is less 1622 * than the second, greater than 0 otherwise. 1623 */ 1624 static int 1625 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1626 { 1627 const struct mlx5_switch_info *si_a = 1628 &((const struct mlx5_dev_spawn_data *)a)->info; 1629 const struct mlx5_switch_info *si_b = 1630 &((const struct mlx5_dev_spawn_data *)b)->info; 1631 int ret; 1632 1633 /* Master device first. */ 1634 ret = si_b->master - si_a->master; 1635 if (ret) 1636 return ret; 1637 /* Then representor devices. */ 1638 ret = si_b->representor - si_a->representor; 1639 if (ret) 1640 return ret; 1641 /* Unidentified devices come last in no specific order. */ 1642 if (!si_a->representor) 1643 return 0; 1644 /* Order representors by name. */ 1645 return si_a->port_name - si_b->port_name; 1646 } 1647 1648 /** 1649 * Match PCI information for possible slaves of bonding device. 1650 * 1651 * @param[in] ibv_dev 1652 * Pointer to Infiniband device structure. 1653 * @param[in] pci_dev 1654 * Pointer to PCI device structure to match PCI address. 1655 * @param[in] nl_rdma 1656 * Netlink RDMA group socket handle. 1657 * 1658 * @return 1659 * negative value if no bonding device found, otherwise 1660 * positive index of slave PF in bonding. 1661 */ 1662 static int 1663 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1664 const struct rte_pci_device *pci_dev, 1665 int nl_rdma) 1666 { 1667 char ifname[IF_NAMESIZE + 1]; 1668 unsigned int ifindex; 1669 unsigned int np, i; 1670 FILE *file = NULL; 1671 int pf = -1; 1672 1673 /* 1674 * Try to get master device name. If something goes 1675 * wrong suppose the lack of kernel support and no 1676 * bonding devices. 1677 */ 1678 if (nl_rdma < 0) 1679 return -1; 1680 if (!strstr(ibv_dev->name, "bond")) 1681 return -1; 1682 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1683 if (!np) 1684 return -1; 1685 /* 1686 * The Master device might not be on the predefined 1687 * port (not on port index 1, it is not garanted), 1688 * we have to scan all Infiniband device port and 1689 * find master. 1690 */ 1691 for (i = 1; i <= np; ++i) { 1692 /* Check whether Infiniband port is populated. */ 1693 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1694 if (!ifindex) 1695 continue; 1696 if (!if_indextoname(ifindex, ifname)) 1697 continue; 1698 /* Try to read bonding slave names from sysfs. */ 1699 MKSTR(slaves, 1700 "/sys/class/net/%s/master/bonding/slaves", ifname); 1701 file = fopen(slaves, "r"); 1702 if (file) 1703 break; 1704 } 1705 if (!file) 1706 return -1; 1707 /* Use safe format to check maximal buffer length. */ 1708 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1709 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1710 char tmp_str[IF_NAMESIZE + 32]; 1711 struct rte_pci_addr pci_addr; 1712 struct mlx5_switch_info info; 1713 1714 /* Process slave interface names in the loop. */ 1715 snprintf(tmp_str, sizeof(tmp_str), 1716 "/sys/class/net/%s", ifname); 1717 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1718 DRV_LOG(WARNING, "can not get PCI address" 1719 " for netdev \"%s\"", ifname); 1720 continue; 1721 } 1722 if (pci_dev->addr.domain != pci_addr.domain || 1723 pci_dev->addr.bus != pci_addr.bus || 1724 pci_dev->addr.devid != pci_addr.devid || 1725 pci_dev->addr.function != pci_addr.function) 1726 continue; 1727 /* Slave interface PCI address match found. */ 1728 fclose(file); 1729 snprintf(tmp_str, sizeof(tmp_str), 1730 "/sys/class/net/%s/phys_port_name", ifname); 1731 file = fopen(tmp_str, "rb"); 1732 if (!file) 1733 break; 1734 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1735 if (fscanf(file, "%32s", tmp_str) == 1) 1736 mlx5_translate_port_name(tmp_str, &info); 1737 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 1738 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1739 pf = info.port_name; 1740 break; 1741 } 1742 if (file) 1743 fclose(file); 1744 return pf; 1745 } 1746 1747 /** 1748 * DPDK callback to register a PCI device. 1749 * 1750 * This function spawns Ethernet devices out of a given PCI device. 1751 * 1752 * @param[in] pci_drv 1753 * PCI driver structure (mlx5_driver). 1754 * @param[in] pci_dev 1755 * PCI device information. 1756 * 1757 * @return 1758 * 0 on success, a negative errno value otherwise and rte_errno is set. 1759 */ 1760 int 1761 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1762 struct rte_pci_device *pci_dev) 1763 { 1764 struct ibv_device **ibv_list; 1765 /* 1766 * Number of found IB Devices matching with requested PCI BDF. 1767 * nd != 1 means there are multiple IB devices over the same 1768 * PCI device and we have representors and master. 1769 */ 1770 unsigned int nd = 0; 1771 /* 1772 * Number of found IB device Ports. nd = 1 and np = 1..n means 1773 * we have the single multiport IB device, and there may be 1774 * representors attached to some of found ports. 1775 */ 1776 unsigned int np = 0; 1777 /* 1778 * Number of DPDK ethernet devices to Spawn - either over 1779 * multiple IB devices or multiple ports of single IB device. 1780 * Actually this is the number of iterations to spawn. 1781 */ 1782 unsigned int ns = 0; 1783 /* 1784 * Bonding device 1785 * < 0 - no bonding device (single one) 1786 * >= 0 - bonding device (value is slave PF index) 1787 */ 1788 int bd = -1; 1789 struct mlx5_dev_spawn_data *list = NULL; 1790 struct mlx5_dev_config dev_config; 1791 unsigned int dev_config_vf; 1792 int ret; 1793 1794 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1795 mlx5_pmd_socket_init(); 1796 ret = mlx5_init_once(); 1797 if (ret) { 1798 DRV_LOG(ERR, "unable to init PMD global data: %s", 1799 strerror(rte_errno)); 1800 return -rte_errno; 1801 } 1802 errno = 0; 1803 ibv_list = mlx5_glue->get_device_list(&ret); 1804 if (!ibv_list) { 1805 rte_errno = errno ? errno : ENOSYS; 1806 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1807 return -rte_errno; 1808 } 1809 /* 1810 * First scan the list of all Infiniband devices to find 1811 * matching ones, gathering into the list. 1812 */ 1813 struct ibv_device *ibv_match[ret + 1]; 1814 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1815 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1816 unsigned int i; 1817 1818 while (ret-- > 0) { 1819 struct rte_pci_addr pci_addr; 1820 1821 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1822 bd = mlx5_device_bond_pci_match 1823 (ibv_list[ret], pci_dev, nl_rdma); 1824 if (bd >= 0) { 1825 /* 1826 * Bonding device detected. Only one match is allowed, 1827 * the bonding is supported over multi-port IB device, 1828 * there should be no matches on representor PCI 1829 * functions or non VF LAG bonding devices with 1830 * specified address. 1831 */ 1832 if (nd) { 1833 DRV_LOG(ERR, 1834 "multiple PCI match on bonding device" 1835 "\"%s\" found", ibv_list[ret]->name); 1836 rte_errno = ENOENT; 1837 ret = -rte_errno; 1838 goto exit; 1839 } 1840 DRV_LOG(INFO, "PCI information matches for" 1841 " slave %d bonding device \"%s\"", 1842 bd, ibv_list[ret]->name); 1843 ibv_match[nd++] = ibv_list[ret]; 1844 break; 1845 } 1846 if (mlx5_dev_to_pci_addr 1847 (ibv_list[ret]->ibdev_path, &pci_addr)) 1848 continue; 1849 if (pci_dev->addr.domain != pci_addr.domain || 1850 pci_dev->addr.bus != pci_addr.bus || 1851 pci_dev->addr.devid != pci_addr.devid || 1852 pci_dev->addr.function != pci_addr.function) 1853 continue; 1854 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1855 ibv_list[ret]->name); 1856 ibv_match[nd++] = ibv_list[ret]; 1857 } 1858 ibv_match[nd] = NULL; 1859 if (!nd) { 1860 /* No device matches, just complain and bail out. */ 1861 DRV_LOG(WARNING, 1862 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1863 " are kernel drivers loaded?", 1864 pci_dev->addr.domain, pci_dev->addr.bus, 1865 pci_dev->addr.devid, pci_dev->addr.function); 1866 rte_errno = ENOENT; 1867 ret = -rte_errno; 1868 goto exit; 1869 } 1870 if (nd == 1) { 1871 /* 1872 * Found single matching device may have multiple ports. 1873 * Each port may be representor, we have to check the port 1874 * number and check the representors existence. 1875 */ 1876 if (nl_rdma >= 0) 1877 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1878 if (!np) 1879 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1880 " ports number", ibv_match[0]->name); 1881 if (bd >= 0 && !np) { 1882 DRV_LOG(ERR, "can not get ports" 1883 " for bonding device"); 1884 rte_errno = ENOENT; 1885 ret = -rte_errno; 1886 goto exit; 1887 } 1888 } 1889 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 1890 if (bd >= 0) { 1891 /* 1892 * This may happen if there is VF LAG kernel support and 1893 * application is compiled with older rdma_core library. 1894 */ 1895 DRV_LOG(ERR, 1896 "No kernel/verbs support for VF LAG bonding found."); 1897 rte_errno = ENOTSUP; 1898 ret = -rte_errno; 1899 goto exit; 1900 } 1901 #endif 1902 /* 1903 * Now we can determine the maximal 1904 * amount of devices to be spawned. 1905 */ 1906 list = mlx5_malloc(MLX5_MEM_ZERO, 1907 sizeof(struct mlx5_dev_spawn_data) * 1908 (np ? np : nd), 1909 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1910 if (!list) { 1911 DRV_LOG(ERR, "spawn data array allocation failure"); 1912 rte_errno = ENOMEM; 1913 ret = -rte_errno; 1914 goto exit; 1915 } 1916 if (bd >= 0 || np > 1) { 1917 /* 1918 * Single IB device with multiple ports found, 1919 * it may be E-Switch master device and representors. 1920 * We have to perform identification through the ports. 1921 */ 1922 MLX5_ASSERT(nl_rdma >= 0); 1923 MLX5_ASSERT(ns == 0); 1924 MLX5_ASSERT(nd == 1); 1925 MLX5_ASSERT(np); 1926 for (i = 1; i <= np; ++i) { 1927 list[ns].max_port = np; 1928 list[ns].phys_port = i; 1929 list[ns].phys_dev = ibv_match[0]; 1930 list[ns].eth_dev = NULL; 1931 list[ns].pci_dev = pci_dev; 1932 list[ns].pf_bond = bd; 1933 list[ns].ifindex = mlx5_nl_ifindex 1934 (nl_rdma, 1935 mlx5_os_get_dev_device_name 1936 (list[ns].phys_dev), i); 1937 if (!list[ns].ifindex) { 1938 /* 1939 * No network interface index found for the 1940 * specified port, it means there is no 1941 * representor on this port. It's OK, 1942 * there can be disabled ports, for example 1943 * if sriov_numvfs < sriov_totalvfs. 1944 */ 1945 continue; 1946 } 1947 ret = -1; 1948 if (nl_route >= 0) 1949 ret = mlx5_nl_switch_info 1950 (nl_route, 1951 list[ns].ifindex, 1952 &list[ns].info); 1953 if (ret || (!list[ns].info.representor && 1954 !list[ns].info.master)) { 1955 /* 1956 * We failed to recognize representors with 1957 * Netlink, let's try to perform the task 1958 * with sysfs. 1959 */ 1960 ret = mlx5_sysfs_switch_info 1961 (list[ns].ifindex, 1962 &list[ns].info); 1963 } 1964 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 1965 if (!ret && bd >= 0) { 1966 switch (list[ns].info.name_type) { 1967 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 1968 if (list[ns].info.port_name == bd) 1969 ns++; 1970 break; 1971 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 1972 /* Fallthrough */ 1973 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 1974 if (list[ns].info.pf_num == bd) 1975 ns++; 1976 break; 1977 default: 1978 break; 1979 } 1980 continue; 1981 } 1982 #endif 1983 if (!ret && (list[ns].info.representor ^ 1984 list[ns].info.master)) 1985 ns++; 1986 } 1987 if (!ns) { 1988 DRV_LOG(ERR, 1989 "unable to recognize master/representors" 1990 " on the IB device with multiple ports"); 1991 rte_errno = ENOENT; 1992 ret = -rte_errno; 1993 goto exit; 1994 } 1995 } else { 1996 /* 1997 * The existence of several matching entries (nd > 1) means 1998 * port representors have been instantiated. No existing Verbs 1999 * call nor sysfs entries can tell them apart, this can only 2000 * be done through Netlink calls assuming kernel drivers are 2001 * recent enough to support them. 2002 * 2003 * In the event of identification failure through Netlink, 2004 * try again through sysfs, then: 2005 * 2006 * 1. A single IB device matches (nd == 1) with single 2007 * port (np=0/1) and is not a representor, assume 2008 * no switch support. 2009 * 2010 * 2. Otherwise no safe assumptions can be made; 2011 * complain louder and bail out. 2012 */ 2013 for (i = 0; i != nd; ++i) { 2014 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2015 list[ns].max_port = 1; 2016 list[ns].phys_port = 1; 2017 list[ns].phys_dev = ibv_match[i]; 2018 list[ns].eth_dev = NULL; 2019 list[ns].pci_dev = pci_dev; 2020 list[ns].pf_bond = -1; 2021 list[ns].ifindex = 0; 2022 if (nl_rdma >= 0) 2023 list[ns].ifindex = mlx5_nl_ifindex 2024 (nl_rdma, 2025 mlx5_os_get_dev_device_name 2026 (list[ns].phys_dev), 1); 2027 if (!list[ns].ifindex) { 2028 char ifname[IF_NAMESIZE]; 2029 2030 /* 2031 * Netlink failed, it may happen with old 2032 * ib_core kernel driver (before 4.16). 2033 * We can assume there is old driver because 2034 * here we are processing single ports IB 2035 * devices. Let's try sysfs to retrieve 2036 * the ifindex. The method works for 2037 * master device only. 2038 */ 2039 if (nd > 1) { 2040 /* 2041 * Multiple devices found, assume 2042 * representors, can not distinguish 2043 * master/representor and retrieve 2044 * ifindex via sysfs. 2045 */ 2046 continue; 2047 } 2048 ret = mlx5_get_ifname_sysfs 2049 (ibv_match[i]->ibdev_path, ifname); 2050 if (!ret) 2051 list[ns].ifindex = 2052 if_nametoindex(ifname); 2053 if (!list[ns].ifindex) { 2054 /* 2055 * No network interface index found 2056 * for the specified device, it means 2057 * there it is neither representor 2058 * nor master. 2059 */ 2060 continue; 2061 } 2062 } 2063 ret = -1; 2064 if (nl_route >= 0) 2065 ret = mlx5_nl_switch_info 2066 (nl_route, 2067 list[ns].ifindex, 2068 &list[ns].info); 2069 if (ret || (!list[ns].info.representor && 2070 !list[ns].info.master)) { 2071 /* 2072 * We failed to recognize representors with 2073 * Netlink, let's try to perform the task 2074 * with sysfs. 2075 */ 2076 ret = mlx5_sysfs_switch_info 2077 (list[ns].ifindex, 2078 &list[ns].info); 2079 } 2080 if (!ret && (list[ns].info.representor ^ 2081 list[ns].info.master)) { 2082 ns++; 2083 } else if ((nd == 1) && 2084 !list[ns].info.representor && 2085 !list[ns].info.master) { 2086 /* 2087 * Single IB device with 2088 * one physical port and 2089 * attached network device. 2090 * May be SRIOV is not enabled 2091 * or there is no representors. 2092 */ 2093 DRV_LOG(INFO, "no E-Switch support detected"); 2094 ns++; 2095 break; 2096 } 2097 } 2098 if (!ns) { 2099 DRV_LOG(ERR, 2100 "unable to recognize master/representors" 2101 " on the multiple IB devices"); 2102 rte_errno = ENOENT; 2103 ret = -rte_errno; 2104 goto exit; 2105 } 2106 } 2107 MLX5_ASSERT(ns); 2108 /* 2109 * Sort list to probe devices in natural order for users convenience 2110 * (i.e. master first, then representors from lowest to highest ID). 2111 */ 2112 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2113 /* Device specific configuration. */ 2114 switch (pci_dev->id.device_id) { 2115 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2116 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2117 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2118 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2119 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2120 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2121 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2122 dev_config_vf = 1; 2123 break; 2124 default: 2125 dev_config_vf = 0; 2126 break; 2127 } 2128 for (i = 0; i != ns; ++i) { 2129 uint32_t restore; 2130 2131 /* Default configuration. */ 2132 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2133 dev_config.vf = dev_config_vf; 2134 dev_config.mps = MLX5_ARG_UNSET; 2135 dev_config.dbnc = MLX5_ARG_UNSET; 2136 dev_config.rx_vec_en = 1; 2137 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2138 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2139 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2140 dev_config.txqs_inline = MLX5_ARG_UNSET; 2141 dev_config.vf_nl_en = 1; 2142 dev_config.mr_ext_memseg_en = 1; 2143 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2144 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2145 dev_config.dv_esw_en = 1; 2146 dev_config.dv_flow_en = 1; 2147 dev_config.decap_en = 1; 2148 dev_config.log_hp_size = MLX5_ARG_UNSET; 2149 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2150 &list[i], 2151 &dev_config); 2152 if (!list[i].eth_dev) { 2153 if (rte_errno != EBUSY && rte_errno != EEXIST) 2154 break; 2155 /* Device is disabled or already spawned. Ignore it. */ 2156 continue; 2157 } 2158 restore = list[i].eth_dev->data->dev_flags; 2159 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2160 /* Restore non-PCI flags cleared by the above call. */ 2161 list[i].eth_dev->data->dev_flags |= restore; 2162 rte_eth_dev_probing_finish(list[i].eth_dev); 2163 } 2164 if (i != ns) { 2165 DRV_LOG(ERR, 2166 "probe of PCI device " PCI_PRI_FMT " aborted after" 2167 " encountering an error: %s", 2168 pci_dev->addr.domain, pci_dev->addr.bus, 2169 pci_dev->addr.devid, pci_dev->addr.function, 2170 strerror(rte_errno)); 2171 ret = -rte_errno; 2172 /* Roll back. */ 2173 while (i--) { 2174 if (!list[i].eth_dev) 2175 continue; 2176 mlx5_dev_close(list[i].eth_dev); 2177 /* mac_addrs must not be freed because in dev_private */ 2178 list[i].eth_dev->data->mac_addrs = NULL; 2179 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2180 } 2181 /* Restore original error. */ 2182 rte_errno = -ret; 2183 } else { 2184 ret = 0; 2185 } 2186 exit: 2187 /* 2188 * Do the routine cleanup: 2189 * - close opened Netlink sockets 2190 * - free allocated spawn data array 2191 * - free the Infiniband device list 2192 */ 2193 if (nl_rdma >= 0) 2194 close(nl_rdma); 2195 if (nl_route >= 0) 2196 close(nl_route); 2197 if (list) 2198 mlx5_free(list); 2199 MLX5_ASSERT(ibv_list); 2200 mlx5_glue->free_device_list(ibv_list); 2201 return ret; 2202 } 2203 2204 static int 2205 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2206 { 2207 char *env; 2208 int value; 2209 2210 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2211 /* Get environment variable to store. */ 2212 env = getenv(MLX5_SHUT_UP_BF); 2213 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2214 if (config->dbnc == MLX5_ARG_UNSET) 2215 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2216 else 2217 setenv(MLX5_SHUT_UP_BF, 2218 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2219 return value; 2220 } 2221 2222 static void 2223 mlx5_restore_doorbell_mapping_env(int value) 2224 { 2225 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2226 /* Restore the original environment variable state. */ 2227 if (value == MLX5_ARG_UNSET) 2228 unsetenv(MLX5_SHUT_UP_BF); 2229 else 2230 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2231 } 2232 2233 /** 2234 * Extract pdn of PD object using DV API. 2235 * 2236 * @param[in] pd 2237 * Pointer to the verbs PD object. 2238 * @param[out] pdn 2239 * Pointer to the PD object number variable. 2240 * 2241 * @return 2242 * 0 on success, error value otherwise. 2243 */ 2244 int 2245 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2246 { 2247 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2248 struct mlx5dv_obj obj; 2249 struct mlx5dv_pd pd_info; 2250 int ret = 0; 2251 2252 obj.pd.in = pd; 2253 obj.pd.out = &pd_info; 2254 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2255 if (ret) { 2256 DRV_LOG(DEBUG, "Fail to get PD object info"); 2257 return ret; 2258 } 2259 *pdn = pd_info.pdn; 2260 return 0; 2261 #else 2262 (void)pd; 2263 (void)pdn; 2264 return -ENOTSUP; 2265 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2266 } 2267 2268 /** 2269 * Function API to open IB device. 2270 * 2271 * This function calls the Linux glue APIs to open a device. 2272 * 2273 * @param[in] spawn 2274 * Pointer to the IB device attributes (name, port, etc). 2275 * @param[out] config 2276 * Pointer to device configuration structure. 2277 * @param[out] sh 2278 * Pointer to shared context structure. 2279 * 2280 * @return 2281 * 0 on success, a positive error value otherwise. 2282 */ 2283 int 2284 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2285 const struct mlx5_dev_config *config, 2286 struct mlx5_dev_ctx_shared *sh) 2287 { 2288 int dbmap_env; 2289 int err = 0; 2290 2291 sh->numa_node = spawn->pci_dev->device.numa_node; 2292 pthread_mutex_init(&sh->txpp.mutex, NULL); 2293 /* 2294 * Configure environment variable "MLX5_BF_SHUT_UP" 2295 * before the device creation. The rdma_core library 2296 * checks the variable at device creation and 2297 * stores the result internally. 2298 */ 2299 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2300 /* Try to open IB device with DV first, then usual Verbs. */ 2301 errno = 0; 2302 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2303 if (sh->ctx) { 2304 sh->devx = 1; 2305 DRV_LOG(DEBUG, "DevX is supported"); 2306 /* The device is created, no need for environment. */ 2307 mlx5_restore_doorbell_mapping_env(dbmap_env); 2308 } else { 2309 /* The environment variable is still configured. */ 2310 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2311 err = errno ? errno : ENODEV; 2312 /* 2313 * The environment variable is not needed anymore, 2314 * all device creation attempts are completed. 2315 */ 2316 mlx5_restore_doorbell_mapping_env(dbmap_env); 2317 if (!sh->ctx) 2318 return err; 2319 DRV_LOG(DEBUG, "DevX is NOT supported"); 2320 err = 0; 2321 } 2322 if (!err && sh->ctx) { 2323 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2324 mlx5_glue->dv_set_context_attr(sh->ctx, 2325 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2326 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2327 .alloc = &mlx5_alloc_verbs_buf, 2328 .free = &mlx5_free_verbs_buf, 2329 .data = sh, 2330 })); 2331 } 2332 return err; 2333 } 2334 2335 /** 2336 * Install shared asynchronous device events handler. 2337 * This function is implemented to support event sharing 2338 * between multiple ports of single IB device. 2339 * 2340 * @param sh 2341 * Pointer to mlx5_dev_ctx_shared object. 2342 */ 2343 void 2344 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2345 { 2346 int ret; 2347 int flags; 2348 2349 sh->intr_handle.fd = -1; 2350 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2351 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2352 F_SETFL, flags | O_NONBLOCK); 2353 if (ret) { 2354 DRV_LOG(INFO, "failed to change file descriptor async event" 2355 " queue"); 2356 } else { 2357 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2358 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2359 if (rte_intr_callback_register(&sh->intr_handle, 2360 mlx5_dev_interrupt_handler, sh)) { 2361 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2362 sh->intr_handle.fd = -1; 2363 } 2364 } 2365 if (sh->devx) { 2366 #ifdef HAVE_IBV_DEVX_ASYNC 2367 sh->intr_handle_devx.fd = -1; 2368 sh->devx_comp = 2369 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2370 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2371 if (!devx_comp) { 2372 DRV_LOG(INFO, "failed to allocate devx_comp."); 2373 return; 2374 } 2375 flags = fcntl(devx_comp->fd, F_GETFL); 2376 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2377 if (ret) { 2378 DRV_LOG(INFO, "failed to change file descriptor" 2379 " devx comp"); 2380 return; 2381 } 2382 sh->intr_handle_devx.fd = devx_comp->fd; 2383 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2384 if (rte_intr_callback_register(&sh->intr_handle_devx, 2385 mlx5_dev_interrupt_handler_devx, sh)) { 2386 DRV_LOG(INFO, "Fail to install the devx shared" 2387 " interrupt."); 2388 sh->intr_handle_devx.fd = -1; 2389 } 2390 #endif /* HAVE_IBV_DEVX_ASYNC */ 2391 } 2392 } 2393 2394 /** 2395 * Uninstall shared asynchronous device events handler. 2396 * This function is implemented to support event sharing 2397 * between multiple ports of single IB device. 2398 * 2399 * @param dev 2400 * Pointer to mlx5_dev_ctx_shared object. 2401 */ 2402 void 2403 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2404 { 2405 if (sh->intr_handle.fd >= 0) 2406 mlx5_intr_callback_unregister(&sh->intr_handle, 2407 mlx5_dev_interrupt_handler, sh); 2408 #ifdef HAVE_IBV_DEVX_ASYNC 2409 if (sh->intr_handle_devx.fd >= 0) 2410 rte_intr_callback_unregister(&sh->intr_handle_devx, 2411 mlx5_dev_interrupt_handler_devx, sh); 2412 if (sh->devx_comp) 2413 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2414 #endif 2415 } 2416 2417 /** 2418 * Read statistics by a named counter. 2419 * 2420 * @param[in] priv 2421 * Pointer to the private device data structure. 2422 * @param[in] ctr_name 2423 * Pointer to the name of the statistic counter to read 2424 * @param[out] stat 2425 * Pointer to read statistic value. 2426 * @return 2427 * 0 on success and stat is valud, 1 if failed to read the value 2428 * rte_errno is set. 2429 * 2430 */ 2431 int 2432 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2433 uint64_t *stat) 2434 { 2435 int fd; 2436 2437 if (priv->sh) { 2438 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2439 priv->sh->ibdev_path, 2440 priv->dev_port, 2441 ctr_name); 2442 fd = open(path, O_RDONLY); 2443 /* 2444 * in switchdev the file location is not per port 2445 * but rather in <ibdev_path>/hw_counters/<file_name>. 2446 */ 2447 if (fd == -1) { 2448 MKSTR(path1, "%s/hw_counters/%s", 2449 priv->sh->ibdev_path, 2450 ctr_name); 2451 fd = open(path1, O_RDONLY); 2452 } 2453 if (fd != -1) { 2454 char buf[21] = {'\0'}; 2455 ssize_t n = read(fd, buf, sizeof(buf)); 2456 2457 close(fd); 2458 if (n != -1) { 2459 *stat = strtoull(buf, NULL, 10); 2460 return 0; 2461 } 2462 } 2463 } 2464 *stat = 0; 2465 return 1; 2466 } 2467 2468 /** 2469 * Set the reg_mr and dereg_mr call backs 2470 * 2471 * @param reg_mr_cb[out] 2472 * Pointer to reg_mr func 2473 * @param dereg_mr_cb[out] 2474 * Pointer to dereg_mr func 2475 * 2476 */ 2477 void 2478 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2479 mlx5_dereg_mr_t *dereg_mr_cb) 2480 { 2481 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 2482 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 2483 } 2484 2485 /** 2486 * Remove a MAC address from device 2487 * 2488 * @param dev 2489 * Pointer to Ethernet device structure. 2490 * @param index 2491 * MAC address index. 2492 */ 2493 void 2494 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2495 { 2496 struct mlx5_priv *priv = dev->data->dev_private; 2497 const int vf = priv->config.vf; 2498 2499 if (vf) 2500 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2501 mlx5_ifindex(dev), priv->mac_own, 2502 &dev->data->mac_addrs[index], index); 2503 } 2504 2505 /** 2506 * Adds a MAC address to the device 2507 * 2508 * @param dev 2509 * Pointer to Ethernet device structure. 2510 * @param mac_addr 2511 * MAC address to register. 2512 * @param index 2513 * MAC address index. 2514 * 2515 * @return 2516 * 0 on success, a negative errno value otherwise 2517 */ 2518 int 2519 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2520 uint32_t index) 2521 { 2522 struct mlx5_priv *priv = dev->data->dev_private; 2523 const int vf = priv->config.vf; 2524 int ret = 0; 2525 2526 if (vf) 2527 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2528 mlx5_ifindex(dev), priv->mac_own, 2529 mac, index); 2530 return ret; 2531 } 2532 2533 /** 2534 * Modify a VF MAC address 2535 * 2536 * @param priv 2537 * Pointer to device private data. 2538 * @param mac_addr 2539 * MAC address to modify into. 2540 * @param iface_idx 2541 * Net device interface index 2542 * @param vf_index 2543 * VF index 2544 * 2545 * @return 2546 * 0 on success, a negative errno value otherwise 2547 */ 2548 int 2549 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2550 unsigned int iface_idx, 2551 struct rte_ether_addr *mac_addr, 2552 int vf_index) 2553 { 2554 return mlx5_nl_vf_mac_addr_modify 2555 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2556 } 2557 2558 /** 2559 * Set device promiscuous mode 2560 * 2561 * @param dev 2562 * Pointer to Ethernet device structure. 2563 * @param enable 2564 * 0 - promiscuous is disabled, otherwise - enabled 2565 * 2566 * @return 2567 * 0 on success, a negative error value otherwise 2568 */ 2569 int 2570 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2571 { 2572 struct mlx5_priv *priv = dev->data->dev_private; 2573 2574 return mlx5_nl_promisc(priv->nl_socket_route, 2575 mlx5_ifindex(dev), !!enable); 2576 } 2577 2578 /** 2579 * Set device promiscuous mode 2580 * 2581 * @param dev 2582 * Pointer to Ethernet device structure. 2583 * @param enable 2584 * 0 - all multicase is disabled, otherwise - enabled 2585 * 2586 * @return 2587 * 0 on success, a negative error value otherwise 2588 */ 2589 int 2590 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2591 { 2592 struct mlx5_priv *priv = dev->data->dev_private; 2593 2594 return mlx5_nl_allmulti(priv->nl_socket_route, 2595 mlx5_ifindex(dev), !!enable); 2596 } 2597 2598 /** 2599 * Flush device MAC addresses 2600 * 2601 * @param dev 2602 * Pointer to Ethernet device structure. 2603 * 2604 */ 2605 void 2606 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2607 { 2608 struct mlx5_priv *priv = dev->data->dev_private; 2609 2610 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2611 dev->data->mac_addrs, 2612 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2613 } 2614 2615 const struct eth_dev_ops mlx5_os_dev_ops = { 2616 .dev_configure = mlx5_dev_configure, 2617 .dev_start = mlx5_dev_start, 2618 .dev_stop = mlx5_dev_stop, 2619 .dev_set_link_down = mlx5_set_link_down, 2620 .dev_set_link_up = mlx5_set_link_up, 2621 .dev_close = mlx5_dev_close, 2622 .promiscuous_enable = mlx5_promiscuous_enable, 2623 .promiscuous_disable = mlx5_promiscuous_disable, 2624 .allmulticast_enable = mlx5_allmulticast_enable, 2625 .allmulticast_disable = mlx5_allmulticast_disable, 2626 .link_update = mlx5_link_update, 2627 .stats_get = mlx5_stats_get, 2628 .stats_reset = mlx5_stats_reset, 2629 .xstats_get = mlx5_xstats_get, 2630 .xstats_reset = mlx5_xstats_reset, 2631 .xstats_get_names = mlx5_xstats_get_names, 2632 .fw_version_get = mlx5_fw_version_get, 2633 .dev_infos_get = mlx5_dev_infos_get, 2634 .read_clock = mlx5_txpp_read_clock, 2635 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2636 .vlan_filter_set = mlx5_vlan_filter_set, 2637 .rx_queue_setup = mlx5_rx_queue_setup, 2638 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2639 .tx_queue_setup = mlx5_tx_queue_setup, 2640 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2641 .rx_queue_release = mlx5_rx_queue_release, 2642 .tx_queue_release = mlx5_tx_queue_release, 2643 .rx_queue_start = mlx5_rx_queue_start, 2644 .rx_queue_stop = mlx5_rx_queue_stop, 2645 .tx_queue_start = mlx5_tx_queue_start, 2646 .tx_queue_stop = mlx5_tx_queue_stop, 2647 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2648 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2649 .mac_addr_remove = mlx5_mac_addr_remove, 2650 .mac_addr_add = mlx5_mac_addr_add, 2651 .mac_addr_set = mlx5_mac_addr_set, 2652 .set_mc_addr_list = mlx5_set_mc_addr_list, 2653 .mtu_set = mlx5_dev_set_mtu, 2654 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2655 .vlan_offload_set = mlx5_vlan_offload_set, 2656 .reta_update = mlx5_dev_rss_reta_update, 2657 .reta_query = mlx5_dev_rss_reta_query, 2658 .rss_hash_update = mlx5_rss_hash_update, 2659 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2660 .filter_ctrl = mlx5_dev_filter_ctrl, 2661 .rxq_info_get = mlx5_rxq_info_get, 2662 .txq_info_get = mlx5_txq_info_get, 2663 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2664 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2665 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2666 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2667 .is_removed = mlx5_is_removed, 2668 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2669 .get_module_info = mlx5_get_module_info, 2670 .get_module_eeprom = mlx5_get_module_eeprom, 2671 .hairpin_cap_get = mlx5_hairpin_cap_get, 2672 .mtr_ops_get = mlx5_flow_meter_ops_get, 2673 .hairpin_bind = mlx5_hairpin_bind, 2674 .hairpin_unbind = mlx5_hairpin_unbind, 2675 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2676 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2677 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2678 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2679 }; 2680 2681 /* Available operations from secondary process. */ 2682 const struct eth_dev_ops mlx5_os_dev_sec_ops = { 2683 .stats_get = mlx5_stats_get, 2684 .stats_reset = mlx5_stats_reset, 2685 .xstats_get = mlx5_xstats_get, 2686 .xstats_reset = mlx5_xstats_reset, 2687 .xstats_get_names = mlx5_xstats_get_names, 2688 .fw_version_get = mlx5_fw_version_get, 2689 .dev_infos_get = mlx5_dev_infos_get, 2690 .read_clock = mlx5_txpp_read_clock, 2691 .rx_queue_start = mlx5_rx_queue_start, 2692 .rx_queue_stop = mlx5_rx_queue_stop, 2693 .tx_queue_start = mlx5_tx_queue_start, 2694 .tx_queue_stop = mlx5_tx_queue_stop, 2695 .rxq_info_get = mlx5_rxq_info_get, 2696 .txq_info_get = mlx5_txq_info_get, 2697 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2698 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2699 .get_module_info = mlx5_get_module_info, 2700 .get_module_eeprom = mlx5_get_module_eeprom, 2701 }; 2702 2703 /* Available operations in flow isolated mode. */ 2704 const struct eth_dev_ops mlx5_os_dev_ops_isolate = { 2705 .dev_configure = mlx5_dev_configure, 2706 .dev_start = mlx5_dev_start, 2707 .dev_stop = mlx5_dev_stop, 2708 .dev_set_link_down = mlx5_set_link_down, 2709 .dev_set_link_up = mlx5_set_link_up, 2710 .dev_close = mlx5_dev_close, 2711 .promiscuous_enable = mlx5_promiscuous_enable, 2712 .promiscuous_disable = mlx5_promiscuous_disable, 2713 .allmulticast_enable = mlx5_allmulticast_enable, 2714 .allmulticast_disable = mlx5_allmulticast_disable, 2715 .link_update = mlx5_link_update, 2716 .stats_get = mlx5_stats_get, 2717 .stats_reset = mlx5_stats_reset, 2718 .xstats_get = mlx5_xstats_get, 2719 .xstats_reset = mlx5_xstats_reset, 2720 .xstats_get_names = mlx5_xstats_get_names, 2721 .fw_version_get = mlx5_fw_version_get, 2722 .dev_infos_get = mlx5_dev_infos_get, 2723 .read_clock = mlx5_txpp_read_clock, 2724 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2725 .vlan_filter_set = mlx5_vlan_filter_set, 2726 .rx_queue_setup = mlx5_rx_queue_setup, 2727 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2728 .tx_queue_setup = mlx5_tx_queue_setup, 2729 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2730 .rx_queue_release = mlx5_rx_queue_release, 2731 .tx_queue_release = mlx5_tx_queue_release, 2732 .rx_queue_start = mlx5_rx_queue_start, 2733 .rx_queue_stop = mlx5_rx_queue_stop, 2734 .tx_queue_start = mlx5_tx_queue_start, 2735 .tx_queue_stop = mlx5_tx_queue_stop, 2736 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2737 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2738 .mac_addr_remove = mlx5_mac_addr_remove, 2739 .mac_addr_add = mlx5_mac_addr_add, 2740 .mac_addr_set = mlx5_mac_addr_set, 2741 .set_mc_addr_list = mlx5_set_mc_addr_list, 2742 .mtu_set = mlx5_dev_set_mtu, 2743 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2744 .vlan_offload_set = mlx5_vlan_offload_set, 2745 .filter_ctrl = mlx5_dev_filter_ctrl, 2746 .rxq_info_get = mlx5_rxq_info_get, 2747 .txq_info_get = mlx5_txq_info_get, 2748 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2749 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2750 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2751 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2752 .is_removed = mlx5_is_removed, 2753 .get_module_info = mlx5_get_module_info, 2754 .get_module_eeprom = mlx5_get_module_eeprom, 2755 .hairpin_cap_get = mlx5_hairpin_cap_get, 2756 .mtr_ops_get = mlx5_flow_meter_ops_get, 2757 .hairpin_bind = mlx5_hairpin_bind, 2758 .hairpin_unbind = mlx5_hairpin_unbind, 2759 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2760 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2761 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2762 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2763 }; 2764