1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_qp = attr_ex.orig_attr.max_qp; 120 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 121 device_attr->max_rwq_indirection_table_size = 122 attr_ex.rss_caps.max_rwq_indirection_table_size; 123 device_attr->max_tso = attr_ex.tso_caps.max_tso; 124 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 125 126 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 127 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 128 if (err) 129 return err; 130 131 device_attr->flags = dv_attr.flags; 132 device_attr->comp_mask = dv_attr.comp_mask; 133 #ifdef HAVE_IBV_MLX5_MOD_SWP 134 device_attr->sw_parsing_offloads = 135 dv_attr.sw_parsing_caps.sw_parsing_offloads; 136 #endif 137 device_attr->min_single_stride_log_num_of_bytes = 138 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 139 device_attr->max_single_stride_log_num_of_bytes = 140 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 141 device_attr->min_single_wqe_log_num_of_strides = 142 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 143 device_attr->max_single_wqe_log_num_of_strides = 144 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 145 device_attr->stride_supported_qpts = 146 dv_attr.striding_rq_caps.supported_qpts; 147 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 148 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 149 #endif 150 151 return err; 152 } 153 154 /** 155 * Verbs callback to allocate a memory. This function should allocate the space 156 * according to the size provided residing inside a huge page. 157 * Please note that all allocation must respect the alignment from libmlx5 158 * (i.e. currently rte_mem_page_size()). 159 * 160 * @param[in] size 161 * The size in bytes of the memory to allocate. 162 * @param[in] data 163 * A pointer to the callback data. 164 * 165 * @return 166 * Allocated buffer, NULL otherwise and rte_errno is set. 167 */ 168 static void * 169 mlx5_alloc_verbs_buf(size_t size, void *data) 170 { 171 struct mlx5_priv *priv = data; 172 void *ret; 173 unsigned int socket = SOCKET_ID_ANY; 174 size_t alignment = rte_mem_page_size(); 175 if (alignment == (size_t)-1) { 176 DRV_LOG(ERR, "Failed to get mem page size"); 177 rte_errno = ENOMEM; 178 return NULL; 179 } 180 181 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 182 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 183 184 socket = ctrl->socket; 185 } else if (priv->verbs_alloc_ctx.type == 186 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 187 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 188 189 socket = ctrl->socket; 190 } 191 MLX5_ASSERT(data != NULL); 192 ret = mlx5_malloc(0, size, alignment, socket); 193 if (!ret && size) 194 rte_errno = ENOMEM; 195 return ret; 196 } 197 198 /** 199 * Verbs callback to free a memory. 200 * 201 * @param[in] ptr 202 * A pointer to the memory to free. 203 * @param[in] data 204 * A pointer to the callback data. 205 */ 206 static void 207 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 208 { 209 MLX5_ASSERT(data != NULL); 210 mlx5_free(ptr); 211 } 212 213 /** 214 * Initialize DR related data within private structure. 215 * Routine checks the reference counter and does actual 216 * resources creation/initialization only if counter is zero. 217 * 218 * @param[in] priv 219 * Pointer to the private device data structure. 220 * 221 * @return 222 * Zero on success, positive error code otherwise. 223 */ 224 static int 225 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 226 { 227 struct mlx5_dev_ctx_shared *sh = priv->sh; 228 char s[MLX5_HLIST_NAMESIZE]; 229 int err; 230 231 MLX5_ASSERT(sh && sh->refcnt); 232 if (sh->refcnt > 1) 233 return 0; 234 err = mlx5_alloc_table_hash_list(priv); 235 if (err) 236 return err; 237 /* Create tags hash list table. */ 238 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 239 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE); 240 if (!sh->tag_table) { 241 DRV_LOG(ERR, "tags with hash creation failed."); 242 err = ENOMEM; 243 goto error; 244 } 245 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 246 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ); 247 if (!sh->modify_cmds) { 248 DRV_LOG(ERR, "hdr modify hash creation failed"); 249 err = ENOMEM; 250 goto error; 251 } 252 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 253 sh->encaps_decaps = mlx5_hlist_create(s, 254 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ); 255 if (!sh->encaps_decaps) { 256 DRV_LOG(ERR, "encap decap hash creation failed"); 257 err = ENOMEM; 258 goto error; 259 } 260 #ifdef HAVE_MLX5DV_DR 261 void *domain; 262 263 /* Reference counter is zero, we should initialize structures. */ 264 domain = mlx5_glue->dr_create_domain(sh->ctx, 265 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 266 if (!domain) { 267 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 268 err = errno; 269 goto error; 270 } 271 sh->rx_domain = domain; 272 domain = mlx5_glue->dr_create_domain(sh->ctx, 273 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 274 if (!domain) { 275 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 276 err = errno; 277 goto error; 278 } 279 pthread_mutex_init(&sh->dv_mutex, NULL); 280 sh->tx_domain = domain; 281 #ifdef HAVE_MLX5DV_DR_ESWITCH 282 if (priv->config.dv_esw_en) { 283 domain = mlx5_glue->dr_create_domain 284 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 285 if (!domain) { 286 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 287 err = errno; 288 goto error; 289 } 290 sh->fdb_domain = domain; 291 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 292 } 293 #endif 294 if (!sh->tunnel_hub) 295 err = mlx5_alloc_tunnel_hub(sh); 296 if (err) { 297 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 298 goto error; 299 } 300 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 301 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 302 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 303 if (sh->fdb_domain) 304 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 305 } 306 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 307 #endif /* HAVE_MLX5DV_DR */ 308 return 0; 309 error: 310 /* Rollback the created objects. */ 311 if (sh->rx_domain) { 312 mlx5_glue->dr_destroy_domain(sh->rx_domain); 313 sh->rx_domain = NULL; 314 } 315 if (sh->tx_domain) { 316 mlx5_glue->dr_destroy_domain(sh->tx_domain); 317 sh->tx_domain = NULL; 318 } 319 if (sh->fdb_domain) { 320 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 321 sh->fdb_domain = NULL; 322 } 323 if (sh->esw_drop_action) { 324 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 325 sh->esw_drop_action = NULL; 326 } 327 if (sh->pop_vlan_action) { 328 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 329 sh->pop_vlan_action = NULL; 330 } 331 if (sh->encaps_decaps) { 332 mlx5_hlist_destroy(sh->encaps_decaps, NULL, NULL); 333 sh->encaps_decaps = NULL; 334 } 335 if (sh->modify_cmds) { 336 mlx5_hlist_destroy(sh->modify_cmds, NULL, NULL); 337 sh->modify_cmds = NULL; 338 } 339 if (sh->tag_table) { 340 /* tags should be destroyed with flow before. */ 341 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 342 sh->tag_table = NULL; 343 } 344 if (sh->tunnel_hub) { 345 mlx5_release_tunnel_hub(sh, priv->dev_port); 346 sh->tunnel_hub = NULL; 347 } 348 mlx5_free_table_hash_list(priv); 349 return err; 350 } 351 352 /** 353 * Destroy DR related data within private structure. 354 * 355 * @param[in] priv 356 * Pointer to the private device data structure. 357 */ 358 void 359 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 360 { 361 struct mlx5_dev_ctx_shared *sh = priv->sh; 362 363 MLX5_ASSERT(sh && sh->refcnt); 364 if (sh->refcnt > 1) 365 return; 366 #ifdef HAVE_MLX5DV_DR 367 if (sh->rx_domain) { 368 mlx5_glue->dr_destroy_domain(sh->rx_domain); 369 sh->rx_domain = NULL; 370 } 371 if (sh->tx_domain) { 372 mlx5_glue->dr_destroy_domain(sh->tx_domain); 373 sh->tx_domain = NULL; 374 } 375 #ifdef HAVE_MLX5DV_DR_ESWITCH 376 if (sh->fdb_domain) { 377 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 378 sh->fdb_domain = NULL; 379 } 380 if (sh->esw_drop_action) { 381 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 382 sh->esw_drop_action = NULL; 383 } 384 #endif 385 if (sh->pop_vlan_action) { 386 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 387 sh->pop_vlan_action = NULL; 388 } 389 pthread_mutex_destroy(&sh->dv_mutex); 390 #endif /* HAVE_MLX5DV_DR */ 391 if (sh->encaps_decaps) { 392 mlx5_hlist_destroy(sh->encaps_decaps, NULL, NULL); 393 sh->encaps_decaps = NULL; 394 } 395 if (sh->modify_cmds) { 396 mlx5_hlist_destroy(sh->modify_cmds, NULL, NULL); 397 sh->modify_cmds = NULL; 398 } 399 if (sh->tag_table) { 400 /* tags should be destroyed with flow before. */ 401 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 402 sh->tag_table = NULL; 403 } 404 if (sh->tunnel_hub) { 405 mlx5_release_tunnel_hub(sh, priv->dev_port); 406 sh->tunnel_hub = NULL; 407 } 408 mlx5_free_table_hash_list(priv); 409 } 410 411 /** 412 * Initialize shared data between primary and secondary process. 413 * 414 * A memzone is reserved by primary process and secondary processes attach to 415 * the memzone. 416 * 417 * @return 418 * 0 on success, a negative errno value otherwise and rte_errno is set. 419 */ 420 static int 421 mlx5_init_shared_data(void) 422 { 423 const struct rte_memzone *mz; 424 int ret = 0; 425 426 rte_spinlock_lock(&mlx5_shared_data_lock); 427 if (mlx5_shared_data == NULL) { 428 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 429 /* Allocate shared memory. */ 430 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 431 sizeof(*mlx5_shared_data), 432 SOCKET_ID_ANY, 0); 433 if (mz == NULL) { 434 DRV_LOG(ERR, 435 "Cannot allocate mlx5 shared data"); 436 ret = -rte_errno; 437 goto error; 438 } 439 mlx5_shared_data = mz->addr; 440 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 441 rte_spinlock_init(&mlx5_shared_data->lock); 442 } else { 443 /* Lookup allocated shared memory. */ 444 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 445 if (mz == NULL) { 446 DRV_LOG(ERR, 447 "Cannot attach mlx5 shared data"); 448 ret = -rte_errno; 449 goto error; 450 } 451 mlx5_shared_data = mz->addr; 452 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 453 } 454 } 455 error: 456 rte_spinlock_unlock(&mlx5_shared_data_lock); 457 return ret; 458 } 459 460 /** 461 * PMD global initialization. 462 * 463 * Independent from individual device, this function initializes global 464 * per-PMD data structures distinguishing primary and secondary processes. 465 * Hence, each initialization is called once per a process. 466 * 467 * @return 468 * 0 on success, a negative errno value otherwise and rte_errno is set. 469 */ 470 static int 471 mlx5_init_once(void) 472 { 473 struct mlx5_shared_data *sd; 474 struct mlx5_local_data *ld = &mlx5_local_data; 475 int ret = 0; 476 477 if (mlx5_init_shared_data()) 478 return -rte_errno; 479 sd = mlx5_shared_data; 480 MLX5_ASSERT(sd); 481 rte_spinlock_lock(&sd->lock); 482 switch (rte_eal_process_type()) { 483 case RTE_PROC_PRIMARY: 484 if (sd->init_done) 485 break; 486 LIST_INIT(&sd->mem_event_cb_list); 487 rte_rwlock_init(&sd->mem_event_rwlock); 488 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 489 mlx5_mr_mem_event_cb, NULL); 490 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 491 mlx5_mp_os_primary_handle); 492 if (ret) 493 goto out; 494 sd->init_done = true; 495 break; 496 case RTE_PROC_SECONDARY: 497 if (ld->init_done) 498 break; 499 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 500 mlx5_mp_os_secondary_handle); 501 if (ret) 502 goto out; 503 ++sd->secondary_cnt; 504 ld->init_done = true; 505 break; 506 default: 507 break; 508 } 509 out: 510 rte_spinlock_unlock(&sd->lock); 511 return ret; 512 } 513 514 /** 515 * Create the Tx queue DevX/Verbs object. 516 * 517 * @param dev 518 * Pointer to Ethernet device. 519 * @param idx 520 * Queue index in DPDK Tx queue array. 521 * 522 * @return 523 * 0 on success, a negative errno value otherwise and rte_errno is set. 524 */ 525 static int 526 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 527 { 528 struct mlx5_priv *priv = dev->data->dev_private; 529 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 530 struct mlx5_txq_ctrl *txq_ctrl = 531 container_of(txq_data, struct mlx5_txq_ctrl, txq); 532 533 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 534 return mlx5_txq_devx_obj_new(dev, idx); 535 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 536 if (!priv->config.dv_esw_en) 537 return mlx5_txq_devx_obj_new(dev, idx); 538 #endif 539 return mlx5_txq_ibv_obj_new(dev, idx); 540 } 541 542 /** 543 * Release an Tx DevX/verbs queue object. 544 * 545 * @param txq_obj 546 * DevX/Verbs Tx queue object. 547 */ 548 static void 549 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 550 { 551 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 552 mlx5_txq_devx_obj_release(txq_obj); 553 return; 554 } 555 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 556 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 557 mlx5_txq_devx_obj_release(txq_obj); 558 return; 559 } 560 #endif 561 mlx5_txq_ibv_obj_release(txq_obj); 562 } 563 564 /** 565 * DV flow counter mode detect and config. 566 * 567 * @param dev 568 * Pointer to rte_eth_dev structure. 569 * 570 */ 571 static void 572 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 573 { 574 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 575 struct mlx5_priv *priv = dev->data->dev_private; 576 struct mlx5_dev_ctx_shared *sh = priv->sh; 577 bool fallback; 578 579 #ifndef HAVE_IBV_DEVX_ASYNC 580 fallback = true; 581 #else 582 fallback = false; 583 if (!priv->config.devx || !priv->config.dv_flow_en || 584 !priv->config.hca_attr.flow_counters_dump || 585 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 586 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 587 fallback = true; 588 #endif 589 if (fallback) 590 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 591 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 592 priv->config.hca_attr.flow_counters_dump, 593 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 594 /* Initialize fallback mode only on the port initializes sh. */ 595 if (sh->refcnt == 1) 596 sh->cmng.counter_fallback = fallback; 597 else if (fallback != sh->cmng.counter_fallback) 598 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 599 "with others:%d.", PORT_ID(priv), fallback); 600 #endif 601 } 602 603 /** 604 * Spawn an Ethernet device from Verbs information. 605 * 606 * @param dpdk_dev 607 * Backing DPDK device. 608 * @param spawn 609 * Verbs device parameters (name, port, switch_info) to spawn. 610 * @param config 611 * Device configuration parameters. 612 * 613 * @return 614 * A valid Ethernet device object on success, NULL otherwise and rte_errno 615 * is set. The following errors are defined: 616 * 617 * EBUSY: device is not supposed to be spawned. 618 * EEXIST: device is already spawned 619 */ 620 static struct rte_eth_dev * 621 mlx5_dev_spawn(struct rte_device *dpdk_dev, 622 struct mlx5_dev_spawn_data *spawn, 623 struct mlx5_dev_config *config) 624 { 625 const struct mlx5_switch_info *switch_info = &spawn->info; 626 struct mlx5_dev_ctx_shared *sh = NULL; 627 struct ibv_port_attr port_attr; 628 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 629 struct rte_eth_dev *eth_dev = NULL; 630 struct mlx5_priv *priv = NULL; 631 int err = 0; 632 unsigned int hw_padding = 0; 633 unsigned int mps; 634 unsigned int cqe_comp; 635 unsigned int cqe_pad = 0; 636 unsigned int tunnel_en = 0; 637 unsigned int mpls_en = 0; 638 unsigned int swp = 0; 639 unsigned int mprq = 0; 640 unsigned int mprq_min_stride_size_n = 0; 641 unsigned int mprq_max_stride_size_n = 0; 642 unsigned int mprq_min_stride_num_n = 0; 643 unsigned int mprq_max_stride_num_n = 0; 644 struct rte_ether_addr mac; 645 char name[RTE_ETH_NAME_MAX_LEN]; 646 int own_domain_id = 0; 647 uint16_t port_id; 648 unsigned int i; 649 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 650 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 651 #endif 652 653 /* Determine if this port representor is supposed to be spawned. */ 654 if (switch_info->representor && dpdk_dev->devargs) { 655 struct rte_eth_devargs eth_da; 656 657 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 658 if (err) { 659 rte_errno = -err; 660 DRV_LOG(ERR, "failed to process device arguments: %s", 661 strerror(rte_errno)); 662 return NULL; 663 } 664 for (i = 0; i < eth_da.nb_representor_ports; ++i) 665 if (eth_da.representor_ports[i] == 666 (uint16_t)switch_info->port_name) 667 break; 668 if (i == eth_da.nb_representor_ports) { 669 rte_errno = EBUSY; 670 return NULL; 671 } 672 } 673 /* Build device name. */ 674 if (spawn->pf_bond < 0) { 675 /* Single device. */ 676 if (!switch_info->representor) 677 strlcpy(name, dpdk_dev->name, sizeof(name)); 678 else 679 snprintf(name, sizeof(name), "%s_representor_%u", 680 dpdk_dev->name, switch_info->port_name); 681 } else { 682 /* Bonding device. */ 683 if (!switch_info->representor) 684 snprintf(name, sizeof(name), "%s_%s", 685 dpdk_dev->name, 686 mlx5_os_get_dev_device_name(spawn->phys_dev)); 687 else 688 snprintf(name, sizeof(name), "%s_%s_representor_%u", 689 dpdk_dev->name, 690 mlx5_os_get_dev_device_name(spawn->phys_dev), 691 switch_info->port_name); 692 } 693 /* check if the device is already spawned */ 694 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 695 rte_errno = EEXIST; 696 return NULL; 697 } 698 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 699 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 700 struct mlx5_mp_id mp_id; 701 702 eth_dev = rte_eth_dev_attach_secondary(name); 703 if (eth_dev == NULL) { 704 DRV_LOG(ERR, "can not attach rte ethdev"); 705 rte_errno = ENOMEM; 706 return NULL; 707 } 708 eth_dev->device = dpdk_dev; 709 eth_dev->dev_ops = &mlx5_os_dev_sec_ops; 710 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 711 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 712 err = mlx5_proc_priv_init(eth_dev); 713 if (err) 714 return NULL; 715 mp_id.port_id = eth_dev->data->port_id; 716 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 717 /* Receive command fd from primary process */ 718 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 719 if (err < 0) 720 goto err_secondary; 721 /* Remap UAR for Tx queues. */ 722 err = mlx5_tx_uar_init_secondary(eth_dev, err); 723 if (err) 724 goto err_secondary; 725 /* 726 * Ethdev pointer is still required as input since 727 * the primary device is not accessible from the 728 * secondary process. 729 */ 730 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 731 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 732 return eth_dev; 733 err_secondary: 734 mlx5_dev_close(eth_dev); 735 return NULL; 736 } 737 /* 738 * Some parameters ("tx_db_nc" in particularly) are needed in 739 * advance to create dv/verbs device context. We proceed the 740 * devargs here to get ones, and later proceed devargs again 741 * to override some hardware settings. 742 */ 743 err = mlx5_args(config, dpdk_dev->devargs); 744 if (err) { 745 err = rte_errno; 746 DRV_LOG(ERR, "failed to process device arguments: %s", 747 strerror(rte_errno)); 748 goto error; 749 } 750 if (config->dv_miss_info) { 751 if (switch_info->master || switch_info->representor) 752 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 753 } 754 mlx5_malloc_mem_select(config->sys_mem_en); 755 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 756 if (!sh) 757 return NULL; 758 config->devx = sh->devx; 759 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 760 config->dest_tir = 1; 761 #endif 762 #ifdef HAVE_IBV_MLX5_MOD_SWP 763 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 764 #endif 765 /* 766 * Multi-packet send is supported by ConnectX-4 Lx PF as well 767 * as all ConnectX-5 devices. 768 */ 769 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 770 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 771 #endif 772 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 773 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 774 #endif 775 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 776 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 777 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 778 DRV_LOG(DEBUG, "enhanced MPW is supported"); 779 mps = MLX5_MPW_ENHANCED; 780 } else { 781 DRV_LOG(DEBUG, "MPW is supported"); 782 mps = MLX5_MPW; 783 } 784 } else { 785 DRV_LOG(DEBUG, "MPW isn't supported"); 786 mps = MLX5_MPW_DISABLED; 787 } 788 #ifdef HAVE_IBV_MLX5_MOD_SWP 789 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 790 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 791 DRV_LOG(DEBUG, "SWP support: %u", swp); 792 #endif 793 config->swp = !!swp; 794 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 795 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 796 struct mlx5dv_striding_rq_caps mprq_caps = 797 dv_attr.striding_rq_caps; 798 799 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 800 mprq_caps.min_single_stride_log_num_of_bytes); 801 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 802 mprq_caps.max_single_stride_log_num_of_bytes); 803 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 804 mprq_caps.min_single_wqe_log_num_of_strides); 805 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 806 mprq_caps.max_single_wqe_log_num_of_strides); 807 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 808 mprq_caps.supported_qpts); 809 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 810 mprq = 1; 811 mprq_min_stride_size_n = 812 mprq_caps.min_single_stride_log_num_of_bytes; 813 mprq_max_stride_size_n = 814 mprq_caps.max_single_stride_log_num_of_bytes; 815 mprq_min_stride_num_n = 816 mprq_caps.min_single_wqe_log_num_of_strides; 817 mprq_max_stride_num_n = 818 mprq_caps.max_single_wqe_log_num_of_strides; 819 } 820 #endif 821 if (RTE_CACHE_LINE_SIZE == 128 && 822 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 823 cqe_comp = 0; 824 else 825 cqe_comp = 1; 826 config->cqe_comp = cqe_comp; 827 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 828 /* Whether device supports 128B Rx CQE padding. */ 829 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 830 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 831 #endif 832 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 833 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 834 tunnel_en = ((dv_attr.tunnel_offloads_caps & 835 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 836 (dv_attr.tunnel_offloads_caps & 837 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 838 (dv_attr.tunnel_offloads_caps & 839 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 840 } 841 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 842 tunnel_en ? "" : "not "); 843 #else 844 DRV_LOG(WARNING, 845 "tunnel offloading disabled due to old OFED/rdma-core version"); 846 #endif 847 config->tunnel_en = tunnel_en; 848 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 849 mpls_en = ((dv_attr.tunnel_offloads_caps & 850 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 851 (dv_attr.tunnel_offloads_caps & 852 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 853 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 854 mpls_en ? "" : "not "); 855 #else 856 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 857 " old OFED/rdma-core version or firmware configuration"); 858 #endif 859 config->mpls_en = mpls_en; 860 /* Check port status. */ 861 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 862 if (err) { 863 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 864 goto error; 865 } 866 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 867 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 868 err = EINVAL; 869 goto error; 870 } 871 if (port_attr.state != IBV_PORT_ACTIVE) 872 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 873 mlx5_glue->port_state_str(port_attr.state), 874 port_attr.state); 875 /* Allocate private eth device data. */ 876 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 877 sizeof(*priv), 878 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 879 if (priv == NULL) { 880 DRV_LOG(ERR, "priv allocation failure"); 881 err = ENOMEM; 882 goto error; 883 } 884 priv->sh = sh; 885 priv->dev_port = spawn->phys_port; 886 priv->pci_dev = spawn->pci_dev; 887 priv->mtu = RTE_ETHER_MTU; 888 priv->mp_id.port_id = port_id; 889 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 890 /* Some internal functions rely on Netlink sockets, open them now. */ 891 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 892 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 893 priv->representor = !!switch_info->representor; 894 priv->master = !!switch_info->master; 895 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 896 priv->vport_meta_tag = 0; 897 priv->vport_meta_mask = 0; 898 priv->pf_bond = spawn->pf_bond; 899 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 900 /* 901 * The DevX port query API is implemented. E-Switch may use 902 * either vport or reg_c[0] metadata register to match on 903 * vport index. The engaged part of metadata register is 904 * defined by mask. 905 */ 906 if (switch_info->representor || switch_info->master) { 907 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 908 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 909 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 910 &devx_port); 911 if (err) { 912 DRV_LOG(WARNING, 913 "can't query devx port %d on device %s", 914 spawn->phys_port, 915 mlx5_os_get_dev_device_name(spawn->phys_dev)); 916 devx_port.comp_mask = 0; 917 } 918 } 919 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 920 priv->vport_meta_tag = devx_port.reg_c_0.value; 921 priv->vport_meta_mask = devx_port.reg_c_0.mask; 922 if (!priv->vport_meta_mask) { 923 DRV_LOG(ERR, "vport zero mask for port %d" 924 " on bonding device %s", 925 spawn->phys_port, 926 mlx5_os_get_dev_device_name 927 (spawn->phys_dev)); 928 err = ENOTSUP; 929 goto error; 930 } 931 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 932 DRV_LOG(ERR, "invalid vport tag for port %d" 933 " on bonding device %s", 934 spawn->phys_port, 935 mlx5_os_get_dev_device_name 936 (spawn->phys_dev)); 937 err = ENOTSUP; 938 goto error; 939 } 940 } 941 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 942 priv->vport_id = devx_port.vport_num; 943 } else if (spawn->pf_bond >= 0) { 944 DRV_LOG(ERR, "can't deduce vport index for port %d" 945 " on bonding device %s", 946 spawn->phys_port, 947 mlx5_os_get_dev_device_name(spawn->phys_dev)); 948 err = ENOTSUP; 949 goto error; 950 } else { 951 /* Suppose vport index in compatible way. */ 952 priv->vport_id = switch_info->representor ? 953 switch_info->port_name + 1 : -1; 954 } 955 #else 956 /* 957 * Kernel/rdma_core support single E-Switch per PF configurations 958 * only and vport_id field contains the vport index for 959 * associated VF, which is deduced from representor port name. 960 * For example, let's have the IB device port 10, it has 961 * attached network device eth0, which has port name attribute 962 * pf0vf2, we can deduce the VF number as 2, and set vport index 963 * as 3 (2+1). This assigning schema should be changed if the 964 * multiple E-Switch instances per PF configurations or/and PCI 965 * subfunctions are added. 966 */ 967 priv->vport_id = switch_info->representor ? 968 switch_info->port_name + 1 : -1; 969 #endif 970 /* representor_id field keeps the unmodified VF index. */ 971 priv->representor_id = switch_info->representor ? 972 switch_info->port_name : -1; 973 /* 974 * Look for sibling devices in order to reuse their switch domain 975 * if any, otherwise allocate one. 976 */ 977 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 978 const struct mlx5_priv *opriv = 979 rte_eth_devices[port_id].data->dev_private; 980 981 if (!opriv || 982 opriv->sh != priv->sh || 983 opriv->domain_id == 984 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 985 continue; 986 priv->domain_id = opriv->domain_id; 987 break; 988 } 989 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 990 err = rte_eth_switch_domain_alloc(&priv->domain_id); 991 if (err) { 992 err = rte_errno; 993 DRV_LOG(ERR, "unable to allocate switch domain: %s", 994 strerror(rte_errno)); 995 goto error; 996 } 997 own_domain_id = 1; 998 } 999 /* Override some values set by hardware configuration. */ 1000 mlx5_args(config, dpdk_dev->devargs); 1001 err = mlx5_dev_check_sibling_config(priv, config); 1002 if (err) 1003 goto error; 1004 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1005 IBV_DEVICE_RAW_IP_CSUM); 1006 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1007 (config->hw_csum ? "" : "not ")); 1008 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1009 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1010 DRV_LOG(DEBUG, "counters are not supported"); 1011 #endif 1012 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1013 if (config->dv_flow_en) { 1014 DRV_LOG(WARNING, "DV flow is not supported"); 1015 config->dv_flow_en = 0; 1016 } 1017 #endif 1018 config->ind_table_max_size = 1019 sh->device_attr.max_rwq_indirection_table_size; 1020 /* 1021 * Remove this check once DPDK supports larger/variable 1022 * indirection tables. 1023 */ 1024 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1025 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1026 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1027 config->ind_table_max_size); 1028 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1029 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1030 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1031 (config->hw_vlan_strip ? "" : "not ")); 1032 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1033 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1034 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1035 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1036 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1037 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1038 IBV_DEVICE_PCI_WRITE_END_PADDING); 1039 #endif 1040 if (config->hw_padding && !hw_padding) { 1041 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1042 config->hw_padding = 0; 1043 } else if (config->hw_padding) { 1044 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1045 } 1046 config->tso = (sh->device_attr.max_tso > 0 && 1047 (sh->device_attr.tso_supported_qpts & 1048 (1 << IBV_QPT_RAW_PACKET))); 1049 if (config->tso) 1050 config->tso_max_payload_sz = sh->device_attr.max_tso; 1051 /* 1052 * MPW is disabled by default, while the Enhanced MPW is enabled 1053 * by default. 1054 */ 1055 if (config->mps == MLX5_ARG_UNSET) 1056 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1057 MLX5_MPW_DISABLED; 1058 else 1059 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1060 DRV_LOG(INFO, "%sMPS is %s", 1061 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1062 config->mps == MLX5_MPW ? "legacy " : "", 1063 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1064 if (config->cqe_comp && !cqe_comp) { 1065 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1066 config->cqe_comp = 0; 1067 } 1068 if (config->cqe_pad && !cqe_pad) { 1069 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1070 config->cqe_pad = 0; 1071 } else if (config->cqe_pad) { 1072 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1073 } 1074 if (config->devx) { 1075 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1076 if (err) { 1077 err = -err; 1078 goto error; 1079 } 1080 /* Check relax ordering support. */ 1081 if (config->hca_attr.relaxed_ordering_write && 1082 config->hca_attr.relaxed_ordering_read && 1083 !haswell_broadwell_cpu) 1084 sh->cmng.relaxed_ordering = 1; 1085 /* Check for LRO support. */ 1086 if (config->dest_tir && config->hca_attr.lro_cap && 1087 config->dv_flow_en) { 1088 /* TBD check tunnel lro caps. */ 1089 config->lro.supported = config->hca_attr.lro_cap; 1090 DRV_LOG(DEBUG, "Device supports LRO"); 1091 /* 1092 * If LRO timeout is not configured by application, 1093 * use the minimal supported value. 1094 */ 1095 if (!config->lro.timeout) 1096 config->lro.timeout = 1097 config->hca_attr.lro_timer_supported_periods[0]; 1098 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1099 config->lro.timeout); 1100 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1101 "required for coalescing is %d bytes", 1102 config->hca_attr.lro_min_mss_size); 1103 } 1104 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1105 if (config->hca_attr.qos.sup && 1106 config->hca_attr.qos.srtcm_sup && 1107 config->dv_flow_en) { 1108 uint8_t reg_c_mask = 1109 config->hca_attr.qos.flow_meter_reg_c_ids; 1110 /* 1111 * Meter needs two REG_C's for color match and pre-sfx 1112 * flow match. Here get the REG_C for color match. 1113 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1114 */ 1115 reg_c_mask &= 0xfc; 1116 if (__builtin_popcount(reg_c_mask) < 1) { 1117 priv->mtr_en = 0; 1118 DRV_LOG(WARNING, "No available register for" 1119 " meter."); 1120 } else { 1121 priv->mtr_color_reg = ffs(reg_c_mask) - 1 + 1122 REG_C_0; 1123 priv->mtr_en = 1; 1124 priv->mtr_reg_share = 1125 config->hca_attr.qos.flow_meter_reg_share; 1126 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1127 priv->mtr_color_reg); 1128 } 1129 } 1130 #endif 1131 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1132 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1133 config->dv_flow_en) { 1134 priv->sampler_en = 1; 1135 DRV_LOG(DEBUG, "The Sampler enabled!\n"); 1136 } else { 1137 priv->sampler_en = 0; 1138 if (!config->hca_attr.log_max_ft_sampler_num) 1139 DRV_LOG(WARNING, "No available register for" 1140 " Sampler."); 1141 else 1142 DRV_LOG(DEBUG, "DV flow is not supported!\n"); 1143 } 1144 #endif 1145 } 1146 if (config->tx_pp) { 1147 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1148 config->hca_attr.dev_freq_khz); 1149 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1150 config->hca_attr.qos.packet_pacing ? "" : "not "); 1151 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1152 config->hca_attr.cross_channel ? "" : "not "); 1153 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1154 config->hca_attr.wqe_index_ignore ? "" : "not "); 1155 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1156 config->hca_attr.non_wire_sq ? "" : "not "); 1157 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1158 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1159 config->hca_attr.log_max_static_sq_wq); 1160 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1161 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1162 if (!config->devx) { 1163 DRV_LOG(ERR, "DevX is required for packet pacing"); 1164 err = ENODEV; 1165 goto error; 1166 } 1167 if (!config->hca_attr.qos.packet_pacing) { 1168 DRV_LOG(ERR, "Packet pacing is not supported"); 1169 err = ENODEV; 1170 goto error; 1171 } 1172 if (!config->hca_attr.cross_channel) { 1173 DRV_LOG(ERR, "Cross channel operations are" 1174 " required for packet pacing"); 1175 err = ENODEV; 1176 goto error; 1177 } 1178 if (!config->hca_attr.wqe_index_ignore) { 1179 DRV_LOG(ERR, "WQE index ignore feature is" 1180 " required for packet pacing"); 1181 err = ENODEV; 1182 goto error; 1183 } 1184 if (!config->hca_attr.non_wire_sq) { 1185 DRV_LOG(ERR, "Non-wire SQ feature is" 1186 " required for packet pacing"); 1187 err = ENODEV; 1188 goto error; 1189 } 1190 if (!config->hca_attr.log_max_static_sq_wq) { 1191 DRV_LOG(ERR, "Static WQE SQ feature is" 1192 " required for packet pacing"); 1193 err = ENODEV; 1194 goto error; 1195 } 1196 if (!config->hca_attr.qos.wqe_rate_pp) { 1197 DRV_LOG(ERR, "WQE rate mode is required" 1198 " for packet pacing"); 1199 err = ENODEV; 1200 goto error; 1201 } 1202 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1203 DRV_LOG(ERR, "DevX does not provide UAR offset," 1204 " can't create queues for packet pacing"); 1205 err = ENODEV; 1206 goto error; 1207 #endif 1208 } 1209 if (config->devx) { 1210 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1211 1212 err = config->hca_attr.access_register_user ? 1213 mlx5_devx_cmd_register_read 1214 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1215 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1216 if (!err) { 1217 uint32_t ts_mode; 1218 1219 /* MTUTC register is read successfully. */ 1220 ts_mode = MLX5_GET(register_mtutc, reg, 1221 time_stamp_mode); 1222 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1223 config->rt_timestamp = 1; 1224 } else { 1225 /* Kernel does not support register reading. */ 1226 if (config->hca_attr.dev_freq_khz == 1227 (NS_PER_S / MS_PER_S)) 1228 config->rt_timestamp = 1; 1229 } 1230 } 1231 /* 1232 * If HW has bug working with tunnel packet decapsulation and 1233 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1234 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1235 */ 1236 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1237 config->hw_fcs_strip = 0; 1238 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1239 (config->hw_fcs_strip ? "" : "not ")); 1240 if (config->mprq.enabled && mprq) { 1241 if (config->mprq.stride_num_n && 1242 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1243 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1244 config->mprq.stride_num_n = 1245 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1246 mprq_min_stride_num_n), 1247 mprq_max_stride_num_n); 1248 DRV_LOG(WARNING, 1249 "the number of strides" 1250 " for Multi-Packet RQ is out of range," 1251 " setting default value (%u)", 1252 1 << config->mprq.stride_num_n); 1253 } 1254 if (config->mprq.stride_size_n && 1255 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1256 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1257 config->mprq.stride_size_n = 1258 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1259 mprq_min_stride_size_n), 1260 mprq_max_stride_size_n); 1261 DRV_LOG(WARNING, 1262 "the size of a stride" 1263 " for Multi-Packet RQ is out of range," 1264 " setting default value (%u)", 1265 1 << config->mprq.stride_size_n); 1266 } 1267 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1268 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1269 } else if (config->mprq.enabled && !mprq) { 1270 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1271 config->mprq.enabled = 0; 1272 } 1273 if (config->max_dump_files_num == 0) 1274 config->max_dump_files_num = 128; 1275 eth_dev = rte_eth_dev_allocate(name); 1276 if (eth_dev == NULL) { 1277 DRV_LOG(ERR, "can not allocate rte ethdev"); 1278 err = ENOMEM; 1279 goto error; 1280 } 1281 if (priv->representor) { 1282 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1283 eth_dev->data->representor_id = priv->representor_id; 1284 } 1285 /* 1286 * Store associated network device interface index. This index 1287 * is permanent throughout the lifetime of device. So, we may store 1288 * the ifindex here and use the cached value further. 1289 */ 1290 MLX5_ASSERT(spawn->ifindex); 1291 priv->if_index = spawn->ifindex; 1292 if (priv->pf_bond >= 0 && priv->master) { 1293 /* Get bond interface info */ 1294 err = mlx5_sysfs_bond_info(priv->if_index, 1295 &priv->bond_ifindex, 1296 priv->bond_name); 1297 if (err) 1298 DRV_LOG(ERR, "unable to get bond info: %s", 1299 strerror(rte_errno)); 1300 else 1301 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1302 priv->if_index, priv->bond_ifindex, 1303 priv->bond_name); 1304 } 1305 eth_dev->data->dev_private = priv; 1306 priv->dev_data = eth_dev->data; 1307 eth_dev->data->mac_addrs = priv->mac; 1308 eth_dev->device = dpdk_dev; 1309 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1310 /* Configure the first MAC address by default. */ 1311 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1312 DRV_LOG(ERR, 1313 "port %u cannot get MAC address, is mlx5_en" 1314 " loaded? (errno: %s)", 1315 eth_dev->data->port_id, strerror(rte_errno)); 1316 err = ENODEV; 1317 goto error; 1318 } 1319 DRV_LOG(INFO, 1320 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1321 eth_dev->data->port_id, 1322 mac.addr_bytes[0], mac.addr_bytes[1], 1323 mac.addr_bytes[2], mac.addr_bytes[3], 1324 mac.addr_bytes[4], mac.addr_bytes[5]); 1325 #ifdef RTE_LIBRTE_MLX5_DEBUG 1326 { 1327 char ifname[IF_NAMESIZE]; 1328 1329 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1330 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1331 eth_dev->data->port_id, ifname); 1332 else 1333 DRV_LOG(DEBUG, "port %u ifname is unknown", 1334 eth_dev->data->port_id); 1335 } 1336 #endif 1337 /* Get actual MTU if possible. */ 1338 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1339 if (err) { 1340 err = rte_errno; 1341 goto error; 1342 } 1343 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1344 priv->mtu); 1345 /* Initialize burst functions to prevent crashes before link-up. */ 1346 eth_dev->rx_pkt_burst = removed_rx_burst; 1347 eth_dev->tx_pkt_burst = removed_tx_burst; 1348 eth_dev->dev_ops = &mlx5_os_dev_ops; 1349 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1350 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1351 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1352 /* Register MAC address. */ 1353 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1354 if (config->vf && config->vf_nl_en) 1355 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1356 mlx5_ifindex(eth_dev), 1357 eth_dev->data->mac_addrs, 1358 MLX5_MAX_MAC_ADDRESSES); 1359 priv->flows = 0; 1360 priv->ctrl_flows = 0; 1361 rte_spinlock_init(&priv->flow_list_lock); 1362 TAILQ_INIT(&priv->flow_meters); 1363 TAILQ_INIT(&priv->flow_meter_profiles); 1364 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1365 mlx5_glue->dv_set_context_attr(sh->ctx, 1366 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1367 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1368 .alloc = &mlx5_alloc_verbs_buf, 1369 .free = &mlx5_free_verbs_buf, 1370 .data = priv, 1371 })); 1372 /* Bring Ethernet device up. */ 1373 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1374 eth_dev->data->port_id); 1375 mlx5_set_link_up(eth_dev); 1376 /* 1377 * Even though the interrupt handler is not installed yet, 1378 * interrupts will still trigger on the async_fd from 1379 * Verbs context returned by ibv_open_device(). 1380 */ 1381 mlx5_link_update(eth_dev, 0); 1382 #ifdef HAVE_MLX5DV_DR_ESWITCH 1383 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1384 (switch_info->representor || switch_info->master))) 1385 config->dv_esw_en = 0; 1386 #else 1387 config->dv_esw_en = 0; 1388 #endif 1389 /* Detect minimal data bytes to inline. */ 1390 mlx5_set_min_inline(spawn, config); 1391 /* Store device configuration on private structure. */ 1392 priv->config = *config; 1393 /* Create context for virtual machine VLAN workaround. */ 1394 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1395 if (config->dv_flow_en) { 1396 err = mlx5_alloc_shared_dr(priv); 1397 if (err) 1398 goto error; 1399 } 1400 if (config->devx && config->dv_flow_en && config->dest_tir) { 1401 priv->obj_ops = devx_obj_ops; 1402 priv->obj_ops.drop_action_create = 1403 ibv_obj_ops.drop_action_create; 1404 priv->obj_ops.drop_action_destroy = 1405 ibv_obj_ops.drop_action_destroy; 1406 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1407 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1408 #else 1409 if (config->dv_esw_en) 1410 priv->obj_ops.txq_obj_modify = 1411 ibv_obj_ops.txq_obj_modify; 1412 #endif 1413 /* Use specific wrappers for Tx object. */ 1414 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1415 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1416 1417 } else { 1418 priv->obj_ops = ibv_obj_ops; 1419 } 1420 /* Supported Verbs flow priority number detection. */ 1421 err = mlx5_flow_discover_priorities(eth_dev); 1422 if (err < 0) { 1423 err = -err; 1424 goto error; 1425 } 1426 priv->config.flow_prio = err; 1427 if (!priv->config.dv_esw_en && 1428 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1429 DRV_LOG(WARNING, "metadata mode %u is not supported " 1430 "(no E-Switch)", priv->config.dv_xmeta_en); 1431 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1432 } 1433 mlx5_set_metadata_mask(eth_dev); 1434 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1435 !priv->sh->dv_regc0_mask) { 1436 DRV_LOG(ERR, "metadata mode %u is not supported " 1437 "(no metadata reg_c[0] is available)", 1438 priv->config.dv_xmeta_en); 1439 err = ENOTSUP; 1440 goto error; 1441 } 1442 /* Query availability of metadata reg_c's. */ 1443 err = mlx5_flow_discover_mreg_c(eth_dev); 1444 if (err < 0) { 1445 err = -err; 1446 goto error; 1447 } 1448 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1449 DRV_LOG(DEBUG, 1450 "port %u extensive metadata register is not supported", 1451 eth_dev->data->port_id); 1452 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1453 DRV_LOG(ERR, "metadata mode %u is not supported " 1454 "(no metadata registers available)", 1455 priv->config.dv_xmeta_en); 1456 err = ENOTSUP; 1457 goto error; 1458 } 1459 } 1460 if (priv->config.dv_flow_en && 1461 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1462 mlx5_flow_ext_mreg_supported(eth_dev) && 1463 priv->sh->dv_regc0_mask) { 1464 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1465 MLX5_FLOW_MREG_HTABLE_SZ); 1466 if (!priv->mreg_cp_tbl) { 1467 err = ENOMEM; 1468 goto error; 1469 } 1470 } 1471 mlx5_flow_counter_mode_config(eth_dev); 1472 return eth_dev; 1473 error: 1474 if (priv) { 1475 if (priv->mreg_cp_tbl) 1476 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL); 1477 if (priv->sh) 1478 mlx5_os_free_shared_dr(priv); 1479 if (priv->nl_socket_route >= 0) 1480 close(priv->nl_socket_route); 1481 if (priv->nl_socket_rdma >= 0) 1482 close(priv->nl_socket_rdma); 1483 if (priv->vmwa_context) 1484 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1485 if (own_domain_id) 1486 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1487 mlx5_free(priv); 1488 if (eth_dev != NULL) 1489 eth_dev->data->dev_private = NULL; 1490 } 1491 if (eth_dev != NULL) { 1492 /* mac_addrs must not be freed alone because part of 1493 * dev_private 1494 **/ 1495 eth_dev->data->mac_addrs = NULL; 1496 rte_eth_dev_release_port(eth_dev); 1497 } 1498 if (sh) 1499 mlx5_free_shared_dev_ctx(sh); 1500 MLX5_ASSERT(err > 0); 1501 rte_errno = err; 1502 return NULL; 1503 } 1504 1505 /** 1506 * Comparison callback to sort device data. 1507 * 1508 * This is meant to be used with qsort(). 1509 * 1510 * @param a[in] 1511 * Pointer to pointer to first data object. 1512 * @param b[in] 1513 * Pointer to pointer to second data object. 1514 * 1515 * @return 1516 * 0 if both objects are equal, less than 0 if the first argument is less 1517 * than the second, greater than 0 otherwise. 1518 */ 1519 static int 1520 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1521 { 1522 const struct mlx5_switch_info *si_a = 1523 &((const struct mlx5_dev_spawn_data *)a)->info; 1524 const struct mlx5_switch_info *si_b = 1525 &((const struct mlx5_dev_spawn_data *)b)->info; 1526 int ret; 1527 1528 /* Master device first. */ 1529 ret = si_b->master - si_a->master; 1530 if (ret) 1531 return ret; 1532 /* Then representor devices. */ 1533 ret = si_b->representor - si_a->representor; 1534 if (ret) 1535 return ret; 1536 /* Unidentified devices come last in no specific order. */ 1537 if (!si_a->representor) 1538 return 0; 1539 /* Order representors by name. */ 1540 return si_a->port_name - si_b->port_name; 1541 } 1542 1543 /** 1544 * Match PCI information for possible slaves of bonding device. 1545 * 1546 * @param[in] ibv_dev 1547 * Pointer to Infiniband device structure. 1548 * @param[in] pci_dev 1549 * Pointer to PCI device structure to match PCI address. 1550 * @param[in] nl_rdma 1551 * Netlink RDMA group socket handle. 1552 * 1553 * @return 1554 * negative value if no bonding device found, otherwise 1555 * positive index of slave PF in bonding. 1556 */ 1557 static int 1558 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1559 const struct rte_pci_device *pci_dev, 1560 int nl_rdma) 1561 { 1562 char ifname[IF_NAMESIZE + 1]; 1563 unsigned int ifindex; 1564 unsigned int np, i; 1565 FILE *file = NULL; 1566 int pf = -1; 1567 1568 /* 1569 * Try to get master device name. If something goes 1570 * wrong suppose the lack of kernel support and no 1571 * bonding devices. 1572 */ 1573 if (nl_rdma < 0) 1574 return -1; 1575 if (!strstr(ibv_dev->name, "bond")) 1576 return -1; 1577 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1578 if (!np) 1579 return -1; 1580 /* 1581 * The Master device might not be on the predefined 1582 * port (not on port index 1, it is not garanted), 1583 * we have to scan all Infiniband device port and 1584 * find master. 1585 */ 1586 for (i = 1; i <= np; ++i) { 1587 /* Check whether Infiniband port is populated. */ 1588 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1589 if (!ifindex) 1590 continue; 1591 if (!if_indextoname(ifindex, ifname)) 1592 continue; 1593 /* Try to read bonding slave names from sysfs. */ 1594 MKSTR(slaves, 1595 "/sys/class/net/%s/master/bonding/slaves", ifname); 1596 file = fopen(slaves, "r"); 1597 if (file) 1598 break; 1599 } 1600 if (!file) 1601 return -1; 1602 /* Use safe format to check maximal buffer length. */ 1603 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1604 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1605 char tmp_str[IF_NAMESIZE + 32]; 1606 struct rte_pci_addr pci_addr; 1607 struct mlx5_switch_info info; 1608 1609 /* Process slave interface names in the loop. */ 1610 snprintf(tmp_str, sizeof(tmp_str), 1611 "/sys/class/net/%s", ifname); 1612 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1613 DRV_LOG(WARNING, "can not get PCI address" 1614 " for netdev \"%s\"", ifname); 1615 continue; 1616 } 1617 if (pci_dev->addr.domain != pci_addr.domain || 1618 pci_dev->addr.bus != pci_addr.bus || 1619 pci_dev->addr.devid != pci_addr.devid || 1620 pci_dev->addr.function != pci_addr.function) 1621 continue; 1622 /* Slave interface PCI address match found. */ 1623 fclose(file); 1624 snprintf(tmp_str, sizeof(tmp_str), 1625 "/sys/class/net/%s/phys_port_name", ifname); 1626 file = fopen(tmp_str, "rb"); 1627 if (!file) 1628 break; 1629 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1630 if (fscanf(file, "%32s", tmp_str) == 1) 1631 mlx5_translate_port_name(tmp_str, &info); 1632 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 1633 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1634 pf = info.port_name; 1635 break; 1636 } 1637 if (file) 1638 fclose(file); 1639 return pf; 1640 } 1641 1642 /** 1643 * DPDK callback to register a PCI device. 1644 * 1645 * This function spawns Ethernet devices out of a given PCI device. 1646 * 1647 * @param[in] pci_drv 1648 * PCI driver structure (mlx5_driver). 1649 * @param[in] pci_dev 1650 * PCI device information. 1651 * 1652 * @return 1653 * 0 on success, a negative errno value otherwise and rte_errno is set. 1654 */ 1655 int 1656 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1657 struct rte_pci_device *pci_dev) 1658 { 1659 struct ibv_device **ibv_list; 1660 /* 1661 * Number of found IB Devices matching with requested PCI BDF. 1662 * nd != 1 means there are multiple IB devices over the same 1663 * PCI device and we have representors and master. 1664 */ 1665 unsigned int nd = 0; 1666 /* 1667 * Number of found IB device Ports. nd = 1 and np = 1..n means 1668 * we have the single multiport IB device, and there may be 1669 * representors attached to some of found ports. 1670 */ 1671 unsigned int np = 0; 1672 /* 1673 * Number of DPDK ethernet devices to Spawn - either over 1674 * multiple IB devices or multiple ports of single IB device. 1675 * Actually this is the number of iterations to spawn. 1676 */ 1677 unsigned int ns = 0; 1678 /* 1679 * Bonding device 1680 * < 0 - no bonding device (single one) 1681 * >= 0 - bonding device (value is slave PF index) 1682 */ 1683 int bd = -1; 1684 struct mlx5_dev_spawn_data *list = NULL; 1685 struct mlx5_dev_config dev_config; 1686 unsigned int dev_config_vf; 1687 int ret; 1688 1689 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1690 mlx5_pmd_socket_init(); 1691 ret = mlx5_init_once(); 1692 if (ret) { 1693 DRV_LOG(ERR, "unable to init PMD global data: %s", 1694 strerror(rte_errno)); 1695 return -rte_errno; 1696 } 1697 errno = 0; 1698 ibv_list = mlx5_glue->get_device_list(&ret); 1699 if (!ibv_list) { 1700 rte_errno = errno ? errno : ENOSYS; 1701 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1702 return -rte_errno; 1703 } 1704 /* 1705 * First scan the list of all Infiniband devices to find 1706 * matching ones, gathering into the list. 1707 */ 1708 struct ibv_device *ibv_match[ret + 1]; 1709 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1710 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1711 unsigned int i; 1712 1713 while (ret-- > 0) { 1714 struct rte_pci_addr pci_addr; 1715 1716 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1717 bd = mlx5_device_bond_pci_match 1718 (ibv_list[ret], pci_dev, nl_rdma); 1719 if (bd >= 0) { 1720 /* 1721 * Bonding device detected. Only one match is allowed, 1722 * the bonding is supported over multi-port IB device, 1723 * there should be no matches on representor PCI 1724 * functions or non VF LAG bonding devices with 1725 * specified address. 1726 */ 1727 if (nd) { 1728 DRV_LOG(ERR, 1729 "multiple PCI match on bonding device" 1730 "\"%s\" found", ibv_list[ret]->name); 1731 rte_errno = ENOENT; 1732 ret = -rte_errno; 1733 goto exit; 1734 } 1735 DRV_LOG(INFO, "PCI information matches for" 1736 " slave %d bonding device \"%s\"", 1737 bd, ibv_list[ret]->name); 1738 ibv_match[nd++] = ibv_list[ret]; 1739 break; 1740 } 1741 if (mlx5_dev_to_pci_addr 1742 (ibv_list[ret]->ibdev_path, &pci_addr)) 1743 continue; 1744 if (pci_dev->addr.domain != pci_addr.domain || 1745 pci_dev->addr.bus != pci_addr.bus || 1746 pci_dev->addr.devid != pci_addr.devid || 1747 pci_dev->addr.function != pci_addr.function) 1748 continue; 1749 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1750 ibv_list[ret]->name); 1751 ibv_match[nd++] = ibv_list[ret]; 1752 } 1753 ibv_match[nd] = NULL; 1754 if (!nd) { 1755 /* No device matches, just complain and bail out. */ 1756 DRV_LOG(WARNING, 1757 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1758 " are kernel drivers loaded?", 1759 pci_dev->addr.domain, pci_dev->addr.bus, 1760 pci_dev->addr.devid, pci_dev->addr.function); 1761 rte_errno = ENOENT; 1762 ret = -rte_errno; 1763 goto exit; 1764 } 1765 if (nd == 1) { 1766 /* 1767 * Found single matching device may have multiple ports. 1768 * Each port may be representor, we have to check the port 1769 * number and check the representors existence. 1770 */ 1771 if (nl_rdma >= 0) 1772 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1773 if (!np) 1774 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1775 " ports number", ibv_match[0]->name); 1776 if (bd >= 0 && !np) { 1777 DRV_LOG(ERR, "can not get ports" 1778 " for bonding device"); 1779 rte_errno = ENOENT; 1780 ret = -rte_errno; 1781 goto exit; 1782 } 1783 } 1784 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 1785 if (bd >= 0) { 1786 /* 1787 * This may happen if there is VF LAG kernel support and 1788 * application is compiled with older rdma_core library. 1789 */ 1790 DRV_LOG(ERR, 1791 "No kernel/verbs support for VF LAG bonding found."); 1792 rte_errno = ENOTSUP; 1793 ret = -rte_errno; 1794 goto exit; 1795 } 1796 #endif 1797 /* 1798 * Now we can determine the maximal 1799 * amount of devices to be spawned. 1800 */ 1801 list = mlx5_malloc(MLX5_MEM_ZERO, 1802 sizeof(struct mlx5_dev_spawn_data) * 1803 (np ? np : nd), 1804 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1805 if (!list) { 1806 DRV_LOG(ERR, "spawn data array allocation failure"); 1807 rte_errno = ENOMEM; 1808 ret = -rte_errno; 1809 goto exit; 1810 } 1811 if (bd >= 0 || np > 1) { 1812 /* 1813 * Single IB device with multiple ports found, 1814 * it may be E-Switch master device and representors. 1815 * We have to perform identification through the ports. 1816 */ 1817 MLX5_ASSERT(nl_rdma >= 0); 1818 MLX5_ASSERT(ns == 0); 1819 MLX5_ASSERT(nd == 1); 1820 MLX5_ASSERT(np); 1821 for (i = 1; i <= np; ++i) { 1822 list[ns].max_port = np; 1823 list[ns].phys_port = i; 1824 list[ns].phys_dev = ibv_match[0]; 1825 list[ns].eth_dev = NULL; 1826 list[ns].pci_dev = pci_dev; 1827 list[ns].pf_bond = bd; 1828 list[ns].ifindex = mlx5_nl_ifindex 1829 (nl_rdma, 1830 mlx5_os_get_dev_device_name 1831 (list[ns].phys_dev), i); 1832 if (!list[ns].ifindex) { 1833 /* 1834 * No network interface index found for the 1835 * specified port, it means there is no 1836 * representor on this port. It's OK, 1837 * there can be disabled ports, for example 1838 * if sriov_numvfs < sriov_totalvfs. 1839 */ 1840 continue; 1841 } 1842 ret = -1; 1843 if (nl_route >= 0) 1844 ret = mlx5_nl_switch_info 1845 (nl_route, 1846 list[ns].ifindex, 1847 &list[ns].info); 1848 if (ret || (!list[ns].info.representor && 1849 !list[ns].info.master)) { 1850 /* 1851 * We failed to recognize representors with 1852 * Netlink, let's try to perform the task 1853 * with sysfs. 1854 */ 1855 ret = mlx5_sysfs_switch_info 1856 (list[ns].ifindex, 1857 &list[ns].info); 1858 } 1859 if (!ret && bd >= 0) { 1860 switch (list[ns].info.name_type) { 1861 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 1862 if (list[ns].info.port_name == bd) 1863 ns++; 1864 break; 1865 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 1866 /* Fallthrough */ 1867 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 1868 if (list[ns].info.pf_num == bd) 1869 ns++; 1870 break; 1871 default: 1872 break; 1873 } 1874 continue; 1875 } 1876 if (!ret && (list[ns].info.representor ^ 1877 list[ns].info.master)) 1878 ns++; 1879 } 1880 if (!ns) { 1881 DRV_LOG(ERR, 1882 "unable to recognize master/representors" 1883 " on the IB device with multiple ports"); 1884 rte_errno = ENOENT; 1885 ret = -rte_errno; 1886 goto exit; 1887 } 1888 } else { 1889 /* 1890 * The existence of several matching entries (nd > 1) means 1891 * port representors have been instantiated. No existing Verbs 1892 * call nor sysfs entries can tell them apart, this can only 1893 * be done through Netlink calls assuming kernel drivers are 1894 * recent enough to support them. 1895 * 1896 * In the event of identification failure through Netlink, 1897 * try again through sysfs, then: 1898 * 1899 * 1. A single IB device matches (nd == 1) with single 1900 * port (np=0/1) and is not a representor, assume 1901 * no switch support. 1902 * 1903 * 2. Otherwise no safe assumptions can be made; 1904 * complain louder and bail out. 1905 */ 1906 for (i = 0; i != nd; ++i) { 1907 memset(&list[ns].info, 0, sizeof(list[ns].info)); 1908 list[ns].max_port = 1; 1909 list[ns].phys_port = 1; 1910 list[ns].phys_dev = ibv_match[i]; 1911 list[ns].eth_dev = NULL; 1912 list[ns].pci_dev = pci_dev; 1913 list[ns].pf_bond = -1; 1914 list[ns].ifindex = 0; 1915 if (nl_rdma >= 0) 1916 list[ns].ifindex = mlx5_nl_ifindex 1917 (nl_rdma, 1918 mlx5_os_get_dev_device_name 1919 (list[ns].phys_dev), 1); 1920 if (!list[ns].ifindex) { 1921 char ifname[IF_NAMESIZE]; 1922 1923 /* 1924 * Netlink failed, it may happen with old 1925 * ib_core kernel driver (before 4.16). 1926 * We can assume there is old driver because 1927 * here we are processing single ports IB 1928 * devices. Let's try sysfs to retrieve 1929 * the ifindex. The method works for 1930 * master device only. 1931 */ 1932 if (nd > 1) { 1933 /* 1934 * Multiple devices found, assume 1935 * representors, can not distinguish 1936 * master/representor and retrieve 1937 * ifindex via sysfs. 1938 */ 1939 continue; 1940 } 1941 ret = mlx5_get_ifname_sysfs 1942 (ibv_match[i]->ibdev_path, ifname); 1943 if (!ret) 1944 list[ns].ifindex = 1945 if_nametoindex(ifname); 1946 if (!list[ns].ifindex) { 1947 /* 1948 * No network interface index found 1949 * for the specified device, it means 1950 * there it is neither representor 1951 * nor master. 1952 */ 1953 continue; 1954 } 1955 } 1956 ret = -1; 1957 if (nl_route >= 0) 1958 ret = mlx5_nl_switch_info 1959 (nl_route, 1960 list[ns].ifindex, 1961 &list[ns].info); 1962 if (ret || (!list[ns].info.representor && 1963 !list[ns].info.master)) { 1964 /* 1965 * We failed to recognize representors with 1966 * Netlink, let's try to perform the task 1967 * with sysfs. 1968 */ 1969 ret = mlx5_sysfs_switch_info 1970 (list[ns].ifindex, 1971 &list[ns].info); 1972 } 1973 if (!ret && (list[ns].info.representor ^ 1974 list[ns].info.master)) { 1975 ns++; 1976 } else if ((nd == 1) && 1977 !list[ns].info.representor && 1978 !list[ns].info.master) { 1979 /* 1980 * Single IB device with 1981 * one physical port and 1982 * attached network device. 1983 * May be SRIOV is not enabled 1984 * or there is no representors. 1985 */ 1986 DRV_LOG(INFO, "no E-Switch support detected"); 1987 ns++; 1988 break; 1989 } 1990 } 1991 if (!ns) { 1992 DRV_LOG(ERR, 1993 "unable to recognize master/representors" 1994 " on the multiple IB devices"); 1995 rte_errno = ENOENT; 1996 ret = -rte_errno; 1997 goto exit; 1998 } 1999 } 2000 MLX5_ASSERT(ns); 2001 /* 2002 * Sort list to probe devices in natural order for users convenience 2003 * (i.e. master first, then representors from lowest to highest ID). 2004 */ 2005 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2006 /* Device specific configuration. */ 2007 switch (pci_dev->id.device_id) { 2008 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2009 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2010 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2011 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2012 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2013 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2014 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF: 2015 dev_config_vf = 1; 2016 break; 2017 default: 2018 dev_config_vf = 0; 2019 break; 2020 } 2021 for (i = 0; i != ns; ++i) { 2022 uint32_t restore; 2023 2024 /* Default configuration. */ 2025 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2026 dev_config.vf = dev_config_vf; 2027 dev_config.mps = MLX5_ARG_UNSET; 2028 dev_config.dbnc = MLX5_ARG_UNSET; 2029 dev_config.rx_vec_en = 1; 2030 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2031 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2032 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2033 dev_config.txqs_inline = MLX5_ARG_UNSET; 2034 dev_config.vf_nl_en = 1; 2035 dev_config.mr_ext_memseg_en = 1; 2036 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2037 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2038 dev_config.dv_esw_en = 1; 2039 dev_config.dv_flow_en = 1; 2040 dev_config.decap_en = 1; 2041 dev_config.log_hp_size = MLX5_ARG_UNSET; 2042 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2043 &list[i], 2044 &dev_config); 2045 if (!list[i].eth_dev) { 2046 if (rte_errno != EBUSY && rte_errno != EEXIST) 2047 break; 2048 /* Device is disabled or already spawned. Ignore it. */ 2049 continue; 2050 } 2051 restore = list[i].eth_dev->data->dev_flags; 2052 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2053 /* Restore non-PCI flags cleared by the above call. */ 2054 list[i].eth_dev->data->dev_flags |= restore; 2055 rte_eth_dev_probing_finish(list[i].eth_dev); 2056 } 2057 if (i != ns) { 2058 DRV_LOG(ERR, 2059 "probe of PCI device " PCI_PRI_FMT " aborted after" 2060 " encountering an error: %s", 2061 pci_dev->addr.domain, pci_dev->addr.bus, 2062 pci_dev->addr.devid, pci_dev->addr.function, 2063 strerror(rte_errno)); 2064 ret = -rte_errno; 2065 /* Roll back. */ 2066 while (i--) { 2067 if (!list[i].eth_dev) 2068 continue; 2069 mlx5_dev_close(list[i].eth_dev); 2070 /* mac_addrs must not be freed because in dev_private */ 2071 list[i].eth_dev->data->mac_addrs = NULL; 2072 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2073 } 2074 /* Restore original error. */ 2075 rte_errno = -ret; 2076 } else { 2077 ret = 0; 2078 } 2079 exit: 2080 /* 2081 * Do the routine cleanup: 2082 * - close opened Netlink sockets 2083 * - free allocated spawn data array 2084 * - free the Infiniband device list 2085 */ 2086 if (nl_rdma >= 0) 2087 close(nl_rdma); 2088 if (nl_route >= 0) 2089 close(nl_route); 2090 if (list) 2091 mlx5_free(list); 2092 MLX5_ASSERT(ibv_list); 2093 mlx5_glue->free_device_list(ibv_list); 2094 return ret; 2095 } 2096 2097 static int 2098 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2099 { 2100 char *env; 2101 int value; 2102 2103 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2104 /* Get environment variable to store. */ 2105 env = getenv(MLX5_SHUT_UP_BF); 2106 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2107 if (config->dbnc == MLX5_ARG_UNSET) 2108 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2109 else 2110 setenv(MLX5_SHUT_UP_BF, 2111 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2112 return value; 2113 } 2114 2115 static void 2116 mlx5_restore_doorbell_mapping_env(int value) 2117 { 2118 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2119 /* Restore the original environment variable state. */ 2120 if (value == MLX5_ARG_UNSET) 2121 unsetenv(MLX5_SHUT_UP_BF); 2122 else 2123 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2124 } 2125 2126 /** 2127 * Extract pdn of PD object using DV API. 2128 * 2129 * @param[in] pd 2130 * Pointer to the verbs PD object. 2131 * @param[out] pdn 2132 * Pointer to the PD object number variable. 2133 * 2134 * @return 2135 * 0 on success, error value otherwise. 2136 */ 2137 int 2138 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2139 { 2140 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2141 struct mlx5dv_obj obj; 2142 struct mlx5dv_pd pd_info; 2143 int ret = 0; 2144 2145 obj.pd.in = pd; 2146 obj.pd.out = &pd_info; 2147 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2148 if (ret) { 2149 DRV_LOG(DEBUG, "Fail to get PD object info"); 2150 return ret; 2151 } 2152 *pdn = pd_info.pdn; 2153 return 0; 2154 #else 2155 (void)pd; 2156 (void)pdn; 2157 return -ENOTSUP; 2158 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2159 } 2160 2161 /** 2162 * Function API to open IB device. 2163 * 2164 * This function calls the Linux glue APIs to open a device. 2165 * 2166 * @param[in] spawn 2167 * Pointer to the IB device attributes (name, port, etc). 2168 * @param[out] config 2169 * Pointer to device configuration structure. 2170 * @param[out] sh 2171 * Pointer to shared context structure. 2172 * 2173 * @return 2174 * 0 on success, a positive error value otherwise. 2175 */ 2176 int 2177 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2178 const struct mlx5_dev_config *config, 2179 struct mlx5_dev_ctx_shared *sh) 2180 { 2181 int dbmap_env; 2182 int err = 0; 2183 2184 sh->numa_node = spawn->pci_dev->device.numa_node; 2185 pthread_mutex_init(&sh->txpp.mutex, NULL); 2186 /* 2187 * Configure environment variable "MLX5_BF_SHUT_UP" 2188 * before the device creation. The rdma_core library 2189 * checks the variable at device creation and 2190 * stores the result internally. 2191 */ 2192 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2193 /* Try to open IB device with DV first, then usual Verbs. */ 2194 errno = 0; 2195 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2196 if (sh->ctx) { 2197 sh->devx = 1; 2198 DRV_LOG(DEBUG, "DevX is supported"); 2199 /* The device is created, no need for environment. */ 2200 mlx5_restore_doorbell_mapping_env(dbmap_env); 2201 } else { 2202 /* The environment variable is still configured. */ 2203 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2204 err = errno ? errno : ENODEV; 2205 /* 2206 * The environment variable is not needed anymore, 2207 * all device creation attempts are completed. 2208 */ 2209 mlx5_restore_doorbell_mapping_env(dbmap_env); 2210 if (!sh->ctx) 2211 return err; 2212 DRV_LOG(DEBUG, "DevX is NOT supported"); 2213 err = 0; 2214 } 2215 return err; 2216 } 2217 2218 /** 2219 * Install shared asynchronous device events handler. 2220 * This function is implemented to support event sharing 2221 * between multiple ports of single IB device. 2222 * 2223 * @param sh 2224 * Pointer to mlx5_dev_ctx_shared object. 2225 */ 2226 void 2227 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2228 { 2229 int ret; 2230 int flags; 2231 2232 sh->intr_handle.fd = -1; 2233 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2234 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2235 F_SETFL, flags | O_NONBLOCK); 2236 if (ret) { 2237 DRV_LOG(INFO, "failed to change file descriptor async event" 2238 " queue"); 2239 } else { 2240 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2241 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2242 if (rte_intr_callback_register(&sh->intr_handle, 2243 mlx5_dev_interrupt_handler, sh)) { 2244 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2245 sh->intr_handle.fd = -1; 2246 } 2247 } 2248 if (sh->devx) { 2249 #ifdef HAVE_IBV_DEVX_ASYNC 2250 sh->intr_handle_devx.fd = -1; 2251 sh->devx_comp = 2252 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2253 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2254 if (!devx_comp) { 2255 DRV_LOG(INFO, "failed to allocate devx_comp."); 2256 return; 2257 } 2258 flags = fcntl(devx_comp->fd, F_GETFL); 2259 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2260 if (ret) { 2261 DRV_LOG(INFO, "failed to change file descriptor" 2262 " devx comp"); 2263 return; 2264 } 2265 sh->intr_handle_devx.fd = devx_comp->fd; 2266 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2267 if (rte_intr_callback_register(&sh->intr_handle_devx, 2268 mlx5_dev_interrupt_handler_devx, sh)) { 2269 DRV_LOG(INFO, "Fail to install the devx shared" 2270 " interrupt."); 2271 sh->intr_handle_devx.fd = -1; 2272 } 2273 #endif /* HAVE_IBV_DEVX_ASYNC */ 2274 } 2275 } 2276 2277 /** 2278 * Uninstall shared asynchronous device events handler. 2279 * This function is implemented to support event sharing 2280 * between multiple ports of single IB device. 2281 * 2282 * @param dev 2283 * Pointer to mlx5_dev_ctx_shared object. 2284 */ 2285 void 2286 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2287 { 2288 if (sh->intr_handle.fd >= 0) 2289 mlx5_intr_callback_unregister(&sh->intr_handle, 2290 mlx5_dev_interrupt_handler, sh); 2291 #ifdef HAVE_IBV_DEVX_ASYNC 2292 if (sh->intr_handle_devx.fd >= 0) 2293 rte_intr_callback_unregister(&sh->intr_handle_devx, 2294 mlx5_dev_interrupt_handler_devx, sh); 2295 if (sh->devx_comp) 2296 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2297 #endif 2298 } 2299 2300 /** 2301 * Read statistics by a named counter. 2302 * 2303 * @param[in] priv 2304 * Pointer to the private device data structure. 2305 * @param[in] ctr_name 2306 * Pointer to the name of the statistic counter to read 2307 * @param[out] stat 2308 * Pointer to read statistic value. 2309 * @return 2310 * 0 on success and stat is valud, 1 if failed to read the value 2311 * rte_errno is set. 2312 * 2313 */ 2314 int 2315 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2316 uint64_t *stat) 2317 { 2318 int fd; 2319 2320 if (priv->sh) { 2321 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2322 priv->sh->ibdev_path, 2323 priv->dev_port, 2324 ctr_name); 2325 fd = open(path, O_RDONLY); 2326 /* 2327 * in switchdev the file location is not per port 2328 * but rather in <ibdev_path>/hw_counters/<file_name>. 2329 */ 2330 if (fd == -1) { 2331 MKSTR(path1, "%s/hw_counters/%s", 2332 priv->sh->ibdev_path, 2333 ctr_name); 2334 fd = open(path1, O_RDONLY); 2335 } 2336 if (fd != -1) { 2337 char buf[21] = {'\0'}; 2338 ssize_t n = read(fd, buf, sizeof(buf)); 2339 2340 close(fd); 2341 if (n != -1) { 2342 *stat = strtoull(buf, NULL, 10); 2343 return 0; 2344 } 2345 } 2346 } 2347 *stat = 0; 2348 return 1; 2349 } 2350 2351 /** 2352 * Set the reg_mr and dereg_mr call backs 2353 * 2354 * @param reg_mr_cb[out] 2355 * Pointer to reg_mr func 2356 * @param dereg_mr_cb[out] 2357 * Pointer to dereg_mr func 2358 * 2359 */ 2360 void 2361 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2362 mlx5_dereg_mr_t *dereg_mr_cb) 2363 { 2364 *reg_mr_cb = mlx5_verbs_ops.reg_mr; 2365 *dereg_mr_cb = mlx5_verbs_ops.dereg_mr; 2366 } 2367 2368 /** 2369 * Remove a MAC address from device 2370 * 2371 * @param dev 2372 * Pointer to Ethernet device structure. 2373 * @param index 2374 * MAC address index. 2375 */ 2376 void 2377 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2378 { 2379 struct mlx5_priv *priv = dev->data->dev_private; 2380 const int vf = priv->config.vf; 2381 2382 if (vf) 2383 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2384 mlx5_ifindex(dev), priv->mac_own, 2385 &dev->data->mac_addrs[index], index); 2386 } 2387 2388 /** 2389 * Adds a MAC address to the device 2390 * 2391 * @param dev 2392 * Pointer to Ethernet device structure. 2393 * @param mac_addr 2394 * MAC address to register. 2395 * @param index 2396 * MAC address index. 2397 * 2398 * @return 2399 * 0 on success, a negative errno value otherwise 2400 */ 2401 int 2402 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2403 uint32_t index) 2404 { 2405 struct mlx5_priv *priv = dev->data->dev_private; 2406 const int vf = priv->config.vf; 2407 int ret = 0; 2408 2409 if (vf) 2410 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2411 mlx5_ifindex(dev), priv->mac_own, 2412 mac, index); 2413 return ret; 2414 } 2415 2416 /** 2417 * Modify a VF MAC address 2418 * 2419 * @param priv 2420 * Pointer to device private data. 2421 * @param mac_addr 2422 * MAC address to modify into. 2423 * @param iface_idx 2424 * Net device interface index 2425 * @param vf_index 2426 * VF index 2427 * 2428 * @return 2429 * 0 on success, a negative errno value otherwise 2430 */ 2431 int 2432 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2433 unsigned int iface_idx, 2434 struct rte_ether_addr *mac_addr, 2435 int vf_index) 2436 { 2437 return mlx5_nl_vf_mac_addr_modify 2438 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2439 } 2440 2441 /** 2442 * Set device promiscuous mode 2443 * 2444 * @param dev 2445 * Pointer to Ethernet device structure. 2446 * @param enable 2447 * 0 - promiscuous is disabled, otherwise - enabled 2448 * 2449 * @return 2450 * 0 on success, a negative error value otherwise 2451 */ 2452 int 2453 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2454 { 2455 struct mlx5_priv *priv = dev->data->dev_private; 2456 2457 return mlx5_nl_promisc(priv->nl_socket_route, 2458 mlx5_ifindex(dev), !!enable); 2459 } 2460 2461 /** 2462 * Set device promiscuous mode 2463 * 2464 * @param dev 2465 * Pointer to Ethernet device structure. 2466 * @param enable 2467 * 0 - all multicase is disabled, otherwise - enabled 2468 * 2469 * @return 2470 * 0 on success, a negative error value otherwise 2471 */ 2472 int 2473 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2474 { 2475 struct mlx5_priv *priv = dev->data->dev_private; 2476 2477 return mlx5_nl_allmulti(priv->nl_socket_route, 2478 mlx5_ifindex(dev), !!enable); 2479 } 2480 2481 /** 2482 * Flush device MAC addresses 2483 * 2484 * @param dev 2485 * Pointer to Ethernet device structure. 2486 * 2487 */ 2488 void 2489 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2490 { 2491 struct mlx5_priv *priv = dev->data->dev_private; 2492 2493 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2494 dev->data->mac_addrs, 2495 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2496 } 2497 2498 const struct eth_dev_ops mlx5_os_dev_ops = { 2499 .dev_configure = mlx5_dev_configure, 2500 .dev_start = mlx5_dev_start, 2501 .dev_stop = mlx5_dev_stop, 2502 .dev_set_link_down = mlx5_set_link_down, 2503 .dev_set_link_up = mlx5_set_link_up, 2504 .dev_close = mlx5_dev_close, 2505 .promiscuous_enable = mlx5_promiscuous_enable, 2506 .promiscuous_disable = mlx5_promiscuous_disable, 2507 .allmulticast_enable = mlx5_allmulticast_enable, 2508 .allmulticast_disable = mlx5_allmulticast_disable, 2509 .link_update = mlx5_link_update, 2510 .stats_get = mlx5_stats_get, 2511 .stats_reset = mlx5_stats_reset, 2512 .xstats_get = mlx5_xstats_get, 2513 .xstats_reset = mlx5_xstats_reset, 2514 .xstats_get_names = mlx5_xstats_get_names, 2515 .fw_version_get = mlx5_fw_version_get, 2516 .dev_infos_get = mlx5_dev_infos_get, 2517 .read_clock = mlx5_txpp_read_clock, 2518 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2519 .vlan_filter_set = mlx5_vlan_filter_set, 2520 .rx_queue_setup = mlx5_rx_queue_setup, 2521 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2522 .tx_queue_setup = mlx5_tx_queue_setup, 2523 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2524 .rx_queue_release = mlx5_rx_queue_release, 2525 .tx_queue_release = mlx5_tx_queue_release, 2526 .rx_queue_start = mlx5_rx_queue_start, 2527 .rx_queue_stop = mlx5_rx_queue_stop, 2528 .tx_queue_start = mlx5_tx_queue_start, 2529 .tx_queue_stop = mlx5_tx_queue_stop, 2530 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2531 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2532 .mac_addr_remove = mlx5_mac_addr_remove, 2533 .mac_addr_add = mlx5_mac_addr_add, 2534 .mac_addr_set = mlx5_mac_addr_set, 2535 .set_mc_addr_list = mlx5_set_mc_addr_list, 2536 .mtu_set = mlx5_dev_set_mtu, 2537 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2538 .vlan_offload_set = mlx5_vlan_offload_set, 2539 .reta_update = mlx5_dev_rss_reta_update, 2540 .reta_query = mlx5_dev_rss_reta_query, 2541 .rss_hash_update = mlx5_rss_hash_update, 2542 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2543 .filter_ctrl = mlx5_dev_filter_ctrl, 2544 .rxq_info_get = mlx5_rxq_info_get, 2545 .txq_info_get = mlx5_txq_info_get, 2546 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2547 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2548 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2549 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2550 .is_removed = mlx5_is_removed, 2551 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2552 .get_module_info = mlx5_get_module_info, 2553 .get_module_eeprom = mlx5_get_module_eeprom, 2554 .hairpin_cap_get = mlx5_hairpin_cap_get, 2555 .mtr_ops_get = mlx5_flow_meter_ops_get, 2556 .hairpin_bind = mlx5_hairpin_bind, 2557 .hairpin_unbind = mlx5_hairpin_unbind, 2558 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2559 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2560 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2561 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2562 }; 2563 2564 /* Available operations from secondary process. */ 2565 const struct eth_dev_ops mlx5_os_dev_sec_ops = { 2566 .stats_get = mlx5_stats_get, 2567 .stats_reset = mlx5_stats_reset, 2568 .xstats_get = mlx5_xstats_get, 2569 .xstats_reset = mlx5_xstats_reset, 2570 .xstats_get_names = mlx5_xstats_get_names, 2571 .fw_version_get = mlx5_fw_version_get, 2572 .dev_infos_get = mlx5_dev_infos_get, 2573 .read_clock = mlx5_txpp_read_clock, 2574 .rx_queue_start = mlx5_rx_queue_start, 2575 .rx_queue_stop = mlx5_rx_queue_stop, 2576 .tx_queue_start = mlx5_tx_queue_start, 2577 .tx_queue_stop = mlx5_tx_queue_stop, 2578 .rxq_info_get = mlx5_rxq_info_get, 2579 .txq_info_get = mlx5_txq_info_get, 2580 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2581 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2582 .get_module_info = mlx5_get_module_info, 2583 .get_module_eeprom = mlx5_get_module_eeprom, 2584 }; 2585 2586 /* Available operations in flow isolated mode. */ 2587 const struct eth_dev_ops mlx5_os_dev_ops_isolate = { 2588 .dev_configure = mlx5_dev_configure, 2589 .dev_start = mlx5_dev_start, 2590 .dev_stop = mlx5_dev_stop, 2591 .dev_set_link_down = mlx5_set_link_down, 2592 .dev_set_link_up = mlx5_set_link_up, 2593 .dev_close = mlx5_dev_close, 2594 .promiscuous_enable = mlx5_promiscuous_enable, 2595 .promiscuous_disable = mlx5_promiscuous_disable, 2596 .allmulticast_enable = mlx5_allmulticast_enable, 2597 .allmulticast_disable = mlx5_allmulticast_disable, 2598 .link_update = mlx5_link_update, 2599 .stats_get = mlx5_stats_get, 2600 .stats_reset = mlx5_stats_reset, 2601 .xstats_get = mlx5_xstats_get, 2602 .xstats_reset = mlx5_xstats_reset, 2603 .xstats_get_names = mlx5_xstats_get_names, 2604 .fw_version_get = mlx5_fw_version_get, 2605 .dev_infos_get = mlx5_dev_infos_get, 2606 .read_clock = mlx5_txpp_read_clock, 2607 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2608 .vlan_filter_set = mlx5_vlan_filter_set, 2609 .rx_queue_setup = mlx5_rx_queue_setup, 2610 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2611 .tx_queue_setup = mlx5_tx_queue_setup, 2612 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2613 .rx_queue_release = mlx5_rx_queue_release, 2614 .tx_queue_release = mlx5_tx_queue_release, 2615 .rx_queue_start = mlx5_rx_queue_start, 2616 .rx_queue_stop = mlx5_rx_queue_stop, 2617 .tx_queue_start = mlx5_tx_queue_start, 2618 .tx_queue_stop = mlx5_tx_queue_stop, 2619 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2620 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2621 .mac_addr_remove = mlx5_mac_addr_remove, 2622 .mac_addr_add = mlx5_mac_addr_add, 2623 .mac_addr_set = mlx5_mac_addr_set, 2624 .set_mc_addr_list = mlx5_set_mc_addr_list, 2625 .mtu_set = mlx5_dev_set_mtu, 2626 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2627 .vlan_offload_set = mlx5_vlan_offload_set, 2628 .filter_ctrl = mlx5_dev_filter_ctrl, 2629 .rxq_info_get = mlx5_rxq_info_get, 2630 .txq_info_get = mlx5_txq_info_get, 2631 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2632 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2633 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2634 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2635 .is_removed = mlx5_is_removed, 2636 .get_module_info = mlx5_get_module_info, 2637 .get_module_eeprom = mlx5_get_module_eeprom, 2638 .hairpin_cap_get = mlx5_hairpin_cap_get, 2639 .mtr_ops_get = mlx5_flow_meter_ops_get, 2640 .hairpin_bind = mlx5_hairpin_bind, 2641 .hairpin_unbind = mlx5_hairpin_unbind, 2642 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2643 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2644 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2645 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2646 }; 2647