1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_mr.h" 48 #include "mlx5_flow.h" 49 #include "rte_pmd_mlx5.h" 50 #include "mlx5_verbs.h" 51 #include "mlx5_nl.h" 52 #include "mlx5_devx.h" 53 54 #ifndef HAVE_IBV_MLX5_MOD_MPW 55 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 56 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 57 #endif 58 59 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 60 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 61 #endif 62 63 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 64 65 /* Spinlock for mlx5_shared_data allocation. */ 66 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 67 68 /* Process local data for secondary processes. */ 69 static struct mlx5_local_data mlx5_local_data; 70 71 /* rte flow indexed pool configuration. */ 72 static struct mlx5_indexed_pool_config icfg[] = { 73 { 74 .size = sizeof(struct rte_flow), 75 .trunk_size = 64, 76 .need_lock = 1, 77 .release_mem_en = 0, 78 .malloc = mlx5_malloc, 79 .free = mlx5_free, 80 .per_core_cache = 0, 81 .type = "ctl_flow_ipool", 82 }, 83 { 84 .size = sizeof(struct rte_flow), 85 .trunk_size = 64, 86 .grow_trunk = 3, 87 .grow_shift = 2, 88 .need_lock = 1, 89 .release_mem_en = 0, 90 .malloc = mlx5_malloc, 91 .free = mlx5_free, 92 .per_core_cache = 1 << 14, 93 .type = "rte_flow_ipool", 94 }, 95 { 96 .size = sizeof(struct rte_flow), 97 .trunk_size = 64, 98 .grow_trunk = 3, 99 .grow_shift = 2, 100 .need_lock = 1, 101 .release_mem_en = 0, 102 .malloc = mlx5_malloc, 103 .free = mlx5_free, 104 .per_core_cache = 0, 105 .type = "mcp_flow_ipool", 106 }, 107 }; 108 109 /** 110 * Set the completion channel file descriptor interrupt as non-blocking. 111 * 112 * @param[in] rxq_obj 113 * Pointer to RQ channel object, which includes the channel fd 114 * 115 * @param[out] fd 116 * The file descriptor (representing the intetrrupt) used in this channel. 117 * 118 * @return 119 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 120 */ 121 int 122 mlx5_os_set_nonblock_channel_fd(int fd) 123 { 124 int flags; 125 126 flags = fcntl(fd, F_GETFL); 127 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 128 } 129 130 /** 131 * Get mlx5 device attributes. The glue function query_device_ex() is called 132 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 133 * device attributes from the glue out parameter. 134 * 135 * @param dev 136 * Pointer to ibv context. 137 * 138 * @param device_attr 139 * Pointer to mlx5 device attributes. 140 * 141 * @return 142 * 0 on success, non zero error number otherwise 143 */ 144 int 145 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_device_attr_ex attr_ex; 149 memset(device_attr, 0, sizeof(*device_attr)); 150 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 151 if (err) 152 return err; 153 154 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 155 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 156 device_attr->max_sge = attr_ex.orig_attr.max_sge; 157 device_attr->max_cq = attr_ex.orig_attr.max_cq; 158 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 159 device_attr->max_mr = attr_ex.orig_attr.max_mr; 160 device_attr->max_pd = attr_ex.orig_attr.max_pd; 161 device_attr->max_qp = attr_ex.orig_attr.max_qp; 162 device_attr->max_srq = attr_ex.orig_attr.max_srq; 163 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 164 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 165 device_attr->max_rwq_indirection_table_size = 166 attr_ex.rss_caps.max_rwq_indirection_table_size; 167 device_attr->max_tso = attr_ex.tso_caps.max_tso; 168 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 169 170 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 171 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 172 if (err) 173 return err; 174 175 device_attr->flags = dv_attr.flags; 176 device_attr->comp_mask = dv_attr.comp_mask; 177 #ifdef HAVE_IBV_MLX5_MOD_SWP 178 device_attr->sw_parsing_offloads = 179 dv_attr.sw_parsing_caps.sw_parsing_offloads; 180 #endif 181 device_attr->min_single_stride_log_num_of_bytes = 182 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 183 device_attr->max_single_stride_log_num_of_bytes = 184 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 185 device_attr->min_single_wqe_log_num_of_strides = 186 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 187 device_attr->max_single_wqe_log_num_of_strides = 188 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 189 device_attr->stride_supported_qpts = 190 dv_attr.striding_rq_caps.supported_qpts; 191 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 192 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 193 #endif 194 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 195 sizeof(device_attr->fw_ver)); 196 197 return err; 198 } 199 200 /** 201 * Verbs callback to allocate a memory. This function should allocate the space 202 * according to the size provided residing inside a huge page. 203 * Please note that all allocation must respect the alignment from libmlx5 204 * (i.e. currently rte_mem_page_size()). 205 * 206 * @param[in] size 207 * The size in bytes of the memory to allocate. 208 * @param[in] data 209 * A pointer to the callback data. 210 * 211 * @return 212 * Allocated buffer, NULL otherwise and rte_errno is set. 213 */ 214 static void * 215 mlx5_alloc_verbs_buf(size_t size, void *data) 216 { 217 struct mlx5_dev_ctx_shared *sh = data; 218 void *ret; 219 size_t alignment = rte_mem_page_size(); 220 if (alignment == (size_t)-1) { 221 DRV_LOG(ERR, "Failed to get mem page size"); 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 226 MLX5_ASSERT(data != NULL); 227 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 228 if (!ret && size) 229 rte_errno = ENOMEM; 230 return ret; 231 } 232 233 /** 234 * Detect misc5 support or not 235 * 236 * @param[in] priv 237 * Device private data pointer 238 */ 239 #ifdef HAVE_MLX5DV_DR 240 static void 241 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 242 { 243 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 244 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 245 * Case: IPv4--->UDP--->VxLAN--->vni 246 */ 247 void *tbl; 248 struct mlx5_flow_dv_match_params matcher_mask; 249 void *match_m; 250 void *matcher; 251 void *headers_m; 252 void *misc5_m; 253 uint32_t *tunnel_header_m; 254 struct mlx5dv_flow_matcher_attr dv_attr; 255 256 memset(&matcher_mask, 0, sizeof(matcher_mask)); 257 matcher_mask.size = sizeof(matcher_mask.buf); 258 match_m = matcher_mask.buf; 259 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 260 misc5_m = MLX5_ADDR_OF(fte_match_param, 261 match_m, misc_parameters_5); 262 tunnel_header_m = (uint32_t *) 263 MLX5_ADDR_OF(fte_match_set_misc5, 264 misc5_m, tunnel_header_1); 265 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 266 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 268 *tunnel_header_m = 0xffffff; 269 270 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 271 if (!tbl) { 272 DRV_LOG(INFO, "No SW steering support"); 273 return; 274 } 275 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 276 dv_attr.match_mask = (void *)&matcher_mask, 277 dv_attr.match_criteria_enable = 278 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 279 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 280 dv_attr.priority = 3; 281 #ifdef HAVE_MLX5DV_DR_ESWITCH 282 void *misc2_m; 283 if (priv->config.dv_esw_en) { 284 /* FDB enabled reg_c_0 */ 285 dv_attr.match_criteria_enable |= 286 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 287 misc2_m = MLX5_ADDR_OF(fte_match_param, 288 match_m, misc_parameters_2); 289 MLX5_SET(fte_match_set_misc2, misc2_m, 290 metadata_reg_c_0, 0xffff); 291 } 292 #endif 293 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->ctx, 294 &dv_attr, tbl); 295 if (matcher) { 296 priv->sh->misc5_cap = 1; 297 mlx5_glue->dv_destroy_flow_matcher(matcher); 298 } 299 mlx5_glue->dr_destroy_flow_tbl(tbl); 300 #else 301 RTE_SET_USED(priv); 302 #endif 303 } 304 #endif 305 306 /** 307 * Verbs callback to free a memory. 308 * 309 * @param[in] ptr 310 * A pointer to the memory to free. 311 * @param[in] data 312 * A pointer to the callback data. 313 */ 314 static void 315 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 316 { 317 MLX5_ASSERT(data != NULL); 318 mlx5_free(ptr); 319 } 320 321 /** 322 * Initialize DR related data within private structure. 323 * Routine checks the reference counter and does actual 324 * resources creation/initialization only if counter is zero. 325 * 326 * @param[in] priv 327 * Pointer to the private device data structure. 328 * 329 * @return 330 * Zero on success, positive error code otherwise. 331 */ 332 static int 333 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 334 { 335 struct mlx5_dev_ctx_shared *sh = priv->sh; 336 char s[MLX5_NAME_SIZE] __rte_unused; 337 int err; 338 339 MLX5_ASSERT(sh && sh->refcnt); 340 if (sh->refcnt > 1) 341 return 0; 342 err = mlx5_alloc_table_hash_list(priv); 343 if (err) 344 goto error; 345 /* The resources below are only valid with DV support. */ 346 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 347 /* Init port id action list. */ 348 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 349 sh->port_id_action_list = mlx5_list_create(s, sh, true, 350 flow_dv_port_id_create_cb, 351 flow_dv_port_id_match_cb, 352 flow_dv_port_id_remove_cb, 353 flow_dv_port_id_clone_cb, 354 flow_dv_port_id_clone_free_cb); 355 if (!sh->port_id_action_list) 356 goto error; 357 /* Init push vlan action list. */ 358 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 359 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 360 flow_dv_push_vlan_create_cb, 361 flow_dv_push_vlan_match_cb, 362 flow_dv_push_vlan_remove_cb, 363 flow_dv_push_vlan_clone_cb, 364 flow_dv_push_vlan_clone_free_cb); 365 if (!sh->push_vlan_action_list) 366 goto error; 367 /* Init sample action list. */ 368 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 369 sh->sample_action_list = mlx5_list_create(s, sh, true, 370 flow_dv_sample_create_cb, 371 flow_dv_sample_match_cb, 372 flow_dv_sample_remove_cb, 373 flow_dv_sample_clone_cb, 374 flow_dv_sample_clone_free_cb); 375 if (!sh->sample_action_list) 376 goto error; 377 /* Init dest array action list. */ 378 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 379 sh->dest_array_list = mlx5_list_create(s, sh, true, 380 flow_dv_dest_array_create_cb, 381 flow_dv_dest_array_match_cb, 382 flow_dv_dest_array_remove_cb, 383 flow_dv_dest_array_clone_cb, 384 flow_dv_dest_array_clone_free_cb); 385 if (!sh->dest_array_list) 386 goto error; 387 #endif 388 #ifdef HAVE_MLX5DV_DR 389 void *domain; 390 391 /* Reference counter is zero, we should initialize structures. */ 392 domain = mlx5_glue->dr_create_domain(sh->ctx, 393 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 394 if (!domain) { 395 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 396 err = errno; 397 goto error; 398 } 399 sh->rx_domain = domain; 400 domain = mlx5_glue->dr_create_domain(sh->ctx, 401 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 402 if (!domain) { 403 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 404 err = errno; 405 goto error; 406 } 407 sh->tx_domain = domain; 408 #ifdef HAVE_MLX5DV_DR_ESWITCH 409 if (priv->config.dv_esw_en) { 410 domain = mlx5_glue->dr_create_domain 411 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 412 if (!domain) { 413 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 414 err = errno; 415 goto error; 416 } 417 sh->fdb_domain = domain; 418 } 419 /* 420 * The drop action is just some dummy placeholder in rdma-core. It 421 * does not belong to domains and has no any attributes, and, can be 422 * shared by the entire device. 423 */ 424 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 425 if (!sh->dr_drop_action) { 426 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 427 err = errno; 428 goto error; 429 } 430 #endif 431 if (!sh->tunnel_hub && priv->config.dv_miss_info) 432 err = mlx5_alloc_tunnel_hub(sh); 433 if (err) { 434 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 435 goto error; 436 } 437 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 438 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 439 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 440 if (sh->fdb_domain) 441 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 442 } 443 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 444 if (!priv->config.allow_duplicate_pattern) { 445 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 446 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 447 #endif 448 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 449 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 450 if (sh->fdb_domain) 451 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 452 } 453 454 __mlx5_discovery_misc5_cap(priv); 455 #endif /* HAVE_MLX5DV_DR */ 456 sh->default_miss_action = 457 mlx5_glue->dr_create_flow_action_default_miss(); 458 if (!sh->default_miss_action) 459 DRV_LOG(WARNING, "Default miss action is not supported."); 460 return 0; 461 error: 462 /* Rollback the created objects. */ 463 if (sh->rx_domain) { 464 mlx5_glue->dr_destroy_domain(sh->rx_domain); 465 sh->rx_domain = NULL; 466 } 467 if (sh->tx_domain) { 468 mlx5_glue->dr_destroy_domain(sh->tx_domain); 469 sh->tx_domain = NULL; 470 } 471 if (sh->fdb_domain) { 472 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 473 sh->fdb_domain = NULL; 474 } 475 if (sh->dr_drop_action) { 476 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 477 sh->dr_drop_action = NULL; 478 } 479 if (sh->pop_vlan_action) { 480 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 481 sh->pop_vlan_action = NULL; 482 } 483 if (sh->encaps_decaps) { 484 mlx5_hlist_destroy(sh->encaps_decaps); 485 sh->encaps_decaps = NULL; 486 } 487 if (sh->modify_cmds) { 488 mlx5_hlist_destroy(sh->modify_cmds); 489 sh->modify_cmds = NULL; 490 } 491 if (sh->tag_table) { 492 /* tags should be destroyed with flow before. */ 493 mlx5_hlist_destroy(sh->tag_table); 494 sh->tag_table = NULL; 495 } 496 if (sh->tunnel_hub) { 497 mlx5_release_tunnel_hub(sh, priv->dev_port); 498 sh->tunnel_hub = NULL; 499 } 500 mlx5_free_table_hash_list(priv); 501 if (sh->port_id_action_list) { 502 mlx5_list_destroy(sh->port_id_action_list); 503 sh->port_id_action_list = NULL; 504 } 505 if (sh->push_vlan_action_list) { 506 mlx5_list_destroy(sh->push_vlan_action_list); 507 sh->push_vlan_action_list = NULL; 508 } 509 if (sh->sample_action_list) { 510 mlx5_list_destroy(sh->sample_action_list); 511 sh->sample_action_list = NULL; 512 } 513 if (sh->dest_array_list) { 514 mlx5_list_destroy(sh->dest_array_list); 515 sh->dest_array_list = NULL; 516 } 517 return err; 518 } 519 520 /** 521 * Destroy DR related data within private structure. 522 * 523 * @param[in] priv 524 * Pointer to the private device data structure. 525 */ 526 void 527 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 528 { 529 struct mlx5_dev_ctx_shared *sh = priv->sh; 530 531 MLX5_ASSERT(sh && sh->refcnt); 532 if (sh->refcnt > 1) 533 return; 534 #ifdef HAVE_MLX5DV_DR 535 if (sh->rx_domain) { 536 mlx5_glue->dr_destroy_domain(sh->rx_domain); 537 sh->rx_domain = NULL; 538 } 539 if (sh->tx_domain) { 540 mlx5_glue->dr_destroy_domain(sh->tx_domain); 541 sh->tx_domain = NULL; 542 } 543 #ifdef HAVE_MLX5DV_DR_ESWITCH 544 if (sh->fdb_domain) { 545 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 546 sh->fdb_domain = NULL; 547 } 548 if (sh->dr_drop_action) { 549 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 550 sh->dr_drop_action = NULL; 551 } 552 #endif 553 if (sh->pop_vlan_action) { 554 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 555 sh->pop_vlan_action = NULL; 556 } 557 #endif /* HAVE_MLX5DV_DR */ 558 if (sh->default_miss_action) 559 mlx5_glue->destroy_flow_action 560 (sh->default_miss_action); 561 if (sh->encaps_decaps) { 562 mlx5_hlist_destroy(sh->encaps_decaps); 563 sh->encaps_decaps = NULL; 564 } 565 if (sh->modify_cmds) { 566 mlx5_hlist_destroy(sh->modify_cmds); 567 sh->modify_cmds = NULL; 568 } 569 if (sh->tag_table) { 570 /* tags should be destroyed with flow before. */ 571 mlx5_hlist_destroy(sh->tag_table); 572 sh->tag_table = NULL; 573 } 574 if (sh->tunnel_hub) { 575 mlx5_release_tunnel_hub(sh, priv->dev_port); 576 sh->tunnel_hub = NULL; 577 } 578 mlx5_free_table_hash_list(priv); 579 if (sh->port_id_action_list) { 580 mlx5_list_destroy(sh->port_id_action_list); 581 sh->port_id_action_list = NULL; 582 } 583 if (sh->push_vlan_action_list) { 584 mlx5_list_destroy(sh->push_vlan_action_list); 585 sh->push_vlan_action_list = NULL; 586 } 587 if (sh->sample_action_list) { 588 mlx5_list_destroy(sh->sample_action_list); 589 sh->sample_action_list = NULL; 590 } 591 if (sh->dest_array_list) { 592 mlx5_list_destroy(sh->dest_array_list); 593 sh->dest_array_list = NULL; 594 } 595 } 596 597 /** 598 * Initialize shared data between primary and secondary process. 599 * 600 * A memzone is reserved by primary process and secondary processes attach to 601 * the memzone. 602 * 603 * @return 604 * 0 on success, a negative errno value otherwise and rte_errno is set. 605 */ 606 static int 607 mlx5_init_shared_data(void) 608 { 609 const struct rte_memzone *mz; 610 int ret = 0; 611 612 rte_spinlock_lock(&mlx5_shared_data_lock); 613 if (mlx5_shared_data == NULL) { 614 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 615 /* Allocate shared memory. */ 616 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 617 sizeof(*mlx5_shared_data), 618 SOCKET_ID_ANY, 0); 619 if (mz == NULL) { 620 DRV_LOG(ERR, 621 "Cannot allocate mlx5 shared data"); 622 ret = -rte_errno; 623 goto error; 624 } 625 mlx5_shared_data = mz->addr; 626 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 627 rte_spinlock_init(&mlx5_shared_data->lock); 628 } else { 629 /* Lookup allocated shared memory. */ 630 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 631 if (mz == NULL) { 632 DRV_LOG(ERR, 633 "Cannot attach mlx5 shared data"); 634 ret = -rte_errno; 635 goto error; 636 } 637 mlx5_shared_data = mz->addr; 638 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 639 } 640 } 641 error: 642 rte_spinlock_unlock(&mlx5_shared_data_lock); 643 return ret; 644 } 645 646 /** 647 * PMD global initialization. 648 * 649 * Independent from individual device, this function initializes global 650 * per-PMD data structures distinguishing primary and secondary processes. 651 * Hence, each initialization is called once per a process. 652 * 653 * @return 654 * 0 on success, a negative errno value otherwise and rte_errno is set. 655 */ 656 static int 657 mlx5_init_once(void) 658 { 659 struct mlx5_shared_data *sd; 660 struct mlx5_local_data *ld = &mlx5_local_data; 661 int ret = 0; 662 663 if (mlx5_init_shared_data()) 664 return -rte_errno; 665 sd = mlx5_shared_data; 666 MLX5_ASSERT(sd); 667 rte_spinlock_lock(&sd->lock); 668 switch (rte_eal_process_type()) { 669 case RTE_PROC_PRIMARY: 670 if (sd->init_done) 671 break; 672 LIST_INIT(&sd->mem_event_cb_list); 673 rte_rwlock_init(&sd->mem_event_rwlock); 674 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 675 mlx5_mr_mem_event_cb, NULL); 676 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 677 mlx5_mp_os_primary_handle); 678 if (ret) 679 goto out; 680 sd->init_done = true; 681 break; 682 case RTE_PROC_SECONDARY: 683 if (ld->init_done) 684 break; 685 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 686 mlx5_mp_os_secondary_handle); 687 if (ret) 688 goto out; 689 ++sd->secondary_cnt; 690 ld->init_done = true; 691 break; 692 default: 693 break; 694 } 695 out: 696 rte_spinlock_unlock(&sd->lock); 697 return ret; 698 } 699 700 /** 701 * Create the Tx queue DevX/Verbs object. 702 * 703 * @param dev 704 * Pointer to Ethernet device. 705 * @param idx 706 * Queue index in DPDK Tx queue array. 707 * 708 * @return 709 * 0 on success, a negative errno value otherwise and rte_errno is set. 710 */ 711 static int 712 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 713 { 714 struct mlx5_priv *priv = dev->data->dev_private; 715 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 716 struct mlx5_txq_ctrl *txq_ctrl = 717 container_of(txq_data, struct mlx5_txq_ctrl, txq); 718 719 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 720 return mlx5_txq_devx_obj_new(dev, idx); 721 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 722 if (!priv->config.dv_esw_en) 723 return mlx5_txq_devx_obj_new(dev, idx); 724 #endif 725 return mlx5_txq_ibv_obj_new(dev, idx); 726 } 727 728 /** 729 * Release an Tx DevX/verbs queue object. 730 * 731 * @param txq_obj 732 * DevX/Verbs Tx queue object. 733 */ 734 static void 735 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 736 { 737 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 738 mlx5_txq_devx_obj_release(txq_obj); 739 return; 740 } 741 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 742 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 743 mlx5_txq_devx_obj_release(txq_obj); 744 return; 745 } 746 #endif 747 mlx5_txq_ibv_obj_release(txq_obj); 748 } 749 750 /** 751 * DV flow counter mode detect and config. 752 * 753 * @param dev 754 * Pointer to rte_eth_dev structure. 755 * 756 */ 757 static void 758 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 759 { 760 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 761 struct mlx5_priv *priv = dev->data->dev_private; 762 struct mlx5_dev_ctx_shared *sh = priv->sh; 763 bool fallback; 764 765 #ifndef HAVE_IBV_DEVX_ASYNC 766 fallback = true; 767 #else 768 fallback = false; 769 if (!priv->config.devx || !priv->config.dv_flow_en || 770 !priv->config.hca_attr.flow_counters_dump || 771 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 772 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 773 fallback = true; 774 #endif 775 if (fallback) 776 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 777 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 778 priv->config.hca_attr.flow_counters_dump, 779 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 780 /* Initialize fallback mode only on the port initializes sh. */ 781 if (sh->refcnt == 1) 782 sh->cmng.counter_fallback = fallback; 783 else if (fallback != sh->cmng.counter_fallback) 784 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 785 "with others:%d.", PORT_ID(priv), fallback); 786 #endif 787 } 788 789 static void 790 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 791 { 792 struct mlx5_priv *priv = dev->data->dev_private; 793 void *ctx = priv->sh->ctx; 794 795 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 796 if (!priv->q_counters) { 797 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 798 struct ibv_wq *wq; 799 800 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 801 "by DevX - fall-back to use the kernel driver global " 802 "queue counter.", dev->data->port_id); 803 /* Create WQ by kernel and query its queue counter ID. */ 804 if (cq) { 805 wq = mlx5_glue->create_wq(ctx, 806 &(struct ibv_wq_init_attr){ 807 .wq_type = IBV_WQT_RQ, 808 .max_wr = 1, 809 .max_sge = 1, 810 .pd = priv->sh->pd, 811 .cq = cq, 812 }); 813 if (wq) { 814 /* Counter is assigned only on RDY state. */ 815 int ret = mlx5_glue->modify_wq(wq, 816 &(struct ibv_wq_attr){ 817 .attr_mask = IBV_WQ_ATTR_STATE, 818 .wq_state = IBV_WQS_RDY, 819 }); 820 821 if (ret == 0) 822 mlx5_devx_cmd_wq_query(wq, 823 &priv->counter_set_id); 824 claim_zero(mlx5_glue->destroy_wq(wq)); 825 } 826 claim_zero(mlx5_glue->destroy_cq(cq)); 827 } 828 } else { 829 priv->counter_set_id = priv->q_counters->id; 830 } 831 if (priv->counter_set_id == 0) 832 DRV_LOG(INFO, "Part of the port %d statistics will not be " 833 "available.", dev->data->port_id); 834 } 835 836 /** 837 * Check if representor spawn info match devargs. 838 * 839 * @param spawn 840 * Verbs device parameters (name, port, switch_info) to spawn. 841 * @param eth_da 842 * Device devargs to probe. 843 * 844 * @return 845 * Match result. 846 */ 847 static bool 848 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 849 struct rte_eth_devargs *eth_da) 850 { 851 struct mlx5_switch_info *switch_info = &spawn->info; 852 unsigned int p, f; 853 uint16_t id; 854 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 855 eth_da->type); 856 857 switch (eth_da->type) { 858 case RTE_ETH_REPRESENTOR_SF: 859 if (!(spawn->info.port_name == -1 && 860 switch_info->name_type == 861 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 862 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 863 rte_errno = EBUSY; 864 return false; 865 } 866 break; 867 case RTE_ETH_REPRESENTOR_VF: 868 /* Allows HPF representor index -1 as exception. */ 869 if (!(spawn->info.port_name == -1 && 870 switch_info->name_type == 871 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 872 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 873 rte_errno = EBUSY; 874 return false; 875 } 876 break; 877 case RTE_ETH_REPRESENTOR_NONE: 878 rte_errno = EBUSY; 879 return false; 880 default: 881 rte_errno = ENOTSUP; 882 DRV_LOG(ERR, "unsupported representor type"); 883 return false; 884 } 885 /* Check representor ID: */ 886 for (p = 0; p < eth_da->nb_ports; ++p) { 887 if (spawn->pf_bond < 0) { 888 /* For non-LAG mode, allow and ignore pf. */ 889 switch_info->pf_num = eth_da->ports[p]; 890 repr_id = mlx5_representor_id_encode(switch_info, 891 eth_da->type); 892 } 893 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 894 id = MLX5_REPRESENTOR_ID 895 (eth_da->ports[p], eth_da->type, 896 eth_da->representor_ports[f]); 897 if (repr_id == id) 898 return true; 899 } 900 } 901 rte_errno = EBUSY; 902 return false; 903 } 904 905 906 /** 907 * Spawn an Ethernet device from Verbs information. 908 * 909 * @param dpdk_dev 910 * Backing DPDK device. 911 * @param spawn 912 * Verbs device parameters (name, port, switch_info) to spawn. 913 * @param config 914 * Device configuration parameters. 915 * @param config 916 * Device arguments. 917 * 918 * @return 919 * A valid Ethernet device object on success, NULL otherwise and rte_errno 920 * is set. The following errors are defined: 921 * 922 * EBUSY: device is not supposed to be spawned. 923 * EEXIST: device is already spawned 924 */ 925 static struct rte_eth_dev * 926 mlx5_dev_spawn(struct rte_device *dpdk_dev, 927 struct mlx5_dev_spawn_data *spawn, 928 struct mlx5_dev_config *config, 929 struct rte_eth_devargs *eth_da) 930 { 931 const struct mlx5_switch_info *switch_info = &spawn->info; 932 struct mlx5_dev_ctx_shared *sh = NULL; 933 struct ibv_port_attr port_attr; 934 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 935 struct rte_eth_dev *eth_dev = NULL; 936 struct mlx5_priv *priv = NULL; 937 int err = 0; 938 unsigned int hw_padding = 0; 939 unsigned int mps; 940 unsigned int tunnel_en = 0; 941 unsigned int mpls_en = 0; 942 unsigned int swp = 0; 943 unsigned int mprq = 0; 944 unsigned int mprq_min_stride_size_n = 0; 945 unsigned int mprq_max_stride_size_n = 0; 946 unsigned int mprq_min_stride_num_n = 0; 947 unsigned int mprq_max_stride_num_n = 0; 948 struct rte_ether_addr mac; 949 char name[RTE_ETH_NAME_MAX_LEN]; 950 int own_domain_id = 0; 951 uint16_t port_id; 952 struct mlx5_port_info vport_info = { .query_flags = 0 }; 953 int i; 954 955 /* Determine if this port representor is supposed to be spawned. */ 956 if (switch_info->representor && dpdk_dev->devargs && 957 !mlx5_representor_match(spawn, eth_da)) 958 return NULL; 959 /* Build device name. */ 960 if (spawn->pf_bond < 0) { 961 /* Single device. */ 962 if (!switch_info->representor) 963 strlcpy(name, dpdk_dev->name, sizeof(name)); 964 else 965 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 966 dpdk_dev->name, 967 switch_info->name_type == 968 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 969 switch_info->port_name); 970 } else { 971 /* Bonding device. */ 972 if (!switch_info->representor) { 973 err = snprintf(name, sizeof(name), "%s_%s", 974 dpdk_dev->name, 975 mlx5_os_get_dev_device_name(spawn->phys_dev)); 976 } else { 977 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 978 dpdk_dev->name, 979 mlx5_os_get_dev_device_name(spawn->phys_dev), 980 switch_info->ctrl_num, 981 switch_info->pf_num, 982 switch_info->name_type == 983 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 984 switch_info->port_name); 985 } 986 } 987 if (err >= (int)sizeof(name)) 988 DRV_LOG(WARNING, "device name overflow %s", name); 989 /* check if the device is already spawned */ 990 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 991 rte_errno = EEXIST; 992 return NULL; 993 } 994 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 995 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 996 struct mlx5_mp_id mp_id; 997 998 eth_dev = rte_eth_dev_attach_secondary(name); 999 if (eth_dev == NULL) { 1000 DRV_LOG(ERR, "can not attach rte ethdev"); 1001 rte_errno = ENOMEM; 1002 return NULL; 1003 } 1004 eth_dev->device = dpdk_dev; 1005 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1006 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1007 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1008 err = mlx5_proc_priv_init(eth_dev); 1009 if (err) 1010 return NULL; 1011 mp_id.port_id = eth_dev->data->port_id; 1012 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1013 /* Receive command fd from primary process */ 1014 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 1015 if (err < 0) 1016 goto err_secondary; 1017 /* Remap UAR for Tx queues. */ 1018 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1019 if (err) 1020 goto err_secondary; 1021 /* 1022 * Ethdev pointer is still required as input since 1023 * the primary device is not accessible from the 1024 * secondary process. 1025 */ 1026 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1027 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1028 return eth_dev; 1029 err_secondary: 1030 mlx5_dev_close(eth_dev); 1031 return NULL; 1032 } 1033 /* 1034 * Some parameters ("tx_db_nc" in particularly) are needed in 1035 * advance to create dv/verbs device context. We proceed the 1036 * devargs here to get ones, and later proceed devargs again 1037 * to override some hardware settings. 1038 */ 1039 err = mlx5_args(config, dpdk_dev->devargs); 1040 if (err) { 1041 err = rte_errno; 1042 DRV_LOG(ERR, "failed to process device arguments: %s", 1043 strerror(rte_errno)); 1044 goto error; 1045 } 1046 if (config->dv_miss_info) { 1047 if (switch_info->master || switch_info->representor) 1048 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1049 } 1050 mlx5_malloc_mem_select(config->sys_mem_en); 1051 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 1052 if (!sh) 1053 return NULL; 1054 config->devx = sh->devx; 1055 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 1056 config->dest_tir = 1; 1057 #endif 1058 #ifdef HAVE_IBV_MLX5_MOD_SWP 1059 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 1060 #endif 1061 /* 1062 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1063 * as all ConnectX-5 devices. 1064 */ 1065 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1066 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1067 #endif 1068 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1069 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1070 #endif 1071 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 1072 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1073 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1074 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1075 mps = MLX5_MPW_ENHANCED; 1076 } else { 1077 DRV_LOG(DEBUG, "MPW is supported"); 1078 mps = MLX5_MPW; 1079 } 1080 } else { 1081 DRV_LOG(DEBUG, "MPW isn't supported"); 1082 mps = MLX5_MPW_DISABLED; 1083 } 1084 #ifdef HAVE_IBV_MLX5_MOD_SWP 1085 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1086 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1087 DRV_LOG(DEBUG, "SWP support: %u", swp); 1088 #endif 1089 config->swp = !!swp; 1090 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1091 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1092 struct mlx5dv_striding_rq_caps mprq_caps = 1093 dv_attr.striding_rq_caps; 1094 1095 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1096 mprq_caps.min_single_stride_log_num_of_bytes); 1097 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1098 mprq_caps.max_single_stride_log_num_of_bytes); 1099 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1100 mprq_caps.min_single_wqe_log_num_of_strides); 1101 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1102 mprq_caps.max_single_wqe_log_num_of_strides); 1103 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1104 mprq_caps.supported_qpts); 1105 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1106 mprq = 1; 1107 mprq_min_stride_size_n = 1108 mprq_caps.min_single_stride_log_num_of_bytes; 1109 mprq_max_stride_size_n = 1110 mprq_caps.max_single_stride_log_num_of_bytes; 1111 mprq_min_stride_num_n = 1112 mprq_caps.min_single_wqe_log_num_of_strides; 1113 mprq_max_stride_num_n = 1114 mprq_caps.max_single_wqe_log_num_of_strides; 1115 } 1116 #endif 1117 /* Rx CQE compression is enabled by default. */ 1118 config->cqe_comp = 1; 1119 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1120 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1121 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1122 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1123 (dv_attr.tunnel_offloads_caps & 1124 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 1125 (dv_attr.tunnel_offloads_caps & 1126 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 1127 } 1128 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1129 tunnel_en ? "" : "not "); 1130 #else 1131 DRV_LOG(WARNING, 1132 "tunnel offloading disabled due to old OFED/rdma-core version"); 1133 #endif 1134 config->tunnel_en = tunnel_en; 1135 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1136 mpls_en = ((dv_attr.tunnel_offloads_caps & 1137 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1138 (dv_attr.tunnel_offloads_caps & 1139 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1140 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1141 mpls_en ? "" : "not "); 1142 #else 1143 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1144 " old OFED/rdma-core version or firmware configuration"); 1145 #endif 1146 config->mpls_en = mpls_en; 1147 /* Check port status. */ 1148 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1149 if (err) { 1150 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1151 goto error; 1152 } 1153 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1154 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1155 err = EINVAL; 1156 goto error; 1157 } 1158 if (port_attr.state != IBV_PORT_ACTIVE) 1159 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1160 mlx5_glue->port_state_str(port_attr.state), 1161 port_attr.state); 1162 /* Allocate private eth device data. */ 1163 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1164 sizeof(*priv), 1165 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1166 if (priv == NULL) { 1167 DRV_LOG(ERR, "priv allocation failure"); 1168 err = ENOMEM; 1169 goto error; 1170 } 1171 priv->sh = sh; 1172 priv->dev_port = spawn->phys_port; 1173 priv->pci_dev = spawn->pci_dev; 1174 priv->mtu = RTE_ETHER_MTU; 1175 /* Some internal functions rely on Netlink sockets, open them now. */ 1176 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1177 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1178 priv->representor = !!switch_info->representor; 1179 priv->master = !!switch_info->master; 1180 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1181 priv->vport_meta_tag = 0; 1182 priv->vport_meta_mask = 0; 1183 priv->pf_bond = spawn->pf_bond; 1184 /* 1185 * If we have E-Switch we should determine the vport attributes. 1186 * E-Switch may use either source vport field or reg_c[0] metadata 1187 * register to match on vport index. The engaged part of metadata 1188 * register is defined by mask. 1189 */ 1190 if (switch_info->representor || switch_info->master) { 1191 err = mlx5_glue->devx_port_query(sh->ctx, 1192 spawn->phys_port, 1193 &vport_info); 1194 if (err) { 1195 DRV_LOG(WARNING, 1196 "can't query devx port %d on device %s", 1197 spawn->phys_port, 1198 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1199 vport_info.query_flags = 0; 1200 } 1201 } 1202 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1203 priv->vport_meta_tag = vport_info.vport_meta_tag; 1204 priv->vport_meta_mask = vport_info.vport_meta_mask; 1205 if (!priv->vport_meta_mask) { 1206 DRV_LOG(ERR, "vport zero mask for port %d" 1207 " on bonding device %s", 1208 spawn->phys_port, 1209 mlx5_os_get_dev_device_name 1210 (spawn->phys_dev)); 1211 err = ENOTSUP; 1212 goto error; 1213 } 1214 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1215 DRV_LOG(ERR, "invalid vport tag for port %d" 1216 " on bonding device %s", 1217 spawn->phys_port, 1218 mlx5_os_get_dev_device_name 1219 (spawn->phys_dev)); 1220 err = ENOTSUP; 1221 goto error; 1222 } 1223 } 1224 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1225 priv->vport_id = vport_info.vport_id; 1226 } else if (spawn->pf_bond >= 0 && 1227 (switch_info->representor || switch_info->master)) { 1228 DRV_LOG(ERR, "can't deduce vport index for port %d" 1229 " on bonding device %s", 1230 spawn->phys_port, 1231 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1232 err = ENOTSUP; 1233 goto error; 1234 } else { 1235 /* 1236 * Suppose vport index in compatible way. Kernel/rdma_core 1237 * support single E-Switch per PF configurations only and 1238 * vport_id field contains the vport index for associated VF, 1239 * which is deduced from representor port name. 1240 * For example, let's have the IB device port 10, it has 1241 * attached network device eth0, which has port name attribute 1242 * pf0vf2, we can deduce the VF number as 2, and set vport index 1243 * as 3 (2+1). This assigning schema should be changed if the 1244 * multiple E-Switch instances per PF configurations or/and PCI 1245 * subfunctions are added. 1246 */ 1247 priv->vport_id = switch_info->representor ? 1248 switch_info->port_name + 1 : -1; 1249 } 1250 priv->representor_id = mlx5_representor_id_encode(switch_info, 1251 eth_da->type); 1252 /* 1253 * Look for sibling devices in order to reuse their switch domain 1254 * if any, otherwise allocate one. 1255 */ 1256 MLX5_ETH_FOREACH_DEV(port_id, NULL) { 1257 const struct mlx5_priv *opriv = 1258 rte_eth_devices[port_id].data->dev_private; 1259 1260 if (!opriv || 1261 opriv->sh != priv->sh || 1262 opriv->domain_id == 1263 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1264 continue; 1265 priv->domain_id = opriv->domain_id; 1266 break; 1267 } 1268 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1269 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1270 if (err) { 1271 err = rte_errno; 1272 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1273 strerror(rte_errno)); 1274 goto error; 1275 } 1276 own_domain_id = 1; 1277 } 1278 /* Override some values set by hardware configuration. */ 1279 mlx5_args(config, dpdk_dev->devargs); 1280 err = mlx5_dev_check_sibling_config(priv, config); 1281 if (err) 1282 goto error; 1283 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1284 IBV_DEVICE_RAW_IP_CSUM); 1285 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1286 (config->hw_csum ? "" : "not ")); 1287 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1288 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1289 DRV_LOG(DEBUG, "counters are not supported"); 1290 #endif 1291 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1292 if (config->dv_flow_en) { 1293 DRV_LOG(WARNING, "DV flow is not supported"); 1294 config->dv_flow_en = 0; 1295 } 1296 #endif 1297 if (spawn->max_port > UINT8_MAX) { 1298 /* Verbs can't support ports larger than 255 by design. */ 1299 DRV_LOG(ERR, "can't support IB ports > UINT8_MAX"); 1300 err = EINVAL; 1301 goto error; 1302 } 1303 config->ind_table_max_size = 1304 sh->device_attr.max_rwq_indirection_table_size; 1305 /* 1306 * Remove this check once DPDK supports larger/variable 1307 * indirection tables. 1308 */ 1309 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1310 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1311 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1312 config->ind_table_max_size); 1313 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1314 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1315 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1316 (config->hw_vlan_strip ? "" : "not ")); 1317 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1318 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1319 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1320 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1321 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1322 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1323 IBV_DEVICE_PCI_WRITE_END_PADDING); 1324 #endif 1325 if (config->hw_padding && !hw_padding) { 1326 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1327 config->hw_padding = 0; 1328 } else if (config->hw_padding) { 1329 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1330 } 1331 config->tso = (sh->device_attr.max_tso > 0 && 1332 (sh->device_attr.tso_supported_qpts & 1333 (1 << IBV_QPT_RAW_PACKET))); 1334 if (config->tso) 1335 config->tso_max_payload_sz = sh->device_attr.max_tso; 1336 /* 1337 * MPW is disabled by default, while the Enhanced MPW is enabled 1338 * by default. 1339 */ 1340 if (config->mps == MLX5_ARG_UNSET) 1341 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1342 MLX5_MPW_DISABLED; 1343 else 1344 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1345 DRV_LOG(INFO, "%sMPS is %s", 1346 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1347 config->mps == MLX5_MPW ? "legacy " : "", 1348 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1349 if (config->devx) { 1350 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1351 if (err) { 1352 err = -err; 1353 goto error; 1354 } 1355 /* Check relax ordering support. */ 1356 if (!haswell_broadwell_cpu) { 1357 sh->cmng.relaxed_ordering_write = 1358 config->hca_attr.relaxed_ordering_write; 1359 sh->cmng.relaxed_ordering_read = 1360 config->hca_attr.relaxed_ordering_read; 1361 } else { 1362 sh->cmng.relaxed_ordering_read = 0; 1363 sh->cmng.relaxed_ordering_write = 0; 1364 } 1365 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1366 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1367 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1368 /* Check for LRO support. */ 1369 if (config->dest_tir && config->hca_attr.lro_cap && 1370 config->dv_flow_en) { 1371 /* TBD check tunnel lro caps. */ 1372 config->lro.supported = config->hca_attr.lro_cap; 1373 DRV_LOG(DEBUG, "Device supports LRO"); 1374 /* 1375 * If LRO timeout is not configured by application, 1376 * use the minimal supported value. 1377 */ 1378 if (!config->lro.timeout) 1379 config->lro.timeout = 1380 config->hca_attr.lro_timer_supported_periods[0]; 1381 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1382 config->lro.timeout); 1383 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1384 "required for coalescing is %d bytes", 1385 config->hca_attr.lro_min_mss_size); 1386 } 1387 #if defined(HAVE_MLX5DV_DR) && \ 1388 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1389 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1390 if (config->hca_attr.qos.sup && 1391 config->hca_attr.qos.flow_meter_old && 1392 config->dv_flow_en) { 1393 uint8_t reg_c_mask = 1394 config->hca_attr.qos.flow_meter_reg_c_ids; 1395 /* 1396 * Meter needs two REG_C's for color match and pre-sfx 1397 * flow match. Here get the REG_C for color match. 1398 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1399 */ 1400 reg_c_mask &= 0xfc; 1401 if (__builtin_popcount(reg_c_mask) < 1) { 1402 priv->mtr_en = 0; 1403 DRV_LOG(WARNING, "No available register for" 1404 " meter."); 1405 } else { 1406 /* 1407 * The meter color register is used by the 1408 * flow-hit feature as well. 1409 * The flow-hit feature must use REG_C_3 1410 * Prefer REG_C_3 if it is available. 1411 */ 1412 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1413 priv->mtr_color_reg = REG_C_3; 1414 else 1415 priv->mtr_color_reg = ffs(reg_c_mask) 1416 - 1 + REG_C_0; 1417 priv->mtr_en = 1; 1418 priv->mtr_reg_share = 1419 config->hca_attr.qos.flow_meter; 1420 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1421 priv->mtr_color_reg); 1422 } 1423 } 1424 if (config->hca_attr.qos.sup && 1425 config->hca_attr.qos.flow_meter_aso_sup) { 1426 uint32_t log_obj_size = 1427 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1428 if (log_obj_size >= 1429 config->hca_attr.qos.log_meter_aso_granularity && 1430 log_obj_size <= 1431 config->hca_attr.qos.log_meter_aso_max_alloc) 1432 sh->meter_aso_en = 1; 1433 } 1434 if (priv->mtr_en) { 1435 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1436 if (err) { 1437 err = -err; 1438 goto error; 1439 } 1440 } 1441 if (config->hca_attr.flow.tunnel_header_0_1) 1442 sh->tunnel_header_0_1 = 1; 1443 #endif 1444 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1445 if (config->hca_attr.flow_hit_aso && 1446 priv->mtr_color_reg == REG_C_3) { 1447 sh->flow_hit_aso_en = 1; 1448 err = mlx5_flow_aso_age_mng_init(sh); 1449 if (err) { 1450 err = -err; 1451 goto error; 1452 } 1453 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1454 } 1455 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1456 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1457 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1458 if (config->hca_attr.ct_offload && 1459 priv->mtr_color_reg == REG_C_3) { 1460 err = mlx5_flow_aso_ct_mng_init(sh); 1461 if (err) { 1462 err = -err; 1463 goto error; 1464 } 1465 DRV_LOG(DEBUG, "CT ASO is supported."); 1466 sh->ct_aso_en = 1; 1467 } 1468 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1469 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1470 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1471 config->dv_flow_en) { 1472 priv->sampler_en = 1; 1473 DRV_LOG(DEBUG, "Sampler enabled!"); 1474 } else { 1475 priv->sampler_en = 0; 1476 if (!config->hca_attr.log_max_ft_sampler_num) 1477 DRV_LOG(WARNING, 1478 "No available register for sampler."); 1479 else 1480 DRV_LOG(DEBUG, "DV flow is not supported!"); 1481 } 1482 #endif 1483 } 1484 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1485 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1486 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1487 config->cqe_comp = 0; 1488 } 1489 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1490 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1491 DRV_LOG(WARNING, "Flow Tag CQE compression" 1492 " format isn't supported."); 1493 config->cqe_comp = 0; 1494 } 1495 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1496 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1497 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1498 " format isn't supported."); 1499 config->cqe_comp = 0; 1500 } 1501 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1502 config->cqe_comp ? "" : "not "); 1503 if (config->tx_pp) { 1504 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1505 config->hca_attr.dev_freq_khz); 1506 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1507 config->hca_attr.qos.packet_pacing ? "" : "not "); 1508 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1509 config->hca_attr.cross_channel ? "" : "not "); 1510 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1511 config->hca_attr.wqe_index_ignore ? "" : "not "); 1512 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1513 config->hca_attr.non_wire_sq ? "" : "not "); 1514 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1515 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1516 config->hca_attr.log_max_static_sq_wq); 1517 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1518 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1519 if (!config->devx) { 1520 DRV_LOG(ERR, "DevX is required for packet pacing"); 1521 err = ENODEV; 1522 goto error; 1523 } 1524 if (!config->hca_attr.qos.packet_pacing) { 1525 DRV_LOG(ERR, "Packet pacing is not supported"); 1526 err = ENODEV; 1527 goto error; 1528 } 1529 if (!config->hca_attr.cross_channel) { 1530 DRV_LOG(ERR, "Cross channel operations are" 1531 " required for packet pacing"); 1532 err = ENODEV; 1533 goto error; 1534 } 1535 if (!config->hca_attr.wqe_index_ignore) { 1536 DRV_LOG(ERR, "WQE index ignore feature is" 1537 " required for packet pacing"); 1538 err = ENODEV; 1539 goto error; 1540 } 1541 if (!config->hca_attr.non_wire_sq) { 1542 DRV_LOG(ERR, "Non-wire SQ feature is" 1543 " required for packet pacing"); 1544 err = ENODEV; 1545 goto error; 1546 } 1547 if (!config->hca_attr.log_max_static_sq_wq) { 1548 DRV_LOG(ERR, "Static WQE SQ feature is" 1549 " required for packet pacing"); 1550 err = ENODEV; 1551 goto error; 1552 } 1553 if (!config->hca_attr.qos.wqe_rate_pp) { 1554 DRV_LOG(ERR, "WQE rate mode is required" 1555 " for packet pacing"); 1556 err = ENODEV; 1557 goto error; 1558 } 1559 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1560 DRV_LOG(ERR, "DevX does not provide UAR offset," 1561 " can't create queues for packet pacing"); 1562 err = ENODEV; 1563 goto error; 1564 #endif 1565 } 1566 if (config->devx) { 1567 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1568 1569 err = config->hca_attr.access_register_user ? 1570 mlx5_devx_cmd_register_read 1571 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1572 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1573 if (!err) { 1574 uint32_t ts_mode; 1575 1576 /* MTUTC register is read successfully. */ 1577 ts_mode = MLX5_GET(register_mtutc, reg, 1578 time_stamp_mode); 1579 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1580 config->rt_timestamp = 1; 1581 } else { 1582 /* Kernel does not support register reading. */ 1583 if (config->hca_attr.dev_freq_khz == 1584 (NS_PER_S / MS_PER_S)) 1585 config->rt_timestamp = 1; 1586 } 1587 } 1588 /* 1589 * If HW has bug working with tunnel packet decapsulation and 1590 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1591 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1592 */ 1593 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1594 config->hw_fcs_strip = 0; 1595 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1596 (config->hw_fcs_strip ? "" : "not ")); 1597 if (config->mprq.enabled && mprq) { 1598 if (config->mprq.stride_num_n && 1599 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1600 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1601 config->mprq.stride_num_n = 1602 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1603 mprq_min_stride_num_n), 1604 mprq_max_stride_num_n); 1605 DRV_LOG(WARNING, 1606 "the number of strides" 1607 " for Multi-Packet RQ is out of range," 1608 " setting default value (%u)", 1609 1 << config->mprq.stride_num_n); 1610 } 1611 if (config->mprq.stride_size_n && 1612 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1613 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1614 config->mprq.stride_size_n = 1615 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1616 mprq_min_stride_size_n), 1617 mprq_max_stride_size_n); 1618 DRV_LOG(WARNING, 1619 "the size of a stride" 1620 " for Multi-Packet RQ is out of range," 1621 " setting default value (%u)", 1622 1 << config->mprq.stride_size_n); 1623 } 1624 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1625 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1626 } else if (config->mprq.enabled && !mprq) { 1627 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1628 config->mprq.enabled = 0; 1629 } 1630 if (config->max_dump_files_num == 0) 1631 config->max_dump_files_num = 128; 1632 eth_dev = rte_eth_dev_allocate(name); 1633 if (eth_dev == NULL) { 1634 DRV_LOG(ERR, "can not allocate rte ethdev"); 1635 err = ENOMEM; 1636 goto error; 1637 } 1638 if (priv->representor) { 1639 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1640 eth_dev->data->representor_id = priv->representor_id; 1641 } 1642 priv->mp_id.port_id = eth_dev->data->port_id; 1643 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1644 /* 1645 * Store associated network device interface index. This index 1646 * is permanent throughout the lifetime of device. So, we may store 1647 * the ifindex here and use the cached value further. 1648 */ 1649 MLX5_ASSERT(spawn->ifindex); 1650 priv->if_index = spawn->ifindex; 1651 eth_dev->data->dev_private = priv; 1652 priv->dev_data = eth_dev->data; 1653 eth_dev->data->mac_addrs = priv->mac; 1654 eth_dev->device = dpdk_dev; 1655 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1656 /* Configure the first MAC address by default. */ 1657 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1658 DRV_LOG(ERR, 1659 "port %u cannot get MAC address, is mlx5_en" 1660 " loaded? (errno: %s)", 1661 eth_dev->data->port_id, strerror(rte_errno)); 1662 err = ENODEV; 1663 goto error; 1664 } 1665 DRV_LOG(INFO, 1666 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1667 eth_dev->data->port_id, 1668 mac.addr_bytes[0], mac.addr_bytes[1], 1669 mac.addr_bytes[2], mac.addr_bytes[3], 1670 mac.addr_bytes[4], mac.addr_bytes[5]); 1671 #ifdef RTE_LIBRTE_MLX5_DEBUG 1672 { 1673 char ifname[MLX5_NAMESIZE]; 1674 1675 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1676 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1677 eth_dev->data->port_id, ifname); 1678 else 1679 DRV_LOG(DEBUG, "port %u ifname is unknown", 1680 eth_dev->data->port_id); 1681 } 1682 #endif 1683 /* Get actual MTU if possible. */ 1684 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1685 if (err) { 1686 err = rte_errno; 1687 goto error; 1688 } 1689 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1690 priv->mtu); 1691 /* Initialize burst functions to prevent crashes before link-up. */ 1692 eth_dev->rx_pkt_burst = removed_rx_burst; 1693 eth_dev->tx_pkt_burst = removed_tx_burst; 1694 eth_dev->dev_ops = &mlx5_dev_ops; 1695 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1696 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1697 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1698 /* Register MAC address. */ 1699 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1700 if (config->vf && config->vf_nl_en) 1701 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1702 mlx5_ifindex(eth_dev), 1703 eth_dev->data->mac_addrs, 1704 MLX5_MAX_MAC_ADDRESSES); 1705 priv->ctrl_flows = 0; 1706 rte_spinlock_init(&priv->flow_list_lock); 1707 TAILQ_INIT(&priv->flow_meters); 1708 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1709 if (!priv->mtr_profile_tbl) 1710 goto error; 1711 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1712 mlx5_glue->dv_set_context_attr(sh->ctx, 1713 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1714 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1715 .alloc = &mlx5_alloc_verbs_buf, 1716 .free = &mlx5_free_verbs_buf, 1717 .data = sh, 1718 })); 1719 /* Bring Ethernet device up. */ 1720 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1721 eth_dev->data->port_id); 1722 mlx5_set_link_up(eth_dev); 1723 /* 1724 * Even though the interrupt handler is not installed yet, 1725 * interrupts will still trigger on the async_fd from 1726 * Verbs context returned by ibv_open_device(). 1727 */ 1728 mlx5_link_update(eth_dev, 0); 1729 #ifdef HAVE_MLX5DV_DR_ESWITCH 1730 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1731 (switch_info->representor || switch_info->master))) 1732 config->dv_esw_en = 0; 1733 #else 1734 config->dv_esw_en = 0; 1735 #endif 1736 /* Detect minimal data bytes to inline. */ 1737 mlx5_set_min_inline(spawn, config); 1738 /* Store device configuration on private structure. */ 1739 priv->config = *config; 1740 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1741 icfg[i].release_mem_en = !!config->reclaim_mode; 1742 if (config->reclaim_mode) 1743 icfg[i].per_core_cache = 0; 1744 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1745 if (!priv->flows[i]) 1746 goto error; 1747 } 1748 /* Create context for virtual machine VLAN workaround. */ 1749 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1750 if (config->dv_flow_en) { 1751 err = mlx5_alloc_shared_dr(priv); 1752 if (err) 1753 goto error; 1754 } 1755 if (config->devx && config->dv_flow_en && config->dest_tir) { 1756 priv->obj_ops = devx_obj_ops; 1757 priv->obj_ops.drop_action_create = 1758 ibv_obj_ops.drop_action_create; 1759 priv->obj_ops.drop_action_destroy = 1760 ibv_obj_ops.drop_action_destroy; 1761 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1762 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1763 #else 1764 if (config->dv_esw_en) 1765 priv->obj_ops.txq_obj_modify = 1766 ibv_obj_ops.txq_obj_modify; 1767 #endif 1768 /* Use specific wrappers for Tx object. */ 1769 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1770 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1771 mlx5_queue_counter_id_prepare(eth_dev); 1772 priv->obj_ops.lb_dummy_queue_create = 1773 mlx5_rxq_ibv_obj_dummy_lb_create; 1774 priv->obj_ops.lb_dummy_queue_release = 1775 mlx5_rxq_ibv_obj_dummy_lb_release; 1776 } else { 1777 priv->obj_ops = ibv_obj_ops; 1778 } 1779 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1780 if (!priv->drop_queue.hrxq) 1781 goto error; 1782 /* Supported Verbs flow priority number detection. */ 1783 err = mlx5_flow_discover_priorities(eth_dev); 1784 if (err < 0) { 1785 err = -err; 1786 goto error; 1787 } 1788 priv->config.flow_prio = err; 1789 if (!priv->config.dv_esw_en && 1790 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1791 DRV_LOG(WARNING, "metadata mode %u is not supported " 1792 "(no E-Switch)", priv->config.dv_xmeta_en); 1793 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1794 } 1795 mlx5_set_metadata_mask(eth_dev); 1796 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1797 !priv->sh->dv_regc0_mask) { 1798 DRV_LOG(ERR, "metadata mode %u is not supported " 1799 "(no metadata reg_c[0] is available)", 1800 priv->config.dv_xmeta_en); 1801 err = ENOTSUP; 1802 goto error; 1803 } 1804 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1805 mlx5_hrxq_create_cb, 1806 mlx5_hrxq_match_cb, 1807 mlx5_hrxq_remove_cb, 1808 mlx5_hrxq_clone_cb, 1809 mlx5_hrxq_clone_free_cb); 1810 if (!priv->hrxqs) 1811 goto error; 1812 rte_rwlock_init(&priv->ind_tbls_lock); 1813 /* Query availability of metadata reg_c's. */ 1814 err = mlx5_flow_discover_mreg_c(eth_dev); 1815 if (err < 0) { 1816 err = -err; 1817 goto error; 1818 } 1819 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1820 DRV_LOG(DEBUG, 1821 "port %u extensive metadata register is not supported", 1822 eth_dev->data->port_id); 1823 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1824 DRV_LOG(ERR, "metadata mode %u is not supported " 1825 "(no metadata registers available)", 1826 priv->config.dv_xmeta_en); 1827 err = ENOTSUP; 1828 goto error; 1829 } 1830 } 1831 if (priv->config.dv_flow_en && 1832 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1833 mlx5_flow_ext_mreg_supported(eth_dev) && 1834 priv->sh->dv_regc0_mask) { 1835 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1836 MLX5_FLOW_MREG_HTABLE_SZ, 1837 false, true, eth_dev, 1838 flow_dv_mreg_create_cb, 1839 flow_dv_mreg_match_cb, 1840 flow_dv_mreg_remove_cb, 1841 flow_dv_mreg_clone_cb, 1842 flow_dv_mreg_clone_free_cb); 1843 if (!priv->mreg_cp_tbl) { 1844 err = ENOMEM; 1845 goto error; 1846 } 1847 } 1848 rte_spinlock_init(&priv->shared_act_sl); 1849 mlx5_flow_counter_mode_config(eth_dev); 1850 if (priv->config.dv_flow_en) 1851 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1852 return eth_dev; 1853 error: 1854 if (priv) { 1855 if (priv->mreg_cp_tbl) 1856 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1857 if (priv->sh) 1858 mlx5_os_free_shared_dr(priv); 1859 if (priv->nl_socket_route >= 0) 1860 close(priv->nl_socket_route); 1861 if (priv->nl_socket_rdma >= 0) 1862 close(priv->nl_socket_rdma); 1863 if (priv->vmwa_context) 1864 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1865 if (eth_dev && priv->drop_queue.hrxq) 1866 mlx5_drop_action_destroy(eth_dev); 1867 if (priv->mtr_profile_tbl) 1868 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1869 if (own_domain_id) 1870 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1871 if (priv->hrxqs) 1872 mlx5_list_destroy(priv->hrxqs); 1873 mlx5_free(priv); 1874 if (eth_dev != NULL) 1875 eth_dev->data->dev_private = NULL; 1876 } 1877 if (eth_dev != NULL) { 1878 /* mac_addrs must not be freed alone because part of 1879 * dev_private 1880 **/ 1881 eth_dev->data->mac_addrs = NULL; 1882 rte_eth_dev_release_port(eth_dev); 1883 } 1884 if (sh) 1885 mlx5_free_shared_dev_ctx(sh); 1886 MLX5_ASSERT(err > 0); 1887 rte_errno = err; 1888 return NULL; 1889 } 1890 1891 /** 1892 * Comparison callback to sort device data. 1893 * 1894 * This is meant to be used with qsort(). 1895 * 1896 * @param a[in] 1897 * Pointer to pointer to first data object. 1898 * @param b[in] 1899 * Pointer to pointer to second data object. 1900 * 1901 * @return 1902 * 0 if both objects are equal, less than 0 if the first argument is less 1903 * than the second, greater than 0 otherwise. 1904 */ 1905 static int 1906 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1907 { 1908 const struct mlx5_switch_info *si_a = 1909 &((const struct mlx5_dev_spawn_data *)a)->info; 1910 const struct mlx5_switch_info *si_b = 1911 &((const struct mlx5_dev_spawn_data *)b)->info; 1912 int ret; 1913 1914 /* Master device first. */ 1915 ret = si_b->master - si_a->master; 1916 if (ret) 1917 return ret; 1918 /* Then representor devices. */ 1919 ret = si_b->representor - si_a->representor; 1920 if (ret) 1921 return ret; 1922 /* Unidentified devices come last in no specific order. */ 1923 if (!si_a->representor) 1924 return 0; 1925 /* Order representors by name. */ 1926 return si_a->port_name - si_b->port_name; 1927 } 1928 1929 /** 1930 * Match PCI information for possible slaves of bonding device. 1931 * 1932 * @param[in] ibv_dev 1933 * Pointer to Infiniband device structure. 1934 * @param[in] pci_dev 1935 * Pointer to primary PCI address structure to match. 1936 * @param[in] nl_rdma 1937 * Netlink RDMA group socket handle. 1938 * @param[in] owner 1939 * Rerepsentor owner PF index. 1940 * @param[out] bond_info 1941 * Pointer to bonding information. 1942 * 1943 * @return 1944 * negative value if no bonding device found, otherwise 1945 * positive index of slave PF in bonding. 1946 */ 1947 static int 1948 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1949 const struct rte_pci_addr *pci_dev, 1950 int nl_rdma, uint16_t owner, 1951 struct mlx5_bond_info *bond_info) 1952 { 1953 char ifname[IF_NAMESIZE + 1]; 1954 unsigned int ifindex; 1955 unsigned int np, i; 1956 FILE *bond_file = NULL, *file; 1957 int pf = -1; 1958 int ret; 1959 1960 /* 1961 * Try to get master device name. If something goes 1962 * wrong suppose the lack of kernel support and no 1963 * bonding devices. 1964 */ 1965 memset(bond_info, 0, sizeof(*bond_info)); 1966 if (nl_rdma < 0) 1967 return -1; 1968 if (!strstr(ibv_dev->name, "bond")) 1969 return -1; 1970 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1971 if (!np) 1972 return -1; 1973 /* 1974 * The Master device might not be on the predefined 1975 * port (not on port index 1, it is not garanted), 1976 * we have to scan all Infiniband device port and 1977 * find master. 1978 */ 1979 for (i = 1; i <= np; ++i) { 1980 /* Check whether Infiniband port is populated. */ 1981 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1982 if (!ifindex) 1983 continue; 1984 if (!if_indextoname(ifindex, ifname)) 1985 continue; 1986 /* Try to read bonding slave names from sysfs. */ 1987 MKSTR(slaves, 1988 "/sys/class/net/%s/master/bonding/slaves", ifname); 1989 bond_file = fopen(slaves, "r"); 1990 if (bond_file) 1991 break; 1992 } 1993 if (!bond_file) 1994 return -1; 1995 /* Use safe format to check maximal buffer length. */ 1996 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1997 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1998 char tmp_str[IF_NAMESIZE + 32]; 1999 struct rte_pci_addr pci_addr; 2000 struct mlx5_switch_info info; 2001 2002 /* Process slave interface names in the loop. */ 2003 snprintf(tmp_str, sizeof(tmp_str), 2004 "/sys/class/net/%s", ifname); 2005 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 2006 DRV_LOG(WARNING, "can not get PCI address" 2007 " for netdev \"%s\"", ifname); 2008 continue; 2009 } 2010 /* Slave interface PCI address match found. */ 2011 snprintf(tmp_str, sizeof(tmp_str), 2012 "/sys/class/net/%s/phys_port_name", ifname); 2013 file = fopen(tmp_str, "rb"); 2014 if (!file) 2015 break; 2016 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 2017 if (fscanf(file, "%32s", tmp_str) == 1) 2018 mlx5_translate_port_name(tmp_str, &info); 2019 fclose(file); 2020 /* Only process PF ports. */ 2021 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 2022 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 2023 continue; 2024 /* Check max bonding member. */ 2025 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 2026 DRV_LOG(WARNING, "bonding index out of range, " 2027 "please increase MLX5_BOND_MAX_PORTS: %s", 2028 tmp_str); 2029 break; 2030 } 2031 /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */ 2032 if (pci_dev->domain == pci_addr.domain && 2033 pci_dev->bus == pci_addr.bus && 2034 pci_dev->devid == pci_addr.devid && 2035 ((pci_dev->function == 0 && 2036 pci_dev->function + owner == pci_addr.function) || 2037 (pci_dev->function == owner && 2038 pci_addr.function == owner))) 2039 pf = info.port_name; 2040 /* Get ifindex. */ 2041 snprintf(tmp_str, sizeof(tmp_str), 2042 "/sys/class/net/%s/ifindex", ifname); 2043 file = fopen(tmp_str, "rb"); 2044 if (!file) 2045 break; 2046 ret = fscanf(file, "%u", &ifindex); 2047 fclose(file); 2048 if (ret != 1) 2049 break; 2050 /* Save bonding info. */ 2051 strncpy(bond_info->ports[info.port_name].ifname, ifname, 2052 sizeof(bond_info->ports[0].ifname)); 2053 bond_info->ports[info.port_name].pci_addr = pci_addr; 2054 bond_info->ports[info.port_name].ifindex = ifindex; 2055 bond_info->n_port++; 2056 } 2057 if (pf >= 0) { 2058 /* Get bond interface info */ 2059 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2060 bond_info->ifname); 2061 if (ret) 2062 DRV_LOG(ERR, "unable to get bond info: %s", 2063 strerror(rte_errno)); 2064 else 2065 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2066 ifindex, bond_info->ifindex, bond_info->ifname); 2067 } 2068 return pf; 2069 } 2070 2071 static void 2072 mlx5_os_config_default(struct mlx5_dev_config *config) 2073 { 2074 memset(config, 0, sizeof(*config)); 2075 config->mps = MLX5_ARG_UNSET; 2076 config->dbnc = MLX5_ARG_UNSET; 2077 config->rx_vec_en = 1; 2078 config->txq_inline_max = MLX5_ARG_UNSET; 2079 config->txq_inline_min = MLX5_ARG_UNSET; 2080 config->txq_inline_mpw = MLX5_ARG_UNSET; 2081 config->txqs_inline = MLX5_ARG_UNSET; 2082 config->vf_nl_en = 1; 2083 config->mr_ext_memseg_en = 1; 2084 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2085 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2086 config->dv_esw_en = 1; 2087 config->dv_flow_en = 1; 2088 config->decap_en = 1; 2089 config->log_hp_size = MLX5_ARG_UNSET; 2090 } 2091 2092 /** 2093 * Register a PCI device within bonding. 2094 * 2095 * This function spawns Ethernet devices out of a given PCI device and 2096 * bonding owner PF index. 2097 * 2098 * @param[in] pci_dev 2099 * PCI device information. 2100 * @param[in] req_eth_da 2101 * Requested ethdev device argument. 2102 * @param[in] owner_id 2103 * Requested owner PF port ID within bonding device, default to 0. 2104 * 2105 * @return 2106 * 0 on success, a negative errno value otherwise and rte_errno is set. 2107 */ 2108 static int 2109 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 2110 struct rte_eth_devargs *req_eth_da, 2111 uint16_t owner_id) 2112 { 2113 struct ibv_device **ibv_list; 2114 /* 2115 * Number of found IB Devices matching with requested PCI BDF. 2116 * nd != 1 means there are multiple IB devices over the same 2117 * PCI device and we have representors and master. 2118 */ 2119 unsigned int nd = 0; 2120 /* 2121 * Number of found IB device Ports. nd = 1 and np = 1..n means 2122 * we have the single multiport IB device, and there may be 2123 * representors attached to some of found ports. 2124 */ 2125 unsigned int np = 0; 2126 /* 2127 * Number of DPDK ethernet devices to Spawn - either over 2128 * multiple IB devices or multiple ports of single IB device. 2129 * Actually this is the number of iterations to spawn. 2130 */ 2131 unsigned int ns = 0; 2132 /* 2133 * Bonding device 2134 * < 0 - no bonding device (single one) 2135 * >= 0 - bonding device (value is slave PF index) 2136 */ 2137 int bd = -1; 2138 struct mlx5_dev_spawn_data *list = NULL; 2139 struct mlx5_dev_config dev_config; 2140 unsigned int dev_config_vf; 2141 struct rte_eth_devargs eth_da = *req_eth_da; 2142 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2143 struct mlx5_bond_info bond_info; 2144 int ret = -1; 2145 2146 errno = 0; 2147 ibv_list = mlx5_glue->get_device_list(&ret); 2148 if (!ibv_list) { 2149 rte_errno = errno ? errno : ENOSYS; 2150 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 2151 return -rte_errno; 2152 } 2153 /* 2154 * First scan the list of all Infiniband devices to find 2155 * matching ones, gathering into the list. 2156 */ 2157 struct ibv_device *ibv_match[ret + 1]; 2158 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2159 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2160 unsigned int i; 2161 2162 while (ret-- > 0) { 2163 struct rte_pci_addr pci_addr; 2164 2165 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 2166 bd = mlx5_device_bond_pci_match 2167 (ibv_list[ret], &owner_pci, nl_rdma, owner_id, 2168 &bond_info); 2169 if (bd >= 0) { 2170 /* 2171 * Bonding device detected. Only one match is allowed, 2172 * the bonding is supported over multi-port IB device, 2173 * there should be no matches on representor PCI 2174 * functions or non VF LAG bonding devices with 2175 * specified address. 2176 */ 2177 if (nd) { 2178 DRV_LOG(ERR, 2179 "multiple PCI match on bonding device" 2180 "\"%s\" found", ibv_list[ret]->name); 2181 rte_errno = ENOENT; 2182 ret = -rte_errno; 2183 goto exit; 2184 } 2185 /* Amend owner pci address if owner PF ID specified. */ 2186 if (eth_da.nb_representor_ports) 2187 owner_pci.function += owner_id; 2188 DRV_LOG(INFO, "PCI information matches for" 2189 " slave %d bonding device \"%s\"", 2190 bd, ibv_list[ret]->name); 2191 ibv_match[nd++] = ibv_list[ret]; 2192 break; 2193 } else { 2194 /* Bonding device not found. */ 2195 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2196 &pci_addr)) 2197 continue; 2198 if (owner_pci.domain != pci_addr.domain || 2199 owner_pci.bus != pci_addr.bus || 2200 owner_pci.devid != pci_addr.devid || 2201 owner_pci.function != pci_addr.function) 2202 continue; 2203 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2204 ibv_list[ret]->name); 2205 ibv_match[nd++] = ibv_list[ret]; 2206 } 2207 } 2208 ibv_match[nd] = NULL; 2209 if (!nd) { 2210 /* No device matches, just complain and bail out. */ 2211 DRV_LOG(WARNING, 2212 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2213 " are kernel drivers loaded?", 2214 owner_pci.domain, owner_pci.bus, 2215 owner_pci.devid, owner_pci.function); 2216 rte_errno = ENOENT; 2217 ret = -rte_errno; 2218 goto exit; 2219 } 2220 if (nd == 1) { 2221 /* 2222 * Found single matching device may have multiple ports. 2223 * Each port may be representor, we have to check the port 2224 * number and check the representors existence. 2225 */ 2226 if (nl_rdma >= 0) 2227 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2228 if (!np) 2229 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2230 " ports number", ibv_match[0]->name); 2231 if (bd >= 0 && !np) { 2232 DRV_LOG(ERR, "can not get ports" 2233 " for bonding device"); 2234 rte_errno = ENOENT; 2235 ret = -rte_errno; 2236 goto exit; 2237 } 2238 } 2239 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 2240 if (bd >= 0) { 2241 /* 2242 * This may happen if there is VF LAG kernel support and 2243 * application is compiled with older rdma_core library. 2244 */ 2245 DRV_LOG(ERR, 2246 "No kernel/verbs support for VF LAG bonding found."); 2247 rte_errno = ENOTSUP; 2248 ret = -rte_errno; 2249 goto exit; 2250 } 2251 #endif 2252 /* 2253 * Now we can determine the maximal 2254 * amount of devices to be spawned. 2255 */ 2256 list = mlx5_malloc(MLX5_MEM_ZERO, 2257 sizeof(struct mlx5_dev_spawn_data) * 2258 (np ? np : nd), 2259 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2260 if (!list) { 2261 DRV_LOG(ERR, "spawn data array allocation failure"); 2262 rte_errno = ENOMEM; 2263 ret = -rte_errno; 2264 goto exit; 2265 } 2266 if (bd >= 0 || np > 1) { 2267 /* 2268 * Single IB device with multiple ports found, 2269 * it may be E-Switch master device and representors. 2270 * We have to perform identification through the ports. 2271 */ 2272 MLX5_ASSERT(nl_rdma >= 0); 2273 MLX5_ASSERT(ns == 0); 2274 MLX5_ASSERT(nd == 1); 2275 MLX5_ASSERT(np); 2276 for (i = 1; i <= np; ++i) { 2277 list[ns].bond_info = &bond_info; 2278 list[ns].max_port = np; 2279 list[ns].phys_port = i; 2280 list[ns].phys_dev = ibv_match[0]; 2281 list[ns].eth_dev = NULL; 2282 list[ns].pci_dev = pci_dev; 2283 list[ns].pf_bond = bd; 2284 list[ns].ifindex = mlx5_nl_ifindex 2285 (nl_rdma, 2286 mlx5_os_get_dev_device_name 2287 (list[ns].phys_dev), i); 2288 if (!list[ns].ifindex) { 2289 /* 2290 * No network interface index found for the 2291 * specified port, it means there is no 2292 * representor on this port. It's OK, 2293 * there can be disabled ports, for example 2294 * if sriov_numvfs < sriov_totalvfs. 2295 */ 2296 continue; 2297 } 2298 ret = -1; 2299 if (nl_route >= 0) 2300 ret = mlx5_nl_switch_info 2301 (nl_route, 2302 list[ns].ifindex, 2303 &list[ns].info); 2304 if (ret || (!list[ns].info.representor && 2305 !list[ns].info.master)) { 2306 /* 2307 * We failed to recognize representors with 2308 * Netlink, let's try to perform the task 2309 * with sysfs. 2310 */ 2311 ret = mlx5_sysfs_switch_info 2312 (list[ns].ifindex, 2313 &list[ns].info); 2314 } 2315 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2316 if (!ret && bd >= 0) { 2317 switch (list[ns].info.name_type) { 2318 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2319 if (list[ns].info.port_name == bd) 2320 ns++; 2321 break; 2322 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2323 /* Fallthrough */ 2324 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2325 /* Fallthrough */ 2326 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2327 if (list[ns].info.pf_num == bd) 2328 ns++; 2329 break; 2330 default: 2331 break; 2332 } 2333 continue; 2334 } 2335 #endif 2336 if (!ret && (list[ns].info.representor ^ 2337 list[ns].info.master)) 2338 ns++; 2339 } 2340 if (!ns) { 2341 DRV_LOG(ERR, 2342 "unable to recognize master/representors" 2343 " on the IB device with multiple ports"); 2344 rte_errno = ENOENT; 2345 ret = -rte_errno; 2346 goto exit; 2347 } 2348 } else { 2349 /* 2350 * The existence of several matching entries (nd > 1) means 2351 * port representors have been instantiated. No existing Verbs 2352 * call nor sysfs entries can tell them apart, this can only 2353 * be done through Netlink calls assuming kernel drivers are 2354 * recent enough to support them. 2355 * 2356 * In the event of identification failure through Netlink, 2357 * try again through sysfs, then: 2358 * 2359 * 1. A single IB device matches (nd == 1) with single 2360 * port (np=0/1) and is not a representor, assume 2361 * no switch support. 2362 * 2363 * 2. Otherwise no safe assumptions can be made; 2364 * complain louder and bail out. 2365 */ 2366 for (i = 0; i != nd; ++i) { 2367 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2368 list[ns].bond_info = NULL; 2369 list[ns].max_port = 1; 2370 list[ns].phys_port = 1; 2371 list[ns].phys_dev = ibv_match[i]; 2372 list[ns].eth_dev = NULL; 2373 list[ns].pci_dev = pci_dev; 2374 list[ns].pf_bond = -1; 2375 list[ns].ifindex = 0; 2376 if (nl_rdma >= 0) 2377 list[ns].ifindex = mlx5_nl_ifindex 2378 (nl_rdma, 2379 mlx5_os_get_dev_device_name 2380 (list[ns].phys_dev), 1); 2381 if (!list[ns].ifindex) { 2382 char ifname[IF_NAMESIZE]; 2383 2384 /* 2385 * Netlink failed, it may happen with old 2386 * ib_core kernel driver (before 4.16). 2387 * We can assume there is old driver because 2388 * here we are processing single ports IB 2389 * devices. Let's try sysfs to retrieve 2390 * the ifindex. The method works for 2391 * master device only. 2392 */ 2393 if (nd > 1) { 2394 /* 2395 * Multiple devices found, assume 2396 * representors, can not distinguish 2397 * master/representor and retrieve 2398 * ifindex via sysfs. 2399 */ 2400 continue; 2401 } 2402 ret = mlx5_get_ifname_sysfs 2403 (ibv_match[i]->ibdev_path, ifname); 2404 if (!ret) 2405 list[ns].ifindex = 2406 if_nametoindex(ifname); 2407 if (!list[ns].ifindex) { 2408 /* 2409 * No network interface index found 2410 * for the specified device, it means 2411 * there it is neither representor 2412 * nor master. 2413 */ 2414 continue; 2415 } 2416 } 2417 ret = -1; 2418 if (nl_route >= 0) 2419 ret = mlx5_nl_switch_info 2420 (nl_route, 2421 list[ns].ifindex, 2422 &list[ns].info); 2423 if (ret || (!list[ns].info.representor && 2424 !list[ns].info.master)) { 2425 /* 2426 * We failed to recognize representors with 2427 * Netlink, let's try to perform the task 2428 * with sysfs. 2429 */ 2430 ret = mlx5_sysfs_switch_info 2431 (list[ns].ifindex, 2432 &list[ns].info); 2433 } 2434 if (!ret && (list[ns].info.representor ^ 2435 list[ns].info.master)) { 2436 ns++; 2437 } else if ((nd == 1) && 2438 !list[ns].info.representor && 2439 !list[ns].info.master) { 2440 /* 2441 * Single IB device with 2442 * one physical port and 2443 * attached network device. 2444 * May be SRIOV is not enabled 2445 * or there is no representors. 2446 */ 2447 DRV_LOG(INFO, "no E-Switch support detected"); 2448 ns++; 2449 break; 2450 } 2451 } 2452 if (!ns) { 2453 DRV_LOG(ERR, 2454 "unable to recognize master/representors" 2455 " on the multiple IB devices"); 2456 rte_errno = ENOENT; 2457 ret = -rte_errno; 2458 goto exit; 2459 } 2460 /* 2461 * New kernels may add the switch_id attribute for the case 2462 * there is no E-Switch and we wrongly recognized the 2463 * only device as master. Override this if there is the 2464 * single device with single port and new device name 2465 * format present. 2466 */ 2467 if (nd == 1 && 2468 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2469 list[0].info.master = 0; 2470 list[0].info.representor = 0; 2471 } 2472 } 2473 MLX5_ASSERT(ns); 2474 /* 2475 * Sort list to probe devices in natural order for users convenience 2476 * (i.e. master first, then representors from lowest to highest ID). 2477 */ 2478 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2479 /* Device specific configuration. */ 2480 switch (pci_dev->id.device_id) { 2481 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2482 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2483 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2484 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2485 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2486 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2487 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2488 dev_config_vf = 1; 2489 break; 2490 default: 2491 dev_config_vf = 0; 2492 break; 2493 } 2494 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2495 /* Set devargs default values. */ 2496 if (eth_da.nb_mh_controllers == 0) { 2497 eth_da.nb_mh_controllers = 1; 2498 eth_da.mh_controllers[0] = 0; 2499 } 2500 if (eth_da.nb_ports == 0 && ns > 0) { 2501 if (list[0].pf_bond >= 0 && list[0].info.representor) 2502 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2503 pci_dev->device.devargs->args); 2504 eth_da.nb_ports = 1; 2505 eth_da.ports[0] = list[0].info.pf_num; 2506 } 2507 if (eth_da.nb_representor_ports == 0) { 2508 eth_da.nb_representor_ports = 1; 2509 eth_da.representor_ports[0] = 0; 2510 } 2511 } 2512 for (i = 0; i != ns; ++i) { 2513 uint32_t restore; 2514 2515 /* Default configuration. */ 2516 mlx5_os_config_default(&dev_config); 2517 dev_config.vf = dev_config_vf; 2518 dev_config.allow_duplicate_pattern = 1; 2519 list[i].numa_node = pci_dev->device.numa_node; 2520 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2521 &list[i], 2522 &dev_config, 2523 ð_da); 2524 if (!list[i].eth_dev) { 2525 if (rte_errno != EBUSY && rte_errno != EEXIST) 2526 break; 2527 /* Device is disabled or already spawned. Ignore it. */ 2528 continue; 2529 } 2530 restore = list[i].eth_dev->data->dev_flags; 2531 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2532 /* Restore non-PCI flags cleared by the above call. */ 2533 list[i].eth_dev->data->dev_flags |= restore; 2534 rte_eth_dev_probing_finish(list[i].eth_dev); 2535 } 2536 if (i != ns) { 2537 DRV_LOG(ERR, 2538 "probe of PCI device " PCI_PRI_FMT " aborted after" 2539 " encountering an error: %s", 2540 owner_pci.domain, owner_pci.bus, 2541 owner_pci.devid, owner_pci.function, 2542 strerror(rte_errno)); 2543 ret = -rte_errno; 2544 /* Roll back. */ 2545 while (i--) { 2546 if (!list[i].eth_dev) 2547 continue; 2548 mlx5_dev_close(list[i].eth_dev); 2549 /* mac_addrs must not be freed because in dev_private */ 2550 list[i].eth_dev->data->mac_addrs = NULL; 2551 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2552 } 2553 /* Restore original error. */ 2554 rte_errno = -ret; 2555 } else { 2556 ret = 0; 2557 } 2558 exit: 2559 /* 2560 * Do the routine cleanup: 2561 * - close opened Netlink sockets 2562 * - free allocated spawn data array 2563 * - free the Infiniband device list 2564 */ 2565 if (nl_rdma >= 0) 2566 close(nl_rdma); 2567 if (nl_route >= 0) 2568 close(nl_route); 2569 if (list) 2570 mlx5_free(list); 2571 MLX5_ASSERT(ibv_list); 2572 mlx5_glue->free_device_list(ibv_list); 2573 return ret; 2574 } 2575 2576 static int 2577 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2578 struct rte_eth_devargs *eth_da) 2579 { 2580 int ret = 0; 2581 2582 if (dev->devargs == NULL) 2583 return 0; 2584 memset(eth_da, 0, sizeof(*eth_da)); 2585 /* Parse representor information first from class argument. */ 2586 if (dev->devargs->cls_str) 2587 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2588 if (ret != 0) { 2589 DRV_LOG(ERR, "failed to parse device arguments: %s", 2590 dev->devargs->cls_str); 2591 return -rte_errno; 2592 } 2593 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2594 /* Parse legacy device argument */ 2595 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2596 if (ret) { 2597 DRV_LOG(ERR, "failed to parse device arguments: %s", 2598 dev->devargs->args); 2599 return -rte_errno; 2600 } 2601 } 2602 return 0; 2603 } 2604 2605 /** 2606 * Callback to register a PCI device. 2607 * 2608 * This function spawns Ethernet devices out of a given PCI device. 2609 * 2610 * @param[in] pci_dev 2611 * PCI device information. 2612 * 2613 * @return 2614 * 0 on success, a negative errno value otherwise and rte_errno is set. 2615 */ 2616 static int 2617 mlx5_os_pci_probe(struct rte_pci_device *pci_dev) 2618 { 2619 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2620 int ret = 0; 2621 uint16_t p; 2622 2623 ret = mlx5_os_parse_eth_devargs(&pci_dev->device, ð_da); 2624 if (ret != 0) 2625 return ret; 2626 2627 if (eth_da.nb_ports > 0) { 2628 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2629 for (p = 0; p < eth_da.nb_ports; p++) 2630 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2631 eth_da.ports[p]); 2632 } else { 2633 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2634 } 2635 return ret; 2636 } 2637 2638 /* Probe a single SF device on auxiliary bus, no representor support. */ 2639 static int 2640 mlx5_os_auxiliary_probe(struct rte_device *dev) 2641 { 2642 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2643 struct mlx5_dev_config config; 2644 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2645 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2646 struct rte_eth_dev *eth_dev; 2647 int ret = 0; 2648 2649 /* Parse ethdev devargs. */ 2650 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2651 if (ret != 0) 2652 return ret; 2653 /* Set default config data. */ 2654 mlx5_os_config_default(&config); 2655 config.sf = 1; 2656 /* Init spawn data. */ 2657 spawn.max_port = 1; 2658 spawn.phys_port = 1; 2659 spawn.phys_dev = mlx5_os_get_ibv_dev(dev); 2660 if (spawn.phys_dev == NULL) 2661 return -rte_errno; 2662 ret = mlx5_auxiliary_get_ifindex(dev->name); 2663 if (ret < 0) { 2664 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2665 return ret; 2666 } 2667 spawn.ifindex = ret; 2668 spawn.numa_node = dev->numa_node; 2669 /* Spawn device. */ 2670 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2671 if (eth_dev == NULL) 2672 return -rte_errno; 2673 /* Post create. */ 2674 eth_dev->intr_handle = &adev->intr_handle; 2675 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2676 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2677 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2678 eth_dev->data->numa_node = dev->numa_node; 2679 } 2680 rte_eth_dev_probing_finish(eth_dev); 2681 return 0; 2682 } 2683 2684 /** 2685 * Net class driver callback to probe a device. 2686 * 2687 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2688 * 2689 * @param[in] dev 2690 * Pointer to the generic device. 2691 * 2692 * @return 2693 * 0 on success, the function cannot fail. 2694 */ 2695 int 2696 mlx5_os_net_probe(struct rte_device *dev) 2697 { 2698 int ret; 2699 2700 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2701 mlx5_pmd_socket_init(); 2702 ret = mlx5_init_once(); 2703 if (ret) { 2704 DRV_LOG(ERR, "unable to init PMD global data: %s", 2705 strerror(rte_errno)); 2706 return -rte_errno; 2707 } 2708 if (mlx5_dev_is_pci(dev)) 2709 return mlx5_os_pci_probe(RTE_DEV_TO_PCI(dev)); 2710 else 2711 return mlx5_os_auxiliary_probe(dev); 2712 } 2713 2714 static int 2715 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2716 { 2717 char *env; 2718 int value; 2719 2720 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2721 /* Get environment variable to store. */ 2722 env = getenv(MLX5_SHUT_UP_BF); 2723 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2724 if (config->dbnc == MLX5_ARG_UNSET) 2725 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2726 else 2727 setenv(MLX5_SHUT_UP_BF, 2728 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2729 return value; 2730 } 2731 2732 static void 2733 mlx5_restore_doorbell_mapping_env(int value) 2734 { 2735 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2736 /* Restore the original environment variable state. */ 2737 if (value == MLX5_ARG_UNSET) 2738 unsetenv(MLX5_SHUT_UP_BF); 2739 else 2740 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2741 } 2742 2743 /** 2744 * Extract pdn of PD object using DV API. 2745 * 2746 * @param[in] pd 2747 * Pointer to the verbs PD object. 2748 * @param[out] pdn 2749 * Pointer to the PD object number variable. 2750 * 2751 * @return 2752 * 0 on success, error value otherwise. 2753 */ 2754 int 2755 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2756 { 2757 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2758 struct mlx5dv_obj obj; 2759 struct mlx5dv_pd pd_info; 2760 int ret = 0; 2761 2762 obj.pd.in = pd; 2763 obj.pd.out = &pd_info; 2764 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2765 if (ret) { 2766 DRV_LOG(DEBUG, "Fail to get PD object info"); 2767 return ret; 2768 } 2769 *pdn = pd_info.pdn; 2770 return 0; 2771 #else 2772 (void)pd; 2773 (void)pdn; 2774 return -ENOTSUP; 2775 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2776 } 2777 2778 /** 2779 * Function API to open IB device. 2780 * 2781 * This function calls the Linux glue APIs to open a device. 2782 * 2783 * @param[in] spawn 2784 * Pointer to the IB device attributes (name, port, etc). 2785 * @param[out] config 2786 * Pointer to device configuration structure. 2787 * @param[out] sh 2788 * Pointer to shared context structure. 2789 * 2790 * @return 2791 * 0 on success, a positive error value otherwise. 2792 */ 2793 int 2794 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2795 const struct mlx5_dev_config *config, 2796 struct mlx5_dev_ctx_shared *sh) 2797 { 2798 int dbmap_env; 2799 int err = 0; 2800 2801 pthread_mutex_init(&sh->txpp.mutex, NULL); 2802 /* 2803 * Configure environment variable "MLX5_BF_SHUT_UP" 2804 * before the device creation. The rdma_core library 2805 * checks the variable at device creation and 2806 * stores the result internally. 2807 */ 2808 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2809 /* Try to open IB device with DV first, then usual Verbs. */ 2810 errno = 0; 2811 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2812 if (sh->ctx) { 2813 sh->devx = 1; 2814 DRV_LOG(DEBUG, "DevX is supported"); 2815 /* The device is created, no need for environment. */ 2816 mlx5_restore_doorbell_mapping_env(dbmap_env); 2817 } else { 2818 /* The environment variable is still configured. */ 2819 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2820 err = errno ? errno : ENODEV; 2821 /* 2822 * The environment variable is not needed anymore, 2823 * all device creation attempts are completed. 2824 */ 2825 mlx5_restore_doorbell_mapping_env(dbmap_env); 2826 if (!sh->ctx) 2827 return err; 2828 DRV_LOG(DEBUG, "DevX is NOT supported"); 2829 err = 0; 2830 } 2831 if (!err && sh->ctx) { 2832 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2833 mlx5_glue->dv_set_context_attr(sh->ctx, 2834 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2835 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2836 .alloc = &mlx5_alloc_verbs_buf, 2837 .free = &mlx5_free_verbs_buf, 2838 .data = sh, 2839 })); 2840 } 2841 return err; 2842 } 2843 2844 /** 2845 * Install shared asynchronous device events handler. 2846 * This function is implemented to support event sharing 2847 * between multiple ports of single IB device. 2848 * 2849 * @param sh 2850 * Pointer to mlx5_dev_ctx_shared object. 2851 */ 2852 void 2853 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2854 { 2855 int ret; 2856 int flags; 2857 2858 sh->intr_handle.fd = -1; 2859 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2860 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2861 F_SETFL, flags | O_NONBLOCK); 2862 if (ret) { 2863 DRV_LOG(INFO, "failed to change file descriptor async event" 2864 " queue"); 2865 } else { 2866 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2867 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2868 if (rte_intr_callback_register(&sh->intr_handle, 2869 mlx5_dev_interrupt_handler, sh)) { 2870 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2871 sh->intr_handle.fd = -1; 2872 } 2873 } 2874 if (sh->devx) { 2875 #ifdef HAVE_IBV_DEVX_ASYNC 2876 sh->intr_handle_devx.fd = -1; 2877 sh->devx_comp = 2878 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2879 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2880 if (!devx_comp) { 2881 DRV_LOG(INFO, "failed to allocate devx_comp."); 2882 return; 2883 } 2884 flags = fcntl(devx_comp->fd, F_GETFL); 2885 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2886 if (ret) { 2887 DRV_LOG(INFO, "failed to change file descriptor" 2888 " devx comp"); 2889 return; 2890 } 2891 sh->intr_handle_devx.fd = devx_comp->fd; 2892 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2893 if (rte_intr_callback_register(&sh->intr_handle_devx, 2894 mlx5_dev_interrupt_handler_devx, sh)) { 2895 DRV_LOG(INFO, "Fail to install the devx shared" 2896 " interrupt."); 2897 sh->intr_handle_devx.fd = -1; 2898 } 2899 #endif /* HAVE_IBV_DEVX_ASYNC */ 2900 } 2901 } 2902 2903 /** 2904 * Uninstall shared asynchronous device events handler. 2905 * This function is implemented to support event sharing 2906 * between multiple ports of single IB device. 2907 * 2908 * @param dev 2909 * Pointer to mlx5_dev_ctx_shared object. 2910 */ 2911 void 2912 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2913 { 2914 if (sh->intr_handle.fd >= 0) 2915 mlx5_intr_callback_unregister(&sh->intr_handle, 2916 mlx5_dev_interrupt_handler, sh); 2917 #ifdef HAVE_IBV_DEVX_ASYNC 2918 if (sh->intr_handle_devx.fd >= 0) 2919 rte_intr_callback_unregister(&sh->intr_handle_devx, 2920 mlx5_dev_interrupt_handler_devx, sh); 2921 if (sh->devx_comp) 2922 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2923 #endif 2924 } 2925 2926 /** 2927 * Read statistics by a named counter. 2928 * 2929 * @param[in] priv 2930 * Pointer to the private device data structure. 2931 * @param[in] ctr_name 2932 * Pointer to the name of the statistic counter to read 2933 * @param[out] stat 2934 * Pointer to read statistic value. 2935 * @return 2936 * 0 on success and stat is valud, 1 if failed to read the value 2937 * rte_errno is set. 2938 * 2939 */ 2940 int 2941 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2942 uint64_t *stat) 2943 { 2944 int fd; 2945 2946 if (priv->sh) { 2947 if (priv->q_counters != NULL && 2948 strcmp(ctr_name, "out_of_buffer") == 0) 2949 return mlx5_devx_cmd_queue_counter_query 2950 (priv->q_counters, 0, (uint32_t *)stat); 2951 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2952 priv->sh->ibdev_path, 2953 priv->dev_port, 2954 ctr_name); 2955 fd = open(path, O_RDONLY); 2956 /* 2957 * in switchdev the file location is not per port 2958 * but rather in <ibdev_path>/hw_counters/<file_name>. 2959 */ 2960 if (fd == -1) { 2961 MKSTR(path1, "%s/hw_counters/%s", 2962 priv->sh->ibdev_path, 2963 ctr_name); 2964 fd = open(path1, O_RDONLY); 2965 } 2966 if (fd != -1) { 2967 char buf[21] = {'\0'}; 2968 ssize_t n = read(fd, buf, sizeof(buf)); 2969 2970 close(fd); 2971 if (n != -1) { 2972 *stat = strtoull(buf, NULL, 10); 2973 return 0; 2974 } 2975 } 2976 } 2977 *stat = 0; 2978 return 1; 2979 } 2980 2981 /** 2982 * Set the reg_mr and dereg_mr call backs 2983 * 2984 * @param reg_mr_cb[out] 2985 * Pointer to reg_mr func 2986 * @param dereg_mr_cb[out] 2987 * Pointer to dereg_mr func 2988 * 2989 */ 2990 void 2991 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2992 mlx5_dereg_mr_t *dereg_mr_cb) 2993 { 2994 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 2995 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 2996 } 2997 2998 /** 2999 * Remove a MAC address from device 3000 * 3001 * @param dev 3002 * Pointer to Ethernet device structure. 3003 * @param index 3004 * MAC address index. 3005 */ 3006 void 3007 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 3008 { 3009 struct mlx5_priv *priv = dev->data->dev_private; 3010 const int vf = priv->config.vf; 3011 3012 if (vf) 3013 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 3014 mlx5_ifindex(dev), priv->mac_own, 3015 &dev->data->mac_addrs[index], index); 3016 } 3017 3018 /** 3019 * Adds a MAC address to the device 3020 * 3021 * @param dev 3022 * Pointer to Ethernet device structure. 3023 * @param mac_addr 3024 * MAC address to register. 3025 * @param index 3026 * MAC address index. 3027 * 3028 * @return 3029 * 0 on success, a negative errno value otherwise 3030 */ 3031 int 3032 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 3033 uint32_t index) 3034 { 3035 struct mlx5_priv *priv = dev->data->dev_private; 3036 const int vf = priv->config.vf; 3037 int ret = 0; 3038 3039 if (vf) 3040 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 3041 mlx5_ifindex(dev), priv->mac_own, 3042 mac, index); 3043 return ret; 3044 } 3045 3046 /** 3047 * Modify a VF MAC address 3048 * 3049 * @param priv 3050 * Pointer to device private data. 3051 * @param mac_addr 3052 * MAC address to modify into. 3053 * @param iface_idx 3054 * Net device interface index 3055 * @param vf_index 3056 * VF index 3057 * 3058 * @return 3059 * 0 on success, a negative errno value otherwise 3060 */ 3061 int 3062 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 3063 unsigned int iface_idx, 3064 struct rte_ether_addr *mac_addr, 3065 int vf_index) 3066 { 3067 return mlx5_nl_vf_mac_addr_modify 3068 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 3069 } 3070 3071 /** 3072 * Set device promiscuous mode 3073 * 3074 * @param dev 3075 * Pointer to Ethernet device structure. 3076 * @param enable 3077 * 0 - promiscuous is disabled, otherwise - enabled 3078 * 3079 * @return 3080 * 0 on success, a negative error value otherwise 3081 */ 3082 int 3083 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 3084 { 3085 struct mlx5_priv *priv = dev->data->dev_private; 3086 3087 return mlx5_nl_promisc(priv->nl_socket_route, 3088 mlx5_ifindex(dev), !!enable); 3089 } 3090 3091 /** 3092 * Set device promiscuous mode 3093 * 3094 * @param dev 3095 * Pointer to Ethernet device structure. 3096 * @param enable 3097 * 0 - all multicase is disabled, otherwise - enabled 3098 * 3099 * @return 3100 * 0 on success, a negative error value otherwise 3101 */ 3102 int 3103 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 3104 { 3105 struct mlx5_priv *priv = dev->data->dev_private; 3106 3107 return mlx5_nl_allmulti(priv->nl_socket_route, 3108 mlx5_ifindex(dev), !!enable); 3109 } 3110 3111 /** 3112 * Flush device MAC addresses 3113 * 3114 * @param dev 3115 * Pointer to Ethernet device structure. 3116 * 3117 */ 3118 void 3119 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 3120 { 3121 struct mlx5_priv *priv = dev->data->dev_private; 3122 3123 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 3124 dev->data->mac_addrs, 3125 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 3126 } 3127