1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /* rte flow indexed pool configuration. */ 71 static struct mlx5_indexed_pool_config icfg[] = { 72 { 73 .size = sizeof(struct rte_flow), 74 .trunk_size = 64, 75 .need_lock = 1, 76 .release_mem_en = 0, 77 .malloc = mlx5_malloc, 78 .free = mlx5_free, 79 .per_core_cache = 0, 80 .type = "ctl_flow_ipool", 81 }, 82 { 83 .size = sizeof(struct rte_flow), 84 .trunk_size = 64, 85 .grow_trunk = 3, 86 .grow_shift = 2, 87 .need_lock = 1, 88 .release_mem_en = 0, 89 .malloc = mlx5_malloc, 90 .free = mlx5_free, 91 .per_core_cache = 1 << 14, 92 .type = "rte_flow_ipool", 93 }, 94 { 95 .size = sizeof(struct rte_flow), 96 .trunk_size = 64, 97 .grow_trunk = 3, 98 .grow_shift = 2, 99 .need_lock = 1, 100 .release_mem_en = 0, 101 .malloc = mlx5_malloc, 102 .free = mlx5_free, 103 .per_core_cache = 0, 104 .type = "mcp_flow_ipool", 105 }, 106 }; 107 108 /** 109 * Set the completion channel file descriptor interrupt as non-blocking. 110 * 111 * @param[in] rxq_obj 112 * Pointer to RQ channel object, which includes the channel fd 113 * 114 * @param[out] fd 115 * The file descriptor (representing the interrupt) used in this channel. 116 * 117 * @return 118 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 119 */ 120 int 121 mlx5_os_set_nonblock_channel_fd(int fd) 122 { 123 int flags; 124 125 flags = fcntl(fd, F_GETFL); 126 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 127 } 128 129 /** 130 * Get mlx5 device attributes. The glue function query_device_ex() is called 131 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 132 * device attributes from the glue out parameter. 133 * 134 * @param cdev 135 * Pointer to mlx5 device. 136 * 137 * @param device_attr 138 * Pointer to mlx5 device attributes. 139 * 140 * @return 141 * 0 on success, a negative errno value otherwise and rte_errno is set. 142 */ 143 int 144 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, 145 struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_context *ctx = cdev->ctx; 149 struct ibv_device_attr_ex attr_ex; 150 151 memset(device_attr, 0, sizeof(*device_attr)); 152 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 153 if (err) { 154 rte_errno = errno; 155 return -rte_errno; 156 } 157 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 158 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 159 device_attr->max_sge = attr_ex.orig_attr.max_sge; 160 device_attr->max_cq = attr_ex.orig_attr.max_cq; 161 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 162 device_attr->max_mr = attr_ex.orig_attr.max_mr; 163 device_attr->max_pd = attr_ex.orig_attr.max_pd; 164 device_attr->max_qp = attr_ex.orig_attr.max_qp; 165 device_attr->max_srq = attr_ex.orig_attr.max_srq; 166 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 167 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 168 device_attr->max_rwq_indirection_table_size = 169 attr_ex.rss_caps.max_rwq_indirection_table_size; 170 device_attr->max_tso = attr_ex.tso_caps.max_tso; 171 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 172 173 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 174 #ifdef HAVE_IBV_MLX5_MOD_SWP 175 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 176 #endif 177 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 178 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 179 #endif 180 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 181 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 182 #endif 183 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 184 if (err) { 185 rte_errno = errno; 186 return -rte_errno; 187 } 188 189 device_attr->flags = dv_attr.flags; 190 device_attr->comp_mask = dv_attr.comp_mask; 191 #ifdef HAVE_IBV_MLX5_MOD_SWP 192 device_attr->sw_parsing_offloads = 193 dv_attr.sw_parsing_caps.sw_parsing_offloads; 194 #endif 195 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 196 device_attr->min_single_stride_log_num_of_bytes = 197 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 198 device_attr->max_single_stride_log_num_of_bytes = 199 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 200 device_attr->min_single_wqe_log_num_of_strides = 201 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 202 device_attr->max_single_wqe_log_num_of_strides = 203 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 204 device_attr->stride_supported_qpts = 205 dv_attr.striding_rq_caps.supported_qpts; 206 #endif 207 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 208 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 209 #endif 210 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 211 sizeof(device_attr->fw_ver)); 212 213 return 0; 214 } 215 216 /** 217 * Detect misc5 support or not 218 * 219 * @param[in] priv 220 * Device private data pointer 221 */ 222 #ifdef HAVE_MLX5DV_DR 223 static void 224 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 225 { 226 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 227 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 228 * Case: IPv4--->UDP--->VxLAN--->vni 229 */ 230 void *tbl; 231 struct mlx5_flow_dv_match_params matcher_mask; 232 void *match_m; 233 void *matcher; 234 void *headers_m; 235 void *misc5_m; 236 uint32_t *tunnel_header_m; 237 struct mlx5dv_flow_matcher_attr dv_attr; 238 239 memset(&matcher_mask, 0, sizeof(matcher_mask)); 240 matcher_mask.size = sizeof(matcher_mask.buf); 241 match_m = matcher_mask.buf; 242 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 243 misc5_m = MLX5_ADDR_OF(fte_match_param, 244 match_m, misc_parameters_5); 245 tunnel_header_m = (uint32_t *) 246 MLX5_ADDR_OF(fte_match_set_misc5, 247 misc5_m, tunnel_header_1); 248 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 249 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 250 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 251 *tunnel_header_m = 0xffffff; 252 253 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 254 if (!tbl) { 255 DRV_LOG(INFO, "No SW steering support"); 256 return; 257 } 258 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 259 dv_attr.match_mask = (void *)&matcher_mask, 260 dv_attr.match_criteria_enable = 261 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 262 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 263 dv_attr.priority = 3; 264 #ifdef HAVE_MLX5DV_DR_ESWITCH 265 void *misc2_m; 266 if (priv->config.dv_esw_en) { 267 /* FDB enabled reg_c_0 */ 268 dv_attr.match_criteria_enable |= 269 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 270 misc2_m = MLX5_ADDR_OF(fte_match_param, 271 match_m, misc_parameters_2); 272 MLX5_SET(fte_match_set_misc2, misc2_m, 273 metadata_reg_c_0, 0xffff); 274 } 275 #endif 276 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx, 277 &dv_attr, tbl); 278 if (matcher) { 279 priv->sh->misc5_cap = 1; 280 mlx5_glue->dv_destroy_flow_matcher(matcher); 281 } 282 mlx5_glue->dr_destroy_flow_tbl(tbl); 283 #else 284 RTE_SET_USED(priv); 285 #endif 286 } 287 #endif 288 289 /** 290 * Initialize DR related data within private structure. 291 * Routine checks the reference counter and does actual 292 * resources creation/initialization only if counter is zero. 293 * 294 * @param[in] priv 295 * Pointer to the private device data structure. 296 * 297 * @return 298 * Zero on success, positive error code otherwise. 299 */ 300 static int 301 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 302 { 303 struct mlx5_dev_ctx_shared *sh = priv->sh; 304 char s[MLX5_NAME_SIZE] __rte_unused; 305 int err; 306 307 MLX5_ASSERT(sh && sh->refcnt); 308 if (sh->refcnt > 1) 309 return 0; 310 err = mlx5_alloc_table_hash_list(priv); 311 if (err) 312 goto error; 313 /* The resources below are only valid with DV support. */ 314 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 315 /* Init port id action list. */ 316 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 317 sh->port_id_action_list = mlx5_list_create(s, sh, true, 318 flow_dv_port_id_create_cb, 319 flow_dv_port_id_match_cb, 320 flow_dv_port_id_remove_cb, 321 flow_dv_port_id_clone_cb, 322 flow_dv_port_id_clone_free_cb); 323 if (!sh->port_id_action_list) 324 goto error; 325 /* Init push vlan action list. */ 326 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 327 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 328 flow_dv_push_vlan_create_cb, 329 flow_dv_push_vlan_match_cb, 330 flow_dv_push_vlan_remove_cb, 331 flow_dv_push_vlan_clone_cb, 332 flow_dv_push_vlan_clone_free_cb); 333 if (!sh->push_vlan_action_list) 334 goto error; 335 /* Init sample action list. */ 336 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 337 sh->sample_action_list = mlx5_list_create(s, sh, true, 338 flow_dv_sample_create_cb, 339 flow_dv_sample_match_cb, 340 flow_dv_sample_remove_cb, 341 flow_dv_sample_clone_cb, 342 flow_dv_sample_clone_free_cb); 343 if (!sh->sample_action_list) 344 goto error; 345 /* Init dest array action list. */ 346 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 347 sh->dest_array_list = mlx5_list_create(s, sh, true, 348 flow_dv_dest_array_create_cb, 349 flow_dv_dest_array_match_cb, 350 flow_dv_dest_array_remove_cb, 351 flow_dv_dest_array_clone_cb, 352 flow_dv_dest_array_clone_free_cb); 353 if (!sh->dest_array_list) 354 goto error; 355 /* Init shared flex parsers list, no need lcore_share */ 356 snprintf(s, sizeof(s), "%s_flex_parsers_list", sh->ibdev_name); 357 sh->flex_parsers_dv = mlx5_list_create(s, sh, false, 358 mlx5_flex_parser_create_cb, 359 mlx5_flex_parser_match_cb, 360 mlx5_flex_parser_remove_cb, 361 mlx5_flex_parser_clone_cb, 362 mlx5_flex_parser_clone_free_cb); 363 if (!sh->flex_parsers_dv) 364 goto error; 365 #endif 366 #ifdef HAVE_MLX5DV_DR 367 void *domain; 368 369 /* Reference counter is zero, we should initialize structures. */ 370 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 371 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 372 if (!domain) { 373 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 374 err = errno; 375 goto error; 376 } 377 sh->rx_domain = domain; 378 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 379 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 380 if (!domain) { 381 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 382 err = errno; 383 goto error; 384 } 385 sh->tx_domain = domain; 386 #ifdef HAVE_MLX5DV_DR_ESWITCH 387 if (priv->config.dv_esw_en) { 388 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 389 MLX5DV_DR_DOMAIN_TYPE_FDB); 390 if (!domain) { 391 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 392 err = errno; 393 goto error; 394 } 395 sh->fdb_domain = domain; 396 } 397 /* 398 * The drop action is just some dummy placeholder in rdma-core. It 399 * does not belong to domains and has no any attributes, and, can be 400 * shared by the entire device. 401 */ 402 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 403 if (!sh->dr_drop_action) { 404 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 405 err = errno; 406 goto error; 407 } 408 #endif 409 if (!sh->tunnel_hub && priv->config.dv_miss_info) 410 err = mlx5_alloc_tunnel_hub(sh); 411 if (err) { 412 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 413 goto error; 414 } 415 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 416 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 417 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 418 if (sh->fdb_domain) 419 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 420 } 421 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 422 if (!priv->config.allow_duplicate_pattern) { 423 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 424 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 425 #endif 426 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 427 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 428 if (sh->fdb_domain) 429 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 430 } 431 432 __mlx5_discovery_misc5_cap(priv); 433 #endif /* HAVE_MLX5DV_DR */ 434 sh->default_miss_action = 435 mlx5_glue->dr_create_flow_action_default_miss(); 436 if (!sh->default_miss_action) 437 DRV_LOG(WARNING, "Default miss action is not supported."); 438 LIST_INIT(&sh->shared_rxqs); 439 return 0; 440 error: 441 /* Rollback the created objects. */ 442 if (sh->rx_domain) { 443 mlx5_glue->dr_destroy_domain(sh->rx_domain); 444 sh->rx_domain = NULL; 445 } 446 if (sh->tx_domain) { 447 mlx5_glue->dr_destroy_domain(sh->tx_domain); 448 sh->tx_domain = NULL; 449 } 450 if (sh->fdb_domain) { 451 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 452 sh->fdb_domain = NULL; 453 } 454 if (sh->dr_drop_action) { 455 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 456 sh->dr_drop_action = NULL; 457 } 458 if (sh->pop_vlan_action) { 459 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 460 sh->pop_vlan_action = NULL; 461 } 462 if (sh->encaps_decaps) { 463 mlx5_hlist_destroy(sh->encaps_decaps); 464 sh->encaps_decaps = NULL; 465 } 466 if (sh->modify_cmds) { 467 mlx5_hlist_destroy(sh->modify_cmds); 468 sh->modify_cmds = NULL; 469 } 470 if (sh->tag_table) { 471 /* tags should be destroyed with flow before. */ 472 mlx5_hlist_destroy(sh->tag_table); 473 sh->tag_table = NULL; 474 } 475 if (sh->tunnel_hub) { 476 mlx5_release_tunnel_hub(sh, priv->dev_port); 477 sh->tunnel_hub = NULL; 478 } 479 mlx5_free_table_hash_list(priv); 480 if (sh->port_id_action_list) { 481 mlx5_list_destroy(sh->port_id_action_list); 482 sh->port_id_action_list = NULL; 483 } 484 if (sh->push_vlan_action_list) { 485 mlx5_list_destroy(sh->push_vlan_action_list); 486 sh->push_vlan_action_list = NULL; 487 } 488 if (sh->sample_action_list) { 489 mlx5_list_destroy(sh->sample_action_list); 490 sh->sample_action_list = NULL; 491 } 492 if (sh->dest_array_list) { 493 mlx5_list_destroy(sh->dest_array_list); 494 sh->dest_array_list = NULL; 495 } 496 return err; 497 } 498 499 /** 500 * Destroy DR related data within private structure. 501 * 502 * @param[in] priv 503 * Pointer to the private device data structure. 504 */ 505 void 506 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 507 { 508 struct mlx5_dev_ctx_shared *sh = priv->sh; 509 510 MLX5_ASSERT(sh && sh->refcnt); 511 if (sh->refcnt > 1) 512 return; 513 MLX5_ASSERT(LIST_EMPTY(&sh->shared_rxqs)); 514 #ifdef HAVE_MLX5DV_DR 515 if (sh->rx_domain) { 516 mlx5_glue->dr_destroy_domain(sh->rx_domain); 517 sh->rx_domain = NULL; 518 } 519 if (sh->tx_domain) { 520 mlx5_glue->dr_destroy_domain(sh->tx_domain); 521 sh->tx_domain = NULL; 522 } 523 #ifdef HAVE_MLX5DV_DR_ESWITCH 524 if (sh->fdb_domain) { 525 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 526 sh->fdb_domain = NULL; 527 } 528 if (sh->dr_drop_action) { 529 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 530 sh->dr_drop_action = NULL; 531 } 532 #endif 533 if (sh->pop_vlan_action) { 534 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 535 sh->pop_vlan_action = NULL; 536 } 537 #endif /* HAVE_MLX5DV_DR */ 538 if (sh->default_miss_action) 539 mlx5_glue->destroy_flow_action 540 (sh->default_miss_action); 541 if (sh->encaps_decaps) { 542 mlx5_hlist_destroy(sh->encaps_decaps); 543 sh->encaps_decaps = NULL; 544 } 545 if (sh->modify_cmds) { 546 mlx5_hlist_destroy(sh->modify_cmds); 547 sh->modify_cmds = NULL; 548 } 549 if (sh->tag_table) { 550 /* tags should be destroyed with flow before. */ 551 mlx5_hlist_destroy(sh->tag_table); 552 sh->tag_table = NULL; 553 } 554 if (sh->tunnel_hub) { 555 mlx5_release_tunnel_hub(sh, priv->dev_port); 556 sh->tunnel_hub = NULL; 557 } 558 mlx5_free_table_hash_list(priv); 559 if (sh->port_id_action_list) { 560 mlx5_list_destroy(sh->port_id_action_list); 561 sh->port_id_action_list = NULL; 562 } 563 if (sh->push_vlan_action_list) { 564 mlx5_list_destroy(sh->push_vlan_action_list); 565 sh->push_vlan_action_list = NULL; 566 } 567 if (sh->sample_action_list) { 568 mlx5_list_destroy(sh->sample_action_list); 569 sh->sample_action_list = NULL; 570 } 571 if (sh->dest_array_list) { 572 mlx5_list_destroy(sh->dest_array_list); 573 sh->dest_array_list = NULL; 574 } 575 } 576 577 /** 578 * Initialize shared data between primary and secondary process. 579 * 580 * A memzone is reserved by primary process and secondary processes attach to 581 * the memzone. 582 * 583 * @return 584 * 0 on success, a negative errno value otherwise and rte_errno is set. 585 */ 586 static int 587 mlx5_init_shared_data(void) 588 { 589 const struct rte_memzone *mz; 590 int ret = 0; 591 592 rte_spinlock_lock(&mlx5_shared_data_lock); 593 if (mlx5_shared_data == NULL) { 594 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 595 /* Allocate shared memory. */ 596 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 597 sizeof(*mlx5_shared_data), 598 SOCKET_ID_ANY, 0); 599 if (mz == NULL) { 600 DRV_LOG(ERR, 601 "Cannot allocate mlx5 shared data"); 602 ret = -rte_errno; 603 goto error; 604 } 605 mlx5_shared_data = mz->addr; 606 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 607 rte_spinlock_init(&mlx5_shared_data->lock); 608 } else { 609 /* Lookup allocated shared memory. */ 610 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 611 if (mz == NULL) { 612 DRV_LOG(ERR, 613 "Cannot attach mlx5 shared data"); 614 ret = -rte_errno; 615 goto error; 616 } 617 mlx5_shared_data = mz->addr; 618 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 619 } 620 } 621 error: 622 rte_spinlock_unlock(&mlx5_shared_data_lock); 623 return ret; 624 } 625 626 /** 627 * PMD global initialization. 628 * 629 * Independent from individual device, this function initializes global 630 * per-PMD data structures distinguishing primary and secondary processes. 631 * Hence, each initialization is called once per a process. 632 * 633 * @return 634 * 0 on success, a negative errno value otherwise and rte_errno is set. 635 */ 636 static int 637 mlx5_init_once(void) 638 { 639 struct mlx5_shared_data *sd; 640 struct mlx5_local_data *ld = &mlx5_local_data; 641 int ret = 0; 642 643 if (mlx5_init_shared_data()) 644 return -rte_errno; 645 sd = mlx5_shared_data; 646 MLX5_ASSERT(sd); 647 rte_spinlock_lock(&sd->lock); 648 switch (rte_eal_process_type()) { 649 case RTE_PROC_PRIMARY: 650 if (sd->init_done) 651 break; 652 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 653 mlx5_mp_os_primary_handle); 654 if (ret) 655 goto out; 656 sd->init_done = true; 657 break; 658 case RTE_PROC_SECONDARY: 659 if (ld->init_done) 660 break; 661 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 662 mlx5_mp_os_secondary_handle); 663 if (ret) 664 goto out; 665 ++sd->secondary_cnt; 666 ld->init_done = true; 667 break; 668 default: 669 break; 670 } 671 out: 672 rte_spinlock_unlock(&sd->lock); 673 return ret; 674 } 675 676 /** 677 * DR flow drop action support detect. 678 * 679 * @param dev 680 * Pointer to rte_eth_dev structure. 681 * 682 */ 683 static void 684 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 685 { 686 #ifdef HAVE_MLX5DV_DR 687 struct mlx5_priv *priv = dev->data->dev_private; 688 689 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action) 690 return; 691 /** 692 * DR supports drop action placeholder when it is supported; 693 * otherwise, use the queue drop action. 694 */ 695 if (!priv->sh->drop_action_check_flag) { 696 if (!mlx5_flow_discover_dr_action_support(dev)) 697 priv->sh->dr_drop_action_en = 1; 698 priv->sh->drop_action_check_flag = 1; 699 } 700 if (priv->sh->dr_drop_action_en) 701 priv->root_drop_action = priv->sh->dr_drop_action; 702 else 703 priv->root_drop_action = priv->drop_queue.hrxq->action; 704 #endif 705 } 706 707 static void 708 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 709 { 710 struct mlx5_priv *priv = dev->data->dev_private; 711 void *ctx = priv->sh->cdev->ctx; 712 713 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 714 if (!priv->q_counters) { 715 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 716 struct ibv_wq *wq; 717 718 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 719 "by DevX - fall-back to use the kernel driver global " 720 "queue counter.", dev->data->port_id); 721 /* Create WQ by kernel and query its queue counter ID. */ 722 if (cq) { 723 wq = mlx5_glue->create_wq(ctx, 724 &(struct ibv_wq_init_attr){ 725 .wq_type = IBV_WQT_RQ, 726 .max_wr = 1, 727 .max_sge = 1, 728 .pd = priv->sh->cdev->pd, 729 .cq = cq, 730 }); 731 if (wq) { 732 /* Counter is assigned only on RDY state. */ 733 int ret = mlx5_glue->modify_wq(wq, 734 &(struct ibv_wq_attr){ 735 .attr_mask = IBV_WQ_ATTR_STATE, 736 .wq_state = IBV_WQS_RDY, 737 }); 738 739 if (ret == 0) 740 mlx5_devx_cmd_wq_query(wq, 741 &priv->counter_set_id); 742 claim_zero(mlx5_glue->destroy_wq(wq)); 743 } 744 claim_zero(mlx5_glue->destroy_cq(cq)); 745 } 746 } else { 747 priv->counter_set_id = priv->q_counters->id; 748 } 749 if (priv->counter_set_id == 0) 750 DRV_LOG(INFO, "Part of the port %d statistics will not be " 751 "available.", dev->data->port_id); 752 } 753 754 /** 755 * Check if representor spawn info match devargs. 756 * 757 * @param spawn 758 * Verbs device parameters (name, port, switch_info) to spawn. 759 * @param eth_da 760 * Device devargs to probe. 761 * 762 * @return 763 * Match result. 764 */ 765 static bool 766 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 767 struct rte_eth_devargs *eth_da) 768 { 769 struct mlx5_switch_info *switch_info = &spawn->info; 770 unsigned int p, f; 771 uint16_t id; 772 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 773 eth_da->type); 774 775 switch (eth_da->type) { 776 case RTE_ETH_REPRESENTOR_SF: 777 if (!(spawn->info.port_name == -1 && 778 switch_info->name_type == 779 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 780 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 781 rte_errno = EBUSY; 782 return false; 783 } 784 break; 785 case RTE_ETH_REPRESENTOR_VF: 786 /* Allows HPF representor index -1 as exception. */ 787 if (!(spawn->info.port_name == -1 && 788 switch_info->name_type == 789 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 790 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 791 rte_errno = EBUSY; 792 return false; 793 } 794 break; 795 case RTE_ETH_REPRESENTOR_NONE: 796 rte_errno = EBUSY; 797 return false; 798 default: 799 rte_errno = ENOTSUP; 800 DRV_LOG(ERR, "unsupported representor type"); 801 return false; 802 } 803 /* Check representor ID: */ 804 for (p = 0; p < eth_da->nb_ports; ++p) { 805 if (spawn->pf_bond < 0) { 806 /* For non-LAG mode, allow and ignore pf. */ 807 switch_info->pf_num = eth_da->ports[p]; 808 repr_id = mlx5_representor_id_encode(switch_info, 809 eth_da->type); 810 } 811 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 812 id = MLX5_REPRESENTOR_ID 813 (eth_da->ports[p], eth_da->type, 814 eth_da->representor_ports[f]); 815 if (repr_id == id) 816 return true; 817 } 818 } 819 rte_errno = EBUSY; 820 return false; 821 } 822 823 /** 824 * Spawn an Ethernet device from Verbs information. 825 * 826 * @param dpdk_dev 827 * Backing DPDK device. 828 * @param spawn 829 * Verbs device parameters (name, port, switch_info) to spawn. 830 * @param config 831 * Device configuration parameters. 832 * @param eth_da 833 * Device arguments. 834 * 835 * @return 836 * A valid Ethernet device object on success, NULL otherwise and rte_errno 837 * is set. The following errors are defined: 838 * 839 * EBUSY: device is not supposed to be spawned. 840 * EEXIST: device is already spawned 841 */ 842 static struct rte_eth_dev * 843 mlx5_dev_spawn(struct rte_device *dpdk_dev, 844 struct mlx5_dev_spawn_data *spawn, 845 struct mlx5_dev_config *config, 846 struct rte_eth_devargs *eth_da) 847 { 848 const struct mlx5_switch_info *switch_info = &spawn->info; 849 struct mlx5_dev_ctx_shared *sh = NULL; 850 struct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr; 851 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; 852 struct rte_eth_dev *eth_dev = NULL; 853 struct mlx5_priv *priv = NULL; 854 int err = 0; 855 unsigned int hw_padding = 0; 856 unsigned int mps; 857 unsigned int mpls_en = 0; 858 unsigned int swp = 0; 859 unsigned int mprq = 0; 860 struct rte_ether_addr mac; 861 char name[RTE_ETH_NAME_MAX_LEN]; 862 int own_domain_id = 0; 863 uint16_t port_id; 864 struct mlx5_port_info vport_info = { .query_flags = 0 }; 865 int nl_rdma = -1; 866 int i; 867 868 /* Determine if this port representor is supposed to be spawned. */ 869 if (switch_info->representor && dpdk_dev->devargs && 870 !mlx5_representor_match(spawn, eth_da)) 871 return NULL; 872 /* Build device name. */ 873 if (spawn->pf_bond < 0) { 874 /* Single device. */ 875 if (!switch_info->representor) 876 strlcpy(name, dpdk_dev->name, sizeof(name)); 877 else 878 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 879 dpdk_dev->name, 880 switch_info->name_type == 881 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 882 switch_info->port_name); 883 } else { 884 /* Bonding device. */ 885 if (!switch_info->representor) { 886 err = snprintf(name, sizeof(name), "%s_%s", 887 dpdk_dev->name, spawn->phys_dev_name); 888 } else { 889 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 890 dpdk_dev->name, spawn->phys_dev_name, 891 switch_info->ctrl_num, 892 switch_info->pf_num, 893 switch_info->name_type == 894 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 895 switch_info->port_name); 896 } 897 } 898 if (err >= (int)sizeof(name)) 899 DRV_LOG(WARNING, "device name overflow %s", name); 900 /* check if the device is already spawned */ 901 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 902 rte_errno = EEXIST; 903 return NULL; 904 } 905 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 906 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 907 struct mlx5_mp_id mp_id; 908 909 eth_dev = rte_eth_dev_attach_secondary(name); 910 if (eth_dev == NULL) { 911 DRV_LOG(ERR, "can not attach rte ethdev"); 912 rte_errno = ENOMEM; 913 return NULL; 914 } 915 eth_dev->device = dpdk_dev; 916 eth_dev->dev_ops = &mlx5_dev_sec_ops; 917 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 918 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 919 err = mlx5_proc_priv_init(eth_dev); 920 if (err) 921 return NULL; 922 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 923 /* Receive command fd from primary process */ 924 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 925 if (err < 0) 926 goto err_secondary; 927 /* Remap UAR for Tx queues. */ 928 err = mlx5_tx_uar_init_secondary(eth_dev, err); 929 if (err) 930 goto err_secondary; 931 /* 932 * Ethdev pointer is still required as input since 933 * the primary device is not accessible from the 934 * secondary process. 935 */ 936 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 937 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 938 return eth_dev; 939 err_secondary: 940 mlx5_dev_close(eth_dev); 941 return NULL; 942 } 943 /* Process parameters. */ 944 err = mlx5_args(config, dpdk_dev->devargs); 945 if (err) { 946 DRV_LOG(ERR, "failed to process device arguments: %s", 947 strerror(rte_errno)); 948 return NULL; 949 } 950 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 951 if (!sh) 952 return NULL; 953 /* Update final values for devargs before check sibling config. */ 954 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 955 if (config->dv_flow_en) { 956 DRV_LOG(WARNING, "DV flow is not supported."); 957 config->dv_flow_en = 0; 958 } 959 #endif 960 #ifdef HAVE_MLX5DV_DR_ESWITCH 961 if (!(hca_attr->eswitch_manager && config->dv_flow_en && sh->esw_mode)) 962 config->dv_esw_en = 0; 963 #else 964 config->dv_esw_en = 0; 965 #endif 966 if (config->dv_miss_info && config->dv_esw_en) 967 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 968 if (!config->dv_esw_en && 969 config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 970 DRV_LOG(WARNING, 971 "Metadata mode %u is not supported (no E-Switch).", 972 config->dv_xmeta_en); 973 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 974 } 975 /* Check sibling device configurations. */ 976 err = mlx5_dev_check_sibling_config(sh, config, dpdk_dev); 977 if (err) 978 goto error; 979 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 980 config->dest_tir = 1; 981 #endif 982 /* 983 * Multi-packet send is supported by ConnectX-4 Lx PF as well 984 * as all ConnectX-5 devices. 985 */ 986 if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 987 if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 988 DRV_LOG(DEBUG, "enhanced MPW is supported"); 989 mps = MLX5_MPW_ENHANCED; 990 } else { 991 DRV_LOG(DEBUG, "MPW is supported"); 992 mps = MLX5_MPW; 993 } 994 } else { 995 DRV_LOG(DEBUG, "MPW isn't supported"); 996 mps = MLX5_MPW_DISABLED; 997 } 998 #ifdef HAVE_IBV_MLX5_MOD_SWP 999 if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1000 swp = sh->device_attr.sw_parsing_offloads; 1001 DRV_LOG(DEBUG, "SWP support: %u", swp); 1002 #endif 1003 config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP | 1004 MLX5_SW_PARSING_TSO_CAP); 1005 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1006 if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1007 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1008 sh->device_attr.min_single_stride_log_num_of_bytes); 1009 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1010 sh->device_attr.max_single_stride_log_num_of_bytes); 1011 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1012 sh->device_attr.min_single_wqe_log_num_of_strides); 1013 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1014 sh->device_attr.max_single_wqe_log_num_of_strides); 1015 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1016 sh->device_attr.stride_supported_qpts); 1017 DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %d", 1018 config->mprq.log_min_stride_wqe_size); 1019 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1020 mprq = 1; 1021 config->mprq.log_min_stride_size = 1022 sh->device_attr.min_single_stride_log_num_of_bytes; 1023 config->mprq.log_max_stride_size = 1024 sh->device_attr.max_single_stride_log_num_of_bytes; 1025 config->mprq.log_min_stride_num = 1026 sh->device_attr.min_single_wqe_log_num_of_strides; 1027 config->mprq.log_max_stride_num = 1028 sh->device_attr.max_single_wqe_log_num_of_strides; 1029 } 1030 #endif 1031 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1032 if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1033 config->tunnel_en = sh->device_attr.tunnel_offloads_caps & 1034 (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN | 1035 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE | 1036 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE); 1037 } 1038 if (config->tunnel_en) { 1039 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s", 1040 config->tunnel_en & 1041 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "", 1042 config->tunnel_en & 1043 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "", 1044 config->tunnel_en & 1045 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : "" 1046 ); 1047 } else { 1048 DRV_LOG(DEBUG, "tunnel offloading is not supported"); 1049 } 1050 #else 1051 DRV_LOG(WARNING, 1052 "tunnel offloading disabled due to old OFED/rdma-core version"); 1053 #endif 1054 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1055 mpls_en = ((sh->device_attr.tunnel_offloads_caps & 1056 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1057 (sh->device_attr.tunnel_offloads_caps & 1058 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1059 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1060 mpls_en ? "" : "not "); 1061 #else 1062 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1063 " old OFED/rdma-core version or firmware configuration"); 1064 #endif 1065 config->mpls_en = mpls_en; 1066 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1067 /* Check port status. */ 1068 if (spawn->phys_port <= UINT8_MAX) { 1069 /* Legacy Verbs api only support u8 port number. */ 1070 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port, 1071 &port_attr); 1072 if (err) { 1073 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1074 goto error; 1075 } 1076 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1077 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1078 err = EINVAL; 1079 goto error; 1080 } 1081 } else if (nl_rdma >= 0) { 1082 /* IB doesn't allow more than 255 ports, must be Ethernet. */ 1083 err = mlx5_nl_port_state(nl_rdma, 1084 spawn->phys_dev_name, 1085 spawn->phys_port); 1086 if (err < 0) { 1087 DRV_LOG(INFO, "Failed to get netlink port state: %s", 1088 strerror(rte_errno)); 1089 err = -rte_errno; 1090 goto error; 1091 } 1092 port_attr.state = (enum ibv_port_state)err; 1093 } 1094 if (port_attr.state != IBV_PORT_ACTIVE) 1095 DRV_LOG(INFO, "port is not active: \"%s\" (%d)", 1096 mlx5_glue->port_state_str(port_attr.state), 1097 port_attr.state); 1098 /* Allocate private eth device data. */ 1099 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1100 sizeof(*priv), 1101 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1102 if (priv == NULL) { 1103 DRV_LOG(ERR, "priv allocation failure"); 1104 err = ENOMEM; 1105 goto error; 1106 } 1107 priv->sh = sh; 1108 priv->dev_port = spawn->phys_port; 1109 priv->pci_dev = spawn->pci_dev; 1110 priv->mtu = RTE_ETHER_MTU; 1111 /* Some internal functions rely on Netlink sockets, open them now. */ 1112 priv->nl_socket_rdma = nl_rdma; 1113 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1114 priv->representor = !!switch_info->representor; 1115 priv->master = !!switch_info->master; 1116 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1117 priv->vport_meta_tag = 0; 1118 priv->vport_meta_mask = 0; 1119 priv->pf_bond = spawn->pf_bond; 1120 1121 DRV_LOG(DEBUG, 1122 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1123 priv->dev_port, dpdk_dev->bus->name, 1124 priv->pci_dev ? priv->pci_dev->name : "NONE", 1125 priv->master, priv->representor, priv->pf_bond); 1126 1127 /* 1128 * If we have E-Switch we should determine the vport attributes. 1129 * E-Switch may use either source vport field or reg_c[0] metadata 1130 * register to match on vport index. The engaged part of metadata 1131 * register is defined by mask. 1132 */ 1133 if (sh->esw_mode) { 1134 err = mlx5_glue->devx_port_query(sh->cdev->ctx, 1135 spawn->phys_port, 1136 &vport_info); 1137 if (err) { 1138 DRV_LOG(WARNING, 1139 "Cannot query devx port %d on device %s", 1140 spawn->phys_port, spawn->phys_dev_name); 1141 vport_info.query_flags = 0; 1142 } 1143 } 1144 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1145 priv->vport_meta_tag = vport_info.vport_meta_tag; 1146 priv->vport_meta_mask = vport_info.vport_meta_mask; 1147 if (!priv->vport_meta_mask) { 1148 DRV_LOG(ERR, 1149 "vport zero mask for port %d on bonding device %s", 1150 spawn->phys_port, spawn->phys_dev_name); 1151 err = ENOTSUP; 1152 goto error; 1153 } 1154 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1155 DRV_LOG(ERR, 1156 "Invalid vport tag for port %d on bonding device %s", 1157 spawn->phys_port, spawn->phys_dev_name); 1158 err = ENOTSUP; 1159 goto error; 1160 } 1161 } 1162 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1163 priv->vport_id = vport_info.vport_id; 1164 } else if (spawn->pf_bond >= 0 && sh->esw_mode) { 1165 DRV_LOG(ERR, 1166 "Cannot deduce vport index for port %d on bonding device %s", 1167 spawn->phys_port, spawn->phys_dev_name); 1168 err = ENOTSUP; 1169 goto error; 1170 } else { 1171 /* 1172 * Suppose vport index in compatible way. Kernel/rdma_core 1173 * support single E-Switch per PF configurations only and 1174 * vport_id field contains the vport index for associated VF, 1175 * which is deduced from representor port name. 1176 * For example, let's have the IB device port 10, it has 1177 * attached network device eth0, which has port name attribute 1178 * pf0vf2, we can deduce the VF number as 2, and set vport index 1179 * as 3 (2+1). This assigning schema should be changed if the 1180 * multiple E-Switch instances per PF configurations or/and PCI 1181 * subfunctions are added. 1182 */ 1183 priv->vport_id = switch_info->representor ? 1184 switch_info->port_name + 1 : -1; 1185 } 1186 priv->representor_id = mlx5_representor_id_encode(switch_info, 1187 eth_da->type); 1188 /* 1189 * Look for sibling devices in order to reuse their switch domain 1190 * if any, otherwise allocate one. 1191 */ 1192 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1193 const struct mlx5_priv *opriv = 1194 rte_eth_devices[port_id].data->dev_private; 1195 1196 if (!opriv || 1197 opriv->sh != priv->sh || 1198 opriv->domain_id == 1199 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1200 continue; 1201 priv->domain_id = opriv->domain_id; 1202 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1203 priv->dev_port, priv->domain_id); 1204 break; 1205 } 1206 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1207 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1208 if (err) { 1209 err = rte_errno; 1210 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1211 strerror(rte_errno)); 1212 goto error; 1213 } 1214 own_domain_id = 1; 1215 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1216 priv->dev_port, priv->domain_id); 1217 } 1218 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1219 IBV_DEVICE_RAW_IP_CSUM); 1220 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1221 (config->hw_csum ? "" : "not ")); 1222 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1223 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1224 DRV_LOG(DEBUG, "counters are not supported"); 1225 #endif 1226 config->ind_table_max_size = 1227 sh->device_attr.max_rwq_indirection_table_size; 1228 /* 1229 * Remove this check once DPDK supports larger/variable 1230 * indirection tables. 1231 */ 1232 if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512) 1233 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512; 1234 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1235 config->ind_table_max_size); 1236 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1237 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1238 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1239 (config->hw_vlan_strip ? "" : "not ")); 1240 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1241 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1242 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1243 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1244 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1245 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1246 IBV_DEVICE_PCI_WRITE_END_PADDING); 1247 #endif 1248 if (config->hw_padding && !hw_padding) { 1249 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1250 config->hw_padding = 0; 1251 } else if (config->hw_padding) { 1252 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1253 } 1254 config->tso = (sh->device_attr.max_tso > 0 && 1255 (sh->device_attr.tso_supported_qpts & 1256 (1 << IBV_QPT_RAW_PACKET))); 1257 if (config->tso) 1258 config->tso_max_payload_sz = sh->device_attr.max_tso; 1259 /* 1260 * MPW is disabled by default, while the Enhanced MPW is enabled 1261 * by default. 1262 */ 1263 if (config->mps == MLX5_ARG_UNSET) 1264 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1265 MLX5_MPW_DISABLED; 1266 else 1267 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1268 DRV_LOG(INFO, "%sMPS is %s", 1269 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1270 config->mps == MLX5_MPW ? "legacy " : "", 1271 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1272 if (sh->cdev->config.devx) { 1273 sh->steering_format_version = hca_attr->steering_format_version; 1274 /* Check for LRO support. */ 1275 if (config->dest_tir && hca_attr->lro_cap && 1276 config->dv_flow_en) { 1277 /* TBD check tunnel lro caps. */ 1278 config->lro.supported = hca_attr->lro_cap; 1279 DRV_LOG(DEBUG, "Device supports LRO"); 1280 /* 1281 * If LRO timeout is not configured by application, 1282 * use the minimal supported value. 1283 */ 1284 if (!config->lro.timeout) 1285 config->lro.timeout = 1286 hca_attr->lro_timer_supported_periods[0]; 1287 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1288 config->lro.timeout); 1289 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1290 "required for coalescing is %d bytes", 1291 hca_attr->lro_min_mss_size); 1292 } 1293 #if defined(HAVE_MLX5DV_DR) && \ 1294 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1295 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1296 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_old && 1297 config->dv_flow_en) { 1298 uint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids; 1299 /* 1300 * Meter needs two REG_C's for color match and pre-sfx 1301 * flow match. Here get the REG_C for color match. 1302 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1303 */ 1304 reg_c_mask &= 0xfc; 1305 if (__builtin_popcount(reg_c_mask) < 1) { 1306 priv->mtr_en = 0; 1307 DRV_LOG(WARNING, "No available register for" 1308 " meter."); 1309 } else { 1310 /* 1311 * The meter color register is used by the 1312 * flow-hit feature as well. 1313 * The flow-hit feature must use REG_C_3 1314 * Prefer REG_C_3 if it is available. 1315 */ 1316 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1317 priv->mtr_color_reg = REG_C_3; 1318 else 1319 priv->mtr_color_reg = ffs(reg_c_mask) 1320 - 1 + REG_C_0; 1321 priv->mtr_en = 1; 1322 priv->mtr_reg_share = hca_attr->qos.flow_meter; 1323 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1324 priv->mtr_color_reg); 1325 } 1326 } 1327 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) { 1328 uint32_t log_obj_size = 1329 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1330 if (log_obj_size >= 1331 hca_attr->qos.log_meter_aso_granularity && 1332 log_obj_size <= 1333 hca_attr->qos.log_meter_aso_max_alloc) 1334 sh->meter_aso_en = 1; 1335 } 1336 if (priv->mtr_en) { 1337 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1338 if (err) { 1339 err = -err; 1340 goto error; 1341 } 1342 } 1343 if (hca_attr->flow.tunnel_header_0_1) 1344 sh->tunnel_header_0_1 = 1; 1345 #endif 1346 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1347 if (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) { 1348 sh->flow_hit_aso_en = 1; 1349 err = mlx5_flow_aso_age_mng_init(sh); 1350 if (err) { 1351 err = -err; 1352 goto error; 1353 } 1354 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1355 } 1356 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1357 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1358 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1359 if (hca_attr->ct_offload && priv->mtr_color_reg == REG_C_3) { 1360 err = mlx5_flow_aso_ct_mng_init(sh); 1361 if (err) { 1362 err = -err; 1363 goto error; 1364 } 1365 DRV_LOG(DEBUG, "CT ASO is supported."); 1366 sh->ct_aso_en = 1; 1367 } 1368 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1369 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1370 if (hca_attr->log_max_ft_sampler_num > 0 && 1371 config->dv_flow_en) { 1372 priv->sampler_en = 1; 1373 DRV_LOG(DEBUG, "Sampler enabled!"); 1374 } else { 1375 priv->sampler_en = 0; 1376 if (!hca_attr->log_max_ft_sampler_num) 1377 DRV_LOG(WARNING, 1378 "No available register for sampler."); 1379 else 1380 DRV_LOG(DEBUG, "DV flow is not supported!"); 1381 } 1382 #endif 1383 } 1384 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1385 !(sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1386 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1387 config->cqe_comp = 0; 1388 } 1389 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1390 (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_flow_tag)) { 1391 DRV_LOG(WARNING, "Flow Tag CQE compression" 1392 " format isn't supported."); 1393 config->cqe_comp = 0; 1394 } 1395 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1396 (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { 1397 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1398 " format isn't supported."); 1399 config->cqe_comp = 0; 1400 } 1401 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1402 config->cqe_comp ? "" : "not "); 1403 if (config->tx_pp) { 1404 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1405 hca_attr->dev_freq_khz); 1406 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1407 hca_attr->qos.packet_pacing ? "" : "not "); 1408 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1409 hca_attr->cross_channel ? "" : "not "); 1410 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1411 hca_attr->wqe_index_ignore ? "" : "not "); 1412 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1413 hca_attr->non_wire_sq ? "" : "not "); 1414 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1415 hca_attr->log_max_static_sq_wq ? "" : "not ", 1416 hca_attr->log_max_static_sq_wq); 1417 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1418 hca_attr->qos.wqe_rate_pp ? "" : "not "); 1419 if (!sh->cdev->config.devx) { 1420 DRV_LOG(ERR, "DevX is required for packet pacing"); 1421 err = ENODEV; 1422 goto error; 1423 } 1424 if (!hca_attr->qos.packet_pacing) { 1425 DRV_LOG(ERR, "Packet pacing is not supported"); 1426 err = ENODEV; 1427 goto error; 1428 } 1429 if (!hca_attr->cross_channel) { 1430 DRV_LOG(ERR, "Cross channel operations are" 1431 " required for packet pacing"); 1432 err = ENODEV; 1433 goto error; 1434 } 1435 if (!hca_attr->wqe_index_ignore) { 1436 DRV_LOG(ERR, "WQE index ignore feature is" 1437 " required for packet pacing"); 1438 err = ENODEV; 1439 goto error; 1440 } 1441 if (!hca_attr->non_wire_sq) { 1442 DRV_LOG(ERR, "Non-wire SQ feature is" 1443 " required for packet pacing"); 1444 err = ENODEV; 1445 goto error; 1446 } 1447 if (!hca_attr->log_max_static_sq_wq) { 1448 DRV_LOG(ERR, "Static WQE SQ feature is" 1449 " required for packet pacing"); 1450 err = ENODEV; 1451 goto error; 1452 } 1453 if (!hca_attr->qos.wqe_rate_pp) { 1454 DRV_LOG(ERR, "WQE rate mode is required" 1455 " for packet pacing"); 1456 err = ENODEV; 1457 goto error; 1458 } 1459 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1460 DRV_LOG(ERR, "DevX does not provide UAR offset," 1461 " can't create queues for packet pacing"); 1462 err = ENODEV; 1463 goto error; 1464 #endif 1465 } 1466 if (config->std_delay_drop || config->hp_delay_drop) { 1467 if (!hca_attr->rq_delay_drop) { 1468 config->std_delay_drop = 0; 1469 config->hp_delay_drop = 0; 1470 DRV_LOG(WARNING, 1471 "dev_port-%u: Rxq delay drop is not supported", 1472 priv->dev_port); 1473 } 1474 } 1475 if (sh->cdev->config.devx) 1476 mlx5_rt_timestamp_config(sh, config, hca_attr); 1477 /* 1478 * If HW has bug working with tunnel packet decapsulation and 1479 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1480 * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1481 */ 1482 if (hca_attr->scatter_fcs_w_decap_disable && config->decap_en) 1483 config->hw_fcs_strip = 0; 1484 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1485 (config->hw_fcs_strip ? "" : "not ")); 1486 if (config->mprq.enabled && !mprq) { 1487 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1488 config->mprq.enabled = 0; 1489 } 1490 if (config->max_dump_files_num == 0) 1491 config->max_dump_files_num = 128; 1492 eth_dev = rte_eth_dev_allocate(name); 1493 if (eth_dev == NULL) { 1494 DRV_LOG(ERR, "can not allocate rte ethdev"); 1495 err = ENOMEM; 1496 goto error; 1497 } 1498 if (priv->representor) { 1499 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1500 eth_dev->data->representor_id = priv->representor_id; 1501 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1502 struct mlx5_priv *opriv = 1503 rte_eth_devices[port_id].data->dev_private; 1504 if (opriv && 1505 opriv->master && 1506 opriv->domain_id == priv->domain_id && 1507 opriv->sh == priv->sh) { 1508 eth_dev->data->backer_port_id = port_id; 1509 break; 1510 } 1511 } 1512 if (port_id >= RTE_MAX_ETHPORTS) 1513 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1514 } 1515 priv->mp_id.port_id = eth_dev->data->port_id; 1516 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1517 /* 1518 * Store associated network device interface index. This index 1519 * is permanent throughout the lifetime of device. So, we may store 1520 * the ifindex here and use the cached value further. 1521 */ 1522 MLX5_ASSERT(spawn->ifindex); 1523 priv->if_index = spawn->ifindex; 1524 priv->lag_affinity_idx = sh->refcnt - 1; 1525 eth_dev->data->dev_private = priv; 1526 priv->dev_data = eth_dev->data; 1527 eth_dev->data->mac_addrs = priv->mac; 1528 eth_dev->device = dpdk_dev; 1529 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1530 /* Configure the first MAC address by default. */ 1531 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1532 DRV_LOG(ERR, 1533 "port %u cannot get MAC address, is mlx5_en" 1534 " loaded? (errno: %s)", 1535 eth_dev->data->port_id, strerror(rte_errno)); 1536 err = ENODEV; 1537 goto error; 1538 } 1539 DRV_LOG(INFO, 1540 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1541 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1542 #ifdef RTE_LIBRTE_MLX5_DEBUG 1543 { 1544 char ifname[MLX5_NAMESIZE]; 1545 1546 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1547 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1548 eth_dev->data->port_id, ifname); 1549 else 1550 DRV_LOG(DEBUG, "port %u ifname is unknown", 1551 eth_dev->data->port_id); 1552 } 1553 #endif 1554 /* Get actual MTU if possible. */ 1555 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1556 if (err) { 1557 err = rte_errno; 1558 goto error; 1559 } 1560 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1561 priv->mtu); 1562 /* Initialize burst functions to prevent crashes before link-up. */ 1563 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 1564 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 1565 eth_dev->dev_ops = &mlx5_dev_ops; 1566 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1567 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1568 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1569 /* Register MAC address. */ 1570 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1571 if (config->vf && config->vf_nl_en) 1572 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1573 mlx5_ifindex(eth_dev), 1574 eth_dev->data->mac_addrs, 1575 MLX5_MAX_MAC_ADDRESSES); 1576 priv->ctrl_flows = 0; 1577 rte_spinlock_init(&priv->flow_list_lock); 1578 TAILQ_INIT(&priv->flow_meters); 1579 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1580 if (!priv->mtr_profile_tbl) 1581 goto error; 1582 /* Bring Ethernet device up. */ 1583 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1584 eth_dev->data->port_id); 1585 mlx5_set_link_up(eth_dev); 1586 /* 1587 * Even though the interrupt handler is not installed yet, 1588 * interrupts will still trigger on the async_fd from 1589 * Verbs context returned by ibv_open_device(). 1590 */ 1591 mlx5_link_update(eth_dev, 0); 1592 /* Detect minimal data bytes to inline. */ 1593 mlx5_set_min_inline(spawn, config); 1594 /* Store device configuration on private structure. */ 1595 priv->config = *config; 1596 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1597 icfg[i].release_mem_en = !!config->reclaim_mode; 1598 if (config->reclaim_mode) 1599 icfg[i].per_core_cache = 0; 1600 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1601 if (!priv->flows[i]) 1602 goto error; 1603 } 1604 /* Create context for virtual machine VLAN workaround. */ 1605 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1606 if (config->dv_flow_en) { 1607 err = mlx5_alloc_shared_dr(priv); 1608 if (err) 1609 goto error; 1610 if (mlx5_flex_item_port_init(eth_dev) < 0) 1611 goto error; 1612 } 1613 if (sh->cdev->config.devx && config->dv_flow_en && config->dest_tir) { 1614 priv->obj_ops = devx_obj_ops; 1615 mlx5_queue_counter_id_prepare(eth_dev); 1616 priv->obj_ops.lb_dummy_queue_create = 1617 mlx5_rxq_ibv_obj_dummy_lb_create; 1618 priv->obj_ops.lb_dummy_queue_release = 1619 mlx5_rxq_ibv_obj_dummy_lb_release; 1620 } else if (spawn->max_port > UINT8_MAX) { 1621 /* Verbs can't support ports larger than 255 by design. */ 1622 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); 1623 err = ENOTSUP; 1624 goto error; 1625 } else { 1626 priv->obj_ops = ibv_obj_ops; 1627 } 1628 if (config->tx_pp && 1629 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new) { 1630 /* 1631 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1632 * packet pacing and already checked above. 1633 * Hence, we should only make sure the SQs will be created 1634 * with DevX, not with Verbs. 1635 * Verbs allocates the SQ UAR on its own and it can't be shared 1636 * with Clock Queue UAR as required for Tx scheduling. 1637 */ 1638 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1639 err = ENODEV; 1640 goto error; 1641 } 1642 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1643 if (!priv->drop_queue.hrxq) 1644 goto error; 1645 /* Port representor shares the same max priority with pf port. */ 1646 if (!priv->sh->flow_priority_check_flag) { 1647 /* Supported Verbs flow priority number detection. */ 1648 err = mlx5_flow_discover_priorities(eth_dev); 1649 priv->sh->flow_max_priority = err; 1650 priv->sh->flow_priority_check_flag = 1; 1651 } else { 1652 err = priv->sh->flow_max_priority; 1653 } 1654 if (err < 0) { 1655 err = -err; 1656 goto error; 1657 } 1658 mlx5_set_metadata_mask(eth_dev); 1659 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1660 !priv->sh->dv_regc0_mask) { 1661 DRV_LOG(ERR, "metadata mode %u is not supported " 1662 "(no metadata reg_c[0] is available)", 1663 priv->config.dv_xmeta_en); 1664 err = ENOTSUP; 1665 goto error; 1666 } 1667 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1668 mlx5_hrxq_create_cb, 1669 mlx5_hrxq_match_cb, 1670 mlx5_hrxq_remove_cb, 1671 mlx5_hrxq_clone_cb, 1672 mlx5_hrxq_clone_free_cb); 1673 if (!priv->hrxqs) 1674 goto error; 1675 rte_rwlock_init(&priv->ind_tbls_lock); 1676 /* Query availability of metadata reg_c's. */ 1677 if (!priv->sh->metadata_regc_check_flag) { 1678 err = mlx5_flow_discover_mreg_c(eth_dev); 1679 if (err < 0) { 1680 err = -err; 1681 goto error; 1682 } 1683 } 1684 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1685 DRV_LOG(DEBUG, 1686 "port %u extensive metadata register is not supported", 1687 eth_dev->data->port_id); 1688 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1689 DRV_LOG(ERR, "metadata mode %u is not supported " 1690 "(no metadata registers available)", 1691 priv->config.dv_xmeta_en); 1692 err = ENOTSUP; 1693 goto error; 1694 } 1695 } 1696 if (priv->config.dv_flow_en && 1697 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1698 mlx5_flow_ext_mreg_supported(eth_dev) && 1699 priv->sh->dv_regc0_mask) { 1700 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1701 MLX5_FLOW_MREG_HTABLE_SZ, 1702 false, true, eth_dev, 1703 flow_dv_mreg_create_cb, 1704 flow_dv_mreg_match_cb, 1705 flow_dv_mreg_remove_cb, 1706 flow_dv_mreg_clone_cb, 1707 flow_dv_mreg_clone_free_cb); 1708 if (!priv->mreg_cp_tbl) { 1709 err = ENOMEM; 1710 goto error; 1711 } 1712 } 1713 rte_spinlock_init(&priv->shared_act_sl); 1714 mlx5_flow_counter_mode_config(eth_dev); 1715 mlx5_flow_drop_action_config(eth_dev); 1716 if (priv->config.dv_flow_en) 1717 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1718 return eth_dev; 1719 error: 1720 if (priv) { 1721 if (priv->mreg_cp_tbl) 1722 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1723 if (priv->sh) 1724 mlx5_os_free_shared_dr(priv); 1725 if (priv->nl_socket_route >= 0) 1726 close(priv->nl_socket_route); 1727 if (priv->vmwa_context) 1728 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1729 if (eth_dev && priv->drop_queue.hrxq) 1730 mlx5_drop_action_destroy(eth_dev); 1731 if (priv->mtr_profile_tbl) 1732 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1733 if (own_domain_id) 1734 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1735 if (priv->hrxqs) 1736 mlx5_list_destroy(priv->hrxqs); 1737 if (eth_dev && priv->flex_item_map) 1738 mlx5_flex_item_port_cleanup(eth_dev); 1739 mlx5_free(priv); 1740 if (eth_dev != NULL) 1741 eth_dev->data->dev_private = NULL; 1742 } 1743 if (eth_dev != NULL) { 1744 /* mac_addrs must not be freed alone because part of 1745 * dev_private 1746 **/ 1747 eth_dev->data->mac_addrs = NULL; 1748 rte_eth_dev_release_port(eth_dev); 1749 } 1750 if (sh) 1751 mlx5_free_shared_dev_ctx(sh); 1752 if (nl_rdma >= 0) 1753 close(nl_rdma); 1754 MLX5_ASSERT(err > 0); 1755 rte_errno = err; 1756 return NULL; 1757 } 1758 1759 /** 1760 * Comparison callback to sort device data. 1761 * 1762 * This is meant to be used with qsort(). 1763 * 1764 * @param a[in] 1765 * Pointer to pointer to first data object. 1766 * @param b[in] 1767 * Pointer to pointer to second data object. 1768 * 1769 * @return 1770 * 0 if both objects are equal, less than 0 if the first argument is less 1771 * than the second, greater than 0 otherwise. 1772 */ 1773 static int 1774 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1775 { 1776 const struct mlx5_switch_info *si_a = 1777 &((const struct mlx5_dev_spawn_data *)a)->info; 1778 const struct mlx5_switch_info *si_b = 1779 &((const struct mlx5_dev_spawn_data *)b)->info; 1780 int ret; 1781 1782 /* Master device first. */ 1783 ret = si_b->master - si_a->master; 1784 if (ret) 1785 return ret; 1786 /* Then representor devices. */ 1787 ret = si_b->representor - si_a->representor; 1788 if (ret) 1789 return ret; 1790 /* Unidentified devices come last in no specific order. */ 1791 if (!si_a->representor) 1792 return 0; 1793 /* Order representors by name. */ 1794 return si_a->port_name - si_b->port_name; 1795 } 1796 1797 /** 1798 * Match PCI information for possible slaves of bonding device. 1799 * 1800 * @param[in] ibdev_name 1801 * Name of Infiniband device. 1802 * @param[in] pci_dev 1803 * Pointer to primary PCI address structure to match. 1804 * @param[in] nl_rdma 1805 * Netlink RDMA group socket handle. 1806 * @param[in] owner 1807 * Representor owner PF index. 1808 * @param[out] bond_info 1809 * Pointer to bonding information. 1810 * 1811 * @return 1812 * negative value if no bonding device found, otherwise 1813 * positive index of slave PF in bonding. 1814 */ 1815 static int 1816 mlx5_device_bond_pci_match(const char *ibdev_name, 1817 const struct rte_pci_addr *pci_dev, 1818 int nl_rdma, uint16_t owner, 1819 struct mlx5_bond_info *bond_info) 1820 { 1821 char ifname[IF_NAMESIZE + 1]; 1822 unsigned int ifindex; 1823 unsigned int np, i; 1824 FILE *bond_file = NULL, *file; 1825 int pf = -1; 1826 int ret; 1827 uint8_t cur_guid[32] = {0}; 1828 uint8_t guid[32] = {0}; 1829 1830 /* 1831 * Try to get master device name. If something goes wrong suppose 1832 * the lack of kernel support and no bonding devices. 1833 */ 1834 memset(bond_info, 0, sizeof(*bond_info)); 1835 if (nl_rdma < 0) 1836 return -1; 1837 if (!strstr(ibdev_name, "bond")) 1838 return -1; 1839 np = mlx5_nl_portnum(nl_rdma, ibdev_name); 1840 if (!np) 1841 return -1; 1842 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) 1843 return -1; 1844 /* 1845 * The master device might not be on the predefined port(not on port 1846 * index 1, it is not guaranteed), we have to scan all Infiniband 1847 * device ports and find master. 1848 */ 1849 for (i = 1; i <= np; ++i) { 1850 /* Check whether Infiniband port is populated. */ 1851 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); 1852 if (!ifindex) 1853 continue; 1854 if (!if_indextoname(ifindex, ifname)) 1855 continue; 1856 /* Try to read bonding slave names from sysfs. */ 1857 MKSTR(slaves, 1858 "/sys/class/net/%s/master/bonding/slaves", ifname); 1859 bond_file = fopen(slaves, "r"); 1860 if (bond_file) 1861 break; 1862 } 1863 if (!bond_file) 1864 return -1; 1865 /* Use safe format to check maximal buffer length. */ 1866 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1867 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1868 char tmp_str[IF_NAMESIZE + 32]; 1869 struct rte_pci_addr pci_addr; 1870 struct mlx5_switch_info info; 1871 int ret; 1872 1873 /* Process slave interface names in the loop. */ 1874 snprintf(tmp_str, sizeof(tmp_str), 1875 "/sys/class/net/%s", ifname); 1876 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 1877 DRV_LOG(WARNING, 1878 "Cannot get PCI address for netdev \"%s\".", 1879 ifname); 1880 continue; 1881 } 1882 /* Slave interface PCI address match found. */ 1883 snprintf(tmp_str, sizeof(tmp_str), 1884 "/sys/class/net/%s/phys_port_name", ifname); 1885 file = fopen(tmp_str, "rb"); 1886 if (!file) 1887 break; 1888 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1889 if (fscanf(file, "%32s", tmp_str) == 1) 1890 mlx5_translate_port_name(tmp_str, &info); 1891 fclose(file); 1892 /* Only process PF ports. */ 1893 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1894 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1895 continue; 1896 /* Check max bonding member. */ 1897 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1898 DRV_LOG(WARNING, "bonding index out of range, " 1899 "please increase MLX5_BOND_MAX_PORTS: %s", 1900 tmp_str); 1901 break; 1902 } 1903 /* Get ifindex. */ 1904 snprintf(tmp_str, sizeof(tmp_str), 1905 "/sys/class/net/%s/ifindex", ifname); 1906 file = fopen(tmp_str, "rb"); 1907 if (!file) 1908 break; 1909 ret = fscanf(file, "%u", &ifindex); 1910 fclose(file); 1911 if (ret != 1) 1912 break; 1913 /* Save bonding info. */ 1914 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1915 sizeof(bond_info->ports[0].ifname)); 1916 bond_info->ports[info.port_name].pci_addr = pci_addr; 1917 bond_info->ports[info.port_name].ifindex = ifindex; 1918 bond_info->n_port++; 1919 /* 1920 * Under socket direct mode, bonding will use 1921 * system_image_guid as identification. 1922 * After OFED 5.4, guid is readable (ret >= 0) under sysfs. 1923 * All bonding members should have the same guid even if driver 1924 * is using PCIe BDF. 1925 */ 1926 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid)); 1927 if (ret < 0) 1928 break; 1929 else if (ret > 0) { 1930 if (!memcmp(guid, cur_guid, sizeof(guid)) && 1931 owner == info.port_name && 1932 (owner != 0 || (owner == 0 && 1933 !rte_pci_addr_cmp(pci_dev, &pci_addr)))) 1934 pf = info.port_name; 1935 } else if (pci_dev->domain == pci_addr.domain && 1936 pci_dev->bus == pci_addr.bus && 1937 pci_dev->devid == pci_addr.devid && 1938 ((pci_dev->function == 0 && 1939 pci_dev->function + owner == pci_addr.function) || 1940 (pci_dev->function == owner && 1941 pci_addr.function == owner))) 1942 pf = info.port_name; 1943 } 1944 if (pf >= 0) { 1945 /* Get bond interface info */ 1946 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 1947 bond_info->ifname); 1948 if (ret) 1949 DRV_LOG(ERR, "unable to get bond info: %s", 1950 strerror(rte_errno)); 1951 else 1952 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1953 ifindex, bond_info->ifindex, bond_info->ifname); 1954 } 1955 if (owner == 0 && pf != 0) { 1956 DRV_LOG(INFO, "PCIe instance %04x:%02x:%02x.%x isn't bonding owner", 1957 pci_dev->domain, pci_dev->bus, pci_dev->devid, 1958 pci_dev->function); 1959 } 1960 return pf; 1961 } 1962 1963 static void 1964 mlx5_os_config_default(struct mlx5_dev_config *config, 1965 struct mlx5_common_dev_config *cconf) 1966 { 1967 memset(config, 0, sizeof(*config)); 1968 config->mps = MLX5_ARG_UNSET; 1969 config->cqe_comp = 1; 1970 config->rx_vec_en = 1; 1971 config->txq_inline_max = MLX5_ARG_UNSET; 1972 config->txq_inline_min = MLX5_ARG_UNSET; 1973 config->txq_inline_mpw = MLX5_ARG_UNSET; 1974 config->txqs_inline = MLX5_ARG_UNSET; 1975 config->vf_nl_en = 1; 1976 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 1977 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 1978 config->mprq.log_min_stride_wqe_size = cconf->devx ? 1979 cconf->hca_attr.log_min_stride_wqe_sz : 1980 MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1981 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; 1982 config->dv_esw_en = 1; 1983 config->dv_flow_en = 1; 1984 config->decap_en = 1; 1985 config->log_hp_size = MLX5_ARG_UNSET; 1986 config->allow_duplicate_pattern = 1; 1987 config->std_delay_drop = 0; 1988 config->hp_delay_drop = 0; 1989 } 1990 1991 /** 1992 * Register a PCI device within bonding. 1993 * 1994 * This function spawns Ethernet devices out of a given PCI device and 1995 * bonding owner PF index. 1996 * 1997 * @param[in] cdev 1998 * Pointer to common mlx5 device structure. 1999 * @param[in] req_eth_da 2000 * Requested ethdev device argument. 2001 * @param[in] owner_id 2002 * Requested owner PF port ID within bonding device, default to 0. 2003 * 2004 * @return 2005 * 0 on success, a negative errno value otherwise and rte_errno is set. 2006 */ 2007 static int 2008 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, 2009 struct rte_eth_devargs *req_eth_da, 2010 uint16_t owner_id) 2011 { 2012 struct ibv_device **ibv_list; 2013 /* 2014 * Number of found IB Devices matching with requested PCI BDF. 2015 * nd != 1 means there are multiple IB devices over the same 2016 * PCI device and we have representors and master. 2017 */ 2018 unsigned int nd = 0; 2019 /* 2020 * Number of found IB device Ports. nd = 1 and np = 1..n means 2021 * we have the single multiport IB device, and there may be 2022 * representors attached to some of found ports. 2023 */ 2024 unsigned int np = 0; 2025 /* 2026 * Number of DPDK ethernet devices to Spawn - either over 2027 * multiple IB devices or multiple ports of single IB device. 2028 * Actually this is the number of iterations to spawn. 2029 */ 2030 unsigned int ns = 0; 2031 /* 2032 * Bonding device 2033 * < 0 - no bonding device (single one) 2034 * >= 0 - bonding device (value is slave PF index) 2035 */ 2036 int bd = -1; 2037 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2038 struct mlx5_dev_spawn_data *list = NULL; 2039 struct mlx5_dev_config dev_config; 2040 struct rte_eth_devargs eth_da = *req_eth_da; 2041 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2042 struct mlx5_bond_info bond_info; 2043 int ret = -1; 2044 2045 errno = 0; 2046 ibv_list = mlx5_glue->get_device_list(&ret); 2047 if (!ibv_list) { 2048 rte_errno = errno ? errno : ENOSYS; 2049 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?"); 2050 return -rte_errno; 2051 } 2052 /* 2053 * First scan the list of all Infiniband devices to find 2054 * matching ones, gathering into the list. 2055 */ 2056 struct ibv_device *ibv_match[ret + 1]; 2057 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2058 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2059 unsigned int i; 2060 2061 while (ret-- > 0) { 2062 struct rte_pci_addr pci_addr; 2063 2064 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); 2065 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, 2066 nl_rdma, owner_id, &bond_info); 2067 if (bd >= 0) { 2068 /* 2069 * Bonding device detected. Only one match is allowed, 2070 * the bonding is supported over multi-port IB device, 2071 * there should be no matches on representor PCI 2072 * functions or non VF LAG bonding devices with 2073 * specified address. 2074 */ 2075 if (nd) { 2076 DRV_LOG(ERR, 2077 "multiple PCI match on bonding device" 2078 "\"%s\" found", ibv_list[ret]->name); 2079 rte_errno = ENOENT; 2080 ret = -rte_errno; 2081 goto exit; 2082 } 2083 /* Amend owner pci address if owner PF ID specified. */ 2084 if (eth_da.nb_representor_ports) 2085 owner_pci.function += owner_id; 2086 DRV_LOG(INFO, 2087 "PCI information matches for slave %d bonding device \"%s\"", 2088 bd, ibv_list[ret]->name); 2089 ibv_match[nd++] = ibv_list[ret]; 2090 break; 2091 } else { 2092 /* Bonding device not found. */ 2093 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2094 &pci_addr)) 2095 continue; 2096 if (owner_pci.domain != pci_addr.domain || 2097 owner_pci.bus != pci_addr.bus || 2098 owner_pci.devid != pci_addr.devid || 2099 owner_pci.function != pci_addr.function) 2100 continue; 2101 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2102 ibv_list[ret]->name); 2103 ibv_match[nd++] = ibv_list[ret]; 2104 } 2105 } 2106 ibv_match[nd] = NULL; 2107 if (!nd) { 2108 /* No device matches, just complain and bail out. */ 2109 DRV_LOG(WARNING, 2110 "No Verbs device matches PCI device " PCI_PRI_FMT "," 2111 " are kernel drivers loaded?", 2112 owner_pci.domain, owner_pci.bus, 2113 owner_pci.devid, owner_pci.function); 2114 rte_errno = ENOENT; 2115 ret = -rte_errno; 2116 goto exit; 2117 } 2118 if (nd == 1) { 2119 /* 2120 * Found single matching device may have multiple ports. 2121 * Each port may be representor, we have to check the port 2122 * number and check the representors existence. 2123 */ 2124 if (nl_rdma >= 0) 2125 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2126 if (!np) 2127 DRV_LOG(WARNING, 2128 "Cannot get IB device \"%s\" ports number.", 2129 ibv_match[0]->name); 2130 if (bd >= 0 && !np) { 2131 DRV_LOG(ERR, "Cannot get ports for bonding device."); 2132 rte_errno = ENOENT; 2133 ret = -rte_errno; 2134 goto exit; 2135 } 2136 } 2137 /* Now we can determine the maximal amount of devices to be spawned. */ 2138 list = mlx5_malloc(MLX5_MEM_ZERO, 2139 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd), 2140 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2141 if (!list) { 2142 DRV_LOG(ERR, "Spawn data array allocation failure."); 2143 rte_errno = ENOMEM; 2144 ret = -rte_errno; 2145 goto exit; 2146 } 2147 if (bd >= 0 || np > 1) { 2148 /* 2149 * Single IB device with multiple ports found, 2150 * it may be E-Switch master device and representors. 2151 * We have to perform identification through the ports. 2152 */ 2153 MLX5_ASSERT(nl_rdma >= 0); 2154 MLX5_ASSERT(ns == 0); 2155 MLX5_ASSERT(nd == 1); 2156 MLX5_ASSERT(np); 2157 for (i = 1; i <= np; ++i) { 2158 list[ns].bond_info = &bond_info; 2159 list[ns].max_port = np; 2160 list[ns].phys_port = i; 2161 list[ns].phys_dev_name = ibv_match[0]->name; 2162 list[ns].eth_dev = NULL; 2163 list[ns].pci_dev = pci_dev; 2164 list[ns].cdev = cdev; 2165 list[ns].pf_bond = bd; 2166 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, 2167 ibv_match[0]->name, 2168 i); 2169 if (!list[ns].ifindex) { 2170 /* 2171 * No network interface index found for the 2172 * specified port, it means there is no 2173 * representor on this port. It's OK, 2174 * there can be disabled ports, for example 2175 * if sriov_numvfs < sriov_totalvfs. 2176 */ 2177 continue; 2178 } 2179 ret = -1; 2180 if (nl_route >= 0) 2181 ret = mlx5_nl_switch_info(nl_route, 2182 list[ns].ifindex, 2183 &list[ns].info); 2184 if (ret || (!list[ns].info.representor && 2185 !list[ns].info.master)) { 2186 /* 2187 * We failed to recognize representors with 2188 * Netlink, let's try to perform the task 2189 * with sysfs. 2190 */ 2191 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2192 &list[ns].info); 2193 } 2194 if (!ret && bd >= 0) { 2195 switch (list[ns].info.name_type) { 2196 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2197 if (np == 1) { 2198 /* 2199 * Force standalone bonding 2200 * device for ROCE LAG 2201 * configurations. 2202 */ 2203 list[ns].info.master = 0; 2204 list[ns].info.representor = 0; 2205 } 2206 if (list[ns].info.port_name == bd) 2207 ns++; 2208 break; 2209 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2210 /* Fallthrough */ 2211 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2212 /* Fallthrough */ 2213 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2214 if (list[ns].info.pf_num == bd) 2215 ns++; 2216 break; 2217 default: 2218 break; 2219 } 2220 continue; 2221 } 2222 if (!ret && (list[ns].info.representor ^ 2223 list[ns].info.master)) 2224 ns++; 2225 } 2226 if (!ns) { 2227 DRV_LOG(ERR, 2228 "Unable to recognize master/representors on the IB device with multiple ports."); 2229 rte_errno = ENOENT; 2230 ret = -rte_errno; 2231 goto exit; 2232 } 2233 } else { 2234 /* 2235 * The existence of several matching entries (nd > 1) means 2236 * port representors have been instantiated. No existing Verbs 2237 * call nor sysfs entries can tell them apart, this can only 2238 * be done through Netlink calls assuming kernel drivers are 2239 * recent enough to support them. 2240 * 2241 * In the event of identification failure through Netlink, 2242 * try again through sysfs, then: 2243 * 2244 * 1. A single IB device matches (nd == 1) with single 2245 * port (np=0/1) and is not a representor, assume 2246 * no switch support. 2247 * 2248 * 2. Otherwise no safe assumptions can be made; 2249 * complain louder and bail out. 2250 */ 2251 for (i = 0; i != nd; ++i) { 2252 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2253 list[ns].bond_info = NULL; 2254 list[ns].max_port = 1; 2255 list[ns].phys_port = 1; 2256 list[ns].phys_dev_name = ibv_match[i]->name; 2257 list[ns].eth_dev = NULL; 2258 list[ns].pci_dev = pci_dev; 2259 list[ns].cdev = cdev; 2260 list[ns].pf_bond = -1; 2261 list[ns].ifindex = 0; 2262 if (nl_rdma >= 0) 2263 list[ns].ifindex = mlx5_nl_ifindex 2264 (nl_rdma, 2265 ibv_match[i]->name, 2266 1); 2267 if (!list[ns].ifindex) { 2268 char ifname[IF_NAMESIZE]; 2269 2270 /* 2271 * Netlink failed, it may happen with old 2272 * ib_core kernel driver (before 4.16). 2273 * We can assume there is old driver because 2274 * here we are processing single ports IB 2275 * devices. Let's try sysfs to retrieve 2276 * the ifindex. The method works for 2277 * master device only. 2278 */ 2279 if (nd > 1) { 2280 /* 2281 * Multiple devices found, assume 2282 * representors, can not distinguish 2283 * master/representor and retrieve 2284 * ifindex via sysfs. 2285 */ 2286 continue; 2287 } 2288 ret = mlx5_get_ifname_sysfs 2289 (ibv_match[i]->ibdev_path, ifname); 2290 if (!ret) 2291 list[ns].ifindex = 2292 if_nametoindex(ifname); 2293 if (!list[ns].ifindex) { 2294 /* 2295 * No network interface index found 2296 * for the specified device, it means 2297 * there it is neither representor 2298 * nor master. 2299 */ 2300 continue; 2301 } 2302 } 2303 ret = -1; 2304 if (nl_route >= 0) 2305 ret = mlx5_nl_switch_info(nl_route, 2306 list[ns].ifindex, 2307 &list[ns].info); 2308 if (ret || (!list[ns].info.representor && 2309 !list[ns].info.master)) { 2310 /* 2311 * We failed to recognize representors with 2312 * Netlink, let's try to perform the task 2313 * with sysfs. 2314 */ 2315 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2316 &list[ns].info); 2317 } 2318 if (!ret && (list[ns].info.representor ^ 2319 list[ns].info.master)) { 2320 ns++; 2321 } else if ((nd == 1) && 2322 !list[ns].info.representor && 2323 !list[ns].info.master) { 2324 /* 2325 * Single IB device with one physical port and 2326 * attached network device. 2327 * May be SRIOV is not enabled or there is no 2328 * representors. 2329 */ 2330 DRV_LOG(INFO, "No E-Switch support detected."); 2331 ns++; 2332 break; 2333 } 2334 } 2335 if (!ns) { 2336 DRV_LOG(ERR, 2337 "Unable to recognize master/representors on the multiple IB devices."); 2338 rte_errno = ENOENT; 2339 ret = -rte_errno; 2340 goto exit; 2341 } 2342 /* 2343 * New kernels may add the switch_id attribute for the case 2344 * there is no E-Switch and we wrongly recognized the only 2345 * device as master. Override this if there is the single 2346 * device with single port and new device name format present. 2347 */ 2348 if (nd == 1 && 2349 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2350 list[0].info.master = 0; 2351 list[0].info.representor = 0; 2352 } 2353 } 2354 MLX5_ASSERT(ns); 2355 /* 2356 * Sort list to probe devices in natural order for users convenience 2357 * (i.e. master first, then representors from lowest to highest ID). 2358 */ 2359 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2360 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2361 /* Set devargs default values. */ 2362 if (eth_da.nb_mh_controllers == 0) { 2363 eth_da.nb_mh_controllers = 1; 2364 eth_da.mh_controllers[0] = 0; 2365 } 2366 if (eth_da.nb_ports == 0 && ns > 0) { 2367 if (list[0].pf_bond >= 0 && list[0].info.representor) 2368 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2369 pci_dev->device.devargs->args); 2370 eth_da.nb_ports = 1; 2371 eth_da.ports[0] = list[0].info.pf_num; 2372 } 2373 if (eth_da.nb_representor_ports == 0) { 2374 eth_da.nb_representor_ports = 1; 2375 eth_da.representor_ports[0] = 0; 2376 } 2377 } 2378 for (i = 0; i != ns; ++i) { 2379 uint32_t restore; 2380 2381 /* Default configuration. */ 2382 mlx5_os_config_default(&dev_config, &cdev->config); 2383 dev_config.vf = mlx5_dev_is_vf_pci(pci_dev); 2384 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], 2385 &dev_config, ð_da); 2386 if (!list[i].eth_dev) { 2387 if (rte_errno != EBUSY && rte_errno != EEXIST) 2388 break; 2389 /* Device is disabled or already spawned. Ignore it. */ 2390 continue; 2391 } 2392 restore = list[i].eth_dev->data->dev_flags; 2393 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2394 /** 2395 * Each representor has a dedicated interrupts vector. 2396 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2397 * representor eth_dev object because representor and PF 2398 * share the same PCI address. 2399 * Override representor device with a dedicated 2400 * interrupts handle here. 2401 * Representor interrupts handle is released in mlx5_dev_stop(). 2402 */ 2403 if (list[i].info.representor) { 2404 struct rte_intr_handle *intr_handle = 2405 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2406 if (intr_handle == NULL) { 2407 DRV_LOG(ERR, 2408 "port %u failed to allocate memory for interrupt handler " 2409 "Rx interrupts will not be supported", 2410 i); 2411 rte_errno = ENOMEM; 2412 ret = -rte_errno; 2413 goto exit; 2414 } 2415 list[i].eth_dev->intr_handle = intr_handle; 2416 } 2417 /* Restore non-PCI flags cleared by the above call. */ 2418 list[i].eth_dev->data->dev_flags |= restore; 2419 rte_eth_dev_probing_finish(list[i].eth_dev); 2420 } 2421 if (i != ns) { 2422 DRV_LOG(ERR, 2423 "probe of PCI device " PCI_PRI_FMT " aborted after" 2424 " encountering an error: %s", 2425 owner_pci.domain, owner_pci.bus, 2426 owner_pci.devid, owner_pci.function, 2427 strerror(rte_errno)); 2428 ret = -rte_errno; 2429 /* Roll back. */ 2430 while (i--) { 2431 if (!list[i].eth_dev) 2432 continue; 2433 mlx5_dev_close(list[i].eth_dev); 2434 /* mac_addrs must not be freed because in dev_private */ 2435 list[i].eth_dev->data->mac_addrs = NULL; 2436 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2437 } 2438 /* Restore original error. */ 2439 rte_errno = -ret; 2440 } else { 2441 ret = 0; 2442 } 2443 exit: 2444 /* 2445 * Do the routine cleanup: 2446 * - close opened Netlink sockets 2447 * - free allocated spawn data array 2448 * - free the Infiniband device list 2449 */ 2450 if (nl_rdma >= 0) 2451 close(nl_rdma); 2452 if (nl_route >= 0) 2453 close(nl_route); 2454 if (list) 2455 mlx5_free(list); 2456 MLX5_ASSERT(ibv_list); 2457 mlx5_glue->free_device_list(ibv_list); 2458 return ret; 2459 } 2460 2461 static int 2462 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2463 struct rte_eth_devargs *eth_da) 2464 { 2465 int ret = 0; 2466 2467 if (dev->devargs == NULL) 2468 return 0; 2469 memset(eth_da, 0, sizeof(*eth_da)); 2470 /* Parse representor information first from class argument. */ 2471 if (dev->devargs->cls_str) 2472 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2473 if (ret != 0) { 2474 DRV_LOG(ERR, "failed to parse device arguments: %s", 2475 dev->devargs->cls_str); 2476 return -rte_errno; 2477 } 2478 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2479 /* Parse legacy device argument */ 2480 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2481 if (ret) { 2482 DRV_LOG(ERR, "failed to parse device arguments: %s", 2483 dev->devargs->args); 2484 return -rte_errno; 2485 } 2486 } 2487 return 0; 2488 } 2489 2490 /** 2491 * Callback to register a PCI device. 2492 * 2493 * This function spawns Ethernet devices out of a given PCI device. 2494 * 2495 * @param[in] cdev 2496 * Pointer to common mlx5 device structure. 2497 * 2498 * @return 2499 * 0 on success, a negative errno value otherwise and rte_errno is set. 2500 */ 2501 static int 2502 mlx5_os_pci_probe(struct mlx5_common_device *cdev) 2503 { 2504 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2505 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2506 int ret = 0; 2507 uint16_t p; 2508 2509 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da); 2510 if (ret != 0) 2511 return ret; 2512 2513 if (eth_da.nb_ports > 0) { 2514 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2515 for (p = 0; p < eth_da.nb_ports; p++) { 2516 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 2517 eth_da.ports[p]); 2518 if (ret) 2519 break; 2520 } 2521 if (ret) { 2522 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2523 "aborted due to prodding failure of PF %u", 2524 pci_dev->addr.domain, pci_dev->addr.bus, 2525 pci_dev->addr.devid, pci_dev->addr.function, 2526 eth_da.ports[p]); 2527 mlx5_net_remove(cdev); 2528 } 2529 } else { 2530 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0); 2531 } 2532 return ret; 2533 } 2534 2535 /* Probe a single SF device on auxiliary bus, no representor support. */ 2536 static int 2537 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev) 2538 { 2539 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2540 struct mlx5_dev_config config; 2541 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2542 struct rte_device *dev = cdev->dev; 2543 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2544 struct rte_eth_dev *eth_dev; 2545 int ret = 0; 2546 2547 /* Parse ethdev devargs. */ 2548 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2549 if (ret != 0) 2550 return ret; 2551 /* Set default config data. */ 2552 mlx5_os_config_default(&config, &cdev->config); 2553 config.sf = 1; 2554 /* Init spawn data. */ 2555 spawn.max_port = 1; 2556 spawn.phys_port = 1; 2557 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 2558 ret = mlx5_auxiliary_get_ifindex(dev->name); 2559 if (ret < 0) { 2560 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2561 return ret; 2562 } 2563 spawn.ifindex = ret; 2564 spawn.cdev = cdev; 2565 /* Spawn device. */ 2566 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2567 if (eth_dev == NULL) 2568 return -rte_errno; 2569 /* Post create. */ 2570 eth_dev->intr_handle = adev->intr_handle; 2571 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2572 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2573 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2574 eth_dev->data->numa_node = dev->numa_node; 2575 } 2576 rte_eth_dev_probing_finish(eth_dev); 2577 return 0; 2578 } 2579 2580 /** 2581 * Net class driver callback to probe a device. 2582 * 2583 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2584 * 2585 * @param[in] cdev 2586 * Pointer to the common mlx5 device. 2587 * 2588 * @return 2589 * 0 on success, a negative errno value otherwise and rte_errno is set. 2590 */ 2591 int 2592 mlx5_os_net_probe(struct mlx5_common_device *cdev) 2593 { 2594 int ret; 2595 2596 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2597 mlx5_pmd_socket_init(); 2598 ret = mlx5_init_once(); 2599 if (ret) { 2600 DRV_LOG(ERR, "Unable to init PMD global data: %s", 2601 strerror(rte_errno)); 2602 return -rte_errno; 2603 } 2604 if (mlx5_dev_is_pci(cdev->dev)) 2605 return mlx5_os_pci_probe(cdev); 2606 else 2607 return mlx5_os_auxiliary_probe(cdev); 2608 } 2609 2610 /** 2611 * Cleanup resources when the last device is closed. 2612 */ 2613 void 2614 mlx5_os_net_cleanup(void) 2615 { 2616 mlx5_pmd_socket_uninit(); 2617 } 2618 2619 /** 2620 * Install shared asynchronous device events handler. 2621 * This function is implemented to support event sharing 2622 * between multiple ports of single IB device. 2623 * 2624 * @param sh 2625 * Pointer to mlx5_dev_ctx_shared object. 2626 */ 2627 void 2628 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2629 { 2630 int ret; 2631 int flags; 2632 struct ibv_context *ctx = sh->cdev->ctx; 2633 2634 sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2635 if (sh->intr_handle == NULL) { 2636 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2637 rte_errno = ENOMEM; 2638 return; 2639 } 2640 rte_intr_fd_set(sh->intr_handle, -1); 2641 2642 flags = fcntl(ctx->async_fd, F_GETFL); 2643 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); 2644 if (ret) { 2645 DRV_LOG(INFO, "failed to change file descriptor async event" 2646 " queue"); 2647 } else { 2648 rte_intr_fd_set(sh->intr_handle, ctx->async_fd); 2649 rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); 2650 if (rte_intr_callback_register(sh->intr_handle, 2651 mlx5_dev_interrupt_handler, sh)) { 2652 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2653 rte_intr_fd_set(sh->intr_handle, -1); 2654 } 2655 } 2656 if (sh->cdev->config.devx) { 2657 #ifdef HAVE_IBV_DEVX_ASYNC 2658 sh->intr_handle_devx = 2659 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2660 if (!sh->intr_handle_devx) { 2661 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2662 rte_errno = ENOMEM; 2663 return; 2664 } 2665 rte_intr_fd_set(sh->intr_handle_devx, -1); 2666 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); 2667 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2668 if (!devx_comp) { 2669 DRV_LOG(INFO, "failed to allocate devx_comp."); 2670 return; 2671 } 2672 flags = fcntl(devx_comp->fd, F_GETFL); 2673 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2674 if (ret) { 2675 DRV_LOG(INFO, "failed to change file descriptor" 2676 " devx comp"); 2677 return; 2678 } 2679 rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); 2680 rte_intr_type_set(sh->intr_handle_devx, 2681 RTE_INTR_HANDLE_EXT); 2682 if (rte_intr_callback_register(sh->intr_handle_devx, 2683 mlx5_dev_interrupt_handler_devx, sh)) { 2684 DRV_LOG(INFO, "Fail to install the devx shared" 2685 " interrupt."); 2686 rte_intr_fd_set(sh->intr_handle_devx, -1); 2687 } 2688 #endif /* HAVE_IBV_DEVX_ASYNC */ 2689 } 2690 } 2691 2692 /** 2693 * Uninstall shared asynchronous device events handler. 2694 * This function is implemented to support event sharing 2695 * between multiple ports of single IB device. 2696 * 2697 * @param dev 2698 * Pointer to mlx5_dev_ctx_shared object. 2699 */ 2700 void 2701 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2702 { 2703 if (rte_intr_fd_get(sh->intr_handle) >= 0) 2704 mlx5_intr_callback_unregister(sh->intr_handle, 2705 mlx5_dev_interrupt_handler, sh); 2706 rte_intr_instance_free(sh->intr_handle); 2707 #ifdef HAVE_IBV_DEVX_ASYNC 2708 if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) 2709 rte_intr_callback_unregister(sh->intr_handle_devx, 2710 mlx5_dev_interrupt_handler_devx, sh); 2711 rte_intr_instance_free(sh->intr_handle_devx); 2712 if (sh->devx_comp) 2713 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2714 #endif 2715 } 2716 2717 /** 2718 * Read statistics by a named counter. 2719 * 2720 * @param[in] priv 2721 * Pointer to the private device data structure. 2722 * @param[in] ctr_name 2723 * Pointer to the name of the statistic counter to read 2724 * @param[out] stat 2725 * Pointer to read statistic value. 2726 * @return 2727 * 0 on success and stat is valud, 1 if failed to read the value 2728 * rte_errno is set. 2729 * 2730 */ 2731 int 2732 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2733 uint64_t *stat) 2734 { 2735 int fd; 2736 2737 if (priv->sh) { 2738 if (priv->q_counters != NULL && 2739 strcmp(ctr_name, "out_of_buffer") == 0) 2740 return mlx5_devx_cmd_queue_counter_query 2741 (priv->q_counters, 0, (uint32_t *)stat); 2742 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2743 priv->sh->ibdev_path, 2744 priv->dev_port, 2745 ctr_name); 2746 fd = open(path, O_RDONLY); 2747 /* 2748 * in switchdev the file location is not per port 2749 * but rather in <ibdev_path>/hw_counters/<file_name>. 2750 */ 2751 if (fd == -1) { 2752 MKSTR(path1, "%s/hw_counters/%s", 2753 priv->sh->ibdev_path, 2754 ctr_name); 2755 fd = open(path1, O_RDONLY); 2756 } 2757 if (fd != -1) { 2758 char buf[21] = {'\0'}; 2759 ssize_t n = read(fd, buf, sizeof(buf)); 2760 2761 close(fd); 2762 if (n != -1) { 2763 *stat = strtoull(buf, NULL, 10); 2764 return 0; 2765 } 2766 } 2767 } 2768 *stat = 0; 2769 return 1; 2770 } 2771 2772 /** 2773 * Remove a MAC address from device 2774 * 2775 * @param dev 2776 * Pointer to Ethernet device structure. 2777 * @param index 2778 * MAC address index. 2779 */ 2780 void 2781 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2782 { 2783 struct mlx5_priv *priv = dev->data->dev_private; 2784 const int vf = priv->config.vf; 2785 2786 if (vf) 2787 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2788 mlx5_ifindex(dev), priv->mac_own, 2789 &dev->data->mac_addrs[index], index); 2790 } 2791 2792 /** 2793 * Adds a MAC address to the device 2794 * 2795 * @param dev 2796 * Pointer to Ethernet device structure. 2797 * @param mac_addr 2798 * MAC address to register. 2799 * @param index 2800 * MAC address index. 2801 * 2802 * @return 2803 * 0 on success, a negative errno value otherwise 2804 */ 2805 int 2806 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2807 uint32_t index) 2808 { 2809 struct mlx5_priv *priv = dev->data->dev_private; 2810 const int vf = priv->config.vf; 2811 int ret = 0; 2812 2813 if (vf) 2814 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2815 mlx5_ifindex(dev), priv->mac_own, 2816 mac, index); 2817 return ret; 2818 } 2819 2820 /** 2821 * Modify a VF MAC address 2822 * 2823 * @param priv 2824 * Pointer to device private data. 2825 * @param mac_addr 2826 * MAC address to modify into. 2827 * @param iface_idx 2828 * Net device interface index 2829 * @param vf_index 2830 * VF index 2831 * 2832 * @return 2833 * 0 on success, a negative errno value otherwise 2834 */ 2835 int 2836 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2837 unsigned int iface_idx, 2838 struct rte_ether_addr *mac_addr, 2839 int vf_index) 2840 { 2841 return mlx5_nl_vf_mac_addr_modify 2842 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2843 } 2844 2845 /** 2846 * Set device promiscuous mode 2847 * 2848 * @param dev 2849 * Pointer to Ethernet device structure. 2850 * @param enable 2851 * 0 - promiscuous is disabled, otherwise - enabled 2852 * 2853 * @return 2854 * 0 on success, a negative error value otherwise 2855 */ 2856 int 2857 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2858 { 2859 struct mlx5_priv *priv = dev->data->dev_private; 2860 2861 return mlx5_nl_promisc(priv->nl_socket_route, 2862 mlx5_ifindex(dev), !!enable); 2863 } 2864 2865 /** 2866 * Set device promiscuous mode 2867 * 2868 * @param dev 2869 * Pointer to Ethernet device structure. 2870 * @param enable 2871 * 0 - all multicase is disabled, otherwise - enabled 2872 * 2873 * @return 2874 * 0 on success, a negative error value otherwise 2875 */ 2876 int 2877 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2878 { 2879 struct mlx5_priv *priv = dev->data->dev_private; 2880 2881 return mlx5_nl_allmulti(priv->nl_socket_route, 2882 mlx5_ifindex(dev), !!enable); 2883 } 2884 2885 /** 2886 * Flush device MAC addresses 2887 * 2888 * @param dev 2889 * Pointer to Ethernet device structure. 2890 * 2891 */ 2892 void 2893 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2894 { 2895 struct mlx5_priv *priv = dev->data->dev_private; 2896 2897 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2898 dev->data->mac_addrs, 2899 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2900 } 2901