1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /* rte flow indexed pool configuration. */ 71 static struct mlx5_indexed_pool_config icfg[] = { 72 { 73 .size = sizeof(struct rte_flow), 74 .trunk_size = 64, 75 .need_lock = 1, 76 .release_mem_en = 0, 77 .malloc = mlx5_malloc, 78 .free = mlx5_free, 79 .per_core_cache = 0, 80 .type = "ctl_flow_ipool", 81 }, 82 { 83 .size = sizeof(struct rte_flow), 84 .trunk_size = 64, 85 .grow_trunk = 3, 86 .grow_shift = 2, 87 .need_lock = 1, 88 .release_mem_en = 0, 89 .malloc = mlx5_malloc, 90 .free = mlx5_free, 91 .per_core_cache = 1 << 14, 92 .type = "rte_flow_ipool", 93 }, 94 { 95 .size = sizeof(struct rte_flow), 96 .trunk_size = 64, 97 .grow_trunk = 3, 98 .grow_shift = 2, 99 .need_lock = 1, 100 .release_mem_en = 0, 101 .malloc = mlx5_malloc, 102 .free = mlx5_free, 103 .per_core_cache = 0, 104 .type = "mcp_flow_ipool", 105 }, 106 }; 107 108 /** 109 * Set the completion channel file descriptor interrupt as non-blocking. 110 * 111 * @param[in] rxq_obj 112 * Pointer to RQ channel object, which includes the channel fd 113 * 114 * @param[out] fd 115 * The file descriptor (representing the intetrrupt) used in this channel. 116 * 117 * @return 118 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 119 */ 120 int 121 mlx5_os_set_nonblock_channel_fd(int fd) 122 { 123 int flags; 124 125 flags = fcntl(fd, F_GETFL); 126 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 127 } 128 129 /** 130 * Get mlx5 device attributes. The glue function query_device_ex() is called 131 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 132 * device attributes from the glue out parameter. 133 * 134 * @param cdev 135 * Pointer to mlx5 device. 136 * 137 * @param device_attr 138 * Pointer to mlx5 device attributes. 139 * 140 * @return 141 * 0 on success, non zero error number otherwise 142 */ 143 int 144 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, 145 struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_context *ctx = cdev->ctx; 149 struct ibv_device_attr_ex attr_ex; 150 151 memset(device_attr, 0, sizeof(*device_attr)); 152 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 153 if (err) 154 return err; 155 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 156 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 157 device_attr->max_sge = attr_ex.orig_attr.max_sge; 158 device_attr->max_cq = attr_ex.orig_attr.max_cq; 159 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 160 device_attr->max_mr = attr_ex.orig_attr.max_mr; 161 device_attr->max_pd = attr_ex.orig_attr.max_pd; 162 device_attr->max_qp = attr_ex.orig_attr.max_qp; 163 device_attr->max_srq = attr_ex.orig_attr.max_srq; 164 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 165 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 166 device_attr->max_rwq_indirection_table_size = 167 attr_ex.rss_caps.max_rwq_indirection_table_size; 168 device_attr->max_tso = attr_ex.tso_caps.max_tso; 169 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 170 171 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 172 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 173 if (err) 174 return err; 175 176 device_attr->flags = dv_attr.flags; 177 device_attr->comp_mask = dv_attr.comp_mask; 178 #ifdef HAVE_IBV_MLX5_MOD_SWP 179 device_attr->sw_parsing_offloads = 180 dv_attr.sw_parsing_caps.sw_parsing_offloads; 181 #endif 182 device_attr->min_single_stride_log_num_of_bytes = 183 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 184 device_attr->max_single_stride_log_num_of_bytes = 185 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 186 device_attr->min_single_wqe_log_num_of_strides = 187 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 188 device_attr->max_single_wqe_log_num_of_strides = 189 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 190 device_attr->stride_supported_qpts = 191 dv_attr.striding_rq_caps.supported_qpts; 192 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 193 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 194 #endif 195 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 196 sizeof(device_attr->fw_ver)); 197 198 return err; 199 } 200 201 /** 202 * Detect misc5 support or not 203 * 204 * @param[in] priv 205 * Device private data pointer 206 */ 207 #ifdef HAVE_MLX5DV_DR 208 static void 209 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 210 { 211 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 212 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 213 * Case: IPv4--->UDP--->VxLAN--->vni 214 */ 215 void *tbl; 216 struct mlx5_flow_dv_match_params matcher_mask; 217 void *match_m; 218 void *matcher; 219 void *headers_m; 220 void *misc5_m; 221 uint32_t *tunnel_header_m; 222 struct mlx5dv_flow_matcher_attr dv_attr; 223 224 memset(&matcher_mask, 0, sizeof(matcher_mask)); 225 matcher_mask.size = sizeof(matcher_mask.buf); 226 match_m = matcher_mask.buf; 227 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 228 misc5_m = MLX5_ADDR_OF(fte_match_param, 229 match_m, misc_parameters_5); 230 tunnel_header_m = (uint32_t *) 231 MLX5_ADDR_OF(fte_match_set_misc5, 232 misc5_m, tunnel_header_1); 233 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 234 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 235 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 236 *tunnel_header_m = 0xffffff; 237 238 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 239 if (!tbl) { 240 DRV_LOG(INFO, "No SW steering support"); 241 return; 242 } 243 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 244 dv_attr.match_mask = (void *)&matcher_mask, 245 dv_attr.match_criteria_enable = 246 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 247 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 248 dv_attr.priority = 3; 249 #ifdef HAVE_MLX5DV_DR_ESWITCH 250 void *misc2_m; 251 if (priv->config.dv_esw_en) { 252 /* FDB enabled reg_c_0 */ 253 dv_attr.match_criteria_enable |= 254 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 255 misc2_m = MLX5_ADDR_OF(fte_match_param, 256 match_m, misc_parameters_2); 257 MLX5_SET(fte_match_set_misc2, misc2_m, 258 metadata_reg_c_0, 0xffff); 259 } 260 #endif 261 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx, 262 &dv_attr, tbl); 263 if (matcher) { 264 priv->sh->misc5_cap = 1; 265 mlx5_glue->dv_destroy_flow_matcher(matcher); 266 } 267 mlx5_glue->dr_destroy_flow_tbl(tbl); 268 #else 269 RTE_SET_USED(priv); 270 #endif 271 } 272 #endif 273 274 /** 275 * Initialize DR related data within private structure. 276 * Routine checks the reference counter and does actual 277 * resources creation/initialization only if counter is zero. 278 * 279 * @param[in] priv 280 * Pointer to the private device data structure. 281 * 282 * @return 283 * Zero on success, positive error code otherwise. 284 */ 285 static int 286 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 287 { 288 struct mlx5_dev_ctx_shared *sh = priv->sh; 289 char s[MLX5_NAME_SIZE] __rte_unused; 290 int err; 291 292 MLX5_ASSERT(sh && sh->refcnt); 293 if (sh->refcnt > 1) 294 return 0; 295 err = mlx5_alloc_table_hash_list(priv); 296 if (err) 297 goto error; 298 /* The resources below are only valid with DV support. */ 299 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 300 /* Init port id action list. */ 301 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 302 sh->port_id_action_list = mlx5_list_create(s, sh, true, 303 flow_dv_port_id_create_cb, 304 flow_dv_port_id_match_cb, 305 flow_dv_port_id_remove_cb, 306 flow_dv_port_id_clone_cb, 307 flow_dv_port_id_clone_free_cb); 308 if (!sh->port_id_action_list) 309 goto error; 310 /* Init push vlan action list. */ 311 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 312 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 313 flow_dv_push_vlan_create_cb, 314 flow_dv_push_vlan_match_cb, 315 flow_dv_push_vlan_remove_cb, 316 flow_dv_push_vlan_clone_cb, 317 flow_dv_push_vlan_clone_free_cb); 318 if (!sh->push_vlan_action_list) 319 goto error; 320 /* Init sample action list. */ 321 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 322 sh->sample_action_list = mlx5_list_create(s, sh, true, 323 flow_dv_sample_create_cb, 324 flow_dv_sample_match_cb, 325 flow_dv_sample_remove_cb, 326 flow_dv_sample_clone_cb, 327 flow_dv_sample_clone_free_cb); 328 if (!sh->sample_action_list) 329 goto error; 330 /* Init dest array action list. */ 331 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 332 sh->dest_array_list = mlx5_list_create(s, sh, true, 333 flow_dv_dest_array_create_cb, 334 flow_dv_dest_array_match_cb, 335 flow_dv_dest_array_remove_cb, 336 flow_dv_dest_array_clone_cb, 337 flow_dv_dest_array_clone_free_cb); 338 if (!sh->dest_array_list) 339 goto error; 340 #endif 341 #ifdef HAVE_MLX5DV_DR 342 void *domain; 343 344 /* Reference counter is zero, we should initialize structures. */ 345 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 346 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 347 if (!domain) { 348 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 349 err = errno; 350 goto error; 351 } 352 sh->rx_domain = domain; 353 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 354 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 355 if (!domain) { 356 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 357 err = errno; 358 goto error; 359 } 360 sh->tx_domain = domain; 361 #ifdef HAVE_MLX5DV_DR_ESWITCH 362 if (priv->config.dv_esw_en) { 363 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 364 MLX5DV_DR_DOMAIN_TYPE_FDB); 365 if (!domain) { 366 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 367 err = errno; 368 goto error; 369 } 370 sh->fdb_domain = domain; 371 } 372 /* 373 * The drop action is just some dummy placeholder in rdma-core. It 374 * does not belong to domains and has no any attributes, and, can be 375 * shared by the entire device. 376 */ 377 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 378 if (!sh->dr_drop_action) { 379 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 380 err = errno; 381 goto error; 382 } 383 #endif 384 if (!sh->tunnel_hub && priv->config.dv_miss_info) 385 err = mlx5_alloc_tunnel_hub(sh); 386 if (err) { 387 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 388 goto error; 389 } 390 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 391 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 392 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 393 if (sh->fdb_domain) 394 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 395 } 396 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 397 if (!priv->config.allow_duplicate_pattern) { 398 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 399 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 400 #endif 401 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 402 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 403 if (sh->fdb_domain) 404 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 405 } 406 407 __mlx5_discovery_misc5_cap(priv); 408 #endif /* HAVE_MLX5DV_DR */ 409 sh->default_miss_action = 410 mlx5_glue->dr_create_flow_action_default_miss(); 411 if (!sh->default_miss_action) 412 DRV_LOG(WARNING, "Default miss action is not supported."); 413 return 0; 414 error: 415 /* Rollback the created objects. */ 416 if (sh->rx_domain) { 417 mlx5_glue->dr_destroy_domain(sh->rx_domain); 418 sh->rx_domain = NULL; 419 } 420 if (sh->tx_domain) { 421 mlx5_glue->dr_destroy_domain(sh->tx_domain); 422 sh->tx_domain = NULL; 423 } 424 if (sh->fdb_domain) { 425 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 426 sh->fdb_domain = NULL; 427 } 428 if (sh->dr_drop_action) { 429 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 430 sh->dr_drop_action = NULL; 431 } 432 if (sh->pop_vlan_action) { 433 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 434 sh->pop_vlan_action = NULL; 435 } 436 if (sh->encaps_decaps) { 437 mlx5_hlist_destroy(sh->encaps_decaps); 438 sh->encaps_decaps = NULL; 439 } 440 if (sh->modify_cmds) { 441 mlx5_hlist_destroy(sh->modify_cmds); 442 sh->modify_cmds = NULL; 443 } 444 if (sh->tag_table) { 445 /* tags should be destroyed with flow before. */ 446 mlx5_hlist_destroy(sh->tag_table); 447 sh->tag_table = NULL; 448 } 449 if (sh->tunnel_hub) { 450 mlx5_release_tunnel_hub(sh, priv->dev_port); 451 sh->tunnel_hub = NULL; 452 } 453 mlx5_free_table_hash_list(priv); 454 if (sh->port_id_action_list) { 455 mlx5_list_destroy(sh->port_id_action_list); 456 sh->port_id_action_list = NULL; 457 } 458 if (sh->push_vlan_action_list) { 459 mlx5_list_destroy(sh->push_vlan_action_list); 460 sh->push_vlan_action_list = NULL; 461 } 462 if (sh->sample_action_list) { 463 mlx5_list_destroy(sh->sample_action_list); 464 sh->sample_action_list = NULL; 465 } 466 if (sh->dest_array_list) { 467 mlx5_list_destroy(sh->dest_array_list); 468 sh->dest_array_list = NULL; 469 } 470 return err; 471 } 472 473 /** 474 * Destroy DR related data within private structure. 475 * 476 * @param[in] priv 477 * Pointer to the private device data structure. 478 */ 479 void 480 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 481 { 482 struct mlx5_dev_ctx_shared *sh = priv->sh; 483 484 MLX5_ASSERT(sh && sh->refcnt); 485 if (sh->refcnt > 1) 486 return; 487 #ifdef HAVE_MLX5DV_DR 488 if (sh->rx_domain) { 489 mlx5_glue->dr_destroy_domain(sh->rx_domain); 490 sh->rx_domain = NULL; 491 } 492 if (sh->tx_domain) { 493 mlx5_glue->dr_destroy_domain(sh->tx_domain); 494 sh->tx_domain = NULL; 495 } 496 #ifdef HAVE_MLX5DV_DR_ESWITCH 497 if (sh->fdb_domain) { 498 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 499 sh->fdb_domain = NULL; 500 } 501 if (sh->dr_drop_action) { 502 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 503 sh->dr_drop_action = NULL; 504 } 505 #endif 506 if (sh->pop_vlan_action) { 507 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 508 sh->pop_vlan_action = NULL; 509 } 510 #endif /* HAVE_MLX5DV_DR */ 511 if (sh->default_miss_action) 512 mlx5_glue->destroy_flow_action 513 (sh->default_miss_action); 514 if (sh->encaps_decaps) { 515 mlx5_hlist_destroy(sh->encaps_decaps); 516 sh->encaps_decaps = NULL; 517 } 518 if (sh->modify_cmds) { 519 mlx5_hlist_destroy(sh->modify_cmds); 520 sh->modify_cmds = NULL; 521 } 522 if (sh->tag_table) { 523 /* tags should be destroyed with flow before. */ 524 mlx5_hlist_destroy(sh->tag_table); 525 sh->tag_table = NULL; 526 } 527 if (sh->tunnel_hub) { 528 mlx5_release_tunnel_hub(sh, priv->dev_port); 529 sh->tunnel_hub = NULL; 530 } 531 mlx5_free_table_hash_list(priv); 532 if (sh->port_id_action_list) { 533 mlx5_list_destroy(sh->port_id_action_list); 534 sh->port_id_action_list = NULL; 535 } 536 if (sh->push_vlan_action_list) { 537 mlx5_list_destroy(sh->push_vlan_action_list); 538 sh->push_vlan_action_list = NULL; 539 } 540 if (sh->sample_action_list) { 541 mlx5_list_destroy(sh->sample_action_list); 542 sh->sample_action_list = NULL; 543 } 544 if (sh->dest_array_list) { 545 mlx5_list_destroy(sh->dest_array_list); 546 sh->dest_array_list = NULL; 547 } 548 } 549 550 /** 551 * Initialize shared data between primary and secondary process. 552 * 553 * A memzone is reserved by primary process and secondary processes attach to 554 * the memzone. 555 * 556 * @return 557 * 0 on success, a negative errno value otherwise and rte_errno is set. 558 */ 559 static int 560 mlx5_init_shared_data(void) 561 { 562 const struct rte_memzone *mz; 563 int ret = 0; 564 565 rte_spinlock_lock(&mlx5_shared_data_lock); 566 if (mlx5_shared_data == NULL) { 567 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 568 /* Allocate shared memory. */ 569 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 570 sizeof(*mlx5_shared_data), 571 SOCKET_ID_ANY, 0); 572 if (mz == NULL) { 573 DRV_LOG(ERR, 574 "Cannot allocate mlx5 shared data"); 575 ret = -rte_errno; 576 goto error; 577 } 578 mlx5_shared_data = mz->addr; 579 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 580 rte_spinlock_init(&mlx5_shared_data->lock); 581 } else { 582 /* Lookup allocated shared memory. */ 583 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 584 if (mz == NULL) { 585 DRV_LOG(ERR, 586 "Cannot attach mlx5 shared data"); 587 ret = -rte_errno; 588 goto error; 589 } 590 mlx5_shared_data = mz->addr; 591 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 592 } 593 } 594 error: 595 rte_spinlock_unlock(&mlx5_shared_data_lock); 596 return ret; 597 } 598 599 /** 600 * PMD global initialization. 601 * 602 * Independent from individual device, this function initializes global 603 * per-PMD data structures distinguishing primary and secondary processes. 604 * Hence, each initialization is called once per a process. 605 * 606 * @return 607 * 0 on success, a negative errno value otherwise and rte_errno is set. 608 */ 609 static int 610 mlx5_init_once(void) 611 { 612 struct mlx5_shared_data *sd; 613 struct mlx5_local_data *ld = &mlx5_local_data; 614 int ret = 0; 615 616 if (mlx5_init_shared_data()) 617 return -rte_errno; 618 sd = mlx5_shared_data; 619 MLX5_ASSERT(sd); 620 rte_spinlock_lock(&sd->lock); 621 switch (rte_eal_process_type()) { 622 case RTE_PROC_PRIMARY: 623 if (sd->init_done) 624 break; 625 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 626 mlx5_mp_os_primary_handle); 627 if (ret) 628 goto out; 629 sd->init_done = true; 630 break; 631 case RTE_PROC_SECONDARY: 632 if (ld->init_done) 633 break; 634 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 635 mlx5_mp_os_secondary_handle); 636 if (ret) 637 goto out; 638 ++sd->secondary_cnt; 639 ld->init_done = true; 640 break; 641 default: 642 break; 643 } 644 out: 645 rte_spinlock_unlock(&sd->lock); 646 return ret; 647 } 648 649 /** 650 * DV flow counter mode detect and config. 651 * 652 * @param dev 653 * Pointer to rte_eth_dev structure. 654 * 655 */ 656 static void 657 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 658 { 659 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 660 struct mlx5_priv *priv = dev->data->dev_private; 661 struct mlx5_dev_ctx_shared *sh = priv->sh; 662 bool fallback; 663 664 #ifndef HAVE_IBV_DEVX_ASYNC 665 fallback = true; 666 #else 667 fallback = false; 668 if (!sh->devx || !priv->config.dv_flow_en || 669 !priv->config.hca_attr.flow_counters_dump || 670 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 671 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 672 fallback = true; 673 #endif 674 if (fallback) 675 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 676 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 677 priv->config.hca_attr.flow_counters_dump, 678 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 679 /* Initialize fallback mode only on the port initializes sh. */ 680 if (sh->refcnt == 1) 681 sh->cmng.counter_fallback = fallback; 682 else if (fallback != sh->cmng.counter_fallback) 683 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 684 "with others:%d.", PORT_ID(priv), fallback); 685 #endif 686 } 687 688 /** 689 * DR flow drop action support detect. 690 * 691 * @param dev 692 * Pointer to rte_eth_dev structure. 693 * 694 */ 695 static void 696 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 697 { 698 #ifdef HAVE_MLX5DV_DR 699 struct mlx5_priv *priv = dev->data->dev_private; 700 701 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action) 702 return; 703 /** 704 * DR supports drop action placeholder when it is supported; 705 * otherwise, use the queue drop action. 706 */ 707 if (!priv->sh->drop_action_check_flag) { 708 if (!mlx5_flow_discover_dr_action_support(dev)) 709 priv->sh->dr_drop_action_en = 1; 710 priv->sh->drop_action_check_flag = 1; 711 } 712 if (priv->sh->dr_drop_action_en) 713 priv->root_drop_action = priv->sh->dr_drop_action; 714 else 715 priv->root_drop_action = priv->drop_queue.hrxq->action; 716 #endif 717 } 718 719 static void 720 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 721 { 722 struct mlx5_priv *priv = dev->data->dev_private; 723 void *ctx = priv->sh->cdev->ctx; 724 725 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 726 if (!priv->q_counters) { 727 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 728 struct ibv_wq *wq; 729 730 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 731 "by DevX - fall-back to use the kernel driver global " 732 "queue counter.", dev->data->port_id); 733 /* Create WQ by kernel and query its queue counter ID. */ 734 if (cq) { 735 wq = mlx5_glue->create_wq(ctx, 736 &(struct ibv_wq_init_attr){ 737 .wq_type = IBV_WQT_RQ, 738 .max_wr = 1, 739 .max_sge = 1, 740 .pd = priv->sh->cdev->pd, 741 .cq = cq, 742 }); 743 if (wq) { 744 /* Counter is assigned only on RDY state. */ 745 int ret = mlx5_glue->modify_wq(wq, 746 &(struct ibv_wq_attr){ 747 .attr_mask = IBV_WQ_ATTR_STATE, 748 .wq_state = IBV_WQS_RDY, 749 }); 750 751 if (ret == 0) 752 mlx5_devx_cmd_wq_query(wq, 753 &priv->counter_set_id); 754 claim_zero(mlx5_glue->destroy_wq(wq)); 755 } 756 claim_zero(mlx5_glue->destroy_cq(cq)); 757 } 758 } else { 759 priv->counter_set_id = priv->q_counters->id; 760 } 761 if (priv->counter_set_id == 0) 762 DRV_LOG(INFO, "Part of the port %d statistics will not be " 763 "available.", dev->data->port_id); 764 } 765 766 /** 767 * Check if representor spawn info match devargs. 768 * 769 * @param spawn 770 * Verbs device parameters (name, port, switch_info) to spawn. 771 * @param eth_da 772 * Device devargs to probe. 773 * 774 * @return 775 * Match result. 776 */ 777 static bool 778 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 779 struct rte_eth_devargs *eth_da) 780 { 781 struct mlx5_switch_info *switch_info = &spawn->info; 782 unsigned int p, f; 783 uint16_t id; 784 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 785 eth_da->type); 786 787 switch (eth_da->type) { 788 case RTE_ETH_REPRESENTOR_SF: 789 if (!(spawn->info.port_name == -1 && 790 switch_info->name_type == 791 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 792 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 793 rte_errno = EBUSY; 794 return false; 795 } 796 break; 797 case RTE_ETH_REPRESENTOR_VF: 798 /* Allows HPF representor index -1 as exception. */ 799 if (!(spawn->info.port_name == -1 && 800 switch_info->name_type == 801 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 802 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 803 rte_errno = EBUSY; 804 return false; 805 } 806 break; 807 case RTE_ETH_REPRESENTOR_NONE: 808 rte_errno = EBUSY; 809 return false; 810 default: 811 rte_errno = ENOTSUP; 812 DRV_LOG(ERR, "unsupported representor type"); 813 return false; 814 } 815 /* Check representor ID: */ 816 for (p = 0; p < eth_da->nb_ports; ++p) { 817 if (spawn->pf_bond < 0) { 818 /* For non-LAG mode, allow and ignore pf. */ 819 switch_info->pf_num = eth_da->ports[p]; 820 repr_id = mlx5_representor_id_encode(switch_info, 821 eth_da->type); 822 } 823 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 824 id = MLX5_REPRESENTOR_ID 825 (eth_da->ports[p], eth_da->type, 826 eth_da->representor_ports[f]); 827 if (repr_id == id) 828 return true; 829 } 830 } 831 rte_errno = EBUSY; 832 return false; 833 } 834 835 /** 836 * Spawn an Ethernet device from Verbs information. 837 * 838 * @param dpdk_dev 839 * Backing DPDK device. 840 * @param spawn 841 * Verbs device parameters (name, port, switch_info) to spawn. 842 * @param config 843 * Device configuration parameters. 844 * @param eth_da 845 * Device arguments. 846 * 847 * @return 848 * A valid Ethernet device object on success, NULL otherwise and rte_errno 849 * is set. The following errors are defined: 850 * 851 * EBUSY: device is not supposed to be spawned. 852 * EEXIST: device is already spawned 853 */ 854 static struct rte_eth_dev * 855 mlx5_dev_spawn(struct rte_device *dpdk_dev, 856 struct mlx5_dev_spawn_data *spawn, 857 struct mlx5_dev_config *config, 858 struct rte_eth_devargs *eth_da) 859 { 860 const struct mlx5_switch_info *switch_info = &spawn->info; 861 struct mlx5_dev_ctx_shared *sh = NULL; 862 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; 863 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 864 struct rte_eth_dev *eth_dev = NULL; 865 struct mlx5_priv *priv = NULL; 866 int err = 0; 867 unsigned int hw_padding = 0; 868 unsigned int mps; 869 unsigned int mpls_en = 0; 870 unsigned int swp = 0; 871 unsigned int mprq = 0; 872 unsigned int mprq_min_stride_size_n = 0; 873 unsigned int mprq_max_stride_size_n = 0; 874 unsigned int mprq_min_stride_num_n = 0; 875 unsigned int mprq_max_stride_num_n = 0; 876 struct rte_ether_addr mac; 877 char name[RTE_ETH_NAME_MAX_LEN]; 878 int own_domain_id = 0; 879 uint16_t port_id; 880 struct mlx5_port_info vport_info = { .query_flags = 0 }; 881 int nl_rdma = -1; 882 int i; 883 884 /* Determine if this port representor is supposed to be spawned. */ 885 if (switch_info->representor && dpdk_dev->devargs && 886 !mlx5_representor_match(spawn, eth_da)) 887 return NULL; 888 /* Build device name. */ 889 if (spawn->pf_bond < 0) { 890 /* Single device. */ 891 if (!switch_info->representor) 892 strlcpy(name, dpdk_dev->name, sizeof(name)); 893 else 894 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 895 dpdk_dev->name, 896 switch_info->name_type == 897 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 898 switch_info->port_name); 899 } else { 900 /* Bonding device. */ 901 if (!switch_info->representor) { 902 err = snprintf(name, sizeof(name), "%s_%s", 903 dpdk_dev->name, spawn->phys_dev_name); 904 } else { 905 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 906 dpdk_dev->name, spawn->phys_dev_name, 907 switch_info->ctrl_num, 908 switch_info->pf_num, 909 switch_info->name_type == 910 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 911 switch_info->port_name); 912 } 913 } 914 if (err >= (int)sizeof(name)) 915 DRV_LOG(WARNING, "device name overflow %s", name); 916 /* check if the device is already spawned */ 917 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 918 rte_errno = EEXIST; 919 return NULL; 920 } 921 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 922 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 923 struct mlx5_mp_id mp_id; 924 925 eth_dev = rte_eth_dev_attach_secondary(name); 926 if (eth_dev == NULL) { 927 DRV_LOG(ERR, "can not attach rte ethdev"); 928 rte_errno = ENOMEM; 929 return NULL; 930 } 931 eth_dev->device = dpdk_dev; 932 eth_dev->dev_ops = &mlx5_dev_sec_ops; 933 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 934 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 935 err = mlx5_proc_priv_init(eth_dev); 936 if (err) 937 return NULL; 938 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 939 /* Receive command fd from primary process */ 940 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 941 if (err < 0) 942 goto err_secondary; 943 /* Remap UAR for Tx queues. */ 944 err = mlx5_tx_uar_init_secondary(eth_dev, err); 945 if (err) 946 goto err_secondary; 947 /* 948 * Ethdev pointer is still required as input since 949 * the primary device is not accessible from the 950 * secondary process. 951 */ 952 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 953 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 954 return eth_dev; 955 err_secondary: 956 mlx5_dev_close(eth_dev); 957 return NULL; 958 } 959 /* 960 * Some parameters ("tx_db_nc" in particularly) are needed in 961 * advance to create dv/verbs device context. We proceed the 962 * devargs here to get ones, and later proceed devargs again 963 * to override some hardware settings. 964 */ 965 err = mlx5_args(config, dpdk_dev->devargs); 966 if (err) { 967 err = rte_errno; 968 DRV_LOG(ERR, "failed to process device arguments: %s", 969 strerror(rte_errno)); 970 goto error; 971 } 972 if (config->dv_miss_info) { 973 if (switch_info->master || switch_info->representor) 974 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 975 } 976 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 977 if (!sh) 978 return NULL; 979 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 980 config->dest_tir = 1; 981 #endif 982 #ifdef HAVE_IBV_MLX5_MOD_SWP 983 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 984 #endif 985 /* 986 * Multi-packet send is supported by ConnectX-4 Lx PF as well 987 * as all ConnectX-5 devices. 988 */ 989 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 990 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 991 #endif 992 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 993 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 994 #endif 995 mlx5_glue->dv_query_device(sh->cdev->ctx, &dv_attr); 996 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 997 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 998 DRV_LOG(DEBUG, "enhanced MPW is supported"); 999 mps = MLX5_MPW_ENHANCED; 1000 } else { 1001 DRV_LOG(DEBUG, "MPW is supported"); 1002 mps = MLX5_MPW; 1003 } 1004 } else { 1005 DRV_LOG(DEBUG, "MPW isn't supported"); 1006 mps = MLX5_MPW_DISABLED; 1007 } 1008 #ifdef HAVE_IBV_MLX5_MOD_SWP 1009 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1010 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1011 DRV_LOG(DEBUG, "SWP support: %u", swp); 1012 #endif 1013 config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP | 1014 MLX5_SW_PARSING_TSO_CAP); 1015 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1016 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1017 struct mlx5dv_striding_rq_caps mprq_caps = 1018 dv_attr.striding_rq_caps; 1019 1020 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1021 mprq_caps.min_single_stride_log_num_of_bytes); 1022 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1023 mprq_caps.max_single_stride_log_num_of_bytes); 1024 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1025 mprq_caps.min_single_wqe_log_num_of_strides); 1026 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1027 mprq_caps.max_single_wqe_log_num_of_strides); 1028 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1029 mprq_caps.supported_qpts); 1030 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1031 mprq = 1; 1032 mprq_min_stride_size_n = 1033 mprq_caps.min_single_stride_log_num_of_bytes; 1034 mprq_max_stride_size_n = 1035 mprq_caps.max_single_stride_log_num_of_bytes; 1036 mprq_min_stride_num_n = 1037 mprq_caps.min_single_wqe_log_num_of_strides; 1038 mprq_max_stride_num_n = 1039 mprq_caps.max_single_wqe_log_num_of_strides; 1040 } 1041 #endif 1042 /* Rx CQE compression is enabled by default. */ 1043 config->cqe_comp = 1; 1044 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1045 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1046 config->tunnel_en = dv_attr.tunnel_offloads_caps & 1047 (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN | 1048 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE | 1049 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE); 1050 } 1051 if (config->tunnel_en) { 1052 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s", 1053 config->tunnel_en & 1054 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "", 1055 config->tunnel_en & 1056 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "", 1057 config->tunnel_en & 1058 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : "" 1059 ); 1060 } else { 1061 DRV_LOG(DEBUG, "tunnel offloading is not supported"); 1062 } 1063 #else 1064 DRV_LOG(WARNING, 1065 "tunnel offloading disabled due to old OFED/rdma-core version"); 1066 #endif 1067 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1068 mpls_en = ((dv_attr.tunnel_offloads_caps & 1069 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1070 (dv_attr.tunnel_offloads_caps & 1071 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1072 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1073 mpls_en ? "" : "not "); 1074 #else 1075 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1076 " old OFED/rdma-core version or firmware configuration"); 1077 #endif 1078 config->mpls_en = mpls_en; 1079 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1080 /* Check port status. */ 1081 if (spawn->phys_port <= UINT8_MAX) { 1082 /* Legacy Verbs api only support u8 port number. */ 1083 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port, 1084 &port_attr); 1085 if (err) { 1086 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1087 goto error; 1088 } 1089 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1090 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1091 err = EINVAL; 1092 goto error; 1093 } 1094 } else if (nl_rdma >= 0) { 1095 /* IB doesn't allow more than 255 ports, must be Ethernet. */ 1096 err = mlx5_nl_port_state(nl_rdma, 1097 spawn->phys_dev_name, 1098 spawn->phys_port); 1099 if (err < 0) { 1100 DRV_LOG(INFO, "Failed to get netlink port state: %s", 1101 strerror(rte_errno)); 1102 err = -rte_errno; 1103 goto error; 1104 } 1105 port_attr.state = (enum ibv_port_state)err; 1106 } 1107 if (port_attr.state != IBV_PORT_ACTIVE) 1108 DRV_LOG(INFO, "port is not active: \"%s\" (%d)", 1109 mlx5_glue->port_state_str(port_attr.state), 1110 port_attr.state); 1111 /* Allocate private eth device data. */ 1112 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1113 sizeof(*priv), 1114 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1115 if (priv == NULL) { 1116 DRV_LOG(ERR, "priv allocation failure"); 1117 err = ENOMEM; 1118 goto error; 1119 } 1120 priv->sh = sh; 1121 priv->dev_port = spawn->phys_port; 1122 priv->pci_dev = spawn->pci_dev; 1123 priv->mtu = RTE_ETHER_MTU; 1124 /* Some internal functions rely on Netlink sockets, open them now. */ 1125 priv->nl_socket_rdma = nl_rdma; 1126 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1127 priv->representor = !!switch_info->representor; 1128 priv->master = !!switch_info->master; 1129 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1130 priv->vport_meta_tag = 0; 1131 priv->vport_meta_mask = 0; 1132 priv->pf_bond = spawn->pf_bond; 1133 1134 DRV_LOG(DEBUG, 1135 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1136 priv->dev_port, dpdk_dev->bus->name, 1137 priv->pci_dev ? priv->pci_dev->name : "NONE", 1138 priv->master, priv->representor, priv->pf_bond); 1139 1140 /* 1141 * If we have E-Switch we should determine the vport attributes. 1142 * E-Switch may use either source vport field or reg_c[0] metadata 1143 * register to match on vport index. The engaged part of metadata 1144 * register is defined by mask. 1145 */ 1146 if (switch_info->representor || switch_info->master) { 1147 err = mlx5_glue->devx_port_query(sh->cdev->ctx, 1148 spawn->phys_port, 1149 &vport_info); 1150 if (err) { 1151 DRV_LOG(WARNING, 1152 "Cannot query devx port %d on device %s", 1153 spawn->phys_port, spawn->phys_dev_name); 1154 vport_info.query_flags = 0; 1155 } 1156 } 1157 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1158 priv->vport_meta_tag = vport_info.vport_meta_tag; 1159 priv->vport_meta_mask = vport_info.vport_meta_mask; 1160 if (!priv->vport_meta_mask) { 1161 DRV_LOG(ERR, 1162 "vport zero mask for port %d on bonding device %s", 1163 spawn->phys_port, spawn->phys_dev_name); 1164 err = ENOTSUP; 1165 goto error; 1166 } 1167 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1168 DRV_LOG(ERR, 1169 "Invalid vport tag for port %d on bonding device %s", 1170 spawn->phys_port, spawn->phys_dev_name); 1171 err = ENOTSUP; 1172 goto error; 1173 } 1174 } 1175 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1176 priv->vport_id = vport_info.vport_id; 1177 } else if (spawn->pf_bond >= 0 && 1178 (switch_info->representor || switch_info->master)) { 1179 DRV_LOG(ERR, 1180 "Cannot deduce vport index for port %d on bonding device %s", 1181 spawn->phys_port, spawn->phys_dev_name); 1182 err = ENOTSUP; 1183 goto error; 1184 } else { 1185 /* 1186 * Suppose vport index in compatible way. Kernel/rdma_core 1187 * support single E-Switch per PF configurations only and 1188 * vport_id field contains the vport index for associated VF, 1189 * which is deduced from representor port name. 1190 * For example, let's have the IB device port 10, it has 1191 * attached network device eth0, which has port name attribute 1192 * pf0vf2, we can deduce the VF number as 2, and set vport index 1193 * as 3 (2+1). This assigning schema should be changed if the 1194 * multiple E-Switch instances per PF configurations or/and PCI 1195 * subfunctions are added. 1196 */ 1197 priv->vport_id = switch_info->representor ? 1198 switch_info->port_name + 1 : -1; 1199 } 1200 priv->representor_id = mlx5_representor_id_encode(switch_info, 1201 eth_da->type); 1202 /* 1203 * Look for sibling devices in order to reuse their switch domain 1204 * if any, otherwise allocate one. 1205 */ 1206 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1207 const struct mlx5_priv *opriv = 1208 rte_eth_devices[port_id].data->dev_private; 1209 1210 if (!opriv || 1211 opriv->sh != priv->sh || 1212 opriv->domain_id == 1213 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1214 continue; 1215 priv->domain_id = opriv->domain_id; 1216 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1217 priv->dev_port, priv->domain_id); 1218 break; 1219 } 1220 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1221 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1222 if (err) { 1223 err = rte_errno; 1224 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1225 strerror(rte_errno)); 1226 goto error; 1227 } 1228 own_domain_id = 1; 1229 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1230 priv->dev_port, priv->domain_id); 1231 } 1232 /* Override some values set by hardware configuration. */ 1233 mlx5_args(config, dpdk_dev->devargs); 1234 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev); 1235 if (err) 1236 goto error; 1237 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1238 IBV_DEVICE_RAW_IP_CSUM); 1239 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1240 (config->hw_csum ? "" : "not ")); 1241 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1242 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1243 DRV_LOG(DEBUG, "counters are not supported"); 1244 #endif 1245 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1246 if (config->dv_flow_en) { 1247 DRV_LOG(WARNING, "DV flow is not supported"); 1248 config->dv_flow_en = 0; 1249 } 1250 #endif 1251 config->ind_table_max_size = 1252 sh->device_attr.max_rwq_indirection_table_size; 1253 /* 1254 * Remove this check once DPDK supports larger/variable 1255 * indirection tables. 1256 */ 1257 if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512) 1258 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512; 1259 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1260 config->ind_table_max_size); 1261 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1262 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1263 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1264 (config->hw_vlan_strip ? "" : "not ")); 1265 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1266 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1267 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1268 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1269 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1270 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1271 IBV_DEVICE_PCI_WRITE_END_PADDING); 1272 #endif 1273 if (config->hw_padding && !hw_padding) { 1274 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1275 config->hw_padding = 0; 1276 } else if (config->hw_padding) { 1277 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1278 } 1279 config->tso = (sh->device_attr.max_tso > 0 && 1280 (sh->device_attr.tso_supported_qpts & 1281 (1 << IBV_QPT_RAW_PACKET))); 1282 if (config->tso) 1283 config->tso_max_payload_sz = sh->device_attr.max_tso; 1284 /* 1285 * MPW is disabled by default, while the Enhanced MPW is enabled 1286 * by default. 1287 */ 1288 if (config->mps == MLX5_ARG_UNSET) 1289 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1290 MLX5_MPW_DISABLED; 1291 else 1292 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1293 DRV_LOG(INFO, "%sMPS is %s", 1294 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1295 config->mps == MLX5_MPW ? "legacy " : "", 1296 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1297 if (sh->devx) { 1298 config->hca_attr = sh->cdev->config.hca_attr; 1299 sh->steering_format_version = 1300 config->hca_attr.steering_format_version; 1301 /* Check for LRO support. */ 1302 if (config->dest_tir && config->hca_attr.lro_cap && 1303 config->dv_flow_en) { 1304 /* TBD check tunnel lro caps. */ 1305 config->lro.supported = config->hca_attr.lro_cap; 1306 DRV_LOG(DEBUG, "Device supports LRO"); 1307 /* 1308 * If LRO timeout is not configured by application, 1309 * use the minimal supported value. 1310 */ 1311 if (!config->lro.timeout) 1312 config->lro.timeout = 1313 config->hca_attr.lro_timer_supported_periods[0]; 1314 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1315 config->lro.timeout); 1316 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1317 "required for coalescing is %d bytes", 1318 config->hca_attr.lro_min_mss_size); 1319 } 1320 #if defined(HAVE_MLX5DV_DR) && \ 1321 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1322 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1323 if (config->hca_attr.qos.sup && 1324 config->hca_attr.qos.flow_meter_old && 1325 config->dv_flow_en) { 1326 uint8_t reg_c_mask = 1327 config->hca_attr.qos.flow_meter_reg_c_ids; 1328 /* 1329 * Meter needs two REG_C's for color match and pre-sfx 1330 * flow match. Here get the REG_C for color match. 1331 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1332 */ 1333 reg_c_mask &= 0xfc; 1334 if (__builtin_popcount(reg_c_mask) < 1) { 1335 priv->mtr_en = 0; 1336 DRV_LOG(WARNING, "No available register for" 1337 " meter."); 1338 } else { 1339 /* 1340 * The meter color register is used by the 1341 * flow-hit feature as well. 1342 * The flow-hit feature must use REG_C_3 1343 * Prefer REG_C_3 if it is available. 1344 */ 1345 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1346 priv->mtr_color_reg = REG_C_3; 1347 else 1348 priv->mtr_color_reg = ffs(reg_c_mask) 1349 - 1 + REG_C_0; 1350 priv->mtr_en = 1; 1351 priv->mtr_reg_share = 1352 config->hca_attr.qos.flow_meter; 1353 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1354 priv->mtr_color_reg); 1355 } 1356 } 1357 if (config->hca_attr.qos.sup && 1358 config->hca_attr.qos.flow_meter_aso_sup) { 1359 uint32_t log_obj_size = 1360 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1361 if (log_obj_size >= 1362 config->hca_attr.qos.log_meter_aso_granularity && 1363 log_obj_size <= 1364 config->hca_attr.qos.log_meter_aso_max_alloc) 1365 sh->meter_aso_en = 1; 1366 } 1367 if (priv->mtr_en) { 1368 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1369 if (err) { 1370 err = -err; 1371 goto error; 1372 } 1373 } 1374 if (config->hca_attr.flow.tunnel_header_0_1) 1375 sh->tunnel_header_0_1 = 1; 1376 #endif 1377 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1378 if (config->hca_attr.flow_hit_aso && 1379 priv->mtr_color_reg == REG_C_3) { 1380 sh->flow_hit_aso_en = 1; 1381 err = mlx5_flow_aso_age_mng_init(sh); 1382 if (err) { 1383 err = -err; 1384 goto error; 1385 } 1386 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1387 } 1388 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1389 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1390 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1391 if (config->hca_attr.ct_offload && 1392 priv->mtr_color_reg == REG_C_3) { 1393 err = mlx5_flow_aso_ct_mng_init(sh); 1394 if (err) { 1395 err = -err; 1396 goto error; 1397 } 1398 DRV_LOG(DEBUG, "CT ASO is supported."); 1399 sh->ct_aso_en = 1; 1400 } 1401 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1402 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1403 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1404 config->dv_flow_en) { 1405 priv->sampler_en = 1; 1406 DRV_LOG(DEBUG, "Sampler enabled!"); 1407 } else { 1408 priv->sampler_en = 0; 1409 if (!config->hca_attr.log_max_ft_sampler_num) 1410 DRV_LOG(WARNING, 1411 "No available register for sampler."); 1412 else 1413 DRV_LOG(DEBUG, "DV flow is not supported!"); 1414 } 1415 #endif 1416 } 1417 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1418 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1419 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1420 config->cqe_comp = 0; 1421 } 1422 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1423 (!sh->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1424 DRV_LOG(WARNING, "Flow Tag CQE compression" 1425 " format isn't supported."); 1426 config->cqe_comp = 0; 1427 } 1428 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1429 (!sh->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1430 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1431 " format isn't supported."); 1432 config->cqe_comp = 0; 1433 } 1434 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1435 config->cqe_comp ? "" : "not "); 1436 if (config->tx_pp) { 1437 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1438 config->hca_attr.dev_freq_khz); 1439 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1440 config->hca_attr.qos.packet_pacing ? "" : "not "); 1441 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1442 config->hca_attr.cross_channel ? "" : "not "); 1443 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1444 config->hca_attr.wqe_index_ignore ? "" : "not "); 1445 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1446 config->hca_attr.non_wire_sq ? "" : "not "); 1447 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1448 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1449 config->hca_attr.log_max_static_sq_wq); 1450 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1451 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1452 if (!sh->devx) { 1453 DRV_LOG(ERR, "DevX is required for packet pacing"); 1454 err = ENODEV; 1455 goto error; 1456 } 1457 if (!config->hca_attr.qos.packet_pacing) { 1458 DRV_LOG(ERR, "Packet pacing is not supported"); 1459 err = ENODEV; 1460 goto error; 1461 } 1462 if (!config->hca_attr.cross_channel) { 1463 DRV_LOG(ERR, "Cross channel operations are" 1464 " required for packet pacing"); 1465 err = ENODEV; 1466 goto error; 1467 } 1468 if (!config->hca_attr.wqe_index_ignore) { 1469 DRV_LOG(ERR, "WQE index ignore feature is" 1470 " required for packet pacing"); 1471 err = ENODEV; 1472 goto error; 1473 } 1474 if (!config->hca_attr.non_wire_sq) { 1475 DRV_LOG(ERR, "Non-wire SQ feature is" 1476 " required for packet pacing"); 1477 err = ENODEV; 1478 goto error; 1479 } 1480 if (!config->hca_attr.log_max_static_sq_wq) { 1481 DRV_LOG(ERR, "Static WQE SQ feature is" 1482 " required for packet pacing"); 1483 err = ENODEV; 1484 goto error; 1485 } 1486 if (!config->hca_attr.qos.wqe_rate_pp) { 1487 DRV_LOG(ERR, "WQE rate mode is required" 1488 " for packet pacing"); 1489 err = ENODEV; 1490 goto error; 1491 } 1492 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1493 DRV_LOG(ERR, "DevX does not provide UAR offset," 1494 " can't create queues for packet pacing"); 1495 err = ENODEV; 1496 goto error; 1497 #endif 1498 } 1499 if (sh->devx) { 1500 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1501 1502 err = config->hca_attr.access_register_user ? 1503 mlx5_devx_cmd_register_read 1504 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1505 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1506 if (!err) { 1507 uint32_t ts_mode; 1508 1509 /* MTUTC register is read successfully. */ 1510 ts_mode = MLX5_GET(register_mtutc, reg, 1511 time_stamp_mode); 1512 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1513 config->rt_timestamp = 1; 1514 } else { 1515 /* Kernel does not support register reading. */ 1516 if (config->hca_attr.dev_freq_khz == 1517 (NS_PER_S / MS_PER_S)) 1518 config->rt_timestamp = 1; 1519 } 1520 } 1521 /* 1522 * If HW has bug working with tunnel packet decapsulation and 1523 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1524 * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1525 */ 1526 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1527 config->hw_fcs_strip = 0; 1528 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1529 (config->hw_fcs_strip ? "" : "not ")); 1530 if (config->mprq.enabled && mprq) { 1531 if (config->mprq.stride_num_n && 1532 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1533 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1534 config->mprq.stride_num_n = 1535 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1536 mprq_min_stride_num_n), 1537 mprq_max_stride_num_n); 1538 DRV_LOG(WARNING, 1539 "the number of strides" 1540 " for Multi-Packet RQ is out of range," 1541 " setting default value (%u)", 1542 1 << config->mprq.stride_num_n); 1543 } 1544 if (config->mprq.stride_size_n && 1545 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1546 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1547 config->mprq.stride_size_n = 1548 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1549 mprq_min_stride_size_n), 1550 mprq_max_stride_size_n); 1551 DRV_LOG(WARNING, 1552 "the size of a stride" 1553 " for Multi-Packet RQ is out of range," 1554 " setting default value (%u)", 1555 1 << config->mprq.stride_size_n); 1556 } 1557 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1558 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1559 } else if (config->mprq.enabled && !mprq) { 1560 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1561 config->mprq.enabled = 0; 1562 } 1563 if (config->max_dump_files_num == 0) 1564 config->max_dump_files_num = 128; 1565 eth_dev = rte_eth_dev_allocate(name); 1566 if (eth_dev == NULL) { 1567 DRV_LOG(ERR, "can not allocate rte ethdev"); 1568 err = ENOMEM; 1569 goto error; 1570 } 1571 if (priv->representor) { 1572 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1573 eth_dev->data->representor_id = priv->representor_id; 1574 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1575 struct mlx5_priv *opriv = 1576 rte_eth_devices[port_id].data->dev_private; 1577 if (opriv && 1578 opriv->master && 1579 opriv->domain_id == priv->domain_id && 1580 opriv->sh == priv->sh) { 1581 eth_dev->data->backer_port_id = port_id; 1582 break; 1583 } 1584 } 1585 if (port_id >= RTE_MAX_ETHPORTS) 1586 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1587 } 1588 priv->mp_id.port_id = eth_dev->data->port_id; 1589 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1590 /* 1591 * Store associated network device interface index. This index 1592 * is permanent throughout the lifetime of device. So, we may store 1593 * the ifindex here and use the cached value further. 1594 */ 1595 MLX5_ASSERT(spawn->ifindex); 1596 priv->if_index = spawn->ifindex; 1597 priv->lag_affinity_idx = sh->refcnt - 1; 1598 eth_dev->data->dev_private = priv; 1599 priv->dev_data = eth_dev->data; 1600 eth_dev->data->mac_addrs = priv->mac; 1601 eth_dev->device = dpdk_dev; 1602 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1603 /* Configure the first MAC address by default. */ 1604 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1605 DRV_LOG(ERR, 1606 "port %u cannot get MAC address, is mlx5_en" 1607 " loaded? (errno: %s)", 1608 eth_dev->data->port_id, strerror(rte_errno)); 1609 err = ENODEV; 1610 goto error; 1611 } 1612 DRV_LOG(INFO, 1613 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1614 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1615 #ifdef RTE_LIBRTE_MLX5_DEBUG 1616 { 1617 char ifname[MLX5_NAMESIZE]; 1618 1619 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1620 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1621 eth_dev->data->port_id, ifname); 1622 else 1623 DRV_LOG(DEBUG, "port %u ifname is unknown", 1624 eth_dev->data->port_id); 1625 } 1626 #endif 1627 /* Get actual MTU if possible. */ 1628 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1629 if (err) { 1630 err = rte_errno; 1631 goto error; 1632 } 1633 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1634 priv->mtu); 1635 /* Initialize burst functions to prevent crashes before link-up. */ 1636 eth_dev->rx_pkt_burst = removed_rx_burst; 1637 eth_dev->tx_pkt_burst = removed_tx_burst; 1638 eth_dev->dev_ops = &mlx5_dev_ops; 1639 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1640 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1641 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1642 /* Register MAC address. */ 1643 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1644 if (config->vf && config->vf_nl_en) 1645 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1646 mlx5_ifindex(eth_dev), 1647 eth_dev->data->mac_addrs, 1648 MLX5_MAX_MAC_ADDRESSES); 1649 priv->ctrl_flows = 0; 1650 rte_spinlock_init(&priv->flow_list_lock); 1651 TAILQ_INIT(&priv->flow_meters); 1652 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1653 if (!priv->mtr_profile_tbl) 1654 goto error; 1655 /* Bring Ethernet device up. */ 1656 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1657 eth_dev->data->port_id); 1658 mlx5_set_link_up(eth_dev); 1659 /* 1660 * Even though the interrupt handler is not installed yet, 1661 * interrupts will still trigger on the async_fd from 1662 * Verbs context returned by ibv_open_device(). 1663 */ 1664 mlx5_link_update(eth_dev, 0); 1665 #ifdef HAVE_MLX5DV_DR_ESWITCH 1666 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1667 (switch_info->representor || switch_info->master))) 1668 config->dv_esw_en = 0; 1669 #else 1670 config->dv_esw_en = 0; 1671 #endif 1672 /* Detect minimal data bytes to inline. */ 1673 mlx5_set_min_inline(spawn, config); 1674 /* Store device configuration on private structure. */ 1675 priv->config = *config; 1676 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1677 icfg[i].release_mem_en = !!config->reclaim_mode; 1678 if (config->reclaim_mode) 1679 icfg[i].per_core_cache = 0; 1680 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1681 if (!priv->flows[i]) 1682 goto error; 1683 } 1684 /* Create context for virtual machine VLAN workaround. */ 1685 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1686 if (config->dv_flow_en) { 1687 err = mlx5_alloc_shared_dr(priv); 1688 if (err) 1689 goto error; 1690 } 1691 if (sh->devx && config->dv_flow_en && config->dest_tir) { 1692 priv->obj_ops = devx_obj_ops; 1693 mlx5_queue_counter_id_prepare(eth_dev); 1694 priv->obj_ops.lb_dummy_queue_create = 1695 mlx5_rxq_ibv_obj_dummy_lb_create; 1696 priv->obj_ops.lb_dummy_queue_release = 1697 mlx5_rxq_ibv_obj_dummy_lb_release; 1698 } else if (spawn->max_port > UINT8_MAX) { 1699 /* Verbs can't support ports larger than 255 by design. */ 1700 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); 1701 err = ENOTSUP; 1702 goto error; 1703 } else { 1704 priv->obj_ops = ibv_obj_ops; 1705 } 1706 if (config->tx_pp && 1707 (priv->config.dv_esw_en || 1708 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new)) { 1709 /* 1710 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1711 * packet pacing and already checked above. 1712 * Hence, we should only make sure the SQs will be created 1713 * with DevX, not with Verbs. 1714 * Verbs allocates the SQ UAR on its own and it can't be shared 1715 * with Clock Queue UAR as required for Tx scheduling. 1716 */ 1717 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1718 err = ENODEV; 1719 goto error; 1720 } 1721 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1722 if (!priv->drop_queue.hrxq) 1723 goto error; 1724 /* Port representor shares the same max prioirity with pf port. */ 1725 if (!priv->sh->flow_priority_check_flag) { 1726 /* Supported Verbs flow priority number detection. */ 1727 err = mlx5_flow_discover_priorities(eth_dev); 1728 priv->sh->flow_max_priority = err; 1729 priv->sh->flow_priority_check_flag = 1; 1730 } else { 1731 err = priv->sh->flow_max_priority; 1732 } 1733 if (err < 0) { 1734 err = -err; 1735 goto error; 1736 } 1737 if (!priv->config.dv_esw_en && 1738 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1739 DRV_LOG(WARNING, "metadata mode %u is not supported " 1740 "(no E-Switch)", priv->config.dv_xmeta_en); 1741 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1742 } 1743 mlx5_set_metadata_mask(eth_dev); 1744 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1745 !priv->sh->dv_regc0_mask) { 1746 DRV_LOG(ERR, "metadata mode %u is not supported " 1747 "(no metadata reg_c[0] is available)", 1748 priv->config.dv_xmeta_en); 1749 err = ENOTSUP; 1750 goto error; 1751 } 1752 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1753 mlx5_hrxq_create_cb, 1754 mlx5_hrxq_match_cb, 1755 mlx5_hrxq_remove_cb, 1756 mlx5_hrxq_clone_cb, 1757 mlx5_hrxq_clone_free_cb); 1758 if (!priv->hrxqs) 1759 goto error; 1760 rte_rwlock_init(&priv->ind_tbls_lock); 1761 /* Query availability of metadata reg_c's. */ 1762 if (!priv->sh->metadata_regc_check_flag) { 1763 err = mlx5_flow_discover_mreg_c(eth_dev); 1764 if (err < 0) { 1765 err = -err; 1766 goto error; 1767 } 1768 } 1769 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1770 DRV_LOG(DEBUG, 1771 "port %u extensive metadata register is not supported", 1772 eth_dev->data->port_id); 1773 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1774 DRV_LOG(ERR, "metadata mode %u is not supported " 1775 "(no metadata registers available)", 1776 priv->config.dv_xmeta_en); 1777 err = ENOTSUP; 1778 goto error; 1779 } 1780 } 1781 if (priv->config.dv_flow_en && 1782 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1783 mlx5_flow_ext_mreg_supported(eth_dev) && 1784 priv->sh->dv_regc0_mask) { 1785 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1786 MLX5_FLOW_MREG_HTABLE_SZ, 1787 false, true, eth_dev, 1788 flow_dv_mreg_create_cb, 1789 flow_dv_mreg_match_cb, 1790 flow_dv_mreg_remove_cb, 1791 flow_dv_mreg_clone_cb, 1792 flow_dv_mreg_clone_free_cb); 1793 if (!priv->mreg_cp_tbl) { 1794 err = ENOMEM; 1795 goto error; 1796 } 1797 } 1798 rte_spinlock_init(&priv->shared_act_sl); 1799 mlx5_flow_counter_mode_config(eth_dev); 1800 mlx5_flow_drop_action_config(eth_dev); 1801 if (priv->config.dv_flow_en) 1802 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1803 return eth_dev; 1804 error: 1805 if (priv) { 1806 if (priv->mreg_cp_tbl) 1807 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1808 if (priv->sh) 1809 mlx5_os_free_shared_dr(priv); 1810 if (priv->nl_socket_route >= 0) 1811 close(priv->nl_socket_route); 1812 if (priv->vmwa_context) 1813 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1814 if (eth_dev && priv->drop_queue.hrxq) 1815 mlx5_drop_action_destroy(eth_dev); 1816 if (priv->mtr_profile_tbl) 1817 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1818 if (own_domain_id) 1819 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1820 if (priv->hrxqs) 1821 mlx5_list_destroy(priv->hrxqs); 1822 mlx5_free(priv); 1823 if (eth_dev != NULL) 1824 eth_dev->data->dev_private = NULL; 1825 } 1826 if (eth_dev != NULL) { 1827 /* mac_addrs must not be freed alone because part of 1828 * dev_private 1829 **/ 1830 eth_dev->data->mac_addrs = NULL; 1831 rte_eth_dev_release_port(eth_dev); 1832 } 1833 if (sh) 1834 mlx5_free_shared_dev_ctx(sh); 1835 if (nl_rdma >= 0) 1836 close(nl_rdma); 1837 MLX5_ASSERT(err > 0); 1838 rte_errno = err; 1839 return NULL; 1840 } 1841 1842 /** 1843 * Comparison callback to sort device data. 1844 * 1845 * This is meant to be used with qsort(). 1846 * 1847 * @param a[in] 1848 * Pointer to pointer to first data object. 1849 * @param b[in] 1850 * Pointer to pointer to second data object. 1851 * 1852 * @return 1853 * 0 if both objects are equal, less than 0 if the first argument is less 1854 * than the second, greater than 0 otherwise. 1855 */ 1856 static int 1857 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1858 { 1859 const struct mlx5_switch_info *si_a = 1860 &((const struct mlx5_dev_spawn_data *)a)->info; 1861 const struct mlx5_switch_info *si_b = 1862 &((const struct mlx5_dev_spawn_data *)b)->info; 1863 int ret; 1864 1865 /* Master device first. */ 1866 ret = si_b->master - si_a->master; 1867 if (ret) 1868 return ret; 1869 /* Then representor devices. */ 1870 ret = si_b->representor - si_a->representor; 1871 if (ret) 1872 return ret; 1873 /* Unidentified devices come last in no specific order. */ 1874 if (!si_a->representor) 1875 return 0; 1876 /* Order representors by name. */ 1877 return si_a->port_name - si_b->port_name; 1878 } 1879 1880 /** 1881 * Match PCI information for possible slaves of bonding device. 1882 * 1883 * @param[in] ibdev_name 1884 * Name of Infiniband device. 1885 * @param[in] pci_dev 1886 * Pointer to primary PCI address structure to match. 1887 * @param[in] nl_rdma 1888 * Netlink RDMA group socket handle. 1889 * @param[in] owner 1890 * Representor owner PF index. 1891 * @param[out] bond_info 1892 * Pointer to bonding information. 1893 * 1894 * @return 1895 * negative value if no bonding device found, otherwise 1896 * positive index of slave PF in bonding. 1897 */ 1898 static int 1899 mlx5_device_bond_pci_match(const char *ibdev_name, 1900 const struct rte_pci_addr *pci_dev, 1901 int nl_rdma, uint16_t owner, 1902 struct mlx5_bond_info *bond_info) 1903 { 1904 char ifname[IF_NAMESIZE + 1]; 1905 unsigned int ifindex; 1906 unsigned int np, i; 1907 FILE *bond_file = NULL, *file; 1908 int pf = -1; 1909 int ret; 1910 uint8_t cur_guid[32] = {0}; 1911 uint8_t guid[32] = {0}; 1912 1913 /* 1914 * Try to get master device name. If something goes wrong suppose 1915 * the lack of kernel support and no bonding devices. 1916 */ 1917 memset(bond_info, 0, sizeof(*bond_info)); 1918 if (nl_rdma < 0) 1919 return -1; 1920 if (!strstr(ibdev_name, "bond")) 1921 return -1; 1922 np = mlx5_nl_portnum(nl_rdma, ibdev_name); 1923 if (!np) 1924 return -1; 1925 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) 1926 return -1; 1927 /* 1928 * The master device might not be on the predefined port(not on port 1929 * index 1, it is not guaranteed), we have to scan all Infiniband 1930 * device ports and find master. 1931 */ 1932 for (i = 1; i <= np; ++i) { 1933 /* Check whether Infiniband port is populated. */ 1934 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); 1935 if (!ifindex) 1936 continue; 1937 if (!if_indextoname(ifindex, ifname)) 1938 continue; 1939 /* Try to read bonding slave names from sysfs. */ 1940 MKSTR(slaves, 1941 "/sys/class/net/%s/master/bonding/slaves", ifname); 1942 bond_file = fopen(slaves, "r"); 1943 if (bond_file) 1944 break; 1945 } 1946 if (!bond_file) 1947 return -1; 1948 /* Use safe format to check maximal buffer length. */ 1949 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1950 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1951 char tmp_str[IF_NAMESIZE + 32]; 1952 struct rte_pci_addr pci_addr; 1953 struct mlx5_switch_info info; 1954 int ret; 1955 1956 /* Process slave interface names in the loop. */ 1957 snprintf(tmp_str, sizeof(tmp_str), 1958 "/sys/class/net/%s", ifname); 1959 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 1960 DRV_LOG(WARNING, 1961 "Cannot get PCI address for netdev \"%s\".", 1962 ifname); 1963 continue; 1964 } 1965 /* Slave interface PCI address match found. */ 1966 snprintf(tmp_str, sizeof(tmp_str), 1967 "/sys/class/net/%s/phys_port_name", ifname); 1968 file = fopen(tmp_str, "rb"); 1969 if (!file) 1970 break; 1971 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1972 if (fscanf(file, "%32s", tmp_str) == 1) 1973 mlx5_translate_port_name(tmp_str, &info); 1974 fclose(file); 1975 /* Only process PF ports. */ 1976 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1977 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1978 continue; 1979 /* Check max bonding member. */ 1980 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1981 DRV_LOG(WARNING, "bonding index out of range, " 1982 "please increase MLX5_BOND_MAX_PORTS: %s", 1983 tmp_str); 1984 break; 1985 } 1986 /* Get ifindex. */ 1987 snprintf(tmp_str, sizeof(tmp_str), 1988 "/sys/class/net/%s/ifindex", ifname); 1989 file = fopen(tmp_str, "rb"); 1990 if (!file) 1991 break; 1992 ret = fscanf(file, "%u", &ifindex); 1993 fclose(file); 1994 if (ret != 1) 1995 break; 1996 /* Save bonding info. */ 1997 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1998 sizeof(bond_info->ports[0].ifname)); 1999 bond_info->ports[info.port_name].pci_addr = pci_addr; 2000 bond_info->ports[info.port_name].ifindex = ifindex; 2001 bond_info->n_port++; 2002 /* 2003 * Under socket direct mode, bonding will use 2004 * system_image_guid as identification. 2005 * After OFED 5.4, guid is readable (ret >= 0) under sysfs. 2006 * All bonding members should have the same guid even if driver 2007 * is using PCIe BDF. 2008 */ 2009 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid)); 2010 if (ret < 0) 2011 break; 2012 else if (ret > 0) { 2013 if (!memcmp(guid, cur_guid, sizeof(guid)) && 2014 owner == info.port_name && 2015 (owner != 0 || (owner == 0 && 2016 !rte_pci_addr_cmp(pci_dev, &pci_addr)))) 2017 pf = info.port_name; 2018 } else if (pci_dev->domain == pci_addr.domain && 2019 pci_dev->bus == pci_addr.bus && 2020 pci_dev->devid == pci_addr.devid && 2021 ((pci_dev->function == 0 && 2022 pci_dev->function + owner == pci_addr.function) || 2023 (pci_dev->function == owner && 2024 pci_addr.function == owner))) 2025 pf = info.port_name; 2026 } 2027 if (pf >= 0) { 2028 /* Get bond interface info */ 2029 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2030 bond_info->ifname); 2031 if (ret) 2032 DRV_LOG(ERR, "unable to get bond info: %s", 2033 strerror(rte_errno)); 2034 else 2035 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2036 ifindex, bond_info->ifindex, bond_info->ifname); 2037 } 2038 if (owner == 0 && pf != 0) { 2039 DRV_LOG(INFO, "PCIe instance %04x:%02x:%02x.%x isn't bonding owner", 2040 pci_dev->domain, pci_dev->bus, pci_dev->devid, 2041 pci_dev->function); 2042 } 2043 return pf; 2044 } 2045 2046 static void 2047 mlx5_os_config_default(struct mlx5_dev_config *config) 2048 { 2049 memset(config, 0, sizeof(*config)); 2050 config->mps = MLX5_ARG_UNSET; 2051 config->rx_vec_en = 1; 2052 config->txq_inline_max = MLX5_ARG_UNSET; 2053 config->txq_inline_min = MLX5_ARG_UNSET; 2054 config->txq_inline_mpw = MLX5_ARG_UNSET; 2055 config->txqs_inline = MLX5_ARG_UNSET; 2056 config->vf_nl_en = 1; 2057 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2058 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2059 config->dv_esw_en = 1; 2060 config->dv_flow_en = 1; 2061 config->decap_en = 1; 2062 config->log_hp_size = MLX5_ARG_UNSET; 2063 config->allow_duplicate_pattern = 1; 2064 } 2065 2066 /** 2067 * Register a PCI device within bonding. 2068 * 2069 * This function spawns Ethernet devices out of a given PCI device and 2070 * bonding owner PF index. 2071 * 2072 * @param[in] cdev 2073 * Pointer to common mlx5 device structure. 2074 * @param[in] req_eth_da 2075 * Requested ethdev device argument. 2076 * @param[in] owner_id 2077 * Requested owner PF port ID within bonding device, default to 0. 2078 * 2079 * @return 2080 * 0 on success, a negative errno value otherwise and rte_errno is set. 2081 */ 2082 static int 2083 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, 2084 struct rte_eth_devargs *req_eth_da, 2085 uint16_t owner_id) 2086 { 2087 struct ibv_device **ibv_list; 2088 /* 2089 * Number of found IB Devices matching with requested PCI BDF. 2090 * nd != 1 means there are multiple IB devices over the same 2091 * PCI device and we have representors and master. 2092 */ 2093 unsigned int nd = 0; 2094 /* 2095 * Number of found IB device Ports. nd = 1 and np = 1..n means 2096 * we have the single multiport IB device, and there may be 2097 * representors attached to some of found ports. 2098 */ 2099 unsigned int np = 0; 2100 /* 2101 * Number of DPDK ethernet devices to Spawn - either over 2102 * multiple IB devices or multiple ports of single IB device. 2103 * Actually this is the number of iterations to spawn. 2104 */ 2105 unsigned int ns = 0; 2106 /* 2107 * Bonding device 2108 * < 0 - no bonding device (single one) 2109 * >= 0 - bonding device (value is slave PF index) 2110 */ 2111 int bd = -1; 2112 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2113 struct mlx5_dev_spawn_data *list = NULL; 2114 struct mlx5_dev_config dev_config; 2115 unsigned int dev_config_vf; 2116 struct rte_eth_devargs eth_da = *req_eth_da; 2117 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2118 struct mlx5_bond_info bond_info; 2119 int ret = -1; 2120 2121 errno = 0; 2122 ibv_list = mlx5_glue->get_device_list(&ret); 2123 if (!ibv_list) { 2124 rte_errno = errno ? errno : ENOSYS; 2125 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?"); 2126 return -rte_errno; 2127 } 2128 /* 2129 * First scan the list of all Infiniband devices to find 2130 * matching ones, gathering into the list. 2131 */ 2132 struct ibv_device *ibv_match[ret + 1]; 2133 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2134 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2135 unsigned int i; 2136 2137 while (ret-- > 0) { 2138 struct rte_pci_addr pci_addr; 2139 2140 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); 2141 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, 2142 nl_rdma, owner_id, &bond_info); 2143 if (bd >= 0) { 2144 /* 2145 * Bonding device detected. Only one match is allowed, 2146 * the bonding is supported over multi-port IB device, 2147 * there should be no matches on representor PCI 2148 * functions or non VF LAG bonding devices with 2149 * specified address. 2150 */ 2151 if (nd) { 2152 DRV_LOG(ERR, 2153 "multiple PCI match on bonding device" 2154 "\"%s\" found", ibv_list[ret]->name); 2155 rte_errno = ENOENT; 2156 ret = -rte_errno; 2157 goto exit; 2158 } 2159 /* Amend owner pci address if owner PF ID specified. */ 2160 if (eth_da.nb_representor_ports) 2161 owner_pci.function += owner_id; 2162 DRV_LOG(INFO, 2163 "PCI information matches for slave %d bonding device \"%s\"", 2164 bd, ibv_list[ret]->name); 2165 ibv_match[nd++] = ibv_list[ret]; 2166 break; 2167 } else { 2168 /* Bonding device not found. */ 2169 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2170 &pci_addr)) 2171 continue; 2172 if (owner_pci.domain != pci_addr.domain || 2173 owner_pci.bus != pci_addr.bus || 2174 owner_pci.devid != pci_addr.devid || 2175 owner_pci.function != pci_addr.function) 2176 continue; 2177 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2178 ibv_list[ret]->name); 2179 ibv_match[nd++] = ibv_list[ret]; 2180 } 2181 } 2182 ibv_match[nd] = NULL; 2183 if (!nd) { 2184 /* No device matches, just complain and bail out. */ 2185 DRV_LOG(WARNING, 2186 "No Verbs device matches PCI device " PCI_PRI_FMT "," 2187 " are kernel drivers loaded?", 2188 owner_pci.domain, owner_pci.bus, 2189 owner_pci.devid, owner_pci.function); 2190 rte_errno = ENOENT; 2191 ret = -rte_errno; 2192 goto exit; 2193 } 2194 if (nd == 1) { 2195 /* 2196 * Found single matching device may have multiple ports. 2197 * Each port may be representor, we have to check the port 2198 * number and check the representors existence. 2199 */ 2200 if (nl_rdma >= 0) 2201 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2202 if (!np) 2203 DRV_LOG(WARNING, 2204 "Cannot get IB device \"%s\" ports number.", 2205 ibv_match[0]->name); 2206 if (bd >= 0 && !np) { 2207 DRV_LOG(ERR, "Cannot get ports for bonding device."); 2208 rte_errno = ENOENT; 2209 ret = -rte_errno; 2210 goto exit; 2211 } 2212 } 2213 /* Now we can determine the maximal amount of devices to be spawned. */ 2214 list = mlx5_malloc(MLX5_MEM_ZERO, 2215 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd), 2216 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2217 if (!list) { 2218 DRV_LOG(ERR, "Spawn data array allocation failure."); 2219 rte_errno = ENOMEM; 2220 ret = -rte_errno; 2221 goto exit; 2222 } 2223 if (bd >= 0 || np > 1) { 2224 /* 2225 * Single IB device with multiple ports found, 2226 * it may be E-Switch master device and representors. 2227 * We have to perform identification through the ports. 2228 */ 2229 MLX5_ASSERT(nl_rdma >= 0); 2230 MLX5_ASSERT(ns == 0); 2231 MLX5_ASSERT(nd == 1); 2232 MLX5_ASSERT(np); 2233 for (i = 1; i <= np; ++i) { 2234 list[ns].bond_info = &bond_info; 2235 list[ns].max_port = np; 2236 list[ns].phys_port = i; 2237 list[ns].phys_dev_name = ibv_match[0]->name; 2238 list[ns].eth_dev = NULL; 2239 list[ns].pci_dev = pci_dev; 2240 list[ns].cdev = cdev; 2241 list[ns].pf_bond = bd; 2242 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, 2243 ibv_match[0]->name, 2244 i); 2245 if (!list[ns].ifindex) { 2246 /* 2247 * No network interface index found for the 2248 * specified port, it means there is no 2249 * representor on this port. It's OK, 2250 * there can be disabled ports, for example 2251 * if sriov_numvfs < sriov_totalvfs. 2252 */ 2253 continue; 2254 } 2255 ret = -1; 2256 if (nl_route >= 0) 2257 ret = mlx5_nl_switch_info(nl_route, 2258 list[ns].ifindex, 2259 &list[ns].info); 2260 if (ret || (!list[ns].info.representor && 2261 !list[ns].info.master)) { 2262 /* 2263 * We failed to recognize representors with 2264 * Netlink, let's try to perform the task 2265 * with sysfs. 2266 */ 2267 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2268 &list[ns].info); 2269 } 2270 if (!ret && bd >= 0) { 2271 switch (list[ns].info.name_type) { 2272 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2273 if (np == 1) { 2274 /* 2275 * Force standalone bonding 2276 * device for ROCE LAG 2277 * confgiurations. 2278 */ 2279 list[ns].info.master = 0; 2280 list[ns].info.representor = 0; 2281 } 2282 if (list[ns].info.port_name == bd) 2283 ns++; 2284 break; 2285 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2286 /* Fallthrough */ 2287 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2288 /* Fallthrough */ 2289 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2290 if (list[ns].info.pf_num == bd) 2291 ns++; 2292 break; 2293 default: 2294 break; 2295 } 2296 continue; 2297 } 2298 if (!ret && (list[ns].info.representor ^ 2299 list[ns].info.master)) 2300 ns++; 2301 } 2302 if (!ns) { 2303 DRV_LOG(ERR, 2304 "Unable to recognize master/representors on the IB device with multiple ports."); 2305 rte_errno = ENOENT; 2306 ret = -rte_errno; 2307 goto exit; 2308 } 2309 } else { 2310 /* 2311 * The existence of several matching entries (nd > 1) means 2312 * port representors have been instantiated. No existing Verbs 2313 * call nor sysfs entries can tell them apart, this can only 2314 * be done through Netlink calls assuming kernel drivers are 2315 * recent enough to support them. 2316 * 2317 * In the event of identification failure through Netlink, 2318 * try again through sysfs, then: 2319 * 2320 * 1. A single IB device matches (nd == 1) with single 2321 * port (np=0/1) and is not a representor, assume 2322 * no switch support. 2323 * 2324 * 2. Otherwise no safe assumptions can be made; 2325 * complain louder and bail out. 2326 */ 2327 for (i = 0; i != nd; ++i) { 2328 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2329 list[ns].bond_info = NULL; 2330 list[ns].max_port = 1; 2331 list[ns].phys_port = 1; 2332 list[ns].phys_dev_name = ibv_match[i]->name; 2333 list[ns].eth_dev = NULL; 2334 list[ns].pci_dev = pci_dev; 2335 list[ns].cdev = cdev; 2336 list[ns].pf_bond = -1; 2337 list[ns].ifindex = 0; 2338 if (nl_rdma >= 0) 2339 list[ns].ifindex = mlx5_nl_ifindex 2340 (nl_rdma, 2341 ibv_match[i]->name, 2342 1); 2343 if (!list[ns].ifindex) { 2344 char ifname[IF_NAMESIZE]; 2345 2346 /* 2347 * Netlink failed, it may happen with old 2348 * ib_core kernel driver (before 4.16). 2349 * We can assume there is old driver because 2350 * here we are processing single ports IB 2351 * devices. Let's try sysfs to retrieve 2352 * the ifindex. The method works for 2353 * master device only. 2354 */ 2355 if (nd > 1) { 2356 /* 2357 * Multiple devices found, assume 2358 * representors, can not distinguish 2359 * master/representor and retrieve 2360 * ifindex via sysfs. 2361 */ 2362 continue; 2363 } 2364 ret = mlx5_get_ifname_sysfs 2365 (ibv_match[i]->ibdev_path, ifname); 2366 if (!ret) 2367 list[ns].ifindex = 2368 if_nametoindex(ifname); 2369 if (!list[ns].ifindex) { 2370 /* 2371 * No network interface index found 2372 * for the specified device, it means 2373 * there it is neither representor 2374 * nor master. 2375 */ 2376 continue; 2377 } 2378 } 2379 ret = -1; 2380 if (nl_route >= 0) 2381 ret = mlx5_nl_switch_info(nl_route, 2382 list[ns].ifindex, 2383 &list[ns].info); 2384 if (ret || (!list[ns].info.representor && 2385 !list[ns].info.master)) { 2386 /* 2387 * We failed to recognize representors with 2388 * Netlink, let's try to perform the task 2389 * with sysfs. 2390 */ 2391 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2392 &list[ns].info); 2393 } 2394 if (!ret && (list[ns].info.representor ^ 2395 list[ns].info.master)) { 2396 ns++; 2397 } else if ((nd == 1) && 2398 !list[ns].info.representor && 2399 !list[ns].info.master) { 2400 /* 2401 * Single IB device with one physical port and 2402 * attached network device. 2403 * May be SRIOV is not enabled or there is no 2404 * representors. 2405 */ 2406 DRV_LOG(INFO, "No E-Switch support detected."); 2407 ns++; 2408 break; 2409 } 2410 } 2411 if (!ns) { 2412 DRV_LOG(ERR, 2413 "Unable to recognize master/representors on the multiple IB devices."); 2414 rte_errno = ENOENT; 2415 ret = -rte_errno; 2416 goto exit; 2417 } 2418 /* 2419 * New kernels may add the switch_id attribute for the case 2420 * there is no E-Switch and we wrongly recognized the only 2421 * device as master. Override this if there is the single 2422 * device with single port and new device name format present. 2423 */ 2424 if (nd == 1 && 2425 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2426 list[0].info.master = 0; 2427 list[0].info.representor = 0; 2428 } 2429 } 2430 MLX5_ASSERT(ns); 2431 /* 2432 * Sort list to probe devices in natural order for users convenience 2433 * (i.e. master first, then representors from lowest to highest ID). 2434 */ 2435 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2436 /* Device specific configuration. */ 2437 switch (pci_dev->id.device_id) { 2438 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2439 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2440 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2441 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2442 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2443 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2444 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2445 dev_config_vf = 1; 2446 break; 2447 default: 2448 dev_config_vf = 0; 2449 break; 2450 } 2451 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2452 /* Set devargs default values. */ 2453 if (eth_da.nb_mh_controllers == 0) { 2454 eth_da.nb_mh_controllers = 1; 2455 eth_da.mh_controllers[0] = 0; 2456 } 2457 if (eth_da.nb_ports == 0 && ns > 0) { 2458 if (list[0].pf_bond >= 0 && list[0].info.representor) 2459 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2460 pci_dev->device.devargs->args); 2461 eth_da.nb_ports = 1; 2462 eth_da.ports[0] = list[0].info.pf_num; 2463 } 2464 if (eth_da.nb_representor_ports == 0) { 2465 eth_da.nb_representor_ports = 1; 2466 eth_da.representor_ports[0] = 0; 2467 } 2468 } 2469 for (i = 0; i != ns; ++i) { 2470 uint32_t restore; 2471 2472 /* Default configuration. */ 2473 mlx5_os_config_default(&dev_config); 2474 dev_config.vf = dev_config_vf; 2475 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], 2476 &dev_config, ð_da); 2477 if (!list[i].eth_dev) { 2478 if (rte_errno != EBUSY && rte_errno != EEXIST) 2479 break; 2480 /* Device is disabled or already spawned. Ignore it. */ 2481 continue; 2482 } 2483 restore = list[i].eth_dev->data->dev_flags; 2484 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2485 /** 2486 * Each representor has a dedicated interrupts vector. 2487 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2488 * representor eth_dev object because representor and PF 2489 * share the same PCI address. 2490 * Override representor device with a dedicated 2491 * interrupts handle here. 2492 * Representor interrupts handle is released in mlx5_dev_stop(). 2493 */ 2494 if (list[i].info.representor) { 2495 struct rte_intr_handle *intr_handle = 2496 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2497 if (intr_handle == NULL) { 2498 DRV_LOG(ERR, 2499 "port %u failed to allocate memory for interrupt handler " 2500 "Rx interrupts will not be supported", 2501 i); 2502 rte_errno = ENOMEM; 2503 ret = -rte_errno; 2504 goto exit; 2505 } 2506 list[i].eth_dev->intr_handle = intr_handle; 2507 } 2508 /* Restore non-PCI flags cleared by the above call. */ 2509 list[i].eth_dev->data->dev_flags |= restore; 2510 rte_eth_dev_probing_finish(list[i].eth_dev); 2511 } 2512 if (i != ns) { 2513 DRV_LOG(ERR, 2514 "probe of PCI device " PCI_PRI_FMT " aborted after" 2515 " encountering an error: %s", 2516 owner_pci.domain, owner_pci.bus, 2517 owner_pci.devid, owner_pci.function, 2518 strerror(rte_errno)); 2519 ret = -rte_errno; 2520 /* Roll back. */ 2521 while (i--) { 2522 if (!list[i].eth_dev) 2523 continue; 2524 mlx5_dev_close(list[i].eth_dev); 2525 /* mac_addrs must not be freed because in dev_private */ 2526 list[i].eth_dev->data->mac_addrs = NULL; 2527 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2528 } 2529 /* Restore original error. */ 2530 rte_errno = -ret; 2531 } else { 2532 ret = 0; 2533 } 2534 exit: 2535 /* 2536 * Do the routine cleanup: 2537 * - close opened Netlink sockets 2538 * - free allocated spawn data array 2539 * - free the Infiniband device list 2540 */ 2541 if (nl_rdma >= 0) 2542 close(nl_rdma); 2543 if (nl_route >= 0) 2544 close(nl_route); 2545 if (list) 2546 mlx5_free(list); 2547 MLX5_ASSERT(ibv_list); 2548 mlx5_glue->free_device_list(ibv_list); 2549 return ret; 2550 } 2551 2552 static int 2553 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2554 struct rte_eth_devargs *eth_da) 2555 { 2556 int ret = 0; 2557 2558 if (dev->devargs == NULL) 2559 return 0; 2560 memset(eth_da, 0, sizeof(*eth_da)); 2561 /* Parse representor information first from class argument. */ 2562 if (dev->devargs->cls_str) 2563 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2564 if (ret != 0) { 2565 DRV_LOG(ERR, "failed to parse device arguments: %s", 2566 dev->devargs->cls_str); 2567 return -rte_errno; 2568 } 2569 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2570 /* Parse legacy device argument */ 2571 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2572 if (ret) { 2573 DRV_LOG(ERR, "failed to parse device arguments: %s", 2574 dev->devargs->args); 2575 return -rte_errno; 2576 } 2577 } 2578 return 0; 2579 } 2580 2581 /** 2582 * Callback to register a PCI device. 2583 * 2584 * This function spawns Ethernet devices out of a given PCI device. 2585 * 2586 * @param[in] cdev 2587 * Pointer to common mlx5 device structure. 2588 * 2589 * @return 2590 * 0 on success, a negative errno value otherwise and rte_errno is set. 2591 */ 2592 static int 2593 mlx5_os_pci_probe(struct mlx5_common_device *cdev) 2594 { 2595 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2596 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2597 int ret = 0; 2598 uint16_t p; 2599 2600 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da); 2601 if (ret != 0) 2602 return ret; 2603 2604 if (eth_da.nb_ports > 0) { 2605 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2606 for (p = 0; p < eth_da.nb_ports; p++) { 2607 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 2608 eth_da.ports[p]); 2609 if (ret) 2610 break; 2611 } 2612 if (ret) { 2613 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2614 "aborted due to proding failure of PF %u", 2615 pci_dev->addr.domain, pci_dev->addr.bus, 2616 pci_dev->addr.devid, pci_dev->addr.function, 2617 eth_da.ports[p]); 2618 mlx5_net_remove(cdev); 2619 } 2620 } else { 2621 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0); 2622 } 2623 return ret; 2624 } 2625 2626 /* Probe a single SF device on auxiliary bus, no representor support. */ 2627 static int 2628 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev) 2629 { 2630 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2631 struct mlx5_dev_config config; 2632 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2633 struct rte_device *dev = cdev->dev; 2634 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2635 struct rte_eth_dev *eth_dev; 2636 int ret = 0; 2637 2638 /* Parse ethdev devargs. */ 2639 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2640 if (ret != 0) 2641 return ret; 2642 /* Set default config data. */ 2643 mlx5_os_config_default(&config); 2644 config.sf = 1; 2645 /* Init spawn data. */ 2646 spawn.max_port = 1; 2647 spawn.phys_port = 1; 2648 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 2649 ret = mlx5_auxiliary_get_ifindex(dev->name); 2650 if (ret < 0) { 2651 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2652 return ret; 2653 } 2654 spawn.ifindex = ret; 2655 spawn.cdev = cdev; 2656 /* Spawn device. */ 2657 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2658 if (eth_dev == NULL) 2659 return -rte_errno; 2660 /* Post create. */ 2661 eth_dev->intr_handle = adev->intr_handle; 2662 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2663 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2664 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2665 eth_dev->data->numa_node = dev->numa_node; 2666 } 2667 rte_eth_dev_probing_finish(eth_dev); 2668 return 0; 2669 } 2670 2671 /** 2672 * Net class driver callback to probe a device. 2673 * 2674 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2675 * 2676 * @param[in] cdev 2677 * Pointer to the common mlx5 device. 2678 * 2679 * @return 2680 * 0 on success, a negative errno value otherwise and rte_errno is set. 2681 */ 2682 int 2683 mlx5_os_net_probe(struct mlx5_common_device *cdev) 2684 { 2685 int ret; 2686 2687 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2688 mlx5_pmd_socket_init(); 2689 ret = mlx5_init_once(); 2690 if (ret) { 2691 DRV_LOG(ERR, "Unable to init PMD global data: %s", 2692 strerror(rte_errno)); 2693 return -rte_errno; 2694 } 2695 if (mlx5_dev_is_pci(cdev->dev)) 2696 return mlx5_os_pci_probe(cdev); 2697 else 2698 return mlx5_os_auxiliary_probe(cdev); 2699 } 2700 2701 /** 2702 * Cleanup resources when the last device is closed. 2703 */ 2704 void 2705 mlx5_os_net_cleanup(void) 2706 { 2707 mlx5_pmd_socket_uninit(); 2708 } 2709 2710 /** 2711 * Install shared asynchronous device events handler. 2712 * This function is implemented to support event sharing 2713 * between multiple ports of single IB device. 2714 * 2715 * @param sh 2716 * Pointer to mlx5_dev_ctx_shared object. 2717 */ 2718 void 2719 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2720 { 2721 int ret; 2722 int flags; 2723 struct ibv_context *ctx = sh->cdev->ctx; 2724 2725 sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2726 if (sh->intr_handle == NULL) { 2727 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2728 rte_errno = ENOMEM; 2729 return; 2730 } 2731 rte_intr_fd_set(sh->intr_handle, -1); 2732 2733 flags = fcntl(ctx->async_fd, F_GETFL); 2734 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); 2735 if (ret) { 2736 DRV_LOG(INFO, "failed to change file descriptor async event" 2737 " queue"); 2738 } else { 2739 rte_intr_fd_set(sh->intr_handle, ctx->async_fd); 2740 rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); 2741 if (rte_intr_callback_register(sh->intr_handle, 2742 mlx5_dev_interrupt_handler, sh)) { 2743 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2744 rte_intr_fd_set(sh->intr_handle, -1); 2745 } 2746 } 2747 if (sh->devx) { 2748 #ifdef HAVE_IBV_DEVX_ASYNC 2749 sh->intr_handle_devx = 2750 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2751 if (!sh->intr_handle_devx) { 2752 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2753 rte_errno = ENOMEM; 2754 return; 2755 } 2756 rte_intr_fd_set(sh->intr_handle_devx, -1); 2757 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); 2758 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2759 if (!devx_comp) { 2760 DRV_LOG(INFO, "failed to allocate devx_comp."); 2761 return; 2762 } 2763 flags = fcntl(devx_comp->fd, F_GETFL); 2764 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2765 if (ret) { 2766 DRV_LOG(INFO, "failed to change file descriptor" 2767 " devx comp"); 2768 return; 2769 } 2770 rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); 2771 rte_intr_type_set(sh->intr_handle_devx, 2772 RTE_INTR_HANDLE_EXT); 2773 if (rte_intr_callback_register(sh->intr_handle_devx, 2774 mlx5_dev_interrupt_handler_devx, sh)) { 2775 DRV_LOG(INFO, "Fail to install the devx shared" 2776 " interrupt."); 2777 rte_intr_fd_set(sh->intr_handle_devx, -1); 2778 } 2779 #endif /* HAVE_IBV_DEVX_ASYNC */ 2780 } 2781 } 2782 2783 /** 2784 * Uninstall shared asynchronous device events handler. 2785 * This function is implemented to support event sharing 2786 * between multiple ports of single IB device. 2787 * 2788 * @param dev 2789 * Pointer to mlx5_dev_ctx_shared object. 2790 */ 2791 void 2792 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2793 { 2794 if (rte_intr_fd_get(sh->intr_handle) >= 0) 2795 mlx5_intr_callback_unregister(sh->intr_handle, 2796 mlx5_dev_interrupt_handler, sh); 2797 rte_intr_instance_free(sh->intr_handle); 2798 #ifdef HAVE_IBV_DEVX_ASYNC 2799 if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) 2800 rte_intr_callback_unregister(sh->intr_handle_devx, 2801 mlx5_dev_interrupt_handler_devx, sh); 2802 rte_intr_instance_free(sh->intr_handle_devx); 2803 if (sh->devx_comp) 2804 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2805 #endif 2806 } 2807 2808 /** 2809 * Read statistics by a named counter. 2810 * 2811 * @param[in] priv 2812 * Pointer to the private device data structure. 2813 * @param[in] ctr_name 2814 * Pointer to the name of the statistic counter to read 2815 * @param[out] stat 2816 * Pointer to read statistic value. 2817 * @return 2818 * 0 on success and stat is valud, 1 if failed to read the value 2819 * rte_errno is set. 2820 * 2821 */ 2822 int 2823 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2824 uint64_t *stat) 2825 { 2826 int fd; 2827 2828 if (priv->sh) { 2829 if (priv->q_counters != NULL && 2830 strcmp(ctr_name, "out_of_buffer") == 0) 2831 return mlx5_devx_cmd_queue_counter_query 2832 (priv->q_counters, 0, (uint32_t *)stat); 2833 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2834 priv->sh->ibdev_path, 2835 priv->dev_port, 2836 ctr_name); 2837 fd = open(path, O_RDONLY); 2838 /* 2839 * in switchdev the file location is not per port 2840 * but rather in <ibdev_path>/hw_counters/<file_name>. 2841 */ 2842 if (fd == -1) { 2843 MKSTR(path1, "%s/hw_counters/%s", 2844 priv->sh->ibdev_path, 2845 ctr_name); 2846 fd = open(path1, O_RDONLY); 2847 } 2848 if (fd != -1) { 2849 char buf[21] = {'\0'}; 2850 ssize_t n = read(fd, buf, sizeof(buf)); 2851 2852 close(fd); 2853 if (n != -1) { 2854 *stat = strtoull(buf, NULL, 10); 2855 return 0; 2856 } 2857 } 2858 } 2859 *stat = 0; 2860 return 1; 2861 } 2862 2863 /** 2864 * Remove a MAC address from device 2865 * 2866 * @param dev 2867 * Pointer to Ethernet device structure. 2868 * @param index 2869 * MAC address index. 2870 */ 2871 void 2872 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2873 { 2874 struct mlx5_priv *priv = dev->data->dev_private; 2875 const int vf = priv->config.vf; 2876 2877 if (vf) 2878 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2879 mlx5_ifindex(dev), priv->mac_own, 2880 &dev->data->mac_addrs[index], index); 2881 } 2882 2883 /** 2884 * Adds a MAC address to the device 2885 * 2886 * @param dev 2887 * Pointer to Ethernet device structure. 2888 * @param mac_addr 2889 * MAC address to register. 2890 * @param index 2891 * MAC address index. 2892 * 2893 * @return 2894 * 0 on success, a negative errno value otherwise 2895 */ 2896 int 2897 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2898 uint32_t index) 2899 { 2900 struct mlx5_priv *priv = dev->data->dev_private; 2901 const int vf = priv->config.vf; 2902 int ret = 0; 2903 2904 if (vf) 2905 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2906 mlx5_ifindex(dev), priv->mac_own, 2907 mac, index); 2908 return ret; 2909 } 2910 2911 /** 2912 * Modify a VF MAC address 2913 * 2914 * @param priv 2915 * Pointer to device private data. 2916 * @param mac_addr 2917 * MAC address to modify into. 2918 * @param iface_idx 2919 * Net device interface index 2920 * @param vf_index 2921 * VF index 2922 * 2923 * @return 2924 * 0 on success, a negative errno value otherwise 2925 */ 2926 int 2927 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2928 unsigned int iface_idx, 2929 struct rte_ether_addr *mac_addr, 2930 int vf_index) 2931 { 2932 return mlx5_nl_vf_mac_addr_modify 2933 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2934 } 2935 2936 /** 2937 * Set device promiscuous mode 2938 * 2939 * @param dev 2940 * Pointer to Ethernet device structure. 2941 * @param enable 2942 * 0 - promiscuous is disabled, otherwise - enabled 2943 * 2944 * @return 2945 * 0 on success, a negative error value otherwise 2946 */ 2947 int 2948 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2949 { 2950 struct mlx5_priv *priv = dev->data->dev_private; 2951 2952 return mlx5_nl_promisc(priv->nl_socket_route, 2953 mlx5_ifindex(dev), !!enable); 2954 } 2955 2956 /** 2957 * Set device promiscuous mode 2958 * 2959 * @param dev 2960 * Pointer to Ethernet device structure. 2961 * @param enable 2962 * 0 - all multicase is disabled, otherwise - enabled 2963 * 2964 * @return 2965 * 0 on success, a negative error value otherwise 2966 */ 2967 int 2968 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2969 { 2970 struct mlx5_priv *priv = dev->data->dev_private; 2971 2972 return mlx5_nl_allmulti(priv->nl_socket_route, 2973 mlx5_ifindex(dev), !!enable); 2974 } 2975 2976 /** 2977 * Flush device MAC addresses 2978 * 2979 * @param dev 2980 * Pointer to Ethernet device structure. 2981 * 2982 */ 2983 void 2984 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2985 { 2986 struct mlx5_priv *priv = dev->data->dev_private; 2987 2988 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2989 dev->data->mac_addrs, 2990 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2991 } 2992