1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_qp = attr_ex.orig_attr.max_qp; 120 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 121 device_attr->max_rwq_indirection_table_size = 122 attr_ex.rss_caps.max_rwq_indirection_table_size; 123 device_attr->max_tso = attr_ex.tso_caps.max_tso; 124 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 125 126 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 127 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 128 if (err) 129 return err; 130 131 device_attr->flags = dv_attr.flags; 132 device_attr->comp_mask = dv_attr.comp_mask; 133 #ifdef HAVE_IBV_MLX5_MOD_SWP 134 device_attr->sw_parsing_offloads = 135 dv_attr.sw_parsing_caps.sw_parsing_offloads; 136 #endif 137 device_attr->min_single_stride_log_num_of_bytes = 138 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 139 device_attr->max_single_stride_log_num_of_bytes = 140 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 141 device_attr->min_single_wqe_log_num_of_strides = 142 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 143 device_attr->max_single_wqe_log_num_of_strides = 144 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 145 device_attr->stride_supported_qpts = 146 dv_attr.striding_rq_caps.supported_qpts; 147 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 148 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 149 #endif 150 151 return err; 152 } 153 154 /** 155 * Verbs callback to allocate a memory. This function should allocate the space 156 * according to the size provided residing inside a huge page. 157 * Please note that all allocation must respect the alignment from libmlx5 158 * (i.e. currently rte_mem_page_size()). 159 * 160 * @param[in] size 161 * The size in bytes of the memory to allocate. 162 * @param[in] data 163 * A pointer to the callback data. 164 * 165 * @return 166 * Allocated buffer, NULL otherwise and rte_errno is set. 167 */ 168 static void * 169 mlx5_alloc_verbs_buf(size_t size, void *data) 170 { 171 struct mlx5_priv *priv = data; 172 void *ret; 173 unsigned int socket = SOCKET_ID_ANY; 174 size_t alignment = rte_mem_page_size(); 175 if (alignment == (size_t)-1) { 176 DRV_LOG(ERR, "Failed to get mem page size"); 177 rte_errno = ENOMEM; 178 return NULL; 179 } 180 181 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 182 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 183 184 socket = ctrl->socket; 185 } else if (priv->verbs_alloc_ctx.type == 186 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 187 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 188 189 socket = ctrl->socket; 190 } 191 MLX5_ASSERT(data != NULL); 192 ret = mlx5_malloc(0, size, alignment, socket); 193 if (!ret && size) 194 rte_errno = ENOMEM; 195 return ret; 196 } 197 198 /** 199 * Verbs callback to free a memory. 200 * 201 * @param[in] ptr 202 * A pointer to the memory to free. 203 * @param[in] data 204 * A pointer to the callback data. 205 */ 206 static void 207 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 208 { 209 MLX5_ASSERT(data != NULL); 210 mlx5_free(ptr); 211 } 212 213 /** 214 * Initialize DR related data within private structure. 215 * Routine checks the reference counter and does actual 216 * resources creation/initialization only if counter is zero. 217 * 218 * @param[in] priv 219 * Pointer to the private device data structure. 220 * 221 * @return 222 * Zero on success, positive error code otherwise. 223 */ 224 static int 225 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 226 { 227 struct mlx5_dev_ctx_shared *sh = priv->sh; 228 char s[MLX5_HLIST_NAMESIZE] __rte_unused; 229 int err; 230 231 MLX5_ASSERT(sh && sh->refcnt); 232 if (sh->refcnt > 1) 233 return 0; 234 err = mlx5_alloc_table_hash_list(priv); 235 if (err) 236 goto error; 237 /* The resources below are only valid with DV support. */ 238 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 239 /* Init port id action cache list. */ 240 snprintf(s, sizeof(s), "%s_port_id_action_cache", sh->ibdev_name); 241 mlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh, 242 flow_dv_port_id_create_cb, 243 flow_dv_port_id_match_cb, 244 flow_dv_port_id_remove_cb); 245 /* Init push vlan action cache list. */ 246 snprintf(s, sizeof(s), "%s_push_vlan_action_cache", sh->ibdev_name); 247 mlx5_cache_list_init(&sh->push_vlan_action_list, s, 0, sh, 248 flow_dv_push_vlan_create_cb, 249 flow_dv_push_vlan_match_cb, 250 flow_dv_push_vlan_remove_cb); 251 /* Init sample action cache list. */ 252 snprintf(s, sizeof(s), "%s_sample_action_cache", sh->ibdev_name); 253 mlx5_cache_list_init(&sh->sample_action_list, s, 0, sh, 254 flow_dv_sample_create_cb, 255 flow_dv_sample_match_cb, 256 flow_dv_sample_remove_cb); 257 /* Init dest array action cache list. */ 258 snprintf(s, sizeof(s), "%s_dest_array_cache", sh->ibdev_name); 259 mlx5_cache_list_init(&sh->dest_array_list, s, 0, sh, 260 flow_dv_dest_array_create_cb, 261 flow_dv_dest_array_match_cb, 262 flow_dv_dest_array_remove_cb); 263 /* Create tags hash list table. */ 264 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 265 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0, 266 MLX5_HLIST_WRITE_MOST, 267 flow_dv_tag_create_cb, NULL, 268 flow_dv_tag_remove_cb); 269 if (!sh->tag_table) { 270 DRV_LOG(ERR, "tags with hash creation failed."); 271 err = ENOMEM; 272 goto error; 273 } 274 sh->tag_table->ctx = sh; 275 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 276 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ, 277 0, MLX5_HLIST_WRITE_MOST | 278 MLX5_HLIST_DIRECT_KEY, 279 flow_dv_modify_create_cb, 280 flow_dv_modify_match_cb, 281 flow_dv_modify_remove_cb); 282 if (!sh->modify_cmds) { 283 DRV_LOG(ERR, "hdr modify hash creation failed"); 284 err = ENOMEM; 285 goto error; 286 } 287 sh->modify_cmds->ctx = sh; 288 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 289 sh->encaps_decaps = mlx5_hlist_create(s, 290 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ, 291 0, MLX5_HLIST_DIRECT_KEY | 292 MLX5_HLIST_WRITE_MOST, 293 flow_dv_encap_decap_create_cb, 294 flow_dv_encap_decap_match_cb, 295 flow_dv_encap_decap_remove_cb); 296 if (!sh->encaps_decaps) { 297 DRV_LOG(ERR, "encap decap hash creation failed"); 298 err = ENOMEM; 299 goto error; 300 } 301 sh->encaps_decaps->ctx = sh; 302 #endif 303 #ifdef HAVE_MLX5DV_DR 304 void *domain; 305 306 /* Reference counter is zero, we should initialize structures. */ 307 domain = mlx5_glue->dr_create_domain(sh->ctx, 308 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 309 if (!domain) { 310 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 311 err = errno; 312 goto error; 313 } 314 sh->rx_domain = domain; 315 domain = mlx5_glue->dr_create_domain(sh->ctx, 316 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 317 if (!domain) { 318 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 319 err = errno; 320 goto error; 321 } 322 sh->tx_domain = domain; 323 #ifdef HAVE_MLX5DV_DR_ESWITCH 324 if (priv->config.dv_esw_en) { 325 domain = mlx5_glue->dr_create_domain 326 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 327 if (!domain) { 328 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 329 err = errno; 330 goto error; 331 } 332 sh->fdb_domain = domain; 333 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 334 } 335 #endif 336 if (!sh->tunnel_hub) 337 err = mlx5_alloc_tunnel_hub(sh); 338 if (err) { 339 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 340 goto error; 341 } 342 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 343 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 344 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 345 if (sh->fdb_domain) 346 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 347 } 348 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 349 #endif /* HAVE_MLX5DV_DR */ 350 sh->default_miss_action = 351 mlx5_glue->dr_create_flow_action_default_miss(); 352 if (!sh->default_miss_action) 353 DRV_LOG(WARNING, "Default miss action is not supported."); 354 return 0; 355 error: 356 /* Rollback the created objects. */ 357 if (sh->rx_domain) { 358 mlx5_glue->dr_destroy_domain(sh->rx_domain); 359 sh->rx_domain = NULL; 360 } 361 if (sh->tx_domain) { 362 mlx5_glue->dr_destroy_domain(sh->tx_domain); 363 sh->tx_domain = NULL; 364 } 365 if (sh->fdb_domain) { 366 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 367 sh->fdb_domain = NULL; 368 } 369 if (sh->esw_drop_action) { 370 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 371 sh->esw_drop_action = NULL; 372 } 373 if (sh->pop_vlan_action) { 374 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 375 sh->pop_vlan_action = NULL; 376 } 377 if (sh->encaps_decaps) { 378 mlx5_hlist_destroy(sh->encaps_decaps); 379 sh->encaps_decaps = NULL; 380 } 381 if (sh->modify_cmds) { 382 mlx5_hlist_destroy(sh->modify_cmds); 383 sh->modify_cmds = NULL; 384 } 385 if (sh->tag_table) { 386 /* tags should be destroyed with flow before. */ 387 mlx5_hlist_destroy(sh->tag_table); 388 sh->tag_table = NULL; 389 } 390 if (sh->tunnel_hub) { 391 mlx5_release_tunnel_hub(sh, priv->dev_port); 392 sh->tunnel_hub = NULL; 393 } 394 mlx5_free_table_hash_list(priv); 395 return err; 396 } 397 398 /** 399 * Destroy DR related data within private structure. 400 * 401 * @param[in] priv 402 * Pointer to the private device data structure. 403 */ 404 void 405 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 406 { 407 struct mlx5_dev_ctx_shared *sh = priv->sh; 408 409 MLX5_ASSERT(sh && sh->refcnt); 410 if (sh->refcnt > 1) 411 return; 412 #ifdef HAVE_MLX5DV_DR 413 if (sh->rx_domain) { 414 mlx5_glue->dr_destroy_domain(sh->rx_domain); 415 sh->rx_domain = NULL; 416 } 417 if (sh->tx_domain) { 418 mlx5_glue->dr_destroy_domain(sh->tx_domain); 419 sh->tx_domain = NULL; 420 } 421 #ifdef HAVE_MLX5DV_DR_ESWITCH 422 if (sh->fdb_domain) { 423 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 424 sh->fdb_domain = NULL; 425 } 426 if (sh->esw_drop_action) { 427 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 428 sh->esw_drop_action = NULL; 429 } 430 #endif 431 if (sh->pop_vlan_action) { 432 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 433 sh->pop_vlan_action = NULL; 434 } 435 #endif /* HAVE_MLX5DV_DR */ 436 if (sh->default_miss_action) 437 mlx5_glue->destroy_flow_action 438 (sh->default_miss_action); 439 if (sh->encaps_decaps) { 440 mlx5_hlist_destroy(sh->encaps_decaps); 441 sh->encaps_decaps = NULL; 442 } 443 if (sh->modify_cmds) { 444 mlx5_hlist_destroy(sh->modify_cmds); 445 sh->modify_cmds = NULL; 446 } 447 if (sh->tag_table) { 448 /* tags should be destroyed with flow before. */ 449 mlx5_hlist_destroy(sh->tag_table); 450 sh->tag_table = NULL; 451 } 452 if (sh->tunnel_hub) { 453 mlx5_release_tunnel_hub(sh, priv->dev_port); 454 sh->tunnel_hub = NULL; 455 } 456 mlx5_cache_list_destroy(&sh->port_id_action_list); 457 mlx5_cache_list_destroy(&sh->push_vlan_action_list); 458 mlx5_free_table_hash_list(priv); 459 } 460 461 /** 462 * Initialize shared data between primary and secondary process. 463 * 464 * A memzone is reserved by primary process and secondary processes attach to 465 * the memzone. 466 * 467 * @return 468 * 0 on success, a negative errno value otherwise and rte_errno is set. 469 */ 470 static int 471 mlx5_init_shared_data(void) 472 { 473 const struct rte_memzone *mz; 474 int ret = 0; 475 476 rte_spinlock_lock(&mlx5_shared_data_lock); 477 if (mlx5_shared_data == NULL) { 478 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 479 /* Allocate shared memory. */ 480 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 481 sizeof(*mlx5_shared_data), 482 SOCKET_ID_ANY, 0); 483 if (mz == NULL) { 484 DRV_LOG(ERR, 485 "Cannot allocate mlx5 shared data"); 486 ret = -rte_errno; 487 goto error; 488 } 489 mlx5_shared_data = mz->addr; 490 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 491 rte_spinlock_init(&mlx5_shared_data->lock); 492 } else { 493 /* Lookup allocated shared memory. */ 494 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 495 if (mz == NULL) { 496 DRV_LOG(ERR, 497 "Cannot attach mlx5 shared data"); 498 ret = -rte_errno; 499 goto error; 500 } 501 mlx5_shared_data = mz->addr; 502 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 503 } 504 } 505 error: 506 rte_spinlock_unlock(&mlx5_shared_data_lock); 507 return ret; 508 } 509 510 /** 511 * PMD global initialization. 512 * 513 * Independent from individual device, this function initializes global 514 * per-PMD data structures distinguishing primary and secondary processes. 515 * Hence, each initialization is called once per a process. 516 * 517 * @return 518 * 0 on success, a negative errno value otherwise and rte_errno is set. 519 */ 520 static int 521 mlx5_init_once(void) 522 { 523 struct mlx5_shared_data *sd; 524 struct mlx5_local_data *ld = &mlx5_local_data; 525 int ret = 0; 526 527 if (mlx5_init_shared_data()) 528 return -rte_errno; 529 sd = mlx5_shared_data; 530 MLX5_ASSERT(sd); 531 rte_spinlock_lock(&sd->lock); 532 switch (rte_eal_process_type()) { 533 case RTE_PROC_PRIMARY: 534 if (sd->init_done) 535 break; 536 LIST_INIT(&sd->mem_event_cb_list); 537 rte_rwlock_init(&sd->mem_event_rwlock); 538 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 539 mlx5_mr_mem_event_cb, NULL); 540 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 541 mlx5_mp_os_primary_handle); 542 if (ret) 543 goto out; 544 sd->init_done = true; 545 break; 546 case RTE_PROC_SECONDARY: 547 if (ld->init_done) 548 break; 549 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 550 mlx5_mp_os_secondary_handle); 551 if (ret) 552 goto out; 553 ++sd->secondary_cnt; 554 ld->init_done = true; 555 break; 556 default: 557 break; 558 } 559 out: 560 rte_spinlock_unlock(&sd->lock); 561 return ret; 562 } 563 564 /** 565 * Create the Tx queue DevX/Verbs object. 566 * 567 * @param dev 568 * Pointer to Ethernet device. 569 * @param idx 570 * Queue index in DPDK Tx queue array. 571 * 572 * @return 573 * 0 on success, a negative errno value otherwise and rte_errno is set. 574 */ 575 static int 576 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 577 { 578 struct mlx5_priv *priv = dev->data->dev_private; 579 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 580 struct mlx5_txq_ctrl *txq_ctrl = 581 container_of(txq_data, struct mlx5_txq_ctrl, txq); 582 583 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 584 return mlx5_txq_devx_obj_new(dev, idx); 585 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 586 if (!priv->config.dv_esw_en) 587 return mlx5_txq_devx_obj_new(dev, idx); 588 #endif 589 return mlx5_txq_ibv_obj_new(dev, idx); 590 } 591 592 /** 593 * Release an Tx DevX/verbs queue object. 594 * 595 * @param txq_obj 596 * DevX/Verbs Tx queue object. 597 */ 598 static void 599 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 600 { 601 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 602 mlx5_txq_devx_obj_release(txq_obj); 603 return; 604 } 605 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 606 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 607 mlx5_txq_devx_obj_release(txq_obj); 608 return; 609 } 610 #endif 611 mlx5_txq_ibv_obj_release(txq_obj); 612 } 613 614 /** 615 * DV flow counter mode detect and config. 616 * 617 * @param dev 618 * Pointer to rte_eth_dev structure. 619 * 620 */ 621 static void 622 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 623 { 624 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 625 struct mlx5_priv *priv = dev->data->dev_private; 626 struct mlx5_dev_ctx_shared *sh = priv->sh; 627 bool fallback; 628 629 #ifndef HAVE_IBV_DEVX_ASYNC 630 fallback = true; 631 #else 632 fallback = false; 633 if (!priv->config.devx || !priv->config.dv_flow_en || 634 !priv->config.hca_attr.flow_counters_dump || 635 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 636 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 637 fallback = true; 638 #endif 639 if (fallback) 640 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 641 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 642 priv->config.hca_attr.flow_counters_dump, 643 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 644 /* Initialize fallback mode only on the port initializes sh. */ 645 if (sh->refcnt == 1) 646 sh->cmng.counter_fallback = fallback; 647 else if (fallback != sh->cmng.counter_fallback) 648 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 649 "with others:%d.", PORT_ID(priv), fallback); 650 #endif 651 } 652 653 /** 654 * Spawn an Ethernet device from Verbs information. 655 * 656 * @param dpdk_dev 657 * Backing DPDK device. 658 * @param spawn 659 * Verbs device parameters (name, port, switch_info) to spawn. 660 * @param config 661 * Device configuration parameters. 662 * 663 * @return 664 * A valid Ethernet device object on success, NULL otherwise and rte_errno 665 * is set. The following errors are defined: 666 * 667 * EBUSY: device is not supposed to be spawned. 668 * EEXIST: device is already spawned 669 */ 670 static struct rte_eth_dev * 671 mlx5_dev_spawn(struct rte_device *dpdk_dev, 672 struct mlx5_dev_spawn_data *spawn, 673 struct mlx5_dev_config *config) 674 { 675 const struct mlx5_switch_info *switch_info = &spawn->info; 676 struct mlx5_dev_ctx_shared *sh = NULL; 677 struct ibv_port_attr port_attr; 678 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 679 struct rte_eth_dev *eth_dev = NULL; 680 struct mlx5_priv *priv = NULL; 681 int err = 0; 682 unsigned int hw_padding = 0; 683 unsigned int mps; 684 unsigned int cqe_comp; 685 unsigned int cqe_pad = 0; 686 unsigned int tunnel_en = 0; 687 unsigned int mpls_en = 0; 688 unsigned int swp = 0; 689 unsigned int mprq = 0; 690 unsigned int mprq_min_stride_size_n = 0; 691 unsigned int mprq_max_stride_size_n = 0; 692 unsigned int mprq_min_stride_num_n = 0; 693 unsigned int mprq_max_stride_num_n = 0; 694 struct rte_ether_addr mac; 695 char name[RTE_ETH_NAME_MAX_LEN]; 696 int own_domain_id = 0; 697 uint16_t port_id; 698 unsigned int i; 699 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 700 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 701 #endif 702 703 /* Determine if this port representor is supposed to be spawned. */ 704 if (switch_info->representor && dpdk_dev->devargs) { 705 struct rte_eth_devargs eth_da; 706 707 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 708 if (err) { 709 rte_errno = -err; 710 DRV_LOG(ERR, "failed to process device arguments: %s", 711 strerror(rte_errno)); 712 return NULL; 713 } 714 for (i = 0; i < eth_da.nb_representor_ports; ++i) 715 if (eth_da.representor_ports[i] == 716 (uint16_t)switch_info->port_name) 717 break; 718 if (i == eth_da.nb_representor_ports) { 719 rte_errno = EBUSY; 720 return NULL; 721 } 722 } 723 /* Build device name. */ 724 if (spawn->pf_bond < 0) { 725 /* Single device. */ 726 if (!switch_info->representor) 727 strlcpy(name, dpdk_dev->name, sizeof(name)); 728 else 729 snprintf(name, sizeof(name), "%s_representor_%u", 730 dpdk_dev->name, switch_info->port_name); 731 } else { 732 /* Bonding device. */ 733 if (!switch_info->representor) 734 snprintf(name, sizeof(name), "%s_%s", 735 dpdk_dev->name, 736 mlx5_os_get_dev_device_name(spawn->phys_dev)); 737 else 738 snprintf(name, sizeof(name), "%s_%s_representor_%u", 739 dpdk_dev->name, 740 mlx5_os_get_dev_device_name(spawn->phys_dev), 741 switch_info->port_name); 742 } 743 /* check if the device is already spawned */ 744 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 745 rte_errno = EEXIST; 746 return NULL; 747 } 748 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 749 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 750 struct mlx5_mp_id mp_id; 751 752 eth_dev = rte_eth_dev_attach_secondary(name); 753 if (eth_dev == NULL) { 754 DRV_LOG(ERR, "can not attach rte ethdev"); 755 rte_errno = ENOMEM; 756 return NULL; 757 } 758 priv = eth_dev->data->dev_private; 759 if (priv->sh->bond_dev != UINT16_MAX) 760 /* For bonding port, use primary PCI device. */ 761 eth_dev->device = 762 rte_eth_devices[priv->sh->bond_dev].device; 763 else 764 eth_dev->device = dpdk_dev; 765 eth_dev->dev_ops = &mlx5_os_dev_sec_ops; 766 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 767 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 768 err = mlx5_proc_priv_init(eth_dev); 769 if (err) 770 return NULL; 771 mp_id.port_id = eth_dev->data->port_id; 772 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 773 /* Receive command fd from primary process */ 774 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 775 if (err < 0) 776 goto err_secondary; 777 /* Remap UAR for Tx queues. */ 778 err = mlx5_tx_uar_init_secondary(eth_dev, err); 779 if (err) 780 goto err_secondary; 781 /* 782 * Ethdev pointer is still required as input since 783 * the primary device is not accessible from the 784 * secondary process. 785 */ 786 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 787 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 788 return eth_dev; 789 err_secondary: 790 mlx5_dev_close(eth_dev); 791 return NULL; 792 } 793 /* 794 * Some parameters ("tx_db_nc" in particularly) are needed in 795 * advance to create dv/verbs device context. We proceed the 796 * devargs here to get ones, and later proceed devargs again 797 * to override some hardware settings. 798 */ 799 err = mlx5_args(config, dpdk_dev->devargs); 800 if (err) { 801 err = rte_errno; 802 DRV_LOG(ERR, "failed to process device arguments: %s", 803 strerror(rte_errno)); 804 goto error; 805 } 806 if (config->dv_miss_info) { 807 if (switch_info->master || switch_info->representor) 808 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 809 } 810 mlx5_malloc_mem_select(config->sys_mem_en); 811 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 812 if (!sh) 813 return NULL; 814 config->devx = sh->devx; 815 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 816 config->dest_tir = 1; 817 #endif 818 #ifdef HAVE_IBV_MLX5_MOD_SWP 819 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 820 #endif 821 /* 822 * Multi-packet send is supported by ConnectX-4 Lx PF as well 823 * as all ConnectX-5 devices. 824 */ 825 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 826 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 827 #endif 828 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 829 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 830 #endif 831 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 832 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 833 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 834 DRV_LOG(DEBUG, "enhanced MPW is supported"); 835 mps = MLX5_MPW_ENHANCED; 836 } else { 837 DRV_LOG(DEBUG, "MPW is supported"); 838 mps = MLX5_MPW; 839 } 840 } else { 841 DRV_LOG(DEBUG, "MPW isn't supported"); 842 mps = MLX5_MPW_DISABLED; 843 } 844 #ifdef HAVE_IBV_MLX5_MOD_SWP 845 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 846 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 847 DRV_LOG(DEBUG, "SWP support: %u", swp); 848 #endif 849 config->swp = !!swp; 850 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 851 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 852 struct mlx5dv_striding_rq_caps mprq_caps = 853 dv_attr.striding_rq_caps; 854 855 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 856 mprq_caps.min_single_stride_log_num_of_bytes); 857 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 858 mprq_caps.max_single_stride_log_num_of_bytes); 859 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 860 mprq_caps.min_single_wqe_log_num_of_strides); 861 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 862 mprq_caps.max_single_wqe_log_num_of_strides); 863 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 864 mprq_caps.supported_qpts); 865 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 866 mprq = 1; 867 mprq_min_stride_size_n = 868 mprq_caps.min_single_stride_log_num_of_bytes; 869 mprq_max_stride_size_n = 870 mprq_caps.max_single_stride_log_num_of_bytes; 871 mprq_min_stride_num_n = 872 mprq_caps.min_single_wqe_log_num_of_strides; 873 mprq_max_stride_num_n = 874 mprq_caps.max_single_wqe_log_num_of_strides; 875 } 876 #endif 877 if (RTE_CACHE_LINE_SIZE == 128 && 878 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 879 cqe_comp = 0; 880 else 881 cqe_comp = 1; 882 config->cqe_comp = cqe_comp; 883 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 884 /* Whether device supports 128B Rx CQE padding. */ 885 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 886 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 887 #endif 888 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 889 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 890 tunnel_en = ((dv_attr.tunnel_offloads_caps & 891 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 892 (dv_attr.tunnel_offloads_caps & 893 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 894 (dv_attr.tunnel_offloads_caps & 895 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 896 } 897 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 898 tunnel_en ? "" : "not "); 899 #else 900 DRV_LOG(WARNING, 901 "tunnel offloading disabled due to old OFED/rdma-core version"); 902 #endif 903 config->tunnel_en = tunnel_en; 904 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 905 mpls_en = ((dv_attr.tunnel_offloads_caps & 906 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 907 (dv_attr.tunnel_offloads_caps & 908 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 909 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 910 mpls_en ? "" : "not "); 911 #else 912 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 913 " old OFED/rdma-core version or firmware configuration"); 914 #endif 915 config->mpls_en = mpls_en; 916 /* Check port status. */ 917 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 918 if (err) { 919 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 920 goto error; 921 } 922 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 923 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 924 err = EINVAL; 925 goto error; 926 } 927 if (port_attr.state != IBV_PORT_ACTIVE) 928 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 929 mlx5_glue->port_state_str(port_attr.state), 930 port_attr.state); 931 /* Allocate private eth device data. */ 932 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 933 sizeof(*priv), 934 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 935 if (priv == NULL) { 936 DRV_LOG(ERR, "priv allocation failure"); 937 err = ENOMEM; 938 goto error; 939 } 940 priv->sh = sh; 941 priv->dev_port = spawn->phys_port; 942 priv->pci_dev = spawn->pci_dev; 943 priv->mtu = RTE_ETHER_MTU; 944 priv->mp_id.port_id = port_id; 945 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 946 /* Some internal functions rely on Netlink sockets, open them now. */ 947 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 948 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 949 priv->representor = !!switch_info->representor; 950 priv->master = !!switch_info->master; 951 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 952 priv->vport_meta_tag = 0; 953 priv->vport_meta_mask = 0; 954 priv->pf_bond = spawn->pf_bond; 955 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 956 /* 957 * The DevX port query API is implemented. E-Switch may use 958 * either vport or reg_c[0] metadata register to match on 959 * vport index. The engaged part of metadata register is 960 * defined by mask. 961 */ 962 if (switch_info->representor || switch_info->master) { 963 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 964 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 965 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 966 &devx_port); 967 if (err) { 968 DRV_LOG(WARNING, 969 "can't query devx port %d on device %s", 970 spawn->phys_port, 971 mlx5_os_get_dev_device_name(spawn->phys_dev)); 972 devx_port.comp_mask = 0; 973 } 974 } 975 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 976 priv->vport_meta_tag = devx_port.reg_c_0.value; 977 priv->vport_meta_mask = devx_port.reg_c_0.mask; 978 if (!priv->vport_meta_mask) { 979 DRV_LOG(ERR, "vport zero mask for port %d" 980 " on bonding device %s", 981 spawn->phys_port, 982 mlx5_os_get_dev_device_name 983 (spawn->phys_dev)); 984 err = ENOTSUP; 985 goto error; 986 } 987 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 988 DRV_LOG(ERR, "invalid vport tag for port %d" 989 " on bonding device %s", 990 spawn->phys_port, 991 mlx5_os_get_dev_device_name 992 (spawn->phys_dev)); 993 err = ENOTSUP; 994 goto error; 995 } 996 } 997 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 998 priv->vport_id = devx_port.vport_num; 999 } else if (spawn->pf_bond >= 0) { 1000 DRV_LOG(ERR, "can't deduce vport index for port %d" 1001 " on bonding device %s", 1002 spawn->phys_port, 1003 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1004 err = ENOTSUP; 1005 goto error; 1006 } else { 1007 /* Suppose vport index in compatible way. */ 1008 priv->vport_id = switch_info->representor ? 1009 switch_info->port_name + 1 : -1; 1010 } 1011 #else 1012 /* 1013 * Kernel/rdma_core support single E-Switch per PF configurations 1014 * only and vport_id field contains the vport index for 1015 * associated VF, which is deduced from representor port name. 1016 * For example, let's have the IB device port 10, it has 1017 * attached network device eth0, which has port name attribute 1018 * pf0vf2, we can deduce the VF number as 2, and set vport index 1019 * as 3 (2+1). This assigning schema should be changed if the 1020 * multiple E-Switch instances per PF configurations or/and PCI 1021 * subfunctions are added. 1022 */ 1023 priv->vport_id = switch_info->representor ? 1024 switch_info->port_name + 1 : -1; 1025 #endif 1026 /* representor_id field keeps the unmodified VF index. */ 1027 priv->representor_id = switch_info->representor ? 1028 switch_info->port_name : -1; 1029 /* 1030 * Look for sibling devices in order to reuse their switch domain 1031 * if any, otherwise allocate one. 1032 */ 1033 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1034 const struct mlx5_priv *opriv = 1035 rte_eth_devices[port_id].data->dev_private; 1036 1037 if (!opriv || 1038 opriv->sh != priv->sh || 1039 opriv->domain_id == 1040 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1041 continue; 1042 priv->domain_id = opriv->domain_id; 1043 break; 1044 } 1045 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1046 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1047 if (err) { 1048 err = rte_errno; 1049 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1050 strerror(rte_errno)); 1051 goto error; 1052 } 1053 own_domain_id = 1; 1054 } 1055 /* Override some values set by hardware configuration. */ 1056 mlx5_args(config, dpdk_dev->devargs); 1057 err = mlx5_dev_check_sibling_config(priv, config); 1058 if (err) 1059 goto error; 1060 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1061 IBV_DEVICE_RAW_IP_CSUM); 1062 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1063 (config->hw_csum ? "" : "not ")); 1064 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1065 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1066 DRV_LOG(DEBUG, "counters are not supported"); 1067 #endif 1068 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1069 if (config->dv_flow_en) { 1070 DRV_LOG(WARNING, "DV flow is not supported"); 1071 config->dv_flow_en = 0; 1072 } 1073 #endif 1074 config->ind_table_max_size = 1075 sh->device_attr.max_rwq_indirection_table_size; 1076 /* 1077 * Remove this check once DPDK supports larger/variable 1078 * indirection tables. 1079 */ 1080 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1081 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1082 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1083 config->ind_table_max_size); 1084 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1085 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1086 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1087 (config->hw_vlan_strip ? "" : "not ")); 1088 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1089 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1090 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1091 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1092 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1093 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1094 IBV_DEVICE_PCI_WRITE_END_PADDING); 1095 #endif 1096 if (config->hw_padding && !hw_padding) { 1097 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1098 config->hw_padding = 0; 1099 } else if (config->hw_padding) { 1100 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1101 } 1102 config->tso = (sh->device_attr.max_tso > 0 && 1103 (sh->device_attr.tso_supported_qpts & 1104 (1 << IBV_QPT_RAW_PACKET))); 1105 if (config->tso) 1106 config->tso_max_payload_sz = sh->device_attr.max_tso; 1107 /* 1108 * MPW is disabled by default, while the Enhanced MPW is enabled 1109 * by default. 1110 */ 1111 if (config->mps == MLX5_ARG_UNSET) 1112 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1113 MLX5_MPW_DISABLED; 1114 else 1115 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1116 DRV_LOG(INFO, "%sMPS is %s", 1117 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1118 config->mps == MLX5_MPW ? "legacy " : "", 1119 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1120 if (config->cqe_comp && !cqe_comp) { 1121 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1122 config->cqe_comp = 0; 1123 } 1124 if (config->cqe_pad && !cqe_pad) { 1125 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1126 config->cqe_pad = 0; 1127 } else if (config->cqe_pad) { 1128 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1129 } 1130 if (config->devx) { 1131 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1132 if (err) { 1133 err = -err; 1134 goto error; 1135 } 1136 /* Check relax ordering support. */ 1137 if (!haswell_broadwell_cpu) { 1138 sh->cmng.relaxed_ordering_write = 1139 config->hca_attr.relaxed_ordering_write; 1140 sh->cmng.relaxed_ordering_read = 1141 config->hca_attr.relaxed_ordering_read; 1142 } else { 1143 sh->cmng.relaxed_ordering_read = 0; 1144 sh->cmng.relaxed_ordering_write = 0; 1145 } 1146 /* Check for LRO support. */ 1147 if (config->dest_tir && config->hca_attr.lro_cap && 1148 config->dv_flow_en) { 1149 /* TBD check tunnel lro caps. */ 1150 config->lro.supported = config->hca_attr.lro_cap; 1151 DRV_LOG(DEBUG, "Device supports LRO"); 1152 /* 1153 * If LRO timeout is not configured by application, 1154 * use the minimal supported value. 1155 */ 1156 if (!config->lro.timeout) 1157 config->lro.timeout = 1158 config->hca_attr.lro_timer_supported_periods[0]; 1159 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1160 config->lro.timeout); 1161 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1162 "required for coalescing is %d bytes", 1163 config->hca_attr.lro_min_mss_size); 1164 } 1165 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1166 if (config->hca_attr.qos.sup && 1167 config->hca_attr.qos.srtcm_sup && 1168 config->dv_flow_en) { 1169 uint8_t reg_c_mask = 1170 config->hca_attr.qos.flow_meter_reg_c_ids; 1171 /* 1172 * Meter needs two REG_C's for color match and pre-sfx 1173 * flow match. Here get the REG_C for color match. 1174 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1175 */ 1176 reg_c_mask &= 0xfc; 1177 if (__builtin_popcount(reg_c_mask) < 1) { 1178 priv->mtr_en = 0; 1179 DRV_LOG(WARNING, "No available register for" 1180 " meter."); 1181 } else { 1182 /* 1183 * The meter color register is used by the 1184 * flow-hit feature as well. 1185 * The flow-hit feature must use REG_C_3 1186 * Prefer REG_C_3 if it is available. 1187 */ 1188 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1189 priv->mtr_color_reg = REG_C_3; 1190 else 1191 priv->mtr_color_reg = ffs(reg_c_mask) 1192 - 1 + REG_C_0; 1193 priv->mtr_en = 1; 1194 priv->mtr_reg_share = 1195 config->hca_attr.qos.flow_meter_reg_share; 1196 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1197 priv->mtr_color_reg); 1198 } 1199 } 1200 #endif 1201 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1202 if (config->hca_attr.flow_hit_aso && 1203 priv->mtr_color_reg == REG_C_3) { 1204 sh->flow_hit_aso_en = 1; 1205 err = mlx5_flow_aso_age_mng_init(sh); 1206 if (err) { 1207 err = -err; 1208 goto error; 1209 } 1210 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1211 } 1212 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1213 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1214 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1215 config->dv_flow_en) { 1216 priv->sampler_en = 1; 1217 DRV_LOG(DEBUG, "The Sampler enabled!\n"); 1218 } else { 1219 priv->sampler_en = 0; 1220 if (!config->hca_attr.log_max_ft_sampler_num) 1221 DRV_LOG(WARNING, "No available register for" 1222 " Sampler."); 1223 else 1224 DRV_LOG(DEBUG, "DV flow is not supported!\n"); 1225 } 1226 #endif 1227 } 1228 if (config->tx_pp) { 1229 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1230 config->hca_attr.dev_freq_khz); 1231 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1232 config->hca_attr.qos.packet_pacing ? "" : "not "); 1233 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1234 config->hca_attr.cross_channel ? "" : "not "); 1235 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1236 config->hca_attr.wqe_index_ignore ? "" : "not "); 1237 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1238 config->hca_attr.non_wire_sq ? "" : "not "); 1239 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1240 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1241 config->hca_attr.log_max_static_sq_wq); 1242 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1243 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1244 if (!config->devx) { 1245 DRV_LOG(ERR, "DevX is required for packet pacing"); 1246 err = ENODEV; 1247 goto error; 1248 } 1249 if (!config->hca_attr.qos.packet_pacing) { 1250 DRV_LOG(ERR, "Packet pacing is not supported"); 1251 err = ENODEV; 1252 goto error; 1253 } 1254 if (!config->hca_attr.cross_channel) { 1255 DRV_LOG(ERR, "Cross channel operations are" 1256 " required for packet pacing"); 1257 err = ENODEV; 1258 goto error; 1259 } 1260 if (!config->hca_attr.wqe_index_ignore) { 1261 DRV_LOG(ERR, "WQE index ignore feature is" 1262 " required for packet pacing"); 1263 err = ENODEV; 1264 goto error; 1265 } 1266 if (!config->hca_attr.non_wire_sq) { 1267 DRV_LOG(ERR, "Non-wire SQ feature is" 1268 " required for packet pacing"); 1269 err = ENODEV; 1270 goto error; 1271 } 1272 if (!config->hca_attr.log_max_static_sq_wq) { 1273 DRV_LOG(ERR, "Static WQE SQ feature is" 1274 " required for packet pacing"); 1275 err = ENODEV; 1276 goto error; 1277 } 1278 if (!config->hca_attr.qos.wqe_rate_pp) { 1279 DRV_LOG(ERR, "WQE rate mode is required" 1280 " for packet pacing"); 1281 err = ENODEV; 1282 goto error; 1283 } 1284 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1285 DRV_LOG(ERR, "DevX does not provide UAR offset," 1286 " can't create queues for packet pacing"); 1287 err = ENODEV; 1288 goto error; 1289 #endif 1290 } 1291 if (config->devx) { 1292 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1293 1294 err = config->hca_attr.access_register_user ? 1295 mlx5_devx_cmd_register_read 1296 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1297 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1298 if (!err) { 1299 uint32_t ts_mode; 1300 1301 /* MTUTC register is read successfully. */ 1302 ts_mode = MLX5_GET(register_mtutc, reg, 1303 time_stamp_mode); 1304 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1305 config->rt_timestamp = 1; 1306 } else { 1307 /* Kernel does not support register reading. */ 1308 if (config->hca_attr.dev_freq_khz == 1309 (NS_PER_S / MS_PER_S)) 1310 config->rt_timestamp = 1; 1311 } 1312 } 1313 /* 1314 * If HW has bug working with tunnel packet decapsulation and 1315 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1316 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1317 */ 1318 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1319 config->hw_fcs_strip = 0; 1320 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1321 (config->hw_fcs_strip ? "" : "not ")); 1322 if (config->mprq.enabled && mprq) { 1323 if (config->mprq.stride_num_n && 1324 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1325 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1326 config->mprq.stride_num_n = 1327 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1328 mprq_min_stride_num_n), 1329 mprq_max_stride_num_n); 1330 DRV_LOG(WARNING, 1331 "the number of strides" 1332 " for Multi-Packet RQ is out of range," 1333 " setting default value (%u)", 1334 1 << config->mprq.stride_num_n); 1335 } 1336 if (config->mprq.stride_size_n && 1337 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1338 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1339 config->mprq.stride_size_n = 1340 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1341 mprq_min_stride_size_n), 1342 mprq_max_stride_size_n); 1343 DRV_LOG(WARNING, 1344 "the size of a stride" 1345 " for Multi-Packet RQ is out of range," 1346 " setting default value (%u)", 1347 1 << config->mprq.stride_size_n); 1348 } 1349 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1350 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1351 } else if (config->mprq.enabled && !mprq) { 1352 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1353 config->mprq.enabled = 0; 1354 } 1355 if (config->max_dump_files_num == 0) 1356 config->max_dump_files_num = 128; 1357 eth_dev = rte_eth_dev_allocate(name); 1358 if (eth_dev == NULL) { 1359 DRV_LOG(ERR, "can not allocate rte ethdev"); 1360 err = ENOMEM; 1361 goto error; 1362 } 1363 if (priv->representor) { 1364 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1365 eth_dev->data->representor_id = priv->representor_id; 1366 } 1367 /* 1368 * Store associated network device interface index. This index 1369 * is permanent throughout the lifetime of device. So, we may store 1370 * the ifindex here and use the cached value further. 1371 */ 1372 MLX5_ASSERT(spawn->ifindex); 1373 priv->if_index = spawn->ifindex; 1374 if (priv->pf_bond >= 0 && priv->master) { 1375 /* Get bond interface info */ 1376 err = mlx5_sysfs_bond_info(priv->if_index, 1377 &priv->bond_ifindex, 1378 priv->bond_name); 1379 if (err) 1380 DRV_LOG(ERR, "unable to get bond info: %s", 1381 strerror(rte_errno)); 1382 else 1383 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1384 priv->if_index, priv->bond_ifindex, 1385 priv->bond_name); 1386 } 1387 eth_dev->data->dev_private = priv; 1388 priv->dev_data = eth_dev->data; 1389 eth_dev->data->mac_addrs = priv->mac; 1390 if (spawn->pf_bond < 0) { 1391 eth_dev->device = dpdk_dev; 1392 } else { 1393 /* Use primary bond PCI as device. */ 1394 if (sh->bond_dev == UINT16_MAX) { 1395 sh->bond_dev = eth_dev->data->port_id; 1396 eth_dev->device = dpdk_dev; 1397 } else { 1398 eth_dev->device = rte_eth_devices[sh->bond_dev].device; 1399 } 1400 } 1401 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1402 /* Configure the first MAC address by default. */ 1403 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1404 DRV_LOG(ERR, 1405 "port %u cannot get MAC address, is mlx5_en" 1406 " loaded? (errno: %s)", 1407 eth_dev->data->port_id, strerror(rte_errno)); 1408 err = ENODEV; 1409 goto error; 1410 } 1411 DRV_LOG(INFO, 1412 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1413 eth_dev->data->port_id, 1414 mac.addr_bytes[0], mac.addr_bytes[1], 1415 mac.addr_bytes[2], mac.addr_bytes[3], 1416 mac.addr_bytes[4], mac.addr_bytes[5]); 1417 #ifdef RTE_LIBRTE_MLX5_DEBUG 1418 { 1419 char ifname[IF_NAMESIZE]; 1420 1421 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1422 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1423 eth_dev->data->port_id, ifname); 1424 else 1425 DRV_LOG(DEBUG, "port %u ifname is unknown", 1426 eth_dev->data->port_id); 1427 } 1428 #endif 1429 /* Get actual MTU if possible. */ 1430 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1431 if (err) { 1432 err = rte_errno; 1433 goto error; 1434 } 1435 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1436 priv->mtu); 1437 /* Initialize burst functions to prevent crashes before link-up. */ 1438 eth_dev->rx_pkt_burst = removed_rx_burst; 1439 eth_dev->tx_pkt_burst = removed_tx_burst; 1440 eth_dev->dev_ops = &mlx5_os_dev_ops; 1441 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1442 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1443 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1444 /* Register MAC address. */ 1445 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1446 if (config->vf && config->vf_nl_en) 1447 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1448 mlx5_ifindex(eth_dev), 1449 eth_dev->data->mac_addrs, 1450 MLX5_MAX_MAC_ADDRESSES); 1451 priv->flows = 0; 1452 priv->ctrl_flows = 0; 1453 rte_spinlock_init(&priv->flow_list_lock); 1454 TAILQ_INIT(&priv->flow_meters); 1455 TAILQ_INIT(&priv->flow_meter_profiles); 1456 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1457 mlx5_glue->dv_set_context_attr(sh->ctx, 1458 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1459 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1460 .alloc = &mlx5_alloc_verbs_buf, 1461 .free = &mlx5_free_verbs_buf, 1462 .data = priv, 1463 })); 1464 /* Bring Ethernet device up. */ 1465 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1466 eth_dev->data->port_id); 1467 mlx5_set_link_up(eth_dev); 1468 /* 1469 * Even though the interrupt handler is not installed yet, 1470 * interrupts will still trigger on the async_fd from 1471 * Verbs context returned by ibv_open_device(). 1472 */ 1473 mlx5_link_update(eth_dev, 0); 1474 #ifdef HAVE_MLX5DV_DR_ESWITCH 1475 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1476 (switch_info->representor || switch_info->master))) 1477 config->dv_esw_en = 0; 1478 #else 1479 config->dv_esw_en = 0; 1480 #endif 1481 /* Detect minimal data bytes to inline. */ 1482 mlx5_set_min_inline(spawn, config); 1483 /* Store device configuration on private structure. */ 1484 priv->config = *config; 1485 /* Create context for virtual machine VLAN workaround. */ 1486 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1487 if (config->dv_flow_en) { 1488 err = mlx5_alloc_shared_dr(priv); 1489 if (err) 1490 goto error; 1491 } 1492 if (config->devx && config->dv_flow_en && config->dest_tir) { 1493 priv->obj_ops = devx_obj_ops; 1494 priv->obj_ops.drop_action_create = 1495 ibv_obj_ops.drop_action_create; 1496 priv->obj_ops.drop_action_destroy = 1497 ibv_obj_ops.drop_action_destroy; 1498 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1499 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1500 #else 1501 if (config->dv_esw_en) 1502 priv->obj_ops.txq_obj_modify = 1503 ibv_obj_ops.txq_obj_modify; 1504 #endif 1505 /* Use specific wrappers for Tx object. */ 1506 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1507 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1508 1509 } else { 1510 priv->obj_ops = ibv_obj_ops; 1511 } 1512 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1513 if (!priv->drop_queue.hrxq) 1514 goto error; 1515 /* Supported Verbs flow priority number detection. */ 1516 err = mlx5_flow_discover_priorities(eth_dev); 1517 if (err < 0) { 1518 err = -err; 1519 goto error; 1520 } 1521 priv->config.flow_prio = err; 1522 if (!priv->config.dv_esw_en && 1523 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1524 DRV_LOG(WARNING, "metadata mode %u is not supported " 1525 "(no E-Switch)", priv->config.dv_xmeta_en); 1526 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1527 } 1528 mlx5_set_metadata_mask(eth_dev); 1529 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1530 !priv->sh->dv_regc0_mask) { 1531 DRV_LOG(ERR, "metadata mode %u is not supported " 1532 "(no metadata reg_c[0] is available)", 1533 priv->config.dv_xmeta_en); 1534 err = ENOTSUP; 1535 goto error; 1536 } 1537 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 1538 mlx5_hrxq_create_cb, 1539 mlx5_hrxq_match_cb, 1540 mlx5_hrxq_remove_cb); 1541 /* Query availability of metadata reg_c's. */ 1542 err = mlx5_flow_discover_mreg_c(eth_dev); 1543 if (err < 0) { 1544 err = -err; 1545 goto error; 1546 } 1547 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1548 DRV_LOG(DEBUG, 1549 "port %u extensive metadata register is not supported", 1550 eth_dev->data->port_id); 1551 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1552 DRV_LOG(ERR, "metadata mode %u is not supported " 1553 "(no metadata registers available)", 1554 priv->config.dv_xmeta_en); 1555 err = ENOTSUP; 1556 goto error; 1557 } 1558 } 1559 if (priv->config.dv_flow_en && 1560 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1561 mlx5_flow_ext_mreg_supported(eth_dev) && 1562 priv->sh->dv_regc0_mask) { 1563 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1564 MLX5_FLOW_MREG_HTABLE_SZ, 1565 0, 0, 1566 flow_dv_mreg_create_cb, 1567 NULL, 1568 flow_dv_mreg_remove_cb); 1569 if (!priv->mreg_cp_tbl) { 1570 err = ENOMEM; 1571 goto error; 1572 } 1573 priv->mreg_cp_tbl->ctx = eth_dev; 1574 } 1575 rte_spinlock_init(&priv->shared_act_sl); 1576 mlx5_flow_counter_mode_config(eth_dev); 1577 if (priv->config.dv_flow_en) 1578 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1579 return eth_dev; 1580 error: 1581 if (priv) { 1582 if (priv->mreg_cp_tbl) 1583 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1584 if (priv->sh) 1585 mlx5_os_free_shared_dr(priv); 1586 if (priv->nl_socket_route >= 0) 1587 close(priv->nl_socket_route); 1588 if (priv->nl_socket_rdma >= 0) 1589 close(priv->nl_socket_rdma); 1590 if (priv->vmwa_context) 1591 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1592 if (eth_dev && priv->drop_queue.hrxq) 1593 mlx5_drop_action_destroy(eth_dev); 1594 if (own_domain_id) 1595 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1596 mlx5_cache_list_destroy(&priv->hrxqs); 1597 mlx5_free(priv); 1598 if (eth_dev != NULL) 1599 eth_dev->data->dev_private = NULL; 1600 } 1601 if (eth_dev != NULL) { 1602 /* mac_addrs must not be freed alone because part of 1603 * dev_private 1604 **/ 1605 eth_dev->data->mac_addrs = NULL; 1606 rte_eth_dev_release_port(eth_dev); 1607 } 1608 if (sh) 1609 mlx5_free_shared_dev_ctx(sh); 1610 MLX5_ASSERT(err > 0); 1611 rte_errno = err; 1612 return NULL; 1613 } 1614 1615 /** 1616 * Comparison callback to sort device data. 1617 * 1618 * This is meant to be used with qsort(). 1619 * 1620 * @param a[in] 1621 * Pointer to pointer to first data object. 1622 * @param b[in] 1623 * Pointer to pointer to second data object. 1624 * 1625 * @return 1626 * 0 if both objects are equal, less than 0 if the first argument is less 1627 * than the second, greater than 0 otherwise. 1628 */ 1629 static int 1630 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1631 { 1632 const struct mlx5_switch_info *si_a = 1633 &((const struct mlx5_dev_spawn_data *)a)->info; 1634 const struct mlx5_switch_info *si_b = 1635 &((const struct mlx5_dev_spawn_data *)b)->info; 1636 int ret; 1637 1638 /* Master device first. */ 1639 ret = si_b->master - si_a->master; 1640 if (ret) 1641 return ret; 1642 /* Then representor devices. */ 1643 ret = si_b->representor - si_a->representor; 1644 if (ret) 1645 return ret; 1646 /* Unidentified devices come last in no specific order. */ 1647 if (!si_a->representor) 1648 return 0; 1649 /* Order representors by name. */ 1650 return si_a->port_name - si_b->port_name; 1651 } 1652 1653 /** 1654 * Match PCI information for possible slaves of bonding device. 1655 * 1656 * @param[in] ibv_dev 1657 * Pointer to Infiniband device structure. 1658 * @param[in] pci_dev 1659 * Pointer to PCI device structure to match PCI address. 1660 * @param[in] nl_rdma 1661 * Netlink RDMA group socket handle. 1662 * 1663 * @return 1664 * negative value if no bonding device found, otherwise 1665 * positive index of slave PF in bonding. 1666 */ 1667 static int 1668 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1669 const struct rte_pci_device *pci_dev, 1670 int nl_rdma) 1671 { 1672 char ifname[IF_NAMESIZE + 1]; 1673 unsigned int ifindex; 1674 unsigned int np, i; 1675 FILE *file = NULL; 1676 int pf = -1; 1677 1678 /* 1679 * Try to get master device name. If something goes 1680 * wrong suppose the lack of kernel support and no 1681 * bonding devices. 1682 */ 1683 if (nl_rdma < 0) 1684 return -1; 1685 if (!strstr(ibv_dev->name, "bond")) 1686 return -1; 1687 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1688 if (!np) 1689 return -1; 1690 /* 1691 * The Master device might not be on the predefined 1692 * port (not on port index 1, it is not garanted), 1693 * we have to scan all Infiniband device port and 1694 * find master. 1695 */ 1696 for (i = 1; i <= np; ++i) { 1697 /* Check whether Infiniband port is populated. */ 1698 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1699 if (!ifindex) 1700 continue; 1701 if (!if_indextoname(ifindex, ifname)) 1702 continue; 1703 /* Try to read bonding slave names from sysfs. */ 1704 MKSTR(slaves, 1705 "/sys/class/net/%s/master/bonding/slaves", ifname); 1706 file = fopen(slaves, "r"); 1707 if (file) 1708 break; 1709 } 1710 if (!file) 1711 return -1; 1712 /* Use safe format to check maximal buffer length. */ 1713 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1714 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1715 char tmp_str[IF_NAMESIZE + 32]; 1716 struct rte_pci_addr pci_addr; 1717 struct mlx5_switch_info info; 1718 1719 /* Process slave interface names in the loop. */ 1720 snprintf(tmp_str, sizeof(tmp_str), 1721 "/sys/class/net/%s", ifname); 1722 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1723 DRV_LOG(WARNING, "can not get PCI address" 1724 " for netdev \"%s\"", ifname); 1725 continue; 1726 } 1727 if (pci_dev->addr.domain != pci_addr.domain || 1728 pci_dev->addr.bus != pci_addr.bus || 1729 pci_dev->addr.devid != pci_addr.devid || 1730 pci_dev->addr.function != pci_addr.function) 1731 continue; 1732 /* Slave interface PCI address match found. */ 1733 fclose(file); 1734 snprintf(tmp_str, sizeof(tmp_str), 1735 "/sys/class/net/%s/phys_port_name", ifname); 1736 file = fopen(tmp_str, "rb"); 1737 if (!file) 1738 break; 1739 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1740 if (fscanf(file, "%32s", tmp_str) == 1) 1741 mlx5_translate_port_name(tmp_str, &info); 1742 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 1743 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1744 pf = info.port_name; 1745 break; 1746 } 1747 if (file) 1748 fclose(file); 1749 return pf; 1750 } 1751 1752 /** 1753 * DPDK callback to register a PCI device. 1754 * 1755 * This function spawns Ethernet devices out of a given PCI device. 1756 * 1757 * @param[in] pci_drv 1758 * PCI driver structure (mlx5_driver). 1759 * @param[in] pci_dev 1760 * PCI device information. 1761 * 1762 * @return 1763 * 0 on success, a negative errno value otherwise and rte_errno is set. 1764 */ 1765 int 1766 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1767 struct rte_pci_device *pci_dev) 1768 { 1769 struct ibv_device **ibv_list; 1770 /* 1771 * Number of found IB Devices matching with requested PCI BDF. 1772 * nd != 1 means there are multiple IB devices over the same 1773 * PCI device and we have representors and master. 1774 */ 1775 unsigned int nd = 0; 1776 /* 1777 * Number of found IB device Ports. nd = 1 and np = 1..n means 1778 * we have the single multiport IB device, and there may be 1779 * representors attached to some of found ports. 1780 */ 1781 unsigned int np = 0; 1782 /* 1783 * Number of DPDK ethernet devices to Spawn - either over 1784 * multiple IB devices or multiple ports of single IB device. 1785 * Actually this is the number of iterations to spawn. 1786 */ 1787 unsigned int ns = 0; 1788 /* 1789 * Bonding device 1790 * < 0 - no bonding device (single one) 1791 * >= 0 - bonding device (value is slave PF index) 1792 */ 1793 int bd = -1; 1794 struct mlx5_dev_spawn_data *list = NULL; 1795 struct mlx5_dev_config dev_config; 1796 unsigned int dev_config_vf; 1797 int ret; 1798 1799 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1800 mlx5_pmd_socket_init(); 1801 ret = mlx5_init_once(); 1802 if (ret) { 1803 DRV_LOG(ERR, "unable to init PMD global data: %s", 1804 strerror(rte_errno)); 1805 return -rte_errno; 1806 } 1807 errno = 0; 1808 ibv_list = mlx5_glue->get_device_list(&ret); 1809 if (!ibv_list) { 1810 rte_errno = errno ? errno : ENOSYS; 1811 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1812 return -rte_errno; 1813 } 1814 /* 1815 * First scan the list of all Infiniband devices to find 1816 * matching ones, gathering into the list. 1817 */ 1818 struct ibv_device *ibv_match[ret + 1]; 1819 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1820 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1821 unsigned int i; 1822 1823 while (ret-- > 0) { 1824 struct rte_pci_addr pci_addr; 1825 1826 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1827 bd = mlx5_device_bond_pci_match 1828 (ibv_list[ret], pci_dev, nl_rdma); 1829 if (bd >= 0) { 1830 /* 1831 * Bonding device detected. Only one match is allowed, 1832 * the bonding is supported over multi-port IB device, 1833 * there should be no matches on representor PCI 1834 * functions or non VF LAG bonding devices with 1835 * specified address. 1836 */ 1837 if (nd) { 1838 DRV_LOG(ERR, 1839 "multiple PCI match on bonding device" 1840 "\"%s\" found", ibv_list[ret]->name); 1841 rte_errno = ENOENT; 1842 ret = -rte_errno; 1843 goto exit; 1844 } 1845 DRV_LOG(INFO, "PCI information matches for" 1846 " slave %d bonding device \"%s\"", 1847 bd, ibv_list[ret]->name); 1848 ibv_match[nd++] = ibv_list[ret]; 1849 break; 1850 } 1851 if (mlx5_dev_to_pci_addr 1852 (ibv_list[ret]->ibdev_path, &pci_addr)) 1853 continue; 1854 if (pci_dev->addr.domain != pci_addr.domain || 1855 pci_dev->addr.bus != pci_addr.bus || 1856 pci_dev->addr.devid != pci_addr.devid || 1857 pci_dev->addr.function != pci_addr.function) 1858 continue; 1859 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1860 ibv_list[ret]->name); 1861 ibv_match[nd++] = ibv_list[ret]; 1862 } 1863 ibv_match[nd] = NULL; 1864 if (!nd) { 1865 /* No device matches, just complain and bail out. */ 1866 DRV_LOG(WARNING, 1867 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1868 " are kernel drivers loaded?", 1869 pci_dev->addr.domain, pci_dev->addr.bus, 1870 pci_dev->addr.devid, pci_dev->addr.function); 1871 rte_errno = ENOENT; 1872 ret = -rte_errno; 1873 goto exit; 1874 } 1875 if (nd == 1) { 1876 /* 1877 * Found single matching device may have multiple ports. 1878 * Each port may be representor, we have to check the port 1879 * number and check the representors existence. 1880 */ 1881 if (nl_rdma >= 0) 1882 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1883 if (!np) 1884 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1885 " ports number", ibv_match[0]->name); 1886 if (bd >= 0 && !np) { 1887 DRV_LOG(ERR, "can not get ports" 1888 " for bonding device"); 1889 rte_errno = ENOENT; 1890 ret = -rte_errno; 1891 goto exit; 1892 } 1893 } 1894 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 1895 if (bd >= 0) { 1896 /* 1897 * This may happen if there is VF LAG kernel support and 1898 * application is compiled with older rdma_core library. 1899 */ 1900 DRV_LOG(ERR, 1901 "No kernel/verbs support for VF LAG bonding found."); 1902 rte_errno = ENOTSUP; 1903 ret = -rte_errno; 1904 goto exit; 1905 } 1906 #endif 1907 /* 1908 * Now we can determine the maximal 1909 * amount of devices to be spawned. 1910 */ 1911 list = mlx5_malloc(MLX5_MEM_ZERO, 1912 sizeof(struct mlx5_dev_spawn_data) * 1913 (np ? np : nd), 1914 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1915 if (!list) { 1916 DRV_LOG(ERR, "spawn data array allocation failure"); 1917 rte_errno = ENOMEM; 1918 ret = -rte_errno; 1919 goto exit; 1920 } 1921 if (bd >= 0 || np > 1) { 1922 /* 1923 * Single IB device with multiple ports found, 1924 * it may be E-Switch master device and representors. 1925 * We have to perform identification through the ports. 1926 */ 1927 MLX5_ASSERT(nl_rdma >= 0); 1928 MLX5_ASSERT(ns == 0); 1929 MLX5_ASSERT(nd == 1); 1930 MLX5_ASSERT(np); 1931 for (i = 1; i <= np; ++i) { 1932 list[ns].max_port = np; 1933 list[ns].phys_port = i; 1934 list[ns].phys_dev = ibv_match[0]; 1935 list[ns].eth_dev = NULL; 1936 list[ns].pci_dev = pci_dev; 1937 list[ns].pf_bond = bd; 1938 list[ns].ifindex = mlx5_nl_ifindex 1939 (nl_rdma, 1940 mlx5_os_get_dev_device_name 1941 (list[ns].phys_dev), i); 1942 if (!list[ns].ifindex) { 1943 /* 1944 * No network interface index found for the 1945 * specified port, it means there is no 1946 * representor on this port. It's OK, 1947 * there can be disabled ports, for example 1948 * if sriov_numvfs < sriov_totalvfs. 1949 */ 1950 continue; 1951 } 1952 ret = -1; 1953 if (nl_route >= 0) 1954 ret = mlx5_nl_switch_info 1955 (nl_route, 1956 list[ns].ifindex, 1957 &list[ns].info); 1958 if (ret || (!list[ns].info.representor && 1959 !list[ns].info.master)) { 1960 /* 1961 * We failed to recognize representors with 1962 * Netlink, let's try to perform the task 1963 * with sysfs. 1964 */ 1965 ret = mlx5_sysfs_switch_info 1966 (list[ns].ifindex, 1967 &list[ns].info); 1968 } 1969 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 1970 if (!ret && bd >= 0) { 1971 switch (list[ns].info.name_type) { 1972 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 1973 if (list[ns].info.port_name == bd) 1974 ns++; 1975 break; 1976 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 1977 /* Fallthrough */ 1978 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 1979 if (list[ns].info.pf_num == bd) 1980 ns++; 1981 break; 1982 default: 1983 break; 1984 } 1985 continue; 1986 } 1987 #endif 1988 if (!ret && (list[ns].info.representor ^ 1989 list[ns].info.master)) 1990 ns++; 1991 } 1992 if (!ns) { 1993 DRV_LOG(ERR, 1994 "unable to recognize master/representors" 1995 " on the IB device with multiple ports"); 1996 rte_errno = ENOENT; 1997 ret = -rte_errno; 1998 goto exit; 1999 } 2000 } else { 2001 /* 2002 * The existence of several matching entries (nd > 1) means 2003 * port representors have been instantiated. No existing Verbs 2004 * call nor sysfs entries can tell them apart, this can only 2005 * be done through Netlink calls assuming kernel drivers are 2006 * recent enough to support them. 2007 * 2008 * In the event of identification failure through Netlink, 2009 * try again through sysfs, then: 2010 * 2011 * 1. A single IB device matches (nd == 1) with single 2012 * port (np=0/1) and is not a representor, assume 2013 * no switch support. 2014 * 2015 * 2. Otherwise no safe assumptions can be made; 2016 * complain louder and bail out. 2017 */ 2018 for (i = 0; i != nd; ++i) { 2019 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2020 list[ns].max_port = 1; 2021 list[ns].phys_port = 1; 2022 list[ns].phys_dev = ibv_match[i]; 2023 list[ns].eth_dev = NULL; 2024 list[ns].pci_dev = pci_dev; 2025 list[ns].pf_bond = -1; 2026 list[ns].ifindex = 0; 2027 if (nl_rdma >= 0) 2028 list[ns].ifindex = mlx5_nl_ifindex 2029 (nl_rdma, 2030 mlx5_os_get_dev_device_name 2031 (list[ns].phys_dev), 1); 2032 if (!list[ns].ifindex) { 2033 char ifname[IF_NAMESIZE]; 2034 2035 /* 2036 * Netlink failed, it may happen with old 2037 * ib_core kernel driver (before 4.16). 2038 * We can assume there is old driver because 2039 * here we are processing single ports IB 2040 * devices. Let's try sysfs to retrieve 2041 * the ifindex. The method works for 2042 * master device only. 2043 */ 2044 if (nd > 1) { 2045 /* 2046 * Multiple devices found, assume 2047 * representors, can not distinguish 2048 * master/representor and retrieve 2049 * ifindex via sysfs. 2050 */ 2051 continue; 2052 } 2053 ret = mlx5_get_ifname_sysfs 2054 (ibv_match[i]->ibdev_path, ifname); 2055 if (!ret) 2056 list[ns].ifindex = 2057 if_nametoindex(ifname); 2058 if (!list[ns].ifindex) { 2059 /* 2060 * No network interface index found 2061 * for the specified device, it means 2062 * there it is neither representor 2063 * nor master. 2064 */ 2065 continue; 2066 } 2067 } 2068 ret = -1; 2069 if (nl_route >= 0) 2070 ret = mlx5_nl_switch_info 2071 (nl_route, 2072 list[ns].ifindex, 2073 &list[ns].info); 2074 if (ret || (!list[ns].info.representor && 2075 !list[ns].info.master)) { 2076 /* 2077 * We failed to recognize representors with 2078 * Netlink, let's try to perform the task 2079 * with sysfs. 2080 */ 2081 ret = mlx5_sysfs_switch_info 2082 (list[ns].ifindex, 2083 &list[ns].info); 2084 } 2085 if (!ret && (list[ns].info.representor ^ 2086 list[ns].info.master)) { 2087 ns++; 2088 } else if ((nd == 1) && 2089 !list[ns].info.representor && 2090 !list[ns].info.master) { 2091 /* 2092 * Single IB device with 2093 * one physical port and 2094 * attached network device. 2095 * May be SRIOV is not enabled 2096 * or there is no representors. 2097 */ 2098 DRV_LOG(INFO, "no E-Switch support detected"); 2099 ns++; 2100 break; 2101 } 2102 } 2103 if (!ns) { 2104 DRV_LOG(ERR, 2105 "unable to recognize master/representors" 2106 " on the multiple IB devices"); 2107 rte_errno = ENOENT; 2108 ret = -rte_errno; 2109 goto exit; 2110 } 2111 } 2112 MLX5_ASSERT(ns); 2113 /* 2114 * Sort list to probe devices in natural order for users convenience 2115 * (i.e. master first, then representors from lowest to highest ID). 2116 */ 2117 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2118 /* Device specific configuration. */ 2119 switch (pci_dev->id.device_id) { 2120 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2121 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2122 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2123 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2124 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2125 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2126 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2127 dev_config_vf = 1; 2128 break; 2129 default: 2130 dev_config_vf = 0; 2131 break; 2132 } 2133 for (i = 0; i != ns; ++i) { 2134 uint32_t restore; 2135 2136 /* Default configuration. */ 2137 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2138 dev_config.vf = dev_config_vf; 2139 dev_config.mps = MLX5_ARG_UNSET; 2140 dev_config.dbnc = MLX5_ARG_UNSET; 2141 dev_config.rx_vec_en = 1; 2142 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2143 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2144 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2145 dev_config.txqs_inline = MLX5_ARG_UNSET; 2146 dev_config.vf_nl_en = 1; 2147 dev_config.mr_ext_memseg_en = 1; 2148 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2149 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2150 dev_config.dv_esw_en = 1; 2151 dev_config.dv_flow_en = 1; 2152 dev_config.decap_en = 1; 2153 dev_config.log_hp_size = MLX5_ARG_UNSET; 2154 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2155 &list[i], 2156 &dev_config); 2157 if (!list[i].eth_dev) { 2158 if (rte_errno != EBUSY && rte_errno != EEXIST) 2159 break; 2160 /* Device is disabled or already spawned. Ignore it. */ 2161 continue; 2162 } 2163 restore = list[i].eth_dev->data->dev_flags; 2164 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2165 /* Restore non-PCI flags cleared by the above call. */ 2166 list[i].eth_dev->data->dev_flags |= restore; 2167 rte_eth_dev_probing_finish(list[i].eth_dev); 2168 } 2169 if (i != ns) { 2170 DRV_LOG(ERR, 2171 "probe of PCI device " PCI_PRI_FMT " aborted after" 2172 " encountering an error: %s", 2173 pci_dev->addr.domain, pci_dev->addr.bus, 2174 pci_dev->addr.devid, pci_dev->addr.function, 2175 strerror(rte_errno)); 2176 ret = -rte_errno; 2177 /* Roll back. */ 2178 while (i--) { 2179 if (!list[i].eth_dev) 2180 continue; 2181 mlx5_dev_close(list[i].eth_dev); 2182 /* mac_addrs must not be freed because in dev_private */ 2183 list[i].eth_dev->data->mac_addrs = NULL; 2184 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2185 } 2186 /* Restore original error. */ 2187 rte_errno = -ret; 2188 } else { 2189 ret = 0; 2190 } 2191 exit: 2192 /* 2193 * Do the routine cleanup: 2194 * - close opened Netlink sockets 2195 * - free allocated spawn data array 2196 * - free the Infiniband device list 2197 */ 2198 if (nl_rdma >= 0) 2199 close(nl_rdma); 2200 if (nl_route >= 0) 2201 close(nl_route); 2202 if (list) 2203 mlx5_free(list); 2204 MLX5_ASSERT(ibv_list); 2205 mlx5_glue->free_device_list(ibv_list); 2206 return ret; 2207 } 2208 2209 static int 2210 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2211 { 2212 char *env; 2213 int value; 2214 2215 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2216 /* Get environment variable to store. */ 2217 env = getenv(MLX5_SHUT_UP_BF); 2218 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2219 if (config->dbnc == MLX5_ARG_UNSET) 2220 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2221 else 2222 setenv(MLX5_SHUT_UP_BF, 2223 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2224 return value; 2225 } 2226 2227 static void 2228 mlx5_restore_doorbell_mapping_env(int value) 2229 { 2230 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2231 /* Restore the original environment variable state. */ 2232 if (value == MLX5_ARG_UNSET) 2233 unsetenv(MLX5_SHUT_UP_BF); 2234 else 2235 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2236 } 2237 2238 /** 2239 * Extract pdn of PD object using DV API. 2240 * 2241 * @param[in] pd 2242 * Pointer to the verbs PD object. 2243 * @param[out] pdn 2244 * Pointer to the PD object number variable. 2245 * 2246 * @return 2247 * 0 on success, error value otherwise. 2248 */ 2249 int 2250 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2251 { 2252 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2253 struct mlx5dv_obj obj; 2254 struct mlx5dv_pd pd_info; 2255 int ret = 0; 2256 2257 obj.pd.in = pd; 2258 obj.pd.out = &pd_info; 2259 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2260 if (ret) { 2261 DRV_LOG(DEBUG, "Fail to get PD object info"); 2262 return ret; 2263 } 2264 *pdn = pd_info.pdn; 2265 return 0; 2266 #else 2267 (void)pd; 2268 (void)pdn; 2269 return -ENOTSUP; 2270 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2271 } 2272 2273 /** 2274 * Function API to open IB device. 2275 * 2276 * This function calls the Linux glue APIs to open a device. 2277 * 2278 * @param[in] spawn 2279 * Pointer to the IB device attributes (name, port, etc). 2280 * @param[out] config 2281 * Pointer to device configuration structure. 2282 * @param[out] sh 2283 * Pointer to shared context structure. 2284 * 2285 * @return 2286 * 0 on success, a positive error value otherwise. 2287 */ 2288 int 2289 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2290 const struct mlx5_dev_config *config, 2291 struct mlx5_dev_ctx_shared *sh) 2292 { 2293 int dbmap_env; 2294 int err = 0; 2295 2296 sh->numa_node = spawn->pci_dev->device.numa_node; 2297 pthread_mutex_init(&sh->txpp.mutex, NULL); 2298 /* 2299 * Configure environment variable "MLX5_BF_SHUT_UP" 2300 * before the device creation. The rdma_core library 2301 * checks the variable at device creation and 2302 * stores the result internally. 2303 */ 2304 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2305 /* Try to open IB device with DV first, then usual Verbs. */ 2306 errno = 0; 2307 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2308 if (sh->ctx) { 2309 sh->devx = 1; 2310 DRV_LOG(DEBUG, "DevX is supported"); 2311 /* The device is created, no need for environment. */ 2312 mlx5_restore_doorbell_mapping_env(dbmap_env); 2313 } else { 2314 /* The environment variable is still configured. */ 2315 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2316 err = errno ? errno : ENODEV; 2317 /* 2318 * The environment variable is not needed anymore, 2319 * all device creation attempts are completed. 2320 */ 2321 mlx5_restore_doorbell_mapping_env(dbmap_env); 2322 if (!sh->ctx) 2323 return err; 2324 DRV_LOG(DEBUG, "DevX is NOT supported"); 2325 err = 0; 2326 } 2327 return err; 2328 } 2329 2330 /** 2331 * Install shared asynchronous device events handler. 2332 * This function is implemented to support event sharing 2333 * between multiple ports of single IB device. 2334 * 2335 * @param sh 2336 * Pointer to mlx5_dev_ctx_shared object. 2337 */ 2338 void 2339 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2340 { 2341 int ret; 2342 int flags; 2343 2344 sh->intr_handle.fd = -1; 2345 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2346 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2347 F_SETFL, flags | O_NONBLOCK); 2348 if (ret) { 2349 DRV_LOG(INFO, "failed to change file descriptor async event" 2350 " queue"); 2351 } else { 2352 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2353 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2354 if (rte_intr_callback_register(&sh->intr_handle, 2355 mlx5_dev_interrupt_handler, sh)) { 2356 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2357 sh->intr_handle.fd = -1; 2358 } 2359 } 2360 if (sh->devx) { 2361 #ifdef HAVE_IBV_DEVX_ASYNC 2362 sh->intr_handle_devx.fd = -1; 2363 sh->devx_comp = 2364 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2365 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2366 if (!devx_comp) { 2367 DRV_LOG(INFO, "failed to allocate devx_comp."); 2368 return; 2369 } 2370 flags = fcntl(devx_comp->fd, F_GETFL); 2371 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2372 if (ret) { 2373 DRV_LOG(INFO, "failed to change file descriptor" 2374 " devx comp"); 2375 return; 2376 } 2377 sh->intr_handle_devx.fd = devx_comp->fd; 2378 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2379 if (rte_intr_callback_register(&sh->intr_handle_devx, 2380 mlx5_dev_interrupt_handler_devx, sh)) { 2381 DRV_LOG(INFO, "Fail to install the devx shared" 2382 " interrupt."); 2383 sh->intr_handle_devx.fd = -1; 2384 } 2385 #endif /* HAVE_IBV_DEVX_ASYNC */ 2386 } 2387 } 2388 2389 /** 2390 * Uninstall shared asynchronous device events handler. 2391 * This function is implemented to support event sharing 2392 * between multiple ports of single IB device. 2393 * 2394 * @param dev 2395 * Pointer to mlx5_dev_ctx_shared object. 2396 */ 2397 void 2398 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2399 { 2400 if (sh->intr_handle.fd >= 0) 2401 mlx5_intr_callback_unregister(&sh->intr_handle, 2402 mlx5_dev_interrupt_handler, sh); 2403 #ifdef HAVE_IBV_DEVX_ASYNC 2404 if (sh->intr_handle_devx.fd >= 0) 2405 rte_intr_callback_unregister(&sh->intr_handle_devx, 2406 mlx5_dev_interrupt_handler_devx, sh); 2407 if (sh->devx_comp) 2408 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2409 #endif 2410 } 2411 2412 /** 2413 * Read statistics by a named counter. 2414 * 2415 * @param[in] priv 2416 * Pointer to the private device data structure. 2417 * @param[in] ctr_name 2418 * Pointer to the name of the statistic counter to read 2419 * @param[out] stat 2420 * Pointer to read statistic value. 2421 * @return 2422 * 0 on success and stat is valud, 1 if failed to read the value 2423 * rte_errno is set. 2424 * 2425 */ 2426 int 2427 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2428 uint64_t *stat) 2429 { 2430 int fd; 2431 2432 if (priv->sh) { 2433 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2434 priv->sh->ibdev_path, 2435 priv->dev_port, 2436 ctr_name); 2437 fd = open(path, O_RDONLY); 2438 /* 2439 * in switchdev the file location is not per port 2440 * but rather in <ibdev_path>/hw_counters/<file_name>. 2441 */ 2442 if (fd == -1) { 2443 MKSTR(path1, "%s/hw_counters/%s", 2444 priv->sh->ibdev_path, 2445 ctr_name); 2446 fd = open(path1, O_RDONLY); 2447 } 2448 if (fd != -1) { 2449 char buf[21] = {'\0'}; 2450 ssize_t n = read(fd, buf, sizeof(buf)); 2451 2452 close(fd); 2453 if (n != -1) { 2454 *stat = strtoull(buf, NULL, 10); 2455 return 0; 2456 } 2457 } 2458 } 2459 *stat = 0; 2460 return 1; 2461 } 2462 2463 /** 2464 * Set the reg_mr and dereg_mr call backs 2465 * 2466 * @param reg_mr_cb[out] 2467 * Pointer to reg_mr func 2468 * @param dereg_mr_cb[out] 2469 * Pointer to dereg_mr func 2470 * 2471 */ 2472 void 2473 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2474 mlx5_dereg_mr_t *dereg_mr_cb) 2475 { 2476 *reg_mr_cb = mlx5_verbs_ops.reg_mr; 2477 *dereg_mr_cb = mlx5_verbs_ops.dereg_mr; 2478 } 2479 2480 /** 2481 * Remove a MAC address from device 2482 * 2483 * @param dev 2484 * Pointer to Ethernet device structure. 2485 * @param index 2486 * MAC address index. 2487 */ 2488 void 2489 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2490 { 2491 struct mlx5_priv *priv = dev->data->dev_private; 2492 const int vf = priv->config.vf; 2493 2494 if (vf) 2495 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2496 mlx5_ifindex(dev), priv->mac_own, 2497 &dev->data->mac_addrs[index], index); 2498 } 2499 2500 /** 2501 * Adds a MAC address to the device 2502 * 2503 * @param dev 2504 * Pointer to Ethernet device structure. 2505 * @param mac_addr 2506 * MAC address to register. 2507 * @param index 2508 * MAC address index. 2509 * 2510 * @return 2511 * 0 on success, a negative errno value otherwise 2512 */ 2513 int 2514 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2515 uint32_t index) 2516 { 2517 struct mlx5_priv *priv = dev->data->dev_private; 2518 const int vf = priv->config.vf; 2519 int ret = 0; 2520 2521 if (vf) 2522 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2523 mlx5_ifindex(dev), priv->mac_own, 2524 mac, index); 2525 return ret; 2526 } 2527 2528 /** 2529 * Modify a VF MAC address 2530 * 2531 * @param priv 2532 * Pointer to device private data. 2533 * @param mac_addr 2534 * MAC address to modify into. 2535 * @param iface_idx 2536 * Net device interface index 2537 * @param vf_index 2538 * VF index 2539 * 2540 * @return 2541 * 0 on success, a negative errno value otherwise 2542 */ 2543 int 2544 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2545 unsigned int iface_idx, 2546 struct rte_ether_addr *mac_addr, 2547 int vf_index) 2548 { 2549 return mlx5_nl_vf_mac_addr_modify 2550 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2551 } 2552 2553 /** 2554 * Set device promiscuous mode 2555 * 2556 * @param dev 2557 * Pointer to Ethernet device structure. 2558 * @param enable 2559 * 0 - promiscuous is disabled, otherwise - enabled 2560 * 2561 * @return 2562 * 0 on success, a negative error value otherwise 2563 */ 2564 int 2565 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2566 { 2567 struct mlx5_priv *priv = dev->data->dev_private; 2568 2569 return mlx5_nl_promisc(priv->nl_socket_route, 2570 mlx5_ifindex(dev), !!enable); 2571 } 2572 2573 /** 2574 * Set device promiscuous mode 2575 * 2576 * @param dev 2577 * Pointer to Ethernet device structure. 2578 * @param enable 2579 * 0 - all multicase is disabled, otherwise - enabled 2580 * 2581 * @return 2582 * 0 on success, a negative error value otherwise 2583 */ 2584 int 2585 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2586 { 2587 struct mlx5_priv *priv = dev->data->dev_private; 2588 2589 return mlx5_nl_allmulti(priv->nl_socket_route, 2590 mlx5_ifindex(dev), !!enable); 2591 } 2592 2593 /** 2594 * Flush device MAC addresses 2595 * 2596 * @param dev 2597 * Pointer to Ethernet device structure. 2598 * 2599 */ 2600 void 2601 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2602 { 2603 struct mlx5_priv *priv = dev->data->dev_private; 2604 2605 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2606 dev->data->mac_addrs, 2607 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2608 } 2609 2610 const struct eth_dev_ops mlx5_os_dev_ops = { 2611 .dev_configure = mlx5_dev_configure, 2612 .dev_start = mlx5_dev_start, 2613 .dev_stop = mlx5_dev_stop, 2614 .dev_set_link_down = mlx5_set_link_down, 2615 .dev_set_link_up = mlx5_set_link_up, 2616 .dev_close = mlx5_dev_close, 2617 .promiscuous_enable = mlx5_promiscuous_enable, 2618 .promiscuous_disable = mlx5_promiscuous_disable, 2619 .allmulticast_enable = mlx5_allmulticast_enable, 2620 .allmulticast_disable = mlx5_allmulticast_disable, 2621 .link_update = mlx5_link_update, 2622 .stats_get = mlx5_stats_get, 2623 .stats_reset = mlx5_stats_reset, 2624 .xstats_get = mlx5_xstats_get, 2625 .xstats_reset = mlx5_xstats_reset, 2626 .xstats_get_names = mlx5_xstats_get_names, 2627 .fw_version_get = mlx5_fw_version_get, 2628 .dev_infos_get = mlx5_dev_infos_get, 2629 .read_clock = mlx5_txpp_read_clock, 2630 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2631 .vlan_filter_set = mlx5_vlan_filter_set, 2632 .rx_queue_setup = mlx5_rx_queue_setup, 2633 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2634 .tx_queue_setup = mlx5_tx_queue_setup, 2635 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2636 .rx_queue_release = mlx5_rx_queue_release, 2637 .tx_queue_release = mlx5_tx_queue_release, 2638 .rx_queue_start = mlx5_rx_queue_start, 2639 .rx_queue_stop = mlx5_rx_queue_stop, 2640 .tx_queue_start = mlx5_tx_queue_start, 2641 .tx_queue_stop = mlx5_tx_queue_stop, 2642 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2643 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2644 .mac_addr_remove = mlx5_mac_addr_remove, 2645 .mac_addr_add = mlx5_mac_addr_add, 2646 .mac_addr_set = mlx5_mac_addr_set, 2647 .set_mc_addr_list = mlx5_set_mc_addr_list, 2648 .mtu_set = mlx5_dev_set_mtu, 2649 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2650 .vlan_offload_set = mlx5_vlan_offload_set, 2651 .reta_update = mlx5_dev_rss_reta_update, 2652 .reta_query = mlx5_dev_rss_reta_query, 2653 .rss_hash_update = mlx5_rss_hash_update, 2654 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2655 .filter_ctrl = mlx5_dev_filter_ctrl, 2656 .rxq_info_get = mlx5_rxq_info_get, 2657 .txq_info_get = mlx5_txq_info_get, 2658 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2659 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2660 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2661 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2662 .is_removed = mlx5_is_removed, 2663 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2664 .get_module_info = mlx5_get_module_info, 2665 .get_module_eeprom = mlx5_get_module_eeprom, 2666 .hairpin_cap_get = mlx5_hairpin_cap_get, 2667 .mtr_ops_get = mlx5_flow_meter_ops_get, 2668 .hairpin_bind = mlx5_hairpin_bind, 2669 .hairpin_unbind = mlx5_hairpin_unbind, 2670 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2671 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2672 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2673 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2674 }; 2675 2676 /* Available operations from secondary process. */ 2677 const struct eth_dev_ops mlx5_os_dev_sec_ops = { 2678 .stats_get = mlx5_stats_get, 2679 .stats_reset = mlx5_stats_reset, 2680 .xstats_get = mlx5_xstats_get, 2681 .xstats_reset = mlx5_xstats_reset, 2682 .xstats_get_names = mlx5_xstats_get_names, 2683 .fw_version_get = mlx5_fw_version_get, 2684 .dev_infos_get = mlx5_dev_infos_get, 2685 .read_clock = mlx5_txpp_read_clock, 2686 .rx_queue_start = mlx5_rx_queue_start, 2687 .rx_queue_stop = mlx5_rx_queue_stop, 2688 .tx_queue_start = mlx5_tx_queue_start, 2689 .tx_queue_stop = mlx5_tx_queue_stop, 2690 .rxq_info_get = mlx5_rxq_info_get, 2691 .txq_info_get = mlx5_txq_info_get, 2692 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2693 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2694 .get_module_info = mlx5_get_module_info, 2695 .get_module_eeprom = mlx5_get_module_eeprom, 2696 }; 2697 2698 /* Available operations in flow isolated mode. */ 2699 const struct eth_dev_ops mlx5_os_dev_ops_isolate = { 2700 .dev_configure = mlx5_dev_configure, 2701 .dev_start = mlx5_dev_start, 2702 .dev_stop = mlx5_dev_stop, 2703 .dev_set_link_down = mlx5_set_link_down, 2704 .dev_set_link_up = mlx5_set_link_up, 2705 .dev_close = mlx5_dev_close, 2706 .promiscuous_enable = mlx5_promiscuous_enable, 2707 .promiscuous_disable = mlx5_promiscuous_disable, 2708 .allmulticast_enable = mlx5_allmulticast_enable, 2709 .allmulticast_disable = mlx5_allmulticast_disable, 2710 .link_update = mlx5_link_update, 2711 .stats_get = mlx5_stats_get, 2712 .stats_reset = mlx5_stats_reset, 2713 .xstats_get = mlx5_xstats_get, 2714 .xstats_reset = mlx5_xstats_reset, 2715 .xstats_get_names = mlx5_xstats_get_names, 2716 .fw_version_get = mlx5_fw_version_get, 2717 .dev_infos_get = mlx5_dev_infos_get, 2718 .read_clock = mlx5_txpp_read_clock, 2719 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2720 .vlan_filter_set = mlx5_vlan_filter_set, 2721 .rx_queue_setup = mlx5_rx_queue_setup, 2722 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2723 .tx_queue_setup = mlx5_tx_queue_setup, 2724 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2725 .rx_queue_release = mlx5_rx_queue_release, 2726 .tx_queue_release = mlx5_tx_queue_release, 2727 .rx_queue_start = mlx5_rx_queue_start, 2728 .rx_queue_stop = mlx5_rx_queue_stop, 2729 .tx_queue_start = mlx5_tx_queue_start, 2730 .tx_queue_stop = mlx5_tx_queue_stop, 2731 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2732 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2733 .mac_addr_remove = mlx5_mac_addr_remove, 2734 .mac_addr_add = mlx5_mac_addr_add, 2735 .mac_addr_set = mlx5_mac_addr_set, 2736 .set_mc_addr_list = mlx5_set_mc_addr_list, 2737 .mtu_set = mlx5_dev_set_mtu, 2738 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2739 .vlan_offload_set = mlx5_vlan_offload_set, 2740 .filter_ctrl = mlx5_dev_filter_ctrl, 2741 .rxq_info_get = mlx5_rxq_info_get, 2742 .txq_info_get = mlx5_txq_info_get, 2743 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2744 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2745 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2746 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2747 .is_removed = mlx5_is_removed, 2748 .get_module_info = mlx5_get_module_info, 2749 .get_module_eeprom = mlx5_get_module_eeprom, 2750 .hairpin_cap_get = mlx5_hairpin_cap_get, 2751 .mtr_ops_get = mlx5_flow_meter_ops_get, 2752 .hairpin_bind = mlx5_hairpin_bind, 2753 .hairpin_unbind = mlx5_hairpin_unbind, 2754 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2755 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2756 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2757 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2758 }; 2759