1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /* rte flow indexed pool configuration. */ 71 static struct mlx5_indexed_pool_config icfg[] = { 72 { 73 .size = sizeof(struct rte_flow), 74 .trunk_size = 64, 75 .need_lock = 1, 76 .release_mem_en = 0, 77 .malloc = mlx5_malloc, 78 .free = mlx5_free, 79 .per_core_cache = 0, 80 .type = "ctl_flow_ipool", 81 }, 82 { 83 .size = sizeof(struct rte_flow), 84 .trunk_size = 64, 85 .grow_trunk = 3, 86 .grow_shift = 2, 87 .need_lock = 1, 88 .release_mem_en = 0, 89 .malloc = mlx5_malloc, 90 .free = mlx5_free, 91 .per_core_cache = 1 << 14, 92 .type = "rte_flow_ipool", 93 }, 94 { 95 .size = sizeof(struct rte_flow), 96 .trunk_size = 64, 97 .grow_trunk = 3, 98 .grow_shift = 2, 99 .need_lock = 1, 100 .release_mem_en = 0, 101 .malloc = mlx5_malloc, 102 .free = mlx5_free, 103 .per_core_cache = 0, 104 .type = "mcp_flow_ipool", 105 }, 106 }; 107 108 /** 109 * Set the completion channel file descriptor interrupt as non-blocking. 110 * 111 * @param[in] rxq_obj 112 * Pointer to RQ channel object, which includes the channel fd 113 * 114 * @param[out] fd 115 * The file descriptor (representing the interrupt) used in this channel. 116 * 117 * @return 118 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 119 */ 120 int 121 mlx5_os_set_nonblock_channel_fd(int fd) 122 { 123 int flags; 124 125 flags = fcntl(fd, F_GETFL); 126 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 127 } 128 129 /** 130 * Get mlx5 device attributes. The glue function query_device_ex() is called 131 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 132 * device attributes from the glue out parameter. 133 * 134 * @param sh 135 * Pointer to shared device context. 136 * 137 * @return 138 * 0 on success, a negative errno value otherwise and rte_errno is set. 139 */ 140 int 141 mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh) 142 { 143 int err; 144 struct mlx5_common_device *cdev = sh->cdev; 145 struct mlx5_hca_attr *hca_attr = &cdev->config.hca_attr; 146 struct ibv_device_attr_ex attr_ex = { .comp_mask = 0 }; 147 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 148 149 err = mlx5_glue->query_device_ex(cdev->ctx, NULL, &attr_ex); 150 if (err) { 151 rte_errno = errno; 152 return -rte_errno; 153 } 154 #ifdef HAVE_IBV_MLX5_MOD_SWP 155 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 156 #endif 157 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 158 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 159 #endif 160 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 161 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 162 #endif 163 err = mlx5_glue->dv_query_device(cdev->ctx, &dv_attr); 164 if (err) { 165 rte_errno = errno; 166 return -rte_errno; 167 } 168 memset(&sh->dev_cap, 0, sizeof(struct mlx5_dev_cap)); 169 if (mlx5_dev_is_pci(cdev->dev)) 170 sh->dev_cap.vf = mlx5_dev_is_vf_pci(RTE_DEV_TO_PCI(cdev->dev)); 171 else 172 sh->dev_cap.sf = 1; 173 sh->dev_cap.max_qp_wr = attr_ex.orig_attr.max_qp_wr; 174 sh->dev_cap.max_sge = attr_ex.orig_attr.max_sge; 175 sh->dev_cap.max_cq = attr_ex.orig_attr.max_cq; 176 sh->dev_cap.max_qp = attr_ex.orig_attr.max_qp; 177 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 178 sh->dev_cap.dest_tir = 1; 179 #endif 180 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) && defined(HAVE_MLX5DV_DR) 181 DRV_LOG(DEBUG, "DV flow is supported."); 182 sh->dev_cap.dv_flow_en = 1; 183 #endif 184 #ifdef HAVE_MLX5DV_DR_ESWITCH 185 if (hca_attr->eswitch_manager && sh->dev_cap.dv_flow_en && sh->esw_mode) 186 sh->dev_cap.dv_esw_en = 1; 187 #endif 188 /* 189 * Multi-packet send is supported by ConnectX-4 Lx PF as well 190 * as all ConnectX-5 devices. 191 */ 192 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 193 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 194 DRV_LOG(DEBUG, "Enhanced MPW is supported."); 195 sh->dev_cap.mps = MLX5_MPW_ENHANCED; 196 } else { 197 DRV_LOG(DEBUG, "MPW is supported."); 198 sh->dev_cap.mps = MLX5_MPW; 199 } 200 } else { 201 DRV_LOG(DEBUG, "MPW isn't supported."); 202 sh->dev_cap.mps = MLX5_MPW_DISABLED; 203 } 204 #if (RTE_CACHE_LINE_SIZE == 128) 205 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP) 206 sh->dev_cap.cqe_comp = 1; 207 DRV_LOG(DEBUG, "Rx CQE 128B compression is %ssupported.", 208 sh->dev_cap.cqe_comp ? "" : "not "); 209 #else 210 sh->dev_cap.cqe_comp = 1; 211 #endif 212 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 213 sh->dev_cap.mpls_en = 214 ((dv_attr.tunnel_offloads_caps & 215 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 216 (dv_attr.tunnel_offloads_caps & 217 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 218 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported.", 219 sh->dev_cap.mpls_en ? "" : "not "); 220 #else 221 DRV_LOG(WARNING, 222 "MPLS over GRE/UDP tunnel offloading disabled due to old OFED/rdma-core version or firmware configuration"); 223 #endif 224 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 225 sh->dev_cap.hw_padding = !!attr_ex.rx_pad_end_addr_align; 226 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 227 sh->dev_cap.hw_padding = !!(attr_ex.device_cap_flags_ex & 228 IBV_DEVICE_PCI_WRITE_END_PADDING); 229 #endif 230 sh->dev_cap.hw_csum = 231 !!(attr_ex.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); 232 DRV_LOG(DEBUG, "Checksum offloading is %ssupported.", 233 sh->dev_cap.hw_csum ? "" : "not "); 234 sh->dev_cap.hw_vlan_strip = !!(attr_ex.raw_packet_caps & 235 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 236 DRV_LOG(DEBUG, "VLAN stripping is %ssupported.", 237 (sh->dev_cap.hw_vlan_strip ? "" : "not ")); 238 sh->dev_cap.hw_fcs_strip = !!(attr_ex.raw_packet_caps & 239 IBV_RAW_PACKET_CAP_SCATTER_FCS); 240 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 241 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 242 DRV_LOG(DEBUG, "Counters are not supported."); 243 #endif 244 /* 245 * DPDK doesn't support larger/variable indirection tables. 246 * Once DPDK supports it, take max size from device attr. 247 */ 248 sh->dev_cap.ind_table_max_size = 249 RTE_MIN(attr_ex.rss_caps.max_rwq_indirection_table_size, 250 (unsigned int)RTE_ETH_RSS_RETA_SIZE_512); 251 DRV_LOG(DEBUG, "Maximum Rx indirection table size is %u", 252 sh->dev_cap.ind_table_max_size); 253 sh->dev_cap.tso = (attr_ex.tso_caps.max_tso > 0 && 254 (attr_ex.tso_caps.supported_qpts & 255 (1 << IBV_QPT_RAW_PACKET))); 256 if (sh->dev_cap.tso) 257 sh->dev_cap.tso_max_payload_sz = attr_ex.tso_caps.max_tso; 258 strlcpy(sh->dev_cap.fw_ver, attr_ex.orig_attr.fw_ver, 259 sizeof(sh->dev_cap.fw_ver)); 260 #ifdef HAVE_IBV_MLX5_MOD_SWP 261 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 262 sh->dev_cap.swp = dv_attr.sw_parsing_caps.sw_parsing_offloads & 263 (MLX5_SW_PARSING_CAP | 264 MLX5_SW_PARSING_CSUM_CAP | 265 MLX5_SW_PARSING_TSO_CAP); 266 DRV_LOG(DEBUG, "SWP support: %u", sh->dev_cap.swp); 267 #endif 268 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 269 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 270 struct mlx5dv_striding_rq_caps *strd_rq_caps = 271 &dv_attr.striding_rq_caps; 272 273 sh->dev_cap.mprq.enabled = 1; 274 sh->dev_cap.mprq.log_min_stride_size = 275 strd_rq_caps->min_single_stride_log_num_of_bytes; 276 sh->dev_cap.mprq.log_max_stride_size = 277 strd_rq_caps->max_single_stride_log_num_of_bytes; 278 sh->dev_cap.mprq.log_min_stride_num = 279 strd_rq_caps->min_single_wqe_log_num_of_strides; 280 sh->dev_cap.mprq.log_max_stride_num = 281 strd_rq_caps->max_single_wqe_log_num_of_strides; 282 sh->dev_cap.mprq.log_min_stride_wqe_size = 283 cdev->config.devx ? 284 hca_attr->log_min_stride_wqe_sz : 285 MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 286 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %u", 287 sh->dev_cap.mprq.log_min_stride_size); 288 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %u", 289 sh->dev_cap.mprq.log_max_stride_size); 290 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %u", 291 sh->dev_cap.mprq.log_min_stride_num); 292 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %u", 293 sh->dev_cap.mprq.log_max_stride_num); 294 DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %u", 295 sh->dev_cap.mprq.log_min_stride_wqe_size); 296 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 297 strd_rq_caps->supported_qpts); 298 DRV_LOG(DEBUG, "Device supports Multi-Packet RQ."); 299 } 300 #endif 301 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 302 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 303 sh->dev_cap.tunnel_en = dv_attr.tunnel_offloads_caps & 304 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP | 305 MLX5_TUNNELED_OFFLOADS_GRE_CAP | 306 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP); 307 } 308 if (sh->dev_cap.tunnel_en) { 309 DRV_LOG(DEBUG, "Tunnel offloading is supported for %s%s%s", 310 sh->dev_cap.tunnel_en & 311 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "", 312 sh->dev_cap.tunnel_en & 313 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "", 314 sh->dev_cap.tunnel_en & 315 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""); 316 } else { 317 DRV_LOG(DEBUG, "Tunnel offloading is not supported."); 318 } 319 #else 320 DRV_LOG(WARNING, 321 "Tunnel offloading disabled due to old OFED/rdma-core version"); 322 #endif 323 if (!sh->cdev->config.devx) 324 return 0; 325 /* Check capabilities for Packet Pacing. */ 326 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz.", 327 hca_attr->dev_freq_khz); 328 DRV_LOG(DEBUG, "Packet pacing is %ssupported.", 329 hca_attr->qos.packet_pacing ? "" : "not "); 330 DRV_LOG(DEBUG, "Cross channel ops are %ssupported.", 331 hca_attr->cross_channel ? "" : "not "); 332 DRV_LOG(DEBUG, "WQE index ignore is %ssupported.", 333 hca_attr->wqe_index_ignore ? "" : "not "); 334 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported.", 335 hca_attr->non_wire_sq ? "" : "not "); 336 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 337 hca_attr->log_max_static_sq_wq ? "" : "not ", 338 hca_attr->log_max_static_sq_wq); 339 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported.", 340 hca_attr->qos.wqe_rate_pp ? "" : "not "); 341 sh->dev_cap.txpp_en = hca_attr->qos.packet_pacing; 342 if (!hca_attr->cross_channel) { 343 DRV_LOG(DEBUG, 344 "Cross channel operations are required for packet pacing."); 345 sh->dev_cap.txpp_en = 0; 346 } 347 if (!hca_attr->wqe_index_ignore) { 348 DRV_LOG(DEBUG, 349 "WQE index ignore feature is required for packet pacing."); 350 sh->dev_cap.txpp_en = 0; 351 } 352 if (!hca_attr->non_wire_sq) { 353 DRV_LOG(DEBUG, 354 "Non-wire SQ feature is required for packet pacing."); 355 sh->dev_cap.txpp_en = 0; 356 } 357 if (!hca_attr->log_max_static_sq_wq) { 358 DRV_LOG(DEBUG, 359 "Static WQE SQ feature is required for packet pacing."); 360 sh->dev_cap.txpp_en = 0; 361 } 362 if (!hca_attr->qos.wqe_rate_pp) { 363 DRV_LOG(DEBUG, 364 "WQE rate mode is required for packet pacing."); 365 sh->dev_cap.txpp_en = 0; 366 } 367 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 368 DRV_LOG(DEBUG, 369 "DevX does not provide UAR offset, can't create queues for packet pacing."); 370 sh->dev_cap.txpp_en = 0; 371 #endif 372 /* Check for LRO support. */ 373 if (sh->dev_cap.dest_tir && sh->dev_cap.dv_flow_en && 374 hca_attr->lro_cap) { 375 /* TBD check tunnel lro caps. */ 376 sh->dev_cap.lro_supported = 1; 377 DRV_LOG(DEBUG, "Device supports LRO."); 378 DRV_LOG(DEBUG, 379 "LRO minimal size of TCP segment required for coalescing is %d bytes.", 380 hca_attr->lro_min_mss_size); 381 } 382 sh->dev_cap.scatter_fcs_w_decap_disable = 383 hca_attr->scatter_fcs_w_decap_disable; 384 sh->dev_cap.rq_delay_drop_en = hca_attr->rq_delay_drop; 385 mlx5_rt_timestamp_config(sh, hca_attr); 386 return 0; 387 } 388 389 /** 390 * Detect misc5 support or not 391 * 392 * @param[in] priv 393 * Device private data pointer 394 */ 395 #ifdef HAVE_MLX5DV_DR 396 static void 397 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 398 { 399 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 400 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 401 * Case: IPv4--->UDP--->VxLAN--->vni 402 */ 403 void *tbl; 404 struct mlx5_flow_dv_match_params matcher_mask; 405 void *match_m; 406 void *matcher; 407 void *headers_m; 408 void *misc5_m; 409 uint32_t *tunnel_header_m; 410 struct mlx5dv_flow_matcher_attr dv_attr; 411 412 memset(&matcher_mask, 0, sizeof(matcher_mask)); 413 matcher_mask.size = sizeof(matcher_mask.buf); 414 match_m = matcher_mask.buf; 415 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 416 misc5_m = MLX5_ADDR_OF(fte_match_param, 417 match_m, misc_parameters_5); 418 tunnel_header_m = (uint32_t *) 419 MLX5_ADDR_OF(fte_match_set_misc5, 420 misc5_m, tunnel_header_1); 421 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 422 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 423 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 424 *tunnel_header_m = 0xffffff; 425 426 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 427 if (!tbl) { 428 DRV_LOG(INFO, "No SW steering support"); 429 return; 430 } 431 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 432 dv_attr.match_mask = (void *)&matcher_mask, 433 dv_attr.match_criteria_enable = 434 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 435 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 436 dv_attr.priority = 3; 437 #ifdef HAVE_MLX5DV_DR_ESWITCH 438 void *misc2_m; 439 if (priv->sh->config.dv_esw_en) { 440 /* FDB enabled reg_c_0 */ 441 dv_attr.match_criteria_enable |= 442 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 443 misc2_m = MLX5_ADDR_OF(fte_match_param, 444 match_m, misc_parameters_2); 445 MLX5_SET(fte_match_set_misc2, misc2_m, 446 metadata_reg_c_0, 0xffff); 447 } 448 #endif 449 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx, 450 &dv_attr, tbl); 451 if (matcher) { 452 priv->sh->misc5_cap = 1; 453 mlx5_glue->dv_destroy_flow_matcher(matcher); 454 } 455 mlx5_glue->dr_destroy_flow_tbl(tbl); 456 #else 457 RTE_SET_USED(priv); 458 #endif 459 } 460 #endif 461 462 /** 463 * Initialize DR related data within private structure. 464 * Routine checks the reference counter and does actual 465 * resources creation/initialization only if counter is zero. 466 * 467 * @param[in] priv 468 * Pointer to the private device data structure. 469 * 470 * @return 471 * Zero on success, positive error code otherwise. 472 */ 473 static int 474 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 475 { 476 struct mlx5_dev_ctx_shared *sh = priv->sh; 477 char s[MLX5_NAME_SIZE] __rte_unused; 478 int err; 479 480 MLX5_ASSERT(sh && sh->refcnt); 481 if (sh->refcnt > 1) 482 return 0; 483 err = mlx5_alloc_table_hash_list(priv); 484 if (err) 485 goto error; 486 /* The resources below are only valid with DV support. */ 487 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 488 /* Init port id action list. */ 489 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 490 sh->port_id_action_list = mlx5_list_create(s, sh, true, 491 flow_dv_port_id_create_cb, 492 flow_dv_port_id_match_cb, 493 flow_dv_port_id_remove_cb, 494 flow_dv_port_id_clone_cb, 495 flow_dv_port_id_clone_free_cb); 496 if (!sh->port_id_action_list) 497 goto error; 498 /* Init push vlan action list. */ 499 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 500 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 501 flow_dv_push_vlan_create_cb, 502 flow_dv_push_vlan_match_cb, 503 flow_dv_push_vlan_remove_cb, 504 flow_dv_push_vlan_clone_cb, 505 flow_dv_push_vlan_clone_free_cb); 506 if (!sh->push_vlan_action_list) 507 goto error; 508 /* Init sample action list. */ 509 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 510 sh->sample_action_list = mlx5_list_create(s, sh, true, 511 flow_dv_sample_create_cb, 512 flow_dv_sample_match_cb, 513 flow_dv_sample_remove_cb, 514 flow_dv_sample_clone_cb, 515 flow_dv_sample_clone_free_cb); 516 if (!sh->sample_action_list) 517 goto error; 518 /* Init dest array action list. */ 519 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 520 sh->dest_array_list = mlx5_list_create(s, sh, true, 521 flow_dv_dest_array_create_cb, 522 flow_dv_dest_array_match_cb, 523 flow_dv_dest_array_remove_cb, 524 flow_dv_dest_array_clone_cb, 525 flow_dv_dest_array_clone_free_cb); 526 if (!sh->dest_array_list) 527 goto error; 528 /* Init shared flex parsers list, no need lcore_share */ 529 snprintf(s, sizeof(s), "%s_flex_parsers_list", sh->ibdev_name); 530 sh->flex_parsers_dv = mlx5_list_create(s, sh, false, 531 mlx5_flex_parser_create_cb, 532 mlx5_flex_parser_match_cb, 533 mlx5_flex_parser_remove_cb, 534 mlx5_flex_parser_clone_cb, 535 mlx5_flex_parser_clone_free_cb); 536 if (!sh->flex_parsers_dv) 537 goto error; 538 #endif 539 #ifdef HAVE_MLX5DV_DR 540 void *domain; 541 542 /* Reference counter is zero, we should initialize structures. */ 543 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 544 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 545 if (!domain) { 546 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 547 err = errno; 548 goto error; 549 } 550 sh->rx_domain = domain; 551 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 552 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 553 if (!domain) { 554 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 555 err = errno; 556 goto error; 557 } 558 sh->tx_domain = domain; 559 #ifdef HAVE_MLX5DV_DR_ESWITCH 560 if (sh->config.dv_esw_en) { 561 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 562 MLX5DV_DR_DOMAIN_TYPE_FDB); 563 if (!domain) { 564 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 565 err = errno; 566 goto error; 567 } 568 sh->fdb_domain = domain; 569 } 570 /* 571 * The drop action is just some dummy placeholder in rdma-core. It 572 * does not belong to domains and has no any attributes, and, can be 573 * shared by the entire device. 574 */ 575 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 576 if (!sh->dr_drop_action) { 577 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 578 err = errno; 579 goto error; 580 } 581 #endif 582 if (!sh->tunnel_hub && sh->config.dv_miss_info) 583 err = mlx5_alloc_tunnel_hub(sh); 584 if (err) { 585 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 586 goto error; 587 } 588 if (sh->config.reclaim_mode == MLX5_RCM_AGGR) { 589 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 590 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 591 if (sh->fdb_domain) 592 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 593 } 594 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 595 if (!sh->config.allow_duplicate_pattern) { 596 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 597 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 598 #endif 599 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 600 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 601 if (sh->fdb_domain) 602 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 603 } 604 605 __mlx5_discovery_misc5_cap(priv); 606 #endif /* HAVE_MLX5DV_DR */ 607 sh->default_miss_action = 608 mlx5_glue->dr_create_flow_action_default_miss(); 609 if (!sh->default_miss_action) 610 DRV_LOG(WARNING, "Default miss action is not supported."); 611 LIST_INIT(&sh->shared_rxqs); 612 return 0; 613 error: 614 /* Rollback the created objects. */ 615 if (sh->rx_domain) { 616 mlx5_glue->dr_destroy_domain(sh->rx_domain); 617 sh->rx_domain = NULL; 618 } 619 if (sh->tx_domain) { 620 mlx5_glue->dr_destroy_domain(sh->tx_domain); 621 sh->tx_domain = NULL; 622 } 623 if (sh->fdb_domain) { 624 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 625 sh->fdb_domain = NULL; 626 } 627 if (sh->dr_drop_action) { 628 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 629 sh->dr_drop_action = NULL; 630 } 631 if (sh->pop_vlan_action) { 632 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 633 sh->pop_vlan_action = NULL; 634 } 635 if (sh->encaps_decaps) { 636 mlx5_hlist_destroy(sh->encaps_decaps); 637 sh->encaps_decaps = NULL; 638 } 639 if (sh->modify_cmds) { 640 mlx5_hlist_destroy(sh->modify_cmds); 641 sh->modify_cmds = NULL; 642 } 643 if (sh->tag_table) { 644 /* tags should be destroyed with flow before. */ 645 mlx5_hlist_destroy(sh->tag_table); 646 sh->tag_table = NULL; 647 } 648 if (sh->tunnel_hub) { 649 mlx5_release_tunnel_hub(sh, priv->dev_port); 650 sh->tunnel_hub = NULL; 651 } 652 mlx5_free_table_hash_list(priv); 653 if (sh->port_id_action_list) { 654 mlx5_list_destroy(sh->port_id_action_list); 655 sh->port_id_action_list = NULL; 656 } 657 if (sh->push_vlan_action_list) { 658 mlx5_list_destroy(sh->push_vlan_action_list); 659 sh->push_vlan_action_list = NULL; 660 } 661 if (sh->sample_action_list) { 662 mlx5_list_destroy(sh->sample_action_list); 663 sh->sample_action_list = NULL; 664 } 665 if (sh->dest_array_list) { 666 mlx5_list_destroy(sh->dest_array_list); 667 sh->dest_array_list = NULL; 668 } 669 return err; 670 } 671 672 /** 673 * Destroy DR related data within private structure. 674 * 675 * @param[in] priv 676 * Pointer to the private device data structure. 677 */ 678 void 679 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 680 { 681 struct mlx5_dev_ctx_shared *sh = priv->sh; 682 683 MLX5_ASSERT(sh && sh->refcnt); 684 if (sh->refcnt > 1) 685 return; 686 MLX5_ASSERT(LIST_EMPTY(&sh->shared_rxqs)); 687 #ifdef HAVE_MLX5DV_DR 688 if (sh->rx_domain) { 689 mlx5_glue->dr_destroy_domain(sh->rx_domain); 690 sh->rx_domain = NULL; 691 } 692 if (sh->tx_domain) { 693 mlx5_glue->dr_destroy_domain(sh->tx_domain); 694 sh->tx_domain = NULL; 695 } 696 #ifdef HAVE_MLX5DV_DR_ESWITCH 697 if (sh->fdb_domain) { 698 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 699 sh->fdb_domain = NULL; 700 } 701 if (sh->dr_drop_action) { 702 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 703 sh->dr_drop_action = NULL; 704 } 705 #endif 706 if (sh->pop_vlan_action) { 707 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 708 sh->pop_vlan_action = NULL; 709 } 710 #endif /* HAVE_MLX5DV_DR */ 711 if (sh->default_miss_action) 712 mlx5_glue->destroy_flow_action 713 (sh->default_miss_action); 714 if (sh->encaps_decaps) { 715 mlx5_hlist_destroy(sh->encaps_decaps); 716 sh->encaps_decaps = NULL; 717 } 718 if (sh->modify_cmds) { 719 mlx5_hlist_destroy(sh->modify_cmds); 720 sh->modify_cmds = NULL; 721 } 722 if (sh->tag_table) { 723 /* tags should be destroyed with flow before. */ 724 mlx5_hlist_destroy(sh->tag_table); 725 sh->tag_table = NULL; 726 } 727 if (sh->tunnel_hub) { 728 mlx5_release_tunnel_hub(sh, priv->dev_port); 729 sh->tunnel_hub = NULL; 730 } 731 mlx5_free_table_hash_list(priv); 732 if (sh->port_id_action_list) { 733 mlx5_list_destroy(sh->port_id_action_list); 734 sh->port_id_action_list = NULL; 735 } 736 if (sh->push_vlan_action_list) { 737 mlx5_list_destroy(sh->push_vlan_action_list); 738 sh->push_vlan_action_list = NULL; 739 } 740 if (sh->sample_action_list) { 741 mlx5_list_destroy(sh->sample_action_list); 742 sh->sample_action_list = NULL; 743 } 744 if (sh->dest_array_list) { 745 mlx5_list_destroy(sh->dest_array_list); 746 sh->dest_array_list = NULL; 747 } 748 } 749 750 /** 751 * Initialize shared data between primary and secondary process. 752 * 753 * A memzone is reserved by primary process and secondary processes attach to 754 * the memzone. 755 * 756 * @return 757 * 0 on success, a negative errno value otherwise and rte_errno is set. 758 */ 759 static int 760 mlx5_init_shared_data(void) 761 { 762 const struct rte_memzone *mz; 763 int ret = 0; 764 765 rte_spinlock_lock(&mlx5_shared_data_lock); 766 if (mlx5_shared_data == NULL) { 767 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 768 /* Allocate shared memory. */ 769 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 770 sizeof(*mlx5_shared_data), 771 SOCKET_ID_ANY, 0); 772 if (mz == NULL) { 773 DRV_LOG(ERR, 774 "Cannot allocate mlx5 shared data"); 775 ret = -rte_errno; 776 goto error; 777 } 778 mlx5_shared_data = mz->addr; 779 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 780 rte_spinlock_init(&mlx5_shared_data->lock); 781 } else { 782 /* Lookup allocated shared memory. */ 783 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 784 if (mz == NULL) { 785 DRV_LOG(ERR, 786 "Cannot attach mlx5 shared data"); 787 ret = -rte_errno; 788 goto error; 789 } 790 mlx5_shared_data = mz->addr; 791 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 792 } 793 } 794 error: 795 rte_spinlock_unlock(&mlx5_shared_data_lock); 796 return ret; 797 } 798 799 /** 800 * PMD global initialization. 801 * 802 * Independent from individual device, this function initializes global 803 * per-PMD data structures distinguishing primary and secondary processes. 804 * Hence, each initialization is called once per a process. 805 * 806 * @return 807 * 0 on success, a negative errno value otherwise and rte_errno is set. 808 */ 809 static int 810 mlx5_init_once(void) 811 { 812 struct mlx5_shared_data *sd; 813 struct mlx5_local_data *ld = &mlx5_local_data; 814 int ret = 0; 815 816 if (mlx5_init_shared_data()) 817 return -rte_errno; 818 sd = mlx5_shared_data; 819 MLX5_ASSERT(sd); 820 rte_spinlock_lock(&sd->lock); 821 switch (rte_eal_process_type()) { 822 case RTE_PROC_PRIMARY: 823 if (sd->init_done) 824 break; 825 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 826 mlx5_mp_os_primary_handle); 827 if (ret) 828 goto out; 829 sd->init_done = true; 830 break; 831 case RTE_PROC_SECONDARY: 832 if (ld->init_done) 833 break; 834 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 835 mlx5_mp_os_secondary_handle); 836 if (ret) 837 goto out; 838 ++sd->secondary_cnt; 839 ld->init_done = true; 840 break; 841 default: 842 break; 843 } 844 out: 845 rte_spinlock_unlock(&sd->lock); 846 return ret; 847 } 848 849 /** 850 * DR flow drop action support detect. 851 * 852 * @param dev 853 * Pointer to rte_eth_dev structure. 854 * 855 */ 856 static void 857 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 858 { 859 #ifdef HAVE_MLX5DV_DR 860 struct mlx5_priv *priv = dev->data->dev_private; 861 862 if (!priv->sh->config.dv_flow_en || !priv->sh->dr_drop_action) 863 return; 864 /** 865 * DR supports drop action placeholder when it is supported; 866 * otherwise, use the queue drop action. 867 */ 868 if (!priv->sh->drop_action_check_flag) { 869 if (!mlx5_flow_discover_dr_action_support(dev)) 870 priv->sh->dr_drop_action_en = 1; 871 priv->sh->drop_action_check_flag = 1; 872 } 873 if (priv->sh->dr_drop_action_en) 874 priv->root_drop_action = priv->sh->dr_drop_action; 875 else 876 priv->root_drop_action = priv->drop_queue.hrxq->action; 877 #endif 878 } 879 880 static void 881 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 882 { 883 struct mlx5_priv *priv = dev->data->dev_private; 884 void *ctx = priv->sh->cdev->ctx; 885 886 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 887 if (!priv->q_counters) { 888 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 889 struct ibv_wq *wq; 890 891 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 892 "by DevX - fall-back to use the kernel driver global " 893 "queue counter.", dev->data->port_id); 894 /* Create WQ by kernel and query its queue counter ID. */ 895 if (cq) { 896 wq = mlx5_glue->create_wq(ctx, 897 &(struct ibv_wq_init_attr){ 898 .wq_type = IBV_WQT_RQ, 899 .max_wr = 1, 900 .max_sge = 1, 901 .pd = priv->sh->cdev->pd, 902 .cq = cq, 903 }); 904 if (wq) { 905 /* Counter is assigned only on RDY state. */ 906 int ret = mlx5_glue->modify_wq(wq, 907 &(struct ibv_wq_attr){ 908 .attr_mask = IBV_WQ_ATTR_STATE, 909 .wq_state = IBV_WQS_RDY, 910 }); 911 912 if (ret == 0) 913 mlx5_devx_cmd_wq_query(wq, 914 &priv->counter_set_id); 915 claim_zero(mlx5_glue->destroy_wq(wq)); 916 } 917 claim_zero(mlx5_glue->destroy_cq(cq)); 918 } 919 } else { 920 priv->counter_set_id = priv->q_counters->id; 921 } 922 if (priv->counter_set_id == 0) 923 DRV_LOG(INFO, "Part of the port %d statistics will not be " 924 "available.", dev->data->port_id); 925 } 926 927 /** 928 * Check if representor spawn info match devargs. 929 * 930 * @param spawn 931 * Verbs device parameters (name, port, switch_info) to spawn. 932 * @param eth_da 933 * Device devargs to probe. 934 * 935 * @return 936 * Match result. 937 */ 938 static bool 939 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 940 struct rte_eth_devargs *eth_da) 941 { 942 struct mlx5_switch_info *switch_info = &spawn->info; 943 unsigned int p, f; 944 uint16_t id; 945 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 946 eth_da->type); 947 948 switch (eth_da->type) { 949 case RTE_ETH_REPRESENTOR_SF: 950 if (!(spawn->info.port_name == -1 && 951 switch_info->name_type == 952 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 953 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 954 rte_errno = EBUSY; 955 return false; 956 } 957 break; 958 case RTE_ETH_REPRESENTOR_VF: 959 /* Allows HPF representor index -1 as exception. */ 960 if (!(spawn->info.port_name == -1 && 961 switch_info->name_type == 962 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 963 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 964 rte_errno = EBUSY; 965 return false; 966 } 967 break; 968 case RTE_ETH_REPRESENTOR_NONE: 969 rte_errno = EBUSY; 970 return false; 971 default: 972 rte_errno = ENOTSUP; 973 DRV_LOG(ERR, "unsupported representor type"); 974 return false; 975 } 976 /* Check representor ID: */ 977 for (p = 0; p < eth_da->nb_ports; ++p) { 978 if (spawn->pf_bond < 0) { 979 /* For non-LAG mode, allow and ignore pf. */ 980 switch_info->pf_num = eth_da->ports[p]; 981 repr_id = mlx5_representor_id_encode(switch_info, 982 eth_da->type); 983 } 984 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 985 id = MLX5_REPRESENTOR_ID 986 (eth_da->ports[p], eth_da->type, 987 eth_da->representor_ports[f]); 988 if (repr_id == id) 989 return true; 990 } 991 } 992 rte_errno = EBUSY; 993 return false; 994 } 995 996 /** 997 * Spawn an Ethernet device from Verbs information. 998 * 999 * @param dpdk_dev 1000 * Backing DPDK device. 1001 * @param spawn 1002 * Verbs device parameters (name, port, switch_info) to spawn. 1003 * @param config 1004 * Device configuration parameters. 1005 * @param eth_da 1006 * Device arguments. 1007 * 1008 * @return 1009 * A valid Ethernet device object on success, NULL otherwise and rte_errno 1010 * is set. The following errors are defined: 1011 * 1012 * EBUSY: device is not supposed to be spawned. 1013 * EEXIST: device is already spawned 1014 */ 1015 static struct rte_eth_dev * 1016 mlx5_dev_spawn(struct rte_device *dpdk_dev, 1017 struct mlx5_dev_spawn_data *spawn, 1018 struct mlx5_dev_config *config, 1019 struct rte_eth_devargs *eth_da) 1020 { 1021 const struct mlx5_switch_info *switch_info = &spawn->info; 1022 struct mlx5_dev_ctx_shared *sh = NULL; 1023 struct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr; 1024 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; 1025 struct rte_eth_dev *eth_dev = NULL; 1026 struct mlx5_priv *priv = NULL; 1027 int err = 0; 1028 struct rte_ether_addr mac; 1029 char name[RTE_ETH_NAME_MAX_LEN]; 1030 int own_domain_id = 0; 1031 uint16_t port_id; 1032 struct mlx5_port_info vport_info = { .query_flags = 0 }; 1033 int nl_rdma = -1; 1034 int i; 1035 1036 /* Determine if this port representor is supposed to be spawned. */ 1037 if (switch_info->representor && dpdk_dev->devargs && 1038 !mlx5_representor_match(spawn, eth_da)) 1039 return NULL; 1040 /* Build device name. */ 1041 if (spawn->pf_bond < 0) { 1042 /* Single device. */ 1043 if (!switch_info->representor) 1044 strlcpy(name, dpdk_dev->name, sizeof(name)); 1045 else 1046 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 1047 dpdk_dev->name, 1048 switch_info->name_type == 1049 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1050 switch_info->port_name); 1051 } else { 1052 /* Bonding device. */ 1053 if (!switch_info->representor) { 1054 err = snprintf(name, sizeof(name), "%s_%s", 1055 dpdk_dev->name, spawn->phys_dev_name); 1056 } else { 1057 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 1058 dpdk_dev->name, spawn->phys_dev_name, 1059 switch_info->ctrl_num, 1060 switch_info->pf_num, 1061 switch_info->name_type == 1062 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1063 switch_info->port_name); 1064 } 1065 } 1066 if (err >= (int)sizeof(name)) 1067 DRV_LOG(WARNING, "device name overflow %s", name); 1068 /* check if the device is already spawned */ 1069 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1070 rte_errno = EEXIST; 1071 return NULL; 1072 } 1073 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1074 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1075 struct mlx5_mp_id mp_id; 1076 1077 eth_dev = rte_eth_dev_attach_secondary(name); 1078 if (eth_dev == NULL) { 1079 DRV_LOG(ERR, "can not attach rte ethdev"); 1080 rte_errno = ENOMEM; 1081 return NULL; 1082 } 1083 eth_dev->device = dpdk_dev; 1084 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1085 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1086 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1087 err = mlx5_proc_priv_init(eth_dev); 1088 if (err) 1089 return NULL; 1090 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 1091 /* Receive command fd from primary process */ 1092 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 1093 if (err < 0) 1094 goto err_secondary; 1095 /* Remap UAR for Tx queues. */ 1096 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1097 if (err) 1098 goto err_secondary; 1099 /* 1100 * Ethdev pointer is still required as input since 1101 * the primary device is not accessible from the 1102 * secondary process. 1103 */ 1104 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1105 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1106 return eth_dev; 1107 err_secondary: 1108 mlx5_dev_close(eth_dev); 1109 return NULL; 1110 } 1111 /* Process parameters. */ 1112 err = mlx5_args(config, dpdk_dev->devargs); 1113 if (err) { 1114 DRV_LOG(ERR, "failed to process device arguments: %s", 1115 strerror(rte_errno)); 1116 return NULL; 1117 } 1118 sh = mlx5_alloc_shared_dev_ctx(spawn); 1119 if (!sh) 1120 return NULL; 1121 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1122 /* Check port status. */ 1123 if (spawn->phys_port <= UINT8_MAX) { 1124 /* Legacy Verbs api only support u8 port number. */ 1125 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port, 1126 &port_attr); 1127 if (err) { 1128 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1129 goto error; 1130 } 1131 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1132 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1133 err = EINVAL; 1134 goto error; 1135 } 1136 } else if (nl_rdma >= 0) { 1137 /* IB doesn't allow more than 255 ports, must be Ethernet. */ 1138 err = mlx5_nl_port_state(nl_rdma, 1139 spawn->phys_dev_name, 1140 spawn->phys_port); 1141 if (err < 0) { 1142 DRV_LOG(INFO, "Failed to get netlink port state: %s", 1143 strerror(rte_errno)); 1144 err = -rte_errno; 1145 goto error; 1146 } 1147 port_attr.state = (enum ibv_port_state)err; 1148 } 1149 if (port_attr.state != IBV_PORT_ACTIVE) 1150 DRV_LOG(INFO, "port is not active: \"%s\" (%d)", 1151 mlx5_glue->port_state_str(port_attr.state), 1152 port_attr.state); 1153 /* Allocate private eth device data. */ 1154 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1155 sizeof(*priv), 1156 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1157 if (priv == NULL) { 1158 DRV_LOG(ERR, "priv allocation failure"); 1159 err = ENOMEM; 1160 goto error; 1161 } 1162 priv->sh = sh; 1163 priv->dev_port = spawn->phys_port; 1164 priv->pci_dev = spawn->pci_dev; 1165 priv->mtu = RTE_ETHER_MTU; 1166 /* Some internal functions rely on Netlink sockets, open them now. */ 1167 priv->nl_socket_rdma = nl_rdma; 1168 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1169 priv->representor = !!switch_info->representor; 1170 priv->master = !!switch_info->master; 1171 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1172 priv->vport_meta_tag = 0; 1173 priv->vport_meta_mask = 0; 1174 priv->pf_bond = spawn->pf_bond; 1175 1176 DRV_LOG(DEBUG, 1177 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1178 priv->dev_port, dpdk_dev->bus->name, 1179 priv->pci_dev ? priv->pci_dev->name : "NONE", 1180 priv->master, priv->representor, priv->pf_bond); 1181 1182 /* 1183 * If we have E-Switch we should determine the vport attributes. 1184 * E-Switch may use either source vport field or reg_c[0] metadata 1185 * register to match on vport index. The engaged part of metadata 1186 * register is defined by mask. 1187 */ 1188 if (sh->esw_mode) { 1189 err = mlx5_glue->devx_port_query(sh->cdev->ctx, 1190 spawn->phys_port, 1191 &vport_info); 1192 if (err) { 1193 DRV_LOG(WARNING, 1194 "Cannot query devx port %d on device %s", 1195 spawn->phys_port, spawn->phys_dev_name); 1196 vport_info.query_flags = 0; 1197 } 1198 } 1199 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1200 priv->vport_meta_tag = vport_info.vport_meta_tag; 1201 priv->vport_meta_mask = vport_info.vport_meta_mask; 1202 if (!priv->vport_meta_mask) { 1203 DRV_LOG(ERR, 1204 "vport zero mask for port %d on bonding device %s", 1205 spawn->phys_port, spawn->phys_dev_name); 1206 err = ENOTSUP; 1207 goto error; 1208 } 1209 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1210 DRV_LOG(ERR, 1211 "Invalid vport tag for port %d on bonding device %s", 1212 spawn->phys_port, spawn->phys_dev_name); 1213 err = ENOTSUP; 1214 goto error; 1215 } 1216 } 1217 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1218 priv->vport_id = vport_info.vport_id; 1219 } else if (spawn->pf_bond >= 0 && sh->esw_mode) { 1220 DRV_LOG(ERR, 1221 "Cannot deduce vport index for port %d on bonding device %s", 1222 spawn->phys_port, spawn->phys_dev_name); 1223 err = ENOTSUP; 1224 goto error; 1225 } else { 1226 /* 1227 * Suppose vport index in compatible way. Kernel/rdma_core 1228 * support single E-Switch per PF configurations only and 1229 * vport_id field contains the vport index for associated VF, 1230 * which is deduced from representor port name. 1231 * For example, let's have the IB device port 10, it has 1232 * attached network device eth0, which has port name attribute 1233 * pf0vf2, we can deduce the VF number as 2, and set vport index 1234 * as 3 (2+1). This assigning schema should be changed if the 1235 * multiple E-Switch instances per PF configurations or/and PCI 1236 * subfunctions are added. 1237 */ 1238 priv->vport_id = switch_info->representor ? 1239 switch_info->port_name + 1 : -1; 1240 } 1241 priv->representor_id = mlx5_representor_id_encode(switch_info, 1242 eth_da->type); 1243 /* 1244 * Look for sibling devices in order to reuse their switch domain 1245 * if any, otherwise allocate one. 1246 */ 1247 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1248 const struct mlx5_priv *opriv = 1249 rte_eth_devices[port_id].data->dev_private; 1250 1251 if (!opriv || 1252 opriv->sh != priv->sh || 1253 opriv->domain_id == 1254 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1255 continue; 1256 priv->domain_id = opriv->domain_id; 1257 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1258 priv->dev_port, priv->domain_id); 1259 break; 1260 } 1261 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1262 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1263 if (err) { 1264 err = rte_errno; 1265 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1266 strerror(rte_errno)); 1267 goto error; 1268 } 1269 own_domain_id = 1; 1270 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1271 priv->dev_port, priv->domain_id); 1272 } 1273 if (config->hw_padding && !sh->dev_cap.hw_padding) { 1274 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1275 config->hw_padding = 0; 1276 } else if (config->hw_padding) { 1277 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1278 } 1279 /* 1280 * MPW is disabled by default, while the Enhanced MPW is enabled 1281 * by default. 1282 */ 1283 if (config->mps == MLX5_ARG_UNSET) 1284 config->mps = (sh->dev_cap.mps == MLX5_MPW_ENHANCED) ? 1285 MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED; 1286 else 1287 config->mps = config->mps ? sh->dev_cap.mps : MLX5_MPW_DISABLED; 1288 DRV_LOG(INFO, "%sMPS is %s", 1289 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1290 config->mps == MLX5_MPW ? "legacy " : "", 1291 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1292 if (sh->cdev->config.devx) { 1293 sh->steering_format_version = hca_attr->steering_format_version; 1294 /* LRO is supported only when DV flow enabled. */ 1295 if (sh->dev_cap.lro_supported && sh->config.dv_flow_en) 1296 sh->dev_cap.lro_supported = 0; 1297 if (sh->dev_cap.lro_supported) { 1298 /* 1299 * If LRO timeout is not configured by application, 1300 * use the minimal supported value. 1301 */ 1302 if (!config->lro_timeout) 1303 config->lro_timeout = 1304 hca_attr->lro_timer_supported_periods[0]; 1305 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1306 config->lro_timeout); 1307 } 1308 #if defined(HAVE_MLX5DV_DR) && \ 1309 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1310 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1311 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_old && 1312 sh->config.dv_flow_en) { 1313 uint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids; 1314 /* 1315 * Meter needs two REG_C's for color match and pre-sfx 1316 * flow match. Here get the REG_C for color match. 1317 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1318 */ 1319 reg_c_mask &= 0xfc; 1320 if (__builtin_popcount(reg_c_mask) < 1) { 1321 priv->mtr_en = 0; 1322 DRV_LOG(WARNING, "No available register for" 1323 " meter."); 1324 } else { 1325 /* 1326 * The meter color register is used by the 1327 * flow-hit feature as well. 1328 * The flow-hit feature must use REG_C_3 1329 * Prefer REG_C_3 if it is available. 1330 */ 1331 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1332 priv->mtr_color_reg = REG_C_3; 1333 else 1334 priv->mtr_color_reg = ffs(reg_c_mask) 1335 - 1 + REG_C_0; 1336 priv->mtr_en = 1; 1337 priv->mtr_reg_share = hca_attr->qos.flow_meter; 1338 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1339 priv->mtr_color_reg); 1340 } 1341 } 1342 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) { 1343 uint32_t log_obj_size = 1344 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1345 if (log_obj_size >= 1346 hca_attr->qos.log_meter_aso_granularity && 1347 log_obj_size <= 1348 hca_attr->qos.log_meter_aso_max_alloc) 1349 sh->meter_aso_en = 1; 1350 } 1351 if (priv->mtr_en) { 1352 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1353 if (err) { 1354 err = -err; 1355 goto error; 1356 } 1357 } 1358 if (hca_attr->flow.tunnel_header_0_1) 1359 sh->tunnel_header_0_1 = 1; 1360 #endif 1361 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1362 if (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) { 1363 sh->flow_hit_aso_en = 1; 1364 err = mlx5_flow_aso_age_mng_init(sh); 1365 if (err) { 1366 err = -err; 1367 goto error; 1368 } 1369 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1370 } 1371 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1372 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1373 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1374 if (hca_attr->ct_offload && priv->mtr_color_reg == REG_C_3) { 1375 err = mlx5_flow_aso_ct_mng_init(sh); 1376 if (err) { 1377 err = -err; 1378 goto error; 1379 } 1380 DRV_LOG(DEBUG, "CT ASO is supported."); 1381 sh->ct_aso_en = 1; 1382 } 1383 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1384 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1385 if (hca_attr->log_max_ft_sampler_num > 0 && 1386 sh->config.dv_flow_en) { 1387 priv->sampler_en = 1; 1388 DRV_LOG(DEBUG, "Sampler enabled!"); 1389 } else { 1390 priv->sampler_en = 0; 1391 if (!hca_attr->log_max_ft_sampler_num) 1392 DRV_LOG(WARNING, 1393 "No available register for sampler."); 1394 else 1395 DRV_LOG(DEBUG, "DV flow is not supported!"); 1396 } 1397 #endif 1398 } 1399 if (config->cqe_comp && !sh->dev_cap.cqe_comp) { 1400 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported."); 1401 config->cqe_comp = 0; 1402 } 1403 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1404 (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_flow_tag)) { 1405 DRV_LOG(WARNING, "Flow Tag CQE compression" 1406 " format isn't supported."); 1407 config->cqe_comp = 0; 1408 } 1409 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1410 (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { 1411 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1412 " format isn't supported."); 1413 config->cqe_comp = 0; 1414 } 1415 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1416 config->cqe_comp ? "" : "not "); 1417 if (config->std_delay_drop || config->hp_delay_drop) { 1418 if (!hca_attr->rq_delay_drop) { 1419 config->std_delay_drop = 0; 1420 config->hp_delay_drop = 0; 1421 DRV_LOG(WARNING, 1422 "dev_port-%u: Rxq delay drop is not supported", 1423 priv->dev_port); 1424 } 1425 } 1426 if (config->mprq.enabled && !sh->dev_cap.mprq.enabled) { 1427 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported."); 1428 config->mprq.enabled = 0; 1429 } 1430 if (config->max_dump_files_num == 0) 1431 config->max_dump_files_num = 128; 1432 eth_dev = rte_eth_dev_allocate(name); 1433 if (eth_dev == NULL) { 1434 DRV_LOG(ERR, "can not allocate rte ethdev"); 1435 err = ENOMEM; 1436 goto error; 1437 } 1438 if (priv->representor) { 1439 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1440 eth_dev->data->representor_id = priv->representor_id; 1441 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1442 struct mlx5_priv *opriv = 1443 rte_eth_devices[port_id].data->dev_private; 1444 if (opriv && 1445 opriv->master && 1446 opriv->domain_id == priv->domain_id && 1447 opriv->sh == priv->sh) { 1448 eth_dev->data->backer_port_id = port_id; 1449 break; 1450 } 1451 } 1452 if (port_id >= RTE_MAX_ETHPORTS) 1453 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1454 } 1455 priv->mp_id.port_id = eth_dev->data->port_id; 1456 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1457 /* 1458 * Store associated network device interface index. This index 1459 * is permanent throughout the lifetime of device. So, we may store 1460 * the ifindex here and use the cached value further. 1461 */ 1462 MLX5_ASSERT(spawn->ifindex); 1463 priv->if_index = spawn->ifindex; 1464 priv->lag_affinity_idx = sh->refcnt - 1; 1465 eth_dev->data->dev_private = priv; 1466 priv->dev_data = eth_dev->data; 1467 eth_dev->data->mac_addrs = priv->mac; 1468 eth_dev->device = dpdk_dev; 1469 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1470 /* Configure the first MAC address by default. */ 1471 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1472 DRV_LOG(ERR, 1473 "port %u cannot get MAC address, is mlx5_en" 1474 " loaded? (errno: %s)", 1475 eth_dev->data->port_id, strerror(rte_errno)); 1476 err = ENODEV; 1477 goto error; 1478 } 1479 DRV_LOG(INFO, 1480 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1481 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1482 #ifdef RTE_LIBRTE_MLX5_DEBUG 1483 { 1484 char ifname[MLX5_NAMESIZE]; 1485 1486 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1487 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1488 eth_dev->data->port_id, ifname); 1489 else 1490 DRV_LOG(DEBUG, "port %u ifname is unknown", 1491 eth_dev->data->port_id); 1492 } 1493 #endif 1494 /* Get actual MTU if possible. */ 1495 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1496 if (err) { 1497 err = rte_errno; 1498 goto error; 1499 } 1500 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1501 priv->mtu); 1502 /* Initialize burst functions to prevent crashes before link-up. */ 1503 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 1504 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 1505 eth_dev->dev_ops = &mlx5_dev_ops; 1506 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1507 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1508 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1509 /* Register MAC address. */ 1510 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1511 if (sh->dev_cap.vf && sh->config.vf_nl_en) 1512 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1513 mlx5_ifindex(eth_dev), 1514 eth_dev->data->mac_addrs, 1515 MLX5_MAX_MAC_ADDRESSES); 1516 priv->ctrl_flows = 0; 1517 rte_spinlock_init(&priv->flow_list_lock); 1518 TAILQ_INIT(&priv->flow_meters); 1519 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1520 if (!priv->mtr_profile_tbl) 1521 goto error; 1522 /* Bring Ethernet device up. */ 1523 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1524 eth_dev->data->port_id); 1525 mlx5_set_link_up(eth_dev); 1526 /* 1527 * Even though the interrupt handler is not installed yet, 1528 * interrupts will still trigger on the async_fd from 1529 * Verbs context returned by ibv_open_device(). 1530 */ 1531 mlx5_link_update(eth_dev, 0); 1532 /* Detect minimal data bytes to inline. */ 1533 mlx5_set_min_inline(spawn, config); 1534 /* Store device configuration on private structure. */ 1535 priv->config = *config; 1536 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1537 icfg[i].release_mem_en = !!sh->config.reclaim_mode; 1538 if (sh->config.reclaim_mode) 1539 icfg[i].per_core_cache = 0; 1540 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1541 if (!priv->flows[i]) 1542 goto error; 1543 } 1544 /* Create context for virtual machine VLAN workaround. */ 1545 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1546 if (sh->config.dv_flow_en) { 1547 err = mlx5_alloc_shared_dr(priv); 1548 if (err) 1549 goto error; 1550 if (mlx5_flex_item_port_init(eth_dev) < 0) 1551 goto error; 1552 } 1553 if (sh->cdev->config.devx && sh->config.dv_flow_en && 1554 sh->dev_cap.dest_tir) { 1555 priv->obj_ops = devx_obj_ops; 1556 mlx5_queue_counter_id_prepare(eth_dev); 1557 priv->obj_ops.lb_dummy_queue_create = 1558 mlx5_rxq_ibv_obj_dummy_lb_create; 1559 priv->obj_ops.lb_dummy_queue_release = 1560 mlx5_rxq_ibv_obj_dummy_lb_release; 1561 } else if (spawn->max_port > UINT8_MAX) { 1562 /* Verbs can't support ports larger than 255 by design. */ 1563 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); 1564 err = ENOTSUP; 1565 goto error; 1566 } else { 1567 priv->obj_ops = ibv_obj_ops; 1568 } 1569 if (sh->config.tx_pp && 1570 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new) { 1571 /* 1572 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1573 * packet pacing and already checked above. 1574 * Hence, we should only make sure the SQs will be created 1575 * with DevX, not with Verbs. 1576 * Verbs allocates the SQ UAR on its own and it can't be shared 1577 * with Clock Queue UAR as required for Tx scheduling. 1578 */ 1579 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1580 err = ENODEV; 1581 goto error; 1582 } 1583 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1584 if (!priv->drop_queue.hrxq) 1585 goto error; 1586 /* Port representor shares the same max priority with pf port. */ 1587 if (!priv->sh->flow_priority_check_flag) { 1588 /* Supported Verbs flow priority number detection. */ 1589 err = mlx5_flow_discover_priorities(eth_dev); 1590 priv->sh->flow_max_priority = err; 1591 priv->sh->flow_priority_check_flag = 1; 1592 } else { 1593 err = priv->sh->flow_max_priority; 1594 } 1595 if (err < 0) { 1596 err = -err; 1597 goto error; 1598 } 1599 mlx5_set_metadata_mask(eth_dev); 1600 if (sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1601 !priv->sh->dv_regc0_mask) { 1602 DRV_LOG(ERR, "metadata mode %u is not supported " 1603 "(no metadata reg_c[0] is available)", 1604 sh->config.dv_xmeta_en); 1605 err = ENOTSUP; 1606 goto error; 1607 } 1608 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1609 mlx5_hrxq_create_cb, 1610 mlx5_hrxq_match_cb, 1611 mlx5_hrxq_remove_cb, 1612 mlx5_hrxq_clone_cb, 1613 mlx5_hrxq_clone_free_cb); 1614 if (!priv->hrxqs) 1615 goto error; 1616 rte_rwlock_init(&priv->ind_tbls_lock); 1617 /* Query availability of metadata reg_c's. */ 1618 if (!priv->sh->metadata_regc_check_flag) { 1619 err = mlx5_flow_discover_mreg_c(eth_dev); 1620 if (err < 0) { 1621 err = -err; 1622 goto error; 1623 } 1624 } 1625 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1626 DRV_LOG(DEBUG, 1627 "port %u extensive metadata register is not supported", 1628 eth_dev->data->port_id); 1629 if (sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1630 DRV_LOG(ERR, "metadata mode %u is not supported " 1631 "(no metadata registers available)", 1632 sh->config.dv_xmeta_en); 1633 err = ENOTSUP; 1634 goto error; 1635 } 1636 } 1637 if (sh->config.dv_flow_en && 1638 sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1639 mlx5_flow_ext_mreg_supported(eth_dev) && 1640 priv->sh->dv_regc0_mask) { 1641 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1642 MLX5_FLOW_MREG_HTABLE_SZ, 1643 false, true, eth_dev, 1644 flow_dv_mreg_create_cb, 1645 flow_dv_mreg_match_cb, 1646 flow_dv_mreg_remove_cb, 1647 flow_dv_mreg_clone_cb, 1648 flow_dv_mreg_clone_free_cb); 1649 if (!priv->mreg_cp_tbl) { 1650 err = ENOMEM; 1651 goto error; 1652 } 1653 } 1654 rte_spinlock_init(&priv->shared_act_sl); 1655 mlx5_flow_counter_mode_config(eth_dev); 1656 mlx5_flow_drop_action_config(eth_dev); 1657 if (sh->config.dv_flow_en) 1658 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1659 return eth_dev; 1660 error: 1661 if (priv) { 1662 if (priv->mreg_cp_tbl) 1663 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1664 if (priv->sh) 1665 mlx5_os_free_shared_dr(priv); 1666 if (priv->nl_socket_route >= 0) 1667 close(priv->nl_socket_route); 1668 if (priv->vmwa_context) 1669 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1670 if (eth_dev && priv->drop_queue.hrxq) 1671 mlx5_drop_action_destroy(eth_dev); 1672 if (priv->mtr_profile_tbl) 1673 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1674 if (own_domain_id) 1675 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1676 if (priv->hrxqs) 1677 mlx5_list_destroy(priv->hrxqs); 1678 if (eth_dev && priv->flex_item_map) 1679 mlx5_flex_item_port_cleanup(eth_dev); 1680 mlx5_free(priv); 1681 if (eth_dev != NULL) 1682 eth_dev->data->dev_private = NULL; 1683 } 1684 if (eth_dev != NULL) { 1685 /* mac_addrs must not be freed alone because part of 1686 * dev_private 1687 **/ 1688 eth_dev->data->mac_addrs = NULL; 1689 rte_eth_dev_release_port(eth_dev); 1690 } 1691 if (sh) 1692 mlx5_free_shared_dev_ctx(sh); 1693 if (nl_rdma >= 0) 1694 close(nl_rdma); 1695 MLX5_ASSERT(err > 0); 1696 rte_errno = err; 1697 return NULL; 1698 } 1699 1700 /** 1701 * Comparison callback to sort device data. 1702 * 1703 * This is meant to be used with qsort(). 1704 * 1705 * @param a[in] 1706 * Pointer to pointer to first data object. 1707 * @param b[in] 1708 * Pointer to pointer to second data object. 1709 * 1710 * @return 1711 * 0 if both objects are equal, less than 0 if the first argument is less 1712 * than the second, greater than 0 otherwise. 1713 */ 1714 static int 1715 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1716 { 1717 const struct mlx5_switch_info *si_a = 1718 &((const struct mlx5_dev_spawn_data *)a)->info; 1719 const struct mlx5_switch_info *si_b = 1720 &((const struct mlx5_dev_spawn_data *)b)->info; 1721 int ret; 1722 1723 /* Master device first. */ 1724 ret = si_b->master - si_a->master; 1725 if (ret) 1726 return ret; 1727 /* Then representor devices. */ 1728 ret = si_b->representor - si_a->representor; 1729 if (ret) 1730 return ret; 1731 /* Unidentified devices come last in no specific order. */ 1732 if (!si_a->representor) 1733 return 0; 1734 /* Order representors by name. */ 1735 return si_a->port_name - si_b->port_name; 1736 } 1737 1738 /** 1739 * Match PCI information for possible slaves of bonding device. 1740 * 1741 * @param[in] ibdev_name 1742 * Name of Infiniband device. 1743 * @param[in] pci_dev 1744 * Pointer to primary PCI address structure to match. 1745 * @param[in] nl_rdma 1746 * Netlink RDMA group socket handle. 1747 * @param[in] owner 1748 * Representor owner PF index. 1749 * @param[out] bond_info 1750 * Pointer to bonding information. 1751 * 1752 * @return 1753 * negative value if no bonding device found, otherwise 1754 * positive index of slave PF in bonding. 1755 */ 1756 static int 1757 mlx5_device_bond_pci_match(const char *ibdev_name, 1758 const struct rte_pci_addr *pci_dev, 1759 int nl_rdma, uint16_t owner, 1760 struct mlx5_bond_info *bond_info) 1761 { 1762 char ifname[IF_NAMESIZE + 1]; 1763 unsigned int ifindex; 1764 unsigned int np, i; 1765 FILE *bond_file = NULL, *file; 1766 int pf = -1; 1767 int ret; 1768 uint8_t cur_guid[32] = {0}; 1769 uint8_t guid[32] = {0}; 1770 1771 /* 1772 * Try to get master device name. If something goes wrong suppose 1773 * the lack of kernel support and no bonding devices. 1774 */ 1775 memset(bond_info, 0, sizeof(*bond_info)); 1776 if (nl_rdma < 0) 1777 return -1; 1778 if (!strstr(ibdev_name, "bond")) 1779 return -1; 1780 np = mlx5_nl_portnum(nl_rdma, ibdev_name); 1781 if (!np) 1782 return -1; 1783 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) 1784 return -1; 1785 /* 1786 * The master device might not be on the predefined port(not on port 1787 * index 1, it is not guaranteed), we have to scan all Infiniband 1788 * device ports and find master. 1789 */ 1790 for (i = 1; i <= np; ++i) { 1791 /* Check whether Infiniband port is populated. */ 1792 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); 1793 if (!ifindex) 1794 continue; 1795 if (!if_indextoname(ifindex, ifname)) 1796 continue; 1797 /* Try to read bonding slave names from sysfs. */ 1798 MKSTR(slaves, 1799 "/sys/class/net/%s/master/bonding/slaves", ifname); 1800 bond_file = fopen(slaves, "r"); 1801 if (bond_file) 1802 break; 1803 } 1804 if (!bond_file) 1805 return -1; 1806 /* Use safe format to check maximal buffer length. */ 1807 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1808 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1809 char tmp_str[IF_NAMESIZE + 32]; 1810 struct rte_pci_addr pci_addr; 1811 struct mlx5_switch_info info; 1812 int ret; 1813 1814 /* Process slave interface names in the loop. */ 1815 snprintf(tmp_str, sizeof(tmp_str), 1816 "/sys/class/net/%s", ifname); 1817 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 1818 DRV_LOG(WARNING, 1819 "Cannot get PCI address for netdev \"%s\".", 1820 ifname); 1821 continue; 1822 } 1823 /* Slave interface PCI address match found. */ 1824 snprintf(tmp_str, sizeof(tmp_str), 1825 "/sys/class/net/%s/phys_port_name", ifname); 1826 file = fopen(tmp_str, "rb"); 1827 if (!file) 1828 break; 1829 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1830 if (fscanf(file, "%32s", tmp_str) == 1) 1831 mlx5_translate_port_name(tmp_str, &info); 1832 fclose(file); 1833 /* Only process PF ports. */ 1834 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1835 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1836 continue; 1837 /* Check max bonding member. */ 1838 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1839 DRV_LOG(WARNING, "bonding index out of range, " 1840 "please increase MLX5_BOND_MAX_PORTS: %s", 1841 tmp_str); 1842 break; 1843 } 1844 /* Get ifindex. */ 1845 snprintf(tmp_str, sizeof(tmp_str), 1846 "/sys/class/net/%s/ifindex", ifname); 1847 file = fopen(tmp_str, "rb"); 1848 if (!file) 1849 break; 1850 ret = fscanf(file, "%u", &ifindex); 1851 fclose(file); 1852 if (ret != 1) 1853 break; 1854 /* Save bonding info. */ 1855 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1856 sizeof(bond_info->ports[0].ifname)); 1857 bond_info->ports[info.port_name].pci_addr = pci_addr; 1858 bond_info->ports[info.port_name].ifindex = ifindex; 1859 bond_info->n_port++; 1860 /* 1861 * Under socket direct mode, bonding will use 1862 * system_image_guid as identification. 1863 * After OFED 5.4, guid is readable (ret >= 0) under sysfs. 1864 * All bonding members should have the same guid even if driver 1865 * is using PCIe BDF. 1866 */ 1867 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid)); 1868 if (ret < 0) 1869 break; 1870 else if (ret > 0) { 1871 if (!memcmp(guid, cur_guid, sizeof(guid)) && 1872 owner == info.port_name && 1873 (owner != 0 || (owner == 0 && 1874 !rte_pci_addr_cmp(pci_dev, &pci_addr)))) 1875 pf = info.port_name; 1876 } else if (pci_dev->domain == pci_addr.domain && 1877 pci_dev->bus == pci_addr.bus && 1878 pci_dev->devid == pci_addr.devid && 1879 ((pci_dev->function == 0 && 1880 pci_dev->function + owner == pci_addr.function) || 1881 (pci_dev->function == owner && 1882 pci_addr.function == owner))) 1883 pf = info.port_name; 1884 } 1885 if (pf >= 0) { 1886 /* Get bond interface info */ 1887 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 1888 bond_info->ifname); 1889 if (ret) 1890 DRV_LOG(ERR, "unable to get bond info: %s", 1891 strerror(rte_errno)); 1892 else 1893 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1894 ifindex, bond_info->ifindex, bond_info->ifname); 1895 } 1896 if (owner == 0 && pf != 0) { 1897 DRV_LOG(INFO, "PCIe instance %04x:%02x:%02x.%x isn't bonding owner", 1898 pci_dev->domain, pci_dev->bus, pci_dev->devid, 1899 pci_dev->function); 1900 } 1901 return pf; 1902 } 1903 1904 static void 1905 mlx5_os_config_default(struct mlx5_dev_config *config) 1906 { 1907 memset(config, 0, sizeof(*config)); 1908 config->mps = MLX5_ARG_UNSET; 1909 config->cqe_comp = 1; 1910 config->rx_vec_en = 1; 1911 config->txq_inline_max = MLX5_ARG_UNSET; 1912 config->txq_inline_min = MLX5_ARG_UNSET; 1913 config->txq_inline_mpw = MLX5_ARG_UNSET; 1914 config->txqs_inline = MLX5_ARG_UNSET; 1915 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 1916 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 1917 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; 1918 config->log_hp_size = MLX5_ARG_UNSET; 1919 config->std_delay_drop = 0; 1920 config->hp_delay_drop = 0; 1921 } 1922 1923 /** 1924 * Register a PCI device within bonding. 1925 * 1926 * This function spawns Ethernet devices out of a given PCI device and 1927 * bonding owner PF index. 1928 * 1929 * @param[in] cdev 1930 * Pointer to common mlx5 device structure. 1931 * @param[in] req_eth_da 1932 * Requested ethdev device argument. 1933 * @param[in] owner_id 1934 * Requested owner PF port ID within bonding device, default to 0. 1935 * 1936 * @return 1937 * 0 on success, a negative errno value otherwise and rte_errno is set. 1938 */ 1939 static int 1940 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, 1941 struct rte_eth_devargs *req_eth_da, 1942 uint16_t owner_id) 1943 { 1944 struct ibv_device **ibv_list; 1945 /* 1946 * Number of found IB Devices matching with requested PCI BDF. 1947 * nd != 1 means there are multiple IB devices over the same 1948 * PCI device and we have representors and master. 1949 */ 1950 unsigned int nd = 0; 1951 /* 1952 * Number of found IB device Ports. nd = 1 and np = 1..n means 1953 * we have the single multiport IB device, and there may be 1954 * representors attached to some of found ports. 1955 */ 1956 unsigned int np = 0; 1957 /* 1958 * Number of DPDK ethernet devices to Spawn - either over 1959 * multiple IB devices or multiple ports of single IB device. 1960 * Actually this is the number of iterations to spawn. 1961 */ 1962 unsigned int ns = 0; 1963 /* 1964 * Bonding device 1965 * < 0 - no bonding device (single one) 1966 * >= 0 - bonding device (value is slave PF index) 1967 */ 1968 int bd = -1; 1969 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 1970 struct mlx5_dev_spawn_data *list = NULL; 1971 struct mlx5_dev_config dev_config; 1972 struct rte_eth_devargs eth_da = *req_eth_da; 1973 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 1974 struct mlx5_bond_info bond_info; 1975 int ret = -1; 1976 1977 errno = 0; 1978 ibv_list = mlx5_glue->get_device_list(&ret); 1979 if (!ibv_list) { 1980 rte_errno = errno ? errno : ENOSYS; 1981 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?"); 1982 return -rte_errno; 1983 } 1984 /* 1985 * First scan the list of all Infiniband devices to find 1986 * matching ones, gathering into the list. 1987 */ 1988 struct ibv_device *ibv_match[ret + 1]; 1989 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1990 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1991 unsigned int i; 1992 1993 while (ret-- > 0) { 1994 struct rte_pci_addr pci_addr; 1995 1996 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); 1997 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, 1998 nl_rdma, owner_id, &bond_info); 1999 if (bd >= 0) { 2000 /* 2001 * Bonding device detected. Only one match is allowed, 2002 * the bonding is supported over multi-port IB device, 2003 * there should be no matches on representor PCI 2004 * functions or non VF LAG bonding devices with 2005 * specified address. 2006 */ 2007 if (nd) { 2008 DRV_LOG(ERR, 2009 "multiple PCI match on bonding device" 2010 "\"%s\" found", ibv_list[ret]->name); 2011 rte_errno = ENOENT; 2012 ret = -rte_errno; 2013 goto exit; 2014 } 2015 /* Amend owner pci address if owner PF ID specified. */ 2016 if (eth_da.nb_representor_ports) 2017 owner_pci.function += owner_id; 2018 DRV_LOG(INFO, 2019 "PCI information matches for slave %d bonding device \"%s\"", 2020 bd, ibv_list[ret]->name); 2021 ibv_match[nd++] = ibv_list[ret]; 2022 break; 2023 } else { 2024 /* Bonding device not found. */ 2025 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2026 &pci_addr)) 2027 continue; 2028 if (owner_pci.domain != pci_addr.domain || 2029 owner_pci.bus != pci_addr.bus || 2030 owner_pci.devid != pci_addr.devid || 2031 owner_pci.function != pci_addr.function) 2032 continue; 2033 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2034 ibv_list[ret]->name); 2035 ibv_match[nd++] = ibv_list[ret]; 2036 } 2037 } 2038 ibv_match[nd] = NULL; 2039 if (!nd) { 2040 /* No device matches, just complain and bail out. */ 2041 DRV_LOG(WARNING, 2042 "No Verbs device matches PCI device " PCI_PRI_FMT "," 2043 " are kernel drivers loaded?", 2044 owner_pci.domain, owner_pci.bus, 2045 owner_pci.devid, owner_pci.function); 2046 rte_errno = ENOENT; 2047 ret = -rte_errno; 2048 goto exit; 2049 } 2050 if (nd == 1) { 2051 /* 2052 * Found single matching device may have multiple ports. 2053 * Each port may be representor, we have to check the port 2054 * number and check the representors existence. 2055 */ 2056 if (nl_rdma >= 0) 2057 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2058 if (!np) 2059 DRV_LOG(WARNING, 2060 "Cannot get IB device \"%s\" ports number.", 2061 ibv_match[0]->name); 2062 if (bd >= 0 && !np) { 2063 DRV_LOG(ERR, "Cannot get ports for bonding device."); 2064 rte_errno = ENOENT; 2065 ret = -rte_errno; 2066 goto exit; 2067 } 2068 } 2069 /* Now we can determine the maximal amount of devices to be spawned. */ 2070 list = mlx5_malloc(MLX5_MEM_ZERO, 2071 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd), 2072 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2073 if (!list) { 2074 DRV_LOG(ERR, "Spawn data array allocation failure."); 2075 rte_errno = ENOMEM; 2076 ret = -rte_errno; 2077 goto exit; 2078 } 2079 if (bd >= 0 || np > 1) { 2080 /* 2081 * Single IB device with multiple ports found, 2082 * it may be E-Switch master device and representors. 2083 * We have to perform identification through the ports. 2084 */ 2085 MLX5_ASSERT(nl_rdma >= 0); 2086 MLX5_ASSERT(ns == 0); 2087 MLX5_ASSERT(nd == 1); 2088 MLX5_ASSERT(np); 2089 for (i = 1; i <= np; ++i) { 2090 list[ns].bond_info = &bond_info; 2091 list[ns].max_port = np; 2092 list[ns].phys_port = i; 2093 list[ns].phys_dev_name = ibv_match[0]->name; 2094 list[ns].eth_dev = NULL; 2095 list[ns].pci_dev = pci_dev; 2096 list[ns].cdev = cdev; 2097 list[ns].pf_bond = bd; 2098 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, 2099 ibv_match[0]->name, 2100 i); 2101 if (!list[ns].ifindex) { 2102 /* 2103 * No network interface index found for the 2104 * specified port, it means there is no 2105 * representor on this port. It's OK, 2106 * there can be disabled ports, for example 2107 * if sriov_numvfs < sriov_totalvfs. 2108 */ 2109 continue; 2110 } 2111 ret = -1; 2112 if (nl_route >= 0) 2113 ret = mlx5_nl_switch_info(nl_route, 2114 list[ns].ifindex, 2115 &list[ns].info); 2116 if (ret || (!list[ns].info.representor && 2117 !list[ns].info.master)) { 2118 /* 2119 * We failed to recognize representors with 2120 * Netlink, let's try to perform the task 2121 * with sysfs. 2122 */ 2123 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2124 &list[ns].info); 2125 } 2126 if (!ret && bd >= 0) { 2127 switch (list[ns].info.name_type) { 2128 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2129 if (np == 1) { 2130 /* 2131 * Force standalone bonding 2132 * device for ROCE LAG 2133 * configurations. 2134 */ 2135 list[ns].info.master = 0; 2136 list[ns].info.representor = 0; 2137 } 2138 if (list[ns].info.port_name == bd) 2139 ns++; 2140 break; 2141 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2142 /* Fallthrough */ 2143 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2144 /* Fallthrough */ 2145 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2146 if (list[ns].info.pf_num == bd) 2147 ns++; 2148 break; 2149 default: 2150 break; 2151 } 2152 continue; 2153 } 2154 if (!ret && (list[ns].info.representor ^ 2155 list[ns].info.master)) 2156 ns++; 2157 } 2158 if (!ns) { 2159 DRV_LOG(ERR, 2160 "Unable to recognize master/representors on the IB device with multiple ports."); 2161 rte_errno = ENOENT; 2162 ret = -rte_errno; 2163 goto exit; 2164 } 2165 } else { 2166 /* 2167 * The existence of several matching entries (nd > 1) means 2168 * port representors have been instantiated. No existing Verbs 2169 * call nor sysfs entries can tell them apart, this can only 2170 * be done through Netlink calls assuming kernel drivers are 2171 * recent enough to support them. 2172 * 2173 * In the event of identification failure through Netlink, 2174 * try again through sysfs, then: 2175 * 2176 * 1. A single IB device matches (nd == 1) with single 2177 * port (np=0/1) and is not a representor, assume 2178 * no switch support. 2179 * 2180 * 2. Otherwise no safe assumptions can be made; 2181 * complain louder and bail out. 2182 */ 2183 for (i = 0; i != nd; ++i) { 2184 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2185 list[ns].bond_info = NULL; 2186 list[ns].max_port = 1; 2187 list[ns].phys_port = 1; 2188 list[ns].phys_dev_name = ibv_match[i]->name; 2189 list[ns].eth_dev = NULL; 2190 list[ns].pci_dev = pci_dev; 2191 list[ns].cdev = cdev; 2192 list[ns].pf_bond = -1; 2193 list[ns].ifindex = 0; 2194 if (nl_rdma >= 0) 2195 list[ns].ifindex = mlx5_nl_ifindex 2196 (nl_rdma, 2197 ibv_match[i]->name, 2198 1); 2199 if (!list[ns].ifindex) { 2200 char ifname[IF_NAMESIZE]; 2201 2202 /* 2203 * Netlink failed, it may happen with old 2204 * ib_core kernel driver (before 4.16). 2205 * We can assume there is old driver because 2206 * here we are processing single ports IB 2207 * devices. Let's try sysfs to retrieve 2208 * the ifindex. The method works for 2209 * master device only. 2210 */ 2211 if (nd > 1) { 2212 /* 2213 * Multiple devices found, assume 2214 * representors, can not distinguish 2215 * master/representor and retrieve 2216 * ifindex via sysfs. 2217 */ 2218 continue; 2219 } 2220 ret = mlx5_get_ifname_sysfs 2221 (ibv_match[i]->ibdev_path, ifname); 2222 if (!ret) 2223 list[ns].ifindex = 2224 if_nametoindex(ifname); 2225 if (!list[ns].ifindex) { 2226 /* 2227 * No network interface index found 2228 * for the specified device, it means 2229 * there it is neither representor 2230 * nor master. 2231 */ 2232 continue; 2233 } 2234 } 2235 ret = -1; 2236 if (nl_route >= 0) 2237 ret = mlx5_nl_switch_info(nl_route, 2238 list[ns].ifindex, 2239 &list[ns].info); 2240 if (ret || (!list[ns].info.representor && 2241 !list[ns].info.master)) { 2242 /* 2243 * We failed to recognize representors with 2244 * Netlink, let's try to perform the task 2245 * with sysfs. 2246 */ 2247 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2248 &list[ns].info); 2249 } 2250 if (!ret && (list[ns].info.representor ^ 2251 list[ns].info.master)) { 2252 ns++; 2253 } else if ((nd == 1) && 2254 !list[ns].info.representor && 2255 !list[ns].info.master) { 2256 /* 2257 * Single IB device with one physical port and 2258 * attached network device. 2259 * May be SRIOV is not enabled or there is no 2260 * representors. 2261 */ 2262 DRV_LOG(INFO, "No E-Switch support detected."); 2263 ns++; 2264 break; 2265 } 2266 } 2267 if (!ns) { 2268 DRV_LOG(ERR, 2269 "Unable to recognize master/representors on the multiple IB devices."); 2270 rte_errno = ENOENT; 2271 ret = -rte_errno; 2272 goto exit; 2273 } 2274 /* 2275 * New kernels may add the switch_id attribute for the case 2276 * there is no E-Switch and we wrongly recognized the only 2277 * device as master. Override this if there is the single 2278 * device with single port and new device name format present. 2279 */ 2280 if (nd == 1 && 2281 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2282 list[0].info.master = 0; 2283 list[0].info.representor = 0; 2284 } 2285 } 2286 MLX5_ASSERT(ns); 2287 /* 2288 * Sort list to probe devices in natural order for users convenience 2289 * (i.e. master first, then representors from lowest to highest ID). 2290 */ 2291 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2292 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2293 /* Set devargs default values. */ 2294 if (eth_da.nb_mh_controllers == 0) { 2295 eth_da.nb_mh_controllers = 1; 2296 eth_da.mh_controllers[0] = 0; 2297 } 2298 if (eth_da.nb_ports == 0 && ns > 0) { 2299 if (list[0].pf_bond >= 0 && list[0].info.representor) 2300 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2301 pci_dev->device.devargs->args); 2302 eth_da.nb_ports = 1; 2303 eth_da.ports[0] = list[0].info.pf_num; 2304 } 2305 if (eth_da.nb_representor_ports == 0) { 2306 eth_da.nb_representor_ports = 1; 2307 eth_da.representor_ports[0] = 0; 2308 } 2309 } 2310 for (i = 0; i != ns; ++i) { 2311 uint32_t restore; 2312 2313 /* Default configuration. */ 2314 mlx5_os_config_default(&dev_config); 2315 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], 2316 &dev_config, ð_da); 2317 if (!list[i].eth_dev) { 2318 if (rte_errno != EBUSY && rte_errno != EEXIST) 2319 break; 2320 /* Device is disabled or already spawned. Ignore it. */ 2321 continue; 2322 } 2323 restore = list[i].eth_dev->data->dev_flags; 2324 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2325 /** 2326 * Each representor has a dedicated interrupts vector. 2327 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2328 * representor eth_dev object because representor and PF 2329 * share the same PCI address. 2330 * Override representor device with a dedicated 2331 * interrupts handle here. 2332 * Representor interrupts handle is released in mlx5_dev_stop(). 2333 */ 2334 if (list[i].info.representor) { 2335 struct rte_intr_handle *intr_handle = 2336 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2337 if (intr_handle == NULL) { 2338 DRV_LOG(ERR, 2339 "port %u failed to allocate memory for interrupt handler " 2340 "Rx interrupts will not be supported", 2341 i); 2342 rte_errno = ENOMEM; 2343 ret = -rte_errno; 2344 goto exit; 2345 } 2346 list[i].eth_dev->intr_handle = intr_handle; 2347 } 2348 /* Restore non-PCI flags cleared by the above call. */ 2349 list[i].eth_dev->data->dev_flags |= restore; 2350 rte_eth_dev_probing_finish(list[i].eth_dev); 2351 } 2352 if (i != ns) { 2353 DRV_LOG(ERR, 2354 "probe of PCI device " PCI_PRI_FMT " aborted after" 2355 " encountering an error: %s", 2356 owner_pci.domain, owner_pci.bus, 2357 owner_pci.devid, owner_pci.function, 2358 strerror(rte_errno)); 2359 ret = -rte_errno; 2360 /* Roll back. */ 2361 while (i--) { 2362 if (!list[i].eth_dev) 2363 continue; 2364 mlx5_dev_close(list[i].eth_dev); 2365 /* mac_addrs must not be freed because in dev_private */ 2366 list[i].eth_dev->data->mac_addrs = NULL; 2367 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2368 } 2369 /* Restore original error. */ 2370 rte_errno = -ret; 2371 } else { 2372 ret = 0; 2373 } 2374 exit: 2375 /* 2376 * Do the routine cleanup: 2377 * - close opened Netlink sockets 2378 * - free allocated spawn data array 2379 * - free the Infiniband device list 2380 */ 2381 if (nl_rdma >= 0) 2382 close(nl_rdma); 2383 if (nl_route >= 0) 2384 close(nl_route); 2385 if (list) 2386 mlx5_free(list); 2387 MLX5_ASSERT(ibv_list); 2388 mlx5_glue->free_device_list(ibv_list); 2389 return ret; 2390 } 2391 2392 static int 2393 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2394 struct rte_eth_devargs *eth_da) 2395 { 2396 int ret = 0; 2397 2398 if (dev->devargs == NULL) 2399 return 0; 2400 memset(eth_da, 0, sizeof(*eth_da)); 2401 /* Parse representor information first from class argument. */ 2402 if (dev->devargs->cls_str) 2403 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2404 if (ret != 0) { 2405 DRV_LOG(ERR, "failed to parse device arguments: %s", 2406 dev->devargs->cls_str); 2407 return -rte_errno; 2408 } 2409 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2410 /* Parse legacy device argument */ 2411 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2412 if (ret) { 2413 DRV_LOG(ERR, "failed to parse device arguments: %s", 2414 dev->devargs->args); 2415 return -rte_errno; 2416 } 2417 } 2418 return 0; 2419 } 2420 2421 /** 2422 * Callback to register a PCI device. 2423 * 2424 * This function spawns Ethernet devices out of a given PCI device. 2425 * 2426 * @param[in] cdev 2427 * Pointer to common mlx5 device structure. 2428 * 2429 * @return 2430 * 0 on success, a negative errno value otherwise and rte_errno is set. 2431 */ 2432 static int 2433 mlx5_os_pci_probe(struct mlx5_common_device *cdev) 2434 { 2435 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2436 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2437 int ret = 0; 2438 uint16_t p; 2439 2440 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da); 2441 if (ret != 0) 2442 return ret; 2443 2444 if (eth_da.nb_ports > 0) { 2445 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2446 for (p = 0; p < eth_da.nb_ports; p++) { 2447 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 2448 eth_da.ports[p]); 2449 if (ret) 2450 break; 2451 } 2452 if (ret) { 2453 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2454 "aborted due to prodding failure of PF %u", 2455 pci_dev->addr.domain, pci_dev->addr.bus, 2456 pci_dev->addr.devid, pci_dev->addr.function, 2457 eth_da.ports[p]); 2458 mlx5_net_remove(cdev); 2459 } 2460 } else { 2461 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0); 2462 } 2463 return ret; 2464 } 2465 2466 /* Probe a single SF device on auxiliary bus, no representor support. */ 2467 static int 2468 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev) 2469 { 2470 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2471 struct mlx5_dev_config config; 2472 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2473 struct rte_device *dev = cdev->dev; 2474 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2475 struct rte_eth_dev *eth_dev; 2476 int ret = 0; 2477 2478 /* Parse ethdev devargs. */ 2479 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2480 if (ret != 0) 2481 return ret; 2482 /* Set default config data. */ 2483 mlx5_os_config_default(&config); 2484 /* Init spawn data. */ 2485 spawn.max_port = 1; 2486 spawn.phys_port = 1; 2487 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 2488 ret = mlx5_auxiliary_get_ifindex(dev->name); 2489 if (ret < 0) { 2490 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2491 return ret; 2492 } 2493 spawn.ifindex = ret; 2494 spawn.cdev = cdev; 2495 /* Spawn device. */ 2496 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2497 if (eth_dev == NULL) 2498 return -rte_errno; 2499 /* Post create. */ 2500 eth_dev->intr_handle = adev->intr_handle; 2501 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2502 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2503 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2504 eth_dev->data->numa_node = dev->numa_node; 2505 } 2506 rte_eth_dev_probing_finish(eth_dev); 2507 return 0; 2508 } 2509 2510 /** 2511 * Net class driver callback to probe a device. 2512 * 2513 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2514 * 2515 * @param[in] cdev 2516 * Pointer to the common mlx5 device. 2517 * 2518 * @return 2519 * 0 on success, a negative errno value otherwise and rte_errno is set. 2520 */ 2521 int 2522 mlx5_os_net_probe(struct mlx5_common_device *cdev) 2523 { 2524 int ret; 2525 2526 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2527 mlx5_pmd_socket_init(); 2528 ret = mlx5_init_once(); 2529 if (ret) { 2530 DRV_LOG(ERR, "Unable to init PMD global data: %s", 2531 strerror(rte_errno)); 2532 return -rte_errno; 2533 } 2534 ret = mlx5_probe_again_args_validate(cdev); 2535 if (ret) { 2536 DRV_LOG(ERR, "Probe again parameters are not compatible : %s", 2537 strerror(rte_errno)); 2538 return -rte_errno; 2539 } 2540 if (mlx5_dev_is_pci(cdev->dev)) 2541 return mlx5_os_pci_probe(cdev); 2542 else 2543 return mlx5_os_auxiliary_probe(cdev); 2544 } 2545 2546 /** 2547 * Cleanup resources when the last device is closed. 2548 */ 2549 void 2550 mlx5_os_net_cleanup(void) 2551 { 2552 mlx5_pmd_socket_uninit(); 2553 } 2554 2555 /** 2556 * Install shared asynchronous device events handler. 2557 * This function is implemented to support event sharing 2558 * between multiple ports of single IB device. 2559 * 2560 * @param sh 2561 * Pointer to mlx5_dev_ctx_shared object. 2562 */ 2563 void 2564 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2565 { 2566 int ret; 2567 int flags; 2568 struct ibv_context *ctx = sh->cdev->ctx; 2569 2570 sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2571 if (sh->intr_handle == NULL) { 2572 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2573 rte_errno = ENOMEM; 2574 return; 2575 } 2576 rte_intr_fd_set(sh->intr_handle, -1); 2577 2578 flags = fcntl(ctx->async_fd, F_GETFL); 2579 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); 2580 if (ret) { 2581 DRV_LOG(INFO, "failed to change file descriptor async event" 2582 " queue"); 2583 } else { 2584 rte_intr_fd_set(sh->intr_handle, ctx->async_fd); 2585 rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); 2586 if (rte_intr_callback_register(sh->intr_handle, 2587 mlx5_dev_interrupt_handler, sh)) { 2588 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2589 rte_intr_fd_set(sh->intr_handle, -1); 2590 } 2591 } 2592 if (sh->cdev->config.devx) { 2593 #ifdef HAVE_IBV_DEVX_ASYNC 2594 sh->intr_handle_devx = 2595 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2596 if (!sh->intr_handle_devx) { 2597 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2598 rte_errno = ENOMEM; 2599 return; 2600 } 2601 rte_intr_fd_set(sh->intr_handle_devx, -1); 2602 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); 2603 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2604 if (!devx_comp) { 2605 DRV_LOG(INFO, "failed to allocate devx_comp."); 2606 return; 2607 } 2608 flags = fcntl(devx_comp->fd, F_GETFL); 2609 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2610 if (ret) { 2611 DRV_LOG(INFO, "failed to change file descriptor" 2612 " devx comp"); 2613 return; 2614 } 2615 rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); 2616 rte_intr_type_set(sh->intr_handle_devx, 2617 RTE_INTR_HANDLE_EXT); 2618 if (rte_intr_callback_register(sh->intr_handle_devx, 2619 mlx5_dev_interrupt_handler_devx, sh)) { 2620 DRV_LOG(INFO, "Fail to install the devx shared" 2621 " interrupt."); 2622 rte_intr_fd_set(sh->intr_handle_devx, -1); 2623 } 2624 #endif /* HAVE_IBV_DEVX_ASYNC */ 2625 } 2626 } 2627 2628 /** 2629 * Uninstall shared asynchronous device events handler. 2630 * This function is implemented to support event sharing 2631 * between multiple ports of single IB device. 2632 * 2633 * @param dev 2634 * Pointer to mlx5_dev_ctx_shared object. 2635 */ 2636 void 2637 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2638 { 2639 if (rte_intr_fd_get(sh->intr_handle) >= 0) 2640 mlx5_intr_callback_unregister(sh->intr_handle, 2641 mlx5_dev_interrupt_handler, sh); 2642 rte_intr_instance_free(sh->intr_handle); 2643 #ifdef HAVE_IBV_DEVX_ASYNC 2644 if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) 2645 rte_intr_callback_unregister(sh->intr_handle_devx, 2646 mlx5_dev_interrupt_handler_devx, sh); 2647 rte_intr_instance_free(sh->intr_handle_devx); 2648 if (sh->devx_comp) 2649 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2650 #endif 2651 } 2652 2653 /** 2654 * Read statistics by a named counter. 2655 * 2656 * @param[in] priv 2657 * Pointer to the private device data structure. 2658 * @param[in] ctr_name 2659 * Pointer to the name of the statistic counter to read 2660 * @param[out] stat 2661 * Pointer to read statistic value. 2662 * @return 2663 * 0 on success and stat is valud, 1 if failed to read the value 2664 * rte_errno is set. 2665 * 2666 */ 2667 int 2668 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2669 uint64_t *stat) 2670 { 2671 int fd; 2672 2673 if (priv->sh) { 2674 if (priv->q_counters != NULL && 2675 strcmp(ctr_name, "out_of_buffer") == 0) 2676 return mlx5_devx_cmd_queue_counter_query 2677 (priv->q_counters, 0, (uint32_t *)stat); 2678 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2679 priv->sh->ibdev_path, 2680 priv->dev_port, 2681 ctr_name); 2682 fd = open(path, O_RDONLY); 2683 /* 2684 * in switchdev the file location is not per port 2685 * but rather in <ibdev_path>/hw_counters/<file_name>. 2686 */ 2687 if (fd == -1) { 2688 MKSTR(path1, "%s/hw_counters/%s", 2689 priv->sh->ibdev_path, 2690 ctr_name); 2691 fd = open(path1, O_RDONLY); 2692 } 2693 if (fd != -1) { 2694 char buf[21] = {'\0'}; 2695 ssize_t n = read(fd, buf, sizeof(buf)); 2696 2697 close(fd); 2698 if (n != -1) { 2699 *stat = strtoull(buf, NULL, 10); 2700 return 0; 2701 } 2702 } 2703 } 2704 *stat = 0; 2705 return 1; 2706 } 2707 2708 /** 2709 * Remove a MAC address from device 2710 * 2711 * @param dev 2712 * Pointer to Ethernet device structure. 2713 * @param index 2714 * MAC address index. 2715 */ 2716 void 2717 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2718 { 2719 struct mlx5_priv *priv = dev->data->dev_private; 2720 const int vf = priv->sh->dev_cap.vf; 2721 2722 if (vf) 2723 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2724 mlx5_ifindex(dev), priv->mac_own, 2725 &dev->data->mac_addrs[index], index); 2726 } 2727 2728 /** 2729 * Adds a MAC address to the device 2730 * 2731 * @param dev 2732 * Pointer to Ethernet device structure. 2733 * @param mac_addr 2734 * MAC address to register. 2735 * @param index 2736 * MAC address index. 2737 * 2738 * @return 2739 * 0 on success, a negative errno value otherwise 2740 */ 2741 int 2742 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2743 uint32_t index) 2744 { 2745 struct mlx5_priv *priv = dev->data->dev_private; 2746 const int vf = priv->sh->dev_cap.vf; 2747 int ret = 0; 2748 2749 if (vf) 2750 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2751 mlx5_ifindex(dev), priv->mac_own, 2752 mac, index); 2753 return ret; 2754 } 2755 2756 /** 2757 * Modify a VF MAC address 2758 * 2759 * @param priv 2760 * Pointer to device private data. 2761 * @param mac_addr 2762 * MAC address to modify into. 2763 * @param iface_idx 2764 * Net device interface index 2765 * @param vf_index 2766 * VF index 2767 * 2768 * @return 2769 * 0 on success, a negative errno value otherwise 2770 */ 2771 int 2772 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2773 unsigned int iface_idx, 2774 struct rte_ether_addr *mac_addr, 2775 int vf_index) 2776 { 2777 return mlx5_nl_vf_mac_addr_modify 2778 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2779 } 2780 2781 /** 2782 * Set device promiscuous mode 2783 * 2784 * @param dev 2785 * Pointer to Ethernet device structure. 2786 * @param enable 2787 * 0 - promiscuous is disabled, otherwise - enabled 2788 * 2789 * @return 2790 * 0 on success, a negative error value otherwise 2791 */ 2792 int 2793 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2794 { 2795 struct mlx5_priv *priv = dev->data->dev_private; 2796 2797 return mlx5_nl_promisc(priv->nl_socket_route, 2798 mlx5_ifindex(dev), !!enable); 2799 } 2800 2801 /** 2802 * Set device promiscuous mode 2803 * 2804 * @param dev 2805 * Pointer to Ethernet device structure. 2806 * @param enable 2807 * 0 - all multicase is disabled, otherwise - enabled 2808 * 2809 * @return 2810 * 0 on success, a negative error value otherwise 2811 */ 2812 int 2813 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2814 { 2815 struct mlx5_priv *priv = dev->data->dev_private; 2816 2817 return mlx5_nl_allmulti(priv->nl_socket_route, 2818 mlx5_ifindex(dev), !!enable); 2819 } 2820 2821 /** 2822 * Flush device MAC addresses 2823 * 2824 * @param dev 2825 * Pointer to Ethernet device structure. 2826 * 2827 */ 2828 void 2829 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2830 { 2831 struct mlx5_priv *priv = dev->data->dev_private; 2832 2833 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2834 dev->data->mac_addrs, 2835 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2836 } 2837