1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_qp = attr_ex.orig_attr.max_qp; 120 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 121 device_attr->max_rwq_indirection_table_size = 122 attr_ex.rss_caps.max_rwq_indirection_table_size; 123 device_attr->max_tso = attr_ex.tso_caps.max_tso; 124 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 125 126 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 127 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 128 if (err) 129 return err; 130 131 device_attr->flags = dv_attr.flags; 132 device_attr->comp_mask = dv_attr.comp_mask; 133 #ifdef HAVE_IBV_MLX5_MOD_SWP 134 device_attr->sw_parsing_offloads = 135 dv_attr.sw_parsing_caps.sw_parsing_offloads; 136 #endif 137 device_attr->min_single_stride_log_num_of_bytes = 138 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 139 device_attr->max_single_stride_log_num_of_bytes = 140 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 141 device_attr->min_single_wqe_log_num_of_strides = 142 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 143 device_attr->max_single_wqe_log_num_of_strides = 144 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 145 device_attr->stride_supported_qpts = 146 dv_attr.striding_rq_caps.supported_qpts; 147 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 148 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 149 #endif 150 151 return err; 152 } 153 154 /** 155 * Verbs callback to allocate a memory. This function should allocate the space 156 * according to the size provided residing inside a huge page. 157 * Please note that all allocation must respect the alignment from libmlx5 158 * (i.e. currently rte_mem_page_size()). 159 * 160 * @param[in] size 161 * The size in bytes of the memory to allocate. 162 * @param[in] data 163 * A pointer to the callback data. 164 * 165 * @return 166 * Allocated buffer, NULL otherwise and rte_errno is set. 167 */ 168 static void * 169 mlx5_alloc_verbs_buf(size_t size, void *data) 170 { 171 struct mlx5_priv *priv = data; 172 void *ret; 173 unsigned int socket = SOCKET_ID_ANY; 174 size_t alignment = rte_mem_page_size(); 175 if (alignment == (size_t)-1) { 176 DRV_LOG(ERR, "Failed to get mem page size"); 177 rte_errno = ENOMEM; 178 return NULL; 179 } 180 181 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 182 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 183 184 socket = ctrl->socket; 185 } else if (priv->verbs_alloc_ctx.type == 186 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 187 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 188 189 socket = ctrl->socket; 190 } 191 MLX5_ASSERT(data != NULL); 192 ret = mlx5_malloc(0, size, alignment, socket); 193 if (!ret && size) 194 rte_errno = ENOMEM; 195 return ret; 196 } 197 198 /** 199 * Verbs callback to free a memory. 200 * 201 * @param[in] ptr 202 * A pointer to the memory to free. 203 * @param[in] data 204 * A pointer to the callback data. 205 */ 206 static void 207 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 208 { 209 MLX5_ASSERT(data != NULL); 210 mlx5_free(ptr); 211 } 212 213 /** 214 * Initialize DR related data within private structure. 215 * Routine checks the reference counter and does actual 216 * resources creation/initialization only if counter is zero. 217 * 218 * @param[in] priv 219 * Pointer to the private device data structure. 220 * 221 * @return 222 * Zero on success, positive error code otherwise. 223 */ 224 static int 225 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 226 { 227 struct mlx5_dev_ctx_shared *sh = priv->sh; 228 char s[MLX5_HLIST_NAMESIZE] __rte_unused; 229 int err; 230 231 MLX5_ASSERT(sh && sh->refcnt); 232 if (sh->refcnt > 1) 233 return 0; 234 err = mlx5_alloc_table_hash_list(priv); 235 if (err) 236 goto error; 237 /* The resources below are only valid with DV support. */ 238 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 239 /* Init port id action cache list. */ 240 snprintf(s, sizeof(s), "%s_port_id_action_cache", sh->ibdev_name); 241 mlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh, 242 flow_dv_port_id_create_cb, 243 flow_dv_port_id_match_cb, 244 flow_dv_port_id_remove_cb); 245 /* Init push vlan action cache list. */ 246 snprintf(s, sizeof(s), "%s_push_vlan_action_cache", sh->ibdev_name); 247 mlx5_cache_list_init(&sh->push_vlan_action_list, s, 0, sh, 248 flow_dv_push_vlan_create_cb, 249 flow_dv_push_vlan_match_cb, 250 flow_dv_push_vlan_remove_cb); 251 /* Init sample action cache list. */ 252 snprintf(s, sizeof(s), "%s_sample_action_cache", sh->ibdev_name); 253 mlx5_cache_list_init(&sh->sample_action_list, s, 0, 254 &rte_eth_devices[priv->dev_data->port_id], 255 flow_dv_sample_create_cb, 256 flow_dv_sample_match_cb, 257 flow_dv_sample_remove_cb); 258 /* Init dest array action cache list. */ 259 snprintf(s, sizeof(s), "%s_dest_array_cache", sh->ibdev_name); 260 mlx5_cache_list_init(&sh->dest_array_list, s, 0, 261 &rte_eth_devices[priv->dev_data->port_id], 262 flow_dv_dest_array_create_cb, 263 flow_dv_dest_array_match_cb, 264 flow_dv_dest_array_remove_cb); 265 /* Create tags hash list table. */ 266 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 267 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0, 268 MLX5_HLIST_WRITE_MOST, 269 flow_dv_tag_create_cb, NULL, 270 flow_dv_tag_remove_cb); 271 if (!sh->tag_table) { 272 DRV_LOG(ERR, "tags with hash creation failed."); 273 err = ENOMEM; 274 goto error; 275 } 276 sh->tag_table->ctx = sh; 277 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 278 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ, 279 0, MLX5_HLIST_WRITE_MOST | 280 MLX5_HLIST_DIRECT_KEY, 281 flow_dv_modify_create_cb, 282 flow_dv_modify_match_cb, 283 flow_dv_modify_remove_cb); 284 if (!sh->modify_cmds) { 285 DRV_LOG(ERR, "hdr modify hash creation failed"); 286 err = ENOMEM; 287 goto error; 288 } 289 sh->modify_cmds->ctx = sh; 290 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 291 sh->encaps_decaps = mlx5_hlist_create(s, 292 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ, 293 0, MLX5_HLIST_DIRECT_KEY | 294 MLX5_HLIST_WRITE_MOST, 295 flow_dv_encap_decap_create_cb, 296 flow_dv_encap_decap_match_cb, 297 flow_dv_encap_decap_remove_cb); 298 if (!sh->encaps_decaps) { 299 DRV_LOG(ERR, "encap decap hash creation failed"); 300 err = ENOMEM; 301 goto error; 302 } 303 sh->encaps_decaps->ctx = sh; 304 #endif 305 #ifdef HAVE_MLX5DV_DR 306 void *domain; 307 308 /* Reference counter is zero, we should initialize structures. */ 309 domain = mlx5_glue->dr_create_domain(sh->ctx, 310 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 311 if (!domain) { 312 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 313 err = errno; 314 goto error; 315 } 316 sh->rx_domain = domain; 317 domain = mlx5_glue->dr_create_domain(sh->ctx, 318 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 319 if (!domain) { 320 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 321 err = errno; 322 goto error; 323 } 324 sh->tx_domain = domain; 325 #ifdef HAVE_MLX5DV_DR_ESWITCH 326 if (priv->config.dv_esw_en) { 327 domain = mlx5_glue->dr_create_domain 328 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 329 if (!domain) { 330 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 331 err = errno; 332 goto error; 333 } 334 sh->fdb_domain = domain; 335 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 336 } 337 #endif 338 if (!sh->tunnel_hub) 339 err = mlx5_alloc_tunnel_hub(sh); 340 if (err) { 341 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 342 goto error; 343 } 344 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 345 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 346 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 347 if (sh->fdb_domain) 348 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 349 } 350 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 351 #endif /* HAVE_MLX5DV_DR */ 352 sh->default_miss_action = 353 mlx5_glue->dr_create_flow_action_default_miss(); 354 if (!sh->default_miss_action) 355 DRV_LOG(WARNING, "Default miss action is not supported."); 356 return 0; 357 error: 358 /* Rollback the created objects. */ 359 if (sh->rx_domain) { 360 mlx5_glue->dr_destroy_domain(sh->rx_domain); 361 sh->rx_domain = NULL; 362 } 363 if (sh->tx_domain) { 364 mlx5_glue->dr_destroy_domain(sh->tx_domain); 365 sh->tx_domain = NULL; 366 } 367 if (sh->fdb_domain) { 368 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 369 sh->fdb_domain = NULL; 370 } 371 if (sh->esw_drop_action) { 372 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 373 sh->esw_drop_action = NULL; 374 } 375 if (sh->pop_vlan_action) { 376 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 377 sh->pop_vlan_action = NULL; 378 } 379 if (sh->encaps_decaps) { 380 mlx5_hlist_destroy(sh->encaps_decaps); 381 sh->encaps_decaps = NULL; 382 } 383 if (sh->modify_cmds) { 384 mlx5_hlist_destroy(sh->modify_cmds); 385 sh->modify_cmds = NULL; 386 } 387 if (sh->tag_table) { 388 /* tags should be destroyed with flow before. */ 389 mlx5_hlist_destroy(sh->tag_table); 390 sh->tag_table = NULL; 391 } 392 if (sh->tunnel_hub) { 393 mlx5_release_tunnel_hub(sh, priv->dev_port); 394 sh->tunnel_hub = NULL; 395 } 396 mlx5_free_table_hash_list(priv); 397 return err; 398 } 399 400 /** 401 * Destroy DR related data within private structure. 402 * 403 * @param[in] priv 404 * Pointer to the private device data structure. 405 */ 406 void 407 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 408 { 409 struct mlx5_dev_ctx_shared *sh = priv->sh; 410 411 MLX5_ASSERT(sh && sh->refcnt); 412 if (sh->refcnt > 1) 413 return; 414 #ifdef HAVE_MLX5DV_DR 415 if (sh->rx_domain) { 416 mlx5_glue->dr_destroy_domain(sh->rx_domain); 417 sh->rx_domain = NULL; 418 } 419 if (sh->tx_domain) { 420 mlx5_glue->dr_destroy_domain(sh->tx_domain); 421 sh->tx_domain = NULL; 422 } 423 #ifdef HAVE_MLX5DV_DR_ESWITCH 424 if (sh->fdb_domain) { 425 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 426 sh->fdb_domain = NULL; 427 } 428 if (sh->esw_drop_action) { 429 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 430 sh->esw_drop_action = NULL; 431 } 432 #endif 433 if (sh->pop_vlan_action) { 434 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 435 sh->pop_vlan_action = NULL; 436 } 437 #endif /* HAVE_MLX5DV_DR */ 438 if (sh->default_miss_action) 439 mlx5_glue->destroy_flow_action 440 (sh->default_miss_action); 441 if (sh->encaps_decaps) { 442 mlx5_hlist_destroy(sh->encaps_decaps); 443 sh->encaps_decaps = NULL; 444 } 445 if (sh->modify_cmds) { 446 mlx5_hlist_destroy(sh->modify_cmds); 447 sh->modify_cmds = NULL; 448 } 449 if (sh->tag_table) { 450 /* tags should be destroyed with flow before. */ 451 mlx5_hlist_destroy(sh->tag_table); 452 sh->tag_table = NULL; 453 } 454 if (sh->tunnel_hub) { 455 mlx5_release_tunnel_hub(sh, priv->dev_port); 456 sh->tunnel_hub = NULL; 457 } 458 mlx5_cache_list_destroy(&sh->port_id_action_list); 459 mlx5_cache_list_destroy(&sh->push_vlan_action_list); 460 mlx5_free_table_hash_list(priv); 461 } 462 463 /** 464 * Initialize shared data between primary and secondary process. 465 * 466 * A memzone is reserved by primary process and secondary processes attach to 467 * the memzone. 468 * 469 * @return 470 * 0 on success, a negative errno value otherwise and rte_errno is set. 471 */ 472 static int 473 mlx5_init_shared_data(void) 474 { 475 const struct rte_memzone *mz; 476 int ret = 0; 477 478 rte_spinlock_lock(&mlx5_shared_data_lock); 479 if (mlx5_shared_data == NULL) { 480 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 481 /* Allocate shared memory. */ 482 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 483 sizeof(*mlx5_shared_data), 484 SOCKET_ID_ANY, 0); 485 if (mz == NULL) { 486 DRV_LOG(ERR, 487 "Cannot allocate mlx5 shared data"); 488 ret = -rte_errno; 489 goto error; 490 } 491 mlx5_shared_data = mz->addr; 492 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 493 rte_spinlock_init(&mlx5_shared_data->lock); 494 } else { 495 /* Lookup allocated shared memory. */ 496 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 497 if (mz == NULL) { 498 DRV_LOG(ERR, 499 "Cannot attach mlx5 shared data"); 500 ret = -rte_errno; 501 goto error; 502 } 503 mlx5_shared_data = mz->addr; 504 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 505 } 506 } 507 error: 508 rte_spinlock_unlock(&mlx5_shared_data_lock); 509 return ret; 510 } 511 512 /** 513 * PMD global initialization. 514 * 515 * Independent from individual device, this function initializes global 516 * per-PMD data structures distinguishing primary and secondary processes. 517 * Hence, each initialization is called once per a process. 518 * 519 * @return 520 * 0 on success, a negative errno value otherwise and rte_errno is set. 521 */ 522 static int 523 mlx5_init_once(void) 524 { 525 struct mlx5_shared_data *sd; 526 struct mlx5_local_data *ld = &mlx5_local_data; 527 int ret = 0; 528 529 if (mlx5_init_shared_data()) 530 return -rte_errno; 531 sd = mlx5_shared_data; 532 MLX5_ASSERT(sd); 533 rte_spinlock_lock(&sd->lock); 534 switch (rte_eal_process_type()) { 535 case RTE_PROC_PRIMARY: 536 if (sd->init_done) 537 break; 538 LIST_INIT(&sd->mem_event_cb_list); 539 rte_rwlock_init(&sd->mem_event_rwlock); 540 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 541 mlx5_mr_mem_event_cb, NULL); 542 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 543 mlx5_mp_os_primary_handle); 544 if (ret) 545 goto out; 546 sd->init_done = true; 547 break; 548 case RTE_PROC_SECONDARY: 549 if (ld->init_done) 550 break; 551 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 552 mlx5_mp_os_secondary_handle); 553 if (ret) 554 goto out; 555 ++sd->secondary_cnt; 556 ld->init_done = true; 557 break; 558 default: 559 break; 560 } 561 out: 562 rte_spinlock_unlock(&sd->lock); 563 return ret; 564 } 565 566 /** 567 * Create the Tx queue DevX/Verbs object. 568 * 569 * @param dev 570 * Pointer to Ethernet device. 571 * @param idx 572 * Queue index in DPDK Tx queue array. 573 * 574 * @return 575 * 0 on success, a negative errno value otherwise and rte_errno is set. 576 */ 577 static int 578 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 579 { 580 struct mlx5_priv *priv = dev->data->dev_private; 581 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 582 struct mlx5_txq_ctrl *txq_ctrl = 583 container_of(txq_data, struct mlx5_txq_ctrl, txq); 584 585 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 586 return mlx5_txq_devx_obj_new(dev, idx); 587 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 588 if (!priv->config.dv_esw_en) 589 return mlx5_txq_devx_obj_new(dev, idx); 590 #endif 591 return mlx5_txq_ibv_obj_new(dev, idx); 592 } 593 594 /** 595 * Release an Tx DevX/verbs queue object. 596 * 597 * @param txq_obj 598 * DevX/Verbs Tx queue object. 599 */ 600 static void 601 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 602 { 603 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 604 mlx5_txq_devx_obj_release(txq_obj); 605 return; 606 } 607 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 608 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 609 mlx5_txq_devx_obj_release(txq_obj); 610 return; 611 } 612 #endif 613 mlx5_txq_ibv_obj_release(txq_obj); 614 } 615 616 /** 617 * DV flow counter mode detect and config. 618 * 619 * @param dev 620 * Pointer to rte_eth_dev structure. 621 * 622 */ 623 static void 624 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 625 { 626 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 627 struct mlx5_priv *priv = dev->data->dev_private; 628 struct mlx5_dev_ctx_shared *sh = priv->sh; 629 bool fallback; 630 631 #ifndef HAVE_IBV_DEVX_ASYNC 632 fallback = true; 633 #else 634 fallback = false; 635 if (!priv->config.devx || !priv->config.dv_flow_en || 636 !priv->config.hca_attr.flow_counters_dump || 637 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 638 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 639 fallback = true; 640 #endif 641 if (fallback) 642 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 643 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 644 priv->config.hca_attr.flow_counters_dump, 645 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 646 /* Initialize fallback mode only on the port initializes sh. */ 647 if (sh->refcnt == 1) 648 sh->cmng.counter_fallback = fallback; 649 else if (fallback != sh->cmng.counter_fallback) 650 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 651 "with others:%d.", PORT_ID(priv), fallback); 652 #endif 653 } 654 655 /** 656 * Spawn an Ethernet device from Verbs information. 657 * 658 * @param dpdk_dev 659 * Backing DPDK device. 660 * @param spawn 661 * Verbs device parameters (name, port, switch_info) to spawn. 662 * @param config 663 * Device configuration parameters. 664 * 665 * @return 666 * A valid Ethernet device object on success, NULL otherwise and rte_errno 667 * is set. The following errors are defined: 668 * 669 * EBUSY: device is not supposed to be spawned. 670 * EEXIST: device is already spawned 671 */ 672 static struct rte_eth_dev * 673 mlx5_dev_spawn(struct rte_device *dpdk_dev, 674 struct mlx5_dev_spawn_data *spawn, 675 struct mlx5_dev_config *config) 676 { 677 const struct mlx5_switch_info *switch_info = &spawn->info; 678 struct mlx5_dev_ctx_shared *sh = NULL; 679 struct ibv_port_attr port_attr; 680 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 681 struct rte_eth_dev *eth_dev = NULL; 682 struct mlx5_priv *priv = NULL; 683 int err = 0; 684 unsigned int hw_padding = 0; 685 unsigned int mps; 686 unsigned int cqe_comp; 687 unsigned int cqe_pad = 0; 688 unsigned int tunnel_en = 0; 689 unsigned int mpls_en = 0; 690 unsigned int swp = 0; 691 unsigned int mprq = 0; 692 unsigned int mprq_min_stride_size_n = 0; 693 unsigned int mprq_max_stride_size_n = 0; 694 unsigned int mprq_min_stride_num_n = 0; 695 unsigned int mprq_max_stride_num_n = 0; 696 struct rte_ether_addr mac; 697 char name[RTE_ETH_NAME_MAX_LEN]; 698 int own_domain_id = 0; 699 uint16_t port_id; 700 unsigned int i; 701 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 702 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 703 #endif 704 705 /* Determine if this port representor is supposed to be spawned. */ 706 if (switch_info->representor && dpdk_dev->devargs) { 707 struct rte_eth_devargs eth_da; 708 709 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 710 if (err) { 711 rte_errno = -err; 712 DRV_LOG(ERR, "failed to process device arguments: %s", 713 strerror(rte_errno)); 714 return NULL; 715 } 716 for (i = 0; i < eth_da.nb_representor_ports; ++i) 717 if (eth_da.representor_ports[i] == 718 (uint16_t)switch_info->port_name) 719 break; 720 if (i == eth_da.nb_representor_ports) { 721 rte_errno = EBUSY; 722 return NULL; 723 } 724 } 725 /* Build device name. */ 726 if (spawn->pf_bond < 0) { 727 /* Single device. */ 728 if (!switch_info->representor) 729 strlcpy(name, dpdk_dev->name, sizeof(name)); 730 else 731 snprintf(name, sizeof(name), "%s_representor_%u", 732 dpdk_dev->name, switch_info->port_name); 733 } else { 734 /* Bonding device. */ 735 if (!switch_info->representor) 736 snprintf(name, sizeof(name), "%s_%s", 737 dpdk_dev->name, 738 mlx5_os_get_dev_device_name(spawn->phys_dev)); 739 else 740 snprintf(name, sizeof(name), "%s_%s_representor_%u", 741 dpdk_dev->name, 742 mlx5_os_get_dev_device_name(spawn->phys_dev), 743 switch_info->port_name); 744 } 745 /* check if the device is already spawned */ 746 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 747 rte_errno = EEXIST; 748 return NULL; 749 } 750 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 751 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 752 struct mlx5_mp_id mp_id; 753 754 eth_dev = rte_eth_dev_attach_secondary(name); 755 if (eth_dev == NULL) { 756 DRV_LOG(ERR, "can not attach rte ethdev"); 757 rte_errno = ENOMEM; 758 return NULL; 759 } 760 eth_dev->device = dpdk_dev; 761 eth_dev->dev_ops = &mlx5_os_dev_sec_ops; 762 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 763 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 764 err = mlx5_proc_priv_init(eth_dev); 765 if (err) 766 return NULL; 767 mp_id.port_id = eth_dev->data->port_id; 768 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 769 /* Receive command fd from primary process */ 770 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 771 if (err < 0) 772 goto err_secondary; 773 /* Remap UAR for Tx queues. */ 774 err = mlx5_tx_uar_init_secondary(eth_dev, err); 775 if (err) 776 goto err_secondary; 777 /* 778 * Ethdev pointer is still required as input since 779 * the primary device is not accessible from the 780 * secondary process. 781 */ 782 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 783 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 784 return eth_dev; 785 err_secondary: 786 mlx5_dev_close(eth_dev); 787 return NULL; 788 } 789 /* 790 * Some parameters ("tx_db_nc" in particularly) are needed in 791 * advance to create dv/verbs device context. We proceed the 792 * devargs here to get ones, and later proceed devargs again 793 * to override some hardware settings. 794 */ 795 err = mlx5_args(config, dpdk_dev->devargs); 796 if (err) { 797 err = rte_errno; 798 DRV_LOG(ERR, "failed to process device arguments: %s", 799 strerror(rte_errno)); 800 goto error; 801 } 802 if (config->dv_miss_info) { 803 if (switch_info->master || switch_info->representor) 804 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 805 } 806 mlx5_malloc_mem_select(config->sys_mem_en); 807 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 808 if (!sh) 809 return NULL; 810 config->devx = sh->devx; 811 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 812 config->dest_tir = 1; 813 #endif 814 #ifdef HAVE_IBV_MLX5_MOD_SWP 815 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 816 #endif 817 /* 818 * Multi-packet send is supported by ConnectX-4 Lx PF as well 819 * as all ConnectX-5 devices. 820 */ 821 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 822 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 823 #endif 824 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 825 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 826 #endif 827 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 828 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 829 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 830 DRV_LOG(DEBUG, "enhanced MPW is supported"); 831 mps = MLX5_MPW_ENHANCED; 832 } else { 833 DRV_LOG(DEBUG, "MPW is supported"); 834 mps = MLX5_MPW; 835 } 836 } else { 837 DRV_LOG(DEBUG, "MPW isn't supported"); 838 mps = MLX5_MPW_DISABLED; 839 } 840 #ifdef HAVE_IBV_MLX5_MOD_SWP 841 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 842 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 843 DRV_LOG(DEBUG, "SWP support: %u", swp); 844 #endif 845 config->swp = !!swp; 846 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 847 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 848 struct mlx5dv_striding_rq_caps mprq_caps = 849 dv_attr.striding_rq_caps; 850 851 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 852 mprq_caps.min_single_stride_log_num_of_bytes); 853 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 854 mprq_caps.max_single_stride_log_num_of_bytes); 855 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 856 mprq_caps.min_single_wqe_log_num_of_strides); 857 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 858 mprq_caps.max_single_wqe_log_num_of_strides); 859 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 860 mprq_caps.supported_qpts); 861 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 862 mprq = 1; 863 mprq_min_stride_size_n = 864 mprq_caps.min_single_stride_log_num_of_bytes; 865 mprq_max_stride_size_n = 866 mprq_caps.max_single_stride_log_num_of_bytes; 867 mprq_min_stride_num_n = 868 mprq_caps.min_single_wqe_log_num_of_strides; 869 mprq_max_stride_num_n = 870 mprq_caps.max_single_wqe_log_num_of_strides; 871 } 872 #endif 873 if (RTE_CACHE_LINE_SIZE == 128 && 874 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 875 cqe_comp = 0; 876 else 877 cqe_comp = 1; 878 config->cqe_comp = cqe_comp; 879 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 880 /* Whether device supports 128B Rx CQE padding. */ 881 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 882 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 883 #endif 884 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 885 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 886 tunnel_en = ((dv_attr.tunnel_offloads_caps & 887 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 888 (dv_attr.tunnel_offloads_caps & 889 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 890 (dv_attr.tunnel_offloads_caps & 891 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 892 } 893 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 894 tunnel_en ? "" : "not "); 895 #else 896 DRV_LOG(WARNING, 897 "tunnel offloading disabled due to old OFED/rdma-core version"); 898 #endif 899 config->tunnel_en = tunnel_en; 900 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 901 mpls_en = ((dv_attr.tunnel_offloads_caps & 902 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 903 (dv_attr.tunnel_offloads_caps & 904 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 905 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 906 mpls_en ? "" : "not "); 907 #else 908 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 909 " old OFED/rdma-core version or firmware configuration"); 910 #endif 911 config->mpls_en = mpls_en; 912 /* Check port status. */ 913 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 914 if (err) { 915 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 916 goto error; 917 } 918 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 919 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 920 err = EINVAL; 921 goto error; 922 } 923 if (port_attr.state != IBV_PORT_ACTIVE) 924 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 925 mlx5_glue->port_state_str(port_attr.state), 926 port_attr.state); 927 /* Allocate private eth device data. */ 928 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 929 sizeof(*priv), 930 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 931 if (priv == NULL) { 932 DRV_LOG(ERR, "priv allocation failure"); 933 err = ENOMEM; 934 goto error; 935 } 936 priv->sh = sh; 937 priv->dev_port = spawn->phys_port; 938 priv->pci_dev = spawn->pci_dev; 939 priv->mtu = RTE_ETHER_MTU; 940 priv->mp_id.port_id = port_id; 941 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 942 /* Some internal functions rely on Netlink sockets, open them now. */ 943 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 944 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 945 priv->representor = !!switch_info->representor; 946 priv->master = !!switch_info->master; 947 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 948 priv->vport_meta_tag = 0; 949 priv->vport_meta_mask = 0; 950 priv->pf_bond = spawn->pf_bond; 951 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 952 /* 953 * The DevX port query API is implemented. E-Switch may use 954 * either vport or reg_c[0] metadata register to match on 955 * vport index. The engaged part of metadata register is 956 * defined by mask. 957 */ 958 if (switch_info->representor || switch_info->master) { 959 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 960 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 961 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 962 &devx_port); 963 if (err) { 964 DRV_LOG(WARNING, 965 "can't query devx port %d on device %s", 966 spawn->phys_port, 967 mlx5_os_get_dev_device_name(spawn->phys_dev)); 968 devx_port.comp_mask = 0; 969 } 970 } 971 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 972 priv->vport_meta_tag = devx_port.reg_c_0.value; 973 priv->vport_meta_mask = devx_port.reg_c_0.mask; 974 if (!priv->vport_meta_mask) { 975 DRV_LOG(ERR, "vport zero mask for port %d" 976 " on bonding device %s", 977 spawn->phys_port, 978 mlx5_os_get_dev_device_name 979 (spawn->phys_dev)); 980 err = ENOTSUP; 981 goto error; 982 } 983 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 984 DRV_LOG(ERR, "invalid vport tag for port %d" 985 " on bonding device %s", 986 spawn->phys_port, 987 mlx5_os_get_dev_device_name 988 (spawn->phys_dev)); 989 err = ENOTSUP; 990 goto error; 991 } 992 } 993 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 994 priv->vport_id = devx_port.vport_num; 995 } else if (spawn->pf_bond >= 0) { 996 DRV_LOG(ERR, "can't deduce vport index for port %d" 997 " on bonding device %s", 998 spawn->phys_port, 999 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1000 err = ENOTSUP; 1001 goto error; 1002 } else { 1003 /* Suppose vport index in compatible way. */ 1004 priv->vport_id = switch_info->representor ? 1005 switch_info->port_name + 1 : -1; 1006 } 1007 #else 1008 /* 1009 * Kernel/rdma_core support single E-Switch per PF configurations 1010 * only and vport_id field contains the vport index for 1011 * associated VF, which is deduced from representor port name. 1012 * For example, let's have the IB device port 10, it has 1013 * attached network device eth0, which has port name attribute 1014 * pf0vf2, we can deduce the VF number as 2, and set vport index 1015 * as 3 (2+1). This assigning schema should be changed if the 1016 * multiple E-Switch instances per PF configurations or/and PCI 1017 * subfunctions are added. 1018 */ 1019 priv->vport_id = switch_info->representor ? 1020 switch_info->port_name + 1 : -1; 1021 #endif 1022 /* representor_id field keeps the unmodified VF index. */ 1023 priv->representor_id = switch_info->representor ? 1024 switch_info->port_name : -1; 1025 /* 1026 * Look for sibling devices in order to reuse their switch domain 1027 * if any, otherwise allocate one. 1028 */ 1029 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1030 const struct mlx5_priv *opriv = 1031 rte_eth_devices[port_id].data->dev_private; 1032 1033 if (!opriv || 1034 opriv->sh != priv->sh || 1035 opriv->domain_id == 1036 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1037 continue; 1038 priv->domain_id = opriv->domain_id; 1039 break; 1040 } 1041 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1042 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1043 if (err) { 1044 err = rte_errno; 1045 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1046 strerror(rte_errno)); 1047 goto error; 1048 } 1049 own_domain_id = 1; 1050 } 1051 /* Override some values set by hardware configuration. */ 1052 mlx5_args(config, dpdk_dev->devargs); 1053 err = mlx5_dev_check_sibling_config(priv, config); 1054 if (err) 1055 goto error; 1056 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1057 IBV_DEVICE_RAW_IP_CSUM); 1058 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1059 (config->hw_csum ? "" : "not ")); 1060 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1061 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1062 DRV_LOG(DEBUG, "counters are not supported"); 1063 #endif 1064 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1065 if (config->dv_flow_en) { 1066 DRV_LOG(WARNING, "DV flow is not supported"); 1067 config->dv_flow_en = 0; 1068 } 1069 #endif 1070 config->ind_table_max_size = 1071 sh->device_attr.max_rwq_indirection_table_size; 1072 /* 1073 * Remove this check once DPDK supports larger/variable 1074 * indirection tables. 1075 */ 1076 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1077 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1078 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1079 config->ind_table_max_size); 1080 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1081 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1082 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1083 (config->hw_vlan_strip ? "" : "not ")); 1084 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1085 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1086 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1087 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1088 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1089 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1090 IBV_DEVICE_PCI_WRITE_END_PADDING); 1091 #endif 1092 if (config->hw_padding && !hw_padding) { 1093 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1094 config->hw_padding = 0; 1095 } else if (config->hw_padding) { 1096 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1097 } 1098 config->tso = (sh->device_attr.max_tso > 0 && 1099 (sh->device_attr.tso_supported_qpts & 1100 (1 << IBV_QPT_RAW_PACKET))); 1101 if (config->tso) 1102 config->tso_max_payload_sz = sh->device_attr.max_tso; 1103 /* 1104 * MPW is disabled by default, while the Enhanced MPW is enabled 1105 * by default. 1106 */ 1107 if (config->mps == MLX5_ARG_UNSET) 1108 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1109 MLX5_MPW_DISABLED; 1110 else 1111 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1112 DRV_LOG(INFO, "%sMPS is %s", 1113 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1114 config->mps == MLX5_MPW ? "legacy " : "", 1115 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1116 if (config->cqe_comp && !cqe_comp) { 1117 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1118 config->cqe_comp = 0; 1119 } 1120 if (config->cqe_pad && !cqe_pad) { 1121 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1122 config->cqe_pad = 0; 1123 } else if (config->cqe_pad) { 1124 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1125 } 1126 if (config->devx) { 1127 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1128 if (err) { 1129 err = -err; 1130 goto error; 1131 } 1132 /* Check relax ordering support. */ 1133 if (config->hca_attr.relaxed_ordering_write && 1134 config->hca_attr.relaxed_ordering_read && 1135 !haswell_broadwell_cpu) 1136 sh->cmng.relaxed_ordering = 1; 1137 /* Check for LRO support. */ 1138 if (config->dest_tir && config->hca_attr.lro_cap && 1139 config->dv_flow_en) { 1140 /* TBD check tunnel lro caps. */ 1141 config->lro.supported = config->hca_attr.lro_cap; 1142 DRV_LOG(DEBUG, "Device supports LRO"); 1143 /* 1144 * If LRO timeout is not configured by application, 1145 * use the minimal supported value. 1146 */ 1147 if (!config->lro.timeout) 1148 config->lro.timeout = 1149 config->hca_attr.lro_timer_supported_periods[0]; 1150 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1151 config->lro.timeout); 1152 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1153 "required for coalescing is %d bytes", 1154 config->hca_attr.lro_min_mss_size); 1155 } 1156 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1157 if (config->hca_attr.qos.sup && 1158 config->hca_attr.qos.srtcm_sup && 1159 config->dv_flow_en) { 1160 uint8_t reg_c_mask = 1161 config->hca_attr.qos.flow_meter_reg_c_ids; 1162 /* 1163 * Meter needs two REG_C's for color match and pre-sfx 1164 * flow match. Here get the REG_C for color match. 1165 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1166 */ 1167 reg_c_mask &= 0xfc; 1168 if (__builtin_popcount(reg_c_mask) < 1) { 1169 priv->mtr_en = 0; 1170 DRV_LOG(WARNING, "No available register for" 1171 " meter."); 1172 } else { 1173 priv->mtr_color_reg = ffs(reg_c_mask) - 1 + 1174 REG_C_0; 1175 priv->mtr_en = 1; 1176 priv->mtr_reg_share = 1177 config->hca_attr.qos.flow_meter_reg_share; 1178 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1179 priv->mtr_color_reg); 1180 } 1181 } 1182 #endif 1183 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1184 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1185 config->dv_flow_en) { 1186 priv->sampler_en = 1; 1187 DRV_LOG(DEBUG, "The Sampler enabled!\n"); 1188 } else { 1189 priv->sampler_en = 0; 1190 if (!config->hca_attr.log_max_ft_sampler_num) 1191 DRV_LOG(WARNING, "No available register for" 1192 " Sampler."); 1193 else 1194 DRV_LOG(DEBUG, "DV flow is not supported!\n"); 1195 } 1196 #endif 1197 } 1198 if (config->tx_pp) { 1199 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1200 config->hca_attr.dev_freq_khz); 1201 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1202 config->hca_attr.qos.packet_pacing ? "" : "not "); 1203 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1204 config->hca_attr.cross_channel ? "" : "not "); 1205 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1206 config->hca_attr.wqe_index_ignore ? "" : "not "); 1207 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1208 config->hca_attr.non_wire_sq ? "" : "not "); 1209 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1210 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1211 config->hca_attr.log_max_static_sq_wq); 1212 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1213 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1214 if (!config->devx) { 1215 DRV_LOG(ERR, "DevX is required for packet pacing"); 1216 err = ENODEV; 1217 goto error; 1218 } 1219 if (!config->hca_attr.qos.packet_pacing) { 1220 DRV_LOG(ERR, "Packet pacing is not supported"); 1221 err = ENODEV; 1222 goto error; 1223 } 1224 if (!config->hca_attr.cross_channel) { 1225 DRV_LOG(ERR, "Cross channel operations are" 1226 " required for packet pacing"); 1227 err = ENODEV; 1228 goto error; 1229 } 1230 if (!config->hca_attr.wqe_index_ignore) { 1231 DRV_LOG(ERR, "WQE index ignore feature is" 1232 " required for packet pacing"); 1233 err = ENODEV; 1234 goto error; 1235 } 1236 if (!config->hca_attr.non_wire_sq) { 1237 DRV_LOG(ERR, "Non-wire SQ feature is" 1238 " required for packet pacing"); 1239 err = ENODEV; 1240 goto error; 1241 } 1242 if (!config->hca_attr.log_max_static_sq_wq) { 1243 DRV_LOG(ERR, "Static WQE SQ feature is" 1244 " required for packet pacing"); 1245 err = ENODEV; 1246 goto error; 1247 } 1248 if (!config->hca_attr.qos.wqe_rate_pp) { 1249 DRV_LOG(ERR, "WQE rate mode is required" 1250 " for packet pacing"); 1251 err = ENODEV; 1252 goto error; 1253 } 1254 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1255 DRV_LOG(ERR, "DevX does not provide UAR offset," 1256 " can't create queues for packet pacing"); 1257 err = ENODEV; 1258 goto error; 1259 #endif 1260 } 1261 if (config->devx) { 1262 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1263 1264 err = config->hca_attr.access_register_user ? 1265 mlx5_devx_cmd_register_read 1266 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1267 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1268 if (!err) { 1269 uint32_t ts_mode; 1270 1271 /* MTUTC register is read successfully. */ 1272 ts_mode = MLX5_GET(register_mtutc, reg, 1273 time_stamp_mode); 1274 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1275 config->rt_timestamp = 1; 1276 } else { 1277 /* Kernel does not support register reading. */ 1278 if (config->hca_attr.dev_freq_khz == 1279 (NS_PER_S / MS_PER_S)) 1280 config->rt_timestamp = 1; 1281 } 1282 } 1283 /* 1284 * If HW has bug working with tunnel packet decapsulation and 1285 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1286 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1287 */ 1288 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1289 config->hw_fcs_strip = 0; 1290 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1291 (config->hw_fcs_strip ? "" : "not ")); 1292 if (config->mprq.enabled && mprq) { 1293 if (config->mprq.stride_num_n && 1294 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1295 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1296 config->mprq.stride_num_n = 1297 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1298 mprq_min_stride_num_n), 1299 mprq_max_stride_num_n); 1300 DRV_LOG(WARNING, 1301 "the number of strides" 1302 " for Multi-Packet RQ is out of range," 1303 " setting default value (%u)", 1304 1 << config->mprq.stride_num_n); 1305 } 1306 if (config->mprq.stride_size_n && 1307 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1308 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1309 config->mprq.stride_size_n = 1310 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1311 mprq_min_stride_size_n), 1312 mprq_max_stride_size_n); 1313 DRV_LOG(WARNING, 1314 "the size of a stride" 1315 " for Multi-Packet RQ is out of range," 1316 " setting default value (%u)", 1317 1 << config->mprq.stride_size_n); 1318 } 1319 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1320 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1321 } else if (config->mprq.enabled && !mprq) { 1322 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1323 config->mprq.enabled = 0; 1324 } 1325 if (config->max_dump_files_num == 0) 1326 config->max_dump_files_num = 128; 1327 eth_dev = rte_eth_dev_allocate(name); 1328 if (eth_dev == NULL) { 1329 DRV_LOG(ERR, "can not allocate rte ethdev"); 1330 err = ENOMEM; 1331 goto error; 1332 } 1333 if (priv->representor) { 1334 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1335 eth_dev->data->representor_id = priv->representor_id; 1336 } 1337 /* 1338 * Store associated network device interface index. This index 1339 * is permanent throughout the lifetime of device. So, we may store 1340 * the ifindex here and use the cached value further. 1341 */ 1342 MLX5_ASSERT(spawn->ifindex); 1343 priv->if_index = spawn->ifindex; 1344 if (priv->pf_bond >= 0 && priv->master) { 1345 /* Get bond interface info */ 1346 err = mlx5_sysfs_bond_info(priv->if_index, 1347 &priv->bond_ifindex, 1348 priv->bond_name); 1349 if (err) 1350 DRV_LOG(ERR, "unable to get bond info: %s", 1351 strerror(rte_errno)); 1352 else 1353 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1354 priv->if_index, priv->bond_ifindex, 1355 priv->bond_name); 1356 } 1357 eth_dev->data->dev_private = priv; 1358 priv->dev_data = eth_dev->data; 1359 eth_dev->data->mac_addrs = priv->mac; 1360 eth_dev->device = dpdk_dev; 1361 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1362 /* Configure the first MAC address by default. */ 1363 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1364 DRV_LOG(ERR, 1365 "port %u cannot get MAC address, is mlx5_en" 1366 " loaded? (errno: %s)", 1367 eth_dev->data->port_id, strerror(rte_errno)); 1368 err = ENODEV; 1369 goto error; 1370 } 1371 DRV_LOG(INFO, 1372 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1373 eth_dev->data->port_id, 1374 mac.addr_bytes[0], mac.addr_bytes[1], 1375 mac.addr_bytes[2], mac.addr_bytes[3], 1376 mac.addr_bytes[4], mac.addr_bytes[5]); 1377 #ifdef RTE_LIBRTE_MLX5_DEBUG 1378 { 1379 char ifname[IF_NAMESIZE]; 1380 1381 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1382 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1383 eth_dev->data->port_id, ifname); 1384 else 1385 DRV_LOG(DEBUG, "port %u ifname is unknown", 1386 eth_dev->data->port_id); 1387 } 1388 #endif 1389 /* Get actual MTU if possible. */ 1390 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1391 if (err) { 1392 err = rte_errno; 1393 goto error; 1394 } 1395 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1396 priv->mtu); 1397 /* Initialize burst functions to prevent crashes before link-up. */ 1398 eth_dev->rx_pkt_burst = removed_rx_burst; 1399 eth_dev->tx_pkt_burst = removed_tx_burst; 1400 eth_dev->dev_ops = &mlx5_os_dev_ops; 1401 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1402 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1403 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1404 /* Register MAC address. */ 1405 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1406 if (config->vf && config->vf_nl_en) 1407 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1408 mlx5_ifindex(eth_dev), 1409 eth_dev->data->mac_addrs, 1410 MLX5_MAX_MAC_ADDRESSES); 1411 priv->flows = 0; 1412 priv->ctrl_flows = 0; 1413 rte_spinlock_init(&priv->flow_list_lock); 1414 TAILQ_INIT(&priv->flow_meters); 1415 TAILQ_INIT(&priv->flow_meter_profiles); 1416 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1417 mlx5_glue->dv_set_context_attr(sh->ctx, 1418 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1419 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1420 .alloc = &mlx5_alloc_verbs_buf, 1421 .free = &mlx5_free_verbs_buf, 1422 .data = priv, 1423 })); 1424 /* Bring Ethernet device up. */ 1425 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1426 eth_dev->data->port_id); 1427 mlx5_set_link_up(eth_dev); 1428 /* 1429 * Even though the interrupt handler is not installed yet, 1430 * interrupts will still trigger on the async_fd from 1431 * Verbs context returned by ibv_open_device(). 1432 */ 1433 mlx5_link_update(eth_dev, 0); 1434 #ifdef HAVE_MLX5DV_DR_ESWITCH 1435 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1436 (switch_info->representor || switch_info->master))) 1437 config->dv_esw_en = 0; 1438 #else 1439 config->dv_esw_en = 0; 1440 #endif 1441 /* Detect minimal data bytes to inline. */ 1442 mlx5_set_min_inline(spawn, config); 1443 /* Store device configuration on private structure. */ 1444 priv->config = *config; 1445 /* Create context for virtual machine VLAN workaround. */ 1446 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1447 if (config->dv_flow_en) { 1448 err = mlx5_alloc_shared_dr(priv); 1449 if (err) 1450 goto error; 1451 } 1452 if (config->devx && config->dv_flow_en && config->dest_tir) { 1453 priv->obj_ops = devx_obj_ops; 1454 priv->obj_ops.drop_action_create = 1455 ibv_obj_ops.drop_action_create; 1456 priv->obj_ops.drop_action_destroy = 1457 ibv_obj_ops.drop_action_destroy; 1458 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1459 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1460 #else 1461 if (config->dv_esw_en) 1462 priv->obj_ops.txq_obj_modify = 1463 ibv_obj_ops.txq_obj_modify; 1464 #endif 1465 /* Use specific wrappers for Tx object. */ 1466 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1467 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1468 1469 } else { 1470 priv->obj_ops = ibv_obj_ops; 1471 } 1472 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1473 if (!priv->drop_queue.hrxq) 1474 goto error; 1475 /* Supported Verbs flow priority number detection. */ 1476 err = mlx5_flow_discover_priorities(eth_dev); 1477 if (err < 0) { 1478 err = -err; 1479 goto error; 1480 } 1481 priv->config.flow_prio = err; 1482 if (!priv->config.dv_esw_en && 1483 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1484 DRV_LOG(WARNING, "metadata mode %u is not supported " 1485 "(no E-Switch)", priv->config.dv_xmeta_en); 1486 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1487 } 1488 mlx5_set_metadata_mask(eth_dev); 1489 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1490 !priv->sh->dv_regc0_mask) { 1491 DRV_LOG(ERR, "metadata mode %u is not supported " 1492 "(no metadata reg_c[0] is available)", 1493 priv->config.dv_xmeta_en); 1494 err = ENOTSUP; 1495 goto error; 1496 } 1497 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 1498 mlx5_hrxq_create_cb, 1499 mlx5_hrxq_match_cb, 1500 mlx5_hrxq_remove_cb); 1501 /* Query availability of metadata reg_c's. */ 1502 err = mlx5_flow_discover_mreg_c(eth_dev); 1503 if (err < 0) { 1504 err = -err; 1505 goto error; 1506 } 1507 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1508 DRV_LOG(DEBUG, 1509 "port %u extensive metadata register is not supported", 1510 eth_dev->data->port_id); 1511 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1512 DRV_LOG(ERR, "metadata mode %u is not supported " 1513 "(no metadata registers available)", 1514 priv->config.dv_xmeta_en); 1515 err = ENOTSUP; 1516 goto error; 1517 } 1518 } 1519 if (priv->config.dv_flow_en && 1520 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1521 mlx5_flow_ext_mreg_supported(eth_dev) && 1522 priv->sh->dv_regc0_mask) { 1523 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1524 MLX5_FLOW_MREG_HTABLE_SZ, 1525 0, 0, 1526 flow_dv_mreg_create_cb, 1527 NULL, 1528 flow_dv_mreg_remove_cb); 1529 if (!priv->mreg_cp_tbl) { 1530 err = ENOMEM; 1531 goto error; 1532 } 1533 priv->mreg_cp_tbl->ctx = eth_dev; 1534 } 1535 rte_spinlock_init(&priv->shared_act_sl); 1536 mlx5_flow_counter_mode_config(eth_dev); 1537 if (priv->config.dv_flow_en) 1538 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1539 return eth_dev; 1540 error: 1541 if (priv) { 1542 if (priv->mreg_cp_tbl) 1543 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1544 if (priv->sh) 1545 mlx5_os_free_shared_dr(priv); 1546 if (priv->nl_socket_route >= 0) 1547 close(priv->nl_socket_route); 1548 if (priv->nl_socket_rdma >= 0) 1549 close(priv->nl_socket_rdma); 1550 if (priv->vmwa_context) 1551 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1552 if (eth_dev && priv->drop_queue.hrxq) 1553 mlx5_drop_action_destroy(eth_dev); 1554 if (own_domain_id) 1555 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1556 mlx5_cache_list_destroy(&priv->hrxqs); 1557 mlx5_free(priv); 1558 if (eth_dev != NULL) 1559 eth_dev->data->dev_private = NULL; 1560 } 1561 if (eth_dev != NULL) { 1562 /* mac_addrs must not be freed alone because part of 1563 * dev_private 1564 **/ 1565 eth_dev->data->mac_addrs = NULL; 1566 rte_eth_dev_release_port(eth_dev); 1567 } 1568 if (sh) 1569 mlx5_free_shared_dev_ctx(sh); 1570 MLX5_ASSERT(err > 0); 1571 rte_errno = err; 1572 return NULL; 1573 } 1574 1575 /** 1576 * Comparison callback to sort device data. 1577 * 1578 * This is meant to be used with qsort(). 1579 * 1580 * @param a[in] 1581 * Pointer to pointer to first data object. 1582 * @param b[in] 1583 * Pointer to pointer to second data object. 1584 * 1585 * @return 1586 * 0 if both objects are equal, less than 0 if the first argument is less 1587 * than the second, greater than 0 otherwise. 1588 */ 1589 static int 1590 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1591 { 1592 const struct mlx5_switch_info *si_a = 1593 &((const struct mlx5_dev_spawn_data *)a)->info; 1594 const struct mlx5_switch_info *si_b = 1595 &((const struct mlx5_dev_spawn_data *)b)->info; 1596 int ret; 1597 1598 /* Master device first. */ 1599 ret = si_b->master - si_a->master; 1600 if (ret) 1601 return ret; 1602 /* Then representor devices. */ 1603 ret = si_b->representor - si_a->representor; 1604 if (ret) 1605 return ret; 1606 /* Unidentified devices come last in no specific order. */ 1607 if (!si_a->representor) 1608 return 0; 1609 /* Order representors by name. */ 1610 return si_a->port_name - si_b->port_name; 1611 } 1612 1613 /** 1614 * Match PCI information for possible slaves of bonding device. 1615 * 1616 * @param[in] ibv_dev 1617 * Pointer to Infiniband device structure. 1618 * @param[in] pci_dev 1619 * Pointer to PCI device structure to match PCI address. 1620 * @param[in] nl_rdma 1621 * Netlink RDMA group socket handle. 1622 * 1623 * @return 1624 * negative value if no bonding device found, otherwise 1625 * positive index of slave PF in bonding. 1626 */ 1627 static int 1628 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1629 const struct rte_pci_device *pci_dev, 1630 int nl_rdma) 1631 { 1632 char ifname[IF_NAMESIZE + 1]; 1633 unsigned int ifindex; 1634 unsigned int np, i; 1635 FILE *file = NULL; 1636 int pf = -1; 1637 1638 /* 1639 * Try to get master device name. If something goes 1640 * wrong suppose the lack of kernel support and no 1641 * bonding devices. 1642 */ 1643 if (nl_rdma < 0) 1644 return -1; 1645 if (!strstr(ibv_dev->name, "bond")) 1646 return -1; 1647 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1648 if (!np) 1649 return -1; 1650 /* 1651 * The Master device might not be on the predefined 1652 * port (not on port index 1, it is not garanted), 1653 * we have to scan all Infiniband device port and 1654 * find master. 1655 */ 1656 for (i = 1; i <= np; ++i) { 1657 /* Check whether Infiniband port is populated. */ 1658 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1659 if (!ifindex) 1660 continue; 1661 if (!if_indextoname(ifindex, ifname)) 1662 continue; 1663 /* Try to read bonding slave names from sysfs. */ 1664 MKSTR(slaves, 1665 "/sys/class/net/%s/master/bonding/slaves", ifname); 1666 file = fopen(slaves, "r"); 1667 if (file) 1668 break; 1669 } 1670 if (!file) 1671 return -1; 1672 /* Use safe format to check maximal buffer length. */ 1673 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1674 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1675 char tmp_str[IF_NAMESIZE + 32]; 1676 struct rte_pci_addr pci_addr; 1677 struct mlx5_switch_info info; 1678 1679 /* Process slave interface names in the loop. */ 1680 snprintf(tmp_str, sizeof(tmp_str), 1681 "/sys/class/net/%s", ifname); 1682 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1683 DRV_LOG(WARNING, "can not get PCI address" 1684 " for netdev \"%s\"", ifname); 1685 continue; 1686 } 1687 if (pci_dev->addr.domain != pci_addr.domain || 1688 pci_dev->addr.bus != pci_addr.bus || 1689 pci_dev->addr.devid != pci_addr.devid || 1690 pci_dev->addr.function != pci_addr.function) 1691 continue; 1692 /* Slave interface PCI address match found. */ 1693 fclose(file); 1694 snprintf(tmp_str, sizeof(tmp_str), 1695 "/sys/class/net/%s/phys_port_name", ifname); 1696 file = fopen(tmp_str, "rb"); 1697 if (!file) 1698 break; 1699 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1700 if (fscanf(file, "%32s", tmp_str) == 1) 1701 mlx5_translate_port_name(tmp_str, &info); 1702 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 1703 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1704 pf = info.port_name; 1705 break; 1706 } 1707 if (file) 1708 fclose(file); 1709 return pf; 1710 } 1711 1712 /** 1713 * DPDK callback to register a PCI device. 1714 * 1715 * This function spawns Ethernet devices out of a given PCI device. 1716 * 1717 * @param[in] pci_drv 1718 * PCI driver structure (mlx5_driver). 1719 * @param[in] pci_dev 1720 * PCI device information. 1721 * 1722 * @return 1723 * 0 on success, a negative errno value otherwise and rte_errno is set. 1724 */ 1725 int 1726 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1727 struct rte_pci_device *pci_dev) 1728 { 1729 struct ibv_device **ibv_list; 1730 /* 1731 * Number of found IB Devices matching with requested PCI BDF. 1732 * nd != 1 means there are multiple IB devices over the same 1733 * PCI device and we have representors and master. 1734 */ 1735 unsigned int nd = 0; 1736 /* 1737 * Number of found IB device Ports. nd = 1 and np = 1..n means 1738 * we have the single multiport IB device, and there may be 1739 * representors attached to some of found ports. 1740 */ 1741 unsigned int np = 0; 1742 /* 1743 * Number of DPDK ethernet devices to Spawn - either over 1744 * multiple IB devices or multiple ports of single IB device. 1745 * Actually this is the number of iterations to spawn. 1746 */ 1747 unsigned int ns = 0; 1748 /* 1749 * Bonding device 1750 * < 0 - no bonding device (single one) 1751 * >= 0 - bonding device (value is slave PF index) 1752 */ 1753 int bd = -1; 1754 struct mlx5_dev_spawn_data *list = NULL; 1755 struct mlx5_dev_config dev_config; 1756 unsigned int dev_config_vf; 1757 int ret; 1758 1759 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1760 mlx5_pmd_socket_init(); 1761 ret = mlx5_init_once(); 1762 if (ret) { 1763 DRV_LOG(ERR, "unable to init PMD global data: %s", 1764 strerror(rte_errno)); 1765 return -rte_errno; 1766 } 1767 errno = 0; 1768 ibv_list = mlx5_glue->get_device_list(&ret); 1769 if (!ibv_list) { 1770 rte_errno = errno ? errno : ENOSYS; 1771 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1772 return -rte_errno; 1773 } 1774 /* 1775 * First scan the list of all Infiniband devices to find 1776 * matching ones, gathering into the list. 1777 */ 1778 struct ibv_device *ibv_match[ret + 1]; 1779 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1780 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1781 unsigned int i; 1782 1783 while (ret-- > 0) { 1784 struct rte_pci_addr pci_addr; 1785 1786 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1787 bd = mlx5_device_bond_pci_match 1788 (ibv_list[ret], pci_dev, nl_rdma); 1789 if (bd >= 0) { 1790 /* 1791 * Bonding device detected. Only one match is allowed, 1792 * the bonding is supported over multi-port IB device, 1793 * there should be no matches on representor PCI 1794 * functions or non VF LAG bonding devices with 1795 * specified address. 1796 */ 1797 if (nd) { 1798 DRV_LOG(ERR, 1799 "multiple PCI match on bonding device" 1800 "\"%s\" found", ibv_list[ret]->name); 1801 rte_errno = ENOENT; 1802 ret = -rte_errno; 1803 goto exit; 1804 } 1805 DRV_LOG(INFO, "PCI information matches for" 1806 " slave %d bonding device \"%s\"", 1807 bd, ibv_list[ret]->name); 1808 ibv_match[nd++] = ibv_list[ret]; 1809 break; 1810 } 1811 if (mlx5_dev_to_pci_addr 1812 (ibv_list[ret]->ibdev_path, &pci_addr)) 1813 continue; 1814 if (pci_dev->addr.domain != pci_addr.domain || 1815 pci_dev->addr.bus != pci_addr.bus || 1816 pci_dev->addr.devid != pci_addr.devid || 1817 pci_dev->addr.function != pci_addr.function) 1818 continue; 1819 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1820 ibv_list[ret]->name); 1821 ibv_match[nd++] = ibv_list[ret]; 1822 } 1823 ibv_match[nd] = NULL; 1824 if (!nd) { 1825 /* No device matches, just complain and bail out. */ 1826 DRV_LOG(WARNING, 1827 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1828 " are kernel drivers loaded?", 1829 pci_dev->addr.domain, pci_dev->addr.bus, 1830 pci_dev->addr.devid, pci_dev->addr.function); 1831 rte_errno = ENOENT; 1832 ret = -rte_errno; 1833 goto exit; 1834 } 1835 if (nd == 1) { 1836 /* 1837 * Found single matching device may have multiple ports. 1838 * Each port may be representor, we have to check the port 1839 * number and check the representors existence. 1840 */ 1841 if (nl_rdma >= 0) 1842 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1843 if (!np) 1844 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1845 " ports number", ibv_match[0]->name); 1846 if (bd >= 0 && !np) { 1847 DRV_LOG(ERR, "can not get ports" 1848 " for bonding device"); 1849 rte_errno = ENOENT; 1850 ret = -rte_errno; 1851 goto exit; 1852 } 1853 } 1854 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 1855 if (bd >= 0) { 1856 /* 1857 * This may happen if there is VF LAG kernel support and 1858 * application is compiled with older rdma_core library. 1859 */ 1860 DRV_LOG(ERR, 1861 "No kernel/verbs support for VF LAG bonding found."); 1862 rte_errno = ENOTSUP; 1863 ret = -rte_errno; 1864 goto exit; 1865 } 1866 #endif 1867 /* 1868 * Now we can determine the maximal 1869 * amount of devices to be spawned. 1870 */ 1871 list = mlx5_malloc(MLX5_MEM_ZERO, 1872 sizeof(struct mlx5_dev_spawn_data) * 1873 (np ? np : nd), 1874 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1875 if (!list) { 1876 DRV_LOG(ERR, "spawn data array allocation failure"); 1877 rte_errno = ENOMEM; 1878 ret = -rte_errno; 1879 goto exit; 1880 } 1881 if (bd >= 0 || np > 1) { 1882 /* 1883 * Single IB device with multiple ports found, 1884 * it may be E-Switch master device and representors. 1885 * We have to perform identification through the ports. 1886 */ 1887 MLX5_ASSERT(nl_rdma >= 0); 1888 MLX5_ASSERT(ns == 0); 1889 MLX5_ASSERT(nd == 1); 1890 MLX5_ASSERT(np); 1891 for (i = 1; i <= np; ++i) { 1892 list[ns].max_port = np; 1893 list[ns].phys_port = i; 1894 list[ns].phys_dev = ibv_match[0]; 1895 list[ns].eth_dev = NULL; 1896 list[ns].pci_dev = pci_dev; 1897 list[ns].pf_bond = bd; 1898 list[ns].ifindex = mlx5_nl_ifindex 1899 (nl_rdma, 1900 mlx5_os_get_dev_device_name 1901 (list[ns].phys_dev), i); 1902 if (!list[ns].ifindex) { 1903 /* 1904 * No network interface index found for the 1905 * specified port, it means there is no 1906 * representor on this port. It's OK, 1907 * there can be disabled ports, for example 1908 * if sriov_numvfs < sriov_totalvfs. 1909 */ 1910 continue; 1911 } 1912 ret = -1; 1913 if (nl_route >= 0) 1914 ret = mlx5_nl_switch_info 1915 (nl_route, 1916 list[ns].ifindex, 1917 &list[ns].info); 1918 if (ret || (!list[ns].info.representor && 1919 !list[ns].info.master)) { 1920 /* 1921 * We failed to recognize representors with 1922 * Netlink, let's try to perform the task 1923 * with sysfs. 1924 */ 1925 ret = mlx5_sysfs_switch_info 1926 (list[ns].ifindex, 1927 &list[ns].info); 1928 } 1929 if (!ret && bd >= 0) { 1930 switch (list[ns].info.name_type) { 1931 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 1932 if (list[ns].info.port_name == bd) 1933 ns++; 1934 break; 1935 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 1936 /* Fallthrough */ 1937 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 1938 if (list[ns].info.pf_num == bd) 1939 ns++; 1940 break; 1941 default: 1942 break; 1943 } 1944 continue; 1945 } 1946 if (!ret && (list[ns].info.representor ^ 1947 list[ns].info.master)) 1948 ns++; 1949 } 1950 if (!ns) { 1951 DRV_LOG(ERR, 1952 "unable to recognize master/representors" 1953 " on the IB device with multiple ports"); 1954 rte_errno = ENOENT; 1955 ret = -rte_errno; 1956 goto exit; 1957 } 1958 } else { 1959 /* 1960 * The existence of several matching entries (nd > 1) means 1961 * port representors have been instantiated. No existing Verbs 1962 * call nor sysfs entries can tell them apart, this can only 1963 * be done through Netlink calls assuming kernel drivers are 1964 * recent enough to support them. 1965 * 1966 * In the event of identification failure through Netlink, 1967 * try again through sysfs, then: 1968 * 1969 * 1. A single IB device matches (nd == 1) with single 1970 * port (np=0/1) and is not a representor, assume 1971 * no switch support. 1972 * 1973 * 2. Otherwise no safe assumptions can be made; 1974 * complain louder and bail out. 1975 */ 1976 for (i = 0; i != nd; ++i) { 1977 memset(&list[ns].info, 0, sizeof(list[ns].info)); 1978 list[ns].max_port = 1; 1979 list[ns].phys_port = 1; 1980 list[ns].phys_dev = ibv_match[i]; 1981 list[ns].eth_dev = NULL; 1982 list[ns].pci_dev = pci_dev; 1983 list[ns].pf_bond = -1; 1984 list[ns].ifindex = 0; 1985 if (nl_rdma >= 0) 1986 list[ns].ifindex = mlx5_nl_ifindex 1987 (nl_rdma, 1988 mlx5_os_get_dev_device_name 1989 (list[ns].phys_dev), 1); 1990 if (!list[ns].ifindex) { 1991 char ifname[IF_NAMESIZE]; 1992 1993 /* 1994 * Netlink failed, it may happen with old 1995 * ib_core kernel driver (before 4.16). 1996 * We can assume there is old driver because 1997 * here we are processing single ports IB 1998 * devices. Let's try sysfs to retrieve 1999 * the ifindex. The method works for 2000 * master device only. 2001 */ 2002 if (nd > 1) { 2003 /* 2004 * Multiple devices found, assume 2005 * representors, can not distinguish 2006 * master/representor and retrieve 2007 * ifindex via sysfs. 2008 */ 2009 continue; 2010 } 2011 ret = mlx5_get_ifname_sysfs 2012 (ibv_match[i]->ibdev_path, ifname); 2013 if (!ret) 2014 list[ns].ifindex = 2015 if_nametoindex(ifname); 2016 if (!list[ns].ifindex) { 2017 /* 2018 * No network interface index found 2019 * for the specified device, it means 2020 * there it is neither representor 2021 * nor master. 2022 */ 2023 continue; 2024 } 2025 } 2026 ret = -1; 2027 if (nl_route >= 0) 2028 ret = mlx5_nl_switch_info 2029 (nl_route, 2030 list[ns].ifindex, 2031 &list[ns].info); 2032 if (ret || (!list[ns].info.representor && 2033 !list[ns].info.master)) { 2034 /* 2035 * We failed to recognize representors with 2036 * Netlink, let's try to perform the task 2037 * with sysfs. 2038 */ 2039 ret = mlx5_sysfs_switch_info 2040 (list[ns].ifindex, 2041 &list[ns].info); 2042 } 2043 if (!ret && (list[ns].info.representor ^ 2044 list[ns].info.master)) { 2045 ns++; 2046 } else if ((nd == 1) && 2047 !list[ns].info.representor && 2048 !list[ns].info.master) { 2049 /* 2050 * Single IB device with 2051 * one physical port and 2052 * attached network device. 2053 * May be SRIOV is not enabled 2054 * or there is no representors. 2055 */ 2056 DRV_LOG(INFO, "no E-Switch support detected"); 2057 ns++; 2058 break; 2059 } 2060 } 2061 if (!ns) { 2062 DRV_LOG(ERR, 2063 "unable to recognize master/representors" 2064 " on the multiple IB devices"); 2065 rte_errno = ENOENT; 2066 ret = -rte_errno; 2067 goto exit; 2068 } 2069 } 2070 MLX5_ASSERT(ns); 2071 /* 2072 * Sort list to probe devices in natural order for users convenience 2073 * (i.e. master first, then representors from lowest to highest ID). 2074 */ 2075 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2076 /* Device specific configuration. */ 2077 switch (pci_dev->id.device_id) { 2078 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2079 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2080 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2081 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2082 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2083 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2084 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF: 2085 dev_config_vf = 1; 2086 break; 2087 default: 2088 dev_config_vf = 0; 2089 break; 2090 } 2091 for (i = 0; i != ns; ++i) { 2092 uint32_t restore; 2093 2094 /* Default configuration. */ 2095 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2096 dev_config.vf = dev_config_vf; 2097 dev_config.mps = MLX5_ARG_UNSET; 2098 dev_config.dbnc = MLX5_ARG_UNSET; 2099 dev_config.rx_vec_en = 1; 2100 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2101 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2102 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2103 dev_config.txqs_inline = MLX5_ARG_UNSET; 2104 dev_config.vf_nl_en = 1; 2105 dev_config.mr_ext_memseg_en = 1; 2106 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2107 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2108 dev_config.dv_esw_en = 1; 2109 dev_config.dv_flow_en = 1; 2110 dev_config.decap_en = 1; 2111 dev_config.log_hp_size = MLX5_ARG_UNSET; 2112 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2113 &list[i], 2114 &dev_config); 2115 if (!list[i].eth_dev) { 2116 if (rte_errno != EBUSY && rte_errno != EEXIST) 2117 break; 2118 /* Device is disabled or already spawned. Ignore it. */ 2119 continue; 2120 } 2121 restore = list[i].eth_dev->data->dev_flags; 2122 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2123 /* Restore non-PCI flags cleared by the above call. */ 2124 list[i].eth_dev->data->dev_flags |= restore; 2125 rte_eth_dev_probing_finish(list[i].eth_dev); 2126 } 2127 if (i != ns) { 2128 DRV_LOG(ERR, 2129 "probe of PCI device " PCI_PRI_FMT " aborted after" 2130 " encountering an error: %s", 2131 pci_dev->addr.domain, pci_dev->addr.bus, 2132 pci_dev->addr.devid, pci_dev->addr.function, 2133 strerror(rte_errno)); 2134 ret = -rte_errno; 2135 /* Roll back. */ 2136 while (i--) { 2137 if (!list[i].eth_dev) 2138 continue; 2139 mlx5_dev_close(list[i].eth_dev); 2140 /* mac_addrs must not be freed because in dev_private */ 2141 list[i].eth_dev->data->mac_addrs = NULL; 2142 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2143 } 2144 /* Restore original error. */ 2145 rte_errno = -ret; 2146 } else { 2147 ret = 0; 2148 } 2149 exit: 2150 /* 2151 * Do the routine cleanup: 2152 * - close opened Netlink sockets 2153 * - free allocated spawn data array 2154 * - free the Infiniband device list 2155 */ 2156 if (nl_rdma >= 0) 2157 close(nl_rdma); 2158 if (nl_route >= 0) 2159 close(nl_route); 2160 if (list) 2161 mlx5_free(list); 2162 MLX5_ASSERT(ibv_list); 2163 mlx5_glue->free_device_list(ibv_list); 2164 return ret; 2165 } 2166 2167 static int 2168 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2169 { 2170 char *env; 2171 int value; 2172 2173 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2174 /* Get environment variable to store. */ 2175 env = getenv(MLX5_SHUT_UP_BF); 2176 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2177 if (config->dbnc == MLX5_ARG_UNSET) 2178 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2179 else 2180 setenv(MLX5_SHUT_UP_BF, 2181 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2182 return value; 2183 } 2184 2185 static void 2186 mlx5_restore_doorbell_mapping_env(int value) 2187 { 2188 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2189 /* Restore the original environment variable state. */ 2190 if (value == MLX5_ARG_UNSET) 2191 unsetenv(MLX5_SHUT_UP_BF); 2192 else 2193 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2194 } 2195 2196 /** 2197 * Extract pdn of PD object using DV API. 2198 * 2199 * @param[in] pd 2200 * Pointer to the verbs PD object. 2201 * @param[out] pdn 2202 * Pointer to the PD object number variable. 2203 * 2204 * @return 2205 * 0 on success, error value otherwise. 2206 */ 2207 int 2208 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2209 { 2210 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2211 struct mlx5dv_obj obj; 2212 struct mlx5dv_pd pd_info; 2213 int ret = 0; 2214 2215 obj.pd.in = pd; 2216 obj.pd.out = &pd_info; 2217 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2218 if (ret) { 2219 DRV_LOG(DEBUG, "Fail to get PD object info"); 2220 return ret; 2221 } 2222 *pdn = pd_info.pdn; 2223 return 0; 2224 #else 2225 (void)pd; 2226 (void)pdn; 2227 return -ENOTSUP; 2228 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2229 } 2230 2231 /** 2232 * Function API to open IB device. 2233 * 2234 * This function calls the Linux glue APIs to open a device. 2235 * 2236 * @param[in] spawn 2237 * Pointer to the IB device attributes (name, port, etc). 2238 * @param[out] config 2239 * Pointer to device configuration structure. 2240 * @param[out] sh 2241 * Pointer to shared context structure. 2242 * 2243 * @return 2244 * 0 on success, a positive error value otherwise. 2245 */ 2246 int 2247 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2248 const struct mlx5_dev_config *config, 2249 struct mlx5_dev_ctx_shared *sh) 2250 { 2251 int dbmap_env; 2252 int err = 0; 2253 2254 sh->numa_node = spawn->pci_dev->device.numa_node; 2255 pthread_mutex_init(&sh->txpp.mutex, NULL); 2256 /* 2257 * Configure environment variable "MLX5_BF_SHUT_UP" 2258 * before the device creation. The rdma_core library 2259 * checks the variable at device creation and 2260 * stores the result internally. 2261 */ 2262 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2263 /* Try to open IB device with DV first, then usual Verbs. */ 2264 errno = 0; 2265 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2266 if (sh->ctx) { 2267 sh->devx = 1; 2268 DRV_LOG(DEBUG, "DevX is supported"); 2269 /* The device is created, no need for environment. */ 2270 mlx5_restore_doorbell_mapping_env(dbmap_env); 2271 } else { 2272 /* The environment variable is still configured. */ 2273 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2274 err = errno ? errno : ENODEV; 2275 /* 2276 * The environment variable is not needed anymore, 2277 * all device creation attempts are completed. 2278 */ 2279 mlx5_restore_doorbell_mapping_env(dbmap_env); 2280 if (!sh->ctx) 2281 return err; 2282 DRV_LOG(DEBUG, "DevX is NOT supported"); 2283 err = 0; 2284 } 2285 return err; 2286 } 2287 2288 /** 2289 * Install shared asynchronous device events handler. 2290 * This function is implemented to support event sharing 2291 * between multiple ports of single IB device. 2292 * 2293 * @param sh 2294 * Pointer to mlx5_dev_ctx_shared object. 2295 */ 2296 void 2297 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2298 { 2299 int ret; 2300 int flags; 2301 2302 sh->intr_handle.fd = -1; 2303 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2304 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2305 F_SETFL, flags | O_NONBLOCK); 2306 if (ret) { 2307 DRV_LOG(INFO, "failed to change file descriptor async event" 2308 " queue"); 2309 } else { 2310 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2311 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2312 if (rte_intr_callback_register(&sh->intr_handle, 2313 mlx5_dev_interrupt_handler, sh)) { 2314 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2315 sh->intr_handle.fd = -1; 2316 } 2317 } 2318 if (sh->devx) { 2319 #ifdef HAVE_IBV_DEVX_ASYNC 2320 sh->intr_handle_devx.fd = -1; 2321 sh->devx_comp = 2322 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2323 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2324 if (!devx_comp) { 2325 DRV_LOG(INFO, "failed to allocate devx_comp."); 2326 return; 2327 } 2328 flags = fcntl(devx_comp->fd, F_GETFL); 2329 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2330 if (ret) { 2331 DRV_LOG(INFO, "failed to change file descriptor" 2332 " devx comp"); 2333 return; 2334 } 2335 sh->intr_handle_devx.fd = devx_comp->fd; 2336 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2337 if (rte_intr_callback_register(&sh->intr_handle_devx, 2338 mlx5_dev_interrupt_handler_devx, sh)) { 2339 DRV_LOG(INFO, "Fail to install the devx shared" 2340 " interrupt."); 2341 sh->intr_handle_devx.fd = -1; 2342 } 2343 #endif /* HAVE_IBV_DEVX_ASYNC */ 2344 } 2345 } 2346 2347 /** 2348 * Uninstall shared asynchronous device events handler. 2349 * This function is implemented to support event sharing 2350 * between multiple ports of single IB device. 2351 * 2352 * @param dev 2353 * Pointer to mlx5_dev_ctx_shared object. 2354 */ 2355 void 2356 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2357 { 2358 if (sh->intr_handle.fd >= 0) 2359 mlx5_intr_callback_unregister(&sh->intr_handle, 2360 mlx5_dev_interrupt_handler, sh); 2361 #ifdef HAVE_IBV_DEVX_ASYNC 2362 if (sh->intr_handle_devx.fd >= 0) 2363 rte_intr_callback_unregister(&sh->intr_handle_devx, 2364 mlx5_dev_interrupt_handler_devx, sh); 2365 if (sh->devx_comp) 2366 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2367 #endif 2368 } 2369 2370 /** 2371 * Read statistics by a named counter. 2372 * 2373 * @param[in] priv 2374 * Pointer to the private device data structure. 2375 * @param[in] ctr_name 2376 * Pointer to the name of the statistic counter to read 2377 * @param[out] stat 2378 * Pointer to read statistic value. 2379 * @return 2380 * 0 on success and stat is valud, 1 if failed to read the value 2381 * rte_errno is set. 2382 * 2383 */ 2384 int 2385 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2386 uint64_t *stat) 2387 { 2388 int fd; 2389 2390 if (priv->sh) { 2391 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2392 priv->sh->ibdev_path, 2393 priv->dev_port, 2394 ctr_name); 2395 fd = open(path, O_RDONLY); 2396 /* 2397 * in switchdev the file location is not per port 2398 * but rather in <ibdev_path>/hw_counters/<file_name>. 2399 */ 2400 if (fd == -1) { 2401 MKSTR(path1, "%s/hw_counters/%s", 2402 priv->sh->ibdev_path, 2403 ctr_name); 2404 fd = open(path1, O_RDONLY); 2405 } 2406 if (fd != -1) { 2407 char buf[21] = {'\0'}; 2408 ssize_t n = read(fd, buf, sizeof(buf)); 2409 2410 close(fd); 2411 if (n != -1) { 2412 *stat = strtoull(buf, NULL, 10); 2413 return 0; 2414 } 2415 } 2416 } 2417 *stat = 0; 2418 return 1; 2419 } 2420 2421 /** 2422 * Set the reg_mr and dereg_mr call backs 2423 * 2424 * @param reg_mr_cb[out] 2425 * Pointer to reg_mr func 2426 * @param dereg_mr_cb[out] 2427 * Pointer to dereg_mr func 2428 * 2429 */ 2430 void 2431 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2432 mlx5_dereg_mr_t *dereg_mr_cb) 2433 { 2434 *reg_mr_cb = mlx5_verbs_ops.reg_mr; 2435 *dereg_mr_cb = mlx5_verbs_ops.dereg_mr; 2436 } 2437 2438 /** 2439 * Remove a MAC address from device 2440 * 2441 * @param dev 2442 * Pointer to Ethernet device structure. 2443 * @param index 2444 * MAC address index. 2445 */ 2446 void 2447 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2448 { 2449 struct mlx5_priv *priv = dev->data->dev_private; 2450 const int vf = priv->config.vf; 2451 2452 if (vf) 2453 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2454 mlx5_ifindex(dev), priv->mac_own, 2455 &dev->data->mac_addrs[index], index); 2456 } 2457 2458 /** 2459 * Adds a MAC address to the device 2460 * 2461 * @param dev 2462 * Pointer to Ethernet device structure. 2463 * @param mac_addr 2464 * MAC address to register. 2465 * @param index 2466 * MAC address index. 2467 * 2468 * @return 2469 * 0 on success, a negative errno value otherwise 2470 */ 2471 int 2472 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2473 uint32_t index) 2474 { 2475 struct mlx5_priv *priv = dev->data->dev_private; 2476 const int vf = priv->config.vf; 2477 int ret = 0; 2478 2479 if (vf) 2480 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2481 mlx5_ifindex(dev), priv->mac_own, 2482 mac, index); 2483 return ret; 2484 } 2485 2486 /** 2487 * Modify a VF MAC address 2488 * 2489 * @param priv 2490 * Pointer to device private data. 2491 * @param mac_addr 2492 * MAC address to modify into. 2493 * @param iface_idx 2494 * Net device interface index 2495 * @param vf_index 2496 * VF index 2497 * 2498 * @return 2499 * 0 on success, a negative errno value otherwise 2500 */ 2501 int 2502 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2503 unsigned int iface_idx, 2504 struct rte_ether_addr *mac_addr, 2505 int vf_index) 2506 { 2507 return mlx5_nl_vf_mac_addr_modify 2508 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2509 } 2510 2511 /** 2512 * Set device promiscuous mode 2513 * 2514 * @param dev 2515 * Pointer to Ethernet device structure. 2516 * @param enable 2517 * 0 - promiscuous is disabled, otherwise - enabled 2518 * 2519 * @return 2520 * 0 on success, a negative error value otherwise 2521 */ 2522 int 2523 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2524 { 2525 struct mlx5_priv *priv = dev->data->dev_private; 2526 2527 return mlx5_nl_promisc(priv->nl_socket_route, 2528 mlx5_ifindex(dev), !!enable); 2529 } 2530 2531 /** 2532 * Set device promiscuous mode 2533 * 2534 * @param dev 2535 * Pointer to Ethernet device structure. 2536 * @param enable 2537 * 0 - all multicase is disabled, otherwise - enabled 2538 * 2539 * @return 2540 * 0 on success, a negative error value otherwise 2541 */ 2542 int 2543 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2544 { 2545 struct mlx5_priv *priv = dev->data->dev_private; 2546 2547 return mlx5_nl_allmulti(priv->nl_socket_route, 2548 mlx5_ifindex(dev), !!enable); 2549 } 2550 2551 /** 2552 * Flush device MAC addresses 2553 * 2554 * @param dev 2555 * Pointer to Ethernet device structure. 2556 * 2557 */ 2558 void 2559 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2560 { 2561 struct mlx5_priv *priv = dev->data->dev_private; 2562 2563 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2564 dev->data->mac_addrs, 2565 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2566 } 2567 2568 const struct eth_dev_ops mlx5_os_dev_ops = { 2569 .dev_configure = mlx5_dev_configure, 2570 .dev_start = mlx5_dev_start, 2571 .dev_stop = mlx5_dev_stop, 2572 .dev_set_link_down = mlx5_set_link_down, 2573 .dev_set_link_up = mlx5_set_link_up, 2574 .dev_close = mlx5_dev_close, 2575 .promiscuous_enable = mlx5_promiscuous_enable, 2576 .promiscuous_disable = mlx5_promiscuous_disable, 2577 .allmulticast_enable = mlx5_allmulticast_enable, 2578 .allmulticast_disable = mlx5_allmulticast_disable, 2579 .link_update = mlx5_link_update, 2580 .stats_get = mlx5_stats_get, 2581 .stats_reset = mlx5_stats_reset, 2582 .xstats_get = mlx5_xstats_get, 2583 .xstats_reset = mlx5_xstats_reset, 2584 .xstats_get_names = mlx5_xstats_get_names, 2585 .fw_version_get = mlx5_fw_version_get, 2586 .dev_infos_get = mlx5_dev_infos_get, 2587 .read_clock = mlx5_txpp_read_clock, 2588 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2589 .vlan_filter_set = mlx5_vlan_filter_set, 2590 .rx_queue_setup = mlx5_rx_queue_setup, 2591 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2592 .tx_queue_setup = mlx5_tx_queue_setup, 2593 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2594 .rx_queue_release = mlx5_rx_queue_release, 2595 .tx_queue_release = mlx5_tx_queue_release, 2596 .rx_queue_start = mlx5_rx_queue_start, 2597 .rx_queue_stop = mlx5_rx_queue_stop, 2598 .tx_queue_start = mlx5_tx_queue_start, 2599 .tx_queue_stop = mlx5_tx_queue_stop, 2600 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2601 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2602 .mac_addr_remove = mlx5_mac_addr_remove, 2603 .mac_addr_add = mlx5_mac_addr_add, 2604 .mac_addr_set = mlx5_mac_addr_set, 2605 .set_mc_addr_list = mlx5_set_mc_addr_list, 2606 .mtu_set = mlx5_dev_set_mtu, 2607 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2608 .vlan_offload_set = mlx5_vlan_offload_set, 2609 .reta_update = mlx5_dev_rss_reta_update, 2610 .reta_query = mlx5_dev_rss_reta_query, 2611 .rss_hash_update = mlx5_rss_hash_update, 2612 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2613 .filter_ctrl = mlx5_dev_filter_ctrl, 2614 .rxq_info_get = mlx5_rxq_info_get, 2615 .txq_info_get = mlx5_txq_info_get, 2616 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2617 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2618 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2619 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2620 .is_removed = mlx5_is_removed, 2621 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2622 .get_module_info = mlx5_get_module_info, 2623 .get_module_eeprom = mlx5_get_module_eeprom, 2624 .hairpin_cap_get = mlx5_hairpin_cap_get, 2625 .mtr_ops_get = mlx5_flow_meter_ops_get, 2626 .hairpin_bind = mlx5_hairpin_bind, 2627 .hairpin_unbind = mlx5_hairpin_unbind, 2628 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2629 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2630 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2631 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2632 }; 2633 2634 /* Available operations from secondary process. */ 2635 const struct eth_dev_ops mlx5_os_dev_sec_ops = { 2636 .stats_get = mlx5_stats_get, 2637 .stats_reset = mlx5_stats_reset, 2638 .xstats_get = mlx5_xstats_get, 2639 .xstats_reset = mlx5_xstats_reset, 2640 .xstats_get_names = mlx5_xstats_get_names, 2641 .fw_version_get = mlx5_fw_version_get, 2642 .dev_infos_get = mlx5_dev_infos_get, 2643 .read_clock = mlx5_txpp_read_clock, 2644 .rx_queue_start = mlx5_rx_queue_start, 2645 .rx_queue_stop = mlx5_rx_queue_stop, 2646 .tx_queue_start = mlx5_tx_queue_start, 2647 .tx_queue_stop = mlx5_tx_queue_stop, 2648 .rxq_info_get = mlx5_rxq_info_get, 2649 .txq_info_get = mlx5_txq_info_get, 2650 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2651 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2652 .get_module_info = mlx5_get_module_info, 2653 .get_module_eeprom = mlx5_get_module_eeprom, 2654 }; 2655 2656 /* Available operations in flow isolated mode. */ 2657 const struct eth_dev_ops mlx5_os_dev_ops_isolate = { 2658 .dev_configure = mlx5_dev_configure, 2659 .dev_start = mlx5_dev_start, 2660 .dev_stop = mlx5_dev_stop, 2661 .dev_set_link_down = mlx5_set_link_down, 2662 .dev_set_link_up = mlx5_set_link_up, 2663 .dev_close = mlx5_dev_close, 2664 .promiscuous_enable = mlx5_promiscuous_enable, 2665 .promiscuous_disable = mlx5_promiscuous_disable, 2666 .allmulticast_enable = mlx5_allmulticast_enable, 2667 .allmulticast_disable = mlx5_allmulticast_disable, 2668 .link_update = mlx5_link_update, 2669 .stats_get = mlx5_stats_get, 2670 .stats_reset = mlx5_stats_reset, 2671 .xstats_get = mlx5_xstats_get, 2672 .xstats_reset = mlx5_xstats_reset, 2673 .xstats_get_names = mlx5_xstats_get_names, 2674 .fw_version_get = mlx5_fw_version_get, 2675 .dev_infos_get = mlx5_dev_infos_get, 2676 .read_clock = mlx5_txpp_read_clock, 2677 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2678 .vlan_filter_set = mlx5_vlan_filter_set, 2679 .rx_queue_setup = mlx5_rx_queue_setup, 2680 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2681 .tx_queue_setup = mlx5_tx_queue_setup, 2682 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2683 .rx_queue_release = mlx5_rx_queue_release, 2684 .tx_queue_release = mlx5_tx_queue_release, 2685 .rx_queue_start = mlx5_rx_queue_start, 2686 .rx_queue_stop = mlx5_rx_queue_stop, 2687 .tx_queue_start = mlx5_tx_queue_start, 2688 .tx_queue_stop = mlx5_tx_queue_stop, 2689 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2690 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2691 .mac_addr_remove = mlx5_mac_addr_remove, 2692 .mac_addr_add = mlx5_mac_addr_add, 2693 .mac_addr_set = mlx5_mac_addr_set, 2694 .set_mc_addr_list = mlx5_set_mc_addr_list, 2695 .mtu_set = mlx5_dev_set_mtu, 2696 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2697 .vlan_offload_set = mlx5_vlan_offload_set, 2698 .filter_ctrl = mlx5_dev_filter_ctrl, 2699 .rxq_info_get = mlx5_rxq_info_get, 2700 .txq_info_get = mlx5_txq_info_get, 2701 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2702 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2703 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2704 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2705 .is_removed = mlx5_is_removed, 2706 .get_module_info = mlx5_get_module_info, 2707 .get_module_eeprom = mlx5_get_module_eeprom, 2708 .hairpin_cap_get = mlx5_hairpin_cap_get, 2709 .mtr_ops_get = mlx5_flow_meter_ops_get, 2710 .hairpin_bind = mlx5_hairpin_bind, 2711 .hairpin_unbind = mlx5_hairpin_unbind, 2712 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2713 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2714 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2715 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2716 }; 2717