1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /* rte flow indexed pool configuration. */ 71 static struct mlx5_indexed_pool_config icfg[] = { 72 { 73 .size = sizeof(struct rte_flow), 74 .trunk_size = 64, 75 .need_lock = 1, 76 .release_mem_en = 0, 77 .malloc = mlx5_malloc, 78 .free = mlx5_free, 79 .per_core_cache = 0, 80 .type = "ctl_flow_ipool", 81 }, 82 { 83 .size = sizeof(struct rte_flow), 84 .trunk_size = 64, 85 .grow_trunk = 3, 86 .grow_shift = 2, 87 .need_lock = 1, 88 .release_mem_en = 0, 89 .malloc = mlx5_malloc, 90 .free = mlx5_free, 91 .per_core_cache = 1 << 14, 92 .type = "rte_flow_ipool", 93 }, 94 { 95 .size = sizeof(struct rte_flow), 96 .trunk_size = 64, 97 .grow_trunk = 3, 98 .grow_shift = 2, 99 .need_lock = 1, 100 .release_mem_en = 0, 101 .malloc = mlx5_malloc, 102 .free = mlx5_free, 103 .per_core_cache = 0, 104 .type = "mcp_flow_ipool", 105 }, 106 }; 107 108 /** 109 * Set the completion channel file descriptor interrupt as non-blocking. 110 * 111 * @param[in] rxq_obj 112 * Pointer to RQ channel object, which includes the channel fd 113 * 114 * @param[out] fd 115 * The file descriptor (representing the intetrrupt) used in this channel. 116 * 117 * @return 118 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 119 */ 120 int 121 mlx5_os_set_nonblock_channel_fd(int fd) 122 { 123 int flags; 124 125 flags = fcntl(fd, F_GETFL); 126 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 127 } 128 129 /** 130 * Get mlx5 device attributes. The glue function query_device_ex() is called 131 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 132 * device attributes from the glue out parameter. 133 * 134 * @param cdev 135 * Pointer to mlx5 device. 136 * 137 * @param device_attr 138 * Pointer to mlx5 device attributes. 139 * 140 * @return 141 * 0 on success, non zero error number otherwise 142 */ 143 int 144 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, 145 struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_context *ctx = cdev->ctx; 149 struct ibv_device_attr_ex attr_ex; 150 151 memset(device_attr, 0, sizeof(*device_attr)); 152 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 153 if (err) 154 return err; 155 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 156 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 157 device_attr->max_sge = attr_ex.orig_attr.max_sge; 158 device_attr->max_cq = attr_ex.orig_attr.max_cq; 159 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 160 device_attr->max_mr = attr_ex.orig_attr.max_mr; 161 device_attr->max_pd = attr_ex.orig_attr.max_pd; 162 device_attr->max_qp = attr_ex.orig_attr.max_qp; 163 device_attr->max_srq = attr_ex.orig_attr.max_srq; 164 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 165 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 166 device_attr->max_rwq_indirection_table_size = 167 attr_ex.rss_caps.max_rwq_indirection_table_size; 168 device_attr->max_tso = attr_ex.tso_caps.max_tso; 169 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 170 171 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 172 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 173 if (err) 174 return err; 175 176 device_attr->flags = dv_attr.flags; 177 device_attr->comp_mask = dv_attr.comp_mask; 178 #ifdef HAVE_IBV_MLX5_MOD_SWP 179 device_attr->sw_parsing_offloads = 180 dv_attr.sw_parsing_caps.sw_parsing_offloads; 181 #endif 182 device_attr->min_single_stride_log_num_of_bytes = 183 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 184 device_attr->max_single_stride_log_num_of_bytes = 185 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 186 device_attr->min_single_wqe_log_num_of_strides = 187 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 188 device_attr->max_single_wqe_log_num_of_strides = 189 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 190 device_attr->stride_supported_qpts = 191 dv_attr.striding_rq_caps.supported_qpts; 192 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 193 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 194 #endif 195 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 196 sizeof(device_attr->fw_ver)); 197 198 return err; 199 } 200 201 /** 202 * Detect misc5 support or not 203 * 204 * @param[in] priv 205 * Device private data pointer 206 */ 207 #ifdef HAVE_MLX5DV_DR 208 static void 209 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 210 { 211 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 212 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 213 * Case: IPv4--->UDP--->VxLAN--->vni 214 */ 215 void *tbl; 216 struct mlx5_flow_dv_match_params matcher_mask; 217 void *match_m; 218 void *matcher; 219 void *headers_m; 220 void *misc5_m; 221 uint32_t *tunnel_header_m; 222 struct mlx5dv_flow_matcher_attr dv_attr; 223 224 memset(&matcher_mask, 0, sizeof(matcher_mask)); 225 matcher_mask.size = sizeof(matcher_mask.buf); 226 match_m = matcher_mask.buf; 227 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 228 misc5_m = MLX5_ADDR_OF(fte_match_param, 229 match_m, misc_parameters_5); 230 tunnel_header_m = (uint32_t *) 231 MLX5_ADDR_OF(fte_match_set_misc5, 232 misc5_m, tunnel_header_1); 233 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 234 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 235 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 236 *tunnel_header_m = 0xffffff; 237 238 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 239 if (!tbl) { 240 DRV_LOG(INFO, "No SW steering support"); 241 return; 242 } 243 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 244 dv_attr.match_mask = (void *)&matcher_mask, 245 dv_attr.match_criteria_enable = 246 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 247 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 248 dv_attr.priority = 3; 249 #ifdef HAVE_MLX5DV_DR_ESWITCH 250 void *misc2_m; 251 if (priv->config.dv_esw_en) { 252 /* FDB enabled reg_c_0 */ 253 dv_attr.match_criteria_enable |= 254 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 255 misc2_m = MLX5_ADDR_OF(fte_match_param, 256 match_m, misc_parameters_2); 257 MLX5_SET(fte_match_set_misc2, misc2_m, 258 metadata_reg_c_0, 0xffff); 259 } 260 #endif 261 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx, 262 &dv_attr, tbl); 263 if (matcher) { 264 priv->sh->misc5_cap = 1; 265 mlx5_glue->dv_destroy_flow_matcher(matcher); 266 } 267 mlx5_glue->dr_destroy_flow_tbl(tbl); 268 #else 269 RTE_SET_USED(priv); 270 #endif 271 } 272 #endif 273 274 /** 275 * Initialize DR related data within private structure. 276 * Routine checks the reference counter and does actual 277 * resources creation/initialization only if counter is zero. 278 * 279 * @param[in] priv 280 * Pointer to the private device data structure. 281 * 282 * @return 283 * Zero on success, positive error code otherwise. 284 */ 285 static int 286 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 287 { 288 struct mlx5_dev_ctx_shared *sh = priv->sh; 289 char s[MLX5_NAME_SIZE] __rte_unused; 290 int err; 291 292 MLX5_ASSERT(sh && sh->refcnt); 293 if (sh->refcnt > 1) 294 return 0; 295 err = mlx5_alloc_table_hash_list(priv); 296 if (err) 297 goto error; 298 /* The resources below are only valid with DV support. */ 299 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 300 /* Init port id action list. */ 301 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 302 sh->port_id_action_list = mlx5_list_create(s, sh, true, 303 flow_dv_port_id_create_cb, 304 flow_dv_port_id_match_cb, 305 flow_dv_port_id_remove_cb, 306 flow_dv_port_id_clone_cb, 307 flow_dv_port_id_clone_free_cb); 308 if (!sh->port_id_action_list) 309 goto error; 310 /* Init push vlan action list. */ 311 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 312 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 313 flow_dv_push_vlan_create_cb, 314 flow_dv_push_vlan_match_cb, 315 flow_dv_push_vlan_remove_cb, 316 flow_dv_push_vlan_clone_cb, 317 flow_dv_push_vlan_clone_free_cb); 318 if (!sh->push_vlan_action_list) 319 goto error; 320 /* Init sample action list. */ 321 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 322 sh->sample_action_list = mlx5_list_create(s, sh, true, 323 flow_dv_sample_create_cb, 324 flow_dv_sample_match_cb, 325 flow_dv_sample_remove_cb, 326 flow_dv_sample_clone_cb, 327 flow_dv_sample_clone_free_cb); 328 if (!sh->sample_action_list) 329 goto error; 330 /* Init dest array action list. */ 331 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 332 sh->dest_array_list = mlx5_list_create(s, sh, true, 333 flow_dv_dest_array_create_cb, 334 flow_dv_dest_array_match_cb, 335 flow_dv_dest_array_remove_cb, 336 flow_dv_dest_array_clone_cb, 337 flow_dv_dest_array_clone_free_cb); 338 if (!sh->dest_array_list) 339 goto error; 340 /* Init shared flex parsers list, no need lcore_share */ 341 snprintf(s, sizeof(s), "%s_flex_parsers_list", sh->ibdev_name); 342 sh->flex_parsers_dv = mlx5_list_create(s, sh, false, 343 mlx5_flex_parser_create_cb, 344 mlx5_flex_parser_match_cb, 345 mlx5_flex_parser_remove_cb, 346 mlx5_flex_parser_clone_cb, 347 mlx5_flex_parser_clone_free_cb); 348 if (!sh->flex_parsers_dv) 349 goto error; 350 #endif 351 #ifdef HAVE_MLX5DV_DR 352 void *domain; 353 354 /* Reference counter is zero, we should initialize structures. */ 355 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 356 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 357 if (!domain) { 358 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 359 err = errno; 360 goto error; 361 } 362 sh->rx_domain = domain; 363 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 364 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 365 if (!domain) { 366 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 367 err = errno; 368 goto error; 369 } 370 sh->tx_domain = domain; 371 #ifdef HAVE_MLX5DV_DR_ESWITCH 372 if (priv->config.dv_esw_en) { 373 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 374 MLX5DV_DR_DOMAIN_TYPE_FDB); 375 if (!domain) { 376 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 377 err = errno; 378 goto error; 379 } 380 sh->fdb_domain = domain; 381 } 382 /* 383 * The drop action is just some dummy placeholder in rdma-core. It 384 * does not belong to domains and has no any attributes, and, can be 385 * shared by the entire device. 386 */ 387 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 388 if (!sh->dr_drop_action) { 389 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 390 err = errno; 391 goto error; 392 } 393 #endif 394 if (!sh->tunnel_hub && priv->config.dv_miss_info) 395 err = mlx5_alloc_tunnel_hub(sh); 396 if (err) { 397 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 398 goto error; 399 } 400 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 401 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 402 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 403 if (sh->fdb_domain) 404 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 405 } 406 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 407 if (!priv->config.allow_duplicate_pattern) { 408 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 409 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 410 #endif 411 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 412 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 413 if (sh->fdb_domain) 414 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 415 } 416 417 __mlx5_discovery_misc5_cap(priv); 418 #endif /* HAVE_MLX5DV_DR */ 419 sh->default_miss_action = 420 mlx5_glue->dr_create_flow_action_default_miss(); 421 if (!sh->default_miss_action) 422 DRV_LOG(WARNING, "Default miss action is not supported."); 423 return 0; 424 error: 425 /* Rollback the created objects. */ 426 if (sh->rx_domain) { 427 mlx5_glue->dr_destroy_domain(sh->rx_domain); 428 sh->rx_domain = NULL; 429 } 430 if (sh->tx_domain) { 431 mlx5_glue->dr_destroy_domain(sh->tx_domain); 432 sh->tx_domain = NULL; 433 } 434 if (sh->fdb_domain) { 435 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 436 sh->fdb_domain = NULL; 437 } 438 if (sh->dr_drop_action) { 439 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 440 sh->dr_drop_action = NULL; 441 } 442 if (sh->pop_vlan_action) { 443 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 444 sh->pop_vlan_action = NULL; 445 } 446 if (sh->encaps_decaps) { 447 mlx5_hlist_destroy(sh->encaps_decaps); 448 sh->encaps_decaps = NULL; 449 } 450 if (sh->modify_cmds) { 451 mlx5_hlist_destroy(sh->modify_cmds); 452 sh->modify_cmds = NULL; 453 } 454 if (sh->tag_table) { 455 /* tags should be destroyed with flow before. */ 456 mlx5_hlist_destroy(sh->tag_table); 457 sh->tag_table = NULL; 458 } 459 if (sh->tunnel_hub) { 460 mlx5_release_tunnel_hub(sh, priv->dev_port); 461 sh->tunnel_hub = NULL; 462 } 463 mlx5_free_table_hash_list(priv); 464 if (sh->port_id_action_list) { 465 mlx5_list_destroy(sh->port_id_action_list); 466 sh->port_id_action_list = NULL; 467 } 468 if (sh->push_vlan_action_list) { 469 mlx5_list_destroy(sh->push_vlan_action_list); 470 sh->push_vlan_action_list = NULL; 471 } 472 if (sh->sample_action_list) { 473 mlx5_list_destroy(sh->sample_action_list); 474 sh->sample_action_list = NULL; 475 } 476 if (sh->dest_array_list) { 477 mlx5_list_destroy(sh->dest_array_list); 478 sh->dest_array_list = NULL; 479 } 480 return err; 481 } 482 483 /** 484 * Destroy DR related data within private structure. 485 * 486 * @param[in] priv 487 * Pointer to the private device data structure. 488 */ 489 void 490 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 491 { 492 struct mlx5_dev_ctx_shared *sh = priv->sh; 493 494 MLX5_ASSERT(sh && sh->refcnt); 495 if (sh->refcnt > 1) 496 return; 497 #ifdef HAVE_MLX5DV_DR 498 if (sh->rx_domain) { 499 mlx5_glue->dr_destroy_domain(sh->rx_domain); 500 sh->rx_domain = NULL; 501 } 502 if (sh->tx_domain) { 503 mlx5_glue->dr_destroy_domain(sh->tx_domain); 504 sh->tx_domain = NULL; 505 } 506 #ifdef HAVE_MLX5DV_DR_ESWITCH 507 if (sh->fdb_domain) { 508 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 509 sh->fdb_domain = NULL; 510 } 511 if (sh->dr_drop_action) { 512 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 513 sh->dr_drop_action = NULL; 514 } 515 #endif 516 if (sh->pop_vlan_action) { 517 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 518 sh->pop_vlan_action = NULL; 519 } 520 #endif /* HAVE_MLX5DV_DR */ 521 if (sh->default_miss_action) 522 mlx5_glue->destroy_flow_action 523 (sh->default_miss_action); 524 if (sh->encaps_decaps) { 525 mlx5_hlist_destroy(sh->encaps_decaps); 526 sh->encaps_decaps = NULL; 527 } 528 if (sh->modify_cmds) { 529 mlx5_hlist_destroy(sh->modify_cmds); 530 sh->modify_cmds = NULL; 531 } 532 if (sh->tag_table) { 533 /* tags should be destroyed with flow before. */ 534 mlx5_hlist_destroy(sh->tag_table); 535 sh->tag_table = NULL; 536 } 537 if (sh->tunnel_hub) { 538 mlx5_release_tunnel_hub(sh, priv->dev_port); 539 sh->tunnel_hub = NULL; 540 } 541 mlx5_free_table_hash_list(priv); 542 if (sh->port_id_action_list) { 543 mlx5_list_destroy(sh->port_id_action_list); 544 sh->port_id_action_list = NULL; 545 } 546 if (sh->push_vlan_action_list) { 547 mlx5_list_destroy(sh->push_vlan_action_list); 548 sh->push_vlan_action_list = NULL; 549 } 550 if (sh->sample_action_list) { 551 mlx5_list_destroy(sh->sample_action_list); 552 sh->sample_action_list = NULL; 553 } 554 if (sh->dest_array_list) { 555 mlx5_list_destroy(sh->dest_array_list); 556 sh->dest_array_list = NULL; 557 } 558 } 559 560 /** 561 * Initialize shared data between primary and secondary process. 562 * 563 * A memzone is reserved by primary process and secondary processes attach to 564 * the memzone. 565 * 566 * @return 567 * 0 on success, a negative errno value otherwise and rte_errno is set. 568 */ 569 static int 570 mlx5_init_shared_data(void) 571 { 572 const struct rte_memzone *mz; 573 int ret = 0; 574 575 rte_spinlock_lock(&mlx5_shared_data_lock); 576 if (mlx5_shared_data == NULL) { 577 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 578 /* Allocate shared memory. */ 579 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 580 sizeof(*mlx5_shared_data), 581 SOCKET_ID_ANY, 0); 582 if (mz == NULL) { 583 DRV_LOG(ERR, 584 "Cannot allocate mlx5 shared data"); 585 ret = -rte_errno; 586 goto error; 587 } 588 mlx5_shared_data = mz->addr; 589 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 590 rte_spinlock_init(&mlx5_shared_data->lock); 591 } else { 592 /* Lookup allocated shared memory. */ 593 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 594 if (mz == NULL) { 595 DRV_LOG(ERR, 596 "Cannot attach mlx5 shared data"); 597 ret = -rte_errno; 598 goto error; 599 } 600 mlx5_shared_data = mz->addr; 601 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 602 } 603 } 604 error: 605 rte_spinlock_unlock(&mlx5_shared_data_lock); 606 return ret; 607 } 608 609 /** 610 * PMD global initialization. 611 * 612 * Independent from individual device, this function initializes global 613 * per-PMD data structures distinguishing primary and secondary processes. 614 * Hence, each initialization is called once per a process. 615 * 616 * @return 617 * 0 on success, a negative errno value otherwise and rte_errno is set. 618 */ 619 static int 620 mlx5_init_once(void) 621 { 622 struct mlx5_shared_data *sd; 623 struct mlx5_local_data *ld = &mlx5_local_data; 624 int ret = 0; 625 626 if (mlx5_init_shared_data()) 627 return -rte_errno; 628 sd = mlx5_shared_data; 629 MLX5_ASSERT(sd); 630 rte_spinlock_lock(&sd->lock); 631 switch (rte_eal_process_type()) { 632 case RTE_PROC_PRIMARY: 633 if (sd->init_done) 634 break; 635 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 636 mlx5_mp_os_primary_handle); 637 if (ret) 638 goto out; 639 sd->init_done = true; 640 break; 641 case RTE_PROC_SECONDARY: 642 if (ld->init_done) 643 break; 644 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 645 mlx5_mp_os_secondary_handle); 646 if (ret) 647 goto out; 648 ++sd->secondary_cnt; 649 ld->init_done = true; 650 break; 651 default: 652 break; 653 } 654 out: 655 rte_spinlock_unlock(&sd->lock); 656 return ret; 657 } 658 659 /** 660 * DV flow counter mode detect and config. 661 * 662 * @param dev 663 * Pointer to rte_eth_dev structure. 664 * 665 */ 666 static void 667 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 668 { 669 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 670 struct mlx5_priv *priv = dev->data->dev_private; 671 struct mlx5_dev_ctx_shared *sh = priv->sh; 672 bool fallback; 673 674 #ifndef HAVE_IBV_DEVX_ASYNC 675 fallback = true; 676 #else 677 fallback = false; 678 if (!sh->devx || !priv->config.dv_flow_en || 679 !priv->config.hca_attr.flow_counters_dump || 680 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 681 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 682 fallback = true; 683 #endif 684 if (fallback) 685 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 686 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 687 priv->config.hca_attr.flow_counters_dump, 688 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 689 /* Initialize fallback mode only on the port initializes sh. */ 690 if (sh->refcnt == 1) 691 sh->cmng.counter_fallback = fallback; 692 else if (fallback != sh->cmng.counter_fallback) 693 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 694 "with others:%d.", PORT_ID(priv), fallback); 695 #endif 696 } 697 698 /** 699 * DR flow drop action support detect. 700 * 701 * @param dev 702 * Pointer to rte_eth_dev structure. 703 * 704 */ 705 static void 706 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 707 { 708 #ifdef HAVE_MLX5DV_DR 709 struct mlx5_priv *priv = dev->data->dev_private; 710 711 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action) 712 return; 713 /** 714 * DR supports drop action placeholder when it is supported; 715 * otherwise, use the queue drop action. 716 */ 717 if (!priv->sh->drop_action_check_flag) { 718 if (!mlx5_flow_discover_dr_action_support(dev)) 719 priv->sh->dr_drop_action_en = 1; 720 priv->sh->drop_action_check_flag = 1; 721 } 722 if (priv->sh->dr_drop_action_en) 723 priv->root_drop_action = priv->sh->dr_drop_action; 724 else 725 priv->root_drop_action = priv->drop_queue.hrxq->action; 726 #endif 727 } 728 729 static void 730 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 731 { 732 struct mlx5_priv *priv = dev->data->dev_private; 733 void *ctx = priv->sh->cdev->ctx; 734 735 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 736 if (!priv->q_counters) { 737 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 738 struct ibv_wq *wq; 739 740 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 741 "by DevX - fall-back to use the kernel driver global " 742 "queue counter.", dev->data->port_id); 743 /* Create WQ by kernel and query its queue counter ID. */ 744 if (cq) { 745 wq = mlx5_glue->create_wq(ctx, 746 &(struct ibv_wq_init_attr){ 747 .wq_type = IBV_WQT_RQ, 748 .max_wr = 1, 749 .max_sge = 1, 750 .pd = priv->sh->cdev->pd, 751 .cq = cq, 752 }); 753 if (wq) { 754 /* Counter is assigned only on RDY state. */ 755 int ret = mlx5_glue->modify_wq(wq, 756 &(struct ibv_wq_attr){ 757 .attr_mask = IBV_WQ_ATTR_STATE, 758 .wq_state = IBV_WQS_RDY, 759 }); 760 761 if (ret == 0) 762 mlx5_devx_cmd_wq_query(wq, 763 &priv->counter_set_id); 764 claim_zero(mlx5_glue->destroy_wq(wq)); 765 } 766 claim_zero(mlx5_glue->destroy_cq(cq)); 767 } 768 } else { 769 priv->counter_set_id = priv->q_counters->id; 770 } 771 if (priv->counter_set_id == 0) 772 DRV_LOG(INFO, "Part of the port %d statistics will not be " 773 "available.", dev->data->port_id); 774 } 775 776 /** 777 * Check if representor spawn info match devargs. 778 * 779 * @param spawn 780 * Verbs device parameters (name, port, switch_info) to spawn. 781 * @param eth_da 782 * Device devargs to probe. 783 * 784 * @return 785 * Match result. 786 */ 787 static bool 788 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 789 struct rte_eth_devargs *eth_da) 790 { 791 struct mlx5_switch_info *switch_info = &spawn->info; 792 unsigned int p, f; 793 uint16_t id; 794 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 795 eth_da->type); 796 797 switch (eth_da->type) { 798 case RTE_ETH_REPRESENTOR_SF: 799 if (!(spawn->info.port_name == -1 && 800 switch_info->name_type == 801 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 802 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 803 rte_errno = EBUSY; 804 return false; 805 } 806 break; 807 case RTE_ETH_REPRESENTOR_VF: 808 /* Allows HPF representor index -1 as exception. */ 809 if (!(spawn->info.port_name == -1 && 810 switch_info->name_type == 811 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 812 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 813 rte_errno = EBUSY; 814 return false; 815 } 816 break; 817 case RTE_ETH_REPRESENTOR_NONE: 818 rte_errno = EBUSY; 819 return false; 820 default: 821 rte_errno = ENOTSUP; 822 DRV_LOG(ERR, "unsupported representor type"); 823 return false; 824 } 825 /* Check representor ID: */ 826 for (p = 0; p < eth_da->nb_ports; ++p) { 827 if (spawn->pf_bond < 0) { 828 /* For non-LAG mode, allow and ignore pf. */ 829 switch_info->pf_num = eth_da->ports[p]; 830 repr_id = mlx5_representor_id_encode(switch_info, 831 eth_da->type); 832 } 833 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 834 id = MLX5_REPRESENTOR_ID 835 (eth_da->ports[p], eth_da->type, 836 eth_da->representor_ports[f]); 837 if (repr_id == id) 838 return true; 839 } 840 } 841 rte_errno = EBUSY; 842 return false; 843 } 844 845 /** 846 * Spawn an Ethernet device from Verbs information. 847 * 848 * @param dpdk_dev 849 * Backing DPDK device. 850 * @param spawn 851 * Verbs device parameters (name, port, switch_info) to spawn. 852 * @param config 853 * Device configuration parameters. 854 * @param eth_da 855 * Device arguments. 856 * 857 * @return 858 * A valid Ethernet device object on success, NULL otherwise and rte_errno 859 * is set. The following errors are defined: 860 * 861 * EBUSY: device is not supposed to be spawned. 862 * EEXIST: device is already spawned 863 */ 864 static struct rte_eth_dev * 865 mlx5_dev_spawn(struct rte_device *dpdk_dev, 866 struct mlx5_dev_spawn_data *spawn, 867 struct mlx5_dev_config *config, 868 struct rte_eth_devargs *eth_da) 869 { 870 const struct mlx5_switch_info *switch_info = &spawn->info; 871 struct mlx5_dev_ctx_shared *sh = NULL; 872 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; 873 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 874 struct rte_eth_dev *eth_dev = NULL; 875 struct mlx5_priv *priv = NULL; 876 int err = 0; 877 unsigned int hw_padding = 0; 878 unsigned int mps; 879 unsigned int mpls_en = 0; 880 unsigned int swp = 0; 881 unsigned int mprq = 0; 882 unsigned int mprq_min_stride_size_n = 0; 883 unsigned int mprq_max_stride_size_n = 0; 884 unsigned int mprq_min_stride_num_n = 0; 885 unsigned int mprq_max_stride_num_n = 0; 886 struct rte_ether_addr mac; 887 char name[RTE_ETH_NAME_MAX_LEN]; 888 int own_domain_id = 0; 889 uint16_t port_id; 890 struct mlx5_port_info vport_info = { .query_flags = 0 }; 891 int nl_rdma = -1; 892 int i; 893 894 /* Determine if this port representor is supposed to be spawned. */ 895 if (switch_info->representor && dpdk_dev->devargs && 896 !mlx5_representor_match(spawn, eth_da)) 897 return NULL; 898 /* Build device name. */ 899 if (spawn->pf_bond < 0) { 900 /* Single device. */ 901 if (!switch_info->representor) 902 strlcpy(name, dpdk_dev->name, sizeof(name)); 903 else 904 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 905 dpdk_dev->name, 906 switch_info->name_type == 907 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 908 switch_info->port_name); 909 } else { 910 /* Bonding device. */ 911 if (!switch_info->representor) { 912 err = snprintf(name, sizeof(name), "%s_%s", 913 dpdk_dev->name, spawn->phys_dev_name); 914 } else { 915 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 916 dpdk_dev->name, spawn->phys_dev_name, 917 switch_info->ctrl_num, 918 switch_info->pf_num, 919 switch_info->name_type == 920 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 921 switch_info->port_name); 922 } 923 } 924 if (err >= (int)sizeof(name)) 925 DRV_LOG(WARNING, "device name overflow %s", name); 926 /* check if the device is already spawned */ 927 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 928 rte_errno = EEXIST; 929 return NULL; 930 } 931 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 932 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 933 struct mlx5_mp_id mp_id; 934 935 eth_dev = rte_eth_dev_attach_secondary(name); 936 if (eth_dev == NULL) { 937 DRV_LOG(ERR, "can not attach rte ethdev"); 938 rte_errno = ENOMEM; 939 return NULL; 940 } 941 eth_dev->device = dpdk_dev; 942 eth_dev->dev_ops = &mlx5_dev_sec_ops; 943 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 944 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 945 err = mlx5_proc_priv_init(eth_dev); 946 if (err) 947 return NULL; 948 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 949 /* Receive command fd from primary process */ 950 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 951 if (err < 0) 952 goto err_secondary; 953 /* Remap UAR for Tx queues. */ 954 err = mlx5_tx_uar_init_secondary(eth_dev, err); 955 if (err) 956 goto err_secondary; 957 /* 958 * Ethdev pointer is still required as input since 959 * the primary device is not accessible from the 960 * secondary process. 961 */ 962 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 963 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 964 return eth_dev; 965 err_secondary: 966 mlx5_dev_close(eth_dev); 967 return NULL; 968 } 969 /* 970 * Some parameters ("tx_db_nc" in particularly) are needed in 971 * advance to create dv/verbs device context. We proceed the 972 * devargs here to get ones, and later proceed devargs again 973 * to override some hardware settings. 974 */ 975 err = mlx5_args(config, dpdk_dev->devargs); 976 if (err) { 977 err = rte_errno; 978 DRV_LOG(ERR, "failed to process device arguments: %s", 979 strerror(rte_errno)); 980 goto error; 981 } 982 if (config->dv_miss_info) { 983 if (switch_info->master || switch_info->representor) 984 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 985 } 986 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 987 if (!sh) 988 return NULL; 989 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 990 config->dest_tir = 1; 991 #endif 992 #ifdef HAVE_IBV_MLX5_MOD_SWP 993 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 994 #endif 995 /* 996 * Multi-packet send is supported by ConnectX-4 Lx PF as well 997 * as all ConnectX-5 devices. 998 */ 999 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1000 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1001 #endif 1002 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1003 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1004 #endif 1005 mlx5_glue->dv_query_device(sh->cdev->ctx, &dv_attr); 1006 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1007 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1008 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1009 mps = MLX5_MPW_ENHANCED; 1010 } else { 1011 DRV_LOG(DEBUG, "MPW is supported"); 1012 mps = MLX5_MPW; 1013 } 1014 } else { 1015 DRV_LOG(DEBUG, "MPW isn't supported"); 1016 mps = MLX5_MPW_DISABLED; 1017 } 1018 #ifdef HAVE_IBV_MLX5_MOD_SWP 1019 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1020 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1021 DRV_LOG(DEBUG, "SWP support: %u", swp); 1022 #endif 1023 config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP | 1024 MLX5_SW_PARSING_TSO_CAP); 1025 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1026 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1027 struct mlx5dv_striding_rq_caps mprq_caps = 1028 dv_attr.striding_rq_caps; 1029 1030 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1031 mprq_caps.min_single_stride_log_num_of_bytes); 1032 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1033 mprq_caps.max_single_stride_log_num_of_bytes); 1034 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1035 mprq_caps.min_single_wqe_log_num_of_strides); 1036 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1037 mprq_caps.max_single_wqe_log_num_of_strides); 1038 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1039 mprq_caps.supported_qpts); 1040 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1041 mprq = 1; 1042 mprq_min_stride_size_n = 1043 mprq_caps.min_single_stride_log_num_of_bytes; 1044 mprq_max_stride_size_n = 1045 mprq_caps.max_single_stride_log_num_of_bytes; 1046 mprq_min_stride_num_n = 1047 mprq_caps.min_single_wqe_log_num_of_strides; 1048 mprq_max_stride_num_n = 1049 mprq_caps.max_single_wqe_log_num_of_strides; 1050 } 1051 #endif 1052 /* Rx CQE compression is enabled by default. */ 1053 config->cqe_comp = 1; 1054 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1055 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1056 config->tunnel_en = dv_attr.tunnel_offloads_caps & 1057 (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN | 1058 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE | 1059 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE); 1060 } 1061 if (config->tunnel_en) { 1062 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s", 1063 config->tunnel_en & 1064 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "", 1065 config->tunnel_en & 1066 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "", 1067 config->tunnel_en & 1068 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : "" 1069 ); 1070 } else { 1071 DRV_LOG(DEBUG, "tunnel offloading is not supported"); 1072 } 1073 #else 1074 DRV_LOG(WARNING, 1075 "tunnel offloading disabled due to old OFED/rdma-core version"); 1076 #endif 1077 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1078 mpls_en = ((dv_attr.tunnel_offloads_caps & 1079 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1080 (dv_attr.tunnel_offloads_caps & 1081 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1082 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1083 mpls_en ? "" : "not "); 1084 #else 1085 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1086 " old OFED/rdma-core version or firmware configuration"); 1087 #endif 1088 config->mpls_en = mpls_en; 1089 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1090 /* Check port status. */ 1091 if (spawn->phys_port <= UINT8_MAX) { 1092 /* Legacy Verbs api only support u8 port number. */ 1093 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port, 1094 &port_attr); 1095 if (err) { 1096 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1097 goto error; 1098 } 1099 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1100 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1101 err = EINVAL; 1102 goto error; 1103 } 1104 } else if (nl_rdma >= 0) { 1105 /* IB doesn't allow more than 255 ports, must be Ethernet. */ 1106 err = mlx5_nl_port_state(nl_rdma, 1107 spawn->phys_dev_name, 1108 spawn->phys_port); 1109 if (err < 0) { 1110 DRV_LOG(INFO, "Failed to get netlink port state: %s", 1111 strerror(rte_errno)); 1112 err = -rte_errno; 1113 goto error; 1114 } 1115 port_attr.state = (enum ibv_port_state)err; 1116 } 1117 if (port_attr.state != IBV_PORT_ACTIVE) 1118 DRV_LOG(INFO, "port is not active: \"%s\" (%d)", 1119 mlx5_glue->port_state_str(port_attr.state), 1120 port_attr.state); 1121 /* Allocate private eth device data. */ 1122 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1123 sizeof(*priv), 1124 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1125 if (priv == NULL) { 1126 DRV_LOG(ERR, "priv allocation failure"); 1127 err = ENOMEM; 1128 goto error; 1129 } 1130 priv->sh = sh; 1131 priv->dev_port = spawn->phys_port; 1132 priv->pci_dev = spawn->pci_dev; 1133 priv->mtu = RTE_ETHER_MTU; 1134 /* Some internal functions rely on Netlink sockets, open them now. */ 1135 priv->nl_socket_rdma = nl_rdma; 1136 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1137 priv->representor = !!switch_info->representor; 1138 priv->master = !!switch_info->master; 1139 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1140 priv->vport_meta_tag = 0; 1141 priv->vport_meta_mask = 0; 1142 priv->pf_bond = spawn->pf_bond; 1143 1144 DRV_LOG(DEBUG, 1145 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1146 priv->dev_port, dpdk_dev->bus->name, 1147 priv->pci_dev ? priv->pci_dev->name : "NONE", 1148 priv->master, priv->representor, priv->pf_bond); 1149 1150 /* 1151 * If we have E-Switch we should determine the vport attributes. 1152 * E-Switch may use either source vport field or reg_c[0] metadata 1153 * register to match on vport index. The engaged part of metadata 1154 * register is defined by mask. 1155 */ 1156 if (switch_info->representor || switch_info->master) { 1157 err = mlx5_glue->devx_port_query(sh->cdev->ctx, 1158 spawn->phys_port, 1159 &vport_info); 1160 if (err) { 1161 DRV_LOG(WARNING, 1162 "Cannot query devx port %d on device %s", 1163 spawn->phys_port, spawn->phys_dev_name); 1164 vport_info.query_flags = 0; 1165 } 1166 } 1167 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1168 priv->vport_meta_tag = vport_info.vport_meta_tag; 1169 priv->vport_meta_mask = vport_info.vport_meta_mask; 1170 if (!priv->vport_meta_mask) { 1171 DRV_LOG(ERR, 1172 "vport zero mask for port %d on bonding device %s", 1173 spawn->phys_port, spawn->phys_dev_name); 1174 err = ENOTSUP; 1175 goto error; 1176 } 1177 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1178 DRV_LOG(ERR, 1179 "Invalid vport tag for port %d on bonding device %s", 1180 spawn->phys_port, spawn->phys_dev_name); 1181 err = ENOTSUP; 1182 goto error; 1183 } 1184 } 1185 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1186 priv->vport_id = vport_info.vport_id; 1187 } else if (spawn->pf_bond >= 0 && 1188 (switch_info->representor || switch_info->master)) { 1189 DRV_LOG(ERR, 1190 "Cannot deduce vport index for port %d on bonding device %s", 1191 spawn->phys_port, spawn->phys_dev_name); 1192 err = ENOTSUP; 1193 goto error; 1194 } else { 1195 /* 1196 * Suppose vport index in compatible way. Kernel/rdma_core 1197 * support single E-Switch per PF configurations only and 1198 * vport_id field contains the vport index for associated VF, 1199 * which is deduced from representor port name. 1200 * For example, let's have the IB device port 10, it has 1201 * attached network device eth0, which has port name attribute 1202 * pf0vf2, we can deduce the VF number as 2, and set vport index 1203 * as 3 (2+1). This assigning schema should be changed if the 1204 * multiple E-Switch instances per PF configurations or/and PCI 1205 * subfunctions are added. 1206 */ 1207 priv->vport_id = switch_info->representor ? 1208 switch_info->port_name + 1 : -1; 1209 } 1210 priv->representor_id = mlx5_representor_id_encode(switch_info, 1211 eth_da->type); 1212 /* 1213 * Look for sibling devices in order to reuse their switch domain 1214 * if any, otherwise allocate one. 1215 */ 1216 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1217 const struct mlx5_priv *opriv = 1218 rte_eth_devices[port_id].data->dev_private; 1219 1220 if (!opriv || 1221 opriv->sh != priv->sh || 1222 opriv->domain_id == 1223 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1224 continue; 1225 priv->domain_id = opriv->domain_id; 1226 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1227 priv->dev_port, priv->domain_id); 1228 break; 1229 } 1230 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1231 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1232 if (err) { 1233 err = rte_errno; 1234 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1235 strerror(rte_errno)); 1236 goto error; 1237 } 1238 own_domain_id = 1; 1239 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1240 priv->dev_port, priv->domain_id); 1241 } 1242 /* Override some values set by hardware configuration. */ 1243 mlx5_args(config, dpdk_dev->devargs); 1244 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev); 1245 if (err) 1246 goto error; 1247 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1248 IBV_DEVICE_RAW_IP_CSUM); 1249 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1250 (config->hw_csum ? "" : "not ")); 1251 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1252 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1253 DRV_LOG(DEBUG, "counters are not supported"); 1254 #endif 1255 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1256 if (config->dv_flow_en) { 1257 DRV_LOG(WARNING, "DV flow is not supported"); 1258 config->dv_flow_en = 0; 1259 } 1260 #endif 1261 config->ind_table_max_size = 1262 sh->device_attr.max_rwq_indirection_table_size; 1263 /* 1264 * Remove this check once DPDK supports larger/variable 1265 * indirection tables. 1266 */ 1267 if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512) 1268 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512; 1269 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1270 config->ind_table_max_size); 1271 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1272 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1273 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1274 (config->hw_vlan_strip ? "" : "not ")); 1275 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1276 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1277 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1278 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1279 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1280 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1281 IBV_DEVICE_PCI_WRITE_END_PADDING); 1282 #endif 1283 if (config->hw_padding && !hw_padding) { 1284 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1285 config->hw_padding = 0; 1286 } else if (config->hw_padding) { 1287 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1288 } 1289 config->tso = (sh->device_attr.max_tso > 0 && 1290 (sh->device_attr.tso_supported_qpts & 1291 (1 << IBV_QPT_RAW_PACKET))); 1292 if (config->tso) 1293 config->tso_max_payload_sz = sh->device_attr.max_tso; 1294 /* 1295 * MPW is disabled by default, while the Enhanced MPW is enabled 1296 * by default. 1297 */ 1298 if (config->mps == MLX5_ARG_UNSET) 1299 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1300 MLX5_MPW_DISABLED; 1301 else 1302 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1303 DRV_LOG(INFO, "%sMPS is %s", 1304 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1305 config->mps == MLX5_MPW ? "legacy " : "", 1306 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1307 if (sh->devx) { 1308 config->hca_attr = sh->cdev->config.hca_attr; 1309 sh->steering_format_version = 1310 config->hca_attr.steering_format_version; 1311 /* Check for LRO support. */ 1312 if (config->dest_tir && config->hca_attr.lro_cap && 1313 config->dv_flow_en) { 1314 /* TBD check tunnel lro caps. */ 1315 config->lro.supported = config->hca_attr.lro_cap; 1316 DRV_LOG(DEBUG, "Device supports LRO"); 1317 /* 1318 * If LRO timeout is not configured by application, 1319 * use the minimal supported value. 1320 */ 1321 if (!config->lro.timeout) 1322 config->lro.timeout = 1323 config->hca_attr.lro_timer_supported_periods[0]; 1324 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1325 config->lro.timeout); 1326 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1327 "required for coalescing is %d bytes", 1328 config->hca_attr.lro_min_mss_size); 1329 } 1330 #if defined(HAVE_MLX5DV_DR) && \ 1331 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1332 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1333 if (config->hca_attr.qos.sup && 1334 config->hca_attr.qos.flow_meter_old && 1335 config->dv_flow_en) { 1336 uint8_t reg_c_mask = 1337 config->hca_attr.qos.flow_meter_reg_c_ids; 1338 /* 1339 * Meter needs two REG_C's for color match and pre-sfx 1340 * flow match. Here get the REG_C for color match. 1341 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1342 */ 1343 reg_c_mask &= 0xfc; 1344 if (__builtin_popcount(reg_c_mask) < 1) { 1345 priv->mtr_en = 0; 1346 DRV_LOG(WARNING, "No available register for" 1347 " meter."); 1348 } else { 1349 /* 1350 * The meter color register is used by the 1351 * flow-hit feature as well. 1352 * The flow-hit feature must use REG_C_3 1353 * Prefer REG_C_3 if it is available. 1354 */ 1355 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1356 priv->mtr_color_reg = REG_C_3; 1357 else 1358 priv->mtr_color_reg = ffs(reg_c_mask) 1359 - 1 + REG_C_0; 1360 priv->mtr_en = 1; 1361 priv->mtr_reg_share = 1362 config->hca_attr.qos.flow_meter; 1363 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1364 priv->mtr_color_reg); 1365 } 1366 } 1367 if (config->hca_attr.qos.sup && 1368 config->hca_attr.qos.flow_meter_aso_sup) { 1369 uint32_t log_obj_size = 1370 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1371 if (log_obj_size >= 1372 config->hca_attr.qos.log_meter_aso_granularity && 1373 log_obj_size <= 1374 config->hca_attr.qos.log_meter_aso_max_alloc) 1375 sh->meter_aso_en = 1; 1376 } 1377 if (priv->mtr_en) { 1378 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1379 if (err) { 1380 err = -err; 1381 goto error; 1382 } 1383 } 1384 if (config->hca_attr.flow.tunnel_header_0_1) 1385 sh->tunnel_header_0_1 = 1; 1386 #endif 1387 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1388 if (config->hca_attr.flow_hit_aso && 1389 priv->mtr_color_reg == REG_C_3) { 1390 sh->flow_hit_aso_en = 1; 1391 err = mlx5_flow_aso_age_mng_init(sh); 1392 if (err) { 1393 err = -err; 1394 goto error; 1395 } 1396 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1397 } 1398 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1399 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1400 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1401 if (config->hca_attr.ct_offload && 1402 priv->mtr_color_reg == REG_C_3) { 1403 err = mlx5_flow_aso_ct_mng_init(sh); 1404 if (err) { 1405 err = -err; 1406 goto error; 1407 } 1408 DRV_LOG(DEBUG, "CT ASO is supported."); 1409 sh->ct_aso_en = 1; 1410 } 1411 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1412 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1413 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1414 config->dv_flow_en) { 1415 priv->sampler_en = 1; 1416 DRV_LOG(DEBUG, "Sampler enabled!"); 1417 } else { 1418 priv->sampler_en = 0; 1419 if (!config->hca_attr.log_max_ft_sampler_num) 1420 DRV_LOG(WARNING, 1421 "No available register for sampler."); 1422 else 1423 DRV_LOG(DEBUG, "DV flow is not supported!"); 1424 } 1425 #endif 1426 } 1427 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1428 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1429 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1430 config->cqe_comp = 0; 1431 } 1432 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1433 (!sh->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1434 DRV_LOG(WARNING, "Flow Tag CQE compression" 1435 " format isn't supported."); 1436 config->cqe_comp = 0; 1437 } 1438 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1439 (!sh->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1440 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1441 " format isn't supported."); 1442 config->cqe_comp = 0; 1443 } 1444 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1445 config->cqe_comp ? "" : "not "); 1446 if (config->tx_pp) { 1447 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1448 config->hca_attr.dev_freq_khz); 1449 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1450 config->hca_attr.qos.packet_pacing ? "" : "not "); 1451 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1452 config->hca_attr.cross_channel ? "" : "not "); 1453 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1454 config->hca_attr.wqe_index_ignore ? "" : "not "); 1455 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1456 config->hca_attr.non_wire_sq ? "" : "not "); 1457 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1458 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1459 config->hca_attr.log_max_static_sq_wq); 1460 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1461 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1462 if (!sh->devx) { 1463 DRV_LOG(ERR, "DevX is required for packet pacing"); 1464 err = ENODEV; 1465 goto error; 1466 } 1467 if (!config->hca_attr.qos.packet_pacing) { 1468 DRV_LOG(ERR, "Packet pacing is not supported"); 1469 err = ENODEV; 1470 goto error; 1471 } 1472 if (!config->hca_attr.cross_channel) { 1473 DRV_LOG(ERR, "Cross channel operations are" 1474 " required for packet pacing"); 1475 err = ENODEV; 1476 goto error; 1477 } 1478 if (!config->hca_attr.wqe_index_ignore) { 1479 DRV_LOG(ERR, "WQE index ignore feature is" 1480 " required for packet pacing"); 1481 err = ENODEV; 1482 goto error; 1483 } 1484 if (!config->hca_attr.non_wire_sq) { 1485 DRV_LOG(ERR, "Non-wire SQ feature is" 1486 " required for packet pacing"); 1487 err = ENODEV; 1488 goto error; 1489 } 1490 if (!config->hca_attr.log_max_static_sq_wq) { 1491 DRV_LOG(ERR, "Static WQE SQ feature is" 1492 " required for packet pacing"); 1493 err = ENODEV; 1494 goto error; 1495 } 1496 if (!config->hca_attr.qos.wqe_rate_pp) { 1497 DRV_LOG(ERR, "WQE rate mode is required" 1498 " for packet pacing"); 1499 err = ENODEV; 1500 goto error; 1501 } 1502 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1503 DRV_LOG(ERR, "DevX does not provide UAR offset," 1504 " can't create queues for packet pacing"); 1505 err = ENODEV; 1506 goto error; 1507 #endif 1508 } 1509 if (sh->devx) { 1510 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1511 1512 err = config->hca_attr.access_register_user ? 1513 mlx5_devx_cmd_register_read 1514 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1515 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1516 if (!err) { 1517 uint32_t ts_mode; 1518 1519 /* MTUTC register is read successfully. */ 1520 ts_mode = MLX5_GET(register_mtutc, reg, 1521 time_stamp_mode); 1522 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1523 config->rt_timestamp = 1; 1524 } else { 1525 /* Kernel does not support register reading. */ 1526 if (config->hca_attr.dev_freq_khz == 1527 (NS_PER_S / MS_PER_S)) 1528 config->rt_timestamp = 1; 1529 } 1530 } 1531 /* 1532 * If HW has bug working with tunnel packet decapsulation and 1533 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1534 * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1535 */ 1536 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1537 config->hw_fcs_strip = 0; 1538 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1539 (config->hw_fcs_strip ? "" : "not ")); 1540 if (config->mprq.enabled && mprq) { 1541 if (config->mprq.stride_num_n && 1542 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1543 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1544 config->mprq.stride_num_n = 1545 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1546 mprq_min_stride_num_n), 1547 mprq_max_stride_num_n); 1548 DRV_LOG(WARNING, 1549 "the number of strides" 1550 " for Multi-Packet RQ is out of range," 1551 " setting default value (%u)", 1552 1 << config->mprq.stride_num_n); 1553 } 1554 if (config->mprq.stride_size_n && 1555 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1556 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1557 config->mprq.stride_size_n = 1558 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1559 mprq_min_stride_size_n), 1560 mprq_max_stride_size_n); 1561 DRV_LOG(WARNING, 1562 "the size of a stride" 1563 " for Multi-Packet RQ is out of range," 1564 " setting default value (%u)", 1565 1 << config->mprq.stride_size_n); 1566 } 1567 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1568 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1569 } else if (config->mprq.enabled && !mprq) { 1570 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1571 config->mprq.enabled = 0; 1572 } 1573 if (config->max_dump_files_num == 0) 1574 config->max_dump_files_num = 128; 1575 eth_dev = rte_eth_dev_allocate(name); 1576 if (eth_dev == NULL) { 1577 DRV_LOG(ERR, "can not allocate rte ethdev"); 1578 err = ENOMEM; 1579 goto error; 1580 } 1581 if (priv->representor) { 1582 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1583 eth_dev->data->representor_id = priv->representor_id; 1584 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1585 struct mlx5_priv *opriv = 1586 rte_eth_devices[port_id].data->dev_private; 1587 if (opriv && 1588 opriv->master && 1589 opriv->domain_id == priv->domain_id && 1590 opriv->sh == priv->sh) { 1591 eth_dev->data->backer_port_id = port_id; 1592 break; 1593 } 1594 } 1595 if (port_id >= RTE_MAX_ETHPORTS) 1596 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1597 } 1598 priv->mp_id.port_id = eth_dev->data->port_id; 1599 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1600 /* 1601 * Store associated network device interface index. This index 1602 * is permanent throughout the lifetime of device. So, we may store 1603 * the ifindex here and use the cached value further. 1604 */ 1605 MLX5_ASSERT(spawn->ifindex); 1606 priv->if_index = spawn->ifindex; 1607 priv->lag_affinity_idx = sh->refcnt - 1; 1608 eth_dev->data->dev_private = priv; 1609 priv->dev_data = eth_dev->data; 1610 eth_dev->data->mac_addrs = priv->mac; 1611 eth_dev->device = dpdk_dev; 1612 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1613 /* Configure the first MAC address by default. */ 1614 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1615 DRV_LOG(ERR, 1616 "port %u cannot get MAC address, is mlx5_en" 1617 " loaded? (errno: %s)", 1618 eth_dev->data->port_id, strerror(rte_errno)); 1619 err = ENODEV; 1620 goto error; 1621 } 1622 DRV_LOG(INFO, 1623 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1624 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1625 #ifdef RTE_LIBRTE_MLX5_DEBUG 1626 { 1627 char ifname[MLX5_NAMESIZE]; 1628 1629 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1630 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1631 eth_dev->data->port_id, ifname); 1632 else 1633 DRV_LOG(DEBUG, "port %u ifname is unknown", 1634 eth_dev->data->port_id); 1635 } 1636 #endif 1637 /* Get actual MTU if possible. */ 1638 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1639 if (err) { 1640 err = rte_errno; 1641 goto error; 1642 } 1643 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1644 priv->mtu); 1645 /* Initialize burst functions to prevent crashes before link-up. */ 1646 eth_dev->rx_pkt_burst = removed_rx_burst; 1647 eth_dev->tx_pkt_burst = removed_tx_burst; 1648 eth_dev->dev_ops = &mlx5_dev_ops; 1649 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1650 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1651 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1652 /* Register MAC address. */ 1653 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1654 if (config->vf && config->vf_nl_en) 1655 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1656 mlx5_ifindex(eth_dev), 1657 eth_dev->data->mac_addrs, 1658 MLX5_MAX_MAC_ADDRESSES); 1659 priv->ctrl_flows = 0; 1660 rte_spinlock_init(&priv->flow_list_lock); 1661 TAILQ_INIT(&priv->flow_meters); 1662 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1663 if (!priv->mtr_profile_tbl) 1664 goto error; 1665 /* Bring Ethernet device up. */ 1666 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1667 eth_dev->data->port_id); 1668 mlx5_set_link_up(eth_dev); 1669 /* 1670 * Even though the interrupt handler is not installed yet, 1671 * interrupts will still trigger on the async_fd from 1672 * Verbs context returned by ibv_open_device(). 1673 */ 1674 mlx5_link_update(eth_dev, 0); 1675 #ifdef HAVE_MLX5DV_DR_ESWITCH 1676 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1677 (switch_info->representor || switch_info->master))) 1678 config->dv_esw_en = 0; 1679 #else 1680 config->dv_esw_en = 0; 1681 #endif 1682 /* Detect minimal data bytes to inline. */ 1683 mlx5_set_min_inline(spawn, config); 1684 /* Store device configuration on private structure. */ 1685 priv->config = *config; 1686 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1687 icfg[i].release_mem_en = !!config->reclaim_mode; 1688 if (config->reclaim_mode) 1689 icfg[i].per_core_cache = 0; 1690 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1691 if (!priv->flows[i]) 1692 goto error; 1693 } 1694 /* Create context for virtual machine VLAN workaround. */ 1695 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1696 if (config->dv_flow_en) { 1697 err = mlx5_alloc_shared_dr(priv); 1698 if (err) 1699 goto error; 1700 if (mlx5_flex_item_port_init(eth_dev) < 0) 1701 goto error; 1702 } 1703 if (sh->devx && config->dv_flow_en && config->dest_tir) { 1704 priv->obj_ops = devx_obj_ops; 1705 mlx5_queue_counter_id_prepare(eth_dev); 1706 priv->obj_ops.lb_dummy_queue_create = 1707 mlx5_rxq_ibv_obj_dummy_lb_create; 1708 priv->obj_ops.lb_dummy_queue_release = 1709 mlx5_rxq_ibv_obj_dummy_lb_release; 1710 } else if (spawn->max_port > UINT8_MAX) { 1711 /* Verbs can't support ports larger than 255 by design. */ 1712 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); 1713 err = ENOTSUP; 1714 goto error; 1715 } else { 1716 priv->obj_ops = ibv_obj_ops; 1717 } 1718 if (config->tx_pp && 1719 (priv->config.dv_esw_en || 1720 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new)) { 1721 /* 1722 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1723 * packet pacing and already checked above. 1724 * Hence, we should only make sure the SQs will be created 1725 * with DevX, not with Verbs. 1726 * Verbs allocates the SQ UAR on its own and it can't be shared 1727 * with Clock Queue UAR as required for Tx scheduling. 1728 */ 1729 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1730 err = ENODEV; 1731 goto error; 1732 } 1733 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1734 if (!priv->drop_queue.hrxq) 1735 goto error; 1736 /* Port representor shares the same max prioirity with pf port. */ 1737 if (!priv->sh->flow_priority_check_flag) { 1738 /* Supported Verbs flow priority number detection. */ 1739 err = mlx5_flow_discover_priorities(eth_dev); 1740 priv->sh->flow_max_priority = err; 1741 priv->sh->flow_priority_check_flag = 1; 1742 } else { 1743 err = priv->sh->flow_max_priority; 1744 } 1745 if (err < 0) { 1746 err = -err; 1747 goto error; 1748 } 1749 if (!priv->config.dv_esw_en && 1750 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1751 DRV_LOG(WARNING, "metadata mode %u is not supported " 1752 "(no E-Switch)", priv->config.dv_xmeta_en); 1753 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1754 } 1755 mlx5_set_metadata_mask(eth_dev); 1756 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1757 !priv->sh->dv_regc0_mask) { 1758 DRV_LOG(ERR, "metadata mode %u is not supported " 1759 "(no metadata reg_c[0] is available)", 1760 priv->config.dv_xmeta_en); 1761 err = ENOTSUP; 1762 goto error; 1763 } 1764 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1765 mlx5_hrxq_create_cb, 1766 mlx5_hrxq_match_cb, 1767 mlx5_hrxq_remove_cb, 1768 mlx5_hrxq_clone_cb, 1769 mlx5_hrxq_clone_free_cb); 1770 if (!priv->hrxqs) 1771 goto error; 1772 rte_rwlock_init(&priv->ind_tbls_lock); 1773 /* Query availability of metadata reg_c's. */ 1774 if (!priv->sh->metadata_regc_check_flag) { 1775 err = mlx5_flow_discover_mreg_c(eth_dev); 1776 if (err < 0) { 1777 err = -err; 1778 goto error; 1779 } 1780 } 1781 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1782 DRV_LOG(DEBUG, 1783 "port %u extensive metadata register is not supported", 1784 eth_dev->data->port_id); 1785 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1786 DRV_LOG(ERR, "metadata mode %u is not supported " 1787 "(no metadata registers available)", 1788 priv->config.dv_xmeta_en); 1789 err = ENOTSUP; 1790 goto error; 1791 } 1792 } 1793 if (priv->config.dv_flow_en && 1794 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1795 mlx5_flow_ext_mreg_supported(eth_dev) && 1796 priv->sh->dv_regc0_mask) { 1797 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1798 MLX5_FLOW_MREG_HTABLE_SZ, 1799 false, true, eth_dev, 1800 flow_dv_mreg_create_cb, 1801 flow_dv_mreg_match_cb, 1802 flow_dv_mreg_remove_cb, 1803 flow_dv_mreg_clone_cb, 1804 flow_dv_mreg_clone_free_cb); 1805 if (!priv->mreg_cp_tbl) { 1806 err = ENOMEM; 1807 goto error; 1808 } 1809 } 1810 rte_spinlock_init(&priv->shared_act_sl); 1811 mlx5_flow_counter_mode_config(eth_dev); 1812 mlx5_flow_drop_action_config(eth_dev); 1813 if (priv->config.dv_flow_en) 1814 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1815 return eth_dev; 1816 error: 1817 if (priv) { 1818 if (priv->mreg_cp_tbl) 1819 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1820 if (priv->sh) 1821 mlx5_os_free_shared_dr(priv); 1822 if (priv->nl_socket_route >= 0) 1823 close(priv->nl_socket_route); 1824 if (priv->vmwa_context) 1825 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1826 if (eth_dev && priv->drop_queue.hrxq) 1827 mlx5_drop_action_destroy(eth_dev); 1828 if (priv->mtr_profile_tbl) 1829 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1830 if (own_domain_id) 1831 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1832 if (priv->hrxqs) 1833 mlx5_list_destroy(priv->hrxqs); 1834 if (eth_dev && priv->flex_item_map) 1835 mlx5_flex_item_port_cleanup(eth_dev); 1836 mlx5_free(priv); 1837 if (eth_dev != NULL) 1838 eth_dev->data->dev_private = NULL; 1839 } 1840 if (eth_dev != NULL) { 1841 /* mac_addrs must not be freed alone because part of 1842 * dev_private 1843 **/ 1844 eth_dev->data->mac_addrs = NULL; 1845 rte_eth_dev_release_port(eth_dev); 1846 } 1847 if (sh) 1848 mlx5_free_shared_dev_ctx(sh); 1849 if (nl_rdma >= 0) 1850 close(nl_rdma); 1851 MLX5_ASSERT(err > 0); 1852 rte_errno = err; 1853 return NULL; 1854 } 1855 1856 /** 1857 * Comparison callback to sort device data. 1858 * 1859 * This is meant to be used with qsort(). 1860 * 1861 * @param a[in] 1862 * Pointer to pointer to first data object. 1863 * @param b[in] 1864 * Pointer to pointer to second data object. 1865 * 1866 * @return 1867 * 0 if both objects are equal, less than 0 if the first argument is less 1868 * than the second, greater than 0 otherwise. 1869 */ 1870 static int 1871 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1872 { 1873 const struct mlx5_switch_info *si_a = 1874 &((const struct mlx5_dev_spawn_data *)a)->info; 1875 const struct mlx5_switch_info *si_b = 1876 &((const struct mlx5_dev_spawn_data *)b)->info; 1877 int ret; 1878 1879 /* Master device first. */ 1880 ret = si_b->master - si_a->master; 1881 if (ret) 1882 return ret; 1883 /* Then representor devices. */ 1884 ret = si_b->representor - si_a->representor; 1885 if (ret) 1886 return ret; 1887 /* Unidentified devices come last in no specific order. */ 1888 if (!si_a->representor) 1889 return 0; 1890 /* Order representors by name. */ 1891 return si_a->port_name - si_b->port_name; 1892 } 1893 1894 /** 1895 * Match PCI information for possible slaves of bonding device. 1896 * 1897 * @param[in] ibdev_name 1898 * Name of Infiniband device. 1899 * @param[in] pci_dev 1900 * Pointer to primary PCI address structure to match. 1901 * @param[in] nl_rdma 1902 * Netlink RDMA group socket handle. 1903 * @param[in] owner 1904 * Representor owner PF index. 1905 * @param[out] bond_info 1906 * Pointer to bonding information. 1907 * 1908 * @return 1909 * negative value if no bonding device found, otherwise 1910 * positive index of slave PF in bonding. 1911 */ 1912 static int 1913 mlx5_device_bond_pci_match(const char *ibdev_name, 1914 const struct rte_pci_addr *pci_dev, 1915 int nl_rdma, uint16_t owner, 1916 struct mlx5_bond_info *bond_info) 1917 { 1918 char ifname[IF_NAMESIZE + 1]; 1919 unsigned int ifindex; 1920 unsigned int np, i; 1921 FILE *bond_file = NULL, *file; 1922 int pf = -1; 1923 int ret; 1924 uint8_t cur_guid[32] = {0}; 1925 uint8_t guid[32] = {0}; 1926 1927 /* 1928 * Try to get master device name. If something goes wrong suppose 1929 * the lack of kernel support and no bonding devices. 1930 */ 1931 memset(bond_info, 0, sizeof(*bond_info)); 1932 if (nl_rdma < 0) 1933 return -1; 1934 if (!strstr(ibdev_name, "bond")) 1935 return -1; 1936 np = mlx5_nl_portnum(nl_rdma, ibdev_name); 1937 if (!np) 1938 return -1; 1939 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) 1940 return -1; 1941 /* 1942 * The master device might not be on the predefined port(not on port 1943 * index 1, it is not guaranteed), we have to scan all Infiniband 1944 * device ports and find master. 1945 */ 1946 for (i = 1; i <= np; ++i) { 1947 /* Check whether Infiniband port is populated. */ 1948 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); 1949 if (!ifindex) 1950 continue; 1951 if (!if_indextoname(ifindex, ifname)) 1952 continue; 1953 /* Try to read bonding slave names from sysfs. */ 1954 MKSTR(slaves, 1955 "/sys/class/net/%s/master/bonding/slaves", ifname); 1956 bond_file = fopen(slaves, "r"); 1957 if (bond_file) 1958 break; 1959 } 1960 if (!bond_file) 1961 return -1; 1962 /* Use safe format to check maximal buffer length. */ 1963 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1964 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1965 char tmp_str[IF_NAMESIZE + 32]; 1966 struct rte_pci_addr pci_addr; 1967 struct mlx5_switch_info info; 1968 int ret; 1969 1970 /* Process slave interface names in the loop. */ 1971 snprintf(tmp_str, sizeof(tmp_str), 1972 "/sys/class/net/%s", ifname); 1973 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 1974 DRV_LOG(WARNING, 1975 "Cannot get PCI address for netdev \"%s\".", 1976 ifname); 1977 continue; 1978 } 1979 /* Slave interface PCI address match found. */ 1980 snprintf(tmp_str, sizeof(tmp_str), 1981 "/sys/class/net/%s/phys_port_name", ifname); 1982 file = fopen(tmp_str, "rb"); 1983 if (!file) 1984 break; 1985 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1986 if (fscanf(file, "%32s", tmp_str) == 1) 1987 mlx5_translate_port_name(tmp_str, &info); 1988 fclose(file); 1989 /* Only process PF ports. */ 1990 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1991 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1992 continue; 1993 /* Check max bonding member. */ 1994 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1995 DRV_LOG(WARNING, "bonding index out of range, " 1996 "please increase MLX5_BOND_MAX_PORTS: %s", 1997 tmp_str); 1998 break; 1999 } 2000 /* Get ifindex. */ 2001 snprintf(tmp_str, sizeof(tmp_str), 2002 "/sys/class/net/%s/ifindex", ifname); 2003 file = fopen(tmp_str, "rb"); 2004 if (!file) 2005 break; 2006 ret = fscanf(file, "%u", &ifindex); 2007 fclose(file); 2008 if (ret != 1) 2009 break; 2010 /* Save bonding info. */ 2011 strncpy(bond_info->ports[info.port_name].ifname, ifname, 2012 sizeof(bond_info->ports[0].ifname)); 2013 bond_info->ports[info.port_name].pci_addr = pci_addr; 2014 bond_info->ports[info.port_name].ifindex = ifindex; 2015 bond_info->n_port++; 2016 /* 2017 * Under socket direct mode, bonding will use 2018 * system_image_guid as identification. 2019 * After OFED 5.4, guid is readable (ret >= 0) under sysfs. 2020 * All bonding members should have the same guid even if driver 2021 * is using PCIe BDF. 2022 */ 2023 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid)); 2024 if (ret < 0) 2025 break; 2026 else if (ret > 0) { 2027 if (!memcmp(guid, cur_guid, sizeof(guid)) && 2028 owner == info.port_name && 2029 (owner != 0 || (owner == 0 && 2030 !rte_pci_addr_cmp(pci_dev, &pci_addr)))) 2031 pf = info.port_name; 2032 } else if (pci_dev->domain == pci_addr.domain && 2033 pci_dev->bus == pci_addr.bus && 2034 pci_dev->devid == pci_addr.devid && 2035 ((pci_dev->function == 0 && 2036 pci_dev->function + owner == pci_addr.function) || 2037 (pci_dev->function == owner && 2038 pci_addr.function == owner))) 2039 pf = info.port_name; 2040 } 2041 if (pf >= 0) { 2042 /* Get bond interface info */ 2043 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2044 bond_info->ifname); 2045 if (ret) 2046 DRV_LOG(ERR, "unable to get bond info: %s", 2047 strerror(rte_errno)); 2048 else 2049 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2050 ifindex, bond_info->ifindex, bond_info->ifname); 2051 } 2052 if (owner == 0 && pf != 0) { 2053 DRV_LOG(INFO, "PCIe instance %04x:%02x:%02x.%x isn't bonding owner", 2054 pci_dev->domain, pci_dev->bus, pci_dev->devid, 2055 pci_dev->function); 2056 } 2057 return pf; 2058 } 2059 2060 static void 2061 mlx5_os_config_default(struct mlx5_dev_config *config) 2062 { 2063 memset(config, 0, sizeof(*config)); 2064 config->mps = MLX5_ARG_UNSET; 2065 config->rx_vec_en = 1; 2066 config->txq_inline_max = MLX5_ARG_UNSET; 2067 config->txq_inline_min = MLX5_ARG_UNSET; 2068 config->txq_inline_mpw = MLX5_ARG_UNSET; 2069 config->txqs_inline = MLX5_ARG_UNSET; 2070 config->vf_nl_en = 1; 2071 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2072 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2073 config->dv_esw_en = 1; 2074 config->dv_flow_en = 1; 2075 config->decap_en = 1; 2076 config->log_hp_size = MLX5_ARG_UNSET; 2077 config->allow_duplicate_pattern = 1; 2078 } 2079 2080 /** 2081 * Register a PCI device within bonding. 2082 * 2083 * This function spawns Ethernet devices out of a given PCI device and 2084 * bonding owner PF index. 2085 * 2086 * @param[in] cdev 2087 * Pointer to common mlx5 device structure. 2088 * @param[in] req_eth_da 2089 * Requested ethdev device argument. 2090 * @param[in] owner_id 2091 * Requested owner PF port ID within bonding device, default to 0. 2092 * 2093 * @return 2094 * 0 on success, a negative errno value otherwise and rte_errno is set. 2095 */ 2096 static int 2097 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, 2098 struct rte_eth_devargs *req_eth_da, 2099 uint16_t owner_id) 2100 { 2101 struct ibv_device **ibv_list; 2102 /* 2103 * Number of found IB Devices matching with requested PCI BDF. 2104 * nd != 1 means there are multiple IB devices over the same 2105 * PCI device and we have representors and master. 2106 */ 2107 unsigned int nd = 0; 2108 /* 2109 * Number of found IB device Ports. nd = 1 and np = 1..n means 2110 * we have the single multiport IB device, and there may be 2111 * representors attached to some of found ports. 2112 */ 2113 unsigned int np = 0; 2114 /* 2115 * Number of DPDK ethernet devices to Spawn - either over 2116 * multiple IB devices or multiple ports of single IB device. 2117 * Actually this is the number of iterations to spawn. 2118 */ 2119 unsigned int ns = 0; 2120 /* 2121 * Bonding device 2122 * < 0 - no bonding device (single one) 2123 * >= 0 - bonding device (value is slave PF index) 2124 */ 2125 int bd = -1; 2126 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2127 struct mlx5_dev_spawn_data *list = NULL; 2128 struct mlx5_dev_config dev_config; 2129 unsigned int dev_config_vf; 2130 struct rte_eth_devargs eth_da = *req_eth_da; 2131 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2132 struct mlx5_bond_info bond_info; 2133 int ret = -1; 2134 2135 errno = 0; 2136 ibv_list = mlx5_glue->get_device_list(&ret); 2137 if (!ibv_list) { 2138 rte_errno = errno ? errno : ENOSYS; 2139 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?"); 2140 return -rte_errno; 2141 } 2142 /* 2143 * First scan the list of all Infiniband devices to find 2144 * matching ones, gathering into the list. 2145 */ 2146 struct ibv_device *ibv_match[ret + 1]; 2147 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2148 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2149 unsigned int i; 2150 2151 while (ret-- > 0) { 2152 struct rte_pci_addr pci_addr; 2153 2154 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); 2155 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, 2156 nl_rdma, owner_id, &bond_info); 2157 if (bd >= 0) { 2158 /* 2159 * Bonding device detected. Only one match is allowed, 2160 * the bonding is supported over multi-port IB device, 2161 * there should be no matches on representor PCI 2162 * functions or non VF LAG bonding devices with 2163 * specified address. 2164 */ 2165 if (nd) { 2166 DRV_LOG(ERR, 2167 "multiple PCI match on bonding device" 2168 "\"%s\" found", ibv_list[ret]->name); 2169 rte_errno = ENOENT; 2170 ret = -rte_errno; 2171 goto exit; 2172 } 2173 /* Amend owner pci address if owner PF ID specified. */ 2174 if (eth_da.nb_representor_ports) 2175 owner_pci.function += owner_id; 2176 DRV_LOG(INFO, 2177 "PCI information matches for slave %d bonding device \"%s\"", 2178 bd, ibv_list[ret]->name); 2179 ibv_match[nd++] = ibv_list[ret]; 2180 break; 2181 } else { 2182 /* Bonding device not found. */ 2183 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2184 &pci_addr)) 2185 continue; 2186 if (owner_pci.domain != pci_addr.domain || 2187 owner_pci.bus != pci_addr.bus || 2188 owner_pci.devid != pci_addr.devid || 2189 owner_pci.function != pci_addr.function) 2190 continue; 2191 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2192 ibv_list[ret]->name); 2193 ibv_match[nd++] = ibv_list[ret]; 2194 } 2195 } 2196 ibv_match[nd] = NULL; 2197 if (!nd) { 2198 /* No device matches, just complain and bail out. */ 2199 DRV_LOG(WARNING, 2200 "No Verbs device matches PCI device " PCI_PRI_FMT "," 2201 " are kernel drivers loaded?", 2202 owner_pci.domain, owner_pci.bus, 2203 owner_pci.devid, owner_pci.function); 2204 rte_errno = ENOENT; 2205 ret = -rte_errno; 2206 goto exit; 2207 } 2208 if (nd == 1) { 2209 /* 2210 * Found single matching device may have multiple ports. 2211 * Each port may be representor, we have to check the port 2212 * number and check the representors existence. 2213 */ 2214 if (nl_rdma >= 0) 2215 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2216 if (!np) 2217 DRV_LOG(WARNING, 2218 "Cannot get IB device \"%s\" ports number.", 2219 ibv_match[0]->name); 2220 if (bd >= 0 && !np) { 2221 DRV_LOG(ERR, "Cannot get ports for bonding device."); 2222 rte_errno = ENOENT; 2223 ret = -rte_errno; 2224 goto exit; 2225 } 2226 } 2227 /* Now we can determine the maximal amount of devices to be spawned. */ 2228 list = mlx5_malloc(MLX5_MEM_ZERO, 2229 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd), 2230 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2231 if (!list) { 2232 DRV_LOG(ERR, "Spawn data array allocation failure."); 2233 rte_errno = ENOMEM; 2234 ret = -rte_errno; 2235 goto exit; 2236 } 2237 if (bd >= 0 || np > 1) { 2238 /* 2239 * Single IB device with multiple ports found, 2240 * it may be E-Switch master device and representors. 2241 * We have to perform identification through the ports. 2242 */ 2243 MLX5_ASSERT(nl_rdma >= 0); 2244 MLX5_ASSERT(ns == 0); 2245 MLX5_ASSERT(nd == 1); 2246 MLX5_ASSERT(np); 2247 for (i = 1; i <= np; ++i) { 2248 list[ns].bond_info = &bond_info; 2249 list[ns].max_port = np; 2250 list[ns].phys_port = i; 2251 list[ns].phys_dev_name = ibv_match[0]->name; 2252 list[ns].eth_dev = NULL; 2253 list[ns].pci_dev = pci_dev; 2254 list[ns].cdev = cdev; 2255 list[ns].pf_bond = bd; 2256 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, 2257 ibv_match[0]->name, 2258 i); 2259 if (!list[ns].ifindex) { 2260 /* 2261 * No network interface index found for the 2262 * specified port, it means there is no 2263 * representor on this port. It's OK, 2264 * there can be disabled ports, for example 2265 * if sriov_numvfs < sriov_totalvfs. 2266 */ 2267 continue; 2268 } 2269 ret = -1; 2270 if (nl_route >= 0) 2271 ret = mlx5_nl_switch_info(nl_route, 2272 list[ns].ifindex, 2273 &list[ns].info); 2274 if (ret || (!list[ns].info.representor && 2275 !list[ns].info.master)) { 2276 /* 2277 * We failed to recognize representors with 2278 * Netlink, let's try to perform the task 2279 * with sysfs. 2280 */ 2281 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2282 &list[ns].info); 2283 } 2284 if (!ret && bd >= 0) { 2285 switch (list[ns].info.name_type) { 2286 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2287 if (np == 1) { 2288 /* 2289 * Force standalone bonding 2290 * device for ROCE LAG 2291 * confgiurations. 2292 */ 2293 list[ns].info.master = 0; 2294 list[ns].info.representor = 0; 2295 } 2296 if (list[ns].info.port_name == bd) 2297 ns++; 2298 break; 2299 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2300 /* Fallthrough */ 2301 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2302 /* Fallthrough */ 2303 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2304 if (list[ns].info.pf_num == bd) 2305 ns++; 2306 break; 2307 default: 2308 break; 2309 } 2310 continue; 2311 } 2312 if (!ret && (list[ns].info.representor ^ 2313 list[ns].info.master)) 2314 ns++; 2315 } 2316 if (!ns) { 2317 DRV_LOG(ERR, 2318 "Unable to recognize master/representors on the IB device with multiple ports."); 2319 rte_errno = ENOENT; 2320 ret = -rte_errno; 2321 goto exit; 2322 } 2323 } else { 2324 /* 2325 * The existence of several matching entries (nd > 1) means 2326 * port representors have been instantiated. No existing Verbs 2327 * call nor sysfs entries can tell them apart, this can only 2328 * be done through Netlink calls assuming kernel drivers are 2329 * recent enough to support them. 2330 * 2331 * In the event of identification failure through Netlink, 2332 * try again through sysfs, then: 2333 * 2334 * 1. A single IB device matches (nd == 1) with single 2335 * port (np=0/1) and is not a representor, assume 2336 * no switch support. 2337 * 2338 * 2. Otherwise no safe assumptions can be made; 2339 * complain louder and bail out. 2340 */ 2341 for (i = 0; i != nd; ++i) { 2342 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2343 list[ns].bond_info = NULL; 2344 list[ns].max_port = 1; 2345 list[ns].phys_port = 1; 2346 list[ns].phys_dev_name = ibv_match[i]->name; 2347 list[ns].eth_dev = NULL; 2348 list[ns].pci_dev = pci_dev; 2349 list[ns].cdev = cdev; 2350 list[ns].pf_bond = -1; 2351 list[ns].ifindex = 0; 2352 if (nl_rdma >= 0) 2353 list[ns].ifindex = mlx5_nl_ifindex 2354 (nl_rdma, 2355 ibv_match[i]->name, 2356 1); 2357 if (!list[ns].ifindex) { 2358 char ifname[IF_NAMESIZE]; 2359 2360 /* 2361 * Netlink failed, it may happen with old 2362 * ib_core kernel driver (before 4.16). 2363 * We can assume there is old driver because 2364 * here we are processing single ports IB 2365 * devices. Let's try sysfs to retrieve 2366 * the ifindex. The method works for 2367 * master device only. 2368 */ 2369 if (nd > 1) { 2370 /* 2371 * Multiple devices found, assume 2372 * representors, can not distinguish 2373 * master/representor and retrieve 2374 * ifindex via sysfs. 2375 */ 2376 continue; 2377 } 2378 ret = mlx5_get_ifname_sysfs 2379 (ibv_match[i]->ibdev_path, ifname); 2380 if (!ret) 2381 list[ns].ifindex = 2382 if_nametoindex(ifname); 2383 if (!list[ns].ifindex) { 2384 /* 2385 * No network interface index found 2386 * for the specified device, it means 2387 * there it is neither representor 2388 * nor master. 2389 */ 2390 continue; 2391 } 2392 } 2393 ret = -1; 2394 if (nl_route >= 0) 2395 ret = mlx5_nl_switch_info(nl_route, 2396 list[ns].ifindex, 2397 &list[ns].info); 2398 if (ret || (!list[ns].info.representor && 2399 !list[ns].info.master)) { 2400 /* 2401 * We failed to recognize representors with 2402 * Netlink, let's try to perform the task 2403 * with sysfs. 2404 */ 2405 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2406 &list[ns].info); 2407 } 2408 if (!ret && (list[ns].info.representor ^ 2409 list[ns].info.master)) { 2410 ns++; 2411 } else if ((nd == 1) && 2412 !list[ns].info.representor && 2413 !list[ns].info.master) { 2414 /* 2415 * Single IB device with one physical port and 2416 * attached network device. 2417 * May be SRIOV is not enabled or there is no 2418 * representors. 2419 */ 2420 DRV_LOG(INFO, "No E-Switch support detected."); 2421 ns++; 2422 break; 2423 } 2424 } 2425 if (!ns) { 2426 DRV_LOG(ERR, 2427 "Unable to recognize master/representors on the multiple IB devices."); 2428 rte_errno = ENOENT; 2429 ret = -rte_errno; 2430 goto exit; 2431 } 2432 /* 2433 * New kernels may add the switch_id attribute for the case 2434 * there is no E-Switch and we wrongly recognized the only 2435 * device as master. Override this if there is the single 2436 * device with single port and new device name format present. 2437 */ 2438 if (nd == 1 && 2439 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2440 list[0].info.master = 0; 2441 list[0].info.representor = 0; 2442 } 2443 } 2444 MLX5_ASSERT(ns); 2445 /* 2446 * Sort list to probe devices in natural order for users convenience 2447 * (i.e. master first, then representors from lowest to highest ID). 2448 */ 2449 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2450 /* Device specific configuration. */ 2451 switch (pci_dev->id.device_id) { 2452 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2453 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2454 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2455 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2456 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2457 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2458 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2459 dev_config_vf = 1; 2460 break; 2461 default: 2462 dev_config_vf = 0; 2463 break; 2464 } 2465 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2466 /* Set devargs default values. */ 2467 if (eth_da.nb_mh_controllers == 0) { 2468 eth_da.nb_mh_controllers = 1; 2469 eth_da.mh_controllers[0] = 0; 2470 } 2471 if (eth_da.nb_ports == 0 && ns > 0) { 2472 if (list[0].pf_bond >= 0 && list[0].info.representor) 2473 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2474 pci_dev->device.devargs->args); 2475 eth_da.nb_ports = 1; 2476 eth_da.ports[0] = list[0].info.pf_num; 2477 } 2478 if (eth_da.nb_representor_ports == 0) { 2479 eth_da.nb_representor_ports = 1; 2480 eth_da.representor_ports[0] = 0; 2481 } 2482 } 2483 for (i = 0; i != ns; ++i) { 2484 uint32_t restore; 2485 2486 /* Default configuration. */ 2487 mlx5_os_config_default(&dev_config); 2488 dev_config.vf = dev_config_vf; 2489 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], 2490 &dev_config, ð_da); 2491 if (!list[i].eth_dev) { 2492 if (rte_errno != EBUSY && rte_errno != EEXIST) 2493 break; 2494 /* Device is disabled or already spawned. Ignore it. */ 2495 continue; 2496 } 2497 restore = list[i].eth_dev->data->dev_flags; 2498 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2499 /** 2500 * Each representor has a dedicated interrupts vector. 2501 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2502 * representor eth_dev object because representor and PF 2503 * share the same PCI address. 2504 * Override representor device with a dedicated 2505 * interrupts handle here. 2506 * Representor interrupts handle is released in mlx5_dev_stop(). 2507 */ 2508 if (list[i].info.representor) { 2509 struct rte_intr_handle *intr_handle = 2510 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2511 if (intr_handle == NULL) { 2512 DRV_LOG(ERR, 2513 "port %u failed to allocate memory for interrupt handler " 2514 "Rx interrupts will not be supported", 2515 i); 2516 rte_errno = ENOMEM; 2517 ret = -rte_errno; 2518 goto exit; 2519 } 2520 list[i].eth_dev->intr_handle = intr_handle; 2521 } 2522 /* Restore non-PCI flags cleared by the above call. */ 2523 list[i].eth_dev->data->dev_flags |= restore; 2524 rte_eth_dev_probing_finish(list[i].eth_dev); 2525 } 2526 if (i != ns) { 2527 DRV_LOG(ERR, 2528 "probe of PCI device " PCI_PRI_FMT " aborted after" 2529 " encountering an error: %s", 2530 owner_pci.domain, owner_pci.bus, 2531 owner_pci.devid, owner_pci.function, 2532 strerror(rte_errno)); 2533 ret = -rte_errno; 2534 /* Roll back. */ 2535 while (i--) { 2536 if (!list[i].eth_dev) 2537 continue; 2538 mlx5_dev_close(list[i].eth_dev); 2539 /* mac_addrs must not be freed because in dev_private */ 2540 list[i].eth_dev->data->mac_addrs = NULL; 2541 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2542 } 2543 /* Restore original error. */ 2544 rte_errno = -ret; 2545 } else { 2546 ret = 0; 2547 } 2548 exit: 2549 /* 2550 * Do the routine cleanup: 2551 * - close opened Netlink sockets 2552 * - free allocated spawn data array 2553 * - free the Infiniband device list 2554 */ 2555 if (nl_rdma >= 0) 2556 close(nl_rdma); 2557 if (nl_route >= 0) 2558 close(nl_route); 2559 if (list) 2560 mlx5_free(list); 2561 MLX5_ASSERT(ibv_list); 2562 mlx5_glue->free_device_list(ibv_list); 2563 return ret; 2564 } 2565 2566 static int 2567 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2568 struct rte_eth_devargs *eth_da) 2569 { 2570 int ret = 0; 2571 2572 if (dev->devargs == NULL) 2573 return 0; 2574 memset(eth_da, 0, sizeof(*eth_da)); 2575 /* Parse representor information first from class argument. */ 2576 if (dev->devargs->cls_str) 2577 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2578 if (ret != 0) { 2579 DRV_LOG(ERR, "failed to parse device arguments: %s", 2580 dev->devargs->cls_str); 2581 return -rte_errno; 2582 } 2583 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2584 /* Parse legacy device argument */ 2585 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2586 if (ret) { 2587 DRV_LOG(ERR, "failed to parse device arguments: %s", 2588 dev->devargs->args); 2589 return -rte_errno; 2590 } 2591 } 2592 return 0; 2593 } 2594 2595 /** 2596 * Callback to register a PCI device. 2597 * 2598 * This function spawns Ethernet devices out of a given PCI device. 2599 * 2600 * @param[in] cdev 2601 * Pointer to common mlx5 device structure. 2602 * 2603 * @return 2604 * 0 on success, a negative errno value otherwise and rte_errno is set. 2605 */ 2606 static int 2607 mlx5_os_pci_probe(struct mlx5_common_device *cdev) 2608 { 2609 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2610 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2611 int ret = 0; 2612 uint16_t p; 2613 2614 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da); 2615 if (ret != 0) 2616 return ret; 2617 2618 if (eth_da.nb_ports > 0) { 2619 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2620 for (p = 0; p < eth_da.nb_ports; p++) { 2621 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 2622 eth_da.ports[p]); 2623 if (ret) 2624 break; 2625 } 2626 if (ret) { 2627 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2628 "aborted due to proding failure of PF %u", 2629 pci_dev->addr.domain, pci_dev->addr.bus, 2630 pci_dev->addr.devid, pci_dev->addr.function, 2631 eth_da.ports[p]); 2632 mlx5_net_remove(cdev); 2633 } 2634 } else { 2635 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0); 2636 } 2637 return ret; 2638 } 2639 2640 /* Probe a single SF device on auxiliary bus, no representor support. */ 2641 static int 2642 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev) 2643 { 2644 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2645 struct mlx5_dev_config config; 2646 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2647 struct rte_device *dev = cdev->dev; 2648 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2649 struct rte_eth_dev *eth_dev; 2650 int ret = 0; 2651 2652 /* Parse ethdev devargs. */ 2653 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2654 if (ret != 0) 2655 return ret; 2656 /* Set default config data. */ 2657 mlx5_os_config_default(&config); 2658 config.sf = 1; 2659 /* Init spawn data. */ 2660 spawn.max_port = 1; 2661 spawn.phys_port = 1; 2662 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 2663 ret = mlx5_auxiliary_get_ifindex(dev->name); 2664 if (ret < 0) { 2665 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2666 return ret; 2667 } 2668 spawn.ifindex = ret; 2669 spawn.cdev = cdev; 2670 /* Spawn device. */ 2671 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2672 if (eth_dev == NULL) 2673 return -rte_errno; 2674 /* Post create. */ 2675 eth_dev->intr_handle = adev->intr_handle; 2676 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2677 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2678 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2679 eth_dev->data->numa_node = dev->numa_node; 2680 } 2681 rte_eth_dev_probing_finish(eth_dev); 2682 return 0; 2683 } 2684 2685 /** 2686 * Net class driver callback to probe a device. 2687 * 2688 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2689 * 2690 * @param[in] cdev 2691 * Pointer to the common mlx5 device. 2692 * 2693 * @return 2694 * 0 on success, a negative errno value otherwise and rte_errno is set. 2695 */ 2696 int 2697 mlx5_os_net_probe(struct mlx5_common_device *cdev) 2698 { 2699 int ret; 2700 2701 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2702 mlx5_pmd_socket_init(); 2703 ret = mlx5_init_once(); 2704 if (ret) { 2705 DRV_LOG(ERR, "Unable to init PMD global data: %s", 2706 strerror(rte_errno)); 2707 return -rte_errno; 2708 } 2709 if (mlx5_dev_is_pci(cdev->dev)) 2710 return mlx5_os_pci_probe(cdev); 2711 else 2712 return mlx5_os_auxiliary_probe(cdev); 2713 } 2714 2715 /** 2716 * Cleanup resources when the last device is closed. 2717 */ 2718 void 2719 mlx5_os_net_cleanup(void) 2720 { 2721 mlx5_pmd_socket_uninit(); 2722 } 2723 2724 /** 2725 * Install shared asynchronous device events handler. 2726 * This function is implemented to support event sharing 2727 * between multiple ports of single IB device. 2728 * 2729 * @param sh 2730 * Pointer to mlx5_dev_ctx_shared object. 2731 */ 2732 void 2733 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2734 { 2735 int ret; 2736 int flags; 2737 struct ibv_context *ctx = sh->cdev->ctx; 2738 2739 sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2740 if (sh->intr_handle == NULL) { 2741 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2742 rte_errno = ENOMEM; 2743 return; 2744 } 2745 rte_intr_fd_set(sh->intr_handle, -1); 2746 2747 flags = fcntl(ctx->async_fd, F_GETFL); 2748 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); 2749 if (ret) { 2750 DRV_LOG(INFO, "failed to change file descriptor async event" 2751 " queue"); 2752 } else { 2753 rte_intr_fd_set(sh->intr_handle, ctx->async_fd); 2754 rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); 2755 if (rte_intr_callback_register(sh->intr_handle, 2756 mlx5_dev_interrupt_handler, sh)) { 2757 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2758 rte_intr_fd_set(sh->intr_handle, -1); 2759 } 2760 } 2761 if (sh->devx) { 2762 #ifdef HAVE_IBV_DEVX_ASYNC 2763 sh->intr_handle_devx = 2764 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2765 if (!sh->intr_handle_devx) { 2766 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2767 rte_errno = ENOMEM; 2768 return; 2769 } 2770 rte_intr_fd_set(sh->intr_handle_devx, -1); 2771 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); 2772 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2773 if (!devx_comp) { 2774 DRV_LOG(INFO, "failed to allocate devx_comp."); 2775 return; 2776 } 2777 flags = fcntl(devx_comp->fd, F_GETFL); 2778 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2779 if (ret) { 2780 DRV_LOG(INFO, "failed to change file descriptor" 2781 " devx comp"); 2782 return; 2783 } 2784 rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); 2785 rte_intr_type_set(sh->intr_handle_devx, 2786 RTE_INTR_HANDLE_EXT); 2787 if (rte_intr_callback_register(sh->intr_handle_devx, 2788 mlx5_dev_interrupt_handler_devx, sh)) { 2789 DRV_LOG(INFO, "Fail to install the devx shared" 2790 " interrupt."); 2791 rte_intr_fd_set(sh->intr_handle_devx, -1); 2792 } 2793 #endif /* HAVE_IBV_DEVX_ASYNC */ 2794 } 2795 } 2796 2797 /** 2798 * Uninstall shared asynchronous device events handler. 2799 * This function is implemented to support event sharing 2800 * between multiple ports of single IB device. 2801 * 2802 * @param dev 2803 * Pointer to mlx5_dev_ctx_shared object. 2804 */ 2805 void 2806 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2807 { 2808 if (rte_intr_fd_get(sh->intr_handle) >= 0) 2809 mlx5_intr_callback_unregister(sh->intr_handle, 2810 mlx5_dev_interrupt_handler, sh); 2811 rte_intr_instance_free(sh->intr_handle); 2812 #ifdef HAVE_IBV_DEVX_ASYNC 2813 if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) 2814 rte_intr_callback_unregister(sh->intr_handle_devx, 2815 mlx5_dev_interrupt_handler_devx, sh); 2816 rte_intr_instance_free(sh->intr_handle_devx); 2817 if (sh->devx_comp) 2818 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2819 #endif 2820 } 2821 2822 /** 2823 * Read statistics by a named counter. 2824 * 2825 * @param[in] priv 2826 * Pointer to the private device data structure. 2827 * @param[in] ctr_name 2828 * Pointer to the name of the statistic counter to read 2829 * @param[out] stat 2830 * Pointer to read statistic value. 2831 * @return 2832 * 0 on success and stat is valud, 1 if failed to read the value 2833 * rte_errno is set. 2834 * 2835 */ 2836 int 2837 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2838 uint64_t *stat) 2839 { 2840 int fd; 2841 2842 if (priv->sh) { 2843 if (priv->q_counters != NULL && 2844 strcmp(ctr_name, "out_of_buffer") == 0) 2845 return mlx5_devx_cmd_queue_counter_query 2846 (priv->q_counters, 0, (uint32_t *)stat); 2847 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2848 priv->sh->ibdev_path, 2849 priv->dev_port, 2850 ctr_name); 2851 fd = open(path, O_RDONLY); 2852 /* 2853 * in switchdev the file location is not per port 2854 * but rather in <ibdev_path>/hw_counters/<file_name>. 2855 */ 2856 if (fd == -1) { 2857 MKSTR(path1, "%s/hw_counters/%s", 2858 priv->sh->ibdev_path, 2859 ctr_name); 2860 fd = open(path1, O_RDONLY); 2861 } 2862 if (fd != -1) { 2863 char buf[21] = {'\0'}; 2864 ssize_t n = read(fd, buf, sizeof(buf)); 2865 2866 close(fd); 2867 if (n != -1) { 2868 *stat = strtoull(buf, NULL, 10); 2869 return 0; 2870 } 2871 } 2872 } 2873 *stat = 0; 2874 return 1; 2875 } 2876 2877 /** 2878 * Remove a MAC address from device 2879 * 2880 * @param dev 2881 * Pointer to Ethernet device structure. 2882 * @param index 2883 * MAC address index. 2884 */ 2885 void 2886 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2887 { 2888 struct mlx5_priv *priv = dev->data->dev_private; 2889 const int vf = priv->config.vf; 2890 2891 if (vf) 2892 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2893 mlx5_ifindex(dev), priv->mac_own, 2894 &dev->data->mac_addrs[index], index); 2895 } 2896 2897 /** 2898 * Adds a MAC address to the device 2899 * 2900 * @param dev 2901 * Pointer to Ethernet device structure. 2902 * @param mac_addr 2903 * MAC address to register. 2904 * @param index 2905 * MAC address index. 2906 * 2907 * @return 2908 * 0 on success, a negative errno value otherwise 2909 */ 2910 int 2911 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2912 uint32_t index) 2913 { 2914 struct mlx5_priv *priv = dev->data->dev_private; 2915 const int vf = priv->config.vf; 2916 int ret = 0; 2917 2918 if (vf) 2919 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2920 mlx5_ifindex(dev), priv->mac_own, 2921 mac, index); 2922 return ret; 2923 } 2924 2925 /** 2926 * Modify a VF MAC address 2927 * 2928 * @param priv 2929 * Pointer to device private data. 2930 * @param mac_addr 2931 * MAC address to modify into. 2932 * @param iface_idx 2933 * Net device interface index 2934 * @param vf_index 2935 * VF index 2936 * 2937 * @return 2938 * 0 on success, a negative errno value otherwise 2939 */ 2940 int 2941 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2942 unsigned int iface_idx, 2943 struct rte_ether_addr *mac_addr, 2944 int vf_index) 2945 { 2946 return mlx5_nl_vf_mac_addr_modify 2947 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2948 } 2949 2950 /** 2951 * Set device promiscuous mode 2952 * 2953 * @param dev 2954 * Pointer to Ethernet device structure. 2955 * @param enable 2956 * 0 - promiscuous is disabled, otherwise - enabled 2957 * 2958 * @return 2959 * 0 on success, a negative error value otherwise 2960 */ 2961 int 2962 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2963 { 2964 struct mlx5_priv *priv = dev->data->dev_private; 2965 2966 return mlx5_nl_promisc(priv->nl_socket_route, 2967 mlx5_ifindex(dev), !!enable); 2968 } 2969 2970 /** 2971 * Set device promiscuous mode 2972 * 2973 * @param dev 2974 * Pointer to Ethernet device structure. 2975 * @param enable 2976 * 0 - all multicase is disabled, otherwise - enabled 2977 * 2978 * @return 2979 * 0 on success, a negative error value otherwise 2980 */ 2981 int 2982 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2983 { 2984 struct mlx5_priv *priv = dev->data->dev_private; 2985 2986 return mlx5_nl_allmulti(priv->nl_socket_route, 2987 mlx5_ifindex(dev), !!enable); 2988 } 2989 2990 /** 2991 * Flush device MAC addresses 2992 * 2993 * @param dev 2994 * Pointer to Ethernet device structure. 2995 * 2996 */ 2997 void 2998 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2999 { 3000 struct mlx5_priv *priv = dev->data->dev_private; 3001 3002 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 3003 dev->data->mac_addrs, 3004 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 3005 } 3006