1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /* rte flow indexed pool configuration. */ 71 static struct mlx5_indexed_pool_config icfg[] = { 72 { 73 .size = sizeof(struct rte_flow), 74 .trunk_size = 64, 75 .need_lock = 1, 76 .release_mem_en = 0, 77 .malloc = mlx5_malloc, 78 .free = mlx5_free, 79 .per_core_cache = 0, 80 .type = "ctl_flow_ipool", 81 }, 82 { 83 .size = sizeof(struct rte_flow), 84 .trunk_size = 64, 85 .grow_trunk = 3, 86 .grow_shift = 2, 87 .need_lock = 1, 88 .release_mem_en = 0, 89 .malloc = mlx5_malloc, 90 .free = mlx5_free, 91 .per_core_cache = 1 << 14, 92 .type = "rte_flow_ipool", 93 }, 94 { 95 .size = sizeof(struct rte_flow), 96 .trunk_size = 64, 97 .grow_trunk = 3, 98 .grow_shift = 2, 99 .need_lock = 1, 100 .release_mem_en = 0, 101 .malloc = mlx5_malloc, 102 .free = mlx5_free, 103 .per_core_cache = 0, 104 .type = "mcp_flow_ipool", 105 }, 106 }; 107 108 /** 109 * Set the completion channel file descriptor interrupt as non-blocking. 110 * 111 * @param[in] rxq_obj 112 * Pointer to RQ channel object, which includes the channel fd 113 * 114 * @param[out] fd 115 * The file descriptor (representing the interrupt) used in this channel. 116 * 117 * @return 118 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 119 */ 120 int 121 mlx5_os_set_nonblock_channel_fd(int fd) 122 { 123 int flags; 124 125 flags = fcntl(fd, F_GETFL); 126 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 127 } 128 129 /** 130 * Get mlx5 device attributes. The glue function query_device_ex() is called 131 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 132 * device attributes from the glue out parameter. 133 * 134 * @param cdev 135 * Pointer to mlx5 device. 136 * 137 * @param device_attr 138 * Pointer to mlx5 device attributes. 139 * 140 * @return 141 * 0 on success, a negative errno value otherwise and rte_errno is set. 142 */ 143 int 144 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, 145 struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_context *ctx = cdev->ctx; 149 struct ibv_device_attr_ex attr_ex; 150 151 memset(device_attr, 0, sizeof(*device_attr)); 152 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 153 if (err) { 154 rte_errno = errno; 155 return -rte_errno; 156 } 157 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 158 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 159 device_attr->max_sge = attr_ex.orig_attr.max_sge; 160 device_attr->max_cq = attr_ex.orig_attr.max_cq; 161 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 162 device_attr->max_mr = attr_ex.orig_attr.max_mr; 163 device_attr->max_pd = attr_ex.orig_attr.max_pd; 164 device_attr->max_qp = attr_ex.orig_attr.max_qp; 165 device_attr->max_srq = attr_ex.orig_attr.max_srq; 166 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 167 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 168 device_attr->max_rwq_indirection_table_size = 169 attr_ex.rss_caps.max_rwq_indirection_table_size; 170 device_attr->max_tso = attr_ex.tso_caps.max_tso; 171 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 172 173 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 174 #ifdef HAVE_IBV_MLX5_MOD_SWP 175 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 176 #endif 177 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 178 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 179 #endif 180 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 181 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 182 #endif 183 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 184 if (err) { 185 rte_errno = errno; 186 return -rte_errno; 187 } 188 189 device_attr->flags = dv_attr.flags; 190 device_attr->comp_mask = dv_attr.comp_mask; 191 #ifdef HAVE_IBV_MLX5_MOD_SWP 192 device_attr->sw_parsing_offloads = 193 dv_attr.sw_parsing_caps.sw_parsing_offloads; 194 #endif 195 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 196 device_attr->min_single_stride_log_num_of_bytes = 197 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 198 device_attr->max_single_stride_log_num_of_bytes = 199 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 200 device_attr->min_single_wqe_log_num_of_strides = 201 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 202 device_attr->max_single_wqe_log_num_of_strides = 203 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 204 device_attr->stride_supported_qpts = 205 dv_attr.striding_rq_caps.supported_qpts; 206 #endif 207 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 208 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 209 #endif 210 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 211 sizeof(device_attr->fw_ver)); 212 213 return 0; 214 } 215 216 /** 217 * Detect misc5 support or not 218 * 219 * @param[in] priv 220 * Device private data pointer 221 */ 222 #ifdef HAVE_MLX5DV_DR 223 static void 224 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 225 { 226 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 227 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 228 * Case: IPv4--->UDP--->VxLAN--->vni 229 */ 230 void *tbl; 231 struct mlx5_flow_dv_match_params matcher_mask; 232 void *match_m; 233 void *matcher; 234 void *headers_m; 235 void *misc5_m; 236 uint32_t *tunnel_header_m; 237 struct mlx5dv_flow_matcher_attr dv_attr; 238 239 memset(&matcher_mask, 0, sizeof(matcher_mask)); 240 matcher_mask.size = sizeof(matcher_mask.buf); 241 match_m = matcher_mask.buf; 242 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 243 misc5_m = MLX5_ADDR_OF(fte_match_param, 244 match_m, misc_parameters_5); 245 tunnel_header_m = (uint32_t *) 246 MLX5_ADDR_OF(fte_match_set_misc5, 247 misc5_m, tunnel_header_1); 248 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 249 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 250 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 251 *tunnel_header_m = 0xffffff; 252 253 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 254 if (!tbl) { 255 DRV_LOG(INFO, "No SW steering support"); 256 return; 257 } 258 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 259 dv_attr.match_mask = (void *)&matcher_mask, 260 dv_attr.match_criteria_enable = 261 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 262 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 263 dv_attr.priority = 3; 264 #ifdef HAVE_MLX5DV_DR_ESWITCH 265 void *misc2_m; 266 if (priv->config.dv_esw_en) { 267 /* FDB enabled reg_c_0 */ 268 dv_attr.match_criteria_enable |= 269 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 270 misc2_m = MLX5_ADDR_OF(fte_match_param, 271 match_m, misc_parameters_2); 272 MLX5_SET(fte_match_set_misc2, misc2_m, 273 metadata_reg_c_0, 0xffff); 274 } 275 #endif 276 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx, 277 &dv_attr, tbl); 278 if (matcher) { 279 priv->sh->misc5_cap = 1; 280 mlx5_glue->dv_destroy_flow_matcher(matcher); 281 } 282 mlx5_glue->dr_destroy_flow_tbl(tbl); 283 #else 284 RTE_SET_USED(priv); 285 #endif 286 } 287 #endif 288 289 /** 290 * Initialize DR related data within private structure. 291 * Routine checks the reference counter and does actual 292 * resources creation/initialization only if counter is zero. 293 * 294 * @param[in] priv 295 * Pointer to the private device data structure. 296 * 297 * @return 298 * Zero on success, positive error code otherwise. 299 */ 300 static int 301 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 302 { 303 struct mlx5_dev_ctx_shared *sh = priv->sh; 304 char s[MLX5_NAME_SIZE] __rte_unused; 305 int err; 306 307 MLX5_ASSERT(sh && sh->refcnt); 308 if (sh->refcnt > 1) 309 return 0; 310 err = mlx5_alloc_table_hash_list(priv); 311 if (err) 312 goto error; 313 /* The resources below are only valid with DV support. */ 314 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 315 /* Init port id action list. */ 316 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 317 sh->port_id_action_list = mlx5_list_create(s, sh, true, 318 flow_dv_port_id_create_cb, 319 flow_dv_port_id_match_cb, 320 flow_dv_port_id_remove_cb, 321 flow_dv_port_id_clone_cb, 322 flow_dv_port_id_clone_free_cb); 323 if (!sh->port_id_action_list) 324 goto error; 325 /* Init push vlan action list. */ 326 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 327 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 328 flow_dv_push_vlan_create_cb, 329 flow_dv_push_vlan_match_cb, 330 flow_dv_push_vlan_remove_cb, 331 flow_dv_push_vlan_clone_cb, 332 flow_dv_push_vlan_clone_free_cb); 333 if (!sh->push_vlan_action_list) 334 goto error; 335 /* Init sample action list. */ 336 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 337 sh->sample_action_list = mlx5_list_create(s, sh, true, 338 flow_dv_sample_create_cb, 339 flow_dv_sample_match_cb, 340 flow_dv_sample_remove_cb, 341 flow_dv_sample_clone_cb, 342 flow_dv_sample_clone_free_cb); 343 if (!sh->sample_action_list) 344 goto error; 345 /* Init dest array action list. */ 346 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 347 sh->dest_array_list = mlx5_list_create(s, sh, true, 348 flow_dv_dest_array_create_cb, 349 flow_dv_dest_array_match_cb, 350 flow_dv_dest_array_remove_cb, 351 flow_dv_dest_array_clone_cb, 352 flow_dv_dest_array_clone_free_cb); 353 if (!sh->dest_array_list) 354 goto error; 355 /* Init shared flex parsers list, no need lcore_share */ 356 snprintf(s, sizeof(s), "%s_flex_parsers_list", sh->ibdev_name); 357 sh->flex_parsers_dv = mlx5_list_create(s, sh, false, 358 mlx5_flex_parser_create_cb, 359 mlx5_flex_parser_match_cb, 360 mlx5_flex_parser_remove_cb, 361 mlx5_flex_parser_clone_cb, 362 mlx5_flex_parser_clone_free_cb); 363 if (!sh->flex_parsers_dv) 364 goto error; 365 #endif 366 #ifdef HAVE_MLX5DV_DR 367 void *domain; 368 369 /* Reference counter is zero, we should initialize structures. */ 370 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 371 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 372 if (!domain) { 373 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 374 err = errno; 375 goto error; 376 } 377 sh->rx_domain = domain; 378 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 379 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 380 if (!domain) { 381 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 382 err = errno; 383 goto error; 384 } 385 sh->tx_domain = domain; 386 #ifdef HAVE_MLX5DV_DR_ESWITCH 387 if (priv->config.dv_esw_en) { 388 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 389 MLX5DV_DR_DOMAIN_TYPE_FDB); 390 if (!domain) { 391 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 392 err = errno; 393 goto error; 394 } 395 sh->fdb_domain = domain; 396 } 397 /* 398 * The drop action is just some dummy placeholder in rdma-core. It 399 * does not belong to domains and has no any attributes, and, can be 400 * shared by the entire device. 401 */ 402 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 403 if (!sh->dr_drop_action) { 404 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 405 err = errno; 406 goto error; 407 } 408 #endif 409 if (!sh->tunnel_hub && priv->config.dv_miss_info) 410 err = mlx5_alloc_tunnel_hub(sh); 411 if (err) { 412 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 413 goto error; 414 } 415 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 416 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 417 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 418 if (sh->fdb_domain) 419 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 420 } 421 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 422 if (!priv->config.allow_duplicate_pattern) { 423 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 424 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 425 #endif 426 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 427 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 428 if (sh->fdb_domain) 429 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 430 } 431 432 __mlx5_discovery_misc5_cap(priv); 433 #endif /* HAVE_MLX5DV_DR */ 434 sh->default_miss_action = 435 mlx5_glue->dr_create_flow_action_default_miss(); 436 if (!sh->default_miss_action) 437 DRV_LOG(WARNING, "Default miss action is not supported."); 438 LIST_INIT(&sh->shared_rxqs); 439 return 0; 440 error: 441 /* Rollback the created objects. */ 442 if (sh->rx_domain) { 443 mlx5_glue->dr_destroy_domain(sh->rx_domain); 444 sh->rx_domain = NULL; 445 } 446 if (sh->tx_domain) { 447 mlx5_glue->dr_destroy_domain(sh->tx_domain); 448 sh->tx_domain = NULL; 449 } 450 if (sh->fdb_domain) { 451 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 452 sh->fdb_domain = NULL; 453 } 454 if (sh->dr_drop_action) { 455 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 456 sh->dr_drop_action = NULL; 457 } 458 if (sh->pop_vlan_action) { 459 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 460 sh->pop_vlan_action = NULL; 461 } 462 if (sh->encaps_decaps) { 463 mlx5_hlist_destroy(sh->encaps_decaps); 464 sh->encaps_decaps = NULL; 465 } 466 if (sh->modify_cmds) { 467 mlx5_hlist_destroy(sh->modify_cmds); 468 sh->modify_cmds = NULL; 469 } 470 if (sh->tag_table) { 471 /* tags should be destroyed with flow before. */ 472 mlx5_hlist_destroy(sh->tag_table); 473 sh->tag_table = NULL; 474 } 475 if (sh->tunnel_hub) { 476 mlx5_release_tunnel_hub(sh, priv->dev_port); 477 sh->tunnel_hub = NULL; 478 } 479 mlx5_free_table_hash_list(priv); 480 if (sh->port_id_action_list) { 481 mlx5_list_destroy(sh->port_id_action_list); 482 sh->port_id_action_list = NULL; 483 } 484 if (sh->push_vlan_action_list) { 485 mlx5_list_destroy(sh->push_vlan_action_list); 486 sh->push_vlan_action_list = NULL; 487 } 488 if (sh->sample_action_list) { 489 mlx5_list_destroy(sh->sample_action_list); 490 sh->sample_action_list = NULL; 491 } 492 if (sh->dest_array_list) { 493 mlx5_list_destroy(sh->dest_array_list); 494 sh->dest_array_list = NULL; 495 } 496 return err; 497 } 498 499 /** 500 * Destroy DR related data within private structure. 501 * 502 * @param[in] priv 503 * Pointer to the private device data structure. 504 */ 505 void 506 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 507 { 508 struct mlx5_dev_ctx_shared *sh = priv->sh; 509 510 MLX5_ASSERT(sh && sh->refcnt); 511 if (sh->refcnt > 1) 512 return; 513 MLX5_ASSERT(LIST_EMPTY(&sh->shared_rxqs)); 514 #ifdef HAVE_MLX5DV_DR 515 if (sh->rx_domain) { 516 mlx5_glue->dr_destroy_domain(sh->rx_domain); 517 sh->rx_domain = NULL; 518 } 519 if (sh->tx_domain) { 520 mlx5_glue->dr_destroy_domain(sh->tx_domain); 521 sh->tx_domain = NULL; 522 } 523 #ifdef HAVE_MLX5DV_DR_ESWITCH 524 if (sh->fdb_domain) { 525 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 526 sh->fdb_domain = NULL; 527 } 528 if (sh->dr_drop_action) { 529 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 530 sh->dr_drop_action = NULL; 531 } 532 #endif 533 if (sh->pop_vlan_action) { 534 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 535 sh->pop_vlan_action = NULL; 536 } 537 #endif /* HAVE_MLX5DV_DR */ 538 if (sh->default_miss_action) 539 mlx5_glue->destroy_flow_action 540 (sh->default_miss_action); 541 if (sh->encaps_decaps) { 542 mlx5_hlist_destroy(sh->encaps_decaps); 543 sh->encaps_decaps = NULL; 544 } 545 if (sh->modify_cmds) { 546 mlx5_hlist_destroy(sh->modify_cmds); 547 sh->modify_cmds = NULL; 548 } 549 if (sh->tag_table) { 550 /* tags should be destroyed with flow before. */ 551 mlx5_hlist_destroy(sh->tag_table); 552 sh->tag_table = NULL; 553 } 554 if (sh->tunnel_hub) { 555 mlx5_release_tunnel_hub(sh, priv->dev_port); 556 sh->tunnel_hub = NULL; 557 } 558 mlx5_free_table_hash_list(priv); 559 if (sh->port_id_action_list) { 560 mlx5_list_destroy(sh->port_id_action_list); 561 sh->port_id_action_list = NULL; 562 } 563 if (sh->push_vlan_action_list) { 564 mlx5_list_destroy(sh->push_vlan_action_list); 565 sh->push_vlan_action_list = NULL; 566 } 567 if (sh->sample_action_list) { 568 mlx5_list_destroy(sh->sample_action_list); 569 sh->sample_action_list = NULL; 570 } 571 if (sh->dest_array_list) { 572 mlx5_list_destroy(sh->dest_array_list); 573 sh->dest_array_list = NULL; 574 } 575 } 576 577 /** 578 * Initialize shared data between primary and secondary process. 579 * 580 * A memzone is reserved by primary process and secondary processes attach to 581 * the memzone. 582 * 583 * @return 584 * 0 on success, a negative errno value otherwise and rte_errno is set. 585 */ 586 static int 587 mlx5_init_shared_data(void) 588 { 589 const struct rte_memzone *mz; 590 int ret = 0; 591 592 rte_spinlock_lock(&mlx5_shared_data_lock); 593 if (mlx5_shared_data == NULL) { 594 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 595 /* Allocate shared memory. */ 596 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 597 sizeof(*mlx5_shared_data), 598 SOCKET_ID_ANY, 0); 599 if (mz == NULL) { 600 DRV_LOG(ERR, 601 "Cannot allocate mlx5 shared data"); 602 ret = -rte_errno; 603 goto error; 604 } 605 mlx5_shared_data = mz->addr; 606 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 607 rte_spinlock_init(&mlx5_shared_data->lock); 608 } else { 609 /* Lookup allocated shared memory. */ 610 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 611 if (mz == NULL) { 612 DRV_LOG(ERR, 613 "Cannot attach mlx5 shared data"); 614 ret = -rte_errno; 615 goto error; 616 } 617 mlx5_shared_data = mz->addr; 618 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 619 } 620 } 621 error: 622 rte_spinlock_unlock(&mlx5_shared_data_lock); 623 return ret; 624 } 625 626 /** 627 * PMD global initialization. 628 * 629 * Independent from individual device, this function initializes global 630 * per-PMD data structures distinguishing primary and secondary processes. 631 * Hence, each initialization is called once per a process. 632 * 633 * @return 634 * 0 on success, a negative errno value otherwise and rte_errno is set. 635 */ 636 static int 637 mlx5_init_once(void) 638 { 639 struct mlx5_shared_data *sd; 640 struct mlx5_local_data *ld = &mlx5_local_data; 641 int ret = 0; 642 643 if (mlx5_init_shared_data()) 644 return -rte_errno; 645 sd = mlx5_shared_data; 646 MLX5_ASSERT(sd); 647 rte_spinlock_lock(&sd->lock); 648 switch (rte_eal_process_type()) { 649 case RTE_PROC_PRIMARY: 650 if (sd->init_done) 651 break; 652 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 653 mlx5_mp_os_primary_handle); 654 if (ret) 655 goto out; 656 sd->init_done = true; 657 break; 658 case RTE_PROC_SECONDARY: 659 if (ld->init_done) 660 break; 661 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 662 mlx5_mp_os_secondary_handle); 663 if (ret) 664 goto out; 665 ++sd->secondary_cnt; 666 ld->init_done = true; 667 break; 668 default: 669 break; 670 } 671 out: 672 rte_spinlock_unlock(&sd->lock); 673 return ret; 674 } 675 676 /** 677 * DV flow counter mode detect and config. 678 * 679 * @param dev 680 * Pointer to rte_eth_dev structure. 681 * 682 */ 683 static void 684 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 685 { 686 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 687 struct mlx5_priv *priv = dev->data->dev_private; 688 struct mlx5_dev_ctx_shared *sh = priv->sh; 689 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 690 bool fallback; 691 692 #ifndef HAVE_IBV_DEVX_ASYNC 693 fallback = true; 694 #else 695 fallback = false; 696 if (!sh->cdev->config.devx || !priv->config.dv_flow_en || 697 !hca_attr->flow_counters_dump || 698 !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) || 699 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 700 fallback = true; 701 #endif 702 if (fallback) 703 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 704 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 705 hca_attr->flow_counters_dump, 706 hca_attr->flow_counter_bulk_alloc_bitmap); 707 /* Initialize fallback mode only on the port initializes sh. */ 708 if (sh->refcnt == 1) 709 sh->cmng.counter_fallback = fallback; 710 else if (fallback != sh->cmng.counter_fallback) 711 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 712 "with others:%d.", PORT_ID(priv), fallback); 713 #endif 714 } 715 716 /** 717 * DR flow drop action support detect. 718 * 719 * @param dev 720 * Pointer to rte_eth_dev structure. 721 * 722 */ 723 static void 724 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 725 { 726 #ifdef HAVE_MLX5DV_DR 727 struct mlx5_priv *priv = dev->data->dev_private; 728 729 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action) 730 return; 731 /** 732 * DR supports drop action placeholder when it is supported; 733 * otherwise, use the queue drop action. 734 */ 735 if (!priv->sh->drop_action_check_flag) { 736 if (!mlx5_flow_discover_dr_action_support(dev)) 737 priv->sh->dr_drop_action_en = 1; 738 priv->sh->drop_action_check_flag = 1; 739 } 740 if (priv->sh->dr_drop_action_en) 741 priv->root_drop_action = priv->sh->dr_drop_action; 742 else 743 priv->root_drop_action = priv->drop_queue.hrxq->action; 744 #endif 745 } 746 747 static void 748 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 749 { 750 struct mlx5_priv *priv = dev->data->dev_private; 751 void *ctx = priv->sh->cdev->ctx; 752 753 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 754 if (!priv->q_counters) { 755 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 756 struct ibv_wq *wq; 757 758 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 759 "by DevX - fall-back to use the kernel driver global " 760 "queue counter.", dev->data->port_id); 761 /* Create WQ by kernel and query its queue counter ID. */ 762 if (cq) { 763 wq = mlx5_glue->create_wq(ctx, 764 &(struct ibv_wq_init_attr){ 765 .wq_type = IBV_WQT_RQ, 766 .max_wr = 1, 767 .max_sge = 1, 768 .pd = priv->sh->cdev->pd, 769 .cq = cq, 770 }); 771 if (wq) { 772 /* Counter is assigned only on RDY state. */ 773 int ret = mlx5_glue->modify_wq(wq, 774 &(struct ibv_wq_attr){ 775 .attr_mask = IBV_WQ_ATTR_STATE, 776 .wq_state = IBV_WQS_RDY, 777 }); 778 779 if (ret == 0) 780 mlx5_devx_cmd_wq_query(wq, 781 &priv->counter_set_id); 782 claim_zero(mlx5_glue->destroy_wq(wq)); 783 } 784 claim_zero(mlx5_glue->destroy_cq(cq)); 785 } 786 } else { 787 priv->counter_set_id = priv->q_counters->id; 788 } 789 if (priv->counter_set_id == 0) 790 DRV_LOG(INFO, "Part of the port %d statistics will not be " 791 "available.", dev->data->port_id); 792 } 793 794 /** 795 * Check if representor spawn info match devargs. 796 * 797 * @param spawn 798 * Verbs device parameters (name, port, switch_info) to spawn. 799 * @param eth_da 800 * Device devargs to probe. 801 * 802 * @return 803 * Match result. 804 */ 805 static bool 806 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 807 struct rte_eth_devargs *eth_da) 808 { 809 struct mlx5_switch_info *switch_info = &spawn->info; 810 unsigned int p, f; 811 uint16_t id; 812 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 813 eth_da->type); 814 815 switch (eth_da->type) { 816 case RTE_ETH_REPRESENTOR_SF: 817 if (!(spawn->info.port_name == -1 && 818 switch_info->name_type == 819 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 820 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 821 rte_errno = EBUSY; 822 return false; 823 } 824 break; 825 case RTE_ETH_REPRESENTOR_VF: 826 /* Allows HPF representor index -1 as exception. */ 827 if (!(spawn->info.port_name == -1 && 828 switch_info->name_type == 829 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 830 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 831 rte_errno = EBUSY; 832 return false; 833 } 834 break; 835 case RTE_ETH_REPRESENTOR_NONE: 836 rte_errno = EBUSY; 837 return false; 838 default: 839 rte_errno = ENOTSUP; 840 DRV_LOG(ERR, "unsupported representor type"); 841 return false; 842 } 843 /* Check representor ID: */ 844 for (p = 0; p < eth_da->nb_ports; ++p) { 845 if (spawn->pf_bond < 0) { 846 /* For non-LAG mode, allow and ignore pf. */ 847 switch_info->pf_num = eth_da->ports[p]; 848 repr_id = mlx5_representor_id_encode(switch_info, 849 eth_da->type); 850 } 851 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 852 id = MLX5_REPRESENTOR_ID 853 (eth_da->ports[p], eth_da->type, 854 eth_da->representor_ports[f]); 855 if (repr_id == id) 856 return true; 857 } 858 } 859 rte_errno = EBUSY; 860 return false; 861 } 862 863 /** 864 * Spawn an Ethernet device from Verbs information. 865 * 866 * @param dpdk_dev 867 * Backing DPDK device. 868 * @param spawn 869 * Verbs device parameters (name, port, switch_info) to spawn. 870 * @param config 871 * Device configuration parameters. 872 * @param eth_da 873 * Device arguments. 874 * 875 * @return 876 * A valid Ethernet device object on success, NULL otherwise and rte_errno 877 * is set. The following errors are defined: 878 * 879 * EBUSY: device is not supposed to be spawned. 880 * EEXIST: device is already spawned 881 */ 882 static struct rte_eth_dev * 883 mlx5_dev_spawn(struct rte_device *dpdk_dev, 884 struct mlx5_dev_spawn_data *spawn, 885 struct mlx5_dev_config *config, 886 struct rte_eth_devargs *eth_da) 887 { 888 const struct mlx5_switch_info *switch_info = &spawn->info; 889 struct mlx5_dev_ctx_shared *sh = NULL; 890 struct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr; 891 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; 892 struct rte_eth_dev *eth_dev = NULL; 893 struct mlx5_priv *priv = NULL; 894 int err = 0; 895 unsigned int hw_padding = 0; 896 unsigned int mps; 897 unsigned int mpls_en = 0; 898 unsigned int swp = 0; 899 unsigned int mprq = 0; 900 struct rte_ether_addr mac; 901 char name[RTE_ETH_NAME_MAX_LEN]; 902 int own_domain_id = 0; 903 uint16_t port_id; 904 struct mlx5_port_info vport_info = { .query_flags = 0 }; 905 int nl_rdma = -1; 906 int i; 907 908 /* Determine if this port representor is supposed to be spawned. */ 909 if (switch_info->representor && dpdk_dev->devargs && 910 !mlx5_representor_match(spawn, eth_da)) 911 return NULL; 912 /* Build device name. */ 913 if (spawn->pf_bond < 0) { 914 /* Single device. */ 915 if (!switch_info->representor) 916 strlcpy(name, dpdk_dev->name, sizeof(name)); 917 else 918 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 919 dpdk_dev->name, 920 switch_info->name_type == 921 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 922 switch_info->port_name); 923 } else { 924 /* Bonding device. */ 925 if (!switch_info->representor) { 926 err = snprintf(name, sizeof(name), "%s_%s", 927 dpdk_dev->name, spawn->phys_dev_name); 928 } else { 929 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 930 dpdk_dev->name, spawn->phys_dev_name, 931 switch_info->ctrl_num, 932 switch_info->pf_num, 933 switch_info->name_type == 934 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 935 switch_info->port_name); 936 } 937 } 938 if (err >= (int)sizeof(name)) 939 DRV_LOG(WARNING, "device name overflow %s", name); 940 /* check if the device is already spawned */ 941 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 942 rte_errno = EEXIST; 943 return NULL; 944 } 945 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 946 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 947 struct mlx5_mp_id mp_id; 948 949 eth_dev = rte_eth_dev_attach_secondary(name); 950 if (eth_dev == NULL) { 951 DRV_LOG(ERR, "can not attach rte ethdev"); 952 rte_errno = ENOMEM; 953 return NULL; 954 } 955 eth_dev->device = dpdk_dev; 956 eth_dev->dev_ops = &mlx5_dev_sec_ops; 957 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 958 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 959 err = mlx5_proc_priv_init(eth_dev); 960 if (err) 961 return NULL; 962 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 963 /* Receive command fd from primary process */ 964 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 965 if (err < 0) 966 goto err_secondary; 967 /* Remap UAR for Tx queues. */ 968 err = mlx5_tx_uar_init_secondary(eth_dev, err); 969 if (err) 970 goto err_secondary; 971 /* 972 * Ethdev pointer is still required as input since 973 * the primary device is not accessible from the 974 * secondary process. 975 */ 976 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 977 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 978 return eth_dev; 979 err_secondary: 980 mlx5_dev_close(eth_dev); 981 return NULL; 982 } 983 /* Process parameters. */ 984 err = mlx5_args(config, dpdk_dev->devargs); 985 if (err) { 986 DRV_LOG(ERR, "failed to process device arguments: %s", 987 strerror(rte_errno)); 988 return NULL; 989 } 990 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 991 if (!sh) 992 return NULL; 993 /* Update final values for devargs before check sibling config. */ 994 if (config->dv_miss_info) { 995 if (switch_info->master || switch_info->representor) 996 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 997 } 998 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 999 if (config->dv_flow_en) { 1000 DRV_LOG(WARNING, "DV flow is not supported."); 1001 config->dv_flow_en = 0; 1002 } 1003 #endif 1004 #ifdef HAVE_MLX5DV_DR_ESWITCH 1005 if (!(hca_attr->eswitch_manager && config->dv_flow_en && 1006 (switch_info->representor || switch_info->master))) 1007 config->dv_esw_en = 0; 1008 #else 1009 config->dv_esw_en = 0; 1010 #endif 1011 if (!config->dv_esw_en && 1012 config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1013 DRV_LOG(WARNING, 1014 "Metadata mode %u is not supported (no E-Switch).", 1015 config->dv_xmeta_en); 1016 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1017 } 1018 /* Check sibling device configurations. */ 1019 err = mlx5_dev_check_sibling_config(sh, config, dpdk_dev); 1020 if (err) 1021 goto error; 1022 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 1023 config->dest_tir = 1; 1024 #endif 1025 /* 1026 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1027 * as all ConnectX-5 devices. 1028 */ 1029 if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1030 if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1031 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1032 mps = MLX5_MPW_ENHANCED; 1033 } else { 1034 DRV_LOG(DEBUG, "MPW is supported"); 1035 mps = MLX5_MPW; 1036 } 1037 } else { 1038 DRV_LOG(DEBUG, "MPW isn't supported"); 1039 mps = MLX5_MPW_DISABLED; 1040 } 1041 #ifdef HAVE_IBV_MLX5_MOD_SWP 1042 if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1043 swp = sh->device_attr.sw_parsing_offloads; 1044 DRV_LOG(DEBUG, "SWP support: %u", swp); 1045 #endif 1046 config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP | 1047 MLX5_SW_PARSING_TSO_CAP); 1048 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1049 if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1050 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1051 sh->device_attr.min_single_stride_log_num_of_bytes); 1052 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1053 sh->device_attr.max_single_stride_log_num_of_bytes); 1054 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1055 sh->device_attr.min_single_wqe_log_num_of_strides); 1056 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1057 sh->device_attr.max_single_wqe_log_num_of_strides); 1058 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1059 sh->device_attr.stride_supported_qpts); 1060 DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %d", 1061 config->mprq.log_min_stride_wqe_size); 1062 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1063 mprq = 1; 1064 config->mprq.log_min_stride_size = 1065 sh->device_attr.min_single_stride_log_num_of_bytes; 1066 config->mprq.log_max_stride_size = 1067 sh->device_attr.max_single_stride_log_num_of_bytes; 1068 config->mprq.log_min_stride_num = 1069 sh->device_attr.min_single_wqe_log_num_of_strides; 1070 config->mprq.log_max_stride_num = 1071 sh->device_attr.max_single_wqe_log_num_of_strides; 1072 } 1073 #endif 1074 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1075 if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1076 config->tunnel_en = sh->device_attr.tunnel_offloads_caps & 1077 (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN | 1078 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE | 1079 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE); 1080 } 1081 if (config->tunnel_en) { 1082 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s", 1083 config->tunnel_en & 1084 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "", 1085 config->tunnel_en & 1086 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "", 1087 config->tunnel_en & 1088 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : "" 1089 ); 1090 } else { 1091 DRV_LOG(DEBUG, "tunnel offloading is not supported"); 1092 } 1093 #else 1094 DRV_LOG(WARNING, 1095 "tunnel offloading disabled due to old OFED/rdma-core version"); 1096 #endif 1097 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1098 mpls_en = ((sh->device_attr.tunnel_offloads_caps & 1099 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1100 (sh->device_attr.tunnel_offloads_caps & 1101 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1102 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1103 mpls_en ? "" : "not "); 1104 #else 1105 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1106 " old OFED/rdma-core version or firmware configuration"); 1107 #endif 1108 config->mpls_en = mpls_en; 1109 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1110 /* Check port status. */ 1111 if (spawn->phys_port <= UINT8_MAX) { 1112 /* Legacy Verbs api only support u8 port number. */ 1113 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port, 1114 &port_attr); 1115 if (err) { 1116 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1117 goto error; 1118 } 1119 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1120 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1121 err = EINVAL; 1122 goto error; 1123 } 1124 } else if (nl_rdma >= 0) { 1125 /* IB doesn't allow more than 255 ports, must be Ethernet. */ 1126 err = mlx5_nl_port_state(nl_rdma, 1127 spawn->phys_dev_name, 1128 spawn->phys_port); 1129 if (err < 0) { 1130 DRV_LOG(INFO, "Failed to get netlink port state: %s", 1131 strerror(rte_errno)); 1132 err = -rte_errno; 1133 goto error; 1134 } 1135 port_attr.state = (enum ibv_port_state)err; 1136 } 1137 if (port_attr.state != IBV_PORT_ACTIVE) 1138 DRV_LOG(INFO, "port is not active: \"%s\" (%d)", 1139 mlx5_glue->port_state_str(port_attr.state), 1140 port_attr.state); 1141 /* Allocate private eth device data. */ 1142 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1143 sizeof(*priv), 1144 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1145 if (priv == NULL) { 1146 DRV_LOG(ERR, "priv allocation failure"); 1147 err = ENOMEM; 1148 goto error; 1149 } 1150 priv->sh = sh; 1151 priv->dev_port = spawn->phys_port; 1152 priv->pci_dev = spawn->pci_dev; 1153 priv->mtu = RTE_ETHER_MTU; 1154 /* Some internal functions rely on Netlink sockets, open them now. */ 1155 priv->nl_socket_rdma = nl_rdma; 1156 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1157 priv->representor = !!switch_info->representor; 1158 priv->master = !!switch_info->master; 1159 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1160 priv->vport_meta_tag = 0; 1161 priv->vport_meta_mask = 0; 1162 priv->pf_bond = spawn->pf_bond; 1163 1164 DRV_LOG(DEBUG, 1165 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1166 priv->dev_port, dpdk_dev->bus->name, 1167 priv->pci_dev ? priv->pci_dev->name : "NONE", 1168 priv->master, priv->representor, priv->pf_bond); 1169 1170 /* 1171 * If we have E-Switch we should determine the vport attributes. 1172 * E-Switch may use either source vport field or reg_c[0] metadata 1173 * register to match on vport index. The engaged part of metadata 1174 * register is defined by mask. 1175 */ 1176 if (switch_info->representor || switch_info->master) { 1177 err = mlx5_glue->devx_port_query(sh->cdev->ctx, 1178 spawn->phys_port, 1179 &vport_info); 1180 if (err) { 1181 DRV_LOG(WARNING, 1182 "Cannot query devx port %d on device %s", 1183 spawn->phys_port, spawn->phys_dev_name); 1184 vport_info.query_flags = 0; 1185 } 1186 } 1187 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1188 priv->vport_meta_tag = vport_info.vport_meta_tag; 1189 priv->vport_meta_mask = vport_info.vport_meta_mask; 1190 if (!priv->vport_meta_mask) { 1191 DRV_LOG(ERR, 1192 "vport zero mask for port %d on bonding device %s", 1193 spawn->phys_port, spawn->phys_dev_name); 1194 err = ENOTSUP; 1195 goto error; 1196 } 1197 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1198 DRV_LOG(ERR, 1199 "Invalid vport tag for port %d on bonding device %s", 1200 spawn->phys_port, spawn->phys_dev_name); 1201 err = ENOTSUP; 1202 goto error; 1203 } 1204 } 1205 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1206 priv->vport_id = vport_info.vport_id; 1207 } else if (spawn->pf_bond >= 0 && 1208 (switch_info->representor || switch_info->master)) { 1209 DRV_LOG(ERR, 1210 "Cannot deduce vport index for port %d on bonding device %s", 1211 spawn->phys_port, spawn->phys_dev_name); 1212 err = ENOTSUP; 1213 goto error; 1214 } else { 1215 /* 1216 * Suppose vport index in compatible way. Kernel/rdma_core 1217 * support single E-Switch per PF configurations only and 1218 * vport_id field contains the vport index for associated VF, 1219 * which is deduced from representor port name. 1220 * For example, let's have the IB device port 10, it has 1221 * attached network device eth0, which has port name attribute 1222 * pf0vf2, we can deduce the VF number as 2, and set vport index 1223 * as 3 (2+1). This assigning schema should be changed if the 1224 * multiple E-Switch instances per PF configurations or/and PCI 1225 * subfunctions are added. 1226 */ 1227 priv->vport_id = switch_info->representor ? 1228 switch_info->port_name + 1 : -1; 1229 } 1230 priv->representor_id = mlx5_representor_id_encode(switch_info, 1231 eth_da->type); 1232 /* 1233 * Look for sibling devices in order to reuse their switch domain 1234 * if any, otherwise allocate one. 1235 */ 1236 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1237 const struct mlx5_priv *opriv = 1238 rte_eth_devices[port_id].data->dev_private; 1239 1240 if (!opriv || 1241 opriv->sh != priv->sh || 1242 opriv->domain_id == 1243 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1244 continue; 1245 priv->domain_id = opriv->domain_id; 1246 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1247 priv->dev_port, priv->domain_id); 1248 break; 1249 } 1250 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1251 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1252 if (err) { 1253 err = rte_errno; 1254 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1255 strerror(rte_errno)); 1256 goto error; 1257 } 1258 own_domain_id = 1; 1259 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1260 priv->dev_port, priv->domain_id); 1261 } 1262 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1263 IBV_DEVICE_RAW_IP_CSUM); 1264 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1265 (config->hw_csum ? "" : "not ")); 1266 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1267 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1268 DRV_LOG(DEBUG, "counters are not supported"); 1269 #endif 1270 config->ind_table_max_size = 1271 sh->device_attr.max_rwq_indirection_table_size; 1272 /* 1273 * Remove this check once DPDK supports larger/variable 1274 * indirection tables. 1275 */ 1276 if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512) 1277 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512; 1278 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1279 config->ind_table_max_size); 1280 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1281 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1282 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1283 (config->hw_vlan_strip ? "" : "not ")); 1284 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1285 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1286 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1287 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1288 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1289 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1290 IBV_DEVICE_PCI_WRITE_END_PADDING); 1291 #endif 1292 if (config->hw_padding && !hw_padding) { 1293 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1294 config->hw_padding = 0; 1295 } else if (config->hw_padding) { 1296 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1297 } 1298 config->tso = (sh->device_attr.max_tso > 0 && 1299 (sh->device_attr.tso_supported_qpts & 1300 (1 << IBV_QPT_RAW_PACKET))); 1301 if (config->tso) 1302 config->tso_max_payload_sz = sh->device_attr.max_tso; 1303 /* 1304 * MPW is disabled by default, while the Enhanced MPW is enabled 1305 * by default. 1306 */ 1307 if (config->mps == MLX5_ARG_UNSET) 1308 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1309 MLX5_MPW_DISABLED; 1310 else 1311 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1312 DRV_LOG(INFO, "%sMPS is %s", 1313 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1314 config->mps == MLX5_MPW ? "legacy " : "", 1315 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1316 if (sh->cdev->config.devx) { 1317 sh->steering_format_version = hca_attr->steering_format_version; 1318 /* Check for LRO support. */ 1319 if (config->dest_tir && hca_attr->lro_cap && 1320 config->dv_flow_en) { 1321 /* TBD check tunnel lro caps. */ 1322 config->lro.supported = hca_attr->lro_cap; 1323 DRV_LOG(DEBUG, "Device supports LRO"); 1324 /* 1325 * If LRO timeout is not configured by application, 1326 * use the minimal supported value. 1327 */ 1328 if (!config->lro.timeout) 1329 config->lro.timeout = 1330 hca_attr->lro_timer_supported_periods[0]; 1331 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1332 config->lro.timeout); 1333 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1334 "required for coalescing is %d bytes", 1335 hca_attr->lro_min_mss_size); 1336 } 1337 #if defined(HAVE_MLX5DV_DR) && \ 1338 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1339 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1340 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_old && 1341 config->dv_flow_en) { 1342 uint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids; 1343 /* 1344 * Meter needs two REG_C's for color match and pre-sfx 1345 * flow match. Here get the REG_C for color match. 1346 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1347 */ 1348 reg_c_mask &= 0xfc; 1349 if (__builtin_popcount(reg_c_mask) < 1) { 1350 priv->mtr_en = 0; 1351 DRV_LOG(WARNING, "No available register for" 1352 " meter."); 1353 } else { 1354 /* 1355 * The meter color register is used by the 1356 * flow-hit feature as well. 1357 * The flow-hit feature must use REG_C_3 1358 * Prefer REG_C_3 if it is available. 1359 */ 1360 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1361 priv->mtr_color_reg = REG_C_3; 1362 else 1363 priv->mtr_color_reg = ffs(reg_c_mask) 1364 - 1 + REG_C_0; 1365 priv->mtr_en = 1; 1366 priv->mtr_reg_share = hca_attr->qos.flow_meter; 1367 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1368 priv->mtr_color_reg); 1369 } 1370 } 1371 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) { 1372 uint32_t log_obj_size = 1373 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1374 if (log_obj_size >= 1375 hca_attr->qos.log_meter_aso_granularity && 1376 log_obj_size <= 1377 hca_attr->qos.log_meter_aso_max_alloc) 1378 sh->meter_aso_en = 1; 1379 } 1380 if (priv->mtr_en) { 1381 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1382 if (err) { 1383 err = -err; 1384 goto error; 1385 } 1386 } 1387 if (hca_attr->flow.tunnel_header_0_1) 1388 sh->tunnel_header_0_1 = 1; 1389 #endif 1390 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1391 if (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) { 1392 sh->flow_hit_aso_en = 1; 1393 err = mlx5_flow_aso_age_mng_init(sh); 1394 if (err) { 1395 err = -err; 1396 goto error; 1397 } 1398 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1399 } 1400 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1401 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1402 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1403 if (hca_attr->ct_offload && priv->mtr_color_reg == REG_C_3) { 1404 err = mlx5_flow_aso_ct_mng_init(sh); 1405 if (err) { 1406 err = -err; 1407 goto error; 1408 } 1409 DRV_LOG(DEBUG, "CT ASO is supported."); 1410 sh->ct_aso_en = 1; 1411 } 1412 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1413 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1414 if (hca_attr->log_max_ft_sampler_num > 0 && 1415 config->dv_flow_en) { 1416 priv->sampler_en = 1; 1417 DRV_LOG(DEBUG, "Sampler enabled!"); 1418 } else { 1419 priv->sampler_en = 0; 1420 if (!hca_attr->log_max_ft_sampler_num) 1421 DRV_LOG(WARNING, 1422 "No available register for sampler."); 1423 else 1424 DRV_LOG(DEBUG, "DV flow is not supported!"); 1425 } 1426 #endif 1427 } 1428 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1429 !(sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1430 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1431 config->cqe_comp = 0; 1432 } 1433 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1434 (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_flow_tag)) { 1435 DRV_LOG(WARNING, "Flow Tag CQE compression" 1436 " format isn't supported."); 1437 config->cqe_comp = 0; 1438 } 1439 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1440 (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { 1441 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1442 " format isn't supported."); 1443 config->cqe_comp = 0; 1444 } 1445 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1446 config->cqe_comp ? "" : "not "); 1447 if (config->tx_pp) { 1448 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1449 hca_attr->dev_freq_khz); 1450 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1451 hca_attr->qos.packet_pacing ? "" : "not "); 1452 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1453 hca_attr->cross_channel ? "" : "not "); 1454 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1455 hca_attr->wqe_index_ignore ? "" : "not "); 1456 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1457 hca_attr->non_wire_sq ? "" : "not "); 1458 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1459 hca_attr->log_max_static_sq_wq ? "" : "not ", 1460 hca_attr->log_max_static_sq_wq); 1461 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1462 hca_attr->qos.wqe_rate_pp ? "" : "not "); 1463 if (!sh->cdev->config.devx) { 1464 DRV_LOG(ERR, "DevX is required for packet pacing"); 1465 err = ENODEV; 1466 goto error; 1467 } 1468 if (!hca_attr->qos.packet_pacing) { 1469 DRV_LOG(ERR, "Packet pacing is not supported"); 1470 err = ENODEV; 1471 goto error; 1472 } 1473 if (!hca_attr->cross_channel) { 1474 DRV_LOG(ERR, "Cross channel operations are" 1475 " required for packet pacing"); 1476 err = ENODEV; 1477 goto error; 1478 } 1479 if (!hca_attr->wqe_index_ignore) { 1480 DRV_LOG(ERR, "WQE index ignore feature is" 1481 " required for packet pacing"); 1482 err = ENODEV; 1483 goto error; 1484 } 1485 if (!hca_attr->non_wire_sq) { 1486 DRV_LOG(ERR, "Non-wire SQ feature is" 1487 " required for packet pacing"); 1488 err = ENODEV; 1489 goto error; 1490 } 1491 if (!hca_attr->log_max_static_sq_wq) { 1492 DRV_LOG(ERR, "Static WQE SQ feature is" 1493 " required for packet pacing"); 1494 err = ENODEV; 1495 goto error; 1496 } 1497 if (!hca_attr->qos.wqe_rate_pp) { 1498 DRV_LOG(ERR, "WQE rate mode is required" 1499 " for packet pacing"); 1500 err = ENODEV; 1501 goto error; 1502 } 1503 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1504 DRV_LOG(ERR, "DevX does not provide UAR offset," 1505 " can't create queues for packet pacing"); 1506 err = ENODEV; 1507 goto error; 1508 #endif 1509 } 1510 if (config->std_delay_drop || config->hp_delay_drop) { 1511 if (!hca_attr->rq_delay_drop) { 1512 config->std_delay_drop = 0; 1513 config->hp_delay_drop = 0; 1514 DRV_LOG(WARNING, 1515 "dev_port-%u: Rxq delay drop is not supported", 1516 priv->dev_port); 1517 } 1518 } 1519 if (sh->cdev->config.devx) { 1520 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1521 1522 err = hca_attr->access_register_user ? 1523 mlx5_devx_cmd_register_read 1524 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1525 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1526 if (!err) { 1527 uint32_t ts_mode; 1528 1529 /* MTUTC register is read successfully. */ 1530 ts_mode = MLX5_GET(register_mtutc, reg, 1531 time_stamp_mode); 1532 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1533 config->rt_timestamp = 1; 1534 } else { 1535 /* Kernel does not support register reading. */ 1536 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S)) 1537 config->rt_timestamp = 1; 1538 } 1539 } 1540 /* 1541 * If HW has bug working with tunnel packet decapsulation and 1542 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1543 * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1544 */ 1545 if (hca_attr->scatter_fcs_w_decap_disable && config->decap_en) 1546 config->hw_fcs_strip = 0; 1547 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1548 (config->hw_fcs_strip ? "" : "not ")); 1549 if (config->mprq.enabled && !mprq) { 1550 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1551 config->mprq.enabled = 0; 1552 } 1553 if (config->max_dump_files_num == 0) 1554 config->max_dump_files_num = 128; 1555 eth_dev = rte_eth_dev_allocate(name); 1556 if (eth_dev == NULL) { 1557 DRV_LOG(ERR, "can not allocate rte ethdev"); 1558 err = ENOMEM; 1559 goto error; 1560 } 1561 if (priv->representor) { 1562 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1563 eth_dev->data->representor_id = priv->representor_id; 1564 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1565 struct mlx5_priv *opriv = 1566 rte_eth_devices[port_id].data->dev_private; 1567 if (opriv && 1568 opriv->master && 1569 opriv->domain_id == priv->domain_id && 1570 opriv->sh == priv->sh) { 1571 eth_dev->data->backer_port_id = port_id; 1572 break; 1573 } 1574 } 1575 if (port_id >= RTE_MAX_ETHPORTS) 1576 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1577 } 1578 priv->mp_id.port_id = eth_dev->data->port_id; 1579 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1580 /* 1581 * Store associated network device interface index. This index 1582 * is permanent throughout the lifetime of device. So, we may store 1583 * the ifindex here and use the cached value further. 1584 */ 1585 MLX5_ASSERT(spawn->ifindex); 1586 priv->if_index = spawn->ifindex; 1587 priv->lag_affinity_idx = sh->refcnt - 1; 1588 eth_dev->data->dev_private = priv; 1589 priv->dev_data = eth_dev->data; 1590 eth_dev->data->mac_addrs = priv->mac; 1591 eth_dev->device = dpdk_dev; 1592 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1593 /* Configure the first MAC address by default. */ 1594 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1595 DRV_LOG(ERR, 1596 "port %u cannot get MAC address, is mlx5_en" 1597 " loaded? (errno: %s)", 1598 eth_dev->data->port_id, strerror(rte_errno)); 1599 err = ENODEV; 1600 goto error; 1601 } 1602 DRV_LOG(INFO, 1603 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1604 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1605 #ifdef RTE_LIBRTE_MLX5_DEBUG 1606 { 1607 char ifname[MLX5_NAMESIZE]; 1608 1609 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1610 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1611 eth_dev->data->port_id, ifname); 1612 else 1613 DRV_LOG(DEBUG, "port %u ifname is unknown", 1614 eth_dev->data->port_id); 1615 } 1616 #endif 1617 /* Get actual MTU if possible. */ 1618 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1619 if (err) { 1620 err = rte_errno; 1621 goto error; 1622 } 1623 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1624 priv->mtu); 1625 /* Initialize burst functions to prevent crashes before link-up. */ 1626 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 1627 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 1628 eth_dev->dev_ops = &mlx5_dev_ops; 1629 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1630 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1631 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1632 /* Register MAC address. */ 1633 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1634 if (config->vf && config->vf_nl_en) 1635 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1636 mlx5_ifindex(eth_dev), 1637 eth_dev->data->mac_addrs, 1638 MLX5_MAX_MAC_ADDRESSES); 1639 priv->ctrl_flows = 0; 1640 rte_spinlock_init(&priv->flow_list_lock); 1641 TAILQ_INIT(&priv->flow_meters); 1642 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1643 if (!priv->mtr_profile_tbl) 1644 goto error; 1645 /* Bring Ethernet device up. */ 1646 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1647 eth_dev->data->port_id); 1648 mlx5_set_link_up(eth_dev); 1649 /* 1650 * Even though the interrupt handler is not installed yet, 1651 * interrupts will still trigger on the async_fd from 1652 * Verbs context returned by ibv_open_device(). 1653 */ 1654 mlx5_link_update(eth_dev, 0); 1655 /* Detect minimal data bytes to inline. */ 1656 mlx5_set_min_inline(spawn, config); 1657 /* Store device configuration on private structure. */ 1658 priv->config = *config; 1659 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1660 icfg[i].release_mem_en = !!config->reclaim_mode; 1661 if (config->reclaim_mode) 1662 icfg[i].per_core_cache = 0; 1663 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1664 if (!priv->flows[i]) 1665 goto error; 1666 } 1667 /* Create context for virtual machine VLAN workaround. */ 1668 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1669 if (config->dv_flow_en) { 1670 err = mlx5_alloc_shared_dr(priv); 1671 if (err) 1672 goto error; 1673 if (mlx5_flex_item_port_init(eth_dev) < 0) 1674 goto error; 1675 } 1676 if (sh->cdev->config.devx && config->dv_flow_en && config->dest_tir) { 1677 priv->obj_ops = devx_obj_ops; 1678 mlx5_queue_counter_id_prepare(eth_dev); 1679 priv->obj_ops.lb_dummy_queue_create = 1680 mlx5_rxq_ibv_obj_dummy_lb_create; 1681 priv->obj_ops.lb_dummy_queue_release = 1682 mlx5_rxq_ibv_obj_dummy_lb_release; 1683 } else if (spawn->max_port > UINT8_MAX) { 1684 /* Verbs can't support ports larger than 255 by design. */ 1685 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); 1686 err = ENOTSUP; 1687 goto error; 1688 } else { 1689 priv->obj_ops = ibv_obj_ops; 1690 } 1691 if (config->tx_pp && 1692 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new) { 1693 /* 1694 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1695 * packet pacing and already checked above. 1696 * Hence, we should only make sure the SQs will be created 1697 * with DevX, not with Verbs. 1698 * Verbs allocates the SQ UAR on its own and it can't be shared 1699 * with Clock Queue UAR as required for Tx scheduling. 1700 */ 1701 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1702 err = ENODEV; 1703 goto error; 1704 } 1705 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1706 if (!priv->drop_queue.hrxq) 1707 goto error; 1708 /* Port representor shares the same max priority with pf port. */ 1709 if (!priv->sh->flow_priority_check_flag) { 1710 /* Supported Verbs flow priority number detection. */ 1711 err = mlx5_flow_discover_priorities(eth_dev); 1712 priv->sh->flow_max_priority = err; 1713 priv->sh->flow_priority_check_flag = 1; 1714 } else { 1715 err = priv->sh->flow_max_priority; 1716 } 1717 if (err < 0) { 1718 err = -err; 1719 goto error; 1720 } 1721 mlx5_set_metadata_mask(eth_dev); 1722 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1723 !priv->sh->dv_regc0_mask) { 1724 DRV_LOG(ERR, "metadata mode %u is not supported " 1725 "(no metadata reg_c[0] is available)", 1726 priv->config.dv_xmeta_en); 1727 err = ENOTSUP; 1728 goto error; 1729 } 1730 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1731 mlx5_hrxq_create_cb, 1732 mlx5_hrxq_match_cb, 1733 mlx5_hrxq_remove_cb, 1734 mlx5_hrxq_clone_cb, 1735 mlx5_hrxq_clone_free_cb); 1736 if (!priv->hrxqs) 1737 goto error; 1738 rte_rwlock_init(&priv->ind_tbls_lock); 1739 /* Query availability of metadata reg_c's. */ 1740 if (!priv->sh->metadata_regc_check_flag) { 1741 err = mlx5_flow_discover_mreg_c(eth_dev); 1742 if (err < 0) { 1743 err = -err; 1744 goto error; 1745 } 1746 } 1747 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1748 DRV_LOG(DEBUG, 1749 "port %u extensive metadata register is not supported", 1750 eth_dev->data->port_id); 1751 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1752 DRV_LOG(ERR, "metadata mode %u is not supported " 1753 "(no metadata registers available)", 1754 priv->config.dv_xmeta_en); 1755 err = ENOTSUP; 1756 goto error; 1757 } 1758 } 1759 if (priv->config.dv_flow_en && 1760 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1761 mlx5_flow_ext_mreg_supported(eth_dev) && 1762 priv->sh->dv_regc0_mask) { 1763 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1764 MLX5_FLOW_MREG_HTABLE_SZ, 1765 false, true, eth_dev, 1766 flow_dv_mreg_create_cb, 1767 flow_dv_mreg_match_cb, 1768 flow_dv_mreg_remove_cb, 1769 flow_dv_mreg_clone_cb, 1770 flow_dv_mreg_clone_free_cb); 1771 if (!priv->mreg_cp_tbl) { 1772 err = ENOMEM; 1773 goto error; 1774 } 1775 } 1776 rte_spinlock_init(&priv->shared_act_sl); 1777 mlx5_flow_counter_mode_config(eth_dev); 1778 mlx5_flow_drop_action_config(eth_dev); 1779 if (priv->config.dv_flow_en) 1780 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1781 return eth_dev; 1782 error: 1783 if (priv) { 1784 if (priv->mreg_cp_tbl) 1785 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1786 if (priv->sh) 1787 mlx5_os_free_shared_dr(priv); 1788 if (priv->nl_socket_route >= 0) 1789 close(priv->nl_socket_route); 1790 if (priv->vmwa_context) 1791 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1792 if (eth_dev && priv->drop_queue.hrxq) 1793 mlx5_drop_action_destroy(eth_dev); 1794 if (priv->mtr_profile_tbl) 1795 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1796 if (own_domain_id) 1797 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1798 if (priv->hrxqs) 1799 mlx5_list_destroy(priv->hrxqs); 1800 if (eth_dev && priv->flex_item_map) 1801 mlx5_flex_item_port_cleanup(eth_dev); 1802 mlx5_free(priv); 1803 if (eth_dev != NULL) 1804 eth_dev->data->dev_private = NULL; 1805 } 1806 if (eth_dev != NULL) { 1807 /* mac_addrs must not be freed alone because part of 1808 * dev_private 1809 **/ 1810 eth_dev->data->mac_addrs = NULL; 1811 rte_eth_dev_release_port(eth_dev); 1812 } 1813 if (sh) 1814 mlx5_free_shared_dev_ctx(sh); 1815 if (nl_rdma >= 0) 1816 close(nl_rdma); 1817 MLX5_ASSERT(err > 0); 1818 rte_errno = err; 1819 return NULL; 1820 } 1821 1822 /** 1823 * Comparison callback to sort device data. 1824 * 1825 * This is meant to be used with qsort(). 1826 * 1827 * @param a[in] 1828 * Pointer to pointer to first data object. 1829 * @param b[in] 1830 * Pointer to pointer to second data object. 1831 * 1832 * @return 1833 * 0 if both objects are equal, less than 0 if the first argument is less 1834 * than the second, greater than 0 otherwise. 1835 */ 1836 static int 1837 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1838 { 1839 const struct mlx5_switch_info *si_a = 1840 &((const struct mlx5_dev_spawn_data *)a)->info; 1841 const struct mlx5_switch_info *si_b = 1842 &((const struct mlx5_dev_spawn_data *)b)->info; 1843 int ret; 1844 1845 /* Master device first. */ 1846 ret = si_b->master - si_a->master; 1847 if (ret) 1848 return ret; 1849 /* Then representor devices. */ 1850 ret = si_b->representor - si_a->representor; 1851 if (ret) 1852 return ret; 1853 /* Unidentified devices come last in no specific order. */ 1854 if (!si_a->representor) 1855 return 0; 1856 /* Order representors by name. */ 1857 return si_a->port_name - si_b->port_name; 1858 } 1859 1860 /** 1861 * Match PCI information for possible slaves of bonding device. 1862 * 1863 * @param[in] ibdev_name 1864 * Name of Infiniband device. 1865 * @param[in] pci_dev 1866 * Pointer to primary PCI address structure to match. 1867 * @param[in] nl_rdma 1868 * Netlink RDMA group socket handle. 1869 * @param[in] owner 1870 * Representor owner PF index. 1871 * @param[out] bond_info 1872 * Pointer to bonding information. 1873 * 1874 * @return 1875 * negative value if no bonding device found, otherwise 1876 * positive index of slave PF in bonding. 1877 */ 1878 static int 1879 mlx5_device_bond_pci_match(const char *ibdev_name, 1880 const struct rte_pci_addr *pci_dev, 1881 int nl_rdma, uint16_t owner, 1882 struct mlx5_bond_info *bond_info) 1883 { 1884 char ifname[IF_NAMESIZE + 1]; 1885 unsigned int ifindex; 1886 unsigned int np, i; 1887 FILE *bond_file = NULL, *file; 1888 int pf = -1; 1889 int ret; 1890 uint8_t cur_guid[32] = {0}; 1891 uint8_t guid[32] = {0}; 1892 1893 /* 1894 * Try to get master device name. If something goes wrong suppose 1895 * the lack of kernel support and no bonding devices. 1896 */ 1897 memset(bond_info, 0, sizeof(*bond_info)); 1898 if (nl_rdma < 0) 1899 return -1; 1900 if (!strstr(ibdev_name, "bond")) 1901 return -1; 1902 np = mlx5_nl_portnum(nl_rdma, ibdev_name); 1903 if (!np) 1904 return -1; 1905 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) 1906 return -1; 1907 /* 1908 * The master device might not be on the predefined port(not on port 1909 * index 1, it is not guaranteed), we have to scan all Infiniband 1910 * device ports and find master. 1911 */ 1912 for (i = 1; i <= np; ++i) { 1913 /* Check whether Infiniband port is populated. */ 1914 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); 1915 if (!ifindex) 1916 continue; 1917 if (!if_indextoname(ifindex, ifname)) 1918 continue; 1919 /* Try to read bonding slave names from sysfs. */ 1920 MKSTR(slaves, 1921 "/sys/class/net/%s/master/bonding/slaves", ifname); 1922 bond_file = fopen(slaves, "r"); 1923 if (bond_file) 1924 break; 1925 } 1926 if (!bond_file) 1927 return -1; 1928 /* Use safe format to check maximal buffer length. */ 1929 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1930 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1931 char tmp_str[IF_NAMESIZE + 32]; 1932 struct rte_pci_addr pci_addr; 1933 struct mlx5_switch_info info; 1934 int ret; 1935 1936 /* Process slave interface names in the loop. */ 1937 snprintf(tmp_str, sizeof(tmp_str), 1938 "/sys/class/net/%s", ifname); 1939 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 1940 DRV_LOG(WARNING, 1941 "Cannot get PCI address for netdev \"%s\".", 1942 ifname); 1943 continue; 1944 } 1945 /* Slave interface PCI address match found. */ 1946 snprintf(tmp_str, sizeof(tmp_str), 1947 "/sys/class/net/%s/phys_port_name", ifname); 1948 file = fopen(tmp_str, "rb"); 1949 if (!file) 1950 break; 1951 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1952 if (fscanf(file, "%32s", tmp_str) == 1) 1953 mlx5_translate_port_name(tmp_str, &info); 1954 fclose(file); 1955 /* Only process PF ports. */ 1956 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1957 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1958 continue; 1959 /* Check max bonding member. */ 1960 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1961 DRV_LOG(WARNING, "bonding index out of range, " 1962 "please increase MLX5_BOND_MAX_PORTS: %s", 1963 tmp_str); 1964 break; 1965 } 1966 /* Get ifindex. */ 1967 snprintf(tmp_str, sizeof(tmp_str), 1968 "/sys/class/net/%s/ifindex", ifname); 1969 file = fopen(tmp_str, "rb"); 1970 if (!file) 1971 break; 1972 ret = fscanf(file, "%u", &ifindex); 1973 fclose(file); 1974 if (ret != 1) 1975 break; 1976 /* Save bonding info. */ 1977 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1978 sizeof(bond_info->ports[0].ifname)); 1979 bond_info->ports[info.port_name].pci_addr = pci_addr; 1980 bond_info->ports[info.port_name].ifindex = ifindex; 1981 bond_info->n_port++; 1982 /* 1983 * Under socket direct mode, bonding will use 1984 * system_image_guid as identification. 1985 * After OFED 5.4, guid is readable (ret >= 0) under sysfs. 1986 * All bonding members should have the same guid even if driver 1987 * is using PCIe BDF. 1988 */ 1989 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid)); 1990 if (ret < 0) 1991 break; 1992 else if (ret > 0) { 1993 if (!memcmp(guid, cur_guid, sizeof(guid)) && 1994 owner == info.port_name && 1995 (owner != 0 || (owner == 0 && 1996 !rte_pci_addr_cmp(pci_dev, &pci_addr)))) 1997 pf = info.port_name; 1998 } else if (pci_dev->domain == pci_addr.domain && 1999 pci_dev->bus == pci_addr.bus && 2000 pci_dev->devid == pci_addr.devid && 2001 ((pci_dev->function == 0 && 2002 pci_dev->function + owner == pci_addr.function) || 2003 (pci_dev->function == owner && 2004 pci_addr.function == owner))) 2005 pf = info.port_name; 2006 } 2007 if (pf >= 0) { 2008 /* Get bond interface info */ 2009 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2010 bond_info->ifname); 2011 if (ret) 2012 DRV_LOG(ERR, "unable to get bond info: %s", 2013 strerror(rte_errno)); 2014 else 2015 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2016 ifindex, bond_info->ifindex, bond_info->ifname); 2017 } 2018 if (owner == 0 && pf != 0) { 2019 DRV_LOG(INFO, "PCIe instance %04x:%02x:%02x.%x isn't bonding owner", 2020 pci_dev->domain, pci_dev->bus, pci_dev->devid, 2021 pci_dev->function); 2022 } 2023 return pf; 2024 } 2025 2026 static void 2027 mlx5_os_config_default(struct mlx5_dev_config *config, 2028 struct mlx5_common_dev_config *cconf) 2029 { 2030 memset(config, 0, sizeof(*config)); 2031 config->mps = MLX5_ARG_UNSET; 2032 config->cqe_comp = 1; 2033 config->rx_vec_en = 1; 2034 config->txq_inline_max = MLX5_ARG_UNSET; 2035 config->txq_inline_min = MLX5_ARG_UNSET; 2036 config->txq_inline_mpw = MLX5_ARG_UNSET; 2037 config->txqs_inline = MLX5_ARG_UNSET; 2038 config->vf_nl_en = 1; 2039 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2040 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2041 config->mprq.log_min_stride_wqe_size = cconf->devx ? 2042 cconf->hca_attr.log_min_stride_wqe_sz : 2043 MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 2044 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; 2045 config->dv_esw_en = 1; 2046 config->dv_flow_en = 1; 2047 config->decap_en = 1; 2048 config->log_hp_size = MLX5_ARG_UNSET; 2049 config->allow_duplicate_pattern = 1; 2050 config->std_delay_drop = 0; 2051 config->hp_delay_drop = 0; 2052 } 2053 2054 /** 2055 * Register a PCI device within bonding. 2056 * 2057 * This function spawns Ethernet devices out of a given PCI device and 2058 * bonding owner PF index. 2059 * 2060 * @param[in] cdev 2061 * Pointer to common mlx5 device structure. 2062 * @param[in] req_eth_da 2063 * Requested ethdev device argument. 2064 * @param[in] owner_id 2065 * Requested owner PF port ID within bonding device, default to 0. 2066 * 2067 * @return 2068 * 0 on success, a negative errno value otherwise and rte_errno is set. 2069 */ 2070 static int 2071 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, 2072 struct rte_eth_devargs *req_eth_da, 2073 uint16_t owner_id) 2074 { 2075 struct ibv_device **ibv_list; 2076 /* 2077 * Number of found IB Devices matching with requested PCI BDF. 2078 * nd != 1 means there are multiple IB devices over the same 2079 * PCI device and we have representors and master. 2080 */ 2081 unsigned int nd = 0; 2082 /* 2083 * Number of found IB device Ports. nd = 1 and np = 1..n means 2084 * we have the single multiport IB device, and there may be 2085 * representors attached to some of found ports. 2086 */ 2087 unsigned int np = 0; 2088 /* 2089 * Number of DPDK ethernet devices to Spawn - either over 2090 * multiple IB devices or multiple ports of single IB device. 2091 * Actually this is the number of iterations to spawn. 2092 */ 2093 unsigned int ns = 0; 2094 /* 2095 * Bonding device 2096 * < 0 - no bonding device (single one) 2097 * >= 0 - bonding device (value is slave PF index) 2098 */ 2099 int bd = -1; 2100 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2101 struct mlx5_dev_spawn_data *list = NULL; 2102 struct mlx5_dev_config dev_config; 2103 unsigned int dev_config_vf; 2104 struct rte_eth_devargs eth_da = *req_eth_da; 2105 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2106 struct mlx5_bond_info bond_info; 2107 int ret = -1; 2108 2109 errno = 0; 2110 ibv_list = mlx5_glue->get_device_list(&ret); 2111 if (!ibv_list) { 2112 rte_errno = errno ? errno : ENOSYS; 2113 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?"); 2114 return -rte_errno; 2115 } 2116 /* 2117 * First scan the list of all Infiniband devices to find 2118 * matching ones, gathering into the list. 2119 */ 2120 struct ibv_device *ibv_match[ret + 1]; 2121 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2122 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2123 unsigned int i; 2124 2125 while (ret-- > 0) { 2126 struct rte_pci_addr pci_addr; 2127 2128 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); 2129 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, 2130 nl_rdma, owner_id, &bond_info); 2131 if (bd >= 0) { 2132 /* 2133 * Bonding device detected. Only one match is allowed, 2134 * the bonding is supported over multi-port IB device, 2135 * there should be no matches on representor PCI 2136 * functions or non VF LAG bonding devices with 2137 * specified address. 2138 */ 2139 if (nd) { 2140 DRV_LOG(ERR, 2141 "multiple PCI match on bonding device" 2142 "\"%s\" found", ibv_list[ret]->name); 2143 rte_errno = ENOENT; 2144 ret = -rte_errno; 2145 goto exit; 2146 } 2147 /* Amend owner pci address if owner PF ID specified. */ 2148 if (eth_da.nb_representor_ports) 2149 owner_pci.function += owner_id; 2150 DRV_LOG(INFO, 2151 "PCI information matches for slave %d bonding device \"%s\"", 2152 bd, ibv_list[ret]->name); 2153 ibv_match[nd++] = ibv_list[ret]; 2154 break; 2155 } else { 2156 /* Bonding device not found. */ 2157 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2158 &pci_addr)) 2159 continue; 2160 if (owner_pci.domain != pci_addr.domain || 2161 owner_pci.bus != pci_addr.bus || 2162 owner_pci.devid != pci_addr.devid || 2163 owner_pci.function != pci_addr.function) 2164 continue; 2165 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2166 ibv_list[ret]->name); 2167 ibv_match[nd++] = ibv_list[ret]; 2168 } 2169 } 2170 ibv_match[nd] = NULL; 2171 if (!nd) { 2172 /* No device matches, just complain and bail out. */ 2173 DRV_LOG(WARNING, 2174 "No Verbs device matches PCI device " PCI_PRI_FMT "," 2175 " are kernel drivers loaded?", 2176 owner_pci.domain, owner_pci.bus, 2177 owner_pci.devid, owner_pci.function); 2178 rte_errno = ENOENT; 2179 ret = -rte_errno; 2180 goto exit; 2181 } 2182 if (nd == 1) { 2183 /* 2184 * Found single matching device may have multiple ports. 2185 * Each port may be representor, we have to check the port 2186 * number and check the representors existence. 2187 */ 2188 if (nl_rdma >= 0) 2189 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2190 if (!np) 2191 DRV_LOG(WARNING, 2192 "Cannot get IB device \"%s\" ports number.", 2193 ibv_match[0]->name); 2194 if (bd >= 0 && !np) { 2195 DRV_LOG(ERR, "Cannot get ports for bonding device."); 2196 rte_errno = ENOENT; 2197 ret = -rte_errno; 2198 goto exit; 2199 } 2200 } 2201 /* Now we can determine the maximal amount of devices to be spawned. */ 2202 list = mlx5_malloc(MLX5_MEM_ZERO, 2203 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd), 2204 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2205 if (!list) { 2206 DRV_LOG(ERR, "Spawn data array allocation failure."); 2207 rte_errno = ENOMEM; 2208 ret = -rte_errno; 2209 goto exit; 2210 } 2211 if (bd >= 0 || np > 1) { 2212 /* 2213 * Single IB device with multiple ports found, 2214 * it may be E-Switch master device and representors. 2215 * We have to perform identification through the ports. 2216 */ 2217 MLX5_ASSERT(nl_rdma >= 0); 2218 MLX5_ASSERT(ns == 0); 2219 MLX5_ASSERT(nd == 1); 2220 MLX5_ASSERT(np); 2221 for (i = 1; i <= np; ++i) { 2222 list[ns].bond_info = &bond_info; 2223 list[ns].max_port = np; 2224 list[ns].phys_port = i; 2225 list[ns].phys_dev_name = ibv_match[0]->name; 2226 list[ns].eth_dev = NULL; 2227 list[ns].pci_dev = pci_dev; 2228 list[ns].cdev = cdev; 2229 list[ns].pf_bond = bd; 2230 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, 2231 ibv_match[0]->name, 2232 i); 2233 if (!list[ns].ifindex) { 2234 /* 2235 * No network interface index found for the 2236 * specified port, it means there is no 2237 * representor on this port. It's OK, 2238 * there can be disabled ports, for example 2239 * if sriov_numvfs < sriov_totalvfs. 2240 */ 2241 continue; 2242 } 2243 ret = -1; 2244 if (nl_route >= 0) 2245 ret = mlx5_nl_switch_info(nl_route, 2246 list[ns].ifindex, 2247 &list[ns].info); 2248 if (ret || (!list[ns].info.representor && 2249 !list[ns].info.master)) { 2250 /* 2251 * We failed to recognize representors with 2252 * Netlink, let's try to perform the task 2253 * with sysfs. 2254 */ 2255 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2256 &list[ns].info); 2257 } 2258 if (!ret && bd >= 0) { 2259 switch (list[ns].info.name_type) { 2260 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2261 if (np == 1) { 2262 /* 2263 * Force standalone bonding 2264 * device for ROCE LAG 2265 * configurations. 2266 */ 2267 list[ns].info.master = 0; 2268 list[ns].info.representor = 0; 2269 } 2270 if (list[ns].info.port_name == bd) 2271 ns++; 2272 break; 2273 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2274 /* Fallthrough */ 2275 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2276 /* Fallthrough */ 2277 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2278 if (list[ns].info.pf_num == bd) 2279 ns++; 2280 break; 2281 default: 2282 break; 2283 } 2284 continue; 2285 } 2286 if (!ret && (list[ns].info.representor ^ 2287 list[ns].info.master)) 2288 ns++; 2289 } 2290 if (!ns) { 2291 DRV_LOG(ERR, 2292 "Unable to recognize master/representors on the IB device with multiple ports."); 2293 rte_errno = ENOENT; 2294 ret = -rte_errno; 2295 goto exit; 2296 } 2297 } else { 2298 /* 2299 * The existence of several matching entries (nd > 1) means 2300 * port representors have been instantiated. No existing Verbs 2301 * call nor sysfs entries can tell them apart, this can only 2302 * be done through Netlink calls assuming kernel drivers are 2303 * recent enough to support them. 2304 * 2305 * In the event of identification failure through Netlink, 2306 * try again through sysfs, then: 2307 * 2308 * 1. A single IB device matches (nd == 1) with single 2309 * port (np=0/1) and is not a representor, assume 2310 * no switch support. 2311 * 2312 * 2. Otherwise no safe assumptions can be made; 2313 * complain louder and bail out. 2314 */ 2315 for (i = 0; i != nd; ++i) { 2316 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2317 list[ns].bond_info = NULL; 2318 list[ns].max_port = 1; 2319 list[ns].phys_port = 1; 2320 list[ns].phys_dev_name = ibv_match[i]->name; 2321 list[ns].eth_dev = NULL; 2322 list[ns].pci_dev = pci_dev; 2323 list[ns].cdev = cdev; 2324 list[ns].pf_bond = -1; 2325 list[ns].ifindex = 0; 2326 if (nl_rdma >= 0) 2327 list[ns].ifindex = mlx5_nl_ifindex 2328 (nl_rdma, 2329 ibv_match[i]->name, 2330 1); 2331 if (!list[ns].ifindex) { 2332 char ifname[IF_NAMESIZE]; 2333 2334 /* 2335 * Netlink failed, it may happen with old 2336 * ib_core kernel driver (before 4.16). 2337 * We can assume there is old driver because 2338 * here we are processing single ports IB 2339 * devices. Let's try sysfs to retrieve 2340 * the ifindex. The method works for 2341 * master device only. 2342 */ 2343 if (nd > 1) { 2344 /* 2345 * Multiple devices found, assume 2346 * representors, can not distinguish 2347 * master/representor and retrieve 2348 * ifindex via sysfs. 2349 */ 2350 continue; 2351 } 2352 ret = mlx5_get_ifname_sysfs 2353 (ibv_match[i]->ibdev_path, ifname); 2354 if (!ret) 2355 list[ns].ifindex = 2356 if_nametoindex(ifname); 2357 if (!list[ns].ifindex) { 2358 /* 2359 * No network interface index found 2360 * for the specified device, it means 2361 * there it is neither representor 2362 * nor master. 2363 */ 2364 continue; 2365 } 2366 } 2367 ret = -1; 2368 if (nl_route >= 0) 2369 ret = mlx5_nl_switch_info(nl_route, 2370 list[ns].ifindex, 2371 &list[ns].info); 2372 if (ret || (!list[ns].info.representor && 2373 !list[ns].info.master)) { 2374 /* 2375 * We failed to recognize representors with 2376 * Netlink, let's try to perform the task 2377 * with sysfs. 2378 */ 2379 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2380 &list[ns].info); 2381 } 2382 if (!ret && (list[ns].info.representor ^ 2383 list[ns].info.master)) { 2384 ns++; 2385 } else if ((nd == 1) && 2386 !list[ns].info.representor && 2387 !list[ns].info.master) { 2388 /* 2389 * Single IB device with one physical port and 2390 * attached network device. 2391 * May be SRIOV is not enabled or there is no 2392 * representors. 2393 */ 2394 DRV_LOG(INFO, "No E-Switch support detected."); 2395 ns++; 2396 break; 2397 } 2398 } 2399 if (!ns) { 2400 DRV_LOG(ERR, 2401 "Unable to recognize master/representors on the multiple IB devices."); 2402 rte_errno = ENOENT; 2403 ret = -rte_errno; 2404 goto exit; 2405 } 2406 /* 2407 * New kernels may add the switch_id attribute for the case 2408 * there is no E-Switch and we wrongly recognized the only 2409 * device as master. Override this if there is the single 2410 * device with single port and new device name format present. 2411 */ 2412 if (nd == 1 && 2413 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2414 list[0].info.master = 0; 2415 list[0].info.representor = 0; 2416 } 2417 } 2418 MLX5_ASSERT(ns); 2419 /* 2420 * Sort list to probe devices in natural order for users convenience 2421 * (i.e. master first, then representors from lowest to highest ID). 2422 */ 2423 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2424 /* Device specific configuration. */ 2425 switch (pci_dev->id.device_id) { 2426 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2427 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2428 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2429 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2430 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2431 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2432 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2433 dev_config_vf = 1; 2434 break; 2435 default: 2436 dev_config_vf = 0; 2437 break; 2438 } 2439 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2440 /* Set devargs default values. */ 2441 if (eth_da.nb_mh_controllers == 0) { 2442 eth_da.nb_mh_controllers = 1; 2443 eth_da.mh_controllers[0] = 0; 2444 } 2445 if (eth_da.nb_ports == 0 && ns > 0) { 2446 if (list[0].pf_bond >= 0 && list[0].info.representor) 2447 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2448 pci_dev->device.devargs->args); 2449 eth_da.nb_ports = 1; 2450 eth_da.ports[0] = list[0].info.pf_num; 2451 } 2452 if (eth_da.nb_representor_ports == 0) { 2453 eth_da.nb_representor_ports = 1; 2454 eth_da.representor_ports[0] = 0; 2455 } 2456 } 2457 for (i = 0; i != ns; ++i) { 2458 uint32_t restore; 2459 2460 /* Default configuration. */ 2461 mlx5_os_config_default(&dev_config, &cdev->config); 2462 dev_config.vf = dev_config_vf; 2463 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], 2464 &dev_config, ð_da); 2465 if (!list[i].eth_dev) { 2466 if (rte_errno != EBUSY && rte_errno != EEXIST) 2467 break; 2468 /* Device is disabled or already spawned. Ignore it. */ 2469 continue; 2470 } 2471 restore = list[i].eth_dev->data->dev_flags; 2472 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2473 /** 2474 * Each representor has a dedicated interrupts vector. 2475 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2476 * representor eth_dev object because representor and PF 2477 * share the same PCI address. 2478 * Override representor device with a dedicated 2479 * interrupts handle here. 2480 * Representor interrupts handle is released in mlx5_dev_stop(). 2481 */ 2482 if (list[i].info.representor) { 2483 struct rte_intr_handle *intr_handle = 2484 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2485 if (intr_handle == NULL) { 2486 DRV_LOG(ERR, 2487 "port %u failed to allocate memory for interrupt handler " 2488 "Rx interrupts will not be supported", 2489 i); 2490 rte_errno = ENOMEM; 2491 ret = -rte_errno; 2492 goto exit; 2493 } 2494 list[i].eth_dev->intr_handle = intr_handle; 2495 } 2496 /* Restore non-PCI flags cleared by the above call. */ 2497 list[i].eth_dev->data->dev_flags |= restore; 2498 rte_eth_dev_probing_finish(list[i].eth_dev); 2499 } 2500 if (i != ns) { 2501 DRV_LOG(ERR, 2502 "probe of PCI device " PCI_PRI_FMT " aborted after" 2503 " encountering an error: %s", 2504 owner_pci.domain, owner_pci.bus, 2505 owner_pci.devid, owner_pci.function, 2506 strerror(rte_errno)); 2507 ret = -rte_errno; 2508 /* Roll back. */ 2509 while (i--) { 2510 if (!list[i].eth_dev) 2511 continue; 2512 mlx5_dev_close(list[i].eth_dev); 2513 /* mac_addrs must not be freed because in dev_private */ 2514 list[i].eth_dev->data->mac_addrs = NULL; 2515 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2516 } 2517 /* Restore original error. */ 2518 rte_errno = -ret; 2519 } else { 2520 ret = 0; 2521 } 2522 exit: 2523 /* 2524 * Do the routine cleanup: 2525 * - close opened Netlink sockets 2526 * - free allocated spawn data array 2527 * - free the Infiniband device list 2528 */ 2529 if (nl_rdma >= 0) 2530 close(nl_rdma); 2531 if (nl_route >= 0) 2532 close(nl_route); 2533 if (list) 2534 mlx5_free(list); 2535 MLX5_ASSERT(ibv_list); 2536 mlx5_glue->free_device_list(ibv_list); 2537 return ret; 2538 } 2539 2540 static int 2541 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2542 struct rte_eth_devargs *eth_da) 2543 { 2544 int ret = 0; 2545 2546 if (dev->devargs == NULL) 2547 return 0; 2548 memset(eth_da, 0, sizeof(*eth_da)); 2549 /* Parse representor information first from class argument. */ 2550 if (dev->devargs->cls_str) 2551 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2552 if (ret != 0) { 2553 DRV_LOG(ERR, "failed to parse device arguments: %s", 2554 dev->devargs->cls_str); 2555 return -rte_errno; 2556 } 2557 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2558 /* Parse legacy device argument */ 2559 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2560 if (ret) { 2561 DRV_LOG(ERR, "failed to parse device arguments: %s", 2562 dev->devargs->args); 2563 return -rte_errno; 2564 } 2565 } 2566 return 0; 2567 } 2568 2569 /** 2570 * Callback to register a PCI device. 2571 * 2572 * This function spawns Ethernet devices out of a given PCI device. 2573 * 2574 * @param[in] cdev 2575 * Pointer to common mlx5 device structure. 2576 * 2577 * @return 2578 * 0 on success, a negative errno value otherwise and rte_errno is set. 2579 */ 2580 static int 2581 mlx5_os_pci_probe(struct mlx5_common_device *cdev) 2582 { 2583 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2584 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2585 int ret = 0; 2586 uint16_t p; 2587 2588 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da); 2589 if (ret != 0) 2590 return ret; 2591 2592 if (eth_da.nb_ports > 0) { 2593 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2594 for (p = 0; p < eth_da.nb_ports; p++) { 2595 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 2596 eth_da.ports[p]); 2597 if (ret) 2598 break; 2599 } 2600 if (ret) { 2601 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2602 "aborted due to prodding failure of PF %u", 2603 pci_dev->addr.domain, pci_dev->addr.bus, 2604 pci_dev->addr.devid, pci_dev->addr.function, 2605 eth_da.ports[p]); 2606 mlx5_net_remove(cdev); 2607 } 2608 } else { 2609 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0); 2610 } 2611 return ret; 2612 } 2613 2614 /* Probe a single SF device on auxiliary bus, no representor support. */ 2615 static int 2616 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev) 2617 { 2618 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2619 struct mlx5_dev_config config; 2620 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2621 struct rte_device *dev = cdev->dev; 2622 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2623 struct rte_eth_dev *eth_dev; 2624 int ret = 0; 2625 2626 /* Parse ethdev devargs. */ 2627 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2628 if (ret != 0) 2629 return ret; 2630 /* Set default config data. */ 2631 mlx5_os_config_default(&config, &cdev->config); 2632 config.sf = 1; 2633 /* Init spawn data. */ 2634 spawn.max_port = 1; 2635 spawn.phys_port = 1; 2636 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 2637 ret = mlx5_auxiliary_get_ifindex(dev->name); 2638 if (ret < 0) { 2639 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2640 return ret; 2641 } 2642 spawn.ifindex = ret; 2643 spawn.cdev = cdev; 2644 /* Spawn device. */ 2645 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2646 if (eth_dev == NULL) 2647 return -rte_errno; 2648 /* Post create. */ 2649 eth_dev->intr_handle = adev->intr_handle; 2650 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2651 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2652 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2653 eth_dev->data->numa_node = dev->numa_node; 2654 } 2655 rte_eth_dev_probing_finish(eth_dev); 2656 return 0; 2657 } 2658 2659 /** 2660 * Net class driver callback to probe a device. 2661 * 2662 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2663 * 2664 * @param[in] cdev 2665 * Pointer to the common mlx5 device. 2666 * 2667 * @return 2668 * 0 on success, a negative errno value otherwise and rte_errno is set. 2669 */ 2670 int 2671 mlx5_os_net_probe(struct mlx5_common_device *cdev) 2672 { 2673 int ret; 2674 2675 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2676 mlx5_pmd_socket_init(); 2677 ret = mlx5_init_once(); 2678 if (ret) { 2679 DRV_LOG(ERR, "Unable to init PMD global data: %s", 2680 strerror(rte_errno)); 2681 return -rte_errno; 2682 } 2683 if (mlx5_dev_is_pci(cdev->dev)) 2684 return mlx5_os_pci_probe(cdev); 2685 else 2686 return mlx5_os_auxiliary_probe(cdev); 2687 } 2688 2689 /** 2690 * Cleanup resources when the last device is closed. 2691 */ 2692 void 2693 mlx5_os_net_cleanup(void) 2694 { 2695 mlx5_pmd_socket_uninit(); 2696 } 2697 2698 /** 2699 * Install shared asynchronous device events handler. 2700 * This function is implemented to support event sharing 2701 * between multiple ports of single IB device. 2702 * 2703 * @param sh 2704 * Pointer to mlx5_dev_ctx_shared object. 2705 */ 2706 void 2707 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2708 { 2709 int ret; 2710 int flags; 2711 struct ibv_context *ctx = sh->cdev->ctx; 2712 2713 sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2714 if (sh->intr_handle == NULL) { 2715 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2716 rte_errno = ENOMEM; 2717 return; 2718 } 2719 rte_intr_fd_set(sh->intr_handle, -1); 2720 2721 flags = fcntl(ctx->async_fd, F_GETFL); 2722 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); 2723 if (ret) { 2724 DRV_LOG(INFO, "failed to change file descriptor async event" 2725 " queue"); 2726 } else { 2727 rte_intr_fd_set(sh->intr_handle, ctx->async_fd); 2728 rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); 2729 if (rte_intr_callback_register(sh->intr_handle, 2730 mlx5_dev_interrupt_handler, sh)) { 2731 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2732 rte_intr_fd_set(sh->intr_handle, -1); 2733 } 2734 } 2735 if (sh->cdev->config.devx) { 2736 #ifdef HAVE_IBV_DEVX_ASYNC 2737 sh->intr_handle_devx = 2738 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2739 if (!sh->intr_handle_devx) { 2740 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2741 rte_errno = ENOMEM; 2742 return; 2743 } 2744 rte_intr_fd_set(sh->intr_handle_devx, -1); 2745 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); 2746 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2747 if (!devx_comp) { 2748 DRV_LOG(INFO, "failed to allocate devx_comp."); 2749 return; 2750 } 2751 flags = fcntl(devx_comp->fd, F_GETFL); 2752 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2753 if (ret) { 2754 DRV_LOG(INFO, "failed to change file descriptor" 2755 " devx comp"); 2756 return; 2757 } 2758 rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); 2759 rte_intr_type_set(sh->intr_handle_devx, 2760 RTE_INTR_HANDLE_EXT); 2761 if (rte_intr_callback_register(sh->intr_handle_devx, 2762 mlx5_dev_interrupt_handler_devx, sh)) { 2763 DRV_LOG(INFO, "Fail to install the devx shared" 2764 " interrupt."); 2765 rte_intr_fd_set(sh->intr_handle_devx, -1); 2766 } 2767 #endif /* HAVE_IBV_DEVX_ASYNC */ 2768 } 2769 } 2770 2771 /** 2772 * Uninstall shared asynchronous device events handler. 2773 * This function is implemented to support event sharing 2774 * between multiple ports of single IB device. 2775 * 2776 * @param dev 2777 * Pointer to mlx5_dev_ctx_shared object. 2778 */ 2779 void 2780 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2781 { 2782 if (rte_intr_fd_get(sh->intr_handle) >= 0) 2783 mlx5_intr_callback_unregister(sh->intr_handle, 2784 mlx5_dev_interrupt_handler, sh); 2785 rte_intr_instance_free(sh->intr_handle); 2786 #ifdef HAVE_IBV_DEVX_ASYNC 2787 if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) 2788 rte_intr_callback_unregister(sh->intr_handle_devx, 2789 mlx5_dev_interrupt_handler_devx, sh); 2790 rte_intr_instance_free(sh->intr_handle_devx); 2791 if (sh->devx_comp) 2792 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2793 #endif 2794 } 2795 2796 /** 2797 * Read statistics by a named counter. 2798 * 2799 * @param[in] priv 2800 * Pointer to the private device data structure. 2801 * @param[in] ctr_name 2802 * Pointer to the name of the statistic counter to read 2803 * @param[out] stat 2804 * Pointer to read statistic value. 2805 * @return 2806 * 0 on success and stat is valud, 1 if failed to read the value 2807 * rte_errno is set. 2808 * 2809 */ 2810 int 2811 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2812 uint64_t *stat) 2813 { 2814 int fd; 2815 2816 if (priv->sh) { 2817 if (priv->q_counters != NULL && 2818 strcmp(ctr_name, "out_of_buffer") == 0) 2819 return mlx5_devx_cmd_queue_counter_query 2820 (priv->q_counters, 0, (uint32_t *)stat); 2821 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2822 priv->sh->ibdev_path, 2823 priv->dev_port, 2824 ctr_name); 2825 fd = open(path, O_RDONLY); 2826 /* 2827 * in switchdev the file location is not per port 2828 * but rather in <ibdev_path>/hw_counters/<file_name>. 2829 */ 2830 if (fd == -1) { 2831 MKSTR(path1, "%s/hw_counters/%s", 2832 priv->sh->ibdev_path, 2833 ctr_name); 2834 fd = open(path1, O_RDONLY); 2835 } 2836 if (fd != -1) { 2837 char buf[21] = {'\0'}; 2838 ssize_t n = read(fd, buf, sizeof(buf)); 2839 2840 close(fd); 2841 if (n != -1) { 2842 *stat = strtoull(buf, NULL, 10); 2843 return 0; 2844 } 2845 } 2846 } 2847 *stat = 0; 2848 return 1; 2849 } 2850 2851 /** 2852 * Remove a MAC address from device 2853 * 2854 * @param dev 2855 * Pointer to Ethernet device structure. 2856 * @param index 2857 * MAC address index. 2858 */ 2859 void 2860 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2861 { 2862 struct mlx5_priv *priv = dev->data->dev_private; 2863 const int vf = priv->config.vf; 2864 2865 if (vf) 2866 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2867 mlx5_ifindex(dev), priv->mac_own, 2868 &dev->data->mac_addrs[index], index); 2869 } 2870 2871 /** 2872 * Adds a MAC address to the device 2873 * 2874 * @param dev 2875 * Pointer to Ethernet device structure. 2876 * @param mac_addr 2877 * MAC address to register. 2878 * @param index 2879 * MAC address index. 2880 * 2881 * @return 2882 * 0 on success, a negative errno value otherwise 2883 */ 2884 int 2885 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2886 uint32_t index) 2887 { 2888 struct mlx5_priv *priv = dev->data->dev_private; 2889 const int vf = priv->config.vf; 2890 int ret = 0; 2891 2892 if (vf) 2893 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2894 mlx5_ifindex(dev), priv->mac_own, 2895 mac, index); 2896 return ret; 2897 } 2898 2899 /** 2900 * Modify a VF MAC address 2901 * 2902 * @param priv 2903 * Pointer to device private data. 2904 * @param mac_addr 2905 * MAC address to modify into. 2906 * @param iface_idx 2907 * Net device interface index 2908 * @param vf_index 2909 * VF index 2910 * 2911 * @return 2912 * 0 on success, a negative errno value otherwise 2913 */ 2914 int 2915 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2916 unsigned int iface_idx, 2917 struct rte_ether_addr *mac_addr, 2918 int vf_index) 2919 { 2920 return mlx5_nl_vf_mac_addr_modify 2921 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2922 } 2923 2924 /** 2925 * Set device promiscuous mode 2926 * 2927 * @param dev 2928 * Pointer to Ethernet device structure. 2929 * @param enable 2930 * 0 - promiscuous is disabled, otherwise - enabled 2931 * 2932 * @return 2933 * 0 on success, a negative error value otherwise 2934 */ 2935 int 2936 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2937 { 2938 struct mlx5_priv *priv = dev->data->dev_private; 2939 2940 return mlx5_nl_promisc(priv->nl_socket_route, 2941 mlx5_ifindex(dev), !!enable); 2942 } 2943 2944 /** 2945 * Set device promiscuous mode 2946 * 2947 * @param dev 2948 * Pointer to Ethernet device structure. 2949 * @param enable 2950 * 0 - all multicase is disabled, otherwise - enabled 2951 * 2952 * @return 2953 * 0 on success, a negative error value otherwise 2954 */ 2955 int 2956 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2957 { 2958 struct mlx5_priv *priv = dev->data->dev_private; 2959 2960 return mlx5_nl_allmulti(priv->nl_socket_route, 2961 mlx5_ifindex(dev), !!enable); 2962 } 2963 2964 /** 2965 * Flush device MAC addresses 2966 * 2967 * @param dev 2968 * Pointer to Ethernet device structure. 2969 * 2970 */ 2971 void 2972 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2973 { 2974 struct mlx5_priv *priv = dev->data->dev_private; 2975 2976 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2977 dev->data->mac_addrs, 2978 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2979 } 2980