1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_qp = attr_ex.orig_attr.max_qp; 120 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 121 device_attr->max_rwq_indirection_table_size = 122 attr_ex.rss_caps.max_rwq_indirection_table_size; 123 device_attr->max_tso = attr_ex.tso_caps.max_tso; 124 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 125 126 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 127 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 128 if (err) 129 return err; 130 131 device_attr->flags = dv_attr.flags; 132 device_attr->comp_mask = dv_attr.comp_mask; 133 #ifdef HAVE_IBV_MLX5_MOD_SWP 134 device_attr->sw_parsing_offloads = 135 dv_attr.sw_parsing_caps.sw_parsing_offloads; 136 #endif 137 device_attr->min_single_stride_log_num_of_bytes = 138 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 139 device_attr->max_single_stride_log_num_of_bytes = 140 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 141 device_attr->min_single_wqe_log_num_of_strides = 142 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 143 device_attr->max_single_wqe_log_num_of_strides = 144 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 145 device_attr->stride_supported_qpts = 146 dv_attr.striding_rq_caps.supported_qpts; 147 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 148 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 149 #endif 150 151 return err; 152 } 153 154 /** 155 * Verbs callback to allocate a memory. This function should allocate the space 156 * according to the size provided residing inside a huge page. 157 * Please note that all allocation must respect the alignment from libmlx5 158 * (i.e. currently rte_mem_page_size()). 159 * 160 * @param[in] size 161 * The size in bytes of the memory to allocate. 162 * @param[in] data 163 * A pointer to the callback data. 164 * 165 * @return 166 * Allocated buffer, NULL otherwise and rte_errno is set. 167 */ 168 static void * 169 mlx5_alloc_verbs_buf(size_t size, void *data) 170 { 171 struct mlx5_priv *priv = data; 172 void *ret; 173 unsigned int socket = SOCKET_ID_ANY; 174 size_t alignment = rte_mem_page_size(); 175 if (alignment == (size_t)-1) { 176 DRV_LOG(ERR, "Failed to get mem page size"); 177 rte_errno = ENOMEM; 178 return NULL; 179 } 180 181 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 182 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 183 184 socket = ctrl->socket; 185 } else if (priv->verbs_alloc_ctx.type == 186 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 187 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 188 189 socket = ctrl->socket; 190 } 191 MLX5_ASSERT(data != NULL); 192 ret = mlx5_malloc(0, size, alignment, socket); 193 if (!ret && size) 194 rte_errno = ENOMEM; 195 return ret; 196 } 197 198 /** 199 * Verbs callback to free a memory. 200 * 201 * @param[in] ptr 202 * A pointer to the memory to free. 203 * @param[in] data 204 * A pointer to the callback data. 205 */ 206 static void 207 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 208 { 209 MLX5_ASSERT(data != NULL); 210 mlx5_free(ptr); 211 } 212 213 /** 214 * Initialize DR related data within private structure. 215 * Routine checks the reference counter and does actual 216 * resources creation/initialization only if counter is zero. 217 * 218 * @param[in] priv 219 * Pointer to the private device data structure. 220 * 221 * @return 222 * Zero on success, positive error code otherwise. 223 */ 224 static int 225 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 226 { 227 struct mlx5_dev_ctx_shared *sh = priv->sh; 228 char s[MLX5_HLIST_NAMESIZE]; 229 int err = 0; 230 231 if (!sh->flow_tbls) 232 err = mlx5_alloc_table_hash_list(priv); 233 else 234 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n", 235 (void *)sh->flow_tbls); 236 if (err) 237 return err; 238 /* Create tags hash list table. */ 239 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 240 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE); 241 if (!sh->tag_table) { 242 DRV_LOG(ERR, "tags with hash creation failed."); 243 err = ENOMEM; 244 goto error; 245 } 246 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 247 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ); 248 if (!sh->modify_cmds) { 249 DRV_LOG(ERR, "hdr modify hash creation failed"); 250 err = ENOMEM; 251 goto error; 252 } 253 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 254 sh->encaps_decaps = mlx5_hlist_create(s, 255 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ); 256 if (!sh->encaps_decaps) { 257 DRV_LOG(ERR, "encap decap hash creation failed"); 258 err = ENOMEM; 259 goto error; 260 } 261 #ifdef HAVE_MLX5DV_DR 262 void *domain; 263 264 if (sh->dv_refcnt) { 265 /* Shared DV/DR structures is already initialized. */ 266 sh->dv_refcnt++; 267 priv->dr_shared = 1; 268 return 0; 269 } 270 /* Reference counter is zero, we should initialize structures. */ 271 domain = mlx5_glue->dr_create_domain(sh->ctx, 272 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 273 if (!domain) { 274 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 275 err = errno; 276 goto error; 277 } 278 sh->rx_domain = domain; 279 domain = mlx5_glue->dr_create_domain(sh->ctx, 280 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 281 if (!domain) { 282 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 283 err = errno; 284 goto error; 285 } 286 pthread_mutex_init(&sh->dv_mutex, NULL); 287 sh->tx_domain = domain; 288 #ifdef HAVE_MLX5DV_DR_ESWITCH 289 if (priv->config.dv_esw_en) { 290 domain = mlx5_glue->dr_create_domain 291 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 292 if (!domain) { 293 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 294 err = errno; 295 goto error; 296 } 297 sh->fdb_domain = domain; 298 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 299 } 300 #endif 301 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 302 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 303 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 304 if (sh->fdb_domain) 305 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 306 } 307 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 308 #endif /* HAVE_MLX5DV_DR */ 309 sh->dv_refcnt++; 310 priv->dr_shared = 1; 311 return 0; 312 error: 313 /* Rollback the created objects. */ 314 if (sh->rx_domain) { 315 mlx5_glue->dr_destroy_domain(sh->rx_domain); 316 sh->rx_domain = NULL; 317 } 318 if (sh->tx_domain) { 319 mlx5_glue->dr_destroy_domain(sh->tx_domain); 320 sh->tx_domain = NULL; 321 } 322 if (sh->fdb_domain) { 323 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 324 sh->fdb_domain = NULL; 325 } 326 if (sh->esw_drop_action) { 327 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 328 sh->esw_drop_action = NULL; 329 } 330 if (sh->pop_vlan_action) { 331 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 332 sh->pop_vlan_action = NULL; 333 } 334 if (sh->encaps_decaps) { 335 mlx5_hlist_destroy(sh->encaps_decaps, NULL, NULL); 336 sh->encaps_decaps = NULL; 337 } 338 if (sh->modify_cmds) { 339 mlx5_hlist_destroy(sh->modify_cmds, NULL, NULL); 340 sh->modify_cmds = NULL; 341 } 342 if (sh->tag_table) { 343 /* tags should be destroyed with flow before. */ 344 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 345 sh->tag_table = NULL; 346 } 347 mlx5_free_table_hash_list(priv); 348 return err; 349 } 350 351 /** 352 * Destroy DR related data within private structure. 353 * 354 * @param[in] priv 355 * Pointer to the private device data structure. 356 */ 357 void 358 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 359 { 360 struct mlx5_dev_ctx_shared *sh; 361 362 if (!priv->dr_shared) 363 return; 364 priv->dr_shared = 0; 365 sh = priv->sh; 366 MLX5_ASSERT(sh); 367 #ifdef HAVE_MLX5DV_DR 368 MLX5_ASSERT(sh->dv_refcnt); 369 if (sh->dv_refcnt && --sh->dv_refcnt) 370 return; 371 if (sh->rx_domain) { 372 mlx5_glue->dr_destroy_domain(sh->rx_domain); 373 sh->rx_domain = NULL; 374 } 375 if (sh->tx_domain) { 376 mlx5_glue->dr_destroy_domain(sh->tx_domain); 377 sh->tx_domain = NULL; 378 } 379 #ifdef HAVE_MLX5DV_DR_ESWITCH 380 if (sh->fdb_domain) { 381 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 382 sh->fdb_domain = NULL; 383 } 384 if (sh->esw_drop_action) { 385 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 386 sh->esw_drop_action = NULL; 387 } 388 #endif 389 if (sh->pop_vlan_action) { 390 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 391 sh->pop_vlan_action = NULL; 392 } 393 pthread_mutex_destroy(&sh->dv_mutex); 394 #endif /* HAVE_MLX5DV_DR */ 395 if (sh->encaps_decaps) { 396 mlx5_hlist_destroy(sh->encaps_decaps, NULL, NULL); 397 sh->encaps_decaps = NULL; 398 } 399 if (sh->modify_cmds) { 400 mlx5_hlist_destroy(sh->modify_cmds, NULL, NULL); 401 sh->modify_cmds = NULL; 402 } 403 if (sh->tag_table) { 404 /* tags should be destroyed with flow before. */ 405 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 406 sh->tag_table = NULL; 407 } 408 mlx5_free_table_hash_list(priv); 409 } 410 411 /** 412 * Initialize shared data between primary and secondary process. 413 * 414 * A memzone is reserved by primary process and secondary processes attach to 415 * the memzone. 416 * 417 * @return 418 * 0 on success, a negative errno value otherwise and rte_errno is set. 419 */ 420 static int 421 mlx5_init_shared_data(void) 422 { 423 const struct rte_memzone *mz; 424 int ret = 0; 425 426 rte_spinlock_lock(&mlx5_shared_data_lock); 427 if (mlx5_shared_data == NULL) { 428 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 429 /* Allocate shared memory. */ 430 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 431 sizeof(*mlx5_shared_data), 432 SOCKET_ID_ANY, 0); 433 if (mz == NULL) { 434 DRV_LOG(ERR, 435 "Cannot allocate mlx5 shared data"); 436 ret = -rte_errno; 437 goto error; 438 } 439 mlx5_shared_data = mz->addr; 440 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 441 rte_spinlock_init(&mlx5_shared_data->lock); 442 } else { 443 /* Lookup allocated shared memory. */ 444 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 445 if (mz == NULL) { 446 DRV_LOG(ERR, 447 "Cannot attach mlx5 shared data"); 448 ret = -rte_errno; 449 goto error; 450 } 451 mlx5_shared_data = mz->addr; 452 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 453 } 454 } 455 error: 456 rte_spinlock_unlock(&mlx5_shared_data_lock); 457 return ret; 458 } 459 460 /** 461 * PMD global initialization. 462 * 463 * Independent from individual device, this function initializes global 464 * per-PMD data structures distinguishing primary and secondary processes. 465 * Hence, each initialization is called once per a process. 466 * 467 * @return 468 * 0 on success, a negative errno value otherwise and rte_errno is set. 469 */ 470 static int 471 mlx5_init_once(void) 472 { 473 struct mlx5_shared_data *sd; 474 struct mlx5_local_data *ld = &mlx5_local_data; 475 int ret = 0; 476 477 if (mlx5_init_shared_data()) 478 return -rte_errno; 479 sd = mlx5_shared_data; 480 MLX5_ASSERT(sd); 481 rte_spinlock_lock(&sd->lock); 482 switch (rte_eal_process_type()) { 483 case RTE_PROC_PRIMARY: 484 if (sd->init_done) 485 break; 486 LIST_INIT(&sd->mem_event_cb_list); 487 rte_rwlock_init(&sd->mem_event_rwlock); 488 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 489 mlx5_mr_mem_event_cb, NULL); 490 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 491 mlx5_mp_os_primary_handle); 492 if (ret) 493 goto out; 494 sd->init_done = true; 495 break; 496 case RTE_PROC_SECONDARY: 497 if (ld->init_done) 498 break; 499 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 500 mlx5_mp_os_secondary_handle); 501 if (ret) 502 goto out; 503 ++sd->secondary_cnt; 504 ld->init_done = true; 505 break; 506 default: 507 break; 508 } 509 out: 510 rte_spinlock_unlock(&sd->lock); 511 return ret; 512 } 513 514 /** 515 * Create the Tx queue DevX/Verbs object. 516 * 517 * @param dev 518 * Pointer to Ethernet device. 519 * @param idx 520 * Queue index in DPDK Tx queue array. 521 * 522 * @return 523 * 0 on success, a negative errno value otherwise and rte_errno is set. 524 */ 525 static int 526 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 527 { 528 struct mlx5_priv *priv = dev->data->dev_private; 529 struct mlx5_dev_config *config = &priv->config; 530 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 531 struct mlx5_txq_ctrl *txq_ctrl = 532 container_of(txq_data, struct mlx5_txq_ctrl, txq); 533 534 /* 535 * When DevX is supported and DV flow is enable, and dest tir is enable, 536 * hairpin functions use DevX API. 537 * When, in addition, DV E-Switch is enable and DevX uar offset is 538 * supported, all Tx functions also use DevX API. 539 * Otherwise, all Tx functions use Verbs API. 540 */ 541 if (config->devx && config->dv_flow_en && config->dest_tir) { 542 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 543 return mlx5_txq_devx_obj_new(dev, idx); 544 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 545 if (config->dv_esw_en) 546 return mlx5_txq_devx_obj_new(dev, idx); 547 #endif 548 } 549 return mlx5_txq_ibv_obj_new(dev, idx); 550 } 551 552 /** 553 * Release an Tx DevX/verbs queue object. 554 * 555 * @param txq_obj 556 * DevX/Verbs Tx queue object. 557 */ 558 static void 559 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 560 { 561 struct mlx5_dev_config *config = &txq_obj->txq_ctrl->priv->config; 562 563 if (config->devx && config->dv_flow_en && config->dest_tir) { 564 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 565 if (config->dv_esw_en) { 566 mlx5_txq_devx_obj_release(txq_obj); 567 return; 568 } 569 #endif 570 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 571 mlx5_txq_devx_obj_release(txq_obj); 572 return; 573 } 574 } 575 mlx5_txq_ibv_obj_release(txq_obj); 576 } 577 578 /** 579 * Spawn an Ethernet device from Verbs information. 580 * 581 * @param dpdk_dev 582 * Backing DPDK device. 583 * @param spawn 584 * Verbs device parameters (name, port, switch_info) to spawn. 585 * @param config 586 * Device configuration parameters. 587 * 588 * @return 589 * A valid Ethernet device object on success, NULL otherwise and rte_errno 590 * is set. The following errors are defined: 591 * 592 * EBUSY: device is not supposed to be spawned. 593 * EEXIST: device is already spawned 594 */ 595 static struct rte_eth_dev * 596 mlx5_dev_spawn(struct rte_device *dpdk_dev, 597 struct mlx5_dev_spawn_data *spawn, 598 struct mlx5_dev_config *config) 599 { 600 const struct mlx5_switch_info *switch_info = &spawn->info; 601 struct mlx5_dev_ctx_shared *sh = NULL; 602 struct ibv_port_attr port_attr; 603 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 604 struct rte_eth_dev *eth_dev = NULL; 605 struct mlx5_priv *priv = NULL; 606 int err = 0; 607 unsigned int hw_padding = 0; 608 unsigned int mps; 609 unsigned int cqe_comp; 610 unsigned int cqe_pad = 0; 611 unsigned int tunnel_en = 0; 612 unsigned int mpls_en = 0; 613 unsigned int swp = 0; 614 unsigned int mprq = 0; 615 unsigned int mprq_min_stride_size_n = 0; 616 unsigned int mprq_max_stride_size_n = 0; 617 unsigned int mprq_min_stride_num_n = 0; 618 unsigned int mprq_max_stride_num_n = 0; 619 struct rte_ether_addr mac; 620 char name[RTE_ETH_NAME_MAX_LEN]; 621 int own_domain_id = 0; 622 uint16_t port_id; 623 unsigned int i; 624 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 625 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 626 #endif 627 628 /* Determine if this port representor is supposed to be spawned. */ 629 if (switch_info->representor && dpdk_dev->devargs) { 630 struct rte_eth_devargs eth_da; 631 632 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 633 if (err) { 634 rte_errno = -err; 635 DRV_LOG(ERR, "failed to process device arguments: %s", 636 strerror(rte_errno)); 637 return NULL; 638 } 639 for (i = 0; i < eth_da.nb_representor_ports; ++i) 640 if (eth_da.representor_ports[i] == 641 (uint16_t)switch_info->port_name) 642 break; 643 if (i == eth_da.nb_representor_ports) { 644 rte_errno = EBUSY; 645 return NULL; 646 } 647 } 648 /* Build device name. */ 649 if (spawn->pf_bond < 0) { 650 /* Single device. */ 651 if (!switch_info->representor) 652 strlcpy(name, dpdk_dev->name, sizeof(name)); 653 else 654 snprintf(name, sizeof(name), "%s_representor_%u", 655 dpdk_dev->name, switch_info->port_name); 656 } else { 657 /* Bonding device. */ 658 if (!switch_info->representor) 659 snprintf(name, sizeof(name), "%s_%s", 660 dpdk_dev->name, 661 mlx5_os_get_dev_device_name(spawn->phys_dev)); 662 else 663 snprintf(name, sizeof(name), "%s_%s_representor_%u", 664 dpdk_dev->name, 665 mlx5_os_get_dev_device_name(spawn->phys_dev), 666 switch_info->port_name); 667 } 668 /* check if the device is already spawned */ 669 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 670 rte_errno = EEXIST; 671 return NULL; 672 } 673 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 674 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 675 struct mlx5_mp_id mp_id; 676 677 eth_dev = rte_eth_dev_attach_secondary(name); 678 if (eth_dev == NULL) { 679 DRV_LOG(ERR, "can not attach rte ethdev"); 680 rte_errno = ENOMEM; 681 return NULL; 682 } 683 eth_dev->device = dpdk_dev; 684 eth_dev->dev_ops = &mlx5_os_dev_sec_ops; 685 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 686 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 687 err = mlx5_proc_priv_init(eth_dev); 688 if (err) 689 return NULL; 690 mp_id.port_id = eth_dev->data->port_id; 691 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 692 /* Receive command fd from primary process */ 693 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 694 if (err < 0) 695 goto err_secondary; 696 /* Remap UAR for Tx queues. */ 697 err = mlx5_tx_uar_init_secondary(eth_dev, err); 698 if (err) 699 goto err_secondary; 700 /* 701 * Ethdev pointer is still required as input since 702 * the primary device is not accessible from the 703 * secondary process. 704 */ 705 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 706 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 707 return eth_dev; 708 err_secondary: 709 mlx5_dev_close(eth_dev); 710 return NULL; 711 } 712 /* 713 * Some parameters ("tx_db_nc" in particularly) are needed in 714 * advance to create dv/verbs device context. We proceed the 715 * devargs here to get ones, and later proceed devargs again 716 * to override some hardware settings. 717 */ 718 err = mlx5_args(config, dpdk_dev->devargs); 719 if (err) { 720 err = rte_errno; 721 DRV_LOG(ERR, "failed to process device arguments: %s", 722 strerror(rte_errno)); 723 goto error; 724 } 725 mlx5_malloc_mem_select(config->sys_mem_en); 726 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 727 if (!sh) 728 return NULL; 729 config->devx = sh->devx; 730 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 731 config->dest_tir = 1; 732 #endif 733 #ifdef HAVE_IBV_MLX5_MOD_SWP 734 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 735 #endif 736 /* 737 * Multi-packet send is supported by ConnectX-4 Lx PF as well 738 * as all ConnectX-5 devices. 739 */ 740 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 741 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 742 #endif 743 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 744 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 745 #endif 746 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 747 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 748 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 749 DRV_LOG(DEBUG, "enhanced MPW is supported"); 750 mps = MLX5_MPW_ENHANCED; 751 } else { 752 DRV_LOG(DEBUG, "MPW is supported"); 753 mps = MLX5_MPW; 754 } 755 } else { 756 DRV_LOG(DEBUG, "MPW isn't supported"); 757 mps = MLX5_MPW_DISABLED; 758 } 759 #ifdef HAVE_IBV_MLX5_MOD_SWP 760 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 761 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 762 DRV_LOG(DEBUG, "SWP support: %u", swp); 763 #endif 764 config->swp = !!swp; 765 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 766 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 767 struct mlx5dv_striding_rq_caps mprq_caps = 768 dv_attr.striding_rq_caps; 769 770 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 771 mprq_caps.min_single_stride_log_num_of_bytes); 772 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 773 mprq_caps.max_single_stride_log_num_of_bytes); 774 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 775 mprq_caps.min_single_wqe_log_num_of_strides); 776 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 777 mprq_caps.max_single_wqe_log_num_of_strides); 778 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 779 mprq_caps.supported_qpts); 780 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 781 mprq = 1; 782 mprq_min_stride_size_n = 783 mprq_caps.min_single_stride_log_num_of_bytes; 784 mprq_max_stride_size_n = 785 mprq_caps.max_single_stride_log_num_of_bytes; 786 mprq_min_stride_num_n = 787 mprq_caps.min_single_wqe_log_num_of_strides; 788 mprq_max_stride_num_n = 789 mprq_caps.max_single_wqe_log_num_of_strides; 790 } 791 #endif 792 if (RTE_CACHE_LINE_SIZE == 128 && 793 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 794 cqe_comp = 0; 795 else 796 cqe_comp = 1; 797 config->cqe_comp = cqe_comp; 798 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 799 /* Whether device supports 128B Rx CQE padding. */ 800 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 801 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 802 #endif 803 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 804 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 805 tunnel_en = ((dv_attr.tunnel_offloads_caps & 806 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 807 (dv_attr.tunnel_offloads_caps & 808 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 809 (dv_attr.tunnel_offloads_caps & 810 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 811 } 812 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 813 tunnel_en ? "" : "not "); 814 #else 815 DRV_LOG(WARNING, 816 "tunnel offloading disabled due to old OFED/rdma-core version"); 817 #endif 818 config->tunnel_en = tunnel_en; 819 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 820 mpls_en = ((dv_attr.tunnel_offloads_caps & 821 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 822 (dv_attr.tunnel_offloads_caps & 823 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 824 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 825 mpls_en ? "" : "not "); 826 #else 827 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 828 " old OFED/rdma-core version or firmware configuration"); 829 #endif 830 config->mpls_en = mpls_en; 831 /* Check port status. */ 832 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 833 if (err) { 834 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 835 goto error; 836 } 837 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 838 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 839 err = EINVAL; 840 goto error; 841 } 842 if (port_attr.state != IBV_PORT_ACTIVE) 843 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 844 mlx5_glue->port_state_str(port_attr.state), 845 port_attr.state); 846 /* Allocate private eth device data. */ 847 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 848 sizeof(*priv), 849 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 850 if (priv == NULL) { 851 DRV_LOG(ERR, "priv allocation failure"); 852 err = ENOMEM; 853 goto error; 854 } 855 priv->sh = sh; 856 priv->dev_port = spawn->phys_port; 857 priv->pci_dev = spawn->pci_dev; 858 priv->mtu = RTE_ETHER_MTU; 859 priv->mp_id.port_id = port_id; 860 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 861 /* Some internal functions rely on Netlink sockets, open them now. */ 862 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 863 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 864 priv->representor = !!switch_info->representor; 865 priv->master = !!switch_info->master; 866 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 867 priv->vport_meta_tag = 0; 868 priv->vport_meta_mask = 0; 869 priv->pf_bond = spawn->pf_bond; 870 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 871 /* 872 * The DevX port query API is implemented. E-Switch may use 873 * either vport or reg_c[0] metadata register to match on 874 * vport index. The engaged part of metadata register is 875 * defined by mask. 876 */ 877 if (switch_info->representor || switch_info->master) { 878 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 879 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 880 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 881 &devx_port); 882 if (err) { 883 DRV_LOG(WARNING, 884 "can't query devx port %d on device %s", 885 spawn->phys_port, 886 mlx5_os_get_dev_device_name(spawn->phys_dev)); 887 devx_port.comp_mask = 0; 888 } 889 } 890 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 891 priv->vport_meta_tag = devx_port.reg_c_0.value; 892 priv->vport_meta_mask = devx_port.reg_c_0.mask; 893 if (!priv->vport_meta_mask) { 894 DRV_LOG(ERR, "vport zero mask for port %d" 895 " on bonding device %s", 896 spawn->phys_port, 897 mlx5_os_get_dev_device_name 898 (spawn->phys_dev)); 899 err = ENOTSUP; 900 goto error; 901 } 902 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 903 DRV_LOG(ERR, "invalid vport tag for port %d" 904 " on bonding device %s", 905 spawn->phys_port, 906 mlx5_os_get_dev_device_name 907 (spawn->phys_dev)); 908 err = ENOTSUP; 909 goto error; 910 } 911 } 912 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 913 priv->vport_id = devx_port.vport_num; 914 } else if (spawn->pf_bond >= 0) { 915 DRV_LOG(ERR, "can't deduce vport index for port %d" 916 " on bonding device %s", 917 spawn->phys_port, 918 mlx5_os_get_dev_device_name(spawn->phys_dev)); 919 err = ENOTSUP; 920 goto error; 921 } else { 922 /* Suppose vport index in compatible way. */ 923 priv->vport_id = switch_info->representor ? 924 switch_info->port_name + 1 : -1; 925 } 926 #else 927 /* 928 * Kernel/rdma_core support single E-Switch per PF configurations 929 * only and vport_id field contains the vport index for 930 * associated VF, which is deduced from representor port name. 931 * For example, let's have the IB device port 10, it has 932 * attached network device eth0, which has port name attribute 933 * pf0vf2, we can deduce the VF number as 2, and set vport index 934 * as 3 (2+1). This assigning schema should be changed if the 935 * multiple E-Switch instances per PF configurations or/and PCI 936 * subfunctions are added. 937 */ 938 priv->vport_id = switch_info->representor ? 939 switch_info->port_name + 1 : -1; 940 #endif 941 /* representor_id field keeps the unmodified VF index. */ 942 priv->representor_id = switch_info->representor ? 943 switch_info->port_name : -1; 944 /* 945 * Look for sibling devices in order to reuse their switch domain 946 * if any, otherwise allocate one. 947 */ 948 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 949 const struct mlx5_priv *opriv = 950 rte_eth_devices[port_id].data->dev_private; 951 952 if (!opriv || 953 opriv->sh != priv->sh || 954 opriv->domain_id == 955 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 956 continue; 957 priv->domain_id = opriv->domain_id; 958 break; 959 } 960 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 961 err = rte_eth_switch_domain_alloc(&priv->domain_id); 962 if (err) { 963 err = rte_errno; 964 DRV_LOG(ERR, "unable to allocate switch domain: %s", 965 strerror(rte_errno)); 966 goto error; 967 } 968 own_domain_id = 1; 969 } 970 /* Override some values set by hardware configuration. */ 971 mlx5_args(config, dpdk_dev->devargs); 972 err = mlx5_dev_check_sibling_config(priv, config); 973 if (err) 974 goto error; 975 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 976 IBV_DEVICE_RAW_IP_CSUM); 977 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 978 (config->hw_csum ? "" : "not ")); 979 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 980 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 981 DRV_LOG(DEBUG, "counters are not supported"); 982 #endif 983 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 984 if (config->dv_flow_en) { 985 DRV_LOG(WARNING, "DV flow is not supported"); 986 config->dv_flow_en = 0; 987 } 988 #endif 989 config->ind_table_max_size = 990 sh->device_attr.max_rwq_indirection_table_size; 991 /* 992 * Remove this check once DPDK supports larger/variable 993 * indirection tables. 994 */ 995 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 996 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 997 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 998 config->ind_table_max_size); 999 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1000 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1001 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1002 (config->hw_vlan_strip ? "" : "not ")); 1003 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1004 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1005 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1006 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1007 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1008 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1009 IBV_DEVICE_PCI_WRITE_END_PADDING); 1010 #endif 1011 if (config->hw_padding && !hw_padding) { 1012 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1013 config->hw_padding = 0; 1014 } else if (config->hw_padding) { 1015 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1016 } 1017 config->tso = (sh->device_attr.max_tso > 0 && 1018 (sh->device_attr.tso_supported_qpts & 1019 (1 << IBV_QPT_RAW_PACKET))); 1020 if (config->tso) 1021 config->tso_max_payload_sz = sh->device_attr.max_tso; 1022 /* 1023 * MPW is disabled by default, while the Enhanced MPW is enabled 1024 * by default. 1025 */ 1026 if (config->mps == MLX5_ARG_UNSET) 1027 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1028 MLX5_MPW_DISABLED; 1029 else 1030 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1031 DRV_LOG(INFO, "%sMPS is %s", 1032 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1033 config->mps == MLX5_MPW ? "legacy " : "", 1034 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1035 if (config->cqe_comp && !cqe_comp) { 1036 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1037 config->cqe_comp = 0; 1038 } 1039 if (config->cqe_pad && !cqe_pad) { 1040 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1041 config->cqe_pad = 0; 1042 } else if (config->cqe_pad) { 1043 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1044 } 1045 if (config->devx) { 1046 priv->counter_fallback = 0; 1047 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1048 if (err) { 1049 err = -err; 1050 goto error; 1051 } 1052 if (!config->hca_attr.flow_counters_dump) 1053 priv->counter_fallback = 1; 1054 #ifndef HAVE_IBV_DEVX_ASYNC 1055 priv->counter_fallback = 1; 1056 #endif 1057 if (priv->counter_fallback) 1058 DRV_LOG(INFO, "Use fall-back DV counter management"); 1059 /* Check for LRO support. */ 1060 if (config->dest_tir && config->hca_attr.lro_cap && 1061 config->dv_flow_en) { 1062 /* TBD check tunnel lro caps. */ 1063 config->lro.supported = config->hca_attr.lro_cap; 1064 DRV_LOG(DEBUG, "Device supports LRO"); 1065 /* 1066 * If LRO timeout is not configured by application, 1067 * use the minimal supported value. 1068 */ 1069 if (!config->lro.timeout) 1070 config->lro.timeout = 1071 config->hca_attr.lro_timer_supported_periods[0]; 1072 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1073 config->lro.timeout); 1074 } 1075 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1076 if (config->hca_attr.qos.sup && 1077 config->hca_attr.qos.srtcm_sup && 1078 config->dv_flow_en) { 1079 uint8_t reg_c_mask = 1080 config->hca_attr.qos.flow_meter_reg_c_ids; 1081 /* 1082 * Meter needs two REG_C's for color match and pre-sfx 1083 * flow match. Here get the REG_C for color match. 1084 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1085 */ 1086 reg_c_mask &= 0xfc; 1087 if (__builtin_popcount(reg_c_mask) < 1) { 1088 priv->mtr_en = 0; 1089 DRV_LOG(WARNING, "No available register for" 1090 " meter."); 1091 } else { 1092 priv->mtr_color_reg = ffs(reg_c_mask) - 1 + 1093 REG_C_0; 1094 priv->mtr_en = 1; 1095 priv->mtr_reg_share = 1096 config->hca_attr.qos.flow_meter_reg_share; 1097 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1098 priv->mtr_color_reg); 1099 } 1100 } 1101 #endif 1102 } 1103 if (config->tx_pp) { 1104 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1105 config->hca_attr.dev_freq_khz); 1106 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1107 config->hca_attr.qos.packet_pacing ? "" : "not "); 1108 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1109 config->hca_attr.cross_channel ? "" : "not "); 1110 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1111 config->hca_attr.wqe_index_ignore ? "" : "not "); 1112 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1113 config->hca_attr.non_wire_sq ? "" : "not "); 1114 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1115 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1116 config->hca_attr.log_max_static_sq_wq); 1117 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1118 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1119 if (!config->devx) { 1120 DRV_LOG(ERR, "DevX is required for packet pacing"); 1121 err = ENODEV; 1122 goto error; 1123 } 1124 if (!config->hca_attr.qos.packet_pacing) { 1125 DRV_LOG(ERR, "Packet pacing is not supported"); 1126 err = ENODEV; 1127 goto error; 1128 } 1129 if (!config->hca_attr.cross_channel) { 1130 DRV_LOG(ERR, "Cross channel operations are" 1131 " required for packet pacing"); 1132 err = ENODEV; 1133 goto error; 1134 } 1135 if (!config->hca_attr.wqe_index_ignore) { 1136 DRV_LOG(ERR, "WQE index ignore feature is" 1137 " required for packet pacing"); 1138 err = ENODEV; 1139 goto error; 1140 } 1141 if (!config->hca_attr.non_wire_sq) { 1142 DRV_LOG(ERR, "Non-wire SQ feature is" 1143 " required for packet pacing"); 1144 err = ENODEV; 1145 goto error; 1146 } 1147 if (!config->hca_attr.log_max_static_sq_wq) { 1148 DRV_LOG(ERR, "Static WQE SQ feature is" 1149 " required for packet pacing"); 1150 err = ENODEV; 1151 goto error; 1152 } 1153 if (!config->hca_attr.qos.wqe_rate_pp) { 1154 DRV_LOG(ERR, "WQE rate mode is required" 1155 " for packet pacing"); 1156 err = ENODEV; 1157 goto error; 1158 } 1159 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1160 DRV_LOG(ERR, "DevX does not provide UAR offset," 1161 " can't create queues for packet pacing"); 1162 err = ENODEV; 1163 goto error; 1164 #endif 1165 } 1166 if (config->devx) { 1167 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1168 1169 err = config->hca_attr.access_register_user ? 1170 mlx5_devx_cmd_register_read 1171 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1172 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1173 if (!err) { 1174 uint32_t ts_mode; 1175 1176 /* MTUTC register is read successfully. */ 1177 ts_mode = MLX5_GET(register_mtutc, reg, 1178 time_stamp_mode); 1179 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1180 config->rt_timestamp = 1; 1181 } else { 1182 /* Kernel does not support register reading. */ 1183 if (config->hca_attr.dev_freq_khz == 1184 (NS_PER_S / MS_PER_S)) 1185 config->rt_timestamp = 1; 1186 } 1187 } 1188 /* 1189 * If HW has bug working with tunnel packet decapsulation and 1190 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1191 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1192 */ 1193 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1194 config->hw_fcs_strip = 0; 1195 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1196 (config->hw_fcs_strip ? "" : "not ")); 1197 if (config->mprq.enabled && mprq) { 1198 if (config->mprq.stride_num_n && 1199 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1200 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1201 config->mprq.stride_num_n = 1202 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1203 mprq_min_stride_num_n), 1204 mprq_max_stride_num_n); 1205 DRV_LOG(WARNING, 1206 "the number of strides" 1207 " for Multi-Packet RQ is out of range," 1208 " setting default value (%u)", 1209 1 << config->mprq.stride_num_n); 1210 } 1211 if (config->mprq.stride_size_n && 1212 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1213 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1214 config->mprq.stride_size_n = 1215 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1216 mprq_min_stride_size_n), 1217 mprq_max_stride_size_n); 1218 DRV_LOG(WARNING, 1219 "the size of a stride" 1220 " for Multi-Packet RQ is out of range," 1221 " setting default value (%u)", 1222 1 << config->mprq.stride_size_n); 1223 } 1224 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1225 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1226 } else if (config->mprq.enabled && !mprq) { 1227 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1228 config->mprq.enabled = 0; 1229 } 1230 if (config->max_dump_files_num == 0) 1231 config->max_dump_files_num = 128; 1232 eth_dev = rte_eth_dev_allocate(name); 1233 if (eth_dev == NULL) { 1234 DRV_LOG(ERR, "can not allocate rte ethdev"); 1235 err = ENOMEM; 1236 goto error; 1237 } 1238 if (priv->representor) { 1239 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1240 eth_dev->data->representor_id = priv->representor_id; 1241 } 1242 /* 1243 * Store associated network device interface index. This index 1244 * is permanent throughout the lifetime of device. So, we may store 1245 * the ifindex here and use the cached value further. 1246 */ 1247 MLX5_ASSERT(spawn->ifindex); 1248 priv->if_index = spawn->ifindex; 1249 if (priv->pf_bond >= 0 && priv->master) { 1250 /* Get bond interface info */ 1251 err = mlx5_sysfs_bond_info(priv->if_index, 1252 &priv->bond_ifindex, 1253 priv->bond_name); 1254 if (err) 1255 DRV_LOG(ERR, "unable to get bond info: %s", 1256 strerror(rte_errno)); 1257 else 1258 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1259 priv->if_index, priv->bond_ifindex, 1260 priv->bond_name); 1261 } 1262 eth_dev->data->dev_private = priv; 1263 priv->dev_data = eth_dev->data; 1264 eth_dev->data->mac_addrs = priv->mac; 1265 eth_dev->device = dpdk_dev; 1266 /* Configure the first MAC address by default. */ 1267 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1268 DRV_LOG(ERR, 1269 "port %u cannot get MAC address, is mlx5_en" 1270 " loaded? (errno: %s)", 1271 eth_dev->data->port_id, strerror(rte_errno)); 1272 err = ENODEV; 1273 goto error; 1274 } 1275 DRV_LOG(INFO, 1276 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1277 eth_dev->data->port_id, 1278 mac.addr_bytes[0], mac.addr_bytes[1], 1279 mac.addr_bytes[2], mac.addr_bytes[3], 1280 mac.addr_bytes[4], mac.addr_bytes[5]); 1281 #ifdef RTE_LIBRTE_MLX5_DEBUG 1282 { 1283 char ifname[IF_NAMESIZE]; 1284 1285 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1286 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1287 eth_dev->data->port_id, ifname); 1288 else 1289 DRV_LOG(DEBUG, "port %u ifname is unknown", 1290 eth_dev->data->port_id); 1291 } 1292 #endif 1293 /* Get actual MTU if possible. */ 1294 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1295 if (err) { 1296 err = rte_errno; 1297 goto error; 1298 } 1299 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1300 priv->mtu); 1301 /* Initialize burst functions to prevent crashes before link-up. */ 1302 eth_dev->rx_pkt_burst = removed_rx_burst; 1303 eth_dev->tx_pkt_burst = removed_tx_burst; 1304 eth_dev->dev_ops = &mlx5_os_dev_ops; 1305 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1306 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1307 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1308 /* Register MAC address. */ 1309 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1310 if (config->vf && config->vf_nl_en) 1311 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1312 mlx5_ifindex(eth_dev), 1313 eth_dev->data->mac_addrs, 1314 MLX5_MAX_MAC_ADDRESSES); 1315 priv->flows = 0; 1316 priv->ctrl_flows = 0; 1317 TAILQ_INIT(&priv->flow_meters); 1318 TAILQ_INIT(&priv->flow_meter_profiles); 1319 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1320 mlx5_glue->dv_set_context_attr(sh->ctx, 1321 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1322 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1323 .alloc = &mlx5_alloc_verbs_buf, 1324 .free = &mlx5_free_verbs_buf, 1325 .data = priv, 1326 })); 1327 /* Bring Ethernet device up. */ 1328 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1329 eth_dev->data->port_id); 1330 mlx5_set_link_up(eth_dev); 1331 /* 1332 * Even though the interrupt handler is not installed yet, 1333 * interrupts will still trigger on the async_fd from 1334 * Verbs context returned by ibv_open_device(). 1335 */ 1336 mlx5_link_update(eth_dev, 0); 1337 #ifdef HAVE_MLX5DV_DR_ESWITCH 1338 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1339 (switch_info->representor || switch_info->master))) 1340 config->dv_esw_en = 0; 1341 #else 1342 config->dv_esw_en = 0; 1343 #endif 1344 /* Detect minimal data bytes to inline. */ 1345 mlx5_set_min_inline(spawn, config); 1346 /* Store device configuration on private structure. */ 1347 priv->config = *config; 1348 /* Create context for virtual machine VLAN workaround. */ 1349 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1350 if (config->dv_flow_en) { 1351 err = mlx5_alloc_shared_dr(priv); 1352 if (err) 1353 goto error; 1354 /* 1355 * RSS id is shared with meter flow id. Meter flow id can only 1356 * use the 24 MSB of the register. 1357 */ 1358 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >> 1359 MLX5_MTR_COLOR_BITS); 1360 if (!priv->qrss_id_pool) { 1361 DRV_LOG(ERR, "can't create flow id pool"); 1362 err = ENOMEM; 1363 goto error; 1364 } 1365 } 1366 /* 1367 * Initialize the dev_ops structure with DevX/Verbs function pointers. 1368 * When DevX is supported and both DV flow and dest tir are enabled, all 1369 * Rx functions use DevX API (except for drop that has not yet been 1370 * implemented in DevX). 1371 */ 1372 if (config->devx && config->dv_flow_en && config->dest_tir) { 1373 priv->obj_ops = devx_obj_ops; 1374 priv->obj_ops.drop_action_create = 1375 ibv_obj_ops.drop_action_create; 1376 priv->obj_ops.drop_action_destroy = 1377 ibv_obj_ops.drop_action_destroy; 1378 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1379 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1380 #else 1381 if (!config->dv_esw_en) 1382 priv->obj_ops.txq_obj_modify = 1383 ibv_obj_ops.txq_obj_modify; 1384 #endif 1385 } else { 1386 priv->obj_ops = ibv_obj_ops; 1387 } 1388 /* The Tx objects are managed by a specific linux wrapper functions. */ 1389 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1390 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1391 /* Supported Verbs flow priority number detection. */ 1392 err = mlx5_flow_discover_priorities(eth_dev); 1393 if (err < 0) { 1394 err = -err; 1395 goto error; 1396 } 1397 priv->config.flow_prio = err; 1398 if (!priv->config.dv_esw_en && 1399 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1400 DRV_LOG(WARNING, "metadata mode %u is not supported " 1401 "(no E-Switch)", priv->config.dv_xmeta_en); 1402 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1403 } 1404 mlx5_set_metadata_mask(eth_dev); 1405 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1406 !priv->sh->dv_regc0_mask) { 1407 DRV_LOG(ERR, "metadata mode %u is not supported " 1408 "(no metadata reg_c[0] is available)", 1409 priv->config.dv_xmeta_en); 1410 err = ENOTSUP; 1411 goto error; 1412 } 1413 /* 1414 * Allocate the buffer for flow creating, just once. 1415 * The allocation must be done before any flow creating. 1416 */ 1417 mlx5_flow_alloc_intermediate(eth_dev); 1418 /* Query availability of metadata reg_c's. */ 1419 err = mlx5_flow_discover_mreg_c(eth_dev); 1420 if (err < 0) { 1421 err = -err; 1422 goto error; 1423 } 1424 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1425 DRV_LOG(DEBUG, 1426 "port %u extensive metadata register is not supported", 1427 eth_dev->data->port_id); 1428 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1429 DRV_LOG(ERR, "metadata mode %u is not supported " 1430 "(no metadata registers available)", 1431 priv->config.dv_xmeta_en); 1432 err = ENOTSUP; 1433 goto error; 1434 } 1435 } 1436 if (priv->config.dv_flow_en && 1437 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1438 mlx5_flow_ext_mreg_supported(eth_dev) && 1439 priv->sh->dv_regc0_mask) { 1440 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1441 MLX5_FLOW_MREG_HTABLE_SZ); 1442 if (!priv->mreg_cp_tbl) { 1443 err = ENOMEM; 1444 goto error; 1445 } 1446 } 1447 return eth_dev; 1448 error: 1449 if (priv) { 1450 if (priv->mreg_cp_tbl) 1451 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL); 1452 if (priv->sh) 1453 mlx5_os_free_shared_dr(priv); 1454 if (priv->nl_socket_route >= 0) 1455 close(priv->nl_socket_route); 1456 if (priv->nl_socket_rdma >= 0) 1457 close(priv->nl_socket_rdma); 1458 if (priv->vmwa_context) 1459 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1460 if (priv->qrss_id_pool) 1461 mlx5_flow_id_pool_release(priv->qrss_id_pool); 1462 if (own_domain_id) 1463 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1464 mlx5_free(priv); 1465 if (eth_dev != NULL) 1466 eth_dev->data->dev_private = NULL; 1467 } 1468 if (eth_dev != NULL) { 1469 /* mac_addrs must not be freed alone because part of 1470 * dev_private 1471 **/ 1472 eth_dev->data->mac_addrs = NULL; 1473 rte_eth_dev_release_port(eth_dev); 1474 } 1475 if (sh) 1476 mlx5_free_shared_dev_ctx(sh); 1477 MLX5_ASSERT(err > 0); 1478 rte_errno = err; 1479 return NULL; 1480 } 1481 1482 /** 1483 * Comparison callback to sort device data. 1484 * 1485 * This is meant to be used with qsort(). 1486 * 1487 * @param a[in] 1488 * Pointer to pointer to first data object. 1489 * @param b[in] 1490 * Pointer to pointer to second data object. 1491 * 1492 * @return 1493 * 0 if both objects are equal, less than 0 if the first argument is less 1494 * than the second, greater than 0 otherwise. 1495 */ 1496 static int 1497 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1498 { 1499 const struct mlx5_switch_info *si_a = 1500 &((const struct mlx5_dev_spawn_data *)a)->info; 1501 const struct mlx5_switch_info *si_b = 1502 &((const struct mlx5_dev_spawn_data *)b)->info; 1503 int ret; 1504 1505 /* Master device first. */ 1506 ret = si_b->master - si_a->master; 1507 if (ret) 1508 return ret; 1509 /* Then representor devices. */ 1510 ret = si_b->representor - si_a->representor; 1511 if (ret) 1512 return ret; 1513 /* Unidentified devices come last in no specific order. */ 1514 if (!si_a->representor) 1515 return 0; 1516 /* Order representors by name. */ 1517 return si_a->port_name - si_b->port_name; 1518 } 1519 1520 /** 1521 * Match PCI information for possible slaves of bonding device. 1522 * 1523 * @param[in] ibv_dev 1524 * Pointer to Infiniband device structure. 1525 * @param[in] pci_dev 1526 * Pointer to PCI device structure to match PCI address. 1527 * @param[in] nl_rdma 1528 * Netlink RDMA group socket handle. 1529 * 1530 * @return 1531 * negative value if no bonding device found, otherwise 1532 * positive index of slave PF in bonding. 1533 */ 1534 static int 1535 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1536 const struct rte_pci_device *pci_dev, 1537 int nl_rdma) 1538 { 1539 char ifname[IF_NAMESIZE + 1]; 1540 unsigned int ifindex; 1541 unsigned int np, i; 1542 FILE *file = NULL; 1543 int pf = -1; 1544 1545 /* 1546 * Try to get master device name. If something goes 1547 * wrong suppose the lack of kernel support and no 1548 * bonding devices. 1549 */ 1550 if (nl_rdma < 0) 1551 return -1; 1552 if (!strstr(ibv_dev->name, "bond")) 1553 return -1; 1554 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1555 if (!np) 1556 return -1; 1557 /* 1558 * The Master device might not be on the predefined 1559 * port (not on port index 1, it is not garanted), 1560 * we have to scan all Infiniband device port and 1561 * find master. 1562 */ 1563 for (i = 1; i <= np; ++i) { 1564 /* Check whether Infiniband port is populated. */ 1565 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1566 if (!ifindex) 1567 continue; 1568 if (!if_indextoname(ifindex, ifname)) 1569 continue; 1570 /* Try to read bonding slave names from sysfs. */ 1571 MKSTR(slaves, 1572 "/sys/class/net/%s/master/bonding/slaves", ifname); 1573 file = fopen(slaves, "r"); 1574 if (file) 1575 break; 1576 } 1577 if (!file) 1578 return -1; 1579 /* Use safe format to check maximal buffer length. */ 1580 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1581 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1582 char tmp_str[IF_NAMESIZE + 32]; 1583 struct rte_pci_addr pci_addr; 1584 struct mlx5_switch_info info; 1585 1586 /* Process slave interface names in the loop. */ 1587 snprintf(tmp_str, sizeof(tmp_str), 1588 "/sys/class/net/%s", ifname); 1589 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1590 DRV_LOG(WARNING, "can not get PCI address" 1591 " for netdev \"%s\"", ifname); 1592 continue; 1593 } 1594 if (pci_dev->addr.domain != pci_addr.domain || 1595 pci_dev->addr.bus != pci_addr.bus || 1596 pci_dev->addr.devid != pci_addr.devid || 1597 pci_dev->addr.function != pci_addr.function) 1598 continue; 1599 /* Slave interface PCI address match found. */ 1600 fclose(file); 1601 snprintf(tmp_str, sizeof(tmp_str), 1602 "/sys/class/net/%s/phys_port_name", ifname); 1603 file = fopen(tmp_str, "rb"); 1604 if (!file) 1605 break; 1606 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1607 if (fscanf(file, "%32s", tmp_str) == 1) 1608 mlx5_translate_port_name(tmp_str, &info); 1609 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 1610 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1611 pf = info.port_name; 1612 break; 1613 } 1614 if (file) 1615 fclose(file); 1616 return pf; 1617 } 1618 1619 /** 1620 * DPDK callback to register a PCI device. 1621 * 1622 * This function spawns Ethernet devices out of a given PCI device. 1623 * 1624 * @param[in] pci_drv 1625 * PCI driver structure (mlx5_driver). 1626 * @param[in] pci_dev 1627 * PCI device information. 1628 * 1629 * @return 1630 * 0 on success, a negative errno value otherwise and rte_errno is set. 1631 */ 1632 int 1633 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1634 struct rte_pci_device *pci_dev) 1635 { 1636 struct ibv_device **ibv_list; 1637 /* 1638 * Number of found IB Devices matching with requested PCI BDF. 1639 * nd != 1 means there are multiple IB devices over the same 1640 * PCI device and we have representors and master. 1641 */ 1642 unsigned int nd = 0; 1643 /* 1644 * Number of found IB device Ports. nd = 1 and np = 1..n means 1645 * we have the single multiport IB device, and there may be 1646 * representors attached to some of found ports. 1647 */ 1648 unsigned int np = 0; 1649 /* 1650 * Number of DPDK ethernet devices to Spawn - either over 1651 * multiple IB devices or multiple ports of single IB device. 1652 * Actually this is the number of iterations to spawn. 1653 */ 1654 unsigned int ns = 0; 1655 /* 1656 * Bonding device 1657 * < 0 - no bonding device (single one) 1658 * >= 0 - bonding device (value is slave PF index) 1659 */ 1660 int bd = -1; 1661 struct mlx5_dev_spawn_data *list = NULL; 1662 struct mlx5_dev_config dev_config; 1663 unsigned int dev_config_vf; 1664 int ret; 1665 1666 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1667 mlx5_pmd_socket_init(); 1668 ret = mlx5_init_once(); 1669 if (ret) { 1670 DRV_LOG(ERR, "unable to init PMD global data: %s", 1671 strerror(rte_errno)); 1672 return -rte_errno; 1673 } 1674 errno = 0; 1675 ibv_list = mlx5_glue->get_device_list(&ret); 1676 if (!ibv_list) { 1677 rte_errno = errno ? errno : ENOSYS; 1678 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1679 return -rte_errno; 1680 } 1681 /* 1682 * First scan the list of all Infiniband devices to find 1683 * matching ones, gathering into the list. 1684 */ 1685 struct ibv_device *ibv_match[ret + 1]; 1686 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1687 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1688 unsigned int i; 1689 1690 while (ret-- > 0) { 1691 struct rte_pci_addr pci_addr; 1692 1693 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1694 bd = mlx5_device_bond_pci_match 1695 (ibv_list[ret], pci_dev, nl_rdma); 1696 if (bd >= 0) { 1697 /* 1698 * Bonding device detected. Only one match is allowed, 1699 * the bonding is supported over multi-port IB device, 1700 * there should be no matches on representor PCI 1701 * functions or non VF LAG bonding devices with 1702 * specified address. 1703 */ 1704 if (nd) { 1705 DRV_LOG(ERR, 1706 "multiple PCI match on bonding device" 1707 "\"%s\" found", ibv_list[ret]->name); 1708 rte_errno = ENOENT; 1709 ret = -rte_errno; 1710 goto exit; 1711 } 1712 DRV_LOG(INFO, "PCI information matches for" 1713 " slave %d bonding device \"%s\"", 1714 bd, ibv_list[ret]->name); 1715 ibv_match[nd++] = ibv_list[ret]; 1716 break; 1717 } 1718 if (mlx5_dev_to_pci_addr 1719 (ibv_list[ret]->ibdev_path, &pci_addr)) 1720 continue; 1721 if (pci_dev->addr.domain != pci_addr.domain || 1722 pci_dev->addr.bus != pci_addr.bus || 1723 pci_dev->addr.devid != pci_addr.devid || 1724 pci_dev->addr.function != pci_addr.function) 1725 continue; 1726 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1727 ibv_list[ret]->name); 1728 ibv_match[nd++] = ibv_list[ret]; 1729 } 1730 ibv_match[nd] = NULL; 1731 if (!nd) { 1732 /* No device matches, just complain and bail out. */ 1733 DRV_LOG(WARNING, 1734 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1735 " are kernel drivers loaded?", 1736 pci_dev->addr.domain, pci_dev->addr.bus, 1737 pci_dev->addr.devid, pci_dev->addr.function); 1738 rte_errno = ENOENT; 1739 ret = -rte_errno; 1740 goto exit; 1741 } 1742 if (nd == 1) { 1743 /* 1744 * Found single matching device may have multiple ports. 1745 * Each port may be representor, we have to check the port 1746 * number and check the representors existence. 1747 */ 1748 if (nl_rdma >= 0) 1749 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1750 if (!np) 1751 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1752 " ports number", ibv_match[0]->name); 1753 if (bd >= 0 && !np) { 1754 DRV_LOG(ERR, "can not get ports" 1755 " for bonding device"); 1756 rte_errno = ENOENT; 1757 ret = -rte_errno; 1758 goto exit; 1759 } 1760 } 1761 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 1762 if (bd >= 0) { 1763 /* 1764 * This may happen if there is VF LAG kernel support and 1765 * application is compiled with older rdma_core library. 1766 */ 1767 DRV_LOG(ERR, 1768 "No kernel/verbs support for VF LAG bonding found."); 1769 rte_errno = ENOTSUP; 1770 ret = -rte_errno; 1771 goto exit; 1772 } 1773 #endif 1774 /* 1775 * Now we can determine the maximal 1776 * amount of devices to be spawned. 1777 */ 1778 list = mlx5_malloc(MLX5_MEM_ZERO, 1779 sizeof(struct mlx5_dev_spawn_data) * 1780 (np ? np : nd), 1781 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1782 if (!list) { 1783 DRV_LOG(ERR, "spawn data array allocation failure"); 1784 rte_errno = ENOMEM; 1785 ret = -rte_errno; 1786 goto exit; 1787 } 1788 if (bd >= 0 || np > 1) { 1789 /* 1790 * Single IB device with multiple ports found, 1791 * it may be E-Switch master device and representors. 1792 * We have to perform identification through the ports. 1793 */ 1794 MLX5_ASSERT(nl_rdma >= 0); 1795 MLX5_ASSERT(ns == 0); 1796 MLX5_ASSERT(nd == 1); 1797 MLX5_ASSERT(np); 1798 for (i = 1; i <= np; ++i) { 1799 list[ns].max_port = np; 1800 list[ns].phys_port = i; 1801 list[ns].phys_dev = ibv_match[0]; 1802 list[ns].eth_dev = NULL; 1803 list[ns].pci_dev = pci_dev; 1804 list[ns].pf_bond = bd; 1805 list[ns].ifindex = mlx5_nl_ifindex 1806 (nl_rdma, 1807 mlx5_os_get_dev_device_name 1808 (list[ns].phys_dev), i); 1809 if (!list[ns].ifindex) { 1810 /* 1811 * No network interface index found for the 1812 * specified port, it means there is no 1813 * representor on this port. It's OK, 1814 * there can be disabled ports, for example 1815 * if sriov_numvfs < sriov_totalvfs. 1816 */ 1817 continue; 1818 } 1819 ret = -1; 1820 if (nl_route >= 0) 1821 ret = mlx5_nl_switch_info 1822 (nl_route, 1823 list[ns].ifindex, 1824 &list[ns].info); 1825 if (ret || (!list[ns].info.representor && 1826 !list[ns].info.master)) { 1827 /* 1828 * We failed to recognize representors with 1829 * Netlink, let's try to perform the task 1830 * with sysfs. 1831 */ 1832 ret = mlx5_sysfs_switch_info 1833 (list[ns].ifindex, 1834 &list[ns].info); 1835 } 1836 if (!ret && bd >= 0) { 1837 switch (list[ns].info.name_type) { 1838 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 1839 if (list[ns].info.port_name == bd) 1840 ns++; 1841 break; 1842 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 1843 /* Fallthrough */ 1844 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 1845 if (list[ns].info.pf_num == bd) 1846 ns++; 1847 break; 1848 default: 1849 break; 1850 } 1851 continue; 1852 } 1853 if (!ret && (list[ns].info.representor ^ 1854 list[ns].info.master)) 1855 ns++; 1856 } 1857 if (!ns) { 1858 DRV_LOG(ERR, 1859 "unable to recognize master/representors" 1860 " on the IB device with multiple ports"); 1861 rte_errno = ENOENT; 1862 ret = -rte_errno; 1863 goto exit; 1864 } 1865 } else { 1866 /* 1867 * The existence of several matching entries (nd > 1) means 1868 * port representors have been instantiated. No existing Verbs 1869 * call nor sysfs entries can tell them apart, this can only 1870 * be done through Netlink calls assuming kernel drivers are 1871 * recent enough to support them. 1872 * 1873 * In the event of identification failure through Netlink, 1874 * try again through sysfs, then: 1875 * 1876 * 1. A single IB device matches (nd == 1) with single 1877 * port (np=0/1) and is not a representor, assume 1878 * no switch support. 1879 * 1880 * 2. Otherwise no safe assumptions can be made; 1881 * complain louder and bail out. 1882 */ 1883 for (i = 0; i != nd; ++i) { 1884 memset(&list[ns].info, 0, sizeof(list[ns].info)); 1885 list[ns].max_port = 1; 1886 list[ns].phys_port = 1; 1887 list[ns].phys_dev = ibv_match[i]; 1888 list[ns].eth_dev = NULL; 1889 list[ns].pci_dev = pci_dev; 1890 list[ns].pf_bond = -1; 1891 list[ns].ifindex = 0; 1892 if (nl_rdma >= 0) 1893 list[ns].ifindex = mlx5_nl_ifindex 1894 (nl_rdma, 1895 mlx5_os_get_dev_device_name 1896 (list[ns].phys_dev), 1); 1897 if (!list[ns].ifindex) { 1898 char ifname[IF_NAMESIZE]; 1899 1900 /* 1901 * Netlink failed, it may happen with old 1902 * ib_core kernel driver (before 4.16). 1903 * We can assume there is old driver because 1904 * here we are processing single ports IB 1905 * devices. Let's try sysfs to retrieve 1906 * the ifindex. The method works for 1907 * master device only. 1908 */ 1909 if (nd > 1) { 1910 /* 1911 * Multiple devices found, assume 1912 * representors, can not distinguish 1913 * master/representor and retrieve 1914 * ifindex via sysfs. 1915 */ 1916 continue; 1917 } 1918 ret = mlx5_get_ifname_sysfs 1919 (ibv_match[i]->ibdev_path, ifname); 1920 if (!ret) 1921 list[ns].ifindex = 1922 if_nametoindex(ifname); 1923 if (!list[ns].ifindex) { 1924 /* 1925 * No network interface index found 1926 * for the specified device, it means 1927 * there it is neither representor 1928 * nor master. 1929 */ 1930 continue; 1931 } 1932 } 1933 ret = -1; 1934 if (nl_route >= 0) 1935 ret = mlx5_nl_switch_info 1936 (nl_route, 1937 list[ns].ifindex, 1938 &list[ns].info); 1939 if (ret || (!list[ns].info.representor && 1940 !list[ns].info.master)) { 1941 /* 1942 * We failed to recognize representors with 1943 * Netlink, let's try to perform the task 1944 * with sysfs. 1945 */ 1946 ret = mlx5_sysfs_switch_info 1947 (list[ns].ifindex, 1948 &list[ns].info); 1949 } 1950 if (!ret && (list[ns].info.representor ^ 1951 list[ns].info.master)) { 1952 ns++; 1953 } else if ((nd == 1) && 1954 !list[ns].info.representor && 1955 !list[ns].info.master) { 1956 /* 1957 * Single IB device with 1958 * one physical port and 1959 * attached network device. 1960 * May be SRIOV is not enabled 1961 * or there is no representors. 1962 */ 1963 DRV_LOG(INFO, "no E-Switch support detected"); 1964 ns++; 1965 break; 1966 } 1967 } 1968 if (!ns) { 1969 DRV_LOG(ERR, 1970 "unable to recognize master/representors" 1971 " on the multiple IB devices"); 1972 rte_errno = ENOENT; 1973 ret = -rte_errno; 1974 goto exit; 1975 } 1976 } 1977 MLX5_ASSERT(ns); 1978 /* 1979 * Sort list to probe devices in natural order for users convenience 1980 * (i.e. master first, then representors from lowest to highest ID). 1981 */ 1982 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 1983 /* Device specific configuration. */ 1984 switch (pci_dev->id.device_id) { 1985 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1986 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1987 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1988 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1989 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 1990 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 1991 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF: 1992 dev_config_vf = 1; 1993 break; 1994 default: 1995 dev_config_vf = 0; 1996 break; 1997 } 1998 for (i = 0; i != ns; ++i) { 1999 uint32_t restore; 2000 2001 /* Default configuration. */ 2002 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2003 dev_config.vf = dev_config_vf; 2004 dev_config.mps = MLX5_ARG_UNSET; 2005 dev_config.dbnc = MLX5_ARG_UNSET; 2006 dev_config.rx_vec_en = 1; 2007 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2008 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2009 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2010 dev_config.txqs_inline = MLX5_ARG_UNSET; 2011 dev_config.vf_nl_en = 1; 2012 dev_config.mr_ext_memseg_en = 1; 2013 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2014 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2015 dev_config.dv_esw_en = 1; 2016 dev_config.dv_flow_en = 1; 2017 dev_config.decap_en = 1; 2018 dev_config.log_hp_size = MLX5_ARG_UNSET; 2019 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2020 &list[i], 2021 &dev_config); 2022 if (!list[i].eth_dev) { 2023 if (rte_errno != EBUSY && rte_errno != EEXIST) 2024 break; 2025 /* Device is disabled or already spawned. Ignore it. */ 2026 continue; 2027 } 2028 restore = list[i].eth_dev->data->dev_flags; 2029 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2030 /* Restore non-PCI flags cleared by the above call. */ 2031 list[i].eth_dev->data->dev_flags |= restore; 2032 rte_eth_dev_probing_finish(list[i].eth_dev); 2033 } 2034 if (i != ns) { 2035 DRV_LOG(ERR, 2036 "probe of PCI device " PCI_PRI_FMT " aborted after" 2037 " encountering an error: %s", 2038 pci_dev->addr.domain, pci_dev->addr.bus, 2039 pci_dev->addr.devid, pci_dev->addr.function, 2040 strerror(rte_errno)); 2041 ret = -rte_errno; 2042 /* Roll back. */ 2043 while (i--) { 2044 if (!list[i].eth_dev) 2045 continue; 2046 mlx5_dev_close(list[i].eth_dev); 2047 /* mac_addrs must not be freed because in dev_private */ 2048 list[i].eth_dev->data->mac_addrs = NULL; 2049 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2050 } 2051 /* Restore original error. */ 2052 rte_errno = -ret; 2053 } else { 2054 ret = 0; 2055 } 2056 exit: 2057 /* 2058 * Do the routine cleanup: 2059 * - close opened Netlink sockets 2060 * - free allocated spawn data array 2061 * - free the Infiniband device list 2062 */ 2063 if (nl_rdma >= 0) 2064 close(nl_rdma); 2065 if (nl_route >= 0) 2066 close(nl_route); 2067 if (list) 2068 mlx5_free(list); 2069 MLX5_ASSERT(ibv_list); 2070 mlx5_glue->free_device_list(ibv_list); 2071 return ret; 2072 } 2073 2074 static int 2075 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2076 { 2077 char *env; 2078 int value; 2079 2080 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2081 /* Get environment variable to store. */ 2082 env = getenv(MLX5_SHUT_UP_BF); 2083 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2084 if (config->dbnc == MLX5_ARG_UNSET) 2085 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2086 else 2087 setenv(MLX5_SHUT_UP_BF, 2088 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2089 return value; 2090 } 2091 2092 static void 2093 mlx5_restore_doorbell_mapping_env(int value) 2094 { 2095 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2096 /* Restore the original environment variable state. */ 2097 if (value == MLX5_ARG_UNSET) 2098 unsetenv(MLX5_SHUT_UP_BF); 2099 else 2100 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2101 } 2102 2103 /** 2104 * Extract pdn of PD object using DV API. 2105 * 2106 * @param[in] pd 2107 * Pointer to the verbs PD object. 2108 * @param[out] pdn 2109 * Pointer to the PD object number variable. 2110 * 2111 * @return 2112 * 0 on success, error value otherwise. 2113 */ 2114 int 2115 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2116 { 2117 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2118 struct mlx5dv_obj obj; 2119 struct mlx5dv_pd pd_info; 2120 int ret = 0; 2121 2122 obj.pd.in = pd; 2123 obj.pd.out = &pd_info; 2124 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2125 if (ret) { 2126 DRV_LOG(DEBUG, "Fail to get PD object info"); 2127 return ret; 2128 } 2129 *pdn = pd_info.pdn; 2130 return 0; 2131 #else 2132 (void)pd; 2133 (void)pdn; 2134 return -ENOTSUP; 2135 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2136 } 2137 2138 /** 2139 * Function API to open IB device. 2140 * 2141 * This function calls the Linux glue APIs to open a device. 2142 * 2143 * @param[in] spawn 2144 * Pointer to the IB device attributes (name, port, etc). 2145 * @param[out] config 2146 * Pointer to device configuration structure. 2147 * @param[out] sh 2148 * Pointer to shared context structure. 2149 * 2150 * @return 2151 * 0 on success, a positive error value otherwise. 2152 */ 2153 int 2154 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2155 const struct mlx5_dev_config *config, 2156 struct mlx5_dev_ctx_shared *sh) 2157 { 2158 int dbmap_env; 2159 int err = 0; 2160 2161 sh->numa_node = spawn->pci_dev->device.numa_node; 2162 pthread_mutex_init(&sh->txpp.mutex, NULL); 2163 /* 2164 * Configure environment variable "MLX5_BF_SHUT_UP" 2165 * before the device creation. The rdma_core library 2166 * checks the variable at device creation and 2167 * stores the result internally. 2168 */ 2169 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2170 /* Try to open IB device with DV first, then usual Verbs. */ 2171 errno = 0; 2172 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2173 if (sh->ctx) { 2174 sh->devx = 1; 2175 DRV_LOG(DEBUG, "DevX is supported"); 2176 /* The device is created, no need for environment. */ 2177 mlx5_restore_doorbell_mapping_env(dbmap_env); 2178 } else { 2179 /* The environment variable is still configured. */ 2180 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2181 err = errno ? errno : ENODEV; 2182 /* 2183 * The environment variable is not needed anymore, 2184 * all device creation attempts are completed. 2185 */ 2186 mlx5_restore_doorbell_mapping_env(dbmap_env); 2187 if (!sh->ctx) 2188 return err; 2189 DRV_LOG(DEBUG, "DevX is NOT supported"); 2190 err = 0; 2191 } 2192 return err; 2193 } 2194 2195 /** 2196 * Install shared asynchronous device events handler. 2197 * This function is implemented to support event sharing 2198 * between multiple ports of single IB device. 2199 * 2200 * @param sh 2201 * Pointer to mlx5_dev_ctx_shared object. 2202 */ 2203 void 2204 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2205 { 2206 int ret; 2207 int flags; 2208 2209 sh->intr_handle.fd = -1; 2210 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2211 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2212 F_SETFL, flags | O_NONBLOCK); 2213 if (ret) { 2214 DRV_LOG(INFO, "failed to change file descriptor async event" 2215 " queue"); 2216 } else { 2217 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2218 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2219 if (rte_intr_callback_register(&sh->intr_handle, 2220 mlx5_dev_interrupt_handler, sh)) { 2221 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2222 sh->intr_handle.fd = -1; 2223 } 2224 } 2225 if (sh->devx) { 2226 #ifdef HAVE_IBV_DEVX_ASYNC 2227 sh->intr_handle_devx.fd = -1; 2228 sh->devx_comp = 2229 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2230 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2231 if (!devx_comp) { 2232 DRV_LOG(INFO, "failed to allocate devx_comp."); 2233 return; 2234 } 2235 flags = fcntl(devx_comp->fd, F_GETFL); 2236 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2237 if (ret) { 2238 DRV_LOG(INFO, "failed to change file descriptor" 2239 " devx comp"); 2240 return; 2241 } 2242 sh->intr_handle_devx.fd = devx_comp->fd; 2243 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2244 if (rte_intr_callback_register(&sh->intr_handle_devx, 2245 mlx5_dev_interrupt_handler_devx, sh)) { 2246 DRV_LOG(INFO, "Fail to install the devx shared" 2247 " interrupt."); 2248 sh->intr_handle_devx.fd = -1; 2249 } 2250 #endif /* HAVE_IBV_DEVX_ASYNC */ 2251 } 2252 } 2253 2254 /** 2255 * Uninstall shared asynchronous device events handler. 2256 * This function is implemented to support event sharing 2257 * between multiple ports of single IB device. 2258 * 2259 * @param dev 2260 * Pointer to mlx5_dev_ctx_shared object. 2261 */ 2262 void 2263 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2264 { 2265 if (sh->intr_handle.fd >= 0) 2266 mlx5_intr_callback_unregister(&sh->intr_handle, 2267 mlx5_dev_interrupt_handler, sh); 2268 #ifdef HAVE_IBV_DEVX_ASYNC 2269 if (sh->intr_handle_devx.fd >= 0) 2270 rte_intr_callback_unregister(&sh->intr_handle_devx, 2271 mlx5_dev_interrupt_handler_devx, sh); 2272 if (sh->devx_comp) 2273 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2274 #endif 2275 } 2276 2277 /** 2278 * Read statistics by a named counter. 2279 * 2280 * @param[in] priv 2281 * Pointer to the private device data structure. 2282 * @param[in] ctr_name 2283 * Pointer to the name of the statistic counter to read 2284 * @param[out] stat 2285 * Pointer to read statistic value. 2286 * @return 2287 * 0 on success and stat is valud, 1 if failed to read the value 2288 * rte_errno is set. 2289 * 2290 */ 2291 int 2292 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2293 uint64_t *stat) 2294 { 2295 int fd; 2296 2297 if (priv->sh) { 2298 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2299 priv->sh->ibdev_path, 2300 priv->dev_port, 2301 ctr_name); 2302 fd = open(path, O_RDONLY); 2303 /* 2304 * in switchdev the file location is not per port 2305 * but rather in <ibdev_path>/hw_counters/<file_name>. 2306 */ 2307 if (fd == -1) { 2308 MKSTR(path1, "%s/hw_counters/%s", 2309 priv->sh->ibdev_path, 2310 ctr_name); 2311 fd = open(path1, O_RDONLY); 2312 } 2313 if (fd != -1) { 2314 char buf[21] = {'\0'}; 2315 ssize_t n = read(fd, buf, sizeof(buf)); 2316 2317 close(fd); 2318 if (n != -1) { 2319 *stat = strtoull(buf, NULL, 10); 2320 return 0; 2321 } 2322 } 2323 } 2324 *stat = 0; 2325 return 1; 2326 } 2327 2328 /** 2329 * Set the reg_mr and dereg_mr call backs 2330 * 2331 * @param reg_mr_cb[out] 2332 * Pointer to reg_mr func 2333 * @param dereg_mr_cb[out] 2334 * Pointer to dereg_mr func 2335 * 2336 */ 2337 void 2338 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2339 mlx5_dereg_mr_t *dereg_mr_cb) 2340 { 2341 *reg_mr_cb = mlx5_verbs_ops.reg_mr; 2342 *dereg_mr_cb = mlx5_verbs_ops.dereg_mr; 2343 } 2344 2345 /** 2346 * Remove a MAC address from device 2347 * 2348 * @param dev 2349 * Pointer to Ethernet device structure. 2350 * @param index 2351 * MAC address index. 2352 */ 2353 void 2354 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2355 { 2356 struct mlx5_priv *priv = dev->data->dev_private; 2357 const int vf = priv->config.vf; 2358 2359 if (vf) 2360 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2361 mlx5_ifindex(dev), priv->mac_own, 2362 &dev->data->mac_addrs[index], index); 2363 } 2364 2365 /** 2366 * Adds a MAC address to the device 2367 * 2368 * @param dev 2369 * Pointer to Ethernet device structure. 2370 * @param mac_addr 2371 * MAC address to register. 2372 * @param index 2373 * MAC address index. 2374 * 2375 * @return 2376 * 0 on success, a negative errno value otherwise 2377 */ 2378 int 2379 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2380 uint32_t index) 2381 { 2382 struct mlx5_priv *priv = dev->data->dev_private; 2383 const int vf = priv->config.vf; 2384 int ret = 0; 2385 2386 if (vf) 2387 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2388 mlx5_ifindex(dev), priv->mac_own, 2389 mac, index); 2390 return ret; 2391 } 2392 2393 /** 2394 * Modify a VF MAC address 2395 * 2396 * @param priv 2397 * Pointer to device private data. 2398 * @param mac_addr 2399 * MAC address to modify into. 2400 * @param iface_idx 2401 * Net device interface index 2402 * @param vf_index 2403 * VF index 2404 * 2405 * @return 2406 * 0 on success, a negative errno value otherwise 2407 */ 2408 int 2409 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2410 unsigned int iface_idx, 2411 struct rte_ether_addr *mac_addr, 2412 int vf_index) 2413 { 2414 return mlx5_nl_vf_mac_addr_modify 2415 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2416 } 2417 2418 /** 2419 * Set device promiscuous mode 2420 * 2421 * @param dev 2422 * Pointer to Ethernet device structure. 2423 * @param enable 2424 * 0 - promiscuous is disabled, otherwise - enabled 2425 * 2426 * @return 2427 * 0 on success, a negative error value otherwise 2428 */ 2429 int 2430 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2431 { 2432 struct mlx5_priv *priv = dev->data->dev_private; 2433 2434 return mlx5_nl_promisc(priv->nl_socket_route, 2435 mlx5_ifindex(dev), !!enable); 2436 } 2437 2438 /** 2439 * Set device promiscuous mode 2440 * 2441 * @param dev 2442 * Pointer to Ethernet device structure. 2443 * @param enable 2444 * 0 - all multicase is disabled, otherwise - enabled 2445 * 2446 * @return 2447 * 0 on success, a negative error value otherwise 2448 */ 2449 int 2450 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2451 { 2452 struct mlx5_priv *priv = dev->data->dev_private; 2453 2454 return mlx5_nl_allmulti(priv->nl_socket_route, 2455 mlx5_ifindex(dev), !!enable); 2456 } 2457 2458 /** 2459 * Flush device MAC addresses 2460 * 2461 * @param dev 2462 * Pointer to Ethernet device structure. 2463 * 2464 */ 2465 void 2466 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2467 { 2468 struct mlx5_priv *priv = dev->data->dev_private; 2469 2470 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2471 dev->data->mac_addrs, 2472 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2473 } 2474 2475 const struct eth_dev_ops mlx5_os_dev_ops = { 2476 .dev_configure = mlx5_dev_configure, 2477 .dev_start = mlx5_dev_start, 2478 .dev_stop = mlx5_dev_stop, 2479 .dev_set_link_down = mlx5_set_link_down, 2480 .dev_set_link_up = mlx5_set_link_up, 2481 .dev_close = mlx5_dev_close, 2482 .promiscuous_enable = mlx5_promiscuous_enable, 2483 .promiscuous_disable = mlx5_promiscuous_disable, 2484 .allmulticast_enable = mlx5_allmulticast_enable, 2485 .allmulticast_disable = mlx5_allmulticast_disable, 2486 .link_update = mlx5_link_update, 2487 .stats_get = mlx5_stats_get, 2488 .stats_reset = mlx5_stats_reset, 2489 .xstats_get = mlx5_xstats_get, 2490 .xstats_reset = mlx5_xstats_reset, 2491 .xstats_get_names = mlx5_xstats_get_names, 2492 .fw_version_get = mlx5_fw_version_get, 2493 .dev_infos_get = mlx5_dev_infos_get, 2494 .read_clock = mlx5_txpp_read_clock, 2495 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2496 .vlan_filter_set = mlx5_vlan_filter_set, 2497 .rx_queue_setup = mlx5_rx_queue_setup, 2498 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2499 .tx_queue_setup = mlx5_tx_queue_setup, 2500 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2501 .rx_queue_release = mlx5_rx_queue_release, 2502 .tx_queue_release = mlx5_tx_queue_release, 2503 .rx_queue_start = mlx5_rx_queue_start, 2504 .rx_queue_stop = mlx5_rx_queue_stop, 2505 .tx_queue_start = mlx5_tx_queue_start, 2506 .tx_queue_stop = mlx5_tx_queue_stop, 2507 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2508 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2509 .mac_addr_remove = mlx5_mac_addr_remove, 2510 .mac_addr_add = mlx5_mac_addr_add, 2511 .mac_addr_set = mlx5_mac_addr_set, 2512 .set_mc_addr_list = mlx5_set_mc_addr_list, 2513 .mtu_set = mlx5_dev_set_mtu, 2514 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2515 .vlan_offload_set = mlx5_vlan_offload_set, 2516 .reta_update = mlx5_dev_rss_reta_update, 2517 .reta_query = mlx5_dev_rss_reta_query, 2518 .rss_hash_update = mlx5_rss_hash_update, 2519 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2520 .filter_ctrl = mlx5_dev_filter_ctrl, 2521 .rxq_info_get = mlx5_rxq_info_get, 2522 .txq_info_get = mlx5_txq_info_get, 2523 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2524 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2525 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2526 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2527 .is_removed = mlx5_is_removed, 2528 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2529 .get_module_info = mlx5_get_module_info, 2530 .get_module_eeprom = mlx5_get_module_eeprom, 2531 .hairpin_cap_get = mlx5_hairpin_cap_get, 2532 .mtr_ops_get = mlx5_flow_meter_ops_get, 2533 }; 2534 2535 /* Available operations from secondary process. */ 2536 const struct eth_dev_ops mlx5_os_dev_sec_ops = { 2537 .stats_get = mlx5_stats_get, 2538 .stats_reset = mlx5_stats_reset, 2539 .xstats_get = mlx5_xstats_get, 2540 .xstats_reset = mlx5_xstats_reset, 2541 .xstats_get_names = mlx5_xstats_get_names, 2542 .fw_version_get = mlx5_fw_version_get, 2543 .dev_infos_get = mlx5_dev_infos_get, 2544 .read_clock = mlx5_txpp_read_clock, 2545 .rx_queue_start = mlx5_rx_queue_start, 2546 .rx_queue_stop = mlx5_rx_queue_stop, 2547 .tx_queue_start = mlx5_tx_queue_start, 2548 .tx_queue_stop = mlx5_tx_queue_stop, 2549 .rxq_info_get = mlx5_rxq_info_get, 2550 .txq_info_get = mlx5_txq_info_get, 2551 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2552 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2553 .get_module_info = mlx5_get_module_info, 2554 .get_module_eeprom = mlx5_get_module_eeprom, 2555 }; 2556 2557 /* Available operations in flow isolated mode. */ 2558 const struct eth_dev_ops mlx5_os_dev_ops_isolate = { 2559 .dev_configure = mlx5_dev_configure, 2560 .dev_start = mlx5_dev_start, 2561 .dev_stop = mlx5_dev_stop, 2562 .dev_set_link_down = mlx5_set_link_down, 2563 .dev_set_link_up = mlx5_set_link_up, 2564 .dev_close = mlx5_dev_close, 2565 .promiscuous_enable = mlx5_promiscuous_enable, 2566 .promiscuous_disable = mlx5_promiscuous_disable, 2567 .allmulticast_enable = mlx5_allmulticast_enable, 2568 .allmulticast_disable = mlx5_allmulticast_disable, 2569 .link_update = mlx5_link_update, 2570 .stats_get = mlx5_stats_get, 2571 .stats_reset = mlx5_stats_reset, 2572 .xstats_get = mlx5_xstats_get, 2573 .xstats_reset = mlx5_xstats_reset, 2574 .xstats_get_names = mlx5_xstats_get_names, 2575 .fw_version_get = mlx5_fw_version_get, 2576 .dev_infos_get = mlx5_dev_infos_get, 2577 .read_clock = mlx5_txpp_read_clock, 2578 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2579 .vlan_filter_set = mlx5_vlan_filter_set, 2580 .rx_queue_setup = mlx5_rx_queue_setup, 2581 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2582 .tx_queue_setup = mlx5_tx_queue_setup, 2583 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2584 .rx_queue_release = mlx5_rx_queue_release, 2585 .tx_queue_release = mlx5_tx_queue_release, 2586 .rx_queue_start = mlx5_rx_queue_start, 2587 .rx_queue_stop = mlx5_rx_queue_stop, 2588 .tx_queue_start = mlx5_tx_queue_start, 2589 .tx_queue_stop = mlx5_tx_queue_stop, 2590 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2591 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2592 .mac_addr_remove = mlx5_mac_addr_remove, 2593 .mac_addr_add = mlx5_mac_addr_add, 2594 .mac_addr_set = mlx5_mac_addr_set, 2595 .set_mc_addr_list = mlx5_set_mc_addr_list, 2596 .mtu_set = mlx5_dev_set_mtu, 2597 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2598 .vlan_offload_set = mlx5_vlan_offload_set, 2599 .filter_ctrl = mlx5_dev_filter_ctrl, 2600 .rxq_info_get = mlx5_rxq_info_get, 2601 .txq_info_get = mlx5_txq_info_get, 2602 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2603 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2604 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2605 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2606 .is_removed = mlx5_is_removed, 2607 .get_module_info = mlx5_get_module_info, 2608 .get_module_eeprom = mlx5_get_module_eeprom, 2609 .hairpin_cap_get = mlx5_hairpin_cap_get, 2610 .mtr_ops_get = mlx5_flow_meter_ops_get, 2611 }; 2612