1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /* rte flow indexed pool configuration. */ 71 static struct mlx5_indexed_pool_config icfg[] = { 72 { 73 .size = sizeof(struct rte_flow), 74 .trunk_size = 64, 75 .need_lock = 1, 76 .release_mem_en = 0, 77 .malloc = mlx5_malloc, 78 .free = mlx5_free, 79 .per_core_cache = 0, 80 .type = "ctl_flow_ipool", 81 }, 82 { 83 .size = sizeof(struct rte_flow), 84 .trunk_size = 64, 85 .grow_trunk = 3, 86 .grow_shift = 2, 87 .need_lock = 1, 88 .release_mem_en = 0, 89 .malloc = mlx5_malloc, 90 .free = mlx5_free, 91 .per_core_cache = 1 << 14, 92 .type = "rte_flow_ipool", 93 }, 94 { 95 .size = sizeof(struct rte_flow), 96 .trunk_size = 64, 97 .grow_trunk = 3, 98 .grow_shift = 2, 99 .need_lock = 1, 100 .release_mem_en = 0, 101 .malloc = mlx5_malloc, 102 .free = mlx5_free, 103 .per_core_cache = 0, 104 .type = "mcp_flow_ipool", 105 }, 106 }; 107 108 /** 109 * Set the completion channel file descriptor interrupt as non-blocking. 110 * 111 * @param[in] rxq_obj 112 * Pointer to RQ channel object, which includes the channel fd 113 * 114 * @param[out] fd 115 * The file descriptor (representing the interrupt) used in this channel. 116 * 117 * @return 118 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 119 */ 120 int 121 mlx5_os_set_nonblock_channel_fd(int fd) 122 { 123 int flags; 124 125 flags = fcntl(fd, F_GETFL); 126 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 127 } 128 129 /** 130 * Get mlx5 device attributes. The glue function query_device_ex() is called 131 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 132 * device attributes from the glue out parameter. 133 * 134 * @param cdev 135 * Pointer to mlx5 device. 136 * 137 * @param device_attr 138 * Pointer to mlx5 device attributes. 139 * 140 * @return 141 * 0 on success, a negative errno value otherwise and rte_errno is set. 142 */ 143 int 144 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, 145 struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_context *ctx = cdev->ctx; 149 struct ibv_device_attr_ex attr_ex; 150 151 memset(device_attr, 0, sizeof(*device_attr)); 152 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 153 if (err) { 154 rte_errno = errno; 155 return -rte_errno; 156 } 157 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 158 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 159 device_attr->max_sge = attr_ex.orig_attr.max_sge; 160 device_attr->max_cq = attr_ex.orig_attr.max_cq; 161 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 162 device_attr->max_mr = attr_ex.orig_attr.max_mr; 163 device_attr->max_pd = attr_ex.orig_attr.max_pd; 164 device_attr->max_qp = attr_ex.orig_attr.max_qp; 165 device_attr->max_srq = attr_ex.orig_attr.max_srq; 166 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 167 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 168 device_attr->max_rwq_indirection_table_size = 169 attr_ex.rss_caps.max_rwq_indirection_table_size; 170 device_attr->max_tso = attr_ex.tso_caps.max_tso; 171 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 172 173 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 174 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 175 if (err) { 176 rte_errno = errno; 177 return -rte_errno; 178 } 179 180 device_attr->flags = dv_attr.flags; 181 device_attr->comp_mask = dv_attr.comp_mask; 182 #ifdef HAVE_IBV_MLX5_MOD_SWP 183 device_attr->sw_parsing_offloads = 184 dv_attr.sw_parsing_caps.sw_parsing_offloads; 185 #endif 186 device_attr->min_single_stride_log_num_of_bytes = 187 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 188 device_attr->max_single_stride_log_num_of_bytes = 189 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 190 device_attr->min_single_wqe_log_num_of_strides = 191 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 192 device_attr->max_single_wqe_log_num_of_strides = 193 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 194 device_attr->stride_supported_qpts = 195 dv_attr.striding_rq_caps.supported_qpts; 196 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 197 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 198 #endif 199 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 200 sizeof(device_attr->fw_ver)); 201 202 return 0; 203 } 204 205 /** 206 * Detect misc5 support or not 207 * 208 * @param[in] priv 209 * Device private data pointer 210 */ 211 #ifdef HAVE_MLX5DV_DR 212 static void 213 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 214 { 215 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 216 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 217 * Case: IPv4--->UDP--->VxLAN--->vni 218 */ 219 void *tbl; 220 struct mlx5_flow_dv_match_params matcher_mask; 221 void *match_m; 222 void *matcher; 223 void *headers_m; 224 void *misc5_m; 225 uint32_t *tunnel_header_m; 226 struct mlx5dv_flow_matcher_attr dv_attr; 227 228 memset(&matcher_mask, 0, sizeof(matcher_mask)); 229 matcher_mask.size = sizeof(matcher_mask.buf); 230 match_m = matcher_mask.buf; 231 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 232 misc5_m = MLX5_ADDR_OF(fte_match_param, 233 match_m, misc_parameters_5); 234 tunnel_header_m = (uint32_t *) 235 MLX5_ADDR_OF(fte_match_set_misc5, 236 misc5_m, tunnel_header_1); 237 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 238 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 239 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 240 *tunnel_header_m = 0xffffff; 241 242 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 243 if (!tbl) { 244 DRV_LOG(INFO, "No SW steering support"); 245 return; 246 } 247 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 248 dv_attr.match_mask = (void *)&matcher_mask, 249 dv_attr.match_criteria_enable = 250 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 251 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 252 dv_attr.priority = 3; 253 #ifdef HAVE_MLX5DV_DR_ESWITCH 254 void *misc2_m; 255 if (priv->config.dv_esw_en) { 256 /* FDB enabled reg_c_0 */ 257 dv_attr.match_criteria_enable |= 258 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 259 misc2_m = MLX5_ADDR_OF(fte_match_param, 260 match_m, misc_parameters_2); 261 MLX5_SET(fte_match_set_misc2, misc2_m, 262 metadata_reg_c_0, 0xffff); 263 } 264 #endif 265 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx, 266 &dv_attr, tbl); 267 if (matcher) { 268 priv->sh->misc5_cap = 1; 269 mlx5_glue->dv_destroy_flow_matcher(matcher); 270 } 271 mlx5_glue->dr_destroy_flow_tbl(tbl); 272 #else 273 RTE_SET_USED(priv); 274 #endif 275 } 276 #endif 277 278 /** 279 * Initialize DR related data within private structure. 280 * Routine checks the reference counter and does actual 281 * resources creation/initialization only if counter is zero. 282 * 283 * @param[in] priv 284 * Pointer to the private device data structure. 285 * 286 * @return 287 * Zero on success, positive error code otherwise. 288 */ 289 static int 290 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 291 { 292 struct mlx5_dev_ctx_shared *sh = priv->sh; 293 char s[MLX5_NAME_SIZE] __rte_unused; 294 int err; 295 296 MLX5_ASSERT(sh && sh->refcnt); 297 if (sh->refcnt > 1) 298 return 0; 299 err = mlx5_alloc_table_hash_list(priv); 300 if (err) 301 goto error; 302 /* The resources below are only valid with DV support. */ 303 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 304 /* Init port id action list. */ 305 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 306 sh->port_id_action_list = mlx5_list_create(s, sh, true, 307 flow_dv_port_id_create_cb, 308 flow_dv_port_id_match_cb, 309 flow_dv_port_id_remove_cb, 310 flow_dv_port_id_clone_cb, 311 flow_dv_port_id_clone_free_cb); 312 if (!sh->port_id_action_list) 313 goto error; 314 /* Init push vlan action list. */ 315 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 316 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 317 flow_dv_push_vlan_create_cb, 318 flow_dv_push_vlan_match_cb, 319 flow_dv_push_vlan_remove_cb, 320 flow_dv_push_vlan_clone_cb, 321 flow_dv_push_vlan_clone_free_cb); 322 if (!sh->push_vlan_action_list) 323 goto error; 324 /* Init sample action list. */ 325 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 326 sh->sample_action_list = mlx5_list_create(s, sh, true, 327 flow_dv_sample_create_cb, 328 flow_dv_sample_match_cb, 329 flow_dv_sample_remove_cb, 330 flow_dv_sample_clone_cb, 331 flow_dv_sample_clone_free_cb); 332 if (!sh->sample_action_list) 333 goto error; 334 /* Init dest array action list. */ 335 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 336 sh->dest_array_list = mlx5_list_create(s, sh, true, 337 flow_dv_dest_array_create_cb, 338 flow_dv_dest_array_match_cb, 339 flow_dv_dest_array_remove_cb, 340 flow_dv_dest_array_clone_cb, 341 flow_dv_dest_array_clone_free_cb); 342 if (!sh->dest_array_list) 343 goto error; 344 /* Init shared flex parsers list, no need lcore_share */ 345 snprintf(s, sizeof(s), "%s_flex_parsers_list", sh->ibdev_name); 346 sh->flex_parsers_dv = mlx5_list_create(s, sh, false, 347 mlx5_flex_parser_create_cb, 348 mlx5_flex_parser_match_cb, 349 mlx5_flex_parser_remove_cb, 350 mlx5_flex_parser_clone_cb, 351 mlx5_flex_parser_clone_free_cb); 352 if (!sh->flex_parsers_dv) 353 goto error; 354 #endif 355 #ifdef HAVE_MLX5DV_DR 356 void *domain; 357 358 /* Reference counter is zero, we should initialize structures. */ 359 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 360 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 361 if (!domain) { 362 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 363 err = errno; 364 goto error; 365 } 366 sh->rx_domain = domain; 367 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 368 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 369 if (!domain) { 370 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 371 err = errno; 372 goto error; 373 } 374 sh->tx_domain = domain; 375 #ifdef HAVE_MLX5DV_DR_ESWITCH 376 if (priv->config.dv_esw_en) { 377 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 378 MLX5DV_DR_DOMAIN_TYPE_FDB); 379 if (!domain) { 380 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 381 err = errno; 382 goto error; 383 } 384 sh->fdb_domain = domain; 385 } 386 /* 387 * The drop action is just some dummy placeholder in rdma-core. It 388 * does not belong to domains and has no any attributes, and, can be 389 * shared by the entire device. 390 */ 391 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 392 if (!sh->dr_drop_action) { 393 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 394 err = errno; 395 goto error; 396 } 397 #endif 398 if (!sh->tunnel_hub && priv->config.dv_miss_info) 399 err = mlx5_alloc_tunnel_hub(sh); 400 if (err) { 401 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 402 goto error; 403 } 404 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 405 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 406 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 407 if (sh->fdb_domain) 408 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 409 } 410 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 411 if (!priv->config.allow_duplicate_pattern) { 412 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 413 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 414 #endif 415 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 416 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 417 if (sh->fdb_domain) 418 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 419 } 420 421 __mlx5_discovery_misc5_cap(priv); 422 #endif /* HAVE_MLX5DV_DR */ 423 sh->default_miss_action = 424 mlx5_glue->dr_create_flow_action_default_miss(); 425 if (!sh->default_miss_action) 426 DRV_LOG(WARNING, "Default miss action is not supported."); 427 LIST_INIT(&sh->shared_rxqs); 428 return 0; 429 error: 430 /* Rollback the created objects. */ 431 if (sh->rx_domain) { 432 mlx5_glue->dr_destroy_domain(sh->rx_domain); 433 sh->rx_domain = NULL; 434 } 435 if (sh->tx_domain) { 436 mlx5_glue->dr_destroy_domain(sh->tx_domain); 437 sh->tx_domain = NULL; 438 } 439 if (sh->fdb_domain) { 440 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 441 sh->fdb_domain = NULL; 442 } 443 if (sh->dr_drop_action) { 444 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 445 sh->dr_drop_action = NULL; 446 } 447 if (sh->pop_vlan_action) { 448 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 449 sh->pop_vlan_action = NULL; 450 } 451 if (sh->encaps_decaps) { 452 mlx5_hlist_destroy(sh->encaps_decaps); 453 sh->encaps_decaps = NULL; 454 } 455 if (sh->modify_cmds) { 456 mlx5_hlist_destroy(sh->modify_cmds); 457 sh->modify_cmds = NULL; 458 } 459 if (sh->tag_table) { 460 /* tags should be destroyed with flow before. */ 461 mlx5_hlist_destroy(sh->tag_table); 462 sh->tag_table = NULL; 463 } 464 if (sh->tunnel_hub) { 465 mlx5_release_tunnel_hub(sh, priv->dev_port); 466 sh->tunnel_hub = NULL; 467 } 468 mlx5_free_table_hash_list(priv); 469 if (sh->port_id_action_list) { 470 mlx5_list_destroy(sh->port_id_action_list); 471 sh->port_id_action_list = NULL; 472 } 473 if (sh->push_vlan_action_list) { 474 mlx5_list_destroy(sh->push_vlan_action_list); 475 sh->push_vlan_action_list = NULL; 476 } 477 if (sh->sample_action_list) { 478 mlx5_list_destroy(sh->sample_action_list); 479 sh->sample_action_list = NULL; 480 } 481 if (sh->dest_array_list) { 482 mlx5_list_destroy(sh->dest_array_list); 483 sh->dest_array_list = NULL; 484 } 485 return err; 486 } 487 488 /** 489 * Destroy DR related data within private structure. 490 * 491 * @param[in] priv 492 * Pointer to the private device data structure. 493 */ 494 void 495 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 496 { 497 struct mlx5_dev_ctx_shared *sh = priv->sh; 498 499 MLX5_ASSERT(sh && sh->refcnt); 500 if (sh->refcnt > 1) 501 return; 502 MLX5_ASSERT(LIST_EMPTY(&sh->shared_rxqs)); 503 #ifdef HAVE_MLX5DV_DR 504 if (sh->rx_domain) { 505 mlx5_glue->dr_destroy_domain(sh->rx_domain); 506 sh->rx_domain = NULL; 507 } 508 if (sh->tx_domain) { 509 mlx5_glue->dr_destroy_domain(sh->tx_domain); 510 sh->tx_domain = NULL; 511 } 512 #ifdef HAVE_MLX5DV_DR_ESWITCH 513 if (sh->fdb_domain) { 514 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 515 sh->fdb_domain = NULL; 516 } 517 if (sh->dr_drop_action) { 518 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 519 sh->dr_drop_action = NULL; 520 } 521 #endif 522 if (sh->pop_vlan_action) { 523 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 524 sh->pop_vlan_action = NULL; 525 } 526 #endif /* HAVE_MLX5DV_DR */ 527 if (sh->default_miss_action) 528 mlx5_glue->destroy_flow_action 529 (sh->default_miss_action); 530 if (sh->encaps_decaps) { 531 mlx5_hlist_destroy(sh->encaps_decaps); 532 sh->encaps_decaps = NULL; 533 } 534 if (sh->modify_cmds) { 535 mlx5_hlist_destroy(sh->modify_cmds); 536 sh->modify_cmds = NULL; 537 } 538 if (sh->tag_table) { 539 /* tags should be destroyed with flow before. */ 540 mlx5_hlist_destroy(sh->tag_table); 541 sh->tag_table = NULL; 542 } 543 if (sh->tunnel_hub) { 544 mlx5_release_tunnel_hub(sh, priv->dev_port); 545 sh->tunnel_hub = NULL; 546 } 547 mlx5_free_table_hash_list(priv); 548 if (sh->port_id_action_list) { 549 mlx5_list_destroy(sh->port_id_action_list); 550 sh->port_id_action_list = NULL; 551 } 552 if (sh->push_vlan_action_list) { 553 mlx5_list_destroy(sh->push_vlan_action_list); 554 sh->push_vlan_action_list = NULL; 555 } 556 if (sh->sample_action_list) { 557 mlx5_list_destroy(sh->sample_action_list); 558 sh->sample_action_list = NULL; 559 } 560 if (sh->dest_array_list) { 561 mlx5_list_destroy(sh->dest_array_list); 562 sh->dest_array_list = NULL; 563 } 564 } 565 566 /** 567 * Initialize shared data between primary and secondary process. 568 * 569 * A memzone is reserved by primary process and secondary processes attach to 570 * the memzone. 571 * 572 * @return 573 * 0 on success, a negative errno value otherwise and rte_errno is set. 574 */ 575 static int 576 mlx5_init_shared_data(void) 577 { 578 const struct rte_memzone *mz; 579 int ret = 0; 580 581 rte_spinlock_lock(&mlx5_shared_data_lock); 582 if (mlx5_shared_data == NULL) { 583 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 584 /* Allocate shared memory. */ 585 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 586 sizeof(*mlx5_shared_data), 587 SOCKET_ID_ANY, 0); 588 if (mz == NULL) { 589 DRV_LOG(ERR, 590 "Cannot allocate mlx5 shared data"); 591 ret = -rte_errno; 592 goto error; 593 } 594 mlx5_shared_data = mz->addr; 595 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 596 rte_spinlock_init(&mlx5_shared_data->lock); 597 } else { 598 /* Lookup allocated shared memory. */ 599 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 600 if (mz == NULL) { 601 DRV_LOG(ERR, 602 "Cannot attach mlx5 shared data"); 603 ret = -rte_errno; 604 goto error; 605 } 606 mlx5_shared_data = mz->addr; 607 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 608 } 609 } 610 error: 611 rte_spinlock_unlock(&mlx5_shared_data_lock); 612 return ret; 613 } 614 615 /** 616 * PMD global initialization. 617 * 618 * Independent from individual device, this function initializes global 619 * per-PMD data structures distinguishing primary and secondary processes. 620 * Hence, each initialization is called once per a process. 621 * 622 * @return 623 * 0 on success, a negative errno value otherwise and rte_errno is set. 624 */ 625 static int 626 mlx5_init_once(void) 627 { 628 struct mlx5_shared_data *sd; 629 struct mlx5_local_data *ld = &mlx5_local_data; 630 int ret = 0; 631 632 if (mlx5_init_shared_data()) 633 return -rte_errno; 634 sd = mlx5_shared_data; 635 MLX5_ASSERT(sd); 636 rte_spinlock_lock(&sd->lock); 637 switch (rte_eal_process_type()) { 638 case RTE_PROC_PRIMARY: 639 if (sd->init_done) 640 break; 641 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 642 mlx5_mp_os_primary_handle); 643 if (ret) 644 goto out; 645 sd->init_done = true; 646 break; 647 case RTE_PROC_SECONDARY: 648 if (ld->init_done) 649 break; 650 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 651 mlx5_mp_os_secondary_handle); 652 if (ret) 653 goto out; 654 ++sd->secondary_cnt; 655 ld->init_done = true; 656 break; 657 default: 658 break; 659 } 660 out: 661 rte_spinlock_unlock(&sd->lock); 662 return ret; 663 } 664 665 /** 666 * DV flow counter mode detect and config. 667 * 668 * @param dev 669 * Pointer to rte_eth_dev structure. 670 * 671 */ 672 static void 673 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 674 { 675 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 676 struct mlx5_priv *priv = dev->data->dev_private; 677 struct mlx5_dev_ctx_shared *sh = priv->sh; 678 bool fallback; 679 680 #ifndef HAVE_IBV_DEVX_ASYNC 681 fallback = true; 682 #else 683 fallback = false; 684 if (!sh->devx || !priv->config.dv_flow_en || 685 !priv->config.hca_attr.flow_counters_dump || 686 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 687 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 688 fallback = true; 689 #endif 690 if (fallback) 691 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 692 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 693 priv->config.hca_attr.flow_counters_dump, 694 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 695 /* Initialize fallback mode only on the port initializes sh. */ 696 if (sh->refcnt == 1) 697 sh->cmng.counter_fallback = fallback; 698 else if (fallback != sh->cmng.counter_fallback) 699 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 700 "with others:%d.", PORT_ID(priv), fallback); 701 #endif 702 } 703 704 /** 705 * DR flow drop action support detect. 706 * 707 * @param dev 708 * Pointer to rte_eth_dev structure. 709 * 710 */ 711 static void 712 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 713 { 714 #ifdef HAVE_MLX5DV_DR 715 struct mlx5_priv *priv = dev->data->dev_private; 716 717 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action) 718 return; 719 /** 720 * DR supports drop action placeholder when it is supported; 721 * otherwise, use the queue drop action. 722 */ 723 if (!priv->sh->drop_action_check_flag) { 724 if (!mlx5_flow_discover_dr_action_support(dev)) 725 priv->sh->dr_drop_action_en = 1; 726 priv->sh->drop_action_check_flag = 1; 727 } 728 if (priv->sh->dr_drop_action_en) 729 priv->root_drop_action = priv->sh->dr_drop_action; 730 else 731 priv->root_drop_action = priv->drop_queue.hrxq->action; 732 #endif 733 } 734 735 static void 736 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 737 { 738 struct mlx5_priv *priv = dev->data->dev_private; 739 void *ctx = priv->sh->cdev->ctx; 740 741 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 742 if (!priv->q_counters) { 743 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 744 struct ibv_wq *wq; 745 746 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 747 "by DevX - fall-back to use the kernel driver global " 748 "queue counter.", dev->data->port_id); 749 /* Create WQ by kernel and query its queue counter ID. */ 750 if (cq) { 751 wq = mlx5_glue->create_wq(ctx, 752 &(struct ibv_wq_init_attr){ 753 .wq_type = IBV_WQT_RQ, 754 .max_wr = 1, 755 .max_sge = 1, 756 .pd = priv->sh->cdev->pd, 757 .cq = cq, 758 }); 759 if (wq) { 760 /* Counter is assigned only on RDY state. */ 761 int ret = mlx5_glue->modify_wq(wq, 762 &(struct ibv_wq_attr){ 763 .attr_mask = IBV_WQ_ATTR_STATE, 764 .wq_state = IBV_WQS_RDY, 765 }); 766 767 if (ret == 0) 768 mlx5_devx_cmd_wq_query(wq, 769 &priv->counter_set_id); 770 claim_zero(mlx5_glue->destroy_wq(wq)); 771 } 772 claim_zero(mlx5_glue->destroy_cq(cq)); 773 } 774 } else { 775 priv->counter_set_id = priv->q_counters->id; 776 } 777 if (priv->counter_set_id == 0) 778 DRV_LOG(INFO, "Part of the port %d statistics will not be " 779 "available.", dev->data->port_id); 780 } 781 782 /** 783 * Check if representor spawn info match devargs. 784 * 785 * @param spawn 786 * Verbs device parameters (name, port, switch_info) to spawn. 787 * @param eth_da 788 * Device devargs to probe. 789 * 790 * @return 791 * Match result. 792 */ 793 static bool 794 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 795 struct rte_eth_devargs *eth_da) 796 { 797 struct mlx5_switch_info *switch_info = &spawn->info; 798 unsigned int p, f; 799 uint16_t id; 800 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 801 eth_da->type); 802 803 switch (eth_da->type) { 804 case RTE_ETH_REPRESENTOR_SF: 805 if (!(spawn->info.port_name == -1 && 806 switch_info->name_type == 807 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 808 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 809 rte_errno = EBUSY; 810 return false; 811 } 812 break; 813 case RTE_ETH_REPRESENTOR_VF: 814 /* Allows HPF representor index -1 as exception. */ 815 if (!(spawn->info.port_name == -1 && 816 switch_info->name_type == 817 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 818 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 819 rte_errno = EBUSY; 820 return false; 821 } 822 break; 823 case RTE_ETH_REPRESENTOR_NONE: 824 rte_errno = EBUSY; 825 return false; 826 default: 827 rte_errno = ENOTSUP; 828 DRV_LOG(ERR, "unsupported representor type"); 829 return false; 830 } 831 /* Check representor ID: */ 832 for (p = 0; p < eth_da->nb_ports; ++p) { 833 if (spawn->pf_bond < 0) { 834 /* For non-LAG mode, allow and ignore pf. */ 835 switch_info->pf_num = eth_da->ports[p]; 836 repr_id = mlx5_representor_id_encode(switch_info, 837 eth_da->type); 838 } 839 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 840 id = MLX5_REPRESENTOR_ID 841 (eth_da->ports[p], eth_da->type, 842 eth_da->representor_ports[f]); 843 if (repr_id == id) 844 return true; 845 } 846 } 847 rte_errno = EBUSY; 848 return false; 849 } 850 851 /** 852 * Spawn an Ethernet device from Verbs information. 853 * 854 * @param dpdk_dev 855 * Backing DPDK device. 856 * @param spawn 857 * Verbs device parameters (name, port, switch_info) to spawn. 858 * @param config 859 * Device configuration parameters. 860 * @param eth_da 861 * Device arguments. 862 * 863 * @return 864 * A valid Ethernet device object on success, NULL otherwise and rte_errno 865 * is set. The following errors are defined: 866 * 867 * EBUSY: device is not supposed to be spawned. 868 * EEXIST: device is already spawned 869 */ 870 static struct rte_eth_dev * 871 mlx5_dev_spawn(struct rte_device *dpdk_dev, 872 struct mlx5_dev_spawn_data *spawn, 873 struct mlx5_dev_config *config, 874 struct rte_eth_devargs *eth_da) 875 { 876 const struct mlx5_switch_info *switch_info = &spawn->info; 877 struct mlx5_dev_ctx_shared *sh = NULL; 878 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; 879 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 880 struct rte_eth_dev *eth_dev = NULL; 881 struct mlx5_priv *priv = NULL; 882 int err = 0; 883 unsigned int hw_padding = 0; 884 unsigned int mps; 885 unsigned int mpls_en = 0; 886 unsigned int swp = 0; 887 unsigned int mprq = 0; 888 struct rte_ether_addr mac; 889 char name[RTE_ETH_NAME_MAX_LEN]; 890 int own_domain_id = 0; 891 uint16_t port_id; 892 struct mlx5_port_info vport_info = { .query_flags = 0 }; 893 int nl_rdma = -1; 894 int i; 895 896 /* Determine if this port representor is supposed to be spawned. */ 897 if (switch_info->representor && dpdk_dev->devargs && 898 !mlx5_representor_match(spawn, eth_da)) 899 return NULL; 900 /* Build device name. */ 901 if (spawn->pf_bond < 0) { 902 /* Single device. */ 903 if (!switch_info->representor) 904 strlcpy(name, dpdk_dev->name, sizeof(name)); 905 else 906 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 907 dpdk_dev->name, 908 switch_info->name_type == 909 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 910 switch_info->port_name); 911 } else { 912 /* Bonding device. */ 913 if (!switch_info->representor) { 914 err = snprintf(name, sizeof(name), "%s_%s", 915 dpdk_dev->name, spawn->phys_dev_name); 916 } else { 917 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 918 dpdk_dev->name, spawn->phys_dev_name, 919 switch_info->ctrl_num, 920 switch_info->pf_num, 921 switch_info->name_type == 922 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 923 switch_info->port_name); 924 } 925 } 926 if (err >= (int)sizeof(name)) 927 DRV_LOG(WARNING, "device name overflow %s", name); 928 /* check if the device is already spawned */ 929 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 930 rte_errno = EEXIST; 931 return NULL; 932 } 933 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 934 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 935 struct mlx5_mp_id mp_id; 936 937 eth_dev = rte_eth_dev_attach_secondary(name); 938 if (eth_dev == NULL) { 939 DRV_LOG(ERR, "can not attach rte ethdev"); 940 rte_errno = ENOMEM; 941 return NULL; 942 } 943 eth_dev->device = dpdk_dev; 944 eth_dev->dev_ops = &mlx5_dev_sec_ops; 945 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 946 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 947 err = mlx5_proc_priv_init(eth_dev); 948 if (err) 949 return NULL; 950 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 951 /* Receive command fd from primary process */ 952 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 953 if (err < 0) 954 goto err_secondary; 955 /* Remap UAR for Tx queues. */ 956 err = mlx5_tx_uar_init_secondary(eth_dev, err); 957 if (err) 958 goto err_secondary; 959 /* 960 * Ethdev pointer is still required as input since 961 * the primary device is not accessible from the 962 * secondary process. 963 */ 964 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 965 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 966 return eth_dev; 967 err_secondary: 968 mlx5_dev_close(eth_dev); 969 return NULL; 970 } 971 /* 972 * Some parameters ("tx_db_nc" in particularly) are needed in 973 * advance to create dv/verbs device context. We proceed the 974 * devargs here to get ones, and later proceed devargs again 975 * to override some hardware settings. 976 */ 977 err = mlx5_args(config, dpdk_dev->devargs); 978 if (err) { 979 err = rte_errno; 980 DRV_LOG(ERR, "failed to process device arguments: %s", 981 strerror(rte_errno)); 982 goto error; 983 } 984 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 985 if (!sh) 986 return NULL; 987 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 988 config->dest_tir = 1; 989 #endif 990 #ifdef HAVE_IBV_MLX5_MOD_SWP 991 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 992 #endif 993 /* 994 * Multi-packet send is supported by ConnectX-4 Lx PF as well 995 * as all ConnectX-5 devices. 996 */ 997 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 998 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 999 #endif 1000 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1001 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1002 #endif 1003 mlx5_glue->dv_query_device(sh->cdev->ctx, &dv_attr); 1004 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1005 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1006 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1007 mps = MLX5_MPW_ENHANCED; 1008 } else { 1009 DRV_LOG(DEBUG, "MPW is supported"); 1010 mps = MLX5_MPW; 1011 } 1012 } else { 1013 DRV_LOG(DEBUG, "MPW isn't supported"); 1014 mps = MLX5_MPW_DISABLED; 1015 } 1016 #ifdef HAVE_IBV_MLX5_MOD_SWP 1017 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1018 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1019 DRV_LOG(DEBUG, "SWP support: %u", swp); 1020 #endif 1021 config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP | 1022 MLX5_SW_PARSING_TSO_CAP); 1023 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1024 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1025 struct mlx5dv_striding_rq_caps mprq_caps = 1026 dv_attr.striding_rq_caps; 1027 1028 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1029 mprq_caps.min_single_stride_log_num_of_bytes); 1030 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1031 mprq_caps.max_single_stride_log_num_of_bytes); 1032 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1033 mprq_caps.min_single_wqe_log_num_of_strides); 1034 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1035 mprq_caps.max_single_wqe_log_num_of_strides); 1036 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1037 mprq_caps.supported_qpts); 1038 DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %d", 1039 config->mprq.log_min_stride_wqe_size); 1040 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1041 mprq = 1; 1042 config->mprq.log_min_stride_size = 1043 mprq_caps.min_single_stride_log_num_of_bytes; 1044 config->mprq.log_max_stride_size = 1045 mprq_caps.max_single_stride_log_num_of_bytes; 1046 config->mprq.log_min_stride_num = 1047 mprq_caps.min_single_wqe_log_num_of_strides; 1048 config->mprq.log_max_stride_num = 1049 mprq_caps.max_single_wqe_log_num_of_strides; 1050 } 1051 #endif 1052 /* Rx CQE compression is enabled by default. */ 1053 config->cqe_comp = 1; 1054 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1055 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1056 config->tunnel_en = dv_attr.tunnel_offloads_caps & 1057 (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN | 1058 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE | 1059 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE); 1060 } 1061 if (config->tunnel_en) { 1062 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s", 1063 config->tunnel_en & 1064 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "", 1065 config->tunnel_en & 1066 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "", 1067 config->tunnel_en & 1068 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : "" 1069 ); 1070 } else { 1071 DRV_LOG(DEBUG, "tunnel offloading is not supported"); 1072 } 1073 #else 1074 DRV_LOG(WARNING, 1075 "tunnel offloading disabled due to old OFED/rdma-core version"); 1076 #endif 1077 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1078 mpls_en = ((dv_attr.tunnel_offloads_caps & 1079 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1080 (dv_attr.tunnel_offloads_caps & 1081 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1082 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1083 mpls_en ? "" : "not "); 1084 #else 1085 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1086 " old OFED/rdma-core version or firmware configuration"); 1087 #endif 1088 config->mpls_en = mpls_en; 1089 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1090 /* Check port status. */ 1091 if (spawn->phys_port <= UINT8_MAX) { 1092 /* Legacy Verbs api only support u8 port number. */ 1093 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port, 1094 &port_attr); 1095 if (err) { 1096 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1097 goto error; 1098 } 1099 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1100 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1101 err = EINVAL; 1102 goto error; 1103 } 1104 } else if (nl_rdma >= 0) { 1105 /* IB doesn't allow more than 255 ports, must be Ethernet. */ 1106 err = mlx5_nl_port_state(nl_rdma, 1107 spawn->phys_dev_name, 1108 spawn->phys_port); 1109 if (err < 0) { 1110 DRV_LOG(INFO, "Failed to get netlink port state: %s", 1111 strerror(rte_errno)); 1112 err = -rte_errno; 1113 goto error; 1114 } 1115 port_attr.state = (enum ibv_port_state)err; 1116 } 1117 if (port_attr.state != IBV_PORT_ACTIVE) 1118 DRV_LOG(INFO, "port is not active: \"%s\" (%d)", 1119 mlx5_glue->port_state_str(port_attr.state), 1120 port_attr.state); 1121 /* Allocate private eth device data. */ 1122 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1123 sizeof(*priv), 1124 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1125 if (priv == NULL) { 1126 DRV_LOG(ERR, "priv allocation failure"); 1127 err = ENOMEM; 1128 goto error; 1129 } 1130 priv->sh = sh; 1131 priv->dev_port = spawn->phys_port; 1132 priv->pci_dev = spawn->pci_dev; 1133 priv->mtu = RTE_ETHER_MTU; 1134 /* Some internal functions rely on Netlink sockets, open them now. */ 1135 priv->nl_socket_rdma = nl_rdma; 1136 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1137 priv->representor = !!switch_info->representor; 1138 priv->master = !!switch_info->master; 1139 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1140 priv->vport_meta_tag = 0; 1141 priv->vport_meta_mask = 0; 1142 priv->pf_bond = spawn->pf_bond; 1143 1144 DRV_LOG(DEBUG, 1145 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1146 priv->dev_port, dpdk_dev->bus->name, 1147 priv->pci_dev ? priv->pci_dev->name : "NONE", 1148 priv->master, priv->representor, priv->pf_bond); 1149 1150 /* 1151 * If we have E-Switch we should determine the vport attributes. 1152 * E-Switch may use either source vport field or reg_c[0] metadata 1153 * register to match on vport index. The engaged part of metadata 1154 * register is defined by mask. 1155 */ 1156 if (switch_info->representor || switch_info->master) { 1157 err = mlx5_glue->devx_port_query(sh->cdev->ctx, 1158 spawn->phys_port, 1159 &vport_info); 1160 if (err) { 1161 DRV_LOG(WARNING, 1162 "Cannot query devx port %d on device %s", 1163 spawn->phys_port, spawn->phys_dev_name); 1164 vport_info.query_flags = 0; 1165 } 1166 } 1167 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1168 priv->vport_meta_tag = vport_info.vport_meta_tag; 1169 priv->vport_meta_mask = vport_info.vport_meta_mask; 1170 if (!priv->vport_meta_mask) { 1171 DRV_LOG(ERR, 1172 "vport zero mask for port %d on bonding device %s", 1173 spawn->phys_port, spawn->phys_dev_name); 1174 err = ENOTSUP; 1175 goto error; 1176 } 1177 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1178 DRV_LOG(ERR, 1179 "Invalid vport tag for port %d on bonding device %s", 1180 spawn->phys_port, spawn->phys_dev_name); 1181 err = ENOTSUP; 1182 goto error; 1183 } 1184 } 1185 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1186 priv->vport_id = vport_info.vport_id; 1187 } else if (spawn->pf_bond >= 0 && 1188 (switch_info->representor || switch_info->master)) { 1189 DRV_LOG(ERR, 1190 "Cannot deduce vport index for port %d on bonding device %s", 1191 spawn->phys_port, spawn->phys_dev_name); 1192 err = ENOTSUP; 1193 goto error; 1194 } else { 1195 /* 1196 * Suppose vport index in compatible way. Kernel/rdma_core 1197 * support single E-Switch per PF configurations only and 1198 * vport_id field contains the vport index for associated VF, 1199 * which is deduced from representor port name. 1200 * For example, let's have the IB device port 10, it has 1201 * attached network device eth0, which has port name attribute 1202 * pf0vf2, we can deduce the VF number as 2, and set vport index 1203 * as 3 (2+1). This assigning schema should be changed if the 1204 * multiple E-Switch instances per PF configurations or/and PCI 1205 * subfunctions are added. 1206 */ 1207 priv->vport_id = switch_info->representor ? 1208 switch_info->port_name + 1 : -1; 1209 } 1210 priv->representor_id = mlx5_representor_id_encode(switch_info, 1211 eth_da->type); 1212 /* 1213 * Look for sibling devices in order to reuse their switch domain 1214 * if any, otherwise allocate one. 1215 */ 1216 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1217 const struct mlx5_priv *opriv = 1218 rte_eth_devices[port_id].data->dev_private; 1219 1220 if (!opriv || 1221 opriv->sh != priv->sh || 1222 opriv->domain_id == 1223 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1224 continue; 1225 priv->domain_id = opriv->domain_id; 1226 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1227 priv->dev_port, priv->domain_id); 1228 break; 1229 } 1230 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1231 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1232 if (err) { 1233 err = rte_errno; 1234 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1235 strerror(rte_errno)); 1236 goto error; 1237 } 1238 own_domain_id = 1; 1239 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1240 priv->dev_port, priv->domain_id); 1241 } 1242 /* Override some values set by hardware configuration. */ 1243 mlx5_args(config, dpdk_dev->devargs); 1244 /* Update final values for devargs before check sibling config. */ 1245 if (config->dv_miss_info) { 1246 if (switch_info->master || switch_info->representor) 1247 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1248 } 1249 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1250 if (config->dv_flow_en) { 1251 DRV_LOG(WARNING, "DV flow is not supported."); 1252 config->dv_flow_en = 0; 1253 } 1254 #endif 1255 #ifdef HAVE_MLX5DV_DR_ESWITCH 1256 if (!(sh->cdev->config.hca_attr.eswitch_manager && config->dv_flow_en && 1257 (switch_info->representor || switch_info->master))) 1258 config->dv_esw_en = 0; 1259 #else 1260 config->dv_esw_en = 0; 1261 #endif 1262 if (!priv->config.dv_esw_en && 1263 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1264 DRV_LOG(WARNING, 1265 "Metadata mode %u is not supported (no E-Switch).", 1266 priv->config.dv_xmeta_en); 1267 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1268 } 1269 /* Check sibling device configurations. */ 1270 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev); 1271 if (err) 1272 goto error; 1273 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1274 IBV_DEVICE_RAW_IP_CSUM); 1275 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1276 (config->hw_csum ? "" : "not ")); 1277 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1278 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1279 DRV_LOG(DEBUG, "counters are not supported"); 1280 #endif 1281 config->ind_table_max_size = 1282 sh->device_attr.max_rwq_indirection_table_size; 1283 /* 1284 * Remove this check once DPDK supports larger/variable 1285 * indirection tables. 1286 */ 1287 if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512) 1288 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512; 1289 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1290 config->ind_table_max_size); 1291 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1292 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1293 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1294 (config->hw_vlan_strip ? "" : "not ")); 1295 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1296 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1297 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1298 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1299 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1300 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1301 IBV_DEVICE_PCI_WRITE_END_PADDING); 1302 #endif 1303 if (config->hw_padding && !hw_padding) { 1304 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1305 config->hw_padding = 0; 1306 } else if (config->hw_padding) { 1307 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1308 } 1309 config->tso = (sh->device_attr.max_tso > 0 && 1310 (sh->device_attr.tso_supported_qpts & 1311 (1 << IBV_QPT_RAW_PACKET))); 1312 if (config->tso) 1313 config->tso_max_payload_sz = sh->device_attr.max_tso; 1314 /* 1315 * MPW is disabled by default, while the Enhanced MPW is enabled 1316 * by default. 1317 */ 1318 if (config->mps == MLX5_ARG_UNSET) 1319 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1320 MLX5_MPW_DISABLED; 1321 else 1322 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1323 DRV_LOG(INFO, "%sMPS is %s", 1324 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1325 config->mps == MLX5_MPW ? "legacy " : "", 1326 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1327 if (sh->devx) { 1328 config->hca_attr = sh->cdev->config.hca_attr; 1329 sh->steering_format_version = 1330 config->hca_attr.steering_format_version; 1331 /* Check for LRO support. */ 1332 if (config->dest_tir && config->hca_attr.lro_cap && 1333 config->dv_flow_en) { 1334 /* TBD check tunnel lro caps. */ 1335 config->lro.supported = config->hca_attr.lro_cap; 1336 DRV_LOG(DEBUG, "Device supports LRO"); 1337 /* 1338 * If LRO timeout is not configured by application, 1339 * use the minimal supported value. 1340 */ 1341 if (!config->lro.timeout) 1342 config->lro.timeout = 1343 config->hca_attr.lro_timer_supported_periods[0]; 1344 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1345 config->lro.timeout); 1346 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1347 "required for coalescing is %d bytes", 1348 config->hca_attr.lro_min_mss_size); 1349 } 1350 #if defined(HAVE_MLX5DV_DR) && \ 1351 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1352 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1353 if (config->hca_attr.qos.sup && 1354 config->hca_attr.qos.flow_meter_old && 1355 config->dv_flow_en) { 1356 uint8_t reg_c_mask = 1357 config->hca_attr.qos.flow_meter_reg_c_ids; 1358 /* 1359 * Meter needs two REG_C's for color match and pre-sfx 1360 * flow match. Here get the REG_C for color match. 1361 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1362 */ 1363 reg_c_mask &= 0xfc; 1364 if (__builtin_popcount(reg_c_mask) < 1) { 1365 priv->mtr_en = 0; 1366 DRV_LOG(WARNING, "No available register for" 1367 " meter."); 1368 } else { 1369 /* 1370 * The meter color register is used by the 1371 * flow-hit feature as well. 1372 * The flow-hit feature must use REG_C_3 1373 * Prefer REG_C_3 if it is available. 1374 */ 1375 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1376 priv->mtr_color_reg = REG_C_3; 1377 else 1378 priv->mtr_color_reg = ffs(reg_c_mask) 1379 - 1 + REG_C_0; 1380 priv->mtr_en = 1; 1381 priv->mtr_reg_share = 1382 config->hca_attr.qos.flow_meter; 1383 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1384 priv->mtr_color_reg); 1385 } 1386 } 1387 if (config->hca_attr.qos.sup && 1388 config->hca_attr.qos.flow_meter_aso_sup) { 1389 uint32_t log_obj_size = 1390 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1391 if (log_obj_size >= 1392 config->hca_attr.qos.log_meter_aso_granularity && 1393 log_obj_size <= 1394 config->hca_attr.qos.log_meter_aso_max_alloc) 1395 sh->meter_aso_en = 1; 1396 } 1397 if (priv->mtr_en) { 1398 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1399 if (err) { 1400 err = -err; 1401 goto error; 1402 } 1403 } 1404 if (config->hca_attr.flow.tunnel_header_0_1) 1405 sh->tunnel_header_0_1 = 1; 1406 #endif 1407 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1408 if (config->hca_attr.flow_hit_aso && 1409 priv->mtr_color_reg == REG_C_3) { 1410 sh->flow_hit_aso_en = 1; 1411 err = mlx5_flow_aso_age_mng_init(sh); 1412 if (err) { 1413 err = -err; 1414 goto error; 1415 } 1416 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1417 } 1418 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1419 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1420 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1421 if (config->hca_attr.ct_offload && 1422 priv->mtr_color_reg == REG_C_3) { 1423 err = mlx5_flow_aso_ct_mng_init(sh); 1424 if (err) { 1425 err = -err; 1426 goto error; 1427 } 1428 DRV_LOG(DEBUG, "CT ASO is supported."); 1429 sh->ct_aso_en = 1; 1430 } 1431 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1432 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1433 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1434 config->dv_flow_en) { 1435 priv->sampler_en = 1; 1436 DRV_LOG(DEBUG, "Sampler enabled!"); 1437 } else { 1438 priv->sampler_en = 0; 1439 if (!config->hca_attr.log_max_ft_sampler_num) 1440 DRV_LOG(WARNING, 1441 "No available register for sampler."); 1442 else 1443 DRV_LOG(DEBUG, "DV flow is not supported!"); 1444 } 1445 #endif 1446 } 1447 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1448 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1449 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1450 config->cqe_comp = 0; 1451 } 1452 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1453 (!sh->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1454 DRV_LOG(WARNING, "Flow Tag CQE compression" 1455 " format isn't supported."); 1456 config->cqe_comp = 0; 1457 } 1458 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1459 (!sh->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1460 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1461 " format isn't supported."); 1462 config->cqe_comp = 0; 1463 } 1464 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1465 config->cqe_comp ? "" : "not "); 1466 if (config->tx_pp) { 1467 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1468 config->hca_attr.dev_freq_khz); 1469 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1470 config->hca_attr.qos.packet_pacing ? "" : "not "); 1471 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1472 config->hca_attr.cross_channel ? "" : "not "); 1473 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1474 config->hca_attr.wqe_index_ignore ? "" : "not "); 1475 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1476 config->hca_attr.non_wire_sq ? "" : "not "); 1477 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1478 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1479 config->hca_attr.log_max_static_sq_wq); 1480 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1481 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1482 if (!sh->devx) { 1483 DRV_LOG(ERR, "DevX is required for packet pacing"); 1484 err = ENODEV; 1485 goto error; 1486 } 1487 if (!config->hca_attr.qos.packet_pacing) { 1488 DRV_LOG(ERR, "Packet pacing is not supported"); 1489 err = ENODEV; 1490 goto error; 1491 } 1492 if (!config->hca_attr.cross_channel) { 1493 DRV_LOG(ERR, "Cross channel operations are" 1494 " required for packet pacing"); 1495 err = ENODEV; 1496 goto error; 1497 } 1498 if (!config->hca_attr.wqe_index_ignore) { 1499 DRV_LOG(ERR, "WQE index ignore feature is" 1500 " required for packet pacing"); 1501 err = ENODEV; 1502 goto error; 1503 } 1504 if (!config->hca_attr.non_wire_sq) { 1505 DRV_LOG(ERR, "Non-wire SQ feature is" 1506 " required for packet pacing"); 1507 err = ENODEV; 1508 goto error; 1509 } 1510 if (!config->hca_attr.log_max_static_sq_wq) { 1511 DRV_LOG(ERR, "Static WQE SQ feature is" 1512 " required for packet pacing"); 1513 err = ENODEV; 1514 goto error; 1515 } 1516 if (!config->hca_attr.qos.wqe_rate_pp) { 1517 DRV_LOG(ERR, "WQE rate mode is required" 1518 " for packet pacing"); 1519 err = ENODEV; 1520 goto error; 1521 } 1522 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1523 DRV_LOG(ERR, "DevX does not provide UAR offset," 1524 " can't create queues for packet pacing"); 1525 err = ENODEV; 1526 goto error; 1527 #endif 1528 } 1529 if (config->std_delay_drop || config->hp_delay_drop) { 1530 if (!config->hca_attr.rq_delay_drop) { 1531 config->std_delay_drop = 0; 1532 config->hp_delay_drop = 0; 1533 DRV_LOG(WARNING, 1534 "dev_port-%u: Rxq delay drop is not supported", 1535 priv->dev_port); 1536 } 1537 } 1538 if (sh->devx) { 1539 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1540 1541 err = config->hca_attr.access_register_user ? 1542 mlx5_devx_cmd_register_read 1543 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1544 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1545 if (!err) { 1546 uint32_t ts_mode; 1547 1548 /* MTUTC register is read successfully. */ 1549 ts_mode = MLX5_GET(register_mtutc, reg, 1550 time_stamp_mode); 1551 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1552 config->rt_timestamp = 1; 1553 } else { 1554 /* Kernel does not support register reading. */ 1555 if (config->hca_attr.dev_freq_khz == 1556 (NS_PER_S / MS_PER_S)) 1557 config->rt_timestamp = 1; 1558 } 1559 } 1560 /* 1561 * If HW has bug working with tunnel packet decapsulation and 1562 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1563 * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1564 */ 1565 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1566 config->hw_fcs_strip = 0; 1567 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1568 (config->hw_fcs_strip ? "" : "not ")); 1569 if (config->mprq.enabled && !mprq) { 1570 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1571 config->mprq.enabled = 0; 1572 } 1573 if (config->max_dump_files_num == 0) 1574 config->max_dump_files_num = 128; 1575 eth_dev = rte_eth_dev_allocate(name); 1576 if (eth_dev == NULL) { 1577 DRV_LOG(ERR, "can not allocate rte ethdev"); 1578 err = ENOMEM; 1579 goto error; 1580 } 1581 if (priv->representor) { 1582 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1583 eth_dev->data->representor_id = priv->representor_id; 1584 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1585 struct mlx5_priv *opriv = 1586 rte_eth_devices[port_id].data->dev_private; 1587 if (opriv && 1588 opriv->master && 1589 opriv->domain_id == priv->domain_id && 1590 opriv->sh == priv->sh) { 1591 eth_dev->data->backer_port_id = port_id; 1592 break; 1593 } 1594 } 1595 if (port_id >= RTE_MAX_ETHPORTS) 1596 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1597 } 1598 priv->mp_id.port_id = eth_dev->data->port_id; 1599 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1600 /* 1601 * Store associated network device interface index. This index 1602 * is permanent throughout the lifetime of device. So, we may store 1603 * the ifindex here and use the cached value further. 1604 */ 1605 MLX5_ASSERT(spawn->ifindex); 1606 priv->if_index = spawn->ifindex; 1607 priv->lag_affinity_idx = sh->refcnt - 1; 1608 eth_dev->data->dev_private = priv; 1609 priv->dev_data = eth_dev->data; 1610 eth_dev->data->mac_addrs = priv->mac; 1611 eth_dev->device = dpdk_dev; 1612 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1613 /* Configure the first MAC address by default. */ 1614 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1615 DRV_LOG(ERR, 1616 "port %u cannot get MAC address, is mlx5_en" 1617 " loaded? (errno: %s)", 1618 eth_dev->data->port_id, strerror(rte_errno)); 1619 err = ENODEV; 1620 goto error; 1621 } 1622 DRV_LOG(INFO, 1623 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1624 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1625 #ifdef RTE_LIBRTE_MLX5_DEBUG 1626 { 1627 char ifname[MLX5_NAMESIZE]; 1628 1629 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1630 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1631 eth_dev->data->port_id, ifname); 1632 else 1633 DRV_LOG(DEBUG, "port %u ifname is unknown", 1634 eth_dev->data->port_id); 1635 } 1636 #endif 1637 /* Get actual MTU if possible. */ 1638 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1639 if (err) { 1640 err = rte_errno; 1641 goto error; 1642 } 1643 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1644 priv->mtu); 1645 /* Initialize burst functions to prevent crashes before link-up. */ 1646 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 1647 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 1648 eth_dev->dev_ops = &mlx5_dev_ops; 1649 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1650 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1651 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1652 /* Register MAC address. */ 1653 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1654 if (config->vf && config->vf_nl_en) 1655 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1656 mlx5_ifindex(eth_dev), 1657 eth_dev->data->mac_addrs, 1658 MLX5_MAX_MAC_ADDRESSES); 1659 priv->ctrl_flows = 0; 1660 rte_spinlock_init(&priv->flow_list_lock); 1661 TAILQ_INIT(&priv->flow_meters); 1662 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1663 if (!priv->mtr_profile_tbl) 1664 goto error; 1665 /* Bring Ethernet device up. */ 1666 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1667 eth_dev->data->port_id); 1668 mlx5_set_link_up(eth_dev); 1669 /* 1670 * Even though the interrupt handler is not installed yet, 1671 * interrupts will still trigger on the async_fd from 1672 * Verbs context returned by ibv_open_device(). 1673 */ 1674 mlx5_link_update(eth_dev, 0); 1675 /* Detect minimal data bytes to inline. */ 1676 mlx5_set_min_inline(spawn, config); 1677 /* Store device configuration on private structure. */ 1678 priv->config = *config; 1679 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1680 icfg[i].release_mem_en = !!config->reclaim_mode; 1681 if (config->reclaim_mode) 1682 icfg[i].per_core_cache = 0; 1683 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1684 if (!priv->flows[i]) 1685 goto error; 1686 } 1687 /* Create context for virtual machine VLAN workaround. */ 1688 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1689 if (config->dv_flow_en) { 1690 err = mlx5_alloc_shared_dr(priv); 1691 if (err) 1692 goto error; 1693 if (mlx5_flex_item_port_init(eth_dev) < 0) 1694 goto error; 1695 } 1696 if (sh->devx && config->dv_flow_en && config->dest_tir) { 1697 priv->obj_ops = devx_obj_ops; 1698 mlx5_queue_counter_id_prepare(eth_dev); 1699 priv->obj_ops.lb_dummy_queue_create = 1700 mlx5_rxq_ibv_obj_dummy_lb_create; 1701 priv->obj_ops.lb_dummy_queue_release = 1702 mlx5_rxq_ibv_obj_dummy_lb_release; 1703 } else if (spawn->max_port > UINT8_MAX) { 1704 /* Verbs can't support ports larger than 255 by design. */ 1705 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); 1706 err = ENOTSUP; 1707 goto error; 1708 } else { 1709 priv->obj_ops = ibv_obj_ops; 1710 } 1711 if (config->tx_pp && 1712 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new) { 1713 /* 1714 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1715 * packet pacing and already checked above. 1716 * Hence, we should only make sure the SQs will be created 1717 * with DevX, not with Verbs. 1718 * Verbs allocates the SQ UAR on its own and it can't be shared 1719 * with Clock Queue UAR as required for Tx scheduling. 1720 */ 1721 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1722 err = ENODEV; 1723 goto error; 1724 } 1725 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1726 if (!priv->drop_queue.hrxq) 1727 goto error; 1728 /* Port representor shares the same max priority with pf port. */ 1729 if (!priv->sh->flow_priority_check_flag) { 1730 /* Supported Verbs flow priority number detection. */ 1731 err = mlx5_flow_discover_priorities(eth_dev); 1732 priv->sh->flow_max_priority = err; 1733 priv->sh->flow_priority_check_flag = 1; 1734 } else { 1735 err = priv->sh->flow_max_priority; 1736 } 1737 if (err < 0) { 1738 err = -err; 1739 goto error; 1740 } 1741 mlx5_set_metadata_mask(eth_dev); 1742 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1743 !priv->sh->dv_regc0_mask) { 1744 DRV_LOG(ERR, "metadata mode %u is not supported " 1745 "(no metadata reg_c[0] is available)", 1746 priv->config.dv_xmeta_en); 1747 err = ENOTSUP; 1748 goto error; 1749 } 1750 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1751 mlx5_hrxq_create_cb, 1752 mlx5_hrxq_match_cb, 1753 mlx5_hrxq_remove_cb, 1754 mlx5_hrxq_clone_cb, 1755 mlx5_hrxq_clone_free_cb); 1756 if (!priv->hrxqs) 1757 goto error; 1758 rte_rwlock_init(&priv->ind_tbls_lock); 1759 /* Query availability of metadata reg_c's. */ 1760 if (!priv->sh->metadata_regc_check_flag) { 1761 err = mlx5_flow_discover_mreg_c(eth_dev); 1762 if (err < 0) { 1763 err = -err; 1764 goto error; 1765 } 1766 } 1767 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1768 DRV_LOG(DEBUG, 1769 "port %u extensive metadata register is not supported", 1770 eth_dev->data->port_id); 1771 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1772 DRV_LOG(ERR, "metadata mode %u is not supported " 1773 "(no metadata registers available)", 1774 priv->config.dv_xmeta_en); 1775 err = ENOTSUP; 1776 goto error; 1777 } 1778 } 1779 if (priv->config.dv_flow_en && 1780 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1781 mlx5_flow_ext_mreg_supported(eth_dev) && 1782 priv->sh->dv_regc0_mask) { 1783 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1784 MLX5_FLOW_MREG_HTABLE_SZ, 1785 false, true, eth_dev, 1786 flow_dv_mreg_create_cb, 1787 flow_dv_mreg_match_cb, 1788 flow_dv_mreg_remove_cb, 1789 flow_dv_mreg_clone_cb, 1790 flow_dv_mreg_clone_free_cb); 1791 if (!priv->mreg_cp_tbl) { 1792 err = ENOMEM; 1793 goto error; 1794 } 1795 } 1796 rte_spinlock_init(&priv->shared_act_sl); 1797 mlx5_flow_counter_mode_config(eth_dev); 1798 mlx5_flow_drop_action_config(eth_dev); 1799 if (priv->config.dv_flow_en) 1800 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1801 return eth_dev; 1802 error: 1803 if (priv) { 1804 if (priv->mreg_cp_tbl) 1805 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1806 if (priv->sh) 1807 mlx5_os_free_shared_dr(priv); 1808 if (priv->nl_socket_route >= 0) 1809 close(priv->nl_socket_route); 1810 if (priv->vmwa_context) 1811 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1812 if (eth_dev && priv->drop_queue.hrxq) 1813 mlx5_drop_action_destroy(eth_dev); 1814 if (priv->mtr_profile_tbl) 1815 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1816 if (own_domain_id) 1817 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1818 if (priv->hrxqs) 1819 mlx5_list_destroy(priv->hrxqs); 1820 if (eth_dev && priv->flex_item_map) 1821 mlx5_flex_item_port_cleanup(eth_dev); 1822 mlx5_free(priv); 1823 if (eth_dev != NULL) 1824 eth_dev->data->dev_private = NULL; 1825 } 1826 if (eth_dev != NULL) { 1827 /* mac_addrs must not be freed alone because part of 1828 * dev_private 1829 **/ 1830 eth_dev->data->mac_addrs = NULL; 1831 rte_eth_dev_release_port(eth_dev); 1832 } 1833 if (sh) 1834 mlx5_free_shared_dev_ctx(sh); 1835 if (nl_rdma >= 0) 1836 close(nl_rdma); 1837 MLX5_ASSERT(err > 0); 1838 rte_errno = err; 1839 return NULL; 1840 } 1841 1842 /** 1843 * Comparison callback to sort device data. 1844 * 1845 * This is meant to be used with qsort(). 1846 * 1847 * @param a[in] 1848 * Pointer to pointer to first data object. 1849 * @param b[in] 1850 * Pointer to pointer to second data object. 1851 * 1852 * @return 1853 * 0 if both objects are equal, less than 0 if the first argument is less 1854 * than the second, greater than 0 otherwise. 1855 */ 1856 static int 1857 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1858 { 1859 const struct mlx5_switch_info *si_a = 1860 &((const struct mlx5_dev_spawn_data *)a)->info; 1861 const struct mlx5_switch_info *si_b = 1862 &((const struct mlx5_dev_spawn_data *)b)->info; 1863 int ret; 1864 1865 /* Master device first. */ 1866 ret = si_b->master - si_a->master; 1867 if (ret) 1868 return ret; 1869 /* Then representor devices. */ 1870 ret = si_b->representor - si_a->representor; 1871 if (ret) 1872 return ret; 1873 /* Unidentified devices come last in no specific order. */ 1874 if (!si_a->representor) 1875 return 0; 1876 /* Order representors by name. */ 1877 return si_a->port_name - si_b->port_name; 1878 } 1879 1880 /** 1881 * Match PCI information for possible slaves of bonding device. 1882 * 1883 * @param[in] ibdev_name 1884 * Name of Infiniband device. 1885 * @param[in] pci_dev 1886 * Pointer to primary PCI address structure to match. 1887 * @param[in] nl_rdma 1888 * Netlink RDMA group socket handle. 1889 * @param[in] owner 1890 * Representor owner PF index. 1891 * @param[out] bond_info 1892 * Pointer to bonding information. 1893 * 1894 * @return 1895 * negative value if no bonding device found, otherwise 1896 * positive index of slave PF in bonding. 1897 */ 1898 static int 1899 mlx5_device_bond_pci_match(const char *ibdev_name, 1900 const struct rte_pci_addr *pci_dev, 1901 int nl_rdma, uint16_t owner, 1902 struct mlx5_bond_info *bond_info) 1903 { 1904 char ifname[IF_NAMESIZE + 1]; 1905 unsigned int ifindex; 1906 unsigned int np, i; 1907 FILE *bond_file = NULL, *file; 1908 int pf = -1; 1909 int ret; 1910 uint8_t cur_guid[32] = {0}; 1911 uint8_t guid[32] = {0}; 1912 1913 /* 1914 * Try to get master device name. If something goes wrong suppose 1915 * the lack of kernel support and no bonding devices. 1916 */ 1917 memset(bond_info, 0, sizeof(*bond_info)); 1918 if (nl_rdma < 0) 1919 return -1; 1920 if (!strstr(ibdev_name, "bond")) 1921 return -1; 1922 np = mlx5_nl_portnum(nl_rdma, ibdev_name); 1923 if (!np) 1924 return -1; 1925 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) 1926 return -1; 1927 /* 1928 * The master device might not be on the predefined port(not on port 1929 * index 1, it is not guaranteed), we have to scan all Infiniband 1930 * device ports and find master. 1931 */ 1932 for (i = 1; i <= np; ++i) { 1933 /* Check whether Infiniband port is populated. */ 1934 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); 1935 if (!ifindex) 1936 continue; 1937 if (!if_indextoname(ifindex, ifname)) 1938 continue; 1939 /* Try to read bonding slave names from sysfs. */ 1940 MKSTR(slaves, 1941 "/sys/class/net/%s/master/bonding/slaves", ifname); 1942 bond_file = fopen(slaves, "r"); 1943 if (bond_file) 1944 break; 1945 } 1946 if (!bond_file) 1947 return -1; 1948 /* Use safe format to check maximal buffer length. */ 1949 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1950 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1951 char tmp_str[IF_NAMESIZE + 32]; 1952 struct rte_pci_addr pci_addr; 1953 struct mlx5_switch_info info; 1954 int ret; 1955 1956 /* Process slave interface names in the loop. */ 1957 snprintf(tmp_str, sizeof(tmp_str), 1958 "/sys/class/net/%s", ifname); 1959 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 1960 DRV_LOG(WARNING, 1961 "Cannot get PCI address for netdev \"%s\".", 1962 ifname); 1963 continue; 1964 } 1965 /* Slave interface PCI address match found. */ 1966 snprintf(tmp_str, sizeof(tmp_str), 1967 "/sys/class/net/%s/phys_port_name", ifname); 1968 file = fopen(tmp_str, "rb"); 1969 if (!file) 1970 break; 1971 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1972 if (fscanf(file, "%32s", tmp_str) == 1) 1973 mlx5_translate_port_name(tmp_str, &info); 1974 fclose(file); 1975 /* Only process PF ports. */ 1976 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1977 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1978 continue; 1979 /* Check max bonding member. */ 1980 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1981 DRV_LOG(WARNING, "bonding index out of range, " 1982 "please increase MLX5_BOND_MAX_PORTS: %s", 1983 tmp_str); 1984 break; 1985 } 1986 /* Get ifindex. */ 1987 snprintf(tmp_str, sizeof(tmp_str), 1988 "/sys/class/net/%s/ifindex", ifname); 1989 file = fopen(tmp_str, "rb"); 1990 if (!file) 1991 break; 1992 ret = fscanf(file, "%u", &ifindex); 1993 fclose(file); 1994 if (ret != 1) 1995 break; 1996 /* Save bonding info. */ 1997 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1998 sizeof(bond_info->ports[0].ifname)); 1999 bond_info->ports[info.port_name].pci_addr = pci_addr; 2000 bond_info->ports[info.port_name].ifindex = ifindex; 2001 bond_info->n_port++; 2002 /* 2003 * Under socket direct mode, bonding will use 2004 * system_image_guid as identification. 2005 * After OFED 5.4, guid is readable (ret >= 0) under sysfs. 2006 * All bonding members should have the same guid even if driver 2007 * is using PCIe BDF. 2008 */ 2009 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid)); 2010 if (ret < 0) 2011 break; 2012 else if (ret > 0) { 2013 if (!memcmp(guid, cur_guid, sizeof(guid)) && 2014 owner == info.port_name && 2015 (owner != 0 || (owner == 0 && 2016 !rte_pci_addr_cmp(pci_dev, &pci_addr)))) 2017 pf = info.port_name; 2018 } else if (pci_dev->domain == pci_addr.domain && 2019 pci_dev->bus == pci_addr.bus && 2020 pci_dev->devid == pci_addr.devid && 2021 ((pci_dev->function == 0 && 2022 pci_dev->function + owner == pci_addr.function) || 2023 (pci_dev->function == owner && 2024 pci_addr.function == owner))) 2025 pf = info.port_name; 2026 } 2027 if (pf >= 0) { 2028 /* Get bond interface info */ 2029 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2030 bond_info->ifname); 2031 if (ret) 2032 DRV_LOG(ERR, "unable to get bond info: %s", 2033 strerror(rte_errno)); 2034 else 2035 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2036 ifindex, bond_info->ifindex, bond_info->ifname); 2037 } 2038 if (owner == 0 && pf != 0) { 2039 DRV_LOG(INFO, "PCIe instance %04x:%02x:%02x.%x isn't bonding owner", 2040 pci_dev->domain, pci_dev->bus, pci_dev->devid, 2041 pci_dev->function); 2042 } 2043 return pf; 2044 } 2045 2046 static void 2047 mlx5_os_config_default(struct mlx5_dev_config *config, 2048 struct mlx5_common_dev_config *cconf) 2049 { 2050 memset(config, 0, sizeof(*config)); 2051 config->mps = MLX5_ARG_UNSET; 2052 config->rx_vec_en = 1; 2053 config->txq_inline_max = MLX5_ARG_UNSET; 2054 config->txq_inline_min = MLX5_ARG_UNSET; 2055 config->txq_inline_mpw = MLX5_ARG_UNSET; 2056 config->txqs_inline = MLX5_ARG_UNSET; 2057 config->vf_nl_en = 1; 2058 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2059 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2060 config->mprq.log_min_stride_wqe_size = cconf->devx ? 2061 cconf->hca_attr.log_min_stride_wqe_sz : 2062 MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 2063 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; 2064 config->dv_esw_en = 1; 2065 config->dv_flow_en = 1; 2066 config->decap_en = 1; 2067 config->log_hp_size = MLX5_ARG_UNSET; 2068 config->allow_duplicate_pattern = 1; 2069 config->std_delay_drop = 0; 2070 config->hp_delay_drop = 0; 2071 } 2072 2073 /** 2074 * Register a PCI device within bonding. 2075 * 2076 * This function spawns Ethernet devices out of a given PCI device and 2077 * bonding owner PF index. 2078 * 2079 * @param[in] cdev 2080 * Pointer to common mlx5 device structure. 2081 * @param[in] req_eth_da 2082 * Requested ethdev device argument. 2083 * @param[in] owner_id 2084 * Requested owner PF port ID within bonding device, default to 0. 2085 * 2086 * @return 2087 * 0 on success, a negative errno value otherwise and rte_errno is set. 2088 */ 2089 static int 2090 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, 2091 struct rte_eth_devargs *req_eth_da, 2092 uint16_t owner_id) 2093 { 2094 struct ibv_device **ibv_list; 2095 /* 2096 * Number of found IB Devices matching with requested PCI BDF. 2097 * nd != 1 means there are multiple IB devices over the same 2098 * PCI device and we have representors and master. 2099 */ 2100 unsigned int nd = 0; 2101 /* 2102 * Number of found IB device Ports. nd = 1 and np = 1..n means 2103 * we have the single multiport IB device, and there may be 2104 * representors attached to some of found ports. 2105 */ 2106 unsigned int np = 0; 2107 /* 2108 * Number of DPDK ethernet devices to Spawn - either over 2109 * multiple IB devices or multiple ports of single IB device. 2110 * Actually this is the number of iterations to spawn. 2111 */ 2112 unsigned int ns = 0; 2113 /* 2114 * Bonding device 2115 * < 0 - no bonding device (single one) 2116 * >= 0 - bonding device (value is slave PF index) 2117 */ 2118 int bd = -1; 2119 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2120 struct mlx5_dev_spawn_data *list = NULL; 2121 struct mlx5_dev_config dev_config; 2122 unsigned int dev_config_vf; 2123 struct rte_eth_devargs eth_da = *req_eth_da; 2124 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2125 struct mlx5_bond_info bond_info; 2126 int ret = -1; 2127 2128 errno = 0; 2129 ibv_list = mlx5_glue->get_device_list(&ret); 2130 if (!ibv_list) { 2131 rte_errno = errno ? errno : ENOSYS; 2132 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?"); 2133 return -rte_errno; 2134 } 2135 /* 2136 * First scan the list of all Infiniband devices to find 2137 * matching ones, gathering into the list. 2138 */ 2139 struct ibv_device *ibv_match[ret + 1]; 2140 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2141 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2142 unsigned int i; 2143 2144 while (ret-- > 0) { 2145 struct rte_pci_addr pci_addr; 2146 2147 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); 2148 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, 2149 nl_rdma, owner_id, &bond_info); 2150 if (bd >= 0) { 2151 /* 2152 * Bonding device detected. Only one match is allowed, 2153 * the bonding is supported over multi-port IB device, 2154 * there should be no matches on representor PCI 2155 * functions or non VF LAG bonding devices with 2156 * specified address. 2157 */ 2158 if (nd) { 2159 DRV_LOG(ERR, 2160 "multiple PCI match on bonding device" 2161 "\"%s\" found", ibv_list[ret]->name); 2162 rte_errno = ENOENT; 2163 ret = -rte_errno; 2164 goto exit; 2165 } 2166 /* Amend owner pci address if owner PF ID specified. */ 2167 if (eth_da.nb_representor_ports) 2168 owner_pci.function += owner_id; 2169 DRV_LOG(INFO, 2170 "PCI information matches for slave %d bonding device \"%s\"", 2171 bd, ibv_list[ret]->name); 2172 ibv_match[nd++] = ibv_list[ret]; 2173 break; 2174 } else { 2175 /* Bonding device not found. */ 2176 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2177 &pci_addr)) 2178 continue; 2179 if (owner_pci.domain != pci_addr.domain || 2180 owner_pci.bus != pci_addr.bus || 2181 owner_pci.devid != pci_addr.devid || 2182 owner_pci.function != pci_addr.function) 2183 continue; 2184 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2185 ibv_list[ret]->name); 2186 ibv_match[nd++] = ibv_list[ret]; 2187 } 2188 } 2189 ibv_match[nd] = NULL; 2190 if (!nd) { 2191 /* No device matches, just complain and bail out. */ 2192 DRV_LOG(WARNING, 2193 "No Verbs device matches PCI device " PCI_PRI_FMT "," 2194 " are kernel drivers loaded?", 2195 owner_pci.domain, owner_pci.bus, 2196 owner_pci.devid, owner_pci.function); 2197 rte_errno = ENOENT; 2198 ret = -rte_errno; 2199 goto exit; 2200 } 2201 if (nd == 1) { 2202 /* 2203 * Found single matching device may have multiple ports. 2204 * Each port may be representor, we have to check the port 2205 * number and check the representors existence. 2206 */ 2207 if (nl_rdma >= 0) 2208 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2209 if (!np) 2210 DRV_LOG(WARNING, 2211 "Cannot get IB device \"%s\" ports number.", 2212 ibv_match[0]->name); 2213 if (bd >= 0 && !np) { 2214 DRV_LOG(ERR, "Cannot get ports for bonding device."); 2215 rte_errno = ENOENT; 2216 ret = -rte_errno; 2217 goto exit; 2218 } 2219 } 2220 /* Now we can determine the maximal amount of devices to be spawned. */ 2221 list = mlx5_malloc(MLX5_MEM_ZERO, 2222 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd), 2223 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2224 if (!list) { 2225 DRV_LOG(ERR, "Spawn data array allocation failure."); 2226 rte_errno = ENOMEM; 2227 ret = -rte_errno; 2228 goto exit; 2229 } 2230 if (bd >= 0 || np > 1) { 2231 /* 2232 * Single IB device with multiple ports found, 2233 * it may be E-Switch master device and representors. 2234 * We have to perform identification through the ports. 2235 */ 2236 MLX5_ASSERT(nl_rdma >= 0); 2237 MLX5_ASSERT(ns == 0); 2238 MLX5_ASSERT(nd == 1); 2239 MLX5_ASSERT(np); 2240 for (i = 1; i <= np; ++i) { 2241 list[ns].bond_info = &bond_info; 2242 list[ns].max_port = np; 2243 list[ns].phys_port = i; 2244 list[ns].phys_dev_name = ibv_match[0]->name; 2245 list[ns].eth_dev = NULL; 2246 list[ns].pci_dev = pci_dev; 2247 list[ns].cdev = cdev; 2248 list[ns].pf_bond = bd; 2249 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, 2250 ibv_match[0]->name, 2251 i); 2252 if (!list[ns].ifindex) { 2253 /* 2254 * No network interface index found for the 2255 * specified port, it means there is no 2256 * representor on this port. It's OK, 2257 * there can be disabled ports, for example 2258 * if sriov_numvfs < sriov_totalvfs. 2259 */ 2260 continue; 2261 } 2262 ret = -1; 2263 if (nl_route >= 0) 2264 ret = mlx5_nl_switch_info(nl_route, 2265 list[ns].ifindex, 2266 &list[ns].info); 2267 if (ret || (!list[ns].info.representor && 2268 !list[ns].info.master)) { 2269 /* 2270 * We failed to recognize representors with 2271 * Netlink, let's try to perform the task 2272 * with sysfs. 2273 */ 2274 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2275 &list[ns].info); 2276 } 2277 if (!ret && bd >= 0) { 2278 switch (list[ns].info.name_type) { 2279 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2280 if (np == 1) { 2281 /* 2282 * Force standalone bonding 2283 * device for ROCE LAG 2284 * configurations. 2285 */ 2286 list[ns].info.master = 0; 2287 list[ns].info.representor = 0; 2288 } 2289 if (list[ns].info.port_name == bd) 2290 ns++; 2291 break; 2292 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2293 /* Fallthrough */ 2294 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2295 /* Fallthrough */ 2296 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2297 if (list[ns].info.pf_num == bd) 2298 ns++; 2299 break; 2300 default: 2301 break; 2302 } 2303 continue; 2304 } 2305 if (!ret && (list[ns].info.representor ^ 2306 list[ns].info.master)) 2307 ns++; 2308 } 2309 if (!ns) { 2310 DRV_LOG(ERR, 2311 "Unable to recognize master/representors on the IB device with multiple ports."); 2312 rte_errno = ENOENT; 2313 ret = -rte_errno; 2314 goto exit; 2315 } 2316 } else { 2317 /* 2318 * The existence of several matching entries (nd > 1) means 2319 * port representors have been instantiated. No existing Verbs 2320 * call nor sysfs entries can tell them apart, this can only 2321 * be done through Netlink calls assuming kernel drivers are 2322 * recent enough to support them. 2323 * 2324 * In the event of identification failure through Netlink, 2325 * try again through sysfs, then: 2326 * 2327 * 1. A single IB device matches (nd == 1) with single 2328 * port (np=0/1) and is not a representor, assume 2329 * no switch support. 2330 * 2331 * 2. Otherwise no safe assumptions can be made; 2332 * complain louder and bail out. 2333 */ 2334 for (i = 0; i != nd; ++i) { 2335 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2336 list[ns].bond_info = NULL; 2337 list[ns].max_port = 1; 2338 list[ns].phys_port = 1; 2339 list[ns].phys_dev_name = ibv_match[i]->name; 2340 list[ns].eth_dev = NULL; 2341 list[ns].pci_dev = pci_dev; 2342 list[ns].cdev = cdev; 2343 list[ns].pf_bond = -1; 2344 list[ns].ifindex = 0; 2345 if (nl_rdma >= 0) 2346 list[ns].ifindex = mlx5_nl_ifindex 2347 (nl_rdma, 2348 ibv_match[i]->name, 2349 1); 2350 if (!list[ns].ifindex) { 2351 char ifname[IF_NAMESIZE]; 2352 2353 /* 2354 * Netlink failed, it may happen with old 2355 * ib_core kernel driver (before 4.16). 2356 * We can assume there is old driver because 2357 * here we are processing single ports IB 2358 * devices. Let's try sysfs to retrieve 2359 * the ifindex. The method works for 2360 * master device only. 2361 */ 2362 if (nd > 1) { 2363 /* 2364 * Multiple devices found, assume 2365 * representors, can not distinguish 2366 * master/representor and retrieve 2367 * ifindex via sysfs. 2368 */ 2369 continue; 2370 } 2371 ret = mlx5_get_ifname_sysfs 2372 (ibv_match[i]->ibdev_path, ifname); 2373 if (!ret) 2374 list[ns].ifindex = 2375 if_nametoindex(ifname); 2376 if (!list[ns].ifindex) { 2377 /* 2378 * No network interface index found 2379 * for the specified device, it means 2380 * there it is neither representor 2381 * nor master. 2382 */ 2383 continue; 2384 } 2385 } 2386 ret = -1; 2387 if (nl_route >= 0) 2388 ret = mlx5_nl_switch_info(nl_route, 2389 list[ns].ifindex, 2390 &list[ns].info); 2391 if (ret || (!list[ns].info.representor && 2392 !list[ns].info.master)) { 2393 /* 2394 * We failed to recognize representors with 2395 * Netlink, let's try to perform the task 2396 * with sysfs. 2397 */ 2398 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2399 &list[ns].info); 2400 } 2401 if (!ret && (list[ns].info.representor ^ 2402 list[ns].info.master)) { 2403 ns++; 2404 } else if ((nd == 1) && 2405 !list[ns].info.representor && 2406 !list[ns].info.master) { 2407 /* 2408 * Single IB device with one physical port and 2409 * attached network device. 2410 * May be SRIOV is not enabled or there is no 2411 * representors. 2412 */ 2413 DRV_LOG(INFO, "No E-Switch support detected."); 2414 ns++; 2415 break; 2416 } 2417 } 2418 if (!ns) { 2419 DRV_LOG(ERR, 2420 "Unable to recognize master/representors on the multiple IB devices."); 2421 rte_errno = ENOENT; 2422 ret = -rte_errno; 2423 goto exit; 2424 } 2425 /* 2426 * New kernels may add the switch_id attribute for the case 2427 * there is no E-Switch and we wrongly recognized the only 2428 * device as master. Override this if there is the single 2429 * device with single port and new device name format present. 2430 */ 2431 if (nd == 1 && 2432 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2433 list[0].info.master = 0; 2434 list[0].info.representor = 0; 2435 } 2436 } 2437 MLX5_ASSERT(ns); 2438 /* 2439 * Sort list to probe devices in natural order for users convenience 2440 * (i.e. master first, then representors from lowest to highest ID). 2441 */ 2442 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2443 /* Device specific configuration. */ 2444 switch (pci_dev->id.device_id) { 2445 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2446 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2447 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2448 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2449 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2450 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2451 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2452 dev_config_vf = 1; 2453 break; 2454 default: 2455 dev_config_vf = 0; 2456 break; 2457 } 2458 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2459 /* Set devargs default values. */ 2460 if (eth_da.nb_mh_controllers == 0) { 2461 eth_da.nb_mh_controllers = 1; 2462 eth_da.mh_controllers[0] = 0; 2463 } 2464 if (eth_da.nb_ports == 0 && ns > 0) { 2465 if (list[0].pf_bond >= 0 && list[0].info.representor) 2466 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2467 pci_dev->device.devargs->args); 2468 eth_da.nb_ports = 1; 2469 eth_da.ports[0] = list[0].info.pf_num; 2470 } 2471 if (eth_da.nb_representor_ports == 0) { 2472 eth_da.nb_representor_ports = 1; 2473 eth_da.representor_ports[0] = 0; 2474 } 2475 } 2476 for (i = 0; i != ns; ++i) { 2477 uint32_t restore; 2478 2479 /* Default configuration. */ 2480 mlx5_os_config_default(&dev_config, &cdev->config); 2481 dev_config.vf = dev_config_vf; 2482 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], 2483 &dev_config, ð_da); 2484 if (!list[i].eth_dev) { 2485 if (rte_errno != EBUSY && rte_errno != EEXIST) 2486 break; 2487 /* Device is disabled or already spawned. Ignore it. */ 2488 continue; 2489 } 2490 restore = list[i].eth_dev->data->dev_flags; 2491 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2492 /** 2493 * Each representor has a dedicated interrupts vector. 2494 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2495 * representor eth_dev object because representor and PF 2496 * share the same PCI address. 2497 * Override representor device with a dedicated 2498 * interrupts handle here. 2499 * Representor interrupts handle is released in mlx5_dev_stop(). 2500 */ 2501 if (list[i].info.representor) { 2502 struct rte_intr_handle *intr_handle = 2503 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2504 if (intr_handle == NULL) { 2505 DRV_LOG(ERR, 2506 "port %u failed to allocate memory for interrupt handler " 2507 "Rx interrupts will not be supported", 2508 i); 2509 rte_errno = ENOMEM; 2510 ret = -rte_errno; 2511 goto exit; 2512 } 2513 list[i].eth_dev->intr_handle = intr_handle; 2514 } 2515 /* Restore non-PCI flags cleared by the above call. */ 2516 list[i].eth_dev->data->dev_flags |= restore; 2517 rte_eth_dev_probing_finish(list[i].eth_dev); 2518 } 2519 if (i != ns) { 2520 DRV_LOG(ERR, 2521 "probe of PCI device " PCI_PRI_FMT " aborted after" 2522 " encountering an error: %s", 2523 owner_pci.domain, owner_pci.bus, 2524 owner_pci.devid, owner_pci.function, 2525 strerror(rte_errno)); 2526 ret = -rte_errno; 2527 /* Roll back. */ 2528 while (i--) { 2529 if (!list[i].eth_dev) 2530 continue; 2531 mlx5_dev_close(list[i].eth_dev); 2532 /* mac_addrs must not be freed because in dev_private */ 2533 list[i].eth_dev->data->mac_addrs = NULL; 2534 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2535 } 2536 /* Restore original error. */ 2537 rte_errno = -ret; 2538 } else { 2539 ret = 0; 2540 } 2541 exit: 2542 /* 2543 * Do the routine cleanup: 2544 * - close opened Netlink sockets 2545 * - free allocated spawn data array 2546 * - free the Infiniband device list 2547 */ 2548 if (nl_rdma >= 0) 2549 close(nl_rdma); 2550 if (nl_route >= 0) 2551 close(nl_route); 2552 if (list) 2553 mlx5_free(list); 2554 MLX5_ASSERT(ibv_list); 2555 mlx5_glue->free_device_list(ibv_list); 2556 return ret; 2557 } 2558 2559 static int 2560 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2561 struct rte_eth_devargs *eth_da) 2562 { 2563 int ret = 0; 2564 2565 if (dev->devargs == NULL) 2566 return 0; 2567 memset(eth_da, 0, sizeof(*eth_da)); 2568 /* Parse representor information first from class argument. */ 2569 if (dev->devargs->cls_str) 2570 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2571 if (ret != 0) { 2572 DRV_LOG(ERR, "failed to parse device arguments: %s", 2573 dev->devargs->cls_str); 2574 return -rte_errno; 2575 } 2576 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2577 /* Parse legacy device argument */ 2578 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2579 if (ret) { 2580 DRV_LOG(ERR, "failed to parse device arguments: %s", 2581 dev->devargs->args); 2582 return -rte_errno; 2583 } 2584 } 2585 return 0; 2586 } 2587 2588 /** 2589 * Callback to register a PCI device. 2590 * 2591 * This function spawns Ethernet devices out of a given PCI device. 2592 * 2593 * @param[in] cdev 2594 * Pointer to common mlx5 device structure. 2595 * 2596 * @return 2597 * 0 on success, a negative errno value otherwise and rte_errno is set. 2598 */ 2599 static int 2600 mlx5_os_pci_probe(struct mlx5_common_device *cdev) 2601 { 2602 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2603 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2604 int ret = 0; 2605 uint16_t p; 2606 2607 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da); 2608 if (ret != 0) 2609 return ret; 2610 2611 if (eth_da.nb_ports > 0) { 2612 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2613 for (p = 0; p < eth_da.nb_ports; p++) { 2614 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 2615 eth_da.ports[p]); 2616 if (ret) 2617 break; 2618 } 2619 if (ret) { 2620 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2621 "aborted due to prodding failure of PF %u", 2622 pci_dev->addr.domain, pci_dev->addr.bus, 2623 pci_dev->addr.devid, pci_dev->addr.function, 2624 eth_da.ports[p]); 2625 mlx5_net_remove(cdev); 2626 } 2627 } else { 2628 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0); 2629 } 2630 return ret; 2631 } 2632 2633 /* Probe a single SF device on auxiliary bus, no representor support. */ 2634 static int 2635 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev) 2636 { 2637 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2638 struct mlx5_dev_config config; 2639 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2640 struct rte_device *dev = cdev->dev; 2641 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2642 struct rte_eth_dev *eth_dev; 2643 int ret = 0; 2644 2645 /* Parse ethdev devargs. */ 2646 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2647 if (ret != 0) 2648 return ret; 2649 /* Set default config data. */ 2650 mlx5_os_config_default(&config, &cdev->config); 2651 config.sf = 1; 2652 /* Init spawn data. */ 2653 spawn.max_port = 1; 2654 spawn.phys_port = 1; 2655 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 2656 ret = mlx5_auxiliary_get_ifindex(dev->name); 2657 if (ret < 0) { 2658 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2659 return ret; 2660 } 2661 spawn.ifindex = ret; 2662 spawn.cdev = cdev; 2663 /* Spawn device. */ 2664 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2665 if (eth_dev == NULL) 2666 return -rte_errno; 2667 /* Post create. */ 2668 eth_dev->intr_handle = adev->intr_handle; 2669 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2670 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2671 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2672 eth_dev->data->numa_node = dev->numa_node; 2673 } 2674 rte_eth_dev_probing_finish(eth_dev); 2675 return 0; 2676 } 2677 2678 /** 2679 * Net class driver callback to probe a device. 2680 * 2681 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2682 * 2683 * @param[in] cdev 2684 * Pointer to the common mlx5 device. 2685 * 2686 * @return 2687 * 0 on success, a negative errno value otherwise and rte_errno is set. 2688 */ 2689 int 2690 mlx5_os_net_probe(struct mlx5_common_device *cdev) 2691 { 2692 int ret; 2693 2694 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2695 mlx5_pmd_socket_init(); 2696 ret = mlx5_init_once(); 2697 if (ret) { 2698 DRV_LOG(ERR, "Unable to init PMD global data: %s", 2699 strerror(rte_errno)); 2700 return -rte_errno; 2701 } 2702 if (mlx5_dev_is_pci(cdev->dev)) 2703 return mlx5_os_pci_probe(cdev); 2704 else 2705 return mlx5_os_auxiliary_probe(cdev); 2706 } 2707 2708 /** 2709 * Cleanup resources when the last device is closed. 2710 */ 2711 void 2712 mlx5_os_net_cleanup(void) 2713 { 2714 mlx5_pmd_socket_uninit(); 2715 } 2716 2717 /** 2718 * Install shared asynchronous device events handler. 2719 * This function is implemented to support event sharing 2720 * between multiple ports of single IB device. 2721 * 2722 * @param sh 2723 * Pointer to mlx5_dev_ctx_shared object. 2724 */ 2725 void 2726 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2727 { 2728 int ret; 2729 int flags; 2730 struct ibv_context *ctx = sh->cdev->ctx; 2731 2732 sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2733 if (sh->intr_handle == NULL) { 2734 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2735 rte_errno = ENOMEM; 2736 return; 2737 } 2738 rte_intr_fd_set(sh->intr_handle, -1); 2739 2740 flags = fcntl(ctx->async_fd, F_GETFL); 2741 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); 2742 if (ret) { 2743 DRV_LOG(INFO, "failed to change file descriptor async event" 2744 " queue"); 2745 } else { 2746 rte_intr_fd_set(sh->intr_handle, ctx->async_fd); 2747 rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); 2748 if (rte_intr_callback_register(sh->intr_handle, 2749 mlx5_dev_interrupt_handler, sh)) { 2750 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2751 rte_intr_fd_set(sh->intr_handle, -1); 2752 } 2753 } 2754 if (sh->devx) { 2755 #ifdef HAVE_IBV_DEVX_ASYNC 2756 sh->intr_handle_devx = 2757 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2758 if (!sh->intr_handle_devx) { 2759 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2760 rte_errno = ENOMEM; 2761 return; 2762 } 2763 rte_intr_fd_set(sh->intr_handle_devx, -1); 2764 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); 2765 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2766 if (!devx_comp) { 2767 DRV_LOG(INFO, "failed to allocate devx_comp."); 2768 return; 2769 } 2770 flags = fcntl(devx_comp->fd, F_GETFL); 2771 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2772 if (ret) { 2773 DRV_LOG(INFO, "failed to change file descriptor" 2774 " devx comp"); 2775 return; 2776 } 2777 rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); 2778 rte_intr_type_set(sh->intr_handle_devx, 2779 RTE_INTR_HANDLE_EXT); 2780 if (rte_intr_callback_register(sh->intr_handle_devx, 2781 mlx5_dev_interrupt_handler_devx, sh)) { 2782 DRV_LOG(INFO, "Fail to install the devx shared" 2783 " interrupt."); 2784 rte_intr_fd_set(sh->intr_handle_devx, -1); 2785 } 2786 #endif /* HAVE_IBV_DEVX_ASYNC */ 2787 } 2788 } 2789 2790 /** 2791 * Uninstall shared asynchronous device events handler. 2792 * This function is implemented to support event sharing 2793 * between multiple ports of single IB device. 2794 * 2795 * @param dev 2796 * Pointer to mlx5_dev_ctx_shared object. 2797 */ 2798 void 2799 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2800 { 2801 if (rte_intr_fd_get(sh->intr_handle) >= 0) 2802 mlx5_intr_callback_unregister(sh->intr_handle, 2803 mlx5_dev_interrupt_handler, sh); 2804 rte_intr_instance_free(sh->intr_handle); 2805 #ifdef HAVE_IBV_DEVX_ASYNC 2806 if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) 2807 rte_intr_callback_unregister(sh->intr_handle_devx, 2808 mlx5_dev_interrupt_handler_devx, sh); 2809 rte_intr_instance_free(sh->intr_handle_devx); 2810 if (sh->devx_comp) 2811 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2812 #endif 2813 } 2814 2815 /** 2816 * Read statistics by a named counter. 2817 * 2818 * @param[in] priv 2819 * Pointer to the private device data structure. 2820 * @param[in] ctr_name 2821 * Pointer to the name of the statistic counter to read 2822 * @param[out] stat 2823 * Pointer to read statistic value. 2824 * @return 2825 * 0 on success and stat is valud, 1 if failed to read the value 2826 * rte_errno is set. 2827 * 2828 */ 2829 int 2830 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2831 uint64_t *stat) 2832 { 2833 int fd; 2834 2835 if (priv->sh) { 2836 if (priv->q_counters != NULL && 2837 strcmp(ctr_name, "out_of_buffer") == 0) 2838 return mlx5_devx_cmd_queue_counter_query 2839 (priv->q_counters, 0, (uint32_t *)stat); 2840 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2841 priv->sh->ibdev_path, 2842 priv->dev_port, 2843 ctr_name); 2844 fd = open(path, O_RDONLY); 2845 /* 2846 * in switchdev the file location is not per port 2847 * but rather in <ibdev_path>/hw_counters/<file_name>. 2848 */ 2849 if (fd == -1) { 2850 MKSTR(path1, "%s/hw_counters/%s", 2851 priv->sh->ibdev_path, 2852 ctr_name); 2853 fd = open(path1, O_RDONLY); 2854 } 2855 if (fd != -1) { 2856 char buf[21] = {'\0'}; 2857 ssize_t n = read(fd, buf, sizeof(buf)); 2858 2859 close(fd); 2860 if (n != -1) { 2861 *stat = strtoull(buf, NULL, 10); 2862 return 0; 2863 } 2864 } 2865 } 2866 *stat = 0; 2867 return 1; 2868 } 2869 2870 /** 2871 * Remove a MAC address from device 2872 * 2873 * @param dev 2874 * Pointer to Ethernet device structure. 2875 * @param index 2876 * MAC address index. 2877 */ 2878 void 2879 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2880 { 2881 struct mlx5_priv *priv = dev->data->dev_private; 2882 const int vf = priv->config.vf; 2883 2884 if (vf) 2885 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2886 mlx5_ifindex(dev), priv->mac_own, 2887 &dev->data->mac_addrs[index], index); 2888 } 2889 2890 /** 2891 * Adds a MAC address to the device 2892 * 2893 * @param dev 2894 * Pointer to Ethernet device structure. 2895 * @param mac_addr 2896 * MAC address to register. 2897 * @param index 2898 * MAC address index. 2899 * 2900 * @return 2901 * 0 on success, a negative errno value otherwise 2902 */ 2903 int 2904 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2905 uint32_t index) 2906 { 2907 struct mlx5_priv *priv = dev->data->dev_private; 2908 const int vf = priv->config.vf; 2909 int ret = 0; 2910 2911 if (vf) 2912 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2913 mlx5_ifindex(dev), priv->mac_own, 2914 mac, index); 2915 return ret; 2916 } 2917 2918 /** 2919 * Modify a VF MAC address 2920 * 2921 * @param priv 2922 * Pointer to device private data. 2923 * @param mac_addr 2924 * MAC address to modify into. 2925 * @param iface_idx 2926 * Net device interface index 2927 * @param vf_index 2928 * VF index 2929 * 2930 * @return 2931 * 0 on success, a negative errno value otherwise 2932 */ 2933 int 2934 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2935 unsigned int iface_idx, 2936 struct rte_ether_addr *mac_addr, 2937 int vf_index) 2938 { 2939 return mlx5_nl_vf_mac_addr_modify 2940 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2941 } 2942 2943 /** 2944 * Set device promiscuous mode 2945 * 2946 * @param dev 2947 * Pointer to Ethernet device structure. 2948 * @param enable 2949 * 0 - promiscuous is disabled, otherwise - enabled 2950 * 2951 * @return 2952 * 0 on success, a negative error value otherwise 2953 */ 2954 int 2955 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2956 { 2957 struct mlx5_priv *priv = dev->data->dev_private; 2958 2959 return mlx5_nl_promisc(priv->nl_socket_route, 2960 mlx5_ifindex(dev), !!enable); 2961 } 2962 2963 /** 2964 * Set device promiscuous mode 2965 * 2966 * @param dev 2967 * Pointer to Ethernet device structure. 2968 * @param enable 2969 * 0 - all multicase is disabled, otherwise - enabled 2970 * 2971 * @return 2972 * 0 on success, a negative error value otherwise 2973 */ 2974 int 2975 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2976 { 2977 struct mlx5_priv *priv = dev->data->dev_private; 2978 2979 return mlx5_nl_allmulti(priv->nl_socket_route, 2980 mlx5_ifindex(dev), !!enable); 2981 } 2982 2983 /** 2984 * Flush device MAC addresses 2985 * 2986 * @param dev 2987 * Pointer to Ethernet device structure. 2988 * 2989 */ 2990 void 2991 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2992 { 2993 struct mlx5_priv *priv = dev->data->dev_private; 2994 2995 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2996 dev->data->mac_addrs, 2997 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2998 } 2999