1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 120 device_attr->max_mr = attr_ex.orig_attr.max_mr; 121 device_attr->max_pd = attr_ex.orig_attr.max_pd; 122 device_attr->max_qp = attr_ex.orig_attr.max_qp; 123 device_attr->max_srq = attr_ex.orig_attr.max_srq; 124 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 125 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 126 device_attr->max_rwq_indirection_table_size = 127 attr_ex.rss_caps.max_rwq_indirection_table_size; 128 device_attr->max_tso = attr_ex.tso_caps.max_tso; 129 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 130 131 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 132 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 133 if (err) 134 return err; 135 136 device_attr->flags = dv_attr.flags; 137 device_attr->comp_mask = dv_attr.comp_mask; 138 #ifdef HAVE_IBV_MLX5_MOD_SWP 139 device_attr->sw_parsing_offloads = 140 dv_attr.sw_parsing_caps.sw_parsing_offloads; 141 #endif 142 device_attr->min_single_stride_log_num_of_bytes = 143 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 144 device_attr->max_single_stride_log_num_of_bytes = 145 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 146 device_attr->min_single_wqe_log_num_of_strides = 147 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 148 device_attr->max_single_wqe_log_num_of_strides = 149 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 150 device_attr->stride_supported_qpts = 151 dv_attr.striding_rq_caps.supported_qpts; 152 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 153 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 154 #endif 155 156 return err; 157 } 158 159 /** 160 * Verbs callback to allocate a memory. This function should allocate the space 161 * according to the size provided residing inside a huge page. 162 * Please note that all allocation must respect the alignment from libmlx5 163 * (i.e. currently rte_mem_page_size()). 164 * 165 * @param[in] size 166 * The size in bytes of the memory to allocate. 167 * @param[in] data 168 * A pointer to the callback data. 169 * 170 * @return 171 * Allocated buffer, NULL otherwise and rte_errno is set. 172 */ 173 static void * 174 mlx5_alloc_verbs_buf(size_t size, void *data) 175 { 176 struct mlx5_dev_ctx_shared *sh = data; 177 void *ret; 178 size_t alignment = rte_mem_page_size(); 179 if (alignment == (size_t)-1) { 180 DRV_LOG(ERR, "Failed to get mem page size"); 181 rte_errno = ENOMEM; 182 return NULL; 183 } 184 185 MLX5_ASSERT(data != NULL); 186 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 187 if (!ret && size) 188 rte_errno = ENOMEM; 189 return ret; 190 } 191 192 /** 193 * Verbs callback to free a memory. 194 * 195 * @param[in] ptr 196 * A pointer to the memory to free. 197 * @param[in] data 198 * A pointer to the callback data. 199 */ 200 static void 201 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 202 { 203 MLX5_ASSERT(data != NULL); 204 mlx5_free(ptr); 205 } 206 207 /** 208 * Initialize DR related data within private structure. 209 * Routine checks the reference counter and does actual 210 * resources creation/initialization only if counter is zero. 211 * 212 * @param[in] priv 213 * Pointer to the private device data structure. 214 * 215 * @return 216 * Zero on success, positive error code otherwise. 217 */ 218 static int 219 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 220 { 221 struct mlx5_dev_ctx_shared *sh = priv->sh; 222 char s[MLX5_HLIST_NAMESIZE] __rte_unused; 223 int err; 224 225 MLX5_ASSERT(sh && sh->refcnt); 226 if (sh->refcnt > 1) 227 return 0; 228 err = mlx5_alloc_table_hash_list(priv); 229 if (err) 230 goto error; 231 /* The resources below are only valid with DV support. */ 232 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 233 /* Init port id action cache list. */ 234 snprintf(s, sizeof(s), "%s_port_id_action_cache", sh->ibdev_name); 235 mlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh, 236 flow_dv_port_id_create_cb, 237 flow_dv_port_id_match_cb, 238 flow_dv_port_id_remove_cb); 239 /* Init push vlan action cache list. */ 240 snprintf(s, sizeof(s), "%s_push_vlan_action_cache", sh->ibdev_name); 241 mlx5_cache_list_init(&sh->push_vlan_action_list, s, 0, sh, 242 flow_dv_push_vlan_create_cb, 243 flow_dv_push_vlan_match_cb, 244 flow_dv_push_vlan_remove_cb); 245 /* Init sample action cache list. */ 246 snprintf(s, sizeof(s), "%s_sample_action_cache", sh->ibdev_name); 247 mlx5_cache_list_init(&sh->sample_action_list, s, 0, sh, 248 flow_dv_sample_create_cb, 249 flow_dv_sample_match_cb, 250 flow_dv_sample_remove_cb); 251 /* Init dest array action cache list. */ 252 snprintf(s, sizeof(s), "%s_dest_array_cache", sh->ibdev_name); 253 mlx5_cache_list_init(&sh->dest_array_list, s, 0, sh, 254 flow_dv_dest_array_create_cb, 255 flow_dv_dest_array_match_cb, 256 flow_dv_dest_array_remove_cb); 257 /* Create tags hash list table. */ 258 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 259 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0, 260 MLX5_HLIST_WRITE_MOST, 261 flow_dv_tag_create_cb, 262 flow_dv_tag_match_cb, 263 flow_dv_tag_remove_cb); 264 if (!sh->tag_table) { 265 DRV_LOG(ERR, "tags with hash creation failed."); 266 err = ENOMEM; 267 goto error; 268 } 269 sh->tag_table->ctx = sh; 270 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 271 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ, 272 0, MLX5_HLIST_WRITE_MOST | 273 MLX5_HLIST_DIRECT_KEY, 274 flow_dv_modify_create_cb, 275 flow_dv_modify_match_cb, 276 flow_dv_modify_remove_cb); 277 if (!sh->modify_cmds) { 278 DRV_LOG(ERR, "hdr modify hash creation failed"); 279 err = ENOMEM; 280 goto error; 281 } 282 sh->modify_cmds->ctx = sh; 283 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 284 sh->encaps_decaps = mlx5_hlist_create(s, 285 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ, 286 0, MLX5_HLIST_DIRECT_KEY | 287 MLX5_HLIST_WRITE_MOST, 288 flow_dv_encap_decap_create_cb, 289 flow_dv_encap_decap_match_cb, 290 flow_dv_encap_decap_remove_cb); 291 if (!sh->encaps_decaps) { 292 DRV_LOG(ERR, "encap decap hash creation failed"); 293 err = ENOMEM; 294 goto error; 295 } 296 sh->encaps_decaps->ctx = sh; 297 #endif 298 #ifdef HAVE_MLX5DV_DR 299 void *domain; 300 301 /* Reference counter is zero, we should initialize structures. */ 302 domain = mlx5_glue->dr_create_domain(sh->ctx, 303 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 304 if (!domain) { 305 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 306 err = errno; 307 goto error; 308 } 309 sh->rx_domain = domain; 310 domain = mlx5_glue->dr_create_domain(sh->ctx, 311 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 312 if (!domain) { 313 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 314 err = errno; 315 goto error; 316 } 317 sh->tx_domain = domain; 318 #ifdef HAVE_MLX5DV_DR_ESWITCH 319 if (priv->config.dv_esw_en) { 320 domain = mlx5_glue->dr_create_domain 321 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 322 if (!domain) { 323 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 324 err = errno; 325 goto error; 326 } 327 sh->fdb_domain = domain; 328 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 329 } 330 #endif 331 if (!sh->tunnel_hub) 332 err = mlx5_alloc_tunnel_hub(sh); 333 if (err) { 334 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 335 goto error; 336 } 337 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 338 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 339 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 340 if (sh->fdb_domain) 341 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 342 } 343 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 344 #endif /* HAVE_MLX5DV_DR */ 345 sh->default_miss_action = 346 mlx5_glue->dr_create_flow_action_default_miss(); 347 if (!sh->default_miss_action) 348 DRV_LOG(WARNING, "Default miss action is not supported."); 349 return 0; 350 error: 351 /* Rollback the created objects. */ 352 if (sh->rx_domain) { 353 mlx5_glue->dr_destroy_domain(sh->rx_domain); 354 sh->rx_domain = NULL; 355 } 356 if (sh->tx_domain) { 357 mlx5_glue->dr_destroy_domain(sh->tx_domain); 358 sh->tx_domain = NULL; 359 } 360 if (sh->fdb_domain) { 361 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 362 sh->fdb_domain = NULL; 363 } 364 if (sh->esw_drop_action) { 365 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 366 sh->esw_drop_action = NULL; 367 } 368 if (sh->pop_vlan_action) { 369 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 370 sh->pop_vlan_action = NULL; 371 } 372 if (sh->encaps_decaps) { 373 mlx5_hlist_destroy(sh->encaps_decaps); 374 sh->encaps_decaps = NULL; 375 } 376 if (sh->modify_cmds) { 377 mlx5_hlist_destroy(sh->modify_cmds); 378 sh->modify_cmds = NULL; 379 } 380 if (sh->tag_table) { 381 /* tags should be destroyed with flow before. */ 382 mlx5_hlist_destroy(sh->tag_table); 383 sh->tag_table = NULL; 384 } 385 if (sh->tunnel_hub) { 386 mlx5_release_tunnel_hub(sh, priv->dev_port); 387 sh->tunnel_hub = NULL; 388 } 389 mlx5_free_table_hash_list(priv); 390 return err; 391 } 392 393 /** 394 * Destroy DR related data within private structure. 395 * 396 * @param[in] priv 397 * Pointer to the private device data structure. 398 */ 399 void 400 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 401 { 402 struct mlx5_dev_ctx_shared *sh = priv->sh; 403 404 MLX5_ASSERT(sh && sh->refcnt); 405 if (sh->refcnt > 1) 406 return; 407 #ifdef HAVE_MLX5DV_DR 408 if (sh->rx_domain) { 409 mlx5_glue->dr_destroy_domain(sh->rx_domain); 410 sh->rx_domain = NULL; 411 } 412 if (sh->tx_domain) { 413 mlx5_glue->dr_destroy_domain(sh->tx_domain); 414 sh->tx_domain = NULL; 415 } 416 #ifdef HAVE_MLX5DV_DR_ESWITCH 417 if (sh->fdb_domain) { 418 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 419 sh->fdb_domain = NULL; 420 } 421 if (sh->esw_drop_action) { 422 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 423 sh->esw_drop_action = NULL; 424 } 425 #endif 426 if (sh->pop_vlan_action) { 427 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 428 sh->pop_vlan_action = NULL; 429 } 430 #endif /* HAVE_MLX5DV_DR */ 431 if (sh->default_miss_action) 432 mlx5_glue->destroy_flow_action 433 (sh->default_miss_action); 434 if (sh->encaps_decaps) { 435 mlx5_hlist_destroy(sh->encaps_decaps); 436 sh->encaps_decaps = NULL; 437 } 438 if (sh->modify_cmds) { 439 mlx5_hlist_destroy(sh->modify_cmds); 440 sh->modify_cmds = NULL; 441 } 442 if (sh->tag_table) { 443 /* tags should be destroyed with flow before. */ 444 mlx5_hlist_destroy(sh->tag_table); 445 sh->tag_table = NULL; 446 } 447 if (sh->tunnel_hub) { 448 mlx5_release_tunnel_hub(sh, priv->dev_port); 449 sh->tunnel_hub = NULL; 450 } 451 mlx5_cache_list_destroy(&sh->port_id_action_list); 452 mlx5_cache_list_destroy(&sh->push_vlan_action_list); 453 mlx5_free_table_hash_list(priv); 454 } 455 456 /** 457 * Initialize shared data between primary and secondary process. 458 * 459 * A memzone is reserved by primary process and secondary processes attach to 460 * the memzone. 461 * 462 * @return 463 * 0 on success, a negative errno value otherwise and rte_errno is set. 464 */ 465 static int 466 mlx5_init_shared_data(void) 467 { 468 const struct rte_memzone *mz; 469 int ret = 0; 470 471 rte_spinlock_lock(&mlx5_shared_data_lock); 472 if (mlx5_shared_data == NULL) { 473 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 474 /* Allocate shared memory. */ 475 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 476 sizeof(*mlx5_shared_data), 477 SOCKET_ID_ANY, 0); 478 if (mz == NULL) { 479 DRV_LOG(ERR, 480 "Cannot allocate mlx5 shared data"); 481 ret = -rte_errno; 482 goto error; 483 } 484 mlx5_shared_data = mz->addr; 485 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 486 rte_spinlock_init(&mlx5_shared_data->lock); 487 } else { 488 /* Lookup allocated shared memory. */ 489 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 490 if (mz == NULL) { 491 DRV_LOG(ERR, 492 "Cannot attach mlx5 shared data"); 493 ret = -rte_errno; 494 goto error; 495 } 496 mlx5_shared_data = mz->addr; 497 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 498 } 499 } 500 error: 501 rte_spinlock_unlock(&mlx5_shared_data_lock); 502 return ret; 503 } 504 505 /** 506 * PMD global initialization. 507 * 508 * Independent from individual device, this function initializes global 509 * per-PMD data structures distinguishing primary and secondary processes. 510 * Hence, each initialization is called once per a process. 511 * 512 * @return 513 * 0 on success, a negative errno value otherwise and rte_errno is set. 514 */ 515 static int 516 mlx5_init_once(void) 517 { 518 struct mlx5_shared_data *sd; 519 struct mlx5_local_data *ld = &mlx5_local_data; 520 int ret = 0; 521 522 if (mlx5_init_shared_data()) 523 return -rte_errno; 524 sd = mlx5_shared_data; 525 MLX5_ASSERT(sd); 526 rte_spinlock_lock(&sd->lock); 527 switch (rte_eal_process_type()) { 528 case RTE_PROC_PRIMARY: 529 if (sd->init_done) 530 break; 531 LIST_INIT(&sd->mem_event_cb_list); 532 rte_rwlock_init(&sd->mem_event_rwlock); 533 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 534 mlx5_mr_mem_event_cb, NULL); 535 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 536 mlx5_mp_os_primary_handle); 537 if (ret) 538 goto out; 539 sd->init_done = true; 540 break; 541 case RTE_PROC_SECONDARY: 542 if (ld->init_done) 543 break; 544 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 545 mlx5_mp_os_secondary_handle); 546 if (ret) 547 goto out; 548 ++sd->secondary_cnt; 549 ld->init_done = true; 550 break; 551 default: 552 break; 553 } 554 out: 555 rte_spinlock_unlock(&sd->lock); 556 return ret; 557 } 558 559 /** 560 * Create the Tx queue DevX/Verbs object. 561 * 562 * @param dev 563 * Pointer to Ethernet device. 564 * @param idx 565 * Queue index in DPDK Tx queue array. 566 * 567 * @return 568 * 0 on success, a negative errno value otherwise and rte_errno is set. 569 */ 570 static int 571 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 572 { 573 struct mlx5_priv *priv = dev->data->dev_private; 574 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 575 struct mlx5_txq_ctrl *txq_ctrl = 576 container_of(txq_data, struct mlx5_txq_ctrl, txq); 577 578 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 579 return mlx5_txq_devx_obj_new(dev, idx); 580 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 581 if (!priv->config.dv_esw_en) 582 return mlx5_txq_devx_obj_new(dev, idx); 583 #endif 584 return mlx5_txq_ibv_obj_new(dev, idx); 585 } 586 587 /** 588 * Release an Tx DevX/verbs queue object. 589 * 590 * @param txq_obj 591 * DevX/Verbs Tx queue object. 592 */ 593 static void 594 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 595 { 596 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 597 mlx5_txq_devx_obj_release(txq_obj); 598 return; 599 } 600 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 601 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 602 mlx5_txq_devx_obj_release(txq_obj); 603 return; 604 } 605 #endif 606 mlx5_txq_ibv_obj_release(txq_obj); 607 } 608 609 /** 610 * DV flow counter mode detect and config. 611 * 612 * @param dev 613 * Pointer to rte_eth_dev structure. 614 * 615 */ 616 static void 617 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 618 { 619 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 620 struct mlx5_priv *priv = dev->data->dev_private; 621 struct mlx5_dev_ctx_shared *sh = priv->sh; 622 bool fallback; 623 624 #ifndef HAVE_IBV_DEVX_ASYNC 625 fallback = true; 626 #else 627 fallback = false; 628 if (!priv->config.devx || !priv->config.dv_flow_en || 629 !priv->config.hca_attr.flow_counters_dump || 630 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 631 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 632 fallback = true; 633 #endif 634 if (fallback) 635 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 636 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 637 priv->config.hca_attr.flow_counters_dump, 638 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 639 /* Initialize fallback mode only on the port initializes sh. */ 640 if (sh->refcnt == 1) 641 sh->cmng.counter_fallback = fallback; 642 else if (fallback != sh->cmng.counter_fallback) 643 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 644 "with others:%d.", PORT_ID(priv), fallback); 645 #endif 646 } 647 648 static void 649 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 650 { 651 struct mlx5_priv *priv = dev->data->dev_private; 652 void *ctx = priv->sh->ctx; 653 654 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 655 if (!priv->q_counters) { 656 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 657 struct ibv_wq *wq; 658 659 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 660 "by DevX - fall-back to use the kernel driver global " 661 "queue counter.", dev->data->port_id); 662 /* Create WQ by kernel and query its queue counter ID. */ 663 if (cq) { 664 wq = mlx5_glue->create_wq(ctx, 665 &(struct ibv_wq_init_attr){ 666 .wq_type = IBV_WQT_RQ, 667 .max_wr = 1, 668 .max_sge = 1, 669 .pd = priv->sh->pd, 670 .cq = cq, 671 }); 672 if (wq) { 673 /* Counter is assigned only on RDY state. */ 674 int ret = mlx5_glue->modify_wq(wq, 675 &(struct ibv_wq_attr){ 676 .attr_mask = IBV_WQ_ATTR_STATE, 677 .wq_state = IBV_WQS_RDY, 678 }); 679 680 if (ret == 0) 681 mlx5_devx_cmd_wq_query(wq, 682 &priv->counter_set_id); 683 claim_zero(mlx5_glue->destroy_wq(wq)); 684 } 685 claim_zero(mlx5_glue->destroy_cq(cq)); 686 } 687 } else { 688 priv->counter_set_id = priv->q_counters->id; 689 } 690 if (priv->counter_set_id == 0) 691 DRV_LOG(INFO, "Part of the port %d statistics will not be " 692 "available.", dev->data->port_id); 693 } 694 695 /** 696 * Check if representor spawn info match devargs. 697 * 698 * @param spawn 699 * Verbs device parameters (name, port, switch_info) to spawn. 700 * @param eth_da 701 * Device devargs to probe. 702 * 703 * @return 704 * Match result. 705 */ 706 static bool 707 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 708 struct rte_eth_devargs *eth_da) 709 { 710 struct mlx5_switch_info *switch_info = &spawn->info; 711 unsigned int p, f; 712 uint16_t id; 713 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 714 eth_da->type); 715 716 switch (eth_da->type) { 717 case RTE_ETH_REPRESENTOR_SF: 718 if (!(spawn->info.port_name == -1 && 719 switch_info->name_type == 720 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 721 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 722 rte_errno = EBUSY; 723 return false; 724 } 725 break; 726 case RTE_ETH_REPRESENTOR_VF: 727 /* Allows HPF representor index -1 as exception. */ 728 if (!(spawn->info.port_name == -1 && 729 switch_info->name_type == 730 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 731 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 732 rte_errno = EBUSY; 733 return false; 734 } 735 break; 736 case RTE_ETH_REPRESENTOR_NONE: 737 rte_errno = EBUSY; 738 return false; 739 default: 740 rte_errno = ENOTSUP; 741 DRV_LOG(ERR, "unsupported representor type"); 742 return false; 743 } 744 /* Check representor ID: */ 745 for (p = 0; p < eth_da->nb_ports; ++p) { 746 if (spawn->pf_bond < 0) { 747 /* For non-LAG mode, allow and ignore pf. */ 748 switch_info->pf_num = eth_da->ports[p]; 749 repr_id = mlx5_representor_id_encode(switch_info, 750 eth_da->type); 751 } 752 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 753 id = MLX5_REPRESENTOR_ID 754 (eth_da->ports[p], eth_da->type, 755 eth_da->representor_ports[f]); 756 if (repr_id == id) 757 return true; 758 } 759 } 760 rte_errno = EBUSY; 761 return false; 762 } 763 764 765 /** 766 * Spawn an Ethernet device from Verbs information. 767 * 768 * @param dpdk_dev 769 * Backing DPDK device. 770 * @param spawn 771 * Verbs device parameters (name, port, switch_info) to spawn. 772 * @param config 773 * Device configuration parameters. 774 * @param config 775 * Device arguments. 776 * 777 * @return 778 * A valid Ethernet device object on success, NULL otherwise and rte_errno 779 * is set. The following errors are defined: 780 * 781 * EBUSY: device is not supposed to be spawned. 782 * EEXIST: device is already spawned 783 */ 784 static struct rte_eth_dev * 785 mlx5_dev_spawn(struct rte_device *dpdk_dev, 786 struct mlx5_dev_spawn_data *spawn, 787 struct mlx5_dev_config *config, 788 struct rte_eth_devargs *eth_da) 789 { 790 const struct mlx5_switch_info *switch_info = &spawn->info; 791 struct mlx5_dev_ctx_shared *sh = NULL; 792 struct ibv_port_attr port_attr; 793 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 794 struct rte_eth_dev *eth_dev = NULL; 795 struct mlx5_priv *priv = NULL; 796 int err = 0; 797 unsigned int hw_padding = 0; 798 unsigned int mps; 799 unsigned int tunnel_en = 0; 800 unsigned int mpls_en = 0; 801 unsigned int swp = 0; 802 unsigned int mprq = 0; 803 unsigned int mprq_min_stride_size_n = 0; 804 unsigned int mprq_max_stride_size_n = 0; 805 unsigned int mprq_min_stride_num_n = 0; 806 unsigned int mprq_max_stride_num_n = 0; 807 struct rte_ether_addr mac; 808 char name[RTE_ETH_NAME_MAX_LEN]; 809 int own_domain_id = 0; 810 uint16_t port_id; 811 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 812 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 813 #endif 814 815 /* Determine if this port representor is supposed to be spawned. */ 816 if (switch_info->representor && dpdk_dev->devargs && 817 !mlx5_representor_match(spawn, eth_da)) 818 return NULL; 819 /* Build device name. */ 820 if (spawn->pf_bond < 0) { 821 /* Single device. */ 822 if (!switch_info->representor) 823 strlcpy(name, dpdk_dev->name, sizeof(name)); 824 else 825 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 826 dpdk_dev->name, 827 switch_info->name_type == 828 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 829 switch_info->port_name); 830 } else { 831 /* Bonding device. */ 832 if (!switch_info->representor) { 833 err = snprintf(name, sizeof(name), "%s_%s", 834 dpdk_dev->name, 835 mlx5_os_get_dev_device_name(spawn->phys_dev)); 836 } else { 837 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 838 dpdk_dev->name, 839 mlx5_os_get_dev_device_name(spawn->phys_dev), 840 switch_info->ctrl_num, 841 switch_info->pf_num, 842 switch_info->name_type == 843 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 844 switch_info->port_name); 845 } 846 } 847 if (err >= (int)sizeof(name)) 848 DRV_LOG(WARNING, "device name overflow %s", name); 849 /* check if the device is already spawned */ 850 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 851 rte_errno = EEXIST; 852 return NULL; 853 } 854 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 855 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 856 struct mlx5_mp_id mp_id; 857 858 eth_dev = rte_eth_dev_attach_secondary(name); 859 if (eth_dev == NULL) { 860 DRV_LOG(ERR, "can not attach rte ethdev"); 861 rte_errno = ENOMEM; 862 return NULL; 863 } 864 eth_dev->device = dpdk_dev; 865 eth_dev->dev_ops = &mlx5_dev_sec_ops; 866 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 867 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 868 err = mlx5_proc_priv_init(eth_dev); 869 if (err) 870 return NULL; 871 mp_id.port_id = eth_dev->data->port_id; 872 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 873 /* Receive command fd from primary process */ 874 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 875 if (err < 0) 876 goto err_secondary; 877 /* Remap UAR for Tx queues. */ 878 err = mlx5_tx_uar_init_secondary(eth_dev, err); 879 if (err) 880 goto err_secondary; 881 /* 882 * Ethdev pointer is still required as input since 883 * the primary device is not accessible from the 884 * secondary process. 885 */ 886 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 887 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 888 return eth_dev; 889 err_secondary: 890 mlx5_dev_close(eth_dev); 891 return NULL; 892 } 893 /* 894 * Some parameters ("tx_db_nc" in particularly) are needed in 895 * advance to create dv/verbs device context. We proceed the 896 * devargs here to get ones, and later proceed devargs again 897 * to override some hardware settings. 898 */ 899 err = mlx5_args(config, dpdk_dev->devargs); 900 if (err) { 901 err = rte_errno; 902 DRV_LOG(ERR, "failed to process device arguments: %s", 903 strerror(rte_errno)); 904 goto error; 905 } 906 if (config->dv_miss_info) { 907 if (switch_info->master || switch_info->representor) 908 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 909 } 910 mlx5_malloc_mem_select(config->sys_mem_en); 911 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 912 if (!sh) 913 return NULL; 914 config->devx = sh->devx; 915 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 916 config->dest_tir = 1; 917 #endif 918 #ifdef HAVE_IBV_MLX5_MOD_SWP 919 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 920 #endif 921 /* 922 * Multi-packet send is supported by ConnectX-4 Lx PF as well 923 * as all ConnectX-5 devices. 924 */ 925 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 926 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 927 #endif 928 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 929 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 930 #endif 931 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 932 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 933 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 934 DRV_LOG(DEBUG, "enhanced MPW is supported"); 935 mps = MLX5_MPW_ENHANCED; 936 } else { 937 DRV_LOG(DEBUG, "MPW is supported"); 938 mps = MLX5_MPW; 939 } 940 } else { 941 DRV_LOG(DEBUG, "MPW isn't supported"); 942 mps = MLX5_MPW_DISABLED; 943 } 944 #ifdef HAVE_IBV_MLX5_MOD_SWP 945 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 946 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 947 DRV_LOG(DEBUG, "SWP support: %u", swp); 948 #endif 949 config->swp = !!swp; 950 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 951 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 952 struct mlx5dv_striding_rq_caps mprq_caps = 953 dv_attr.striding_rq_caps; 954 955 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 956 mprq_caps.min_single_stride_log_num_of_bytes); 957 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 958 mprq_caps.max_single_stride_log_num_of_bytes); 959 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 960 mprq_caps.min_single_wqe_log_num_of_strides); 961 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 962 mprq_caps.max_single_wqe_log_num_of_strides); 963 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 964 mprq_caps.supported_qpts); 965 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 966 mprq = 1; 967 mprq_min_stride_size_n = 968 mprq_caps.min_single_stride_log_num_of_bytes; 969 mprq_max_stride_size_n = 970 mprq_caps.max_single_stride_log_num_of_bytes; 971 mprq_min_stride_num_n = 972 mprq_caps.min_single_wqe_log_num_of_strides; 973 mprq_max_stride_num_n = 974 mprq_caps.max_single_wqe_log_num_of_strides; 975 } 976 #endif 977 /* Rx CQE compression is enabled by default. */ 978 config->cqe_comp = 1; 979 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 980 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 981 tunnel_en = ((dv_attr.tunnel_offloads_caps & 982 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 983 (dv_attr.tunnel_offloads_caps & 984 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 985 (dv_attr.tunnel_offloads_caps & 986 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 987 } 988 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 989 tunnel_en ? "" : "not "); 990 #else 991 DRV_LOG(WARNING, 992 "tunnel offloading disabled due to old OFED/rdma-core version"); 993 #endif 994 config->tunnel_en = tunnel_en; 995 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 996 mpls_en = ((dv_attr.tunnel_offloads_caps & 997 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 998 (dv_attr.tunnel_offloads_caps & 999 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1000 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1001 mpls_en ? "" : "not "); 1002 #else 1003 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1004 " old OFED/rdma-core version or firmware configuration"); 1005 #endif 1006 config->mpls_en = mpls_en; 1007 /* Check port status. */ 1008 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1009 if (err) { 1010 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1011 goto error; 1012 } 1013 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1014 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1015 err = EINVAL; 1016 goto error; 1017 } 1018 if (port_attr.state != IBV_PORT_ACTIVE) 1019 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1020 mlx5_glue->port_state_str(port_attr.state), 1021 port_attr.state); 1022 /* Allocate private eth device data. */ 1023 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1024 sizeof(*priv), 1025 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1026 if (priv == NULL) { 1027 DRV_LOG(ERR, "priv allocation failure"); 1028 err = ENOMEM; 1029 goto error; 1030 } 1031 priv->sh = sh; 1032 priv->dev_port = spawn->phys_port; 1033 priv->pci_dev = spawn->pci_dev; 1034 priv->mtu = RTE_ETHER_MTU; 1035 /* Some internal functions rely on Netlink sockets, open them now. */ 1036 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1037 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1038 priv->representor = !!switch_info->representor; 1039 priv->master = !!switch_info->master; 1040 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1041 priv->vport_meta_tag = 0; 1042 priv->vport_meta_mask = 0; 1043 priv->pf_bond = spawn->pf_bond; 1044 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 1045 /* 1046 * The DevX port query API is implemented. E-Switch may use 1047 * either vport or reg_c[0] metadata register to match on 1048 * vport index. The engaged part of metadata register is 1049 * defined by mask. 1050 */ 1051 if (switch_info->representor || switch_info->master) { 1052 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 1053 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 1054 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 1055 &devx_port); 1056 if (err) { 1057 DRV_LOG(WARNING, 1058 "can't query devx port %d on device %s", 1059 spawn->phys_port, 1060 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1061 devx_port.comp_mask = 0; 1062 } 1063 } 1064 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 1065 priv->vport_meta_tag = devx_port.reg_c_0.value; 1066 priv->vport_meta_mask = devx_port.reg_c_0.mask; 1067 if (!priv->vport_meta_mask) { 1068 DRV_LOG(ERR, "vport zero mask for port %d" 1069 " on bonding device %s", 1070 spawn->phys_port, 1071 mlx5_os_get_dev_device_name 1072 (spawn->phys_dev)); 1073 err = ENOTSUP; 1074 goto error; 1075 } 1076 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1077 DRV_LOG(ERR, "invalid vport tag for port %d" 1078 " on bonding device %s", 1079 spawn->phys_port, 1080 mlx5_os_get_dev_device_name 1081 (spawn->phys_dev)); 1082 err = ENOTSUP; 1083 goto error; 1084 } 1085 } 1086 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 1087 priv->vport_id = devx_port.vport_num; 1088 } else if (spawn->pf_bond >= 0) { 1089 DRV_LOG(ERR, "can't deduce vport index for port %d" 1090 " on bonding device %s", 1091 spawn->phys_port, 1092 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1093 err = ENOTSUP; 1094 goto error; 1095 } else { 1096 /* Suppose vport index in compatible way. */ 1097 priv->vport_id = switch_info->representor ? 1098 switch_info->port_name + 1 : -1; 1099 } 1100 #else 1101 /* 1102 * Kernel/rdma_core support single E-Switch per PF configurations 1103 * only and vport_id field contains the vport index for 1104 * associated VF, which is deduced from representor port name. 1105 * For example, let's have the IB device port 10, it has 1106 * attached network device eth0, which has port name attribute 1107 * pf0vf2, we can deduce the VF number as 2, and set vport index 1108 * as 3 (2+1). This assigning schema should be changed if the 1109 * multiple E-Switch instances per PF configurations or/and PCI 1110 * subfunctions are added. 1111 */ 1112 priv->vport_id = switch_info->representor ? 1113 switch_info->port_name + 1 : -1; 1114 #endif 1115 priv->representor_id = mlx5_representor_id_encode(switch_info, 1116 eth_da->type); 1117 /* 1118 * Look for sibling devices in order to reuse their switch domain 1119 * if any, otherwise allocate one. 1120 */ 1121 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1122 const struct mlx5_priv *opriv = 1123 rte_eth_devices[port_id].data->dev_private; 1124 1125 if (!opriv || 1126 opriv->sh != priv->sh || 1127 opriv->domain_id == 1128 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1129 continue; 1130 priv->domain_id = opriv->domain_id; 1131 break; 1132 } 1133 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1134 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1135 if (err) { 1136 err = rte_errno; 1137 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1138 strerror(rte_errno)); 1139 goto error; 1140 } 1141 own_domain_id = 1; 1142 } 1143 /* Override some values set by hardware configuration. */ 1144 mlx5_args(config, dpdk_dev->devargs); 1145 err = mlx5_dev_check_sibling_config(priv, config); 1146 if (err) 1147 goto error; 1148 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1149 IBV_DEVICE_RAW_IP_CSUM); 1150 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1151 (config->hw_csum ? "" : "not ")); 1152 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1153 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1154 DRV_LOG(DEBUG, "counters are not supported"); 1155 #endif 1156 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1157 if (config->dv_flow_en) { 1158 DRV_LOG(WARNING, "DV flow is not supported"); 1159 config->dv_flow_en = 0; 1160 } 1161 #endif 1162 config->ind_table_max_size = 1163 sh->device_attr.max_rwq_indirection_table_size; 1164 /* 1165 * Remove this check once DPDK supports larger/variable 1166 * indirection tables. 1167 */ 1168 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1169 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1170 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1171 config->ind_table_max_size); 1172 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1173 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1174 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1175 (config->hw_vlan_strip ? "" : "not ")); 1176 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1177 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1178 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1179 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1180 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1181 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1182 IBV_DEVICE_PCI_WRITE_END_PADDING); 1183 #endif 1184 if (config->hw_padding && !hw_padding) { 1185 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1186 config->hw_padding = 0; 1187 } else if (config->hw_padding) { 1188 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1189 } 1190 config->tso = (sh->device_attr.max_tso > 0 && 1191 (sh->device_attr.tso_supported_qpts & 1192 (1 << IBV_QPT_RAW_PACKET))); 1193 if (config->tso) 1194 config->tso_max_payload_sz = sh->device_attr.max_tso; 1195 /* 1196 * MPW is disabled by default, while the Enhanced MPW is enabled 1197 * by default. 1198 */ 1199 if (config->mps == MLX5_ARG_UNSET) 1200 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1201 MLX5_MPW_DISABLED; 1202 else 1203 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1204 DRV_LOG(INFO, "%sMPS is %s", 1205 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1206 config->mps == MLX5_MPW ? "legacy " : "", 1207 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1208 if (config->devx) { 1209 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1210 if (err) { 1211 err = -err; 1212 goto error; 1213 } 1214 /* Check relax ordering support. */ 1215 if (!haswell_broadwell_cpu) { 1216 sh->cmng.relaxed_ordering_write = 1217 config->hca_attr.relaxed_ordering_write; 1218 sh->cmng.relaxed_ordering_read = 1219 config->hca_attr.relaxed_ordering_read; 1220 } else { 1221 sh->cmng.relaxed_ordering_read = 0; 1222 sh->cmng.relaxed_ordering_write = 0; 1223 } 1224 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1225 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1226 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1227 /* Check for LRO support. */ 1228 if (config->dest_tir && config->hca_attr.lro_cap && 1229 config->dv_flow_en) { 1230 /* TBD check tunnel lro caps. */ 1231 config->lro.supported = config->hca_attr.lro_cap; 1232 DRV_LOG(DEBUG, "Device supports LRO"); 1233 /* 1234 * If LRO timeout is not configured by application, 1235 * use the minimal supported value. 1236 */ 1237 if (!config->lro.timeout) 1238 config->lro.timeout = 1239 config->hca_attr.lro_timer_supported_periods[0]; 1240 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1241 config->lro.timeout); 1242 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1243 "required for coalescing is %d bytes", 1244 config->hca_attr.lro_min_mss_size); 1245 } 1246 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1247 if (config->hca_attr.qos.sup && 1248 config->hca_attr.qos.flow_meter_old && 1249 config->dv_flow_en) { 1250 uint8_t reg_c_mask = 1251 config->hca_attr.qos.flow_meter_reg_c_ids; 1252 /* 1253 * Meter needs two REG_C's for color match and pre-sfx 1254 * flow match. Here get the REG_C for color match. 1255 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1256 */ 1257 reg_c_mask &= 0xfc; 1258 if (__builtin_popcount(reg_c_mask) < 1) { 1259 priv->mtr_en = 0; 1260 DRV_LOG(WARNING, "No available register for" 1261 " meter."); 1262 } else { 1263 /* 1264 * The meter color register is used by the 1265 * flow-hit feature as well. 1266 * The flow-hit feature must use REG_C_3 1267 * Prefer REG_C_3 if it is available. 1268 */ 1269 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1270 priv->mtr_color_reg = REG_C_3; 1271 else 1272 priv->mtr_color_reg = ffs(reg_c_mask) 1273 - 1 + REG_C_0; 1274 priv->mtr_en = 1; 1275 priv->mtr_reg_share = 1276 config->hca_attr.qos.flow_meter; 1277 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1278 priv->mtr_color_reg); 1279 } 1280 } 1281 #endif 1282 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1283 if (config->hca_attr.flow_hit_aso && 1284 priv->mtr_color_reg == REG_C_3) { 1285 sh->flow_hit_aso_en = 1; 1286 err = mlx5_flow_aso_age_mng_init(sh); 1287 if (err) { 1288 err = -err; 1289 goto error; 1290 } 1291 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1292 } 1293 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1294 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1295 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1296 config->dv_flow_en) { 1297 priv->sampler_en = 1; 1298 DRV_LOG(DEBUG, "Sampler enabled!"); 1299 } else { 1300 priv->sampler_en = 0; 1301 if (!config->hca_attr.log_max_ft_sampler_num) 1302 DRV_LOG(WARNING, 1303 "No available register for sampler."); 1304 else 1305 DRV_LOG(DEBUG, "DV flow is not supported!"); 1306 } 1307 #endif 1308 } 1309 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1310 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1311 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1312 config->cqe_comp = 0; 1313 } 1314 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1315 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1316 DRV_LOG(WARNING, "Flow Tag CQE compression" 1317 " format isn't supported."); 1318 config->cqe_comp = 0; 1319 } 1320 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1321 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1322 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1323 " format isn't supported."); 1324 config->cqe_comp = 0; 1325 } 1326 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1327 config->cqe_comp ? "" : "not "); 1328 if (config->tx_pp) { 1329 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1330 config->hca_attr.dev_freq_khz); 1331 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1332 config->hca_attr.qos.packet_pacing ? "" : "not "); 1333 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1334 config->hca_attr.cross_channel ? "" : "not "); 1335 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1336 config->hca_attr.wqe_index_ignore ? "" : "not "); 1337 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1338 config->hca_attr.non_wire_sq ? "" : "not "); 1339 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1340 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1341 config->hca_attr.log_max_static_sq_wq); 1342 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1343 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1344 if (!config->devx) { 1345 DRV_LOG(ERR, "DevX is required for packet pacing"); 1346 err = ENODEV; 1347 goto error; 1348 } 1349 if (!config->hca_attr.qos.packet_pacing) { 1350 DRV_LOG(ERR, "Packet pacing is not supported"); 1351 err = ENODEV; 1352 goto error; 1353 } 1354 if (!config->hca_attr.cross_channel) { 1355 DRV_LOG(ERR, "Cross channel operations are" 1356 " required for packet pacing"); 1357 err = ENODEV; 1358 goto error; 1359 } 1360 if (!config->hca_attr.wqe_index_ignore) { 1361 DRV_LOG(ERR, "WQE index ignore feature is" 1362 " required for packet pacing"); 1363 err = ENODEV; 1364 goto error; 1365 } 1366 if (!config->hca_attr.non_wire_sq) { 1367 DRV_LOG(ERR, "Non-wire SQ feature is" 1368 " required for packet pacing"); 1369 err = ENODEV; 1370 goto error; 1371 } 1372 if (!config->hca_attr.log_max_static_sq_wq) { 1373 DRV_LOG(ERR, "Static WQE SQ feature is" 1374 " required for packet pacing"); 1375 err = ENODEV; 1376 goto error; 1377 } 1378 if (!config->hca_attr.qos.wqe_rate_pp) { 1379 DRV_LOG(ERR, "WQE rate mode is required" 1380 " for packet pacing"); 1381 err = ENODEV; 1382 goto error; 1383 } 1384 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1385 DRV_LOG(ERR, "DevX does not provide UAR offset," 1386 " can't create queues for packet pacing"); 1387 err = ENODEV; 1388 goto error; 1389 #endif 1390 } 1391 if (config->devx) { 1392 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1393 1394 err = config->hca_attr.access_register_user ? 1395 mlx5_devx_cmd_register_read 1396 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1397 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1398 if (!err) { 1399 uint32_t ts_mode; 1400 1401 /* MTUTC register is read successfully. */ 1402 ts_mode = MLX5_GET(register_mtutc, reg, 1403 time_stamp_mode); 1404 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1405 config->rt_timestamp = 1; 1406 } else { 1407 /* Kernel does not support register reading. */ 1408 if (config->hca_attr.dev_freq_khz == 1409 (NS_PER_S / MS_PER_S)) 1410 config->rt_timestamp = 1; 1411 } 1412 } 1413 /* 1414 * If HW has bug working with tunnel packet decapsulation and 1415 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1416 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1417 */ 1418 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1419 config->hw_fcs_strip = 0; 1420 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1421 (config->hw_fcs_strip ? "" : "not ")); 1422 if (config->mprq.enabled && mprq) { 1423 if (config->mprq.stride_num_n && 1424 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1425 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1426 config->mprq.stride_num_n = 1427 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1428 mprq_min_stride_num_n), 1429 mprq_max_stride_num_n); 1430 DRV_LOG(WARNING, 1431 "the number of strides" 1432 " for Multi-Packet RQ is out of range," 1433 " setting default value (%u)", 1434 1 << config->mprq.stride_num_n); 1435 } 1436 if (config->mprq.stride_size_n && 1437 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1438 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1439 config->mprq.stride_size_n = 1440 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1441 mprq_min_stride_size_n), 1442 mprq_max_stride_size_n); 1443 DRV_LOG(WARNING, 1444 "the size of a stride" 1445 " for Multi-Packet RQ is out of range," 1446 " setting default value (%u)", 1447 1 << config->mprq.stride_size_n); 1448 } 1449 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1450 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1451 } else if (config->mprq.enabled && !mprq) { 1452 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1453 config->mprq.enabled = 0; 1454 } 1455 if (config->max_dump_files_num == 0) 1456 config->max_dump_files_num = 128; 1457 eth_dev = rte_eth_dev_allocate(name); 1458 if (eth_dev == NULL) { 1459 DRV_LOG(ERR, "can not allocate rte ethdev"); 1460 err = ENOMEM; 1461 goto error; 1462 } 1463 if (priv->representor) { 1464 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1465 eth_dev->data->representor_id = priv->representor_id; 1466 } 1467 priv->mp_id.port_id = eth_dev->data->port_id; 1468 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1469 /* 1470 * Store associated network device interface index. This index 1471 * is permanent throughout the lifetime of device. So, we may store 1472 * the ifindex here and use the cached value further. 1473 */ 1474 MLX5_ASSERT(spawn->ifindex); 1475 priv->if_index = spawn->ifindex; 1476 eth_dev->data->dev_private = priv; 1477 priv->dev_data = eth_dev->data; 1478 eth_dev->data->mac_addrs = priv->mac; 1479 eth_dev->device = dpdk_dev; 1480 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1481 /* Configure the first MAC address by default. */ 1482 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1483 DRV_LOG(ERR, 1484 "port %u cannot get MAC address, is mlx5_en" 1485 " loaded? (errno: %s)", 1486 eth_dev->data->port_id, strerror(rte_errno)); 1487 err = ENODEV; 1488 goto error; 1489 } 1490 DRV_LOG(INFO, 1491 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1492 eth_dev->data->port_id, 1493 mac.addr_bytes[0], mac.addr_bytes[1], 1494 mac.addr_bytes[2], mac.addr_bytes[3], 1495 mac.addr_bytes[4], mac.addr_bytes[5]); 1496 #ifdef RTE_LIBRTE_MLX5_DEBUG 1497 { 1498 char ifname[MLX5_NAMESIZE]; 1499 1500 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1501 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1502 eth_dev->data->port_id, ifname); 1503 else 1504 DRV_LOG(DEBUG, "port %u ifname is unknown", 1505 eth_dev->data->port_id); 1506 } 1507 #endif 1508 /* Get actual MTU if possible. */ 1509 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1510 if (err) { 1511 err = rte_errno; 1512 goto error; 1513 } 1514 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1515 priv->mtu); 1516 /* Initialize burst functions to prevent crashes before link-up. */ 1517 eth_dev->rx_pkt_burst = removed_rx_burst; 1518 eth_dev->tx_pkt_burst = removed_tx_burst; 1519 eth_dev->dev_ops = &mlx5_dev_ops; 1520 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1521 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1522 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1523 /* Register MAC address. */ 1524 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1525 if (config->vf && config->vf_nl_en) 1526 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1527 mlx5_ifindex(eth_dev), 1528 eth_dev->data->mac_addrs, 1529 MLX5_MAX_MAC_ADDRESSES); 1530 priv->flows = 0; 1531 priv->ctrl_flows = 0; 1532 rte_spinlock_init(&priv->flow_list_lock); 1533 TAILQ_INIT(&priv->flow_meters); 1534 TAILQ_INIT(&priv->flow_meter_profiles); 1535 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1536 mlx5_glue->dv_set_context_attr(sh->ctx, 1537 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1538 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1539 .alloc = &mlx5_alloc_verbs_buf, 1540 .free = &mlx5_free_verbs_buf, 1541 .data = sh, 1542 })); 1543 /* Bring Ethernet device up. */ 1544 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1545 eth_dev->data->port_id); 1546 mlx5_set_link_up(eth_dev); 1547 /* 1548 * Even though the interrupt handler is not installed yet, 1549 * interrupts will still trigger on the async_fd from 1550 * Verbs context returned by ibv_open_device(). 1551 */ 1552 mlx5_link_update(eth_dev, 0); 1553 #ifdef HAVE_MLX5DV_DR_ESWITCH 1554 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1555 (switch_info->representor || switch_info->master))) 1556 config->dv_esw_en = 0; 1557 #else 1558 config->dv_esw_en = 0; 1559 #endif 1560 /* Detect minimal data bytes to inline. */ 1561 mlx5_set_min_inline(spawn, config); 1562 /* Store device configuration on private structure. */ 1563 priv->config = *config; 1564 /* Create context for virtual machine VLAN workaround. */ 1565 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1566 if (config->dv_flow_en) { 1567 err = mlx5_alloc_shared_dr(priv); 1568 if (err) 1569 goto error; 1570 } 1571 if (config->devx && config->dv_flow_en && config->dest_tir) { 1572 priv->obj_ops = devx_obj_ops; 1573 priv->obj_ops.drop_action_create = 1574 ibv_obj_ops.drop_action_create; 1575 priv->obj_ops.drop_action_destroy = 1576 ibv_obj_ops.drop_action_destroy; 1577 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1578 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1579 #else 1580 if (config->dv_esw_en) 1581 priv->obj_ops.txq_obj_modify = 1582 ibv_obj_ops.txq_obj_modify; 1583 #endif 1584 /* Use specific wrappers for Tx object. */ 1585 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1586 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1587 mlx5_queue_counter_id_prepare(eth_dev); 1588 1589 } else { 1590 priv->obj_ops = ibv_obj_ops; 1591 } 1592 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1593 if (!priv->drop_queue.hrxq) 1594 goto error; 1595 /* Supported Verbs flow priority number detection. */ 1596 err = mlx5_flow_discover_priorities(eth_dev); 1597 if (err < 0) { 1598 err = -err; 1599 goto error; 1600 } 1601 priv->config.flow_prio = err; 1602 if (!priv->config.dv_esw_en && 1603 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1604 DRV_LOG(WARNING, "metadata mode %u is not supported " 1605 "(no E-Switch)", priv->config.dv_xmeta_en); 1606 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1607 } 1608 mlx5_set_metadata_mask(eth_dev); 1609 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1610 !priv->sh->dv_regc0_mask) { 1611 DRV_LOG(ERR, "metadata mode %u is not supported " 1612 "(no metadata reg_c[0] is available)", 1613 priv->config.dv_xmeta_en); 1614 err = ENOTSUP; 1615 goto error; 1616 } 1617 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 1618 mlx5_hrxq_create_cb, 1619 mlx5_hrxq_match_cb, 1620 mlx5_hrxq_remove_cb); 1621 /* Query availability of metadata reg_c's. */ 1622 err = mlx5_flow_discover_mreg_c(eth_dev); 1623 if (err < 0) { 1624 err = -err; 1625 goto error; 1626 } 1627 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1628 DRV_LOG(DEBUG, 1629 "port %u extensive metadata register is not supported", 1630 eth_dev->data->port_id); 1631 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1632 DRV_LOG(ERR, "metadata mode %u is not supported " 1633 "(no metadata registers available)", 1634 priv->config.dv_xmeta_en); 1635 err = ENOTSUP; 1636 goto error; 1637 } 1638 } 1639 if (priv->config.dv_flow_en && 1640 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1641 mlx5_flow_ext_mreg_supported(eth_dev) && 1642 priv->sh->dv_regc0_mask) { 1643 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1644 MLX5_FLOW_MREG_HTABLE_SZ, 1645 0, 0, 1646 flow_dv_mreg_create_cb, 1647 flow_dv_mreg_match_cb, 1648 flow_dv_mreg_remove_cb); 1649 if (!priv->mreg_cp_tbl) { 1650 err = ENOMEM; 1651 goto error; 1652 } 1653 priv->mreg_cp_tbl->ctx = eth_dev; 1654 } 1655 rte_spinlock_init(&priv->shared_act_sl); 1656 mlx5_flow_counter_mode_config(eth_dev); 1657 if (priv->config.dv_flow_en) 1658 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1659 return eth_dev; 1660 error: 1661 if (priv) { 1662 if (priv->mreg_cp_tbl) 1663 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1664 if (priv->sh) 1665 mlx5_os_free_shared_dr(priv); 1666 if (priv->nl_socket_route >= 0) 1667 close(priv->nl_socket_route); 1668 if (priv->nl_socket_rdma >= 0) 1669 close(priv->nl_socket_rdma); 1670 if (priv->vmwa_context) 1671 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1672 if (eth_dev && priv->drop_queue.hrxq) 1673 mlx5_drop_action_destroy(eth_dev); 1674 if (own_domain_id) 1675 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1676 mlx5_cache_list_destroy(&priv->hrxqs); 1677 mlx5_free(priv); 1678 if (eth_dev != NULL) 1679 eth_dev->data->dev_private = NULL; 1680 } 1681 if (eth_dev != NULL) { 1682 /* mac_addrs must not be freed alone because part of 1683 * dev_private 1684 **/ 1685 eth_dev->data->mac_addrs = NULL; 1686 rte_eth_dev_release_port(eth_dev); 1687 } 1688 if (sh) 1689 mlx5_free_shared_dev_ctx(sh); 1690 MLX5_ASSERT(err > 0); 1691 rte_errno = err; 1692 return NULL; 1693 } 1694 1695 /** 1696 * Comparison callback to sort device data. 1697 * 1698 * This is meant to be used with qsort(). 1699 * 1700 * @param a[in] 1701 * Pointer to pointer to first data object. 1702 * @param b[in] 1703 * Pointer to pointer to second data object. 1704 * 1705 * @return 1706 * 0 if both objects are equal, less than 0 if the first argument is less 1707 * than the second, greater than 0 otherwise. 1708 */ 1709 static int 1710 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1711 { 1712 const struct mlx5_switch_info *si_a = 1713 &((const struct mlx5_dev_spawn_data *)a)->info; 1714 const struct mlx5_switch_info *si_b = 1715 &((const struct mlx5_dev_spawn_data *)b)->info; 1716 int ret; 1717 1718 /* Master device first. */ 1719 ret = si_b->master - si_a->master; 1720 if (ret) 1721 return ret; 1722 /* Then representor devices. */ 1723 ret = si_b->representor - si_a->representor; 1724 if (ret) 1725 return ret; 1726 /* Unidentified devices come last in no specific order. */ 1727 if (!si_a->representor) 1728 return 0; 1729 /* Order representors by name. */ 1730 return si_a->port_name - si_b->port_name; 1731 } 1732 1733 /** 1734 * Match PCI information for possible slaves of bonding device. 1735 * 1736 * @param[in] ibv_dev 1737 * Pointer to Infiniband device structure. 1738 * @param[in] pci_dev 1739 * Pointer to primary PCI address structure to match. 1740 * @param[in] nl_rdma 1741 * Netlink RDMA group socket handle. 1742 * @param[in] owner 1743 * Rerepsentor owner PF index. 1744 * @param[out] bond_info 1745 * Pointer to bonding information. 1746 * 1747 * @return 1748 * negative value if no bonding device found, otherwise 1749 * positive index of slave PF in bonding. 1750 */ 1751 static int 1752 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1753 const struct rte_pci_addr *pci_dev, 1754 int nl_rdma, uint16_t owner, 1755 struct mlx5_bond_info *bond_info) 1756 { 1757 char ifname[IF_NAMESIZE + 1]; 1758 unsigned int ifindex; 1759 unsigned int np, i; 1760 FILE *bond_file = NULL, *file; 1761 int pf = -1; 1762 int ret; 1763 1764 /* 1765 * Try to get master device name. If something goes 1766 * wrong suppose the lack of kernel support and no 1767 * bonding devices. 1768 */ 1769 memset(bond_info, 0, sizeof(*bond_info)); 1770 if (nl_rdma < 0) 1771 return -1; 1772 if (!strstr(ibv_dev->name, "bond")) 1773 return -1; 1774 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1775 if (!np) 1776 return -1; 1777 /* 1778 * The Master device might not be on the predefined 1779 * port (not on port index 1, it is not garanted), 1780 * we have to scan all Infiniband device port and 1781 * find master. 1782 */ 1783 for (i = 1; i <= np; ++i) { 1784 /* Check whether Infiniband port is populated. */ 1785 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1786 if (!ifindex) 1787 continue; 1788 if (!if_indextoname(ifindex, ifname)) 1789 continue; 1790 /* Try to read bonding slave names from sysfs. */ 1791 MKSTR(slaves, 1792 "/sys/class/net/%s/master/bonding/slaves", ifname); 1793 bond_file = fopen(slaves, "r"); 1794 if (bond_file) 1795 break; 1796 } 1797 if (!bond_file) 1798 return -1; 1799 /* Use safe format to check maximal buffer length. */ 1800 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1801 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1802 char tmp_str[IF_NAMESIZE + 32]; 1803 struct rte_pci_addr pci_addr; 1804 struct mlx5_switch_info info; 1805 1806 /* Process slave interface names in the loop. */ 1807 snprintf(tmp_str, sizeof(tmp_str), 1808 "/sys/class/net/%s", ifname); 1809 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1810 DRV_LOG(WARNING, "can not get PCI address" 1811 " for netdev \"%s\"", ifname); 1812 continue; 1813 } 1814 /* Slave interface PCI address match found. */ 1815 snprintf(tmp_str, sizeof(tmp_str), 1816 "/sys/class/net/%s/phys_port_name", ifname); 1817 file = fopen(tmp_str, "rb"); 1818 if (!file) 1819 break; 1820 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1821 if (fscanf(file, "%32s", tmp_str) == 1) 1822 mlx5_translate_port_name(tmp_str, &info); 1823 fclose(file); 1824 /* Only process PF ports. */ 1825 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1826 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1827 continue; 1828 /* Check max bonding member. */ 1829 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1830 DRV_LOG(WARNING, "bonding index out of range, " 1831 "please increase MLX5_BOND_MAX_PORTS: %s", 1832 tmp_str); 1833 break; 1834 } 1835 /* Match PCI address. */ 1836 if (pci_dev->domain == pci_addr.domain && 1837 pci_dev->bus == pci_addr.bus && 1838 pci_dev->devid == pci_addr.devid && 1839 pci_dev->function + owner == pci_addr.function) 1840 pf = info.port_name; 1841 /* Get ifindex. */ 1842 snprintf(tmp_str, sizeof(tmp_str), 1843 "/sys/class/net/%s/ifindex", ifname); 1844 file = fopen(tmp_str, "rb"); 1845 if (!file) 1846 break; 1847 ret = fscanf(file, "%u", &ifindex); 1848 fclose(file); 1849 if (ret != 1) 1850 break; 1851 /* Save bonding info. */ 1852 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1853 sizeof(bond_info->ports[0].ifname)); 1854 bond_info->ports[info.port_name].pci_addr = pci_addr; 1855 bond_info->ports[info.port_name].ifindex = ifindex; 1856 bond_info->n_port++; 1857 } 1858 if (pf >= 0) { 1859 /* Get bond interface info */ 1860 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 1861 bond_info->ifname); 1862 if (ret) 1863 DRV_LOG(ERR, "unable to get bond info: %s", 1864 strerror(rte_errno)); 1865 else 1866 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1867 ifindex, bond_info->ifindex, bond_info->ifname); 1868 } 1869 return pf; 1870 } 1871 1872 /** 1873 * Register a PCI device within bonding. 1874 * 1875 * This function spawns Ethernet devices out of a given PCI device and 1876 * bonding owner PF index. 1877 * 1878 * @param[in] pci_dev 1879 * PCI device information. 1880 * @param[in] req_eth_da 1881 * Requested ethdev device argument. 1882 * @param[in] owner_id 1883 * Requested owner PF port ID within bonding device, default to 0. 1884 * 1885 * @return 1886 * 0 on success, a negative errno value otherwise and rte_errno is set. 1887 */ 1888 static int 1889 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 1890 struct rte_eth_devargs *req_eth_da, 1891 uint16_t owner_id) 1892 { 1893 struct ibv_device **ibv_list; 1894 /* 1895 * Number of found IB Devices matching with requested PCI BDF. 1896 * nd != 1 means there are multiple IB devices over the same 1897 * PCI device and we have representors and master. 1898 */ 1899 unsigned int nd = 0; 1900 /* 1901 * Number of found IB device Ports. nd = 1 and np = 1..n means 1902 * we have the single multiport IB device, and there may be 1903 * representors attached to some of found ports. 1904 */ 1905 unsigned int np = 0; 1906 /* 1907 * Number of DPDK ethernet devices to Spawn - either over 1908 * multiple IB devices or multiple ports of single IB device. 1909 * Actually this is the number of iterations to spawn. 1910 */ 1911 unsigned int ns = 0; 1912 /* 1913 * Bonding device 1914 * < 0 - no bonding device (single one) 1915 * >= 0 - bonding device (value is slave PF index) 1916 */ 1917 int bd = -1; 1918 struct mlx5_dev_spawn_data *list = NULL; 1919 struct mlx5_dev_config dev_config; 1920 unsigned int dev_config_vf; 1921 struct rte_eth_devargs eth_da = *req_eth_da; 1922 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 1923 struct mlx5_bond_info bond_info; 1924 int ret = -1; 1925 1926 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1927 mlx5_pmd_socket_init(); 1928 ret = mlx5_init_once(); 1929 if (ret) { 1930 DRV_LOG(ERR, "unable to init PMD global data: %s", 1931 strerror(rte_errno)); 1932 return -rte_errno; 1933 } 1934 errno = 0; 1935 ibv_list = mlx5_glue->get_device_list(&ret); 1936 if (!ibv_list) { 1937 rte_errno = errno ? errno : ENOSYS; 1938 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1939 return -rte_errno; 1940 } 1941 /* 1942 * First scan the list of all Infiniband devices to find 1943 * matching ones, gathering into the list. 1944 */ 1945 struct ibv_device *ibv_match[ret + 1]; 1946 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1947 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1948 unsigned int i; 1949 1950 while (ret-- > 0) { 1951 struct rte_pci_addr pci_addr; 1952 1953 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1954 bd = mlx5_device_bond_pci_match 1955 (ibv_list[ret], &owner_pci, nl_rdma, owner_id, 1956 &bond_info); 1957 if (bd >= 0) { 1958 /* 1959 * Bonding device detected. Only one match is allowed, 1960 * the bonding is supported over multi-port IB device, 1961 * there should be no matches on representor PCI 1962 * functions or non VF LAG bonding devices with 1963 * specified address. 1964 */ 1965 if (nd) { 1966 DRV_LOG(ERR, 1967 "multiple PCI match on bonding device" 1968 "\"%s\" found", ibv_list[ret]->name); 1969 rte_errno = ENOENT; 1970 ret = -rte_errno; 1971 goto exit; 1972 } 1973 /* Amend owner pci address if owner PF ID specified. */ 1974 if (eth_da.nb_representor_ports) 1975 owner_pci.function += owner_id; 1976 DRV_LOG(INFO, "PCI information matches for" 1977 " slave %d bonding device \"%s\"", 1978 bd, ibv_list[ret]->name); 1979 ibv_match[nd++] = ibv_list[ret]; 1980 break; 1981 } else { 1982 /* Bonding device not found. */ 1983 if (mlx5_dev_to_pci_addr 1984 (ibv_list[ret]->ibdev_path, &pci_addr)) 1985 continue; 1986 if (owner_pci.domain != pci_addr.domain || 1987 owner_pci.bus != pci_addr.bus || 1988 owner_pci.devid != pci_addr.devid || 1989 owner_pci.function != pci_addr.function) 1990 continue; 1991 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1992 ibv_list[ret]->name); 1993 ibv_match[nd++] = ibv_list[ret]; 1994 } 1995 } 1996 ibv_match[nd] = NULL; 1997 if (!nd) { 1998 /* No device matches, just complain and bail out. */ 1999 DRV_LOG(WARNING, 2000 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2001 " are kernel drivers loaded?", 2002 owner_pci.domain, owner_pci.bus, 2003 owner_pci.devid, owner_pci.function); 2004 rte_errno = ENOENT; 2005 ret = -rte_errno; 2006 goto exit; 2007 } 2008 if (nd == 1) { 2009 /* 2010 * Found single matching device may have multiple ports. 2011 * Each port may be representor, we have to check the port 2012 * number and check the representors existence. 2013 */ 2014 if (nl_rdma >= 0) 2015 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2016 if (!np) 2017 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2018 " ports number", ibv_match[0]->name); 2019 if (bd >= 0 && !np) { 2020 DRV_LOG(ERR, "can not get ports" 2021 " for bonding device"); 2022 rte_errno = ENOENT; 2023 ret = -rte_errno; 2024 goto exit; 2025 } 2026 } 2027 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 2028 if (bd >= 0) { 2029 /* 2030 * This may happen if there is VF LAG kernel support and 2031 * application is compiled with older rdma_core library. 2032 */ 2033 DRV_LOG(ERR, 2034 "No kernel/verbs support for VF LAG bonding found."); 2035 rte_errno = ENOTSUP; 2036 ret = -rte_errno; 2037 goto exit; 2038 } 2039 #endif 2040 /* 2041 * Now we can determine the maximal 2042 * amount of devices to be spawned. 2043 */ 2044 list = mlx5_malloc(MLX5_MEM_ZERO, 2045 sizeof(struct mlx5_dev_spawn_data) * 2046 (np ? np : nd), 2047 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2048 if (!list) { 2049 DRV_LOG(ERR, "spawn data array allocation failure"); 2050 rte_errno = ENOMEM; 2051 ret = -rte_errno; 2052 goto exit; 2053 } 2054 if (bd >= 0 || np > 1) { 2055 /* 2056 * Single IB device with multiple ports found, 2057 * it may be E-Switch master device and representors. 2058 * We have to perform identification through the ports. 2059 */ 2060 MLX5_ASSERT(nl_rdma >= 0); 2061 MLX5_ASSERT(ns == 0); 2062 MLX5_ASSERT(nd == 1); 2063 MLX5_ASSERT(np); 2064 for (i = 1; i <= np; ++i) { 2065 list[ns].bond_info = &bond_info; 2066 list[ns].max_port = np; 2067 list[ns].phys_port = i; 2068 list[ns].phys_dev = ibv_match[0]; 2069 list[ns].eth_dev = NULL; 2070 list[ns].pci_dev = pci_dev; 2071 list[ns].pf_bond = bd; 2072 list[ns].ifindex = mlx5_nl_ifindex 2073 (nl_rdma, 2074 mlx5_os_get_dev_device_name 2075 (list[ns].phys_dev), i); 2076 if (!list[ns].ifindex) { 2077 /* 2078 * No network interface index found for the 2079 * specified port, it means there is no 2080 * representor on this port. It's OK, 2081 * there can be disabled ports, for example 2082 * if sriov_numvfs < sriov_totalvfs. 2083 */ 2084 continue; 2085 } 2086 ret = -1; 2087 if (nl_route >= 0) 2088 ret = mlx5_nl_switch_info 2089 (nl_route, 2090 list[ns].ifindex, 2091 &list[ns].info); 2092 if (ret || (!list[ns].info.representor && 2093 !list[ns].info.master)) { 2094 /* 2095 * We failed to recognize representors with 2096 * Netlink, let's try to perform the task 2097 * with sysfs. 2098 */ 2099 ret = mlx5_sysfs_switch_info 2100 (list[ns].ifindex, 2101 &list[ns].info); 2102 } 2103 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2104 if (!ret && bd >= 0) { 2105 switch (list[ns].info.name_type) { 2106 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2107 if (list[ns].info.port_name == bd) 2108 ns++; 2109 break; 2110 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2111 /* Fallthrough */ 2112 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2113 /* Fallthrough */ 2114 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2115 if (list[ns].info.pf_num == bd) 2116 ns++; 2117 break; 2118 default: 2119 break; 2120 } 2121 continue; 2122 } 2123 #endif 2124 if (!ret && (list[ns].info.representor ^ 2125 list[ns].info.master)) 2126 ns++; 2127 } 2128 if (!ns) { 2129 DRV_LOG(ERR, 2130 "unable to recognize master/representors" 2131 " on the IB device with multiple ports"); 2132 rte_errno = ENOENT; 2133 ret = -rte_errno; 2134 goto exit; 2135 } 2136 } else { 2137 /* 2138 * The existence of several matching entries (nd > 1) means 2139 * port representors have been instantiated. No existing Verbs 2140 * call nor sysfs entries can tell them apart, this can only 2141 * be done through Netlink calls assuming kernel drivers are 2142 * recent enough to support them. 2143 * 2144 * In the event of identification failure through Netlink, 2145 * try again through sysfs, then: 2146 * 2147 * 1. A single IB device matches (nd == 1) with single 2148 * port (np=0/1) and is not a representor, assume 2149 * no switch support. 2150 * 2151 * 2. Otherwise no safe assumptions can be made; 2152 * complain louder and bail out. 2153 */ 2154 for (i = 0; i != nd; ++i) { 2155 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2156 list[ns].bond_info = NULL; 2157 list[ns].max_port = 1; 2158 list[ns].phys_port = 1; 2159 list[ns].phys_dev = ibv_match[i]; 2160 list[ns].eth_dev = NULL; 2161 list[ns].pci_dev = pci_dev; 2162 list[ns].pf_bond = -1; 2163 list[ns].ifindex = 0; 2164 if (nl_rdma >= 0) 2165 list[ns].ifindex = mlx5_nl_ifindex 2166 (nl_rdma, 2167 mlx5_os_get_dev_device_name 2168 (list[ns].phys_dev), 1); 2169 if (!list[ns].ifindex) { 2170 char ifname[IF_NAMESIZE]; 2171 2172 /* 2173 * Netlink failed, it may happen with old 2174 * ib_core kernel driver (before 4.16). 2175 * We can assume there is old driver because 2176 * here we are processing single ports IB 2177 * devices. Let's try sysfs to retrieve 2178 * the ifindex. The method works for 2179 * master device only. 2180 */ 2181 if (nd > 1) { 2182 /* 2183 * Multiple devices found, assume 2184 * representors, can not distinguish 2185 * master/representor and retrieve 2186 * ifindex via sysfs. 2187 */ 2188 continue; 2189 } 2190 ret = mlx5_get_ifname_sysfs 2191 (ibv_match[i]->ibdev_path, ifname); 2192 if (!ret) 2193 list[ns].ifindex = 2194 if_nametoindex(ifname); 2195 if (!list[ns].ifindex) { 2196 /* 2197 * No network interface index found 2198 * for the specified device, it means 2199 * there it is neither representor 2200 * nor master. 2201 */ 2202 continue; 2203 } 2204 } 2205 ret = -1; 2206 if (nl_route >= 0) 2207 ret = mlx5_nl_switch_info 2208 (nl_route, 2209 list[ns].ifindex, 2210 &list[ns].info); 2211 if (ret || (!list[ns].info.representor && 2212 !list[ns].info.master)) { 2213 /* 2214 * We failed to recognize representors with 2215 * Netlink, let's try to perform the task 2216 * with sysfs. 2217 */ 2218 ret = mlx5_sysfs_switch_info 2219 (list[ns].ifindex, 2220 &list[ns].info); 2221 } 2222 if (!ret && (list[ns].info.representor ^ 2223 list[ns].info.master)) { 2224 ns++; 2225 } else if ((nd == 1) && 2226 !list[ns].info.representor && 2227 !list[ns].info.master) { 2228 /* 2229 * Single IB device with 2230 * one physical port and 2231 * attached network device. 2232 * May be SRIOV is not enabled 2233 * or there is no representors. 2234 */ 2235 DRV_LOG(INFO, "no E-Switch support detected"); 2236 ns++; 2237 break; 2238 } 2239 } 2240 if (!ns) { 2241 DRV_LOG(ERR, 2242 "unable to recognize master/representors" 2243 " on the multiple IB devices"); 2244 rte_errno = ENOENT; 2245 ret = -rte_errno; 2246 goto exit; 2247 } 2248 } 2249 MLX5_ASSERT(ns); 2250 /* 2251 * Sort list to probe devices in natural order for users convenience 2252 * (i.e. master first, then representors from lowest to highest ID). 2253 */ 2254 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2255 /* Device specific configuration. */ 2256 switch (pci_dev->id.device_id) { 2257 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2258 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2259 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2260 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2261 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2262 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2263 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2264 dev_config_vf = 1; 2265 break; 2266 default: 2267 dev_config_vf = 0; 2268 break; 2269 } 2270 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2271 /* Set devargs default values. */ 2272 if (eth_da.nb_mh_controllers == 0) { 2273 eth_da.nb_mh_controllers = 1; 2274 eth_da.mh_controllers[0] = 0; 2275 } 2276 if (eth_da.nb_ports == 0 && ns > 0) { 2277 if (list[0].pf_bond >= 0 && list[0].info.representor) 2278 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2279 pci_dev->device.devargs->args); 2280 eth_da.nb_ports = 1; 2281 eth_da.ports[0] = list[0].info.pf_num; 2282 } 2283 if (eth_da.nb_representor_ports == 0) { 2284 eth_da.nb_representor_ports = 1; 2285 eth_da.representor_ports[0] = 0; 2286 } 2287 } 2288 for (i = 0; i != ns; ++i) { 2289 uint32_t restore; 2290 2291 /* Default configuration. */ 2292 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2293 dev_config.vf = dev_config_vf; 2294 dev_config.mps = MLX5_ARG_UNSET; 2295 dev_config.dbnc = MLX5_ARG_UNSET; 2296 dev_config.rx_vec_en = 1; 2297 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2298 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2299 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2300 dev_config.txqs_inline = MLX5_ARG_UNSET; 2301 dev_config.vf_nl_en = 1; 2302 dev_config.mr_ext_memseg_en = 1; 2303 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2304 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2305 dev_config.dv_esw_en = 1; 2306 dev_config.dv_flow_en = 1; 2307 dev_config.decap_en = 1; 2308 dev_config.log_hp_size = MLX5_ARG_UNSET; 2309 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2310 &list[i], 2311 &dev_config, 2312 ð_da); 2313 if (!list[i].eth_dev) { 2314 if (rte_errno != EBUSY && rte_errno != EEXIST) 2315 break; 2316 /* Device is disabled or already spawned. Ignore it. */ 2317 continue; 2318 } 2319 restore = list[i].eth_dev->data->dev_flags; 2320 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2321 /* Restore non-PCI flags cleared by the above call. */ 2322 list[i].eth_dev->data->dev_flags |= restore; 2323 rte_eth_dev_probing_finish(list[i].eth_dev); 2324 } 2325 if (i != ns) { 2326 DRV_LOG(ERR, 2327 "probe of PCI device " PCI_PRI_FMT " aborted after" 2328 " encountering an error: %s", 2329 owner_pci.domain, owner_pci.bus, 2330 owner_pci.devid, owner_pci.function, 2331 strerror(rte_errno)); 2332 ret = -rte_errno; 2333 /* Roll back. */ 2334 while (i--) { 2335 if (!list[i].eth_dev) 2336 continue; 2337 mlx5_dev_close(list[i].eth_dev); 2338 /* mac_addrs must not be freed because in dev_private */ 2339 list[i].eth_dev->data->mac_addrs = NULL; 2340 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2341 } 2342 /* Restore original error. */ 2343 rte_errno = -ret; 2344 } else { 2345 ret = 0; 2346 } 2347 exit: 2348 /* 2349 * Do the routine cleanup: 2350 * - close opened Netlink sockets 2351 * - free allocated spawn data array 2352 * - free the Infiniband device list 2353 */ 2354 if (nl_rdma >= 0) 2355 close(nl_rdma); 2356 if (nl_route >= 0) 2357 close(nl_route); 2358 if (list) 2359 mlx5_free(list); 2360 MLX5_ASSERT(ibv_list); 2361 mlx5_glue->free_device_list(ibv_list); 2362 return ret; 2363 } 2364 2365 /** 2366 * DPDK callback to register a PCI device. 2367 * 2368 * This function spawns Ethernet devices out of a given PCI device. 2369 * 2370 * @param[in] pci_drv 2371 * PCI driver structure (mlx5_driver). 2372 * @param[in] pci_dev 2373 * PCI device information. 2374 * 2375 * @return 2376 * 0 on success, a negative errno value otherwise and rte_errno is set. 2377 */ 2378 int 2379 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2380 struct rte_pci_device *pci_dev) 2381 { 2382 struct rte_eth_devargs eth_da = { .type = RTE_ETH_REPRESENTOR_NONE }; 2383 int ret = 0; 2384 uint16_t p; 2385 2386 if (pci_dev->device.devargs) { 2387 /* Parse representor information from device argument. */ 2388 if (pci_dev->device.devargs->cls_str) 2389 ret = rte_eth_devargs_parse 2390 (pci_dev->device.devargs->cls_str, ð_da); 2391 if (ret) { 2392 DRV_LOG(ERR, "failed to parse device arguments: %s", 2393 pci_dev->device.devargs->cls_str); 2394 return -rte_errno; 2395 } 2396 if (eth_da.type == RTE_ETH_REPRESENTOR_NONE) { 2397 /* Support legacy device argument */ 2398 ret = rte_eth_devargs_parse 2399 (pci_dev->device.devargs->args, ð_da); 2400 if (ret) { 2401 DRV_LOG(ERR, "failed to parse device arguments: %s", 2402 pci_dev->device.devargs->args); 2403 return -rte_errno; 2404 } 2405 } 2406 } 2407 2408 if (eth_da.nb_ports > 0) { 2409 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2410 for (p = 0; p < eth_da.nb_ports; p++) 2411 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2412 eth_da.ports[p]); 2413 } else { 2414 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2415 } 2416 return ret; 2417 } 2418 2419 static int 2420 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2421 { 2422 char *env; 2423 int value; 2424 2425 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2426 /* Get environment variable to store. */ 2427 env = getenv(MLX5_SHUT_UP_BF); 2428 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2429 if (config->dbnc == MLX5_ARG_UNSET) 2430 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2431 else 2432 setenv(MLX5_SHUT_UP_BF, 2433 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2434 return value; 2435 } 2436 2437 static void 2438 mlx5_restore_doorbell_mapping_env(int value) 2439 { 2440 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2441 /* Restore the original environment variable state. */ 2442 if (value == MLX5_ARG_UNSET) 2443 unsetenv(MLX5_SHUT_UP_BF); 2444 else 2445 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2446 } 2447 2448 /** 2449 * Extract pdn of PD object using DV API. 2450 * 2451 * @param[in] pd 2452 * Pointer to the verbs PD object. 2453 * @param[out] pdn 2454 * Pointer to the PD object number variable. 2455 * 2456 * @return 2457 * 0 on success, error value otherwise. 2458 */ 2459 int 2460 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2461 { 2462 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2463 struct mlx5dv_obj obj; 2464 struct mlx5dv_pd pd_info; 2465 int ret = 0; 2466 2467 obj.pd.in = pd; 2468 obj.pd.out = &pd_info; 2469 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2470 if (ret) { 2471 DRV_LOG(DEBUG, "Fail to get PD object info"); 2472 return ret; 2473 } 2474 *pdn = pd_info.pdn; 2475 return 0; 2476 #else 2477 (void)pd; 2478 (void)pdn; 2479 return -ENOTSUP; 2480 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2481 } 2482 2483 /** 2484 * Function API to open IB device. 2485 * 2486 * This function calls the Linux glue APIs to open a device. 2487 * 2488 * @param[in] spawn 2489 * Pointer to the IB device attributes (name, port, etc). 2490 * @param[out] config 2491 * Pointer to device configuration structure. 2492 * @param[out] sh 2493 * Pointer to shared context structure. 2494 * 2495 * @return 2496 * 0 on success, a positive error value otherwise. 2497 */ 2498 int 2499 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2500 const struct mlx5_dev_config *config, 2501 struct mlx5_dev_ctx_shared *sh) 2502 { 2503 int dbmap_env; 2504 int err = 0; 2505 2506 sh->numa_node = spawn->pci_dev->device.numa_node; 2507 pthread_mutex_init(&sh->txpp.mutex, NULL); 2508 /* 2509 * Configure environment variable "MLX5_BF_SHUT_UP" 2510 * before the device creation. The rdma_core library 2511 * checks the variable at device creation and 2512 * stores the result internally. 2513 */ 2514 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2515 /* Try to open IB device with DV first, then usual Verbs. */ 2516 errno = 0; 2517 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2518 if (sh->ctx) { 2519 sh->devx = 1; 2520 DRV_LOG(DEBUG, "DevX is supported"); 2521 /* The device is created, no need for environment. */ 2522 mlx5_restore_doorbell_mapping_env(dbmap_env); 2523 } else { 2524 /* The environment variable is still configured. */ 2525 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2526 err = errno ? errno : ENODEV; 2527 /* 2528 * The environment variable is not needed anymore, 2529 * all device creation attempts are completed. 2530 */ 2531 mlx5_restore_doorbell_mapping_env(dbmap_env); 2532 if (!sh->ctx) 2533 return err; 2534 DRV_LOG(DEBUG, "DevX is NOT supported"); 2535 err = 0; 2536 } 2537 if (!err && sh->ctx) { 2538 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2539 mlx5_glue->dv_set_context_attr(sh->ctx, 2540 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2541 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2542 .alloc = &mlx5_alloc_verbs_buf, 2543 .free = &mlx5_free_verbs_buf, 2544 .data = sh, 2545 })); 2546 } 2547 return err; 2548 } 2549 2550 /** 2551 * Install shared asynchronous device events handler. 2552 * This function is implemented to support event sharing 2553 * between multiple ports of single IB device. 2554 * 2555 * @param sh 2556 * Pointer to mlx5_dev_ctx_shared object. 2557 */ 2558 void 2559 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2560 { 2561 int ret; 2562 int flags; 2563 2564 sh->intr_handle.fd = -1; 2565 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2566 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2567 F_SETFL, flags | O_NONBLOCK); 2568 if (ret) { 2569 DRV_LOG(INFO, "failed to change file descriptor async event" 2570 " queue"); 2571 } else { 2572 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2573 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2574 if (rte_intr_callback_register(&sh->intr_handle, 2575 mlx5_dev_interrupt_handler, sh)) { 2576 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2577 sh->intr_handle.fd = -1; 2578 } 2579 } 2580 if (sh->devx) { 2581 #ifdef HAVE_IBV_DEVX_ASYNC 2582 sh->intr_handle_devx.fd = -1; 2583 sh->devx_comp = 2584 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2585 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2586 if (!devx_comp) { 2587 DRV_LOG(INFO, "failed to allocate devx_comp."); 2588 return; 2589 } 2590 flags = fcntl(devx_comp->fd, F_GETFL); 2591 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2592 if (ret) { 2593 DRV_LOG(INFO, "failed to change file descriptor" 2594 " devx comp"); 2595 return; 2596 } 2597 sh->intr_handle_devx.fd = devx_comp->fd; 2598 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2599 if (rte_intr_callback_register(&sh->intr_handle_devx, 2600 mlx5_dev_interrupt_handler_devx, sh)) { 2601 DRV_LOG(INFO, "Fail to install the devx shared" 2602 " interrupt."); 2603 sh->intr_handle_devx.fd = -1; 2604 } 2605 #endif /* HAVE_IBV_DEVX_ASYNC */ 2606 } 2607 } 2608 2609 /** 2610 * Uninstall shared asynchronous device events handler. 2611 * This function is implemented to support event sharing 2612 * between multiple ports of single IB device. 2613 * 2614 * @param dev 2615 * Pointer to mlx5_dev_ctx_shared object. 2616 */ 2617 void 2618 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2619 { 2620 if (sh->intr_handle.fd >= 0) 2621 mlx5_intr_callback_unregister(&sh->intr_handle, 2622 mlx5_dev_interrupt_handler, sh); 2623 #ifdef HAVE_IBV_DEVX_ASYNC 2624 if (sh->intr_handle_devx.fd >= 0) 2625 rte_intr_callback_unregister(&sh->intr_handle_devx, 2626 mlx5_dev_interrupt_handler_devx, sh); 2627 if (sh->devx_comp) 2628 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2629 #endif 2630 } 2631 2632 /** 2633 * Read statistics by a named counter. 2634 * 2635 * @param[in] priv 2636 * Pointer to the private device data structure. 2637 * @param[in] ctr_name 2638 * Pointer to the name of the statistic counter to read 2639 * @param[out] stat 2640 * Pointer to read statistic value. 2641 * @return 2642 * 0 on success and stat is valud, 1 if failed to read the value 2643 * rte_errno is set. 2644 * 2645 */ 2646 int 2647 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2648 uint64_t *stat) 2649 { 2650 int fd; 2651 2652 if (priv->sh) { 2653 if (priv->q_counters != NULL && 2654 strcmp(ctr_name, "out_of_buffer") == 0) 2655 return mlx5_devx_cmd_queue_counter_query(priv->sh->ctx, 2656 0, (uint32_t *)stat); 2657 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2658 priv->sh->ibdev_path, 2659 priv->dev_port, 2660 ctr_name); 2661 fd = open(path, O_RDONLY); 2662 /* 2663 * in switchdev the file location is not per port 2664 * but rather in <ibdev_path>/hw_counters/<file_name>. 2665 */ 2666 if (fd == -1) { 2667 MKSTR(path1, "%s/hw_counters/%s", 2668 priv->sh->ibdev_path, 2669 ctr_name); 2670 fd = open(path1, O_RDONLY); 2671 } 2672 if (fd != -1) { 2673 char buf[21] = {'\0'}; 2674 ssize_t n = read(fd, buf, sizeof(buf)); 2675 2676 close(fd); 2677 if (n != -1) { 2678 *stat = strtoull(buf, NULL, 10); 2679 return 0; 2680 } 2681 } 2682 } 2683 *stat = 0; 2684 return 1; 2685 } 2686 2687 /** 2688 * Set the reg_mr and dereg_mr call backs 2689 * 2690 * @param reg_mr_cb[out] 2691 * Pointer to reg_mr func 2692 * @param dereg_mr_cb[out] 2693 * Pointer to dereg_mr func 2694 * 2695 */ 2696 void 2697 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2698 mlx5_dereg_mr_t *dereg_mr_cb) 2699 { 2700 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 2701 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 2702 } 2703 2704 /** 2705 * Remove a MAC address from device 2706 * 2707 * @param dev 2708 * Pointer to Ethernet device structure. 2709 * @param index 2710 * MAC address index. 2711 */ 2712 void 2713 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2714 { 2715 struct mlx5_priv *priv = dev->data->dev_private; 2716 const int vf = priv->config.vf; 2717 2718 if (vf) 2719 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2720 mlx5_ifindex(dev), priv->mac_own, 2721 &dev->data->mac_addrs[index], index); 2722 } 2723 2724 /** 2725 * Adds a MAC address to the device 2726 * 2727 * @param dev 2728 * Pointer to Ethernet device structure. 2729 * @param mac_addr 2730 * MAC address to register. 2731 * @param index 2732 * MAC address index. 2733 * 2734 * @return 2735 * 0 on success, a negative errno value otherwise 2736 */ 2737 int 2738 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2739 uint32_t index) 2740 { 2741 struct mlx5_priv *priv = dev->data->dev_private; 2742 const int vf = priv->config.vf; 2743 int ret = 0; 2744 2745 if (vf) 2746 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2747 mlx5_ifindex(dev), priv->mac_own, 2748 mac, index); 2749 return ret; 2750 } 2751 2752 /** 2753 * Modify a VF MAC address 2754 * 2755 * @param priv 2756 * Pointer to device private data. 2757 * @param mac_addr 2758 * MAC address to modify into. 2759 * @param iface_idx 2760 * Net device interface index 2761 * @param vf_index 2762 * VF index 2763 * 2764 * @return 2765 * 0 on success, a negative errno value otherwise 2766 */ 2767 int 2768 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2769 unsigned int iface_idx, 2770 struct rte_ether_addr *mac_addr, 2771 int vf_index) 2772 { 2773 return mlx5_nl_vf_mac_addr_modify 2774 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2775 } 2776 2777 /** 2778 * Set device promiscuous mode 2779 * 2780 * @param dev 2781 * Pointer to Ethernet device structure. 2782 * @param enable 2783 * 0 - promiscuous is disabled, otherwise - enabled 2784 * 2785 * @return 2786 * 0 on success, a negative error value otherwise 2787 */ 2788 int 2789 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2790 { 2791 struct mlx5_priv *priv = dev->data->dev_private; 2792 2793 return mlx5_nl_promisc(priv->nl_socket_route, 2794 mlx5_ifindex(dev), !!enable); 2795 } 2796 2797 /** 2798 * Set device promiscuous mode 2799 * 2800 * @param dev 2801 * Pointer to Ethernet device structure. 2802 * @param enable 2803 * 0 - all multicase is disabled, otherwise - enabled 2804 * 2805 * @return 2806 * 0 on success, a negative error value otherwise 2807 */ 2808 int 2809 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2810 { 2811 struct mlx5_priv *priv = dev->data->dev_private; 2812 2813 return mlx5_nl_allmulti(priv->nl_socket_route, 2814 mlx5_ifindex(dev), !!enable); 2815 } 2816 2817 /** 2818 * Flush device MAC addresses 2819 * 2820 * @param dev 2821 * Pointer to Ethernet device structure. 2822 * 2823 */ 2824 void 2825 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2826 { 2827 struct mlx5_priv *priv = dev->data->dev_private; 2828 2829 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2830 dev->data->mac_addrs, 2831 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2832 } 2833