1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_qp = attr_ex.orig_attr.max_qp; 120 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 121 device_attr->max_rwq_indirection_table_size = 122 attr_ex.rss_caps.max_rwq_indirection_table_size; 123 device_attr->max_tso = attr_ex.tso_caps.max_tso; 124 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 125 126 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 127 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 128 if (err) 129 return err; 130 131 device_attr->flags = dv_attr.flags; 132 device_attr->comp_mask = dv_attr.comp_mask; 133 #ifdef HAVE_IBV_MLX5_MOD_SWP 134 device_attr->sw_parsing_offloads = 135 dv_attr.sw_parsing_caps.sw_parsing_offloads; 136 #endif 137 device_attr->min_single_stride_log_num_of_bytes = 138 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 139 device_attr->max_single_stride_log_num_of_bytes = 140 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 141 device_attr->min_single_wqe_log_num_of_strides = 142 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 143 device_attr->max_single_wqe_log_num_of_strides = 144 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 145 device_attr->stride_supported_qpts = 146 dv_attr.striding_rq_caps.supported_qpts; 147 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 148 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 149 #endif 150 151 return err; 152 } 153 154 /** 155 * Verbs callback to allocate a memory. This function should allocate the space 156 * according to the size provided residing inside a huge page. 157 * Please note that all allocation must respect the alignment from libmlx5 158 * (i.e. currently rte_mem_page_size()). 159 * 160 * @param[in] size 161 * The size in bytes of the memory to allocate. 162 * @param[in] data 163 * A pointer to the callback data. 164 * 165 * @return 166 * Allocated buffer, NULL otherwise and rte_errno is set. 167 */ 168 static void * 169 mlx5_alloc_verbs_buf(size_t size, void *data) 170 { 171 struct mlx5_priv *priv = data; 172 void *ret; 173 unsigned int socket = SOCKET_ID_ANY; 174 size_t alignment = rte_mem_page_size(); 175 if (alignment == (size_t)-1) { 176 DRV_LOG(ERR, "Failed to get mem page size"); 177 rte_errno = ENOMEM; 178 return NULL; 179 } 180 181 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 182 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 183 184 socket = ctrl->socket; 185 } else if (priv->verbs_alloc_ctx.type == 186 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 187 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 188 189 socket = ctrl->socket; 190 } 191 MLX5_ASSERT(data != NULL); 192 ret = mlx5_malloc(0, size, alignment, socket); 193 if (!ret && size) 194 rte_errno = ENOMEM; 195 return ret; 196 } 197 198 /** 199 * Verbs callback to free a memory. 200 * 201 * @param[in] ptr 202 * A pointer to the memory to free. 203 * @param[in] data 204 * A pointer to the callback data. 205 */ 206 static void 207 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 208 { 209 MLX5_ASSERT(data != NULL); 210 mlx5_free(ptr); 211 } 212 213 /** 214 * Initialize DR related data within private structure. 215 * Routine checks the reference counter and does actual 216 * resources creation/initialization only if counter is zero. 217 * 218 * @param[in] priv 219 * Pointer to the private device data structure. 220 * 221 * @return 222 * Zero on success, positive error code otherwise. 223 */ 224 static int 225 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 226 { 227 struct mlx5_dev_ctx_shared *sh = priv->sh; 228 char s[MLX5_HLIST_NAMESIZE]; 229 int err; 230 231 MLX5_ASSERT(sh && sh->refcnt); 232 if (sh->refcnt > 1) 233 return 0; 234 err = mlx5_alloc_table_hash_list(priv); 235 if (err) 236 return err; 237 /* Create tags hash list table. */ 238 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 239 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE); 240 if (!sh->tag_table) { 241 DRV_LOG(ERR, "tags with hash creation failed."); 242 err = ENOMEM; 243 goto error; 244 } 245 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 246 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ); 247 if (!sh->modify_cmds) { 248 DRV_LOG(ERR, "hdr modify hash creation failed"); 249 err = ENOMEM; 250 goto error; 251 } 252 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 253 sh->encaps_decaps = mlx5_hlist_create(s, 254 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ); 255 if (!sh->encaps_decaps) { 256 DRV_LOG(ERR, "encap decap hash creation failed"); 257 err = ENOMEM; 258 goto error; 259 } 260 #ifdef HAVE_MLX5DV_DR 261 void *domain; 262 263 /* Reference counter is zero, we should initialize structures. */ 264 domain = mlx5_glue->dr_create_domain(sh->ctx, 265 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 266 if (!domain) { 267 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 268 err = errno; 269 goto error; 270 } 271 sh->rx_domain = domain; 272 domain = mlx5_glue->dr_create_domain(sh->ctx, 273 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 274 if (!domain) { 275 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 276 err = errno; 277 goto error; 278 } 279 pthread_mutex_init(&sh->dv_mutex, NULL); 280 sh->tx_domain = domain; 281 #ifdef HAVE_MLX5DV_DR_ESWITCH 282 if (priv->config.dv_esw_en) { 283 domain = mlx5_glue->dr_create_domain 284 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 285 if (!domain) { 286 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 287 err = errno; 288 goto error; 289 } 290 sh->fdb_domain = domain; 291 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 292 } 293 #endif 294 if (!sh->tunnel_hub) 295 err = mlx5_alloc_tunnel_hub(sh); 296 if (err) { 297 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 298 goto error; 299 } 300 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 301 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 302 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 303 if (sh->fdb_domain) 304 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 305 } 306 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 307 #endif /* HAVE_MLX5DV_DR */ 308 sh->default_miss_action = 309 mlx5_glue->dr_create_flow_action_default_miss(); 310 if (!sh->default_miss_action) 311 DRV_LOG(WARNING, "Default miss action is not supported."); 312 return 0; 313 error: 314 /* Rollback the created objects. */ 315 if (sh->rx_domain) { 316 mlx5_glue->dr_destroy_domain(sh->rx_domain); 317 sh->rx_domain = NULL; 318 } 319 if (sh->tx_domain) { 320 mlx5_glue->dr_destroy_domain(sh->tx_domain); 321 sh->tx_domain = NULL; 322 } 323 if (sh->fdb_domain) { 324 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 325 sh->fdb_domain = NULL; 326 } 327 if (sh->esw_drop_action) { 328 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 329 sh->esw_drop_action = NULL; 330 } 331 if (sh->pop_vlan_action) { 332 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 333 sh->pop_vlan_action = NULL; 334 } 335 if (sh->encaps_decaps) { 336 mlx5_hlist_destroy(sh->encaps_decaps, NULL, NULL); 337 sh->encaps_decaps = NULL; 338 } 339 if (sh->modify_cmds) { 340 mlx5_hlist_destroy(sh->modify_cmds, NULL, NULL); 341 sh->modify_cmds = NULL; 342 } 343 if (sh->tag_table) { 344 /* tags should be destroyed with flow before. */ 345 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 346 sh->tag_table = NULL; 347 } 348 if (sh->tunnel_hub) { 349 mlx5_release_tunnel_hub(sh, priv->dev_port); 350 sh->tunnel_hub = NULL; 351 } 352 mlx5_free_table_hash_list(priv); 353 return err; 354 } 355 356 /** 357 * Destroy DR related data within private structure. 358 * 359 * @param[in] priv 360 * Pointer to the private device data structure. 361 */ 362 void 363 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 364 { 365 struct mlx5_dev_ctx_shared *sh = priv->sh; 366 367 MLX5_ASSERT(sh && sh->refcnt); 368 if (sh->refcnt > 1) 369 return; 370 #ifdef HAVE_MLX5DV_DR 371 if (sh->rx_domain) { 372 mlx5_glue->dr_destroy_domain(sh->rx_domain); 373 sh->rx_domain = NULL; 374 } 375 if (sh->tx_domain) { 376 mlx5_glue->dr_destroy_domain(sh->tx_domain); 377 sh->tx_domain = NULL; 378 } 379 #ifdef HAVE_MLX5DV_DR_ESWITCH 380 if (sh->fdb_domain) { 381 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 382 sh->fdb_domain = NULL; 383 } 384 if (sh->esw_drop_action) { 385 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 386 sh->esw_drop_action = NULL; 387 } 388 #endif 389 if (sh->pop_vlan_action) { 390 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 391 sh->pop_vlan_action = NULL; 392 } 393 pthread_mutex_destroy(&sh->dv_mutex); 394 #endif /* HAVE_MLX5DV_DR */ 395 if (sh->default_miss_action) 396 mlx5_glue->destroy_flow_action 397 (sh->default_miss_action); 398 if (sh->encaps_decaps) { 399 mlx5_hlist_destroy(sh->encaps_decaps, NULL, NULL); 400 sh->encaps_decaps = NULL; 401 } 402 if (sh->modify_cmds) { 403 mlx5_hlist_destroy(sh->modify_cmds, NULL, NULL); 404 sh->modify_cmds = NULL; 405 } 406 if (sh->tag_table) { 407 /* tags should be destroyed with flow before. */ 408 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 409 sh->tag_table = NULL; 410 } 411 if (sh->tunnel_hub) { 412 mlx5_release_tunnel_hub(sh, priv->dev_port); 413 sh->tunnel_hub = NULL; 414 } 415 mlx5_free_table_hash_list(priv); 416 } 417 418 /** 419 * Initialize shared data between primary and secondary process. 420 * 421 * A memzone is reserved by primary process and secondary processes attach to 422 * the memzone. 423 * 424 * @return 425 * 0 on success, a negative errno value otherwise and rte_errno is set. 426 */ 427 static int 428 mlx5_init_shared_data(void) 429 { 430 const struct rte_memzone *mz; 431 int ret = 0; 432 433 rte_spinlock_lock(&mlx5_shared_data_lock); 434 if (mlx5_shared_data == NULL) { 435 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 436 /* Allocate shared memory. */ 437 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 438 sizeof(*mlx5_shared_data), 439 SOCKET_ID_ANY, 0); 440 if (mz == NULL) { 441 DRV_LOG(ERR, 442 "Cannot allocate mlx5 shared data"); 443 ret = -rte_errno; 444 goto error; 445 } 446 mlx5_shared_data = mz->addr; 447 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 448 rte_spinlock_init(&mlx5_shared_data->lock); 449 } else { 450 /* Lookup allocated shared memory. */ 451 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 452 if (mz == NULL) { 453 DRV_LOG(ERR, 454 "Cannot attach mlx5 shared data"); 455 ret = -rte_errno; 456 goto error; 457 } 458 mlx5_shared_data = mz->addr; 459 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 460 } 461 } 462 error: 463 rte_spinlock_unlock(&mlx5_shared_data_lock); 464 return ret; 465 } 466 467 /** 468 * PMD global initialization. 469 * 470 * Independent from individual device, this function initializes global 471 * per-PMD data structures distinguishing primary and secondary processes. 472 * Hence, each initialization is called once per a process. 473 * 474 * @return 475 * 0 on success, a negative errno value otherwise and rte_errno is set. 476 */ 477 static int 478 mlx5_init_once(void) 479 { 480 struct mlx5_shared_data *sd; 481 struct mlx5_local_data *ld = &mlx5_local_data; 482 int ret = 0; 483 484 if (mlx5_init_shared_data()) 485 return -rte_errno; 486 sd = mlx5_shared_data; 487 MLX5_ASSERT(sd); 488 rte_spinlock_lock(&sd->lock); 489 switch (rte_eal_process_type()) { 490 case RTE_PROC_PRIMARY: 491 if (sd->init_done) 492 break; 493 LIST_INIT(&sd->mem_event_cb_list); 494 rte_rwlock_init(&sd->mem_event_rwlock); 495 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 496 mlx5_mr_mem_event_cb, NULL); 497 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 498 mlx5_mp_os_primary_handle); 499 if (ret) 500 goto out; 501 sd->init_done = true; 502 break; 503 case RTE_PROC_SECONDARY: 504 if (ld->init_done) 505 break; 506 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 507 mlx5_mp_os_secondary_handle); 508 if (ret) 509 goto out; 510 ++sd->secondary_cnt; 511 ld->init_done = true; 512 break; 513 default: 514 break; 515 } 516 out: 517 rte_spinlock_unlock(&sd->lock); 518 return ret; 519 } 520 521 /** 522 * Create the Tx queue DevX/Verbs object. 523 * 524 * @param dev 525 * Pointer to Ethernet device. 526 * @param idx 527 * Queue index in DPDK Tx queue array. 528 * 529 * @return 530 * 0 on success, a negative errno value otherwise and rte_errno is set. 531 */ 532 static int 533 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 534 { 535 struct mlx5_priv *priv = dev->data->dev_private; 536 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 537 struct mlx5_txq_ctrl *txq_ctrl = 538 container_of(txq_data, struct mlx5_txq_ctrl, txq); 539 540 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 541 return mlx5_txq_devx_obj_new(dev, idx); 542 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 543 if (!priv->config.dv_esw_en) 544 return mlx5_txq_devx_obj_new(dev, idx); 545 #endif 546 return mlx5_txq_ibv_obj_new(dev, idx); 547 } 548 549 /** 550 * Release an Tx DevX/verbs queue object. 551 * 552 * @param txq_obj 553 * DevX/Verbs Tx queue object. 554 */ 555 static void 556 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 557 { 558 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 559 mlx5_txq_devx_obj_release(txq_obj); 560 return; 561 } 562 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 563 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 564 mlx5_txq_devx_obj_release(txq_obj); 565 return; 566 } 567 #endif 568 mlx5_txq_ibv_obj_release(txq_obj); 569 } 570 571 /** 572 * DV flow counter mode detect and config. 573 * 574 * @param dev 575 * Pointer to rte_eth_dev structure. 576 * 577 */ 578 static void 579 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 580 { 581 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 582 struct mlx5_priv *priv = dev->data->dev_private; 583 struct mlx5_dev_ctx_shared *sh = priv->sh; 584 bool fallback; 585 586 #ifndef HAVE_IBV_DEVX_ASYNC 587 fallback = true; 588 #else 589 fallback = false; 590 if (!priv->config.devx || !priv->config.dv_flow_en || 591 !priv->config.hca_attr.flow_counters_dump || 592 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 593 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 594 fallback = true; 595 #endif 596 if (fallback) 597 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 598 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 599 priv->config.hca_attr.flow_counters_dump, 600 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 601 /* Initialize fallback mode only on the port initializes sh. */ 602 if (sh->refcnt == 1) 603 sh->cmng.counter_fallback = fallback; 604 else if (fallback != sh->cmng.counter_fallback) 605 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 606 "with others:%d.", PORT_ID(priv), fallback); 607 #endif 608 } 609 610 /** 611 * Spawn an Ethernet device from Verbs information. 612 * 613 * @param dpdk_dev 614 * Backing DPDK device. 615 * @param spawn 616 * Verbs device parameters (name, port, switch_info) to spawn. 617 * @param config 618 * Device configuration parameters. 619 * 620 * @return 621 * A valid Ethernet device object on success, NULL otherwise and rte_errno 622 * is set. The following errors are defined: 623 * 624 * EBUSY: device is not supposed to be spawned. 625 * EEXIST: device is already spawned 626 */ 627 static struct rte_eth_dev * 628 mlx5_dev_spawn(struct rte_device *dpdk_dev, 629 struct mlx5_dev_spawn_data *spawn, 630 struct mlx5_dev_config *config) 631 { 632 const struct mlx5_switch_info *switch_info = &spawn->info; 633 struct mlx5_dev_ctx_shared *sh = NULL; 634 struct ibv_port_attr port_attr; 635 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 636 struct rte_eth_dev *eth_dev = NULL; 637 struct mlx5_priv *priv = NULL; 638 int err = 0; 639 unsigned int hw_padding = 0; 640 unsigned int mps; 641 unsigned int cqe_comp; 642 unsigned int cqe_pad = 0; 643 unsigned int tunnel_en = 0; 644 unsigned int mpls_en = 0; 645 unsigned int swp = 0; 646 unsigned int mprq = 0; 647 unsigned int mprq_min_stride_size_n = 0; 648 unsigned int mprq_max_stride_size_n = 0; 649 unsigned int mprq_min_stride_num_n = 0; 650 unsigned int mprq_max_stride_num_n = 0; 651 struct rte_ether_addr mac; 652 char name[RTE_ETH_NAME_MAX_LEN]; 653 int own_domain_id = 0; 654 uint16_t port_id; 655 unsigned int i; 656 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 657 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 658 #endif 659 660 /* Determine if this port representor is supposed to be spawned. */ 661 if (switch_info->representor && dpdk_dev->devargs) { 662 struct rte_eth_devargs eth_da; 663 664 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 665 if (err) { 666 rte_errno = -err; 667 DRV_LOG(ERR, "failed to process device arguments: %s", 668 strerror(rte_errno)); 669 return NULL; 670 } 671 for (i = 0; i < eth_da.nb_representor_ports; ++i) 672 if (eth_da.representor_ports[i] == 673 (uint16_t)switch_info->port_name) 674 break; 675 if (i == eth_da.nb_representor_ports) { 676 rte_errno = EBUSY; 677 return NULL; 678 } 679 } 680 /* Build device name. */ 681 if (spawn->pf_bond < 0) { 682 /* Single device. */ 683 if (!switch_info->representor) 684 strlcpy(name, dpdk_dev->name, sizeof(name)); 685 else 686 snprintf(name, sizeof(name), "%s_representor_%u", 687 dpdk_dev->name, switch_info->port_name); 688 } else { 689 /* Bonding device. */ 690 if (!switch_info->representor) 691 snprintf(name, sizeof(name), "%s_%s", 692 dpdk_dev->name, 693 mlx5_os_get_dev_device_name(spawn->phys_dev)); 694 else 695 snprintf(name, sizeof(name), "%s_%s_representor_%u", 696 dpdk_dev->name, 697 mlx5_os_get_dev_device_name(spawn->phys_dev), 698 switch_info->port_name); 699 } 700 /* check if the device is already spawned */ 701 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 702 rte_errno = EEXIST; 703 return NULL; 704 } 705 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 706 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 707 struct mlx5_mp_id mp_id; 708 709 eth_dev = rte_eth_dev_attach_secondary(name); 710 if (eth_dev == NULL) { 711 DRV_LOG(ERR, "can not attach rte ethdev"); 712 rte_errno = ENOMEM; 713 return NULL; 714 } 715 eth_dev->device = dpdk_dev; 716 eth_dev->dev_ops = &mlx5_os_dev_sec_ops; 717 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 718 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 719 err = mlx5_proc_priv_init(eth_dev); 720 if (err) 721 return NULL; 722 mp_id.port_id = eth_dev->data->port_id; 723 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 724 /* Receive command fd from primary process */ 725 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 726 if (err < 0) 727 goto err_secondary; 728 /* Remap UAR for Tx queues. */ 729 err = mlx5_tx_uar_init_secondary(eth_dev, err); 730 if (err) 731 goto err_secondary; 732 /* 733 * Ethdev pointer is still required as input since 734 * the primary device is not accessible from the 735 * secondary process. 736 */ 737 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 738 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 739 return eth_dev; 740 err_secondary: 741 mlx5_dev_close(eth_dev); 742 return NULL; 743 } 744 /* 745 * Some parameters ("tx_db_nc" in particularly) are needed in 746 * advance to create dv/verbs device context. We proceed the 747 * devargs here to get ones, and later proceed devargs again 748 * to override some hardware settings. 749 */ 750 err = mlx5_args(config, dpdk_dev->devargs); 751 if (err) { 752 err = rte_errno; 753 DRV_LOG(ERR, "failed to process device arguments: %s", 754 strerror(rte_errno)); 755 goto error; 756 } 757 if (config->dv_miss_info) { 758 if (switch_info->master || switch_info->representor) 759 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 760 } 761 mlx5_malloc_mem_select(config->sys_mem_en); 762 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 763 if (!sh) 764 return NULL; 765 config->devx = sh->devx; 766 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 767 config->dest_tir = 1; 768 #endif 769 #ifdef HAVE_IBV_MLX5_MOD_SWP 770 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 771 #endif 772 /* 773 * Multi-packet send is supported by ConnectX-4 Lx PF as well 774 * as all ConnectX-5 devices. 775 */ 776 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 777 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 778 #endif 779 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 780 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 781 #endif 782 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 783 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 784 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 785 DRV_LOG(DEBUG, "enhanced MPW is supported"); 786 mps = MLX5_MPW_ENHANCED; 787 } else { 788 DRV_LOG(DEBUG, "MPW is supported"); 789 mps = MLX5_MPW; 790 } 791 } else { 792 DRV_LOG(DEBUG, "MPW isn't supported"); 793 mps = MLX5_MPW_DISABLED; 794 } 795 #ifdef HAVE_IBV_MLX5_MOD_SWP 796 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 797 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 798 DRV_LOG(DEBUG, "SWP support: %u", swp); 799 #endif 800 config->swp = !!swp; 801 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 802 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 803 struct mlx5dv_striding_rq_caps mprq_caps = 804 dv_attr.striding_rq_caps; 805 806 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 807 mprq_caps.min_single_stride_log_num_of_bytes); 808 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 809 mprq_caps.max_single_stride_log_num_of_bytes); 810 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 811 mprq_caps.min_single_wqe_log_num_of_strides); 812 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 813 mprq_caps.max_single_wqe_log_num_of_strides); 814 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 815 mprq_caps.supported_qpts); 816 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 817 mprq = 1; 818 mprq_min_stride_size_n = 819 mprq_caps.min_single_stride_log_num_of_bytes; 820 mprq_max_stride_size_n = 821 mprq_caps.max_single_stride_log_num_of_bytes; 822 mprq_min_stride_num_n = 823 mprq_caps.min_single_wqe_log_num_of_strides; 824 mprq_max_stride_num_n = 825 mprq_caps.max_single_wqe_log_num_of_strides; 826 } 827 #endif 828 if (RTE_CACHE_LINE_SIZE == 128 && 829 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 830 cqe_comp = 0; 831 else 832 cqe_comp = 1; 833 config->cqe_comp = cqe_comp; 834 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 835 /* Whether device supports 128B Rx CQE padding. */ 836 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 837 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 838 #endif 839 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 840 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 841 tunnel_en = ((dv_attr.tunnel_offloads_caps & 842 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 843 (dv_attr.tunnel_offloads_caps & 844 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 845 (dv_attr.tunnel_offloads_caps & 846 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 847 } 848 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 849 tunnel_en ? "" : "not "); 850 #else 851 DRV_LOG(WARNING, 852 "tunnel offloading disabled due to old OFED/rdma-core version"); 853 #endif 854 config->tunnel_en = tunnel_en; 855 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 856 mpls_en = ((dv_attr.tunnel_offloads_caps & 857 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 858 (dv_attr.tunnel_offloads_caps & 859 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 860 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 861 mpls_en ? "" : "not "); 862 #else 863 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 864 " old OFED/rdma-core version or firmware configuration"); 865 #endif 866 config->mpls_en = mpls_en; 867 /* Check port status. */ 868 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 869 if (err) { 870 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 871 goto error; 872 } 873 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 874 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 875 err = EINVAL; 876 goto error; 877 } 878 if (port_attr.state != IBV_PORT_ACTIVE) 879 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 880 mlx5_glue->port_state_str(port_attr.state), 881 port_attr.state); 882 /* Allocate private eth device data. */ 883 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 884 sizeof(*priv), 885 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 886 if (priv == NULL) { 887 DRV_LOG(ERR, "priv allocation failure"); 888 err = ENOMEM; 889 goto error; 890 } 891 priv->sh = sh; 892 priv->dev_port = spawn->phys_port; 893 priv->pci_dev = spawn->pci_dev; 894 priv->mtu = RTE_ETHER_MTU; 895 priv->mp_id.port_id = port_id; 896 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 897 /* Some internal functions rely on Netlink sockets, open them now. */ 898 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 899 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 900 priv->representor = !!switch_info->representor; 901 priv->master = !!switch_info->master; 902 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 903 priv->vport_meta_tag = 0; 904 priv->vport_meta_mask = 0; 905 priv->pf_bond = spawn->pf_bond; 906 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 907 /* 908 * The DevX port query API is implemented. E-Switch may use 909 * either vport or reg_c[0] metadata register to match on 910 * vport index. The engaged part of metadata register is 911 * defined by mask. 912 */ 913 if (switch_info->representor || switch_info->master) { 914 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 915 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 916 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 917 &devx_port); 918 if (err) { 919 DRV_LOG(WARNING, 920 "can't query devx port %d on device %s", 921 spawn->phys_port, 922 mlx5_os_get_dev_device_name(spawn->phys_dev)); 923 devx_port.comp_mask = 0; 924 } 925 } 926 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 927 priv->vport_meta_tag = devx_port.reg_c_0.value; 928 priv->vport_meta_mask = devx_port.reg_c_0.mask; 929 if (!priv->vport_meta_mask) { 930 DRV_LOG(ERR, "vport zero mask for port %d" 931 " on bonding device %s", 932 spawn->phys_port, 933 mlx5_os_get_dev_device_name 934 (spawn->phys_dev)); 935 err = ENOTSUP; 936 goto error; 937 } 938 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 939 DRV_LOG(ERR, "invalid vport tag for port %d" 940 " on bonding device %s", 941 spawn->phys_port, 942 mlx5_os_get_dev_device_name 943 (spawn->phys_dev)); 944 err = ENOTSUP; 945 goto error; 946 } 947 } 948 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 949 priv->vport_id = devx_port.vport_num; 950 } else if (spawn->pf_bond >= 0) { 951 DRV_LOG(ERR, "can't deduce vport index for port %d" 952 " on bonding device %s", 953 spawn->phys_port, 954 mlx5_os_get_dev_device_name(spawn->phys_dev)); 955 err = ENOTSUP; 956 goto error; 957 } else { 958 /* Suppose vport index in compatible way. */ 959 priv->vport_id = switch_info->representor ? 960 switch_info->port_name + 1 : -1; 961 } 962 #else 963 /* 964 * Kernel/rdma_core support single E-Switch per PF configurations 965 * only and vport_id field contains the vport index for 966 * associated VF, which is deduced from representor port name. 967 * For example, let's have the IB device port 10, it has 968 * attached network device eth0, which has port name attribute 969 * pf0vf2, we can deduce the VF number as 2, and set vport index 970 * as 3 (2+1). This assigning schema should be changed if the 971 * multiple E-Switch instances per PF configurations or/and PCI 972 * subfunctions are added. 973 */ 974 priv->vport_id = switch_info->representor ? 975 switch_info->port_name + 1 : -1; 976 #endif 977 /* representor_id field keeps the unmodified VF index. */ 978 priv->representor_id = switch_info->representor ? 979 switch_info->port_name : -1; 980 /* 981 * Look for sibling devices in order to reuse their switch domain 982 * if any, otherwise allocate one. 983 */ 984 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 985 const struct mlx5_priv *opriv = 986 rte_eth_devices[port_id].data->dev_private; 987 988 if (!opriv || 989 opriv->sh != priv->sh || 990 opriv->domain_id == 991 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 992 continue; 993 priv->domain_id = opriv->domain_id; 994 break; 995 } 996 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 997 err = rte_eth_switch_domain_alloc(&priv->domain_id); 998 if (err) { 999 err = rte_errno; 1000 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1001 strerror(rte_errno)); 1002 goto error; 1003 } 1004 own_domain_id = 1; 1005 } 1006 /* Override some values set by hardware configuration. */ 1007 mlx5_args(config, dpdk_dev->devargs); 1008 err = mlx5_dev_check_sibling_config(priv, config); 1009 if (err) 1010 goto error; 1011 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1012 IBV_DEVICE_RAW_IP_CSUM); 1013 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1014 (config->hw_csum ? "" : "not ")); 1015 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1016 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1017 DRV_LOG(DEBUG, "counters are not supported"); 1018 #endif 1019 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1020 if (config->dv_flow_en) { 1021 DRV_LOG(WARNING, "DV flow is not supported"); 1022 config->dv_flow_en = 0; 1023 } 1024 #endif 1025 config->ind_table_max_size = 1026 sh->device_attr.max_rwq_indirection_table_size; 1027 /* 1028 * Remove this check once DPDK supports larger/variable 1029 * indirection tables. 1030 */ 1031 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1032 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1033 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1034 config->ind_table_max_size); 1035 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1036 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1037 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1038 (config->hw_vlan_strip ? "" : "not ")); 1039 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1040 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1041 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1042 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1043 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1044 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1045 IBV_DEVICE_PCI_WRITE_END_PADDING); 1046 #endif 1047 if (config->hw_padding && !hw_padding) { 1048 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1049 config->hw_padding = 0; 1050 } else if (config->hw_padding) { 1051 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1052 } 1053 config->tso = (sh->device_attr.max_tso > 0 && 1054 (sh->device_attr.tso_supported_qpts & 1055 (1 << IBV_QPT_RAW_PACKET))); 1056 if (config->tso) 1057 config->tso_max_payload_sz = sh->device_attr.max_tso; 1058 /* 1059 * MPW is disabled by default, while the Enhanced MPW is enabled 1060 * by default. 1061 */ 1062 if (config->mps == MLX5_ARG_UNSET) 1063 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1064 MLX5_MPW_DISABLED; 1065 else 1066 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1067 DRV_LOG(INFO, "%sMPS is %s", 1068 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1069 config->mps == MLX5_MPW ? "legacy " : "", 1070 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1071 if (config->cqe_comp && !cqe_comp) { 1072 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1073 config->cqe_comp = 0; 1074 } 1075 if (config->cqe_pad && !cqe_pad) { 1076 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1077 config->cqe_pad = 0; 1078 } else if (config->cqe_pad) { 1079 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1080 } 1081 if (config->devx) { 1082 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1083 if (err) { 1084 err = -err; 1085 goto error; 1086 } 1087 /* Check relax ordering support. */ 1088 if (config->hca_attr.relaxed_ordering_write && 1089 config->hca_attr.relaxed_ordering_read && 1090 !haswell_broadwell_cpu) 1091 sh->cmng.relaxed_ordering = 1; 1092 /* Check for LRO support. */ 1093 if (config->dest_tir && config->hca_attr.lro_cap && 1094 config->dv_flow_en) { 1095 /* TBD check tunnel lro caps. */ 1096 config->lro.supported = config->hca_attr.lro_cap; 1097 DRV_LOG(DEBUG, "Device supports LRO"); 1098 /* 1099 * If LRO timeout is not configured by application, 1100 * use the minimal supported value. 1101 */ 1102 if (!config->lro.timeout) 1103 config->lro.timeout = 1104 config->hca_attr.lro_timer_supported_periods[0]; 1105 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1106 config->lro.timeout); 1107 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1108 "required for coalescing is %d bytes", 1109 config->hca_attr.lro_min_mss_size); 1110 } 1111 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1112 if (config->hca_attr.qos.sup && 1113 config->hca_attr.qos.srtcm_sup && 1114 config->dv_flow_en) { 1115 uint8_t reg_c_mask = 1116 config->hca_attr.qos.flow_meter_reg_c_ids; 1117 /* 1118 * Meter needs two REG_C's for color match and pre-sfx 1119 * flow match. Here get the REG_C for color match. 1120 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1121 */ 1122 reg_c_mask &= 0xfc; 1123 if (__builtin_popcount(reg_c_mask) < 1) { 1124 priv->mtr_en = 0; 1125 DRV_LOG(WARNING, "No available register for" 1126 " meter."); 1127 } else { 1128 priv->mtr_color_reg = ffs(reg_c_mask) - 1 + 1129 REG_C_0; 1130 priv->mtr_en = 1; 1131 priv->mtr_reg_share = 1132 config->hca_attr.qos.flow_meter_reg_share; 1133 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1134 priv->mtr_color_reg); 1135 } 1136 } 1137 #endif 1138 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1139 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1140 config->dv_flow_en) { 1141 priv->sampler_en = 1; 1142 DRV_LOG(DEBUG, "The Sampler enabled!\n"); 1143 } else { 1144 priv->sampler_en = 0; 1145 if (!config->hca_attr.log_max_ft_sampler_num) 1146 DRV_LOG(WARNING, "No available register for" 1147 " Sampler."); 1148 else 1149 DRV_LOG(DEBUG, "DV flow is not supported!\n"); 1150 } 1151 #endif 1152 } 1153 if (config->tx_pp) { 1154 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1155 config->hca_attr.dev_freq_khz); 1156 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1157 config->hca_attr.qos.packet_pacing ? "" : "not "); 1158 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1159 config->hca_attr.cross_channel ? "" : "not "); 1160 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1161 config->hca_attr.wqe_index_ignore ? "" : "not "); 1162 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1163 config->hca_attr.non_wire_sq ? "" : "not "); 1164 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1165 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1166 config->hca_attr.log_max_static_sq_wq); 1167 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1168 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1169 if (!config->devx) { 1170 DRV_LOG(ERR, "DevX is required for packet pacing"); 1171 err = ENODEV; 1172 goto error; 1173 } 1174 if (!config->hca_attr.qos.packet_pacing) { 1175 DRV_LOG(ERR, "Packet pacing is not supported"); 1176 err = ENODEV; 1177 goto error; 1178 } 1179 if (!config->hca_attr.cross_channel) { 1180 DRV_LOG(ERR, "Cross channel operations are" 1181 " required for packet pacing"); 1182 err = ENODEV; 1183 goto error; 1184 } 1185 if (!config->hca_attr.wqe_index_ignore) { 1186 DRV_LOG(ERR, "WQE index ignore feature is" 1187 " required for packet pacing"); 1188 err = ENODEV; 1189 goto error; 1190 } 1191 if (!config->hca_attr.non_wire_sq) { 1192 DRV_LOG(ERR, "Non-wire SQ feature is" 1193 " required for packet pacing"); 1194 err = ENODEV; 1195 goto error; 1196 } 1197 if (!config->hca_attr.log_max_static_sq_wq) { 1198 DRV_LOG(ERR, "Static WQE SQ feature is" 1199 " required for packet pacing"); 1200 err = ENODEV; 1201 goto error; 1202 } 1203 if (!config->hca_attr.qos.wqe_rate_pp) { 1204 DRV_LOG(ERR, "WQE rate mode is required" 1205 " for packet pacing"); 1206 err = ENODEV; 1207 goto error; 1208 } 1209 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1210 DRV_LOG(ERR, "DevX does not provide UAR offset," 1211 " can't create queues for packet pacing"); 1212 err = ENODEV; 1213 goto error; 1214 #endif 1215 } 1216 if (config->devx) { 1217 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1218 1219 err = config->hca_attr.access_register_user ? 1220 mlx5_devx_cmd_register_read 1221 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1222 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1223 if (!err) { 1224 uint32_t ts_mode; 1225 1226 /* MTUTC register is read successfully. */ 1227 ts_mode = MLX5_GET(register_mtutc, reg, 1228 time_stamp_mode); 1229 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1230 config->rt_timestamp = 1; 1231 } else { 1232 /* Kernel does not support register reading. */ 1233 if (config->hca_attr.dev_freq_khz == 1234 (NS_PER_S / MS_PER_S)) 1235 config->rt_timestamp = 1; 1236 } 1237 } 1238 /* 1239 * If HW has bug working with tunnel packet decapsulation and 1240 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1241 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1242 */ 1243 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1244 config->hw_fcs_strip = 0; 1245 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1246 (config->hw_fcs_strip ? "" : "not ")); 1247 if (config->mprq.enabled && mprq) { 1248 if (config->mprq.stride_num_n && 1249 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1250 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1251 config->mprq.stride_num_n = 1252 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1253 mprq_min_stride_num_n), 1254 mprq_max_stride_num_n); 1255 DRV_LOG(WARNING, 1256 "the number of strides" 1257 " for Multi-Packet RQ is out of range," 1258 " setting default value (%u)", 1259 1 << config->mprq.stride_num_n); 1260 } 1261 if (config->mprq.stride_size_n && 1262 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1263 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1264 config->mprq.stride_size_n = 1265 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1266 mprq_min_stride_size_n), 1267 mprq_max_stride_size_n); 1268 DRV_LOG(WARNING, 1269 "the size of a stride" 1270 " for Multi-Packet RQ is out of range," 1271 " setting default value (%u)", 1272 1 << config->mprq.stride_size_n); 1273 } 1274 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1275 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1276 } else if (config->mprq.enabled && !mprq) { 1277 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1278 config->mprq.enabled = 0; 1279 } 1280 if (config->max_dump_files_num == 0) 1281 config->max_dump_files_num = 128; 1282 eth_dev = rte_eth_dev_allocate(name); 1283 if (eth_dev == NULL) { 1284 DRV_LOG(ERR, "can not allocate rte ethdev"); 1285 err = ENOMEM; 1286 goto error; 1287 } 1288 if (priv->representor) { 1289 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1290 eth_dev->data->representor_id = priv->representor_id; 1291 } 1292 /* 1293 * Store associated network device interface index. This index 1294 * is permanent throughout the lifetime of device. So, we may store 1295 * the ifindex here and use the cached value further. 1296 */ 1297 MLX5_ASSERT(spawn->ifindex); 1298 priv->if_index = spawn->ifindex; 1299 if (priv->pf_bond >= 0 && priv->master) { 1300 /* Get bond interface info */ 1301 err = mlx5_sysfs_bond_info(priv->if_index, 1302 &priv->bond_ifindex, 1303 priv->bond_name); 1304 if (err) 1305 DRV_LOG(ERR, "unable to get bond info: %s", 1306 strerror(rte_errno)); 1307 else 1308 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1309 priv->if_index, priv->bond_ifindex, 1310 priv->bond_name); 1311 } 1312 eth_dev->data->dev_private = priv; 1313 priv->dev_data = eth_dev->data; 1314 eth_dev->data->mac_addrs = priv->mac; 1315 eth_dev->device = dpdk_dev; 1316 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1317 /* Configure the first MAC address by default. */ 1318 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1319 DRV_LOG(ERR, 1320 "port %u cannot get MAC address, is mlx5_en" 1321 " loaded? (errno: %s)", 1322 eth_dev->data->port_id, strerror(rte_errno)); 1323 err = ENODEV; 1324 goto error; 1325 } 1326 DRV_LOG(INFO, 1327 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1328 eth_dev->data->port_id, 1329 mac.addr_bytes[0], mac.addr_bytes[1], 1330 mac.addr_bytes[2], mac.addr_bytes[3], 1331 mac.addr_bytes[4], mac.addr_bytes[5]); 1332 #ifdef RTE_LIBRTE_MLX5_DEBUG 1333 { 1334 char ifname[IF_NAMESIZE]; 1335 1336 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1337 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1338 eth_dev->data->port_id, ifname); 1339 else 1340 DRV_LOG(DEBUG, "port %u ifname is unknown", 1341 eth_dev->data->port_id); 1342 } 1343 #endif 1344 /* Get actual MTU if possible. */ 1345 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1346 if (err) { 1347 err = rte_errno; 1348 goto error; 1349 } 1350 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1351 priv->mtu); 1352 /* Initialize burst functions to prevent crashes before link-up. */ 1353 eth_dev->rx_pkt_burst = removed_rx_burst; 1354 eth_dev->tx_pkt_burst = removed_tx_burst; 1355 eth_dev->dev_ops = &mlx5_os_dev_ops; 1356 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1357 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1358 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1359 /* Register MAC address. */ 1360 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1361 if (config->vf && config->vf_nl_en) 1362 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1363 mlx5_ifindex(eth_dev), 1364 eth_dev->data->mac_addrs, 1365 MLX5_MAX_MAC_ADDRESSES); 1366 priv->flows = 0; 1367 priv->ctrl_flows = 0; 1368 rte_spinlock_init(&priv->flow_list_lock); 1369 TAILQ_INIT(&priv->flow_meters); 1370 TAILQ_INIT(&priv->flow_meter_profiles); 1371 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1372 mlx5_glue->dv_set_context_attr(sh->ctx, 1373 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1374 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1375 .alloc = &mlx5_alloc_verbs_buf, 1376 .free = &mlx5_free_verbs_buf, 1377 .data = priv, 1378 })); 1379 /* Bring Ethernet device up. */ 1380 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1381 eth_dev->data->port_id); 1382 mlx5_set_link_up(eth_dev); 1383 /* 1384 * Even though the interrupt handler is not installed yet, 1385 * interrupts will still trigger on the async_fd from 1386 * Verbs context returned by ibv_open_device(). 1387 */ 1388 mlx5_link_update(eth_dev, 0); 1389 #ifdef HAVE_MLX5DV_DR_ESWITCH 1390 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1391 (switch_info->representor || switch_info->master))) 1392 config->dv_esw_en = 0; 1393 #else 1394 config->dv_esw_en = 0; 1395 #endif 1396 /* Detect minimal data bytes to inline. */ 1397 mlx5_set_min_inline(spawn, config); 1398 /* Store device configuration on private structure. */ 1399 priv->config = *config; 1400 /* Create context for virtual machine VLAN workaround. */ 1401 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1402 if (config->dv_flow_en) { 1403 err = mlx5_alloc_shared_dr(priv); 1404 if (err) 1405 goto error; 1406 } 1407 if (config->devx && config->dv_flow_en && config->dest_tir) { 1408 priv->obj_ops = devx_obj_ops; 1409 priv->obj_ops.drop_action_create = 1410 ibv_obj_ops.drop_action_create; 1411 priv->obj_ops.drop_action_destroy = 1412 ibv_obj_ops.drop_action_destroy; 1413 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1414 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1415 #else 1416 if (config->dv_esw_en) 1417 priv->obj_ops.txq_obj_modify = 1418 ibv_obj_ops.txq_obj_modify; 1419 #endif 1420 /* Use specific wrappers for Tx object. */ 1421 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1422 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1423 1424 } else { 1425 priv->obj_ops = ibv_obj_ops; 1426 } 1427 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1428 if (!priv->drop_queue.hrxq) 1429 goto error; 1430 /* Supported Verbs flow priority number detection. */ 1431 err = mlx5_flow_discover_priorities(eth_dev); 1432 if (err < 0) { 1433 err = -err; 1434 goto error; 1435 } 1436 priv->config.flow_prio = err; 1437 if (!priv->config.dv_esw_en && 1438 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1439 DRV_LOG(WARNING, "metadata mode %u is not supported " 1440 "(no E-Switch)", priv->config.dv_xmeta_en); 1441 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1442 } 1443 mlx5_set_metadata_mask(eth_dev); 1444 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1445 !priv->sh->dv_regc0_mask) { 1446 DRV_LOG(ERR, "metadata mode %u is not supported " 1447 "(no metadata reg_c[0] is available)", 1448 priv->config.dv_xmeta_en); 1449 err = ENOTSUP; 1450 goto error; 1451 } 1452 /* Query availability of metadata reg_c's. */ 1453 err = mlx5_flow_discover_mreg_c(eth_dev); 1454 if (err < 0) { 1455 err = -err; 1456 goto error; 1457 } 1458 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1459 DRV_LOG(DEBUG, 1460 "port %u extensive metadata register is not supported", 1461 eth_dev->data->port_id); 1462 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1463 DRV_LOG(ERR, "metadata mode %u is not supported " 1464 "(no metadata registers available)", 1465 priv->config.dv_xmeta_en); 1466 err = ENOTSUP; 1467 goto error; 1468 } 1469 } 1470 if (priv->config.dv_flow_en && 1471 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1472 mlx5_flow_ext_mreg_supported(eth_dev) && 1473 priv->sh->dv_regc0_mask) { 1474 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1475 MLX5_FLOW_MREG_HTABLE_SZ); 1476 if (!priv->mreg_cp_tbl) { 1477 err = ENOMEM; 1478 goto error; 1479 } 1480 } 1481 mlx5_flow_counter_mode_config(eth_dev); 1482 return eth_dev; 1483 error: 1484 if (priv) { 1485 if (priv->mreg_cp_tbl) 1486 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL); 1487 if (priv->sh) 1488 mlx5_os_free_shared_dr(priv); 1489 if (priv->nl_socket_route >= 0) 1490 close(priv->nl_socket_route); 1491 if (priv->nl_socket_rdma >= 0) 1492 close(priv->nl_socket_rdma); 1493 if (priv->vmwa_context) 1494 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1495 if (eth_dev && priv->drop_queue.hrxq) 1496 mlx5_drop_action_destroy(eth_dev); 1497 if (own_domain_id) 1498 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1499 mlx5_free(priv); 1500 if (eth_dev != NULL) 1501 eth_dev->data->dev_private = NULL; 1502 } 1503 if (eth_dev != NULL) { 1504 /* mac_addrs must not be freed alone because part of 1505 * dev_private 1506 **/ 1507 eth_dev->data->mac_addrs = NULL; 1508 rte_eth_dev_release_port(eth_dev); 1509 } 1510 if (sh) 1511 mlx5_free_shared_dev_ctx(sh); 1512 MLX5_ASSERT(err > 0); 1513 rte_errno = err; 1514 return NULL; 1515 } 1516 1517 /** 1518 * Comparison callback to sort device data. 1519 * 1520 * This is meant to be used with qsort(). 1521 * 1522 * @param a[in] 1523 * Pointer to pointer to first data object. 1524 * @param b[in] 1525 * Pointer to pointer to second data object. 1526 * 1527 * @return 1528 * 0 if both objects are equal, less than 0 if the first argument is less 1529 * than the second, greater than 0 otherwise. 1530 */ 1531 static int 1532 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1533 { 1534 const struct mlx5_switch_info *si_a = 1535 &((const struct mlx5_dev_spawn_data *)a)->info; 1536 const struct mlx5_switch_info *si_b = 1537 &((const struct mlx5_dev_spawn_data *)b)->info; 1538 int ret; 1539 1540 /* Master device first. */ 1541 ret = si_b->master - si_a->master; 1542 if (ret) 1543 return ret; 1544 /* Then representor devices. */ 1545 ret = si_b->representor - si_a->representor; 1546 if (ret) 1547 return ret; 1548 /* Unidentified devices come last in no specific order. */ 1549 if (!si_a->representor) 1550 return 0; 1551 /* Order representors by name. */ 1552 return si_a->port_name - si_b->port_name; 1553 } 1554 1555 /** 1556 * Match PCI information for possible slaves of bonding device. 1557 * 1558 * @param[in] ibv_dev 1559 * Pointer to Infiniband device structure. 1560 * @param[in] pci_dev 1561 * Pointer to PCI device structure to match PCI address. 1562 * @param[in] nl_rdma 1563 * Netlink RDMA group socket handle. 1564 * 1565 * @return 1566 * negative value if no bonding device found, otherwise 1567 * positive index of slave PF in bonding. 1568 */ 1569 static int 1570 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1571 const struct rte_pci_device *pci_dev, 1572 int nl_rdma) 1573 { 1574 char ifname[IF_NAMESIZE + 1]; 1575 unsigned int ifindex; 1576 unsigned int np, i; 1577 FILE *file = NULL; 1578 int pf = -1; 1579 1580 /* 1581 * Try to get master device name. If something goes 1582 * wrong suppose the lack of kernel support and no 1583 * bonding devices. 1584 */ 1585 if (nl_rdma < 0) 1586 return -1; 1587 if (!strstr(ibv_dev->name, "bond")) 1588 return -1; 1589 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1590 if (!np) 1591 return -1; 1592 /* 1593 * The Master device might not be on the predefined 1594 * port (not on port index 1, it is not garanted), 1595 * we have to scan all Infiniband device port and 1596 * find master. 1597 */ 1598 for (i = 1; i <= np; ++i) { 1599 /* Check whether Infiniband port is populated. */ 1600 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1601 if (!ifindex) 1602 continue; 1603 if (!if_indextoname(ifindex, ifname)) 1604 continue; 1605 /* Try to read bonding slave names from sysfs. */ 1606 MKSTR(slaves, 1607 "/sys/class/net/%s/master/bonding/slaves", ifname); 1608 file = fopen(slaves, "r"); 1609 if (file) 1610 break; 1611 } 1612 if (!file) 1613 return -1; 1614 /* Use safe format to check maximal buffer length. */ 1615 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1616 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1617 char tmp_str[IF_NAMESIZE + 32]; 1618 struct rte_pci_addr pci_addr; 1619 struct mlx5_switch_info info; 1620 1621 /* Process slave interface names in the loop. */ 1622 snprintf(tmp_str, sizeof(tmp_str), 1623 "/sys/class/net/%s", ifname); 1624 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1625 DRV_LOG(WARNING, "can not get PCI address" 1626 " for netdev \"%s\"", ifname); 1627 continue; 1628 } 1629 if (pci_dev->addr.domain != pci_addr.domain || 1630 pci_dev->addr.bus != pci_addr.bus || 1631 pci_dev->addr.devid != pci_addr.devid || 1632 pci_dev->addr.function != pci_addr.function) 1633 continue; 1634 /* Slave interface PCI address match found. */ 1635 fclose(file); 1636 snprintf(tmp_str, sizeof(tmp_str), 1637 "/sys/class/net/%s/phys_port_name", ifname); 1638 file = fopen(tmp_str, "rb"); 1639 if (!file) 1640 break; 1641 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1642 if (fscanf(file, "%32s", tmp_str) == 1) 1643 mlx5_translate_port_name(tmp_str, &info); 1644 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 1645 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1646 pf = info.port_name; 1647 break; 1648 } 1649 if (file) 1650 fclose(file); 1651 return pf; 1652 } 1653 1654 /** 1655 * DPDK callback to register a PCI device. 1656 * 1657 * This function spawns Ethernet devices out of a given PCI device. 1658 * 1659 * @param[in] pci_drv 1660 * PCI driver structure (mlx5_driver). 1661 * @param[in] pci_dev 1662 * PCI device information. 1663 * 1664 * @return 1665 * 0 on success, a negative errno value otherwise and rte_errno is set. 1666 */ 1667 int 1668 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1669 struct rte_pci_device *pci_dev) 1670 { 1671 struct ibv_device **ibv_list; 1672 /* 1673 * Number of found IB Devices matching with requested PCI BDF. 1674 * nd != 1 means there are multiple IB devices over the same 1675 * PCI device and we have representors and master. 1676 */ 1677 unsigned int nd = 0; 1678 /* 1679 * Number of found IB device Ports. nd = 1 and np = 1..n means 1680 * we have the single multiport IB device, and there may be 1681 * representors attached to some of found ports. 1682 */ 1683 unsigned int np = 0; 1684 /* 1685 * Number of DPDK ethernet devices to Spawn - either over 1686 * multiple IB devices or multiple ports of single IB device. 1687 * Actually this is the number of iterations to spawn. 1688 */ 1689 unsigned int ns = 0; 1690 /* 1691 * Bonding device 1692 * < 0 - no bonding device (single one) 1693 * >= 0 - bonding device (value is slave PF index) 1694 */ 1695 int bd = -1; 1696 struct mlx5_dev_spawn_data *list = NULL; 1697 struct mlx5_dev_config dev_config; 1698 unsigned int dev_config_vf; 1699 int ret; 1700 1701 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1702 mlx5_pmd_socket_init(); 1703 ret = mlx5_init_once(); 1704 if (ret) { 1705 DRV_LOG(ERR, "unable to init PMD global data: %s", 1706 strerror(rte_errno)); 1707 return -rte_errno; 1708 } 1709 errno = 0; 1710 ibv_list = mlx5_glue->get_device_list(&ret); 1711 if (!ibv_list) { 1712 rte_errno = errno ? errno : ENOSYS; 1713 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1714 return -rte_errno; 1715 } 1716 /* 1717 * First scan the list of all Infiniband devices to find 1718 * matching ones, gathering into the list. 1719 */ 1720 struct ibv_device *ibv_match[ret + 1]; 1721 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1722 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1723 unsigned int i; 1724 1725 while (ret-- > 0) { 1726 struct rte_pci_addr pci_addr; 1727 1728 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1729 bd = mlx5_device_bond_pci_match 1730 (ibv_list[ret], pci_dev, nl_rdma); 1731 if (bd >= 0) { 1732 /* 1733 * Bonding device detected. Only one match is allowed, 1734 * the bonding is supported over multi-port IB device, 1735 * there should be no matches on representor PCI 1736 * functions or non VF LAG bonding devices with 1737 * specified address. 1738 */ 1739 if (nd) { 1740 DRV_LOG(ERR, 1741 "multiple PCI match on bonding device" 1742 "\"%s\" found", ibv_list[ret]->name); 1743 rte_errno = ENOENT; 1744 ret = -rte_errno; 1745 goto exit; 1746 } 1747 DRV_LOG(INFO, "PCI information matches for" 1748 " slave %d bonding device \"%s\"", 1749 bd, ibv_list[ret]->name); 1750 ibv_match[nd++] = ibv_list[ret]; 1751 break; 1752 } 1753 if (mlx5_dev_to_pci_addr 1754 (ibv_list[ret]->ibdev_path, &pci_addr)) 1755 continue; 1756 if (pci_dev->addr.domain != pci_addr.domain || 1757 pci_dev->addr.bus != pci_addr.bus || 1758 pci_dev->addr.devid != pci_addr.devid || 1759 pci_dev->addr.function != pci_addr.function) 1760 continue; 1761 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1762 ibv_list[ret]->name); 1763 ibv_match[nd++] = ibv_list[ret]; 1764 } 1765 ibv_match[nd] = NULL; 1766 if (!nd) { 1767 /* No device matches, just complain and bail out. */ 1768 DRV_LOG(WARNING, 1769 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1770 " are kernel drivers loaded?", 1771 pci_dev->addr.domain, pci_dev->addr.bus, 1772 pci_dev->addr.devid, pci_dev->addr.function); 1773 rte_errno = ENOENT; 1774 ret = -rte_errno; 1775 goto exit; 1776 } 1777 if (nd == 1) { 1778 /* 1779 * Found single matching device may have multiple ports. 1780 * Each port may be representor, we have to check the port 1781 * number and check the representors existence. 1782 */ 1783 if (nl_rdma >= 0) 1784 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1785 if (!np) 1786 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1787 " ports number", ibv_match[0]->name); 1788 if (bd >= 0 && !np) { 1789 DRV_LOG(ERR, "can not get ports" 1790 " for bonding device"); 1791 rte_errno = ENOENT; 1792 ret = -rte_errno; 1793 goto exit; 1794 } 1795 } 1796 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 1797 if (bd >= 0) { 1798 /* 1799 * This may happen if there is VF LAG kernel support and 1800 * application is compiled with older rdma_core library. 1801 */ 1802 DRV_LOG(ERR, 1803 "No kernel/verbs support for VF LAG bonding found."); 1804 rte_errno = ENOTSUP; 1805 ret = -rte_errno; 1806 goto exit; 1807 } 1808 #endif 1809 /* 1810 * Now we can determine the maximal 1811 * amount of devices to be spawned. 1812 */ 1813 list = mlx5_malloc(MLX5_MEM_ZERO, 1814 sizeof(struct mlx5_dev_spawn_data) * 1815 (np ? np : nd), 1816 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1817 if (!list) { 1818 DRV_LOG(ERR, "spawn data array allocation failure"); 1819 rte_errno = ENOMEM; 1820 ret = -rte_errno; 1821 goto exit; 1822 } 1823 if (bd >= 0 || np > 1) { 1824 /* 1825 * Single IB device with multiple ports found, 1826 * it may be E-Switch master device and representors. 1827 * We have to perform identification through the ports. 1828 */ 1829 MLX5_ASSERT(nl_rdma >= 0); 1830 MLX5_ASSERT(ns == 0); 1831 MLX5_ASSERT(nd == 1); 1832 MLX5_ASSERT(np); 1833 for (i = 1; i <= np; ++i) { 1834 list[ns].max_port = np; 1835 list[ns].phys_port = i; 1836 list[ns].phys_dev = ibv_match[0]; 1837 list[ns].eth_dev = NULL; 1838 list[ns].pci_dev = pci_dev; 1839 list[ns].pf_bond = bd; 1840 list[ns].ifindex = mlx5_nl_ifindex 1841 (nl_rdma, 1842 mlx5_os_get_dev_device_name 1843 (list[ns].phys_dev), i); 1844 if (!list[ns].ifindex) { 1845 /* 1846 * No network interface index found for the 1847 * specified port, it means there is no 1848 * representor on this port. It's OK, 1849 * there can be disabled ports, for example 1850 * if sriov_numvfs < sriov_totalvfs. 1851 */ 1852 continue; 1853 } 1854 ret = -1; 1855 if (nl_route >= 0) 1856 ret = mlx5_nl_switch_info 1857 (nl_route, 1858 list[ns].ifindex, 1859 &list[ns].info); 1860 if (ret || (!list[ns].info.representor && 1861 !list[ns].info.master)) { 1862 /* 1863 * We failed to recognize representors with 1864 * Netlink, let's try to perform the task 1865 * with sysfs. 1866 */ 1867 ret = mlx5_sysfs_switch_info 1868 (list[ns].ifindex, 1869 &list[ns].info); 1870 } 1871 if (!ret && bd >= 0) { 1872 switch (list[ns].info.name_type) { 1873 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 1874 if (list[ns].info.port_name == bd) 1875 ns++; 1876 break; 1877 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 1878 /* Fallthrough */ 1879 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 1880 if (list[ns].info.pf_num == bd) 1881 ns++; 1882 break; 1883 default: 1884 break; 1885 } 1886 continue; 1887 } 1888 if (!ret && (list[ns].info.representor ^ 1889 list[ns].info.master)) 1890 ns++; 1891 } 1892 if (!ns) { 1893 DRV_LOG(ERR, 1894 "unable to recognize master/representors" 1895 " on the IB device with multiple ports"); 1896 rte_errno = ENOENT; 1897 ret = -rte_errno; 1898 goto exit; 1899 } 1900 } else { 1901 /* 1902 * The existence of several matching entries (nd > 1) means 1903 * port representors have been instantiated. No existing Verbs 1904 * call nor sysfs entries can tell them apart, this can only 1905 * be done through Netlink calls assuming kernel drivers are 1906 * recent enough to support them. 1907 * 1908 * In the event of identification failure through Netlink, 1909 * try again through sysfs, then: 1910 * 1911 * 1. A single IB device matches (nd == 1) with single 1912 * port (np=0/1) and is not a representor, assume 1913 * no switch support. 1914 * 1915 * 2. Otherwise no safe assumptions can be made; 1916 * complain louder and bail out. 1917 */ 1918 for (i = 0; i != nd; ++i) { 1919 memset(&list[ns].info, 0, sizeof(list[ns].info)); 1920 list[ns].max_port = 1; 1921 list[ns].phys_port = 1; 1922 list[ns].phys_dev = ibv_match[i]; 1923 list[ns].eth_dev = NULL; 1924 list[ns].pci_dev = pci_dev; 1925 list[ns].pf_bond = -1; 1926 list[ns].ifindex = 0; 1927 if (nl_rdma >= 0) 1928 list[ns].ifindex = mlx5_nl_ifindex 1929 (nl_rdma, 1930 mlx5_os_get_dev_device_name 1931 (list[ns].phys_dev), 1); 1932 if (!list[ns].ifindex) { 1933 char ifname[IF_NAMESIZE]; 1934 1935 /* 1936 * Netlink failed, it may happen with old 1937 * ib_core kernel driver (before 4.16). 1938 * We can assume there is old driver because 1939 * here we are processing single ports IB 1940 * devices. Let's try sysfs to retrieve 1941 * the ifindex. The method works for 1942 * master device only. 1943 */ 1944 if (nd > 1) { 1945 /* 1946 * Multiple devices found, assume 1947 * representors, can not distinguish 1948 * master/representor and retrieve 1949 * ifindex via sysfs. 1950 */ 1951 continue; 1952 } 1953 ret = mlx5_get_ifname_sysfs 1954 (ibv_match[i]->ibdev_path, ifname); 1955 if (!ret) 1956 list[ns].ifindex = 1957 if_nametoindex(ifname); 1958 if (!list[ns].ifindex) { 1959 /* 1960 * No network interface index found 1961 * for the specified device, it means 1962 * there it is neither representor 1963 * nor master. 1964 */ 1965 continue; 1966 } 1967 } 1968 ret = -1; 1969 if (nl_route >= 0) 1970 ret = mlx5_nl_switch_info 1971 (nl_route, 1972 list[ns].ifindex, 1973 &list[ns].info); 1974 if (ret || (!list[ns].info.representor && 1975 !list[ns].info.master)) { 1976 /* 1977 * We failed to recognize representors with 1978 * Netlink, let's try to perform the task 1979 * with sysfs. 1980 */ 1981 ret = mlx5_sysfs_switch_info 1982 (list[ns].ifindex, 1983 &list[ns].info); 1984 } 1985 if (!ret && (list[ns].info.representor ^ 1986 list[ns].info.master)) { 1987 ns++; 1988 } else if ((nd == 1) && 1989 !list[ns].info.representor && 1990 !list[ns].info.master) { 1991 /* 1992 * Single IB device with 1993 * one physical port and 1994 * attached network device. 1995 * May be SRIOV is not enabled 1996 * or there is no representors. 1997 */ 1998 DRV_LOG(INFO, "no E-Switch support detected"); 1999 ns++; 2000 break; 2001 } 2002 } 2003 if (!ns) { 2004 DRV_LOG(ERR, 2005 "unable to recognize master/representors" 2006 " on the multiple IB devices"); 2007 rte_errno = ENOENT; 2008 ret = -rte_errno; 2009 goto exit; 2010 } 2011 } 2012 MLX5_ASSERT(ns); 2013 /* 2014 * Sort list to probe devices in natural order for users convenience 2015 * (i.e. master first, then representors from lowest to highest ID). 2016 */ 2017 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2018 /* Device specific configuration. */ 2019 switch (pci_dev->id.device_id) { 2020 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2021 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2022 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2023 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2024 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2025 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2026 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF: 2027 dev_config_vf = 1; 2028 break; 2029 default: 2030 dev_config_vf = 0; 2031 break; 2032 } 2033 for (i = 0; i != ns; ++i) { 2034 uint32_t restore; 2035 2036 /* Default configuration. */ 2037 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2038 dev_config.vf = dev_config_vf; 2039 dev_config.mps = MLX5_ARG_UNSET; 2040 dev_config.dbnc = MLX5_ARG_UNSET; 2041 dev_config.rx_vec_en = 1; 2042 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2043 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2044 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2045 dev_config.txqs_inline = MLX5_ARG_UNSET; 2046 dev_config.vf_nl_en = 1; 2047 dev_config.mr_ext_memseg_en = 1; 2048 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2049 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2050 dev_config.dv_esw_en = 1; 2051 dev_config.dv_flow_en = 1; 2052 dev_config.decap_en = 1; 2053 dev_config.log_hp_size = MLX5_ARG_UNSET; 2054 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2055 &list[i], 2056 &dev_config); 2057 if (!list[i].eth_dev) { 2058 if (rte_errno != EBUSY && rte_errno != EEXIST) 2059 break; 2060 /* Device is disabled or already spawned. Ignore it. */ 2061 continue; 2062 } 2063 restore = list[i].eth_dev->data->dev_flags; 2064 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2065 /* Restore non-PCI flags cleared by the above call. */ 2066 list[i].eth_dev->data->dev_flags |= restore; 2067 rte_eth_dev_probing_finish(list[i].eth_dev); 2068 } 2069 if (i != ns) { 2070 DRV_LOG(ERR, 2071 "probe of PCI device " PCI_PRI_FMT " aborted after" 2072 " encountering an error: %s", 2073 pci_dev->addr.domain, pci_dev->addr.bus, 2074 pci_dev->addr.devid, pci_dev->addr.function, 2075 strerror(rte_errno)); 2076 ret = -rte_errno; 2077 /* Roll back. */ 2078 while (i--) { 2079 if (!list[i].eth_dev) 2080 continue; 2081 mlx5_dev_close(list[i].eth_dev); 2082 /* mac_addrs must not be freed because in dev_private */ 2083 list[i].eth_dev->data->mac_addrs = NULL; 2084 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2085 } 2086 /* Restore original error. */ 2087 rte_errno = -ret; 2088 } else { 2089 ret = 0; 2090 } 2091 exit: 2092 /* 2093 * Do the routine cleanup: 2094 * - close opened Netlink sockets 2095 * - free allocated spawn data array 2096 * - free the Infiniband device list 2097 */ 2098 if (nl_rdma >= 0) 2099 close(nl_rdma); 2100 if (nl_route >= 0) 2101 close(nl_route); 2102 if (list) 2103 mlx5_free(list); 2104 MLX5_ASSERT(ibv_list); 2105 mlx5_glue->free_device_list(ibv_list); 2106 return ret; 2107 } 2108 2109 static int 2110 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2111 { 2112 char *env; 2113 int value; 2114 2115 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2116 /* Get environment variable to store. */ 2117 env = getenv(MLX5_SHUT_UP_BF); 2118 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2119 if (config->dbnc == MLX5_ARG_UNSET) 2120 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2121 else 2122 setenv(MLX5_SHUT_UP_BF, 2123 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2124 return value; 2125 } 2126 2127 static void 2128 mlx5_restore_doorbell_mapping_env(int value) 2129 { 2130 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2131 /* Restore the original environment variable state. */ 2132 if (value == MLX5_ARG_UNSET) 2133 unsetenv(MLX5_SHUT_UP_BF); 2134 else 2135 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2136 } 2137 2138 /** 2139 * Extract pdn of PD object using DV API. 2140 * 2141 * @param[in] pd 2142 * Pointer to the verbs PD object. 2143 * @param[out] pdn 2144 * Pointer to the PD object number variable. 2145 * 2146 * @return 2147 * 0 on success, error value otherwise. 2148 */ 2149 int 2150 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2151 { 2152 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2153 struct mlx5dv_obj obj; 2154 struct mlx5dv_pd pd_info; 2155 int ret = 0; 2156 2157 obj.pd.in = pd; 2158 obj.pd.out = &pd_info; 2159 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2160 if (ret) { 2161 DRV_LOG(DEBUG, "Fail to get PD object info"); 2162 return ret; 2163 } 2164 *pdn = pd_info.pdn; 2165 return 0; 2166 #else 2167 (void)pd; 2168 (void)pdn; 2169 return -ENOTSUP; 2170 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2171 } 2172 2173 /** 2174 * Function API to open IB device. 2175 * 2176 * This function calls the Linux glue APIs to open a device. 2177 * 2178 * @param[in] spawn 2179 * Pointer to the IB device attributes (name, port, etc). 2180 * @param[out] config 2181 * Pointer to device configuration structure. 2182 * @param[out] sh 2183 * Pointer to shared context structure. 2184 * 2185 * @return 2186 * 0 on success, a positive error value otherwise. 2187 */ 2188 int 2189 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2190 const struct mlx5_dev_config *config, 2191 struct mlx5_dev_ctx_shared *sh) 2192 { 2193 int dbmap_env; 2194 int err = 0; 2195 2196 sh->numa_node = spawn->pci_dev->device.numa_node; 2197 pthread_mutex_init(&sh->txpp.mutex, NULL); 2198 /* 2199 * Configure environment variable "MLX5_BF_SHUT_UP" 2200 * before the device creation. The rdma_core library 2201 * checks the variable at device creation and 2202 * stores the result internally. 2203 */ 2204 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2205 /* Try to open IB device with DV first, then usual Verbs. */ 2206 errno = 0; 2207 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2208 if (sh->ctx) { 2209 sh->devx = 1; 2210 DRV_LOG(DEBUG, "DevX is supported"); 2211 /* The device is created, no need for environment. */ 2212 mlx5_restore_doorbell_mapping_env(dbmap_env); 2213 } else { 2214 /* The environment variable is still configured. */ 2215 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2216 err = errno ? errno : ENODEV; 2217 /* 2218 * The environment variable is not needed anymore, 2219 * all device creation attempts are completed. 2220 */ 2221 mlx5_restore_doorbell_mapping_env(dbmap_env); 2222 if (!sh->ctx) 2223 return err; 2224 DRV_LOG(DEBUG, "DevX is NOT supported"); 2225 err = 0; 2226 } 2227 return err; 2228 } 2229 2230 /** 2231 * Install shared asynchronous device events handler. 2232 * This function is implemented to support event sharing 2233 * between multiple ports of single IB device. 2234 * 2235 * @param sh 2236 * Pointer to mlx5_dev_ctx_shared object. 2237 */ 2238 void 2239 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2240 { 2241 int ret; 2242 int flags; 2243 2244 sh->intr_handle.fd = -1; 2245 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2246 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2247 F_SETFL, flags | O_NONBLOCK); 2248 if (ret) { 2249 DRV_LOG(INFO, "failed to change file descriptor async event" 2250 " queue"); 2251 } else { 2252 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2253 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2254 if (rte_intr_callback_register(&sh->intr_handle, 2255 mlx5_dev_interrupt_handler, sh)) { 2256 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2257 sh->intr_handle.fd = -1; 2258 } 2259 } 2260 if (sh->devx) { 2261 #ifdef HAVE_IBV_DEVX_ASYNC 2262 sh->intr_handle_devx.fd = -1; 2263 sh->devx_comp = 2264 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2265 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2266 if (!devx_comp) { 2267 DRV_LOG(INFO, "failed to allocate devx_comp."); 2268 return; 2269 } 2270 flags = fcntl(devx_comp->fd, F_GETFL); 2271 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2272 if (ret) { 2273 DRV_LOG(INFO, "failed to change file descriptor" 2274 " devx comp"); 2275 return; 2276 } 2277 sh->intr_handle_devx.fd = devx_comp->fd; 2278 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2279 if (rte_intr_callback_register(&sh->intr_handle_devx, 2280 mlx5_dev_interrupt_handler_devx, sh)) { 2281 DRV_LOG(INFO, "Fail to install the devx shared" 2282 " interrupt."); 2283 sh->intr_handle_devx.fd = -1; 2284 } 2285 #endif /* HAVE_IBV_DEVX_ASYNC */ 2286 } 2287 } 2288 2289 /** 2290 * Uninstall shared asynchronous device events handler. 2291 * This function is implemented to support event sharing 2292 * between multiple ports of single IB device. 2293 * 2294 * @param dev 2295 * Pointer to mlx5_dev_ctx_shared object. 2296 */ 2297 void 2298 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2299 { 2300 if (sh->intr_handle.fd >= 0) 2301 mlx5_intr_callback_unregister(&sh->intr_handle, 2302 mlx5_dev_interrupt_handler, sh); 2303 #ifdef HAVE_IBV_DEVX_ASYNC 2304 if (sh->intr_handle_devx.fd >= 0) 2305 rte_intr_callback_unregister(&sh->intr_handle_devx, 2306 mlx5_dev_interrupt_handler_devx, sh); 2307 if (sh->devx_comp) 2308 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2309 #endif 2310 } 2311 2312 /** 2313 * Read statistics by a named counter. 2314 * 2315 * @param[in] priv 2316 * Pointer to the private device data structure. 2317 * @param[in] ctr_name 2318 * Pointer to the name of the statistic counter to read 2319 * @param[out] stat 2320 * Pointer to read statistic value. 2321 * @return 2322 * 0 on success and stat is valud, 1 if failed to read the value 2323 * rte_errno is set. 2324 * 2325 */ 2326 int 2327 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2328 uint64_t *stat) 2329 { 2330 int fd; 2331 2332 if (priv->sh) { 2333 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2334 priv->sh->ibdev_path, 2335 priv->dev_port, 2336 ctr_name); 2337 fd = open(path, O_RDONLY); 2338 /* 2339 * in switchdev the file location is not per port 2340 * but rather in <ibdev_path>/hw_counters/<file_name>. 2341 */ 2342 if (fd == -1) { 2343 MKSTR(path1, "%s/hw_counters/%s", 2344 priv->sh->ibdev_path, 2345 ctr_name); 2346 fd = open(path1, O_RDONLY); 2347 } 2348 if (fd != -1) { 2349 char buf[21] = {'\0'}; 2350 ssize_t n = read(fd, buf, sizeof(buf)); 2351 2352 close(fd); 2353 if (n != -1) { 2354 *stat = strtoull(buf, NULL, 10); 2355 return 0; 2356 } 2357 } 2358 } 2359 *stat = 0; 2360 return 1; 2361 } 2362 2363 /** 2364 * Set the reg_mr and dereg_mr call backs 2365 * 2366 * @param reg_mr_cb[out] 2367 * Pointer to reg_mr func 2368 * @param dereg_mr_cb[out] 2369 * Pointer to dereg_mr func 2370 * 2371 */ 2372 void 2373 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2374 mlx5_dereg_mr_t *dereg_mr_cb) 2375 { 2376 *reg_mr_cb = mlx5_verbs_ops.reg_mr; 2377 *dereg_mr_cb = mlx5_verbs_ops.dereg_mr; 2378 } 2379 2380 /** 2381 * Remove a MAC address from device 2382 * 2383 * @param dev 2384 * Pointer to Ethernet device structure. 2385 * @param index 2386 * MAC address index. 2387 */ 2388 void 2389 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2390 { 2391 struct mlx5_priv *priv = dev->data->dev_private; 2392 const int vf = priv->config.vf; 2393 2394 if (vf) 2395 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2396 mlx5_ifindex(dev), priv->mac_own, 2397 &dev->data->mac_addrs[index], index); 2398 } 2399 2400 /** 2401 * Adds a MAC address to the device 2402 * 2403 * @param dev 2404 * Pointer to Ethernet device structure. 2405 * @param mac_addr 2406 * MAC address to register. 2407 * @param index 2408 * MAC address index. 2409 * 2410 * @return 2411 * 0 on success, a negative errno value otherwise 2412 */ 2413 int 2414 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2415 uint32_t index) 2416 { 2417 struct mlx5_priv *priv = dev->data->dev_private; 2418 const int vf = priv->config.vf; 2419 int ret = 0; 2420 2421 if (vf) 2422 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2423 mlx5_ifindex(dev), priv->mac_own, 2424 mac, index); 2425 return ret; 2426 } 2427 2428 /** 2429 * Modify a VF MAC address 2430 * 2431 * @param priv 2432 * Pointer to device private data. 2433 * @param mac_addr 2434 * MAC address to modify into. 2435 * @param iface_idx 2436 * Net device interface index 2437 * @param vf_index 2438 * VF index 2439 * 2440 * @return 2441 * 0 on success, a negative errno value otherwise 2442 */ 2443 int 2444 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2445 unsigned int iface_idx, 2446 struct rte_ether_addr *mac_addr, 2447 int vf_index) 2448 { 2449 return mlx5_nl_vf_mac_addr_modify 2450 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2451 } 2452 2453 /** 2454 * Set device promiscuous mode 2455 * 2456 * @param dev 2457 * Pointer to Ethernet device structure. 2458 * @param enable 2459 * 0 - promiscuous is disabled, otherwise - enabled 2460 * 2461 * @return 2462 * 0 on success, a negative error value otherwise 2463 */ 2464 int 2465 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2466 { 2467 struct mlx5_priv *priv = dev->data->dev_private; 2468 2469 return mlx5_nl_promisc(priv->nl_socket_route, 2470 mlx5_ifindex(dev), !!enable); 2471 } 2472 2473 /** 2474 * Set device promiscuous mode 2475 * 2476 * @param dev 2477 * Pointer to Ethernet device structure. 2478 * @param enable 2479 * 0 - all multicase is disabled, otherwise - enabled 2480 * 2481 * @return 2482 * 0 on success, a negative error value otherwise 2483 */ 2484 int 2485 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2486 { 2487 struct mlx5_priv *priv = dev->data->dev_private; 2488 2489 return mlx5_nl_allmulti(priv->nl_socket_route, 2490 mlx5_ifindex(dev), !!enable); 2491 } 2492 2493 /** 2494 * Flush device MAC addresses 2495 * 2496 * @param dev 2497 * Pointer to Ethernet device structure. 2498 * 2499 */ 2500 void 2501 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2502 { 2503 struct mlx5_priv *priv = dev->data->dev_private; 2504 2505 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2506 dev->data->mac_addrs, 2507 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2508 } 2509 2510 const struct eth_dev_ops mlx5_os_dev_ops = { 2511 .dev_configure = mlx5_dev_configure, 2512 .dev_start = mlx5_dev_start, 2513 .dev_stop = mlx5_dev_stop, 2514 .dev_set_link_down = mlx5_set_link_down, 2515 .dev_set_link_up = mlx5_set_link_up, 2516 .dev_close = mlx5_dev_close, 2517 .promiscuous_enable = mlx5_promiscuous_enable, 2518 .promiscuous_disable = mlx5_promiscuous_disable, 2519 .allmulticast_enable = mlx5_allmulticast_enable, 2520 .allmulticast_disable = mlx5_allmulticast_disable, 2521 .link_update = mlx5_link_update, 2522 .stats_get = mlx5_stats_get, 2523 .stats_reset = mlx5_stats_reset, 2524 .xstats_get = mlx5_xstats_get, 2525 .xstats_reset = mlx5_xstats_reset, 2526 .xstats_get_names = mlx5_xstats_get_names, 2527 .fw_version_get = mlx5_fw_version_get, 2528 .dev_infos_get = mlx5_dev_infos_get, 2529 .read_clock = mlx5_txpp_read_clock, 2530 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2531 .vlan_filter_set = mlx5_vlan_filter_set, 2532 .rx_queue_setup = mlx5_rx_queue_setup, 2533 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2534 .tx_queue_setup = mlx5_tx_queue_setup, 2535 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2536 .rx_queue_release = mlx5_rx_queue_release, 2537 .tx_queue_release = mlx5_tx_queue_release, 2538 .rx_queue_start = mlx5_rx_queue_start, 2539 .rx_queue_stop = mlx5_rx_queue_stop, 2540 .tx_queue_start = mlx5_tx_queue_start, 2541 .tx_queue_stop = mlx5_tx_queue_stop, 2542 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2543 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2544 .mac_addr_remove = mlx5_mac_addr_remove, 2545 .mac_addr_add = mlx5_mac_addr_add, 2546 .mac_addr_set = mlx5_mac_addr_set, 2547 .set_mc_addr_list = mlx5_set_mc_addr_list, 2548 .mtu_set = mlx5_dev_set_mtu, 2549 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2550 .vlan_offload_set = mlx5_vlan_offload_set, 2551 .reta_update = mlx5_dev_rss_reta_update, 2552 .reta_query = mlx5_dev_rss_reta_query, 2553 .rss_hash_update = mlx5_rss_hash_update, 2554 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2555 .filter_ctrl = mlx5_dev_filter_ctrl, 2556 .rxq_info_get = mlx5_rxq_info_get, 2557 .txq_info_get = mlx5_txq_info_get, 2558 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2559 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2560 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2561 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2562 .is_removed = mlx5_is_removed, 2563 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2564 .get_module_info = mlx5_get_module_info, 2565 .get_module_eeprom = mlx5_get_module_eeprom, 2566 .hairpin_cap_get = mlx5_hairpin_cap_get, 2567 .mtr_ops_get = mlx5_flow_meter_ops_get, 2568 .hairpin_bind = mlx5_hairpin_bind, 2569 .hairpin_unbind = mlx5_hairpin_unbind, 2570 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2571 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2572 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2573 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2574 }; 2575 2576 /* Available operations from secondary process. */ 2577 const struct eth_dev_ops mlx5_os_dev_sec_ops = { 2578 .stats_get = mlx5_stats_get, 2579 .stats_reset = mlx5_stats_reset, 2580 .xstats_get = mlx5_xstats_get, 2581 .xstats_reset = mlx5_xstats_reset, 2582 .xstats_get_names = mlx5_xstats_get_names, 2583 .fw_version_get = mlx5_fw_version_get, 2584 .dev_infos_get = mlx5_dev_infos_get, 2585 .read_clock = mlx5_txpp_read_clock, 2586 .rx_queue_start = mlx5_rx_queue_start, 2587 .rx_queue_stop = mlx5_rx_queue_stop, 2588 .tx_queue_start = mlx5_tx_queue_start, 2589 .tx_queue_stop = mlx5_tx_queue_stop, 2590 .rxq_info_get = mlx5_rxq_info_get, 2591 .txq_info_get = mlx5_txq_info_get, 2592 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2593 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2594 .get_module_info = mlx5_get_module_info, 2595 .get_module_eeprom = mlx5_get_module_eeprom, 2596 }; 2597 2598 /* Available operations in flow isolated mode. */ 2599 const struct eth_dev_ops mlx5_os_dev_ops_isolate = { 2600 .dev_configure = mlx5_dev_configure, 2601 .dev_start = mlx5_dev_start, 2602 .dev_stop = mlx5_dev_stop, 2603 .dev_set_link_down = mlx5_set_link_down, 2604 .dev_set_link_up = mlx5_set_link_up, 2605 .dev_close = mlx5_dev_close, 2606 .promiscuous_enable = mlx5_promiscuous_enable, 2607 .promiscuous_disable = mlx5_promiscuous_disable, 2608 .allmulticast_enable = mlx5_allmulticast_enable, 2609 .allmulticast_disable = mlx5_allmulticast_disable, 2610 .link_update = mlx5_link_update, 2611 .stats_get = mlx5_stats_get, 2612 .stats_reset = mlx5_stats_reset, 2613 .xstats_get = mlx5_xstats_get, 2614 .xstats_reset = mlx5_xstats_reset, 2615 .xstats_get_names = mlx5_xstats_get_names, 2616 .fw_version_get = mlx5_fw_version_get, 2617 .dev_infos_get = mlx5_dev_infos_get, 2618 .read_clock = mlx5_txpp_read_clock, 2619 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2620 .vlan_filter_set = mlx5_vlan_filter_set, 2621 .rx_queue_setup = mlx5_rx_queue_setup, 2622 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2623 .tx_queue_setup = mlx5_tx_queue_setup, 2624 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2625 .rx_queue_release = mlx5_rx_queue_release, 2626 .tx_queue_release = mlx5_tx_queue_release, 2627 .rx_queue_start = mlx5_rx_queue_start, 2628 .rx_queue_stop = mlx5_rx_queue_stop, 2629 .tx_queue_start = mlx5_tx_queue_start, 2630 .tx_queue_stop = mlx5_tx_queue_stop, 2631 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2632 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2633 .mac_addr_remove = mlx5_mac_addr_remove, 2634 .mac_addr_add = mlx5_mac_addr_add, 2635 .mac_addr_set = mlx5_mac_addr_set, 2636 .set_mc_addr_list = mlx5_set_mc_addr_list, 2637 .mtu_set = mlx5_dev_set_mtu, 2638 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2639 .vlan_offload_set = mlx5_vlan_offload_set, 2640 .filter_ctrl = mlx5_dev_filter_ctrl, 2641 .rxq_info_get = mlx5_rxq_info_get, 2642 .txq_info_get = mlx5_txq_info_get, 2643 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2644 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2645 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2646 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2647 .is_removed = mlx5_is_removed, 2648 .get_module_info = mlx5_get_module_info, 2649 .get_module_eeprom = mlx5_get_module_eeprom, 2650 .hairpin_cap_get = mlx5_hairpin_cap_get, 2651 .mtr_ops_get = mlx5_flow_meter_ops_get, 2652 .hairpin_bind = mlx5_hairpin_bind, 2653 .hairpin_unbind = mlx5_hairpin_unbind, 2654 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2655 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2656 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2657 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2658 }; 2659