1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_qp = attr_ex.orig_attr.max_qp; 120 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 121 device_attr->max_rwq_indirection_table_size = 122 attr_ex.rss_caps.max_rwq_indirection_table_size; 123 device_attr->max_tso = attr_ex.tso_caps.max_tso; 124 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 125 126 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 127 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 128 if (err) 129 return err; 130 131 device_attr->flags = dv_attr.flags; 132 device_attr->comp_mask = dv_attr.comp_mask; 133 #ifdef HAVE_IBV_MLX5_MOD_SWP 134 device_attr->sw_parsing_offloads = 135 dv_attr.sw_parsing_caps.sw_parsing_offloads; 136 #endif 137 device_attr->min_single_stride_log_num_of_bytes = 138 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 139 device_attr->max_single_stride_log_num_of_bytes = 140 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 141 device_attr->min_single_wqe_log_num_of_strides = 142 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 143 device_attr->max_single_wqe_log_num_of_strides = 144 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 145 device_attr->stride_supported_qpts = 146 dv_attr.striding_rq_caps.supported_qpts; 147 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 148 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 149 #endif 150 151 return err; 152 } 153 154 /** 155 * Verbs callback to allocate a memory. This function should allocate the space 156 * according to the size provided residing inside a huge page. 157 * Please note that all allocation must respect the alignment from libmlx5 158 * (i.e. currently rte_mem_page_size()). 159 * 160 * @param[in] size 161 * The size in bytes of the memory to allocate. 162 * @param[in] data 163 * A pointer to the callback data. 164 * 165 * @return 166 * Allocated buffer, NULL otherwise and rte_errno is set. 167 */ 168 static void * 169 mlx5_alloc_verbs_buf(size_t size, void *data) 170 { 171 struct mlx5_priv *priv = data; 172 void *ret; 173 unsigned int socket = SOCKET_ID_ANY; 174 size_t alignment = rte_mem_page_size(); 175 if (alignment == (size_t)-1) { 176 DRV_LOG(ERR, "Failed to get mem page size"); 177 rte_errno = ENOMEM; 178 return NULL; 179 } 180 181 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 182 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 183 184 socket = ctrl->socket; 185 } else if (priv->verbs_alloc_ctx.type == 186 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 187 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 188 189 socket = ctrl->socket; 190 } 191 MLX5_ASSERT(data != NULL); 192 ret = mlx5_malloc(0, size, alignment, socket); 193 if (!ret && size) 194 rte_errno = ENOMEM; 195 return ret; 196 } 197 198 /** 199 * Verbs callback to free a memory. 200 * 201 * @param[in] ptr 202 * A pointer to the memory to free. 203 * @param[in] data 204 * A pointer to the callback data. 205 */ 206 static void 207 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 208 { 209 MLX5_ASSERT(data != NULL); 210 mlx5_free(ptr); 211 } 212 213 /** 214 * Initialize DR related data within private structure. 215 * Routine checks the reference counter and does actual 216 * resources creation/initialization only if counter is zero. 217 * 218 * @param[in] priv 219 * Pointer to the private device data structure. 220 * 221 * @return 222 * Zero on success, positive error code otherwise. 223 */ 224 static int 225 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 226 { 227 struct mlx5_dev_ctx_shared *sh = priv->sh; 228 char s[MLX5_HLIST_NAMESIZE]; 229 int err = 0; 230 231 if (!sh->flow_tbls) 232 err = mlx5_alloc_table_hash_list(priv); 233 else 234 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n", 235 (void *)sh->flow_tbls); 236 if (err) 237 return err; 238 /* Create tags hash list table. */ 239 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 240 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE); 241 if (!sh->tag_table) { 242 DRV_LOG(ERR, "tags with hash creation failed."); 243 err = ENOMEM; 244 goto error; 245 } 246 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 247 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ); 248 if (!sh->modify_cmds) { 249 DRV_LOG(ERR, "hdr modify hash creation failed"); 250 err = ENOMEM; 251 goto error; 252 } 253 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 254 sh->encaps_decaps = mlx5_hlist_create(s, 255 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ); 256 if (!sh->encaps_decaps) { 257 DRV_LOG(ERR, "encap decap hash creation failed"); 258 err = ENOMEM; 259 goto error; 260 } 261 #ifdef HAVE_MLX5DV_DR 262 void *domain; 263 264 if (sh->dv_refcnt) { 265 /* Shared DV/DR structures is already initialized. */ 266 sh->dv_refcnt++; 267 priv->dr_shared = 1; 268 return 0; 269 } 270 /* Reference counter is zero, we should initialize structures. */ 271 domain = mlx5_glue->dr_create_domain(sh->ctx, 272 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 273 if (!domain) { 274 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 275 err = errno; 276 goto error; 277 } 278 sh->rx_domain = domain; 279 domain = mlx5_glue->dr_create_domain(sh->ctx, 280 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 281 if (!domain) { 282 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 283 err = errno; 284 goto error; 285 } 286 pthread_mutex_init(&sh->dv_mutex, NULL); 287 sh->tx_domain = domain; 288 #ifdef HAVE_MLX5DV_DR_ESWITCH 289 if (priv->config.dv_esw_en) { 290 domain = mlx5_glue->dr_create_domain 291 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 292 if (!domain) { 293 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 294 err = errno; 295 goto error; 296 } 297 sh->fdb_domain = domain; 298 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 299 } 300 #endif 301 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 302 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 303 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 304 if (sh->fdb_domain) 305 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 306 } 307 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 308 #endif /* HAVE_MLX5DV_DR */ 309 sh->dv_refcnt++; 310 priv->dr_shared = 1; 311 return 0; 312 error: 313 /* Rollback the created objects. */ 314 if (sh->rx_domain) { 315 mlx5_glue->dr_destroy_domain(sh->rx_domain); 316 sh->rx_domain = NULL; 317 } 318 if (sh->tx_domain) { 319 mlx5_glue->dr_destroy_domain(sh->tx_domain); 320 sh->tx_domain = NULL; 321 } 322 if (sh->fdb_domain) { 323 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 324 sh->fdb_domain = NULL; 325 } 326 if (sh->esw_drop_action) { 327 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 328 sh->esw_drop_action = NULL; 329 } 330 if (sh->pop_vlan_action) { 331 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 332 sh->pop_vlan_action = NULL; 333 } 334 if (sh->encaps_decaps) { 335 mlx5_hlist_destroy(sh->encaps_decaps, NULL, NULL); 336 sh->encaps_decaps = NULL; 337 } 338 if (sh->modify_cmds) { 339 mlx5_hlist_destroy(sh->modify_cmds, NULL, NULL); 340 sh->modify_cmds = NULL; 341 } 342 if (sh->tag_table) { 343 /* tags should be destroyed with flow before. */ 344 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 345 sh->tag_table = NULL; 346 } 347 mlx5_free_table_hash_list(priv); 348 return err; 349 } 350 351 /** 352 * Destroy DR related data within private structure. 353 * 354 * @param[in] priv 355 * Pointer to the private device data structure. 356 */ 357 void 358 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 359 { 360 struct mlx5_dev_ctx_shared *sh; 361 362 if (!priv->dr_shared) 363 return; 364 priv->dr_shared = 0; 365 sh = priv->sh; 366 MLX5_ASSERT(sh); 367 #ifdef HAVE_MLX5DV_DR 368 MLX5_ASSERT(sh->dv_refcnt); 369 if (sh->dv_refcnt && --sh->dv_refcnt) 370 return; 371 if (sh->rx_domain) { 372 mlx5_glue->dr_destroy_domain(sh->rx_domain); 373 sh->rx_domain = NULL; 374 } 375 if (sh->tx_domain) { 376 mlx5_glue->dr_destroy_domain(sh->tx_domain); 377 sh->tx_domain = NULL; 378 } 379 #ifdef HAVE_MLX5DV_DR_ESWITCH 380 if (sh->fdb_domain) { 381 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 382 sh->fdb_domain = NULL; 383 } 384 if (sh->esw_drop_action) { 385 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 386 sh->esw_drop_action = NULL; 387 } 388 #endif 389 if (sh->pop_vlan_action) { 390 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 391 sh->pop_vlan_action = NULL; 392 } 393 pthread_mutex_destroy(&sh->dv_mutex); 394 #endif /* HAVE_MLX5DV_DR */ 395 if (sh->encaps_decaps) { 396 mlx5_hlist_destroy(sh->encaps_decaps, NULL, NULL); 397 sh->encaps_decaps = NULL; 398 } 399 if (sh->modify_cmds) { 400 mlx5_hlist_destroy(sh->modify_cmds, NULL, NULL); 401 sh->modify_cmds = NULL; 402 } 403 if (sh->tag_table) { 404 /* tags should be destroyed with flow before. */ 405 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 406 sh->tag_table = NULL; 407 } 408 mlx5_free_table_hash_list(priv); 409 } 410 411 /** 412 * Initialize shared data between primary and secondary process. 413 * 414 * A memzone is reserved by primary process and secondary processes attach to 415 * the memzone. 416 * 417 * @return 418 * 0 on success, a negative errno value otherwise and rte_errno is set. 419 */ 420 static int 421 mlx5_init_shared_data(void) 422 { 423 const struct rte_memzone *mz; 424 int ret = 0; 425 426 rte_spinlock_lock(&mlx5_shared_data_lock); 427 if (mlx5_shared_data == NULL) { 428 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 429 /* Allocate shared memory. */ 430 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 431 sizeof(*mlx5_shared_data), 432 SOCKET_ID_ANY, 0); 433 if (mz == NULL) { 434 DRV_LOG(ERR, 435 "Cannot allocate mlx5 shared data"); 436 ret = -rte_errno; 437 goto error; 438 } 439 mlx5_shared_data = mz->addr; 440 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 441 rte_spinlock_init(&mlx5_shared_data->lock); 442 } else { 443 /* Lookup allocated shared memory. */ 444 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 445 if (mz == NULL) { 446 DRV_LOG(ERR, 447 "Cannot attach mlx5 shared data"); 448 ret = -rte_errno; 449 goto error; 450 } 451 mlx5_shared_data = mz->addr; 452 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 453 } 454 } 455 error: 456 rte_spinlock_unlock(&mlx5_shared_data_lock); 457 return ret; 458 } 459 460 /** 461 * PMD global initialization. 462 * 463 * Independent from individual device, this function initializes global 464 * per-PMD data structures distinguishing primary and secondary processes. 465 * Hence, each initialization is called once per a process. 466 * 467 * @return 468 * 0 on success, a negative errno value otherwise and rte_errno is set. 469 */ 470 static int 471 mlx5_init_once(void) 472 { 473 struct mlx5_shared_data *sd; 474 struct mlx5_local_data *ld = &mlx5_local_data; 475 int ret = 0; 476 477 if (mlx5_init_shared_data()) 478 return -rte_errno; 479 sd = mlx5_shared_data; 480 MLX5_ASSERT(sd); 481 rte_spinlock_lock(&sd->lock); 482 switch (rte_eal_process_type()) { 483 case RTE_PROC_PRIMARY: 484 if (sd->init_done) 485 break; 486 LIST_INIT(&sd->mem_event_cb_list); 487 rte_rwlock_init(&sd->mem_event_rwlock); 488 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 489 mlx5_mr_mem_event_cb, NULL); 490 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 491 mlx5_mp_os_primary_handle); 492 if (ret) 493 goto out; 494 sd->init_done = true; 495 break; 496 case RTE_PROC_SECONDARY: 497 if (ld->init_done) 498 break; 499 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 500 mlx5_mp_os_secondary_handle); 501 if (ret) 502 goto out; 503 ++sd->secondary_cnt; 504 ld->init_done = true; 505 break; 506 default: 507 break; 508 } 509 out: 510 rte_spinlock_unlock(&sd->lock); 511 return ret; 512 } 513 514 /** 515 * Create the Tx queue DevX/Verbs object. 516 * 517 * @param dev 518 * Pointer to Ethernet device. 519 * @param idx 520 * Queue index in DPDK Tx queue array. 521 * 522 * @return 523 * 0 on success, a negative errno value otherwise and rte_errno is set. 524 */ 525 static int 526 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 527 { 528 struct mlx5_priv *priv = dev->data->dev_private; 529 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 530 struct mlx5_txq_ctrl *txq_ctrl = 531 container_of(txq_data, struct mlx5_txq_ctrl, txq); 532 533 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 534 return mlx5_txq_devx_obj_new(dev, idx); 535 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 536 if (!priv->config.dv_esw_en) 537 return mlx5_txq_devx_obj_new(dev, idx); 538 #endif 539 return mlx5_txq_ibv_obj_new(dev, idx); 540 } 541 542 /** 543 * Release an Tx DevX/verbs queue object. 544 * 545 * @param txq_obj 546 * DevX/Verbs Tx queue object. 547 */ 548 static void 549 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 550 { 551 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 552 mlx5_txq_devx_obj_release(txq_obj); 553 return; 554 } 555 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 556 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 557 mlx5_txq_devx_obj_release(txq_obj); 558 return; 559 } 560 #endif 561 mlx5_txq_ibv_obj_release(txq_obj); 562 } 563 564 /** 565 * Spawn an Ethernet device from Verbs information. 566 * 567 * @param dpdk_dev 568 * Backing DPDK device. 569 * @param spawn 570 * Verbs device parameters (name, port, switch_info) to spawn. 571 * @param config 572 * Device configuration parameters. 573 * 574 * @return 575 * A valid Ethernet device object on success, NULL otherwise and rte_errno 576 * is set. The following errors are defined: 577 * 578 * EBUSY: device is not supposed to be spawned. 579 * EEXIST: device is already spawned 580 */ 581 static struct rte_eth_dev * 582 mlx5_dev_spawn(struct rte_device *dpdk_dev, 583 struct mlx5_dev_spawn_data *spawn, 584 struct mlx5_dev_config *config) 585 { 586 const struct mlx5_switch_info *switch_info = &spawn->info; 587 struct mlx5_dev_ctx_shared *sh = NULL; 588 struct ibv_port_attr port_attr; 589 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 590 struct rte_eth_dev *eth_dev = NULL; 591 struct mlx5_priv *priv = NULL; 592 int err = 0; 593 unsigned int hw_padding = 0; 594 unsigned int mps; 595 unsigned int cqe_comp; 596 unsigned int cqe_pad = 0; 597 unsigned int tunnel_en = 0; 598 unsigned int mpls_en = 0; 599 unsigned int swp = 0; 600 unsigned int mprq = 0; 601 unsigned int mprq_min_stride_size_n = 0; 602 unsigned int mprq_max_stride_size_n = 0; 603 unsigned int mprq_min_stride_num_n = 0; 604 unsigned int mprq_max_stride_num_n = 0; 605 struct rte_ether_addr mac; 606 char name[RTE_ETH_NAME_MAX_LEN]; 607 int own_domain_id = 0; 608 uint16_t port_id; 609 unsigned int i; 610 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 611 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 612 #endif 613 614 /* Determine if this port representor is supposed to be spawned. */ 615 if (switch_info->representor && dpdk_dev->devargs) { 616 struct rte_eth_devargs eth_da; 617 618 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 619 if (err) { 620 rte_errno = -err; 621 DRV_LOG(ERR, "failed to process device arguments: %s", 622 strerror(rte_errno)); 623 return NULL; 624 } 625 for (i = 0; i < eth_da.nb_representor_ports; ++i) 626 if (eth_da.representor_ports[i] == 627 (uint16_t)switch_info->port_name) 628 break; 629 if (i == eth_da.nb_representor_ports) { 630 rte_errno = EBUSY; 631 return NULL; 632 } 633 } 634 /* Build device name. */ 635 if (spawn->pf_bond < 0) { 636 /* Single device. */ 637 if (!switch_info->representor) 638 strlcpy(name, dpdk_dev->name, sizeof(name)); 639 else 640 snprintf(name, sizeof(name), "%s_representor_%u", 641 dpdk_dev->name, switch_info->port_name); 642 } else { 643 /* Bonding device. */ 644 if (!switch_info->representor) 645 snprintf(name, sizeof(name), "%s_%s", 646 dpdk_dev->name, 647 mlx5_os_get_dev_device_name(spawn->phys_dev)); 648 else 649 snprintf(name, sizeof(name), "%s_%s_representor_%u", 650 dpdk_dev->name, 651 mlx5_os_get_dev_device_name(spawn->phys_dev), 652 switch_info->port_name); 653 } 654 /* check if the device is already spawned */ 655 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 656 rte_errno = EEXIST; 657 return NULL; 658 } 659 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 660 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 661 struct mlx5_mp_id mp_id; 662 663 eth_dev = rte_eth_dev_attach_secondary(name); 664 if (eth_dev == NULL) { 665 DRV_LOG(ERR, "can not attach rte ethdev"); 666 rte_errno = ENOMEM; 667 return NULL; 668 } 669 eth_dev->device = dpdk_dev; 670 eth_dev->dev_ops = &mlx5_os_dev_sec_ops; 671 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 672 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 673 err = mlx5_proc_priv_init(eth_dev); 674 if (err) 675 return NULL; 676 mp_id.port_id = eth_dev->data->port_id; 677 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 678 /* Receive command fd from primary process */ 679 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 680 if (err < 0) 681 goto err_secondary; 682 /* Remap UAR for Tx queues. */ 683 err = mlx5_tx_uar_init_secondary(eth_dev, err); 684 if (err) 685 goto err_secondary; 686 /* 687 * Ethdev pointer is still required as input since 688 * the primary device is not accessible from the 689 * secondary process. 690 */ 691 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 692 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 693 return eth_dev; 694 err_secondary: 695 mlx5_dev_close(eth_dev); 696 return NULL; 697 } 698 /* 699 * Some parameters ("tx_db_nc" in particularly) are needed in 700 * advance to create dv/verbs device context. We proceed the 701 * devargs here to get ones, and later proceed devargs again 702 * to override some hardware settings. 703 */ 704 err = mlx5_args(config, dpdk_dev->devargs); 705 if (err) { 706 err = rte_errno; 707 DRV_LOG(ERR, "failed to process device arguments: %s", 708 strerror(rte_errno)); 709 goto error; 710 } 711 mlx5_malloc_mem_select(config->sys_mem_en); 712 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 713 if (!sh) 714 return NULL; 715 config->devx = sh->devx; 716 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 717 config->dest_tir = 1; 718 #endif 719 #ifdef HAVE_IBV_MLX5_MOD_SWP 720 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 721 #endif 722 /* 723 * Multi-packet send is supported by ConnectX-4 Lx PF as well 724 * as all ConnectX-5 devices. 725 */ 726 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 727 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 728 #endif 729 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 730 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 731 #endif 732 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 733 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 734 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 735 DRV_LOG(DEBUG, "enhanced MPW is supported"); 736 mps = MLX5_MPW_ENHANCED; 737 } else { 738 DRV_LOG(DEBUG, "MPW is supported"); 739 mps = MLX5_MPW; 740 } 741 } else { 742 DRV_LOG(DEBUG, "MPW isn't supported"); 743 mps = MLX5_MPW_DISABLED; 744 } 745 #ifdef HAVE_IBV_MLX5_MOD_SWP 746 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 747 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 748 DRV_LOG(DEBUG, "SWP support: %u", swp); 749 #endif 750 config->swp = !!swp; 751 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 752 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 753 struct mlx5dv_striding_rq_caps mprq_caps = 754 dv_attr.striding_rq_caps; 755 756 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 757 mprq_caps.min_single_stride_log_num_of_bytes); 758 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 759 mprq_caps.max_single_stride_log_num_of_bytes); 760 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 761 mprq_caps.min_single_wqe_log_num_of_strides); 762 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 763 mprq_caps.max_single_wqe_log_num_of_strides); 764 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 765 mprq_caps.supported_qpts); 766 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 767 mprq = 1; 768 mprq_min_stride_size_n = 769 mprq_caps.min_single_stride_log_num_of_bytes; 770 mprq_max_stride_size_n = 771 mprq_caps.max_single_stride_log_num_of_bytes; 772 mprq_min_stride_num_n = 773 mprq_caps.min_single_wqe_log_num_of_strides; 774 mprq_max_stride_num_n = 775 mprq_caps.max_single_wqe_log_num_of_strides; 776 } 777 #endif 778 if (RTE_CACHE_LINE_SIZE == 128 && 779 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 780 cqe_comp = 0; 781 else 782 cqe_comp = 1; 783 config->cqe_comp = cqe_comp; 784 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 785 /* Whether device supports 128B Rx CQE padding. */ 786 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 787 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 788 #endif 789 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 790 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 791 tunnel_en = ((dv_attr.tunnel_offloads_caps & 792 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 793 (dv_attr.tunnel_offloads_caps & 794 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 795 (dv_attr.tunnel_offloads_caps & 796 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 797 } 798 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 799 tunnel_en ? "" : "not "); 800 #else 801 DRV_LOG(WARNING, 802 "tunnel offloading disabled due to old OFED/rdma-core version"); 803 #endif 804 config->tunnel_en = tunnel_en; 805 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 806 mpls_en = ((dv_attr.tunnel_offloads_caps & 807 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 808 (dv_attr.tunnel_offloads_caps & 809 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 810 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 811 mpls_en ? "" : "not "); 812 #else 813 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 814 " old OFED/rdma-core version or firmware configuration"); 815 #endif 816 config->mpls_en = mpls_en; 817 /* Check port status. */ 818 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 819 if (err) { 820 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 821 goto error; 822 } 823 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 824 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 825 err = EINVAL; 826 goto error; 827 } 828 if (port_attr.state != IBV_PORT_ACTIVE) 829 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 830 mlx5_glue->port_state_str(port_attr.state), 831 port_attr.state); 832 /* Allocate private eth device data. */ 833 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 834 sizeof(*priv), 835 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 836 if (priv == NULL) { 837 DRV_LOG(ERR, "priv allocation failure"); 838 err = ENOMEM; 839 goto error; 840 } 841 priv->sh = sh; 842 priv->dev_port = spawn->phys_port; 843 priv->pci_dev = spawn->pci_dev; 844 priv->mtu = RTE_ETHER_MTU; 845 priv->mp_id.port_id = port_id; 846 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 847 /* Some internal functions rely on Netlink sockets, open them now. */ 848 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 849 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 850 priv->representor = !!switch_info->representor; 851 priv->master = !!switch_info->master; 852 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 853 priv->vport_meta_tag = 0; 854 priv->vport_meta_mask = 0; 855 priv->pf_bond = spawn->pf_bond; 856 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 857 /* 858 * The DevX port query API is implemented. E-Switch may use 859 * either vport or reg_c[0] metadata register to match on 860 * vport index. The engaged part of metadata register is 861 * defined by mask. 862 */ 863 if (switch_info->representor || switch_info->master) { 864 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 865 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 866 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 867 &devx_port); 868 if (err) { 869 DRV_LOG(WARNING, 870 "can't query devx port %d on device %s", 871 spawn->phys_port, 872 mlx5_os_get_dev_device_name(spawn->phys_dev)); 873 devx_port.comp_mask = 0; 874 } 875 } 876 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 877 priv->vport_meta_tag = devx_port.reg_c_0.value; 878 priv->vport_meta_mask = devx_port.reg_c_0.mask; 879 if (!priv->vport_meta_mask) { 880 DRV_LOG(ERR, "vport zero mask for port %d" 881 " on bonding device %s", 882 spawn->phys_port, 883 mlx5_os_get_dev_device_name 884 (spawn->phys_dev)); 885 err = ENOTSUP; 886 goto error; 887 } 888 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 889 DRV_LOG(ERR, "invalid vport tag for port %d" 890 " on bonding device %s", 891 spawn->phys_port, 892 mlx5_os_get_dev_device_name 893 (spawn->phys_dev)); 894 err = ENOTSUP; 895 goto error; 896 } 897 } 898 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 899 priv->vport_id = devx_port.vport_num; 900 } else if (spawn->pf_bond >= 0) { 901 DRV_LOG(ERR, "can't deduce vport index for port %d" 902 " on bonding device %s", 903 spawn->phys_port, 904 mlx5_os_get_dev_device_name(spawn->phys_dev)); 905 err = ENOTSUP; 906 goto error; 907 } else { 908 /* Suppose vport index in compatible way. */ 909 priv->vport_id = switch_info->representor ? 910 switch_info->port_name + 1 : -1; 911 } 912 #else 913 /* 914 * Kernel/rdma_core support single E-Switch per PF configurations 915 * only and vport_id field contains the vport index for 916 * associated VF, which is deduced from representor port name. 917 * For example, let's have the IB device port 10, it has 918 * attached network device eth0, which has port name attribute 919 * pf0vf2, we can deduce the VF number as 2, and set vport index 920 * as 3 (2+1). This assigning schema should be changed if the 921 * multiple E-Switch instances per PF configurations or/and PCI 922 * subfunctions are added. 923 */ 924 priv->vport_id = switch_info->representor ? 925 switch_info->port_name + 1 : -1; 926 #endif 927 /* representor_id field keeps the unmodified VF index. */ 928 priv->representor_id = switch_info->representor ? 929 switch_info->port_name : -1; 930 /* 931 * Look for sibling devices in order to reuse their switch domain 932 * if any, otherwise allocate one. 933 */ 934 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 935 const struct mlx5_priv *opriv = 936 rte_eth_devices[port_id].data->dev_private; 937 938 if (!opriv || 939 opriv->sh != priv->sh || 940 opriv->domain_id == 941 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 942 continue; 943 priv->domain_id = opriv->domain_id; 944 break; 945 } 946 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 947 err = rte_eth_switch_domain_alloc(&priv->domain_id); 948 if (err) { 949 err = rte_errno; 950 DRV_LOG(ERR, "unable to allocate switch domain: %s", 951 strerror(rte_errno)); 952 goto error; 953 } 954 own_domain_id = 1; 955 } 956 /* Override some values set by hardware configuration. */ 957 mlx5_args(config, dpdk_dev->devargs); 958 err = mlx5_dev_check_sibling_config(priv, config); 959 if (err) 960 goto error; 961 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 962 IBV_DEVICE_RAW_IP_CSUM); 963 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 964 (config->hw_csum ? "" : "not ")); 965 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 966 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 967 DRV_LOG(DEBUG, "counters are not supported"); 968 #endif 969 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 970 if (config->dv_flow_en) { 971 DRV_LOG(WARNING, "DV flow is not supported"); 972 config->dv_flow_en = 0; 973 } 974 #endif 975 config->ind_table_max_size = 976 sh->device_attr.max_rwq_indirection_table_size; 977 /* 978 * Remove this check once DPDK supports larger/variable 979 * indirection tables. 980 */ 981 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 982 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 983 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 984 config->ind_table_max_size); 985 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 986 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 987 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 988 (config->hw_vlan_strip ? "" : "not ")); 989 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 990 IBV_RAW_PACKET_CAP_SCATTER_FCS); 991 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 992 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 993 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 994 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 995 IBV_DEVICE_PCI_WRITE_END_PADDING); 996 #endif 997 if (config->hw_padding && !hw_padding) { 998 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 999 config->hw_padding = 0; 1000 } else if (config->hw_padding) { 1001 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1002 } 1003 config->tso = (sh->device_attr.max_tso > 0 && 1004 (sh->device_attr.tso_supported_qpts & 1005 (1 << IBV_QPT_RAW_PACKET))); 1006 if (config->tso) 1007 config->tso_max_payload_sz = sh->device_attr.max_tso; 1008 /* 1009 * MPW is disabled by default, while the Enhanced MPW is enabled 1010 * by default. 1011 */ 1012 if (config->mps == MLX5_ARG_UNSET) 1013 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1014 MLX5_MPW_DISABLED; 1015 else 1016 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1017 DRV_LOG(INFO, "%sMPS is %s", 1018 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1019 config->mps == MLX5_MPW ? "legacy " : "", 1020 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1021 if (config->cqe_comp && !cqe_comp) { 1022 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1023 config->cqe_comp = 0; 1024 } 1025 if (config->cqe_pad && !cqe_pad) { 1026 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1027 config->cqe_pad = 0; 1028 } else if (config->cqe_pad) { 1029 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1030 } 1031 if (config->devx) { 1032 priv->counter_fallback = 0; 1033 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1034 if (err) { 1035 err = -err; 1036 goto error; 1037 } 1038 if (!config->hca_attr.flow_counters_dump) 1039 priv->counter_fallback = 1; 1040 #ifndef HAVE_IBV_DEVX_ASYNC 1041 priv->counter_fallback = 1; 1042 #endif 1043 if (priv->counter_fallback) 1044 DRV_LOG(INFO, "Use fall-back DV counter management"); 1045 /* Check for LRO support. */ 1046 if (config->dest_tir && config->hca_attr.lro_cap && 1047 config->dv_flow_en) { 1048 /* TBD check tunnel lro caps. */ 1049 config->lro.supported = config->hca_attr.lro_cap; 1050 DRV_LOG(DEBUG, "Device supports LRO"); 1051 /* 1052 * If LRO timeout is not configured by application, 1053 * use the minimal supported value. 1054 */ 1055 if (!config->lro.timeout) 1056 config->lro.timeout = 1057 config->hca_attr.lro_timer_supported_periods[0]; 1058 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1059 config->lro.timeout); 1060 } 1061 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1062 if (config->hca_attr.qos.sup && 1063 config->hca_attr.qos.srtcm_sup && 1064 config->dv_flow_en) { 1065 uint8_t reg_c_mask = 1066 config->hca_attr.qos.flow_meter_reg_c_ids; 1067 /* 1068 * Meter needs two REG_C's for color match and pre-sfx 1069 * flow match. Here get the REG_C for color match. 1070 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1071 */ 1072 reg_c_mask &= 0xfc; 1073 if (__builtin_popcount(reg_c_mask) < 1) { 1074 priv->mtr_en = 0; 1075 DRV_LOG(WARNING, "No available register for" 1076 " meter."); 1077 } else { 1078 priv->mtr_color_reg = ffs(reg_c_mask) - 1 + 1079 REG_C_0; 1080 priv->mtr_en = 1; 1081 priv->mtr_reg_share = 1082 config->hca_attr.qos.flow_meter_reg_share; 1083 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1084 priv->mtr_color_reg); 1085 } 1086 } 1087 #endif 1088 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1089 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1090 config->dv_flow_en) { 1091 priv->sampler_en = 1; 1092 DRV_LOG(DEBUG, "The Sampler enabled!\n"); 1093 } else { 1094 priv->sampler_en = 0; 1095 if (!config->hca_attr.log_max_ft_sampler_num) 1096 DRV_LOG(WARNING, "No available register for" 1097 " Sampler."); 1098 else 1099 DRV_LOG(DEBUG, "DV flow is not supported!\n"); 1100 } 1101 #endif 1102 } 1103 if (config->tx_pp) { 1104 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1105 config->hca_attr.dev_freq_khz); 1106 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1107 config->hca_attr.qos.packet_pacing ? "" : "not "); 1108 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1109 config->hca_attr.cross_channel ? "" : "not "); 1110 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1111 config->hca_attr.wqe_index_ignore ? "" : "not "); 1112 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1113 config->hca_attr.non_wire_sq ? "" : "not "); 1114 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1115 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1116 config->hca_attr.log_max_static_sq_wq); 1117 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1118 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1119 if (!config->devx) { 1120 DRV_LOG(ERR, "DevX is required for packet pacing"); 1121 err = ENODEV; 1122 goto error; 1123 } 1124 if (!config->hca_attr.qos.packet_pacing) { 1125 DRV_LOG(ERR, "Packet pacing is not supported"); 1126 err = ENODEV; 1127 goto error; 1128 } 1129 if (!config->hca_attr.cross_channel) { 1130 DRV_LOG(ERR, "Cross channel operations are" 1131 " required for packet pacing"); 1132 err = ENODEV; 1133 goto error; 1134 } 1135 if (!config->hca_attr.wqe_index_ignore) { 1136 DRV_LOG(ERR, "WQE index ignore feature is" 1137 " required for packet pacing"); 1138 err = ENODEV; 1139 goto error; 1140 } 1141 if (!config->hca_attr.non_wire_sq) { 1142 DRV_LOG(ERR, "Non-wire SQ feature is" 1143 " required for packet pacing"); 1144 err = ENODEV; 1145 goto error; 1146 } 1147 if (!config->hca_attr.log_max_static_sq_wq) { 1148 DRV_LOG(ERR, "Static WQE SQ feature is" 1149 " required for packet pacing"); 1150 err = ENODEV; 1151 goto error; 1152 } 1153 if (!config->hca_attr.qos.wqe_rate_pp) { 1154 DRV_LOG(ERR, "WQE rate mode is required" 1155 " for packet pacing"); 1156 err = ENODEV; 1157 goto error; 1158 } 1159 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1160 DRV_LOG(ERR, "DevX does not provide UAR offset," 1161 " can't create queues for packet pacing"); 1162 err = ENODEV; 1163 goto error; 1164 #endif 1165 } 1166 if (config->devx) { 1167 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1168 1169 err = config->hca_attr.access_register_user ? 1170 mlx5_devx_cmd_register_read 1171 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1172 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1173 if (!err) { 1174 uint32_t ts_mode; 1175 1176 /* MTUTC register is read successfully. */ 1177 ts_mode = MLX5_GET(register_mtutc, reg, 1178 time_stamp_mode); 1179 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1180 config->rt_timestamp = 1; 1181 } else { 1182 /* Kernel does not support register reading. */ 1183 if (config->hca_attr.dev_freq_khz == 1184 (NS_PER_S / MS_PER_S)) 1185 config->rt_timestamp = 1; 1186 } 1187 } 1188 /* 1189 * If HW has bug working with tunnel packet decapsulation and 1190 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1191 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1192 */ 1193 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1194 config->hw_fcs_strip = 0; 1195 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1196 (config->hw_fcs_strip ? "" : "not ")); 1197 if (config->mprq.enabled && mprq) { 1198 if (config->mprq.stride_num_n && 1199 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1200 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1201 config->mprq.stride_num_n = 1202 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1203 mprq_min_stride_num_n), 1204 mprq_max_stride_num_n); 1205 DRV_LOG(WARNING, 1206 "the number of strides" 1207 " for Multi-Packet RQ is out of range," 1208 " setting default value (%u)", 1209 1 << config->mprq.stride_num_n); 1210 } 1211 if (config->mprq.stride_size_n && 1212 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1213 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1214 config->mprq.stride_size_n = 1215 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1216 mprq_min_stride_size_n), 1217 mprq_max_stride_size_n); 1218 DRV_LOG(WARNING, 1219 "the size of a stride" 1220 " for Multi-Packet RQ is out of range," 1221 " setting default value (%u)", 1222 1 << config->mprq.stride_size_n); 1223 } 1224 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1225 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1226 } else if (config->mprq.enabled && !mprq) { 1227 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1228 config->mprq.enabled = 0; 1229 } 1230 if (config->max_dump_files_num == 0) 1231 config->max_dump_files_num = 128; 1232 eth_dev = rte_eth_dev_allocate(name); 1233 if (eth_dev == NULL) { 1234 DRV_LOG(ERR, "can not allocate rte ethdev"); 1235 err = ENOMEM; 1236 goto error; 1237 } 1238 if (priv->representor) { 1239 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1240 eth_dev->data->representor_id = priv->representor_id; 1241 } 1242 /* 1243 * Store associated network device interface index. This index 1244 * is permanent throughout the lifetime of device. So, we may store 1245 * the ifindex here and use the cached value further. 1246 */ 1247 MLX5_ASSERT(spawn->ifindex); 1248 priv->if_index = spawn->ifindex; 1249 if (priv->pf_bond >= 0 && priv->master) { 1250 /* Get bond interface info */ 1251 err = mlx5_sysfs_bond_info(priv->if_index, 1252 &priv->bond_ifindex, 1253 priv->bond_name); 1254 if (err) 1255 DRV_LOG(ERR, "unable to get bond info: %s", 1256 strerror(rte_errno)); 1257 else 1258 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1259 priv->if_index, priv->bond_ifindex, 1260 priv->bond_name); 1261 } 1262 eth_dev->data->dev_private = priv; 1263 priv->dev_data = eth_dev->data; 1264 eth_dev->data->mac_addrs = priv->mac; 1265 eth_dev->device = dpdk_dev; 1266 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1267 /* Configure the first MAC address by default. */ 1268 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1269 DRV_LOG(ERR, 1270 "port %u cannot get MAC address, is mlx5_en" 1271 " loaded? (errno: %s)", 1272 eth_dev->data->port_id, strerror(rte_errno)); 1273 err = ENODEV; 1274 goto error; 1275 } 1276 DRV_LOG(INFO, 1277 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1278 eth_dev->data->port_id, 1279 mac.addr_bytes[0], mac.addr_bytes[1], 1280 mac.addr_bytes[2], mac.addr_bytes[3], 1281 mac.addr_bytes[4], mac.addr_bytes[5]); 1282 #ifdef RTE_LIBRTE_MLX5_DEBUG 1283 { 1284 char ifname[IF_NAMESIZE]; 1285 1286 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1287 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1288 eth_dev->data->port_id, ifname); 1289 else 1290 DRV_LOG(DEBUG, "port %u ifname is unknown", 1291 eth_dev->data->port_id); 1292 } 1293 #endif 1294 /* Get actual MTU if possible. */ 1295 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1296 if (err) { 1297 err = rte_errno; 1298 goto error; 1299 } 1300 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1301 priv->mtu); 1302 /* Initialize burst functions to prevent crashes before link-up. */ 1303 eth_dev->rx_pkt_burst = removed_rx_burst; 1304 eth_dev->tx_pkt_burst = removed_tx_burst; 1305 eth_dev->dev_ops = &mlx5_os_dev_ops; 1306 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1307 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1308 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1309 /* Register MAC address. */ 1310 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1311 if (config->vf && config->vf_nl_en) 1312 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1313 mlx5_ifindex(eth_dev), 1314 eth_dev->data->mac_addrs, 1315 MLX5_MAX_MAC_ADDRESSES); 1316 priv->flows = 0; 1317 priv->ctrl_flows = 0; 1318 TAILQ_INIT(&priv->flow_meters); 1319 TAILQ_INIT(&priv->flow_meter_profiles); 1320 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1321 mlx5_glue->dv_set_context_attr(sh->ctx, 1322 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1323 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1324 .alloc = &mlx5_alloc_verbs_buf, 1325 .free = &mlx5_free_verbs_buf, 1326 .data = priv, 1327 })); 1328 /* Bring Ethernet device up. */ 1329 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1330 eth_dev->data->port_id); 1331 mlx5_set_link_up(eth_dev); 1332 /* 1333 * Even though the interrupt handler is not installed yet, 1334 * interrupts will still trigger on the async_fd from 1335 * Verbs context returned by ibv_open_device(). 1336 */ 1337 mlx5_link_update(eth_dev, 0); 1338 #ifdef HAVE_MLX5DV_DR_ESWITCH 1339 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1340 (switch_info->representor || switch_info->master))) 1341 config->dv_esw_en = 0; 1342 #else 1343 config->dv_esw_en = 0; 1344 #endif 1345 /* Detect minimal data bytes to inline. */ 1346 mlx5_set_min_inline(spawn, config); 1347 /* Store device configuration on private structure. */ 1348 priv->config = *config; 1349 /* Create context for virtual machine VLAN workaround. */ 1350 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1351 if (config->dv_flow_en) { 1352 err = mlx5_alloc_shared_dr(priv); 1353 if (err) 1354 goto error; 1355 /* 1356 * RSS id is shared with meter flow id. Meter flow id can only 1357 * use the 24 MSB of the register. 1358 */ 1359 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >> 1360 MLX5_MTR_COLOR_BITS); 1361 if (!priv->qrss_id_pool) { 1362 DRV_LOG(ERR, "can't create flow id pool"); 1363 err = ENOMEM; 1364 goto error; 1365 } 1366 } 1367 if (config->devx && config->dv_flow_en && config->dest_tir) { 1368 priv->obj_ops = devx_obj_ops; 1369 priv->obj_ops.drop_action_create = 1370 ibv_obj_ops.drop_action_create; 1371 priv->obj_ops.drop_action_destroy = 1372 ibv_obj_ops.drop_action_destroy; 1373 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1374 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1375 #else 1376 if (config->dv_esw_en) 1377 priv->obj_ops.txq_obj_modify = 1378 ibv_obj_ops.txq_obj_modify; 1379 #endif 1380 /* Use specific wrappers for Tx object. */ 1381 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1382 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1383 1384 } else { 1385 priv->obj_ops = ibv_obj_ops; 1386 } 1387 /* Supported Verbs flow priority number detection. */ 1388 err = mlx5_flow_discover_priorities(eth_dev); 1389 if (err < 0) { 1390 err = -err; 1391 goto error; 1392 } 1393 priv->config.flow_prio = err; 1394 if (!priv->config.dv_esw_en && 1395 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1396 DRV_LOG(WARNING, "metadata mode %u is not supported " 1397 "(no E-Switch)", priv->config.dv_xmeta_en); 1398 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1399 } 1400 mlx5_set_metadata_mask(eth_dev); 1401 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1402 !priv->sh->dv_regc0_mask) { 1403 DRV_LOG(ERR, "metadata mode %u is not supported " 1404 "(no metadata reg_c[0] is available)", 1405 priv->config.dv_xmeta_en); 1406 err = ENOTSUP; 1407 goto error; 1408 } 1409 /* 1410 * Allocate the buffer for flow creating, just once. 1411 * The allocation must be done before any flow creating. 1412 */ 1413 mlx5_flow_alloc_intermediate(eth_dev); 1414 /* Query availability of metadata reg_c's. */ 1415 err = mlx5_flow_discover_mreg_c(eth_dev); 1416 if (err < 0) { 1417 err = -err; 1418 goto error; 1419 } 1420 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1421 DRV_LOG(DEBUG, 1422 "port %u extensive metadata register is not supported", 1423 eth_dev->data->port_id); 1424 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1425 DRV_LOG(ERR, "metadata mode %u is not supported " 1426 "(no metadata registers available)", 1427 priv->config.dv_xmeta_en); 1428 err = ENOTSUP; 1429 goto error; 1430 } 1431 } 1432 if (priv->config.dv_flow_en && 1433 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1434 mlx5_flow_ext_mreg_supported(eth_dev) && 1435 priv->sh->dv_regc0_mask) { 1436 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1437 MLX5_FLOW_MREG_HTABLE_SZ); 1438 if (!priv->mreg_cp_tbl) { 1439 err = ENOMEM; 1440 goto error; 1441 } 1442 } 1443 return eth_dev; 1444 error: 1445 if (priv) { 1446 if (priv->mreg_cp_tbl) 1447 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL); 1448 if (priv->sh) 1449 mlx5_os_free_shared_dr(priv); 1450 if (priv->nl_socket_route >= 0) 1451 close(priv->nl_socket_route); 1452 if (priv->nl_socket_rdma >= 0) 1453 close(priv->nl_socket_rdma); 1454 if (priv->vmwa_context) 1455 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1456 if (priv->qrss_id_pool) 1457 mlx5_flow_id_pool_release(priv->qrss_id_pool); 1458 if (own_domain_id) 1459 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1460 mlx5_free(priv); 1461 if (eth_dev != NULL) 1462 eth_dev->data->dev_private = NULL; 1463 } 1464 if (eth_dev != NULL) { 1465 /* mac_addrs must not be freed alone because part of 1466 * dev_private 1467 **/ 1468 eth_dev->data->mac_addrs = NULL; 1469 rte_eth_dev_release_port(eth_dev); 1470 } 1471 if (sh) 1472 mlx5_free_shared_dev_ctx(sh); 1473 MLX5_ASSERT(err > 0); 1474 rte_errno = err; 1475 return NULL; 1476 } 1477 1478 /** 1479 * Comparison callback to sort device data. 1480 * 1481 * This is meant to be used with qsort(). 1482 * 1483 * @param a[in] 1484 * Pointer to pointer to first data object. 1485 * @param b[in] 1486 * Pointer to pointer to second data object. 1487 * 1488 * @return 1489 * 0 if both objects are equal, less than 0 if the first argument is less 1490 * than the second, greater than 0 otherwise. 1491 */ 1492 static int 1493 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1494 { 1495 const struct mlx5_switch_info *si_a = 1496 &((const struct mlx5_dev_spawn_data *)a)->info; 1497 const struct mlx5_switch_info *si_b = 1498 &((const struct mlx5_dev_spawn_data *)b)->info; 1499 int ret; 1500 1501 /* Master device first. */ 1502 ret = si_b->master - si_a->master; 1503 if (ret) 1504 return ret; 1505 /* Then representor devices. */ 1506 ret = si_b->representor - si_a->representor; 1507 if (ret) 1508 return ret; 1509 /* Unidentified devices come last in no specific order. */ 1510 if (!si_a->representor) 1511 return 0; 1512 /* Order representors by name. */ 1513 return si_a->port_name - si_b->port_name; 1514 } 1515 1516 /** 1517 * Match PCI information for possible slaves of bonding device. 1518 * 1519 * @param[in] ibv_dev 1520 * Pointer to Infiniband device structure. 1521 * @param[in] pci_dev 1522 * Pointer to PCI device structure to match PCI address. 1523 * @param[in] nl_rdma 1524 * Netlink RDMA group socket handle. 1525 * 1526 * @return 1527 * negative value if no bonding device found, otherwise 1528 * positive index of slave PF in bonding. 1529 */ 1530 static int 1531 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1532 const struct rte_pci_device *pci_dev, 1533 int nl_rdma) 1534 { 1535 char ifname[IF_NAMESIZE + 1]; 1536 unsigned int ifindex; 1537 unsigned int np, i; 1538 FILE *file = NULL; 1539 int pf = -1; 1540 1541 /* 1542 * Try to get master device name. If something goes 1543 * wrong suppose the lack of kernel support and no 1544 * bonding devices. 1545 */ 1546 if (nl_rdma < 0) 1547 return -1; 1548 if (!strstr(ibv_dev->name, "bond")) 1549 return -1; 1550 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1551 if (!np) 1552 return -1; 1553 /* 1554 * The Master device might not be on the predefined 1555 * port (not on port index 1, it is not garanted), 1556 * we have to scan all Infiniband device port and 1557 * find master. 1558 */ 1559 for (i = 1; i <= np; ++i) { 1560 /* Check whether Infiniband port is populated. */ 1561 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1562 if (!ifindex) 1563 continue; 1564 if (!if_indextoname(ifindex, ifname)) 1565 continue; 1566 /* Try to read bonding slave names from sysfs. */ 1567 MKSTR(slaves, 1568 "/sys/class/net/%s/master/bonding/slaves", ifname); 1569 file = fopen(slaves, "r"); 1570 if (file) 1571 break; 1572 } 1573 if (!file) 1574 return -1; 1575 /* Use safe format to check maximal buffer length. */ 1576 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1577 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1578 char tmp_str[IF_NAMESIZE + 32]; 1579 struct rte_pci_addr pci_addr; 1580 struct mlx5_switch_info info; 1581 1582 /* Process slave interface names in the loop. */ 1583 snprintf(tmp_str, sizeof(tmp_str), 1584 "/sys/class/net/%s", ifname); 1585 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1586 DRV_LOG(WARNING, "can not get PCI address" 1587 " for netdev \"%s\"", ifname); 1588 continue; 1589 } 1590 if (pci_dev->addr.domain != pci_addr.domain || 1591 pci_dev->addr.bus != pci_addr.bus || 1592 pci_dev->addr.devid != pci_addr.devid || 1593 pci_dev->addr.function != pci_addr.function) 1594 continue; 1595 /* Slave interface PCI address match found. */ 1596 fclose(file); 1597 snprintf(tmp_str, sizeof(tmp_str), 1598 "/sys/class/net/%s/phys_port_name", ifname); 1599 file = fopen(tmp_str, "rb"); 1600 if (!file) 1601 break; 1602 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1603 if (fscanf(file, "%32s", tmp_str) == 1) 1604 mlx5_translate_port_name(tmp_str, &info); 1605 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 1606 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1607 pf = info.port_name; 1608 break; 1609 } 1610 if (file) 1611 fclose(file); 1612 return pf; 1613 } 1614 1615 /** 1616 * DPDK callback to register a PCI device. 1617 * 1618 * This function spawns Ethernet devices out of a given PCI device. 1619 * 1620 * @param[in] pci_drv 1621 * PCI driver structure (mlx5_driver). 1622 * @param[in] pci_dev 1623 * PCI device information. 1624 * 1625 * @return 1626 * 0 on success, a negative errno value otherwise and rte_errno is set. 1627 */ 1628 int 1629 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1630 struct rte_pci_device *pci_dev) 1631 { 1632 struct ibv_device **ibv_list; 1633 /* 1634 * Number of found IB Devices matching with requested PCI BDF. 1635 * nd != 1 means there are multiple IB devices over the same 1636 * PCI device and we have representors and master. 1637 */ 1638 unsigned int nd = 0; 1639 /* 1640 * Number of found IB device Ports. nd = 1 and np = 1..n means 1641 * we have the single multiport IB device, and there may be 1642 * representors attached to some of found ports. 1643 */ 1644 unsigned int np = 0; 1645 /* 1646 * Number of DPDK ethernet devices to Spawn - either over 1647 * multiple IB devices or multiple ports of single IB device. 1648 * Actually this is the number of iterations to spawn. 1649 */ 1650 unsigned int ns = 0; 1651 /* 1652 * Bonding device 1653 * < 0 - no bonding device (single one) 1654 * >= 0 - bonding device (value is slave PF index) 1655 */ 1656 int bd = -1; 1657 struct mlx5_dev_spawn_data *list = NULL; 1658 struct mlx5_dev_config dev_config; 1659 unsigned int dev_config_vf; 1660 int ret; 1661 1662 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1663 mlx5_pmd_socket_init(); 1664 ret = mlx5_init_once(); 1665 if (ret) { 1666 DRV_LOG(ERR, "unable to init PMD global data: %s", 1667 strerror(rte_errno)); 1668 return -rte_errno; 1669 } 1670 errno = 0; 1671 ibv_list = mlx5_glue->get_device_list(&ret); 1672 if (!ibv_list) { 1673 rte_errno = errno ? errno : ENOSYS; 1674 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1675 return -rte_errno; 1676 } 1677 /* 1678 * First scan the list of all Infiniband devices to find 1679 * matching ones, gathering into the list. 1680 */ 1681 struct ibv_device *ibv_match[ret + 1]; 1682 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1683 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1684 unsigned int i; 1685 1686 while (ret-- > 0) { 1687 struct rte_pci_addr pci_addr; 1688 1689 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1690 bd = mlx5_device_bond_pci_match 1691 (ibv_list[ret], pci_dev, nl_rdma); 1692 if (bd >= 0) { 1693 /* 1694 * Bonding device detected. Only one match is allowed, 1695 * the bonding is supported over multi-port IB device, 1696 * there should be no matches on representor PCI 1697 * functions or non VF LAG bonding devices with 1698 * specified address. 1699 */ 1700 if (nd) { 1701 DRV_LOG(ERR, 1702 "multiple PCI match on bonding device" 1703 "\"%s\" found", ibv_list[ret]->name); 1704 rte_errno = ENOENT; 1705 ret = -rte_errno; 1706 goto exit; 1707 } 1708 DRV_LOG(INFO, "PCI information matches for" 1709 " slave %d bonding device \"%s\"", 1710 bd, ibv_list[ret]->name); 1711 ibv_match[nd++] = ibv_list[ret]; 1712 break; 1713 } 1714 if (mlx5_dev_to_pci_addr 1715 (ibv_list[ret]->ibdev_path, &pci_addr)) 1716 continue; 1717 if (pci_dev->addr.domain != pci_addr.domain || 1718 pci_dev->addr.bus != pci_addr.bus || 1719 pci_dev->addr.devid != pci_addr.devid || 1720 pci_dev->addr.function != pci_addr.function) 1721 continue; 1722 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1723 ibv_list[ret]->name); 1724 ibv_match[nd++] = ibv_list[ret]; 1725 } 1726 ibv_match[nd] = NULL; 1727 if (!nd) { 1728 /* No device matches, just complain and bail out. */ 1729 DRV_LOG(WARNING, 1730 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1731 " are kernel drivers loaded?", 1732 pci_dev->addr.domain, pci_dev->addr.bus, 1733 pci_dev->addr.devid, pci_dev->addr.function); 1734 rte_errno = ENOENT; 1735 ret = -rte_errno; 1736 goto exit; 1737 } 1738 if (nd == 1) { 1739 /* 1740 * Found single matching device may have multiple ports. 1741 * Each port may be representor, we have to check the port 1742 * number and check the representors existence. 1743 */ 1744 if (nl_rdma >= 0) 1745 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1746 if (!np) 1747 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1748 " ports number", ibv_match[0]->name); 1749 if (bd >= 0 && !np) { 1750 DRV_LOG(ERR, "can not get ports" 1751 " for bonding device"); 1752 rte_errno = ENOENT; 1753 ret = -rte_errno; 1754 goto exit; 1755 } 1756 } 1757 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 1758 if (bd >= 0) { 1759 /* 1760 * This may happen if there is VF LAG kernel support and 1761 * application is compiled with older rdma_core library. 1762 */ 1763 DRV_LOG(ERR, 1764 "No kernel/verbs support for VF LAG bonding found."); 1765 rte_errno = ENOTSUP; 1766 ret = -rte_errno; 1767 goto exit; 1768 } 1769 #endif 1770 /* 1771 * Now we can determine the maximal 1772 * amount of devices to be spawned. 1773 */ 1774 list = mlx5_malloc(MLX5_MEM_ZERO, 1775 sizeof(struct mlx5_dev_spawn_data) * 1776 (np ? np : nd), 1777 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1778 if (!list) { 1779 DRV_LOG(ERR, "spawn data array allocation failure"); 1780 rte_errno = ENOMEM; 1781 ret = -rte_errno; 1782 goto exit; 1783 } 1784 if (bd >= 0 || np > 1) { 1785 /* 1786 * Single IB device with multiple ports found, 1787 * it may be E-Switch master device and representors. 1788 * We have to perform identification through the ports. 1789 */ 1790 MLX5_ASSERT(nl_rdma >= 0); 1791 MLX5_ASSERT(ns == 0); 1792 MLX5_ASSERT(nd == 1); 1793 MLX5_ASSERT(np); 1794 for (i = 1; i <= np; ++i) { 1795 list[ns].max_port = np; 1796 list[ns].phys_port = i; 1797 list[ns].phys_dev = ibv_match[0]; 1798 list[ns].eth_dev = NULL; 1799 list[ns].pci_dev = pci_dev; 1800 list[ns].pf_bond = bd; 1801 list[ns].ifindex = mlx5_nl_ifindex 1802 (nl_rdma, 1803 mlx5_os_get_dev_device_name 1804 (list[ns].phys_dev), i); 1805 if (!list[ns].ifindex) { 1806 /* 1807 * No network interface index found for the 1808 * specified port, it means there is no 1809 * representor on this port. It's OK, 1810 * there can be disabled ports, for example 1811 * if sriov_numvfs < sriov_totalvfs. 1812 */ 1813 continue; 1814 } 1815 ret = -1; 1816 if (nl_route >= 0) 1817 ret = mlx5_nl_switch_info 1818 (nl_route, 1819 list[ns].ifindex, 1820 &list[ns].info); 1821 if (ret || (!list[ns].info.representor && 1822 !list[ns].info.master)) { 1823 /* 1824 * We failed to recognize representors with 1825 * Netlink, let's try to perform the task 1826 * with sysfs. 1827 */ 1828 ret = mlx5_sysfs_switch_info 1829 (list[ns].ifindex, 1830 &list[ns].info); 1831 } 1832 if (!ret && bd >= 0) { 1833 switch (list[ns].info.name_type) { 1834 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 1835 if (list[ns].info.port_name == bd) 1836 ns++; 1837 break; 1838 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 1839 /* Fallthrough */ 1840 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 1841 if (list[ns].info.pf_num == bd) 1842 ns++; 1843 break; 1844 default: 1845 break; 1846 } 1847 continue; 1848 } 1849 if (!ret && (list[ns].info.representor ^ 1850 list[ns].info.master)) 1851 ns++; 1852 } 1853 if (!ns) { 1854 DRV_LOG(ERR, 1855 "unable to recognize master/representors" 1856 " on the IB device with multiple ports"); 1857 rte_errno = ENOENT; 1858 ret = -rte_errno; 1859 goto exit; 1860 } 1861 } else { 1862 /* 1863 * The existence of several matching entries (nd > 1) means 1864 * port representors have been instantiated. No existing Verbs 1865 * call nor sysfs entries can tell them apart, this can only 1866 * be done through Netlink calls assuming kernel drivers are 1867 * recent enough to support them. 1868 * 1869 * In the event of identification failure through Netlink, 1870 * try again through sysfs, then: 1871 * 1872 * 1. A single IB device matches (nd == 1) with single 1873 * port (np=0/1) and is not a representor, assume 1874 * no switch support. 1875 * 1876 * 2. Otherwise no safe assumptions can be made; 1877 * complain louder and bail out. 1878 */ 1879 for (i = 0; i != nd; ++i) { 1880 memset(&list[ns].info, 0, sizeof(list[ns].info)); 1881 list[ns].max_port = 1; 1882 list[ns].phys_port = 1; 1883 list[ns].phys_dev = ibv_match[i]; 1884 list[ns].eth_dev = NULL; 1885 list[ns].pci_dev = pci_dev; 1886 list[ns].pf_bond = -1; 1887 list[ns].ifindex = 0; 1888 if (nl_rdma >= 0) 1889 list[ns].ifindex = mlx5_nl_ifindex 1890 (nl_rdma, 1891 mlx5_os_get_dev_device_name 1892 (list[ns].phys_dev), 1); 1893 if (!list[ns].ifindex) { 1894 char ifname[IF_NAMESIZE]; 1895 1896 /* 1897 * Netlink failed, it may happen with old 1898 * ib_core kernel driver (before 4.16). 1899 * We can assume there is old driver because 1900 * here we are processing single ports IB 1901 * devices. Let's try sysfs to retrieve 1902 * the ifindex. The method works for 1903 * master device only. 1904 */ 1905 if (nd > 1) { 1906 /* 1907 * Multiple devices found, assume 1908 * representors, can not distinguish 1909 * master/representor and retrieve 1910 * ifindex via sysfs. 1911 */ 1912 continue; 1913 } 1914 ret = mlx5_get_ifname_sysfs 1915 (ibv_match[i]->ibdev_path, ifname); 1916 if (!ret) 1917 list[ns].ifindex = 1918 if_nametoindex(ifname); 1919 if (!list[ns].ifindex) { 1920 /* 1921 * No network interface index found 1922 * for the specified device, it means 1923 * there it is neither representor 1924 * nor master. 1925 */ 1926 continue; 1927 } 1928 } 1929 ret = -1; 1930 if (nl_route >= 0) 1931 ret = mlx5_nl_switch_info 1932 (nl_route, 1933 list[ns].ifindex, 1934 &list[ns].info); 1935 if (ret || (!list[ns].info.representor && 1936 !list[ns].info.master)) { 1937 /* 1938 * We failed to recognize representors with 1939 * Netlink, let's try to perform the task 1940 * with sysfs. 1941 */ 1942 ret = mlx5_sysfs_switch_info 1943 (list[ns].ifindex, 1944 &list[ns].info); 1945 } 1946 if (!ret && (list[ns].info.representor ^ 1947 list[ns].info.master)) { 1948 ns++; 1949 } else if ((nd == 1) && 1950 !list[ns].info.representor && 1951 !list[ns].info.master) { 1952 /* 1953 * Single IB device with 1954 * one physical port and 1955 * attached network device. 1956 * May be SRIOV is not enabled 1957 * or there is no representors. 1958 */ 1959 DRV_LOG(INFO, "no E-Switch support detected"); 1960 ns++; 1961 break; 1962 } 1963 } 1964 if (!ns) { 1965 DRV_LOG(ERR, 1966 "unable to recognize master/representors" 1967 " on the multiple IB devices"); 1968 rte_errno = ENOENT; 1969 ret = -rte_errno; 1970 goto exit; 1971 } 1972 } 1973 MLX5_ASSERT(ns); 1974 /* 1975 * Sort list to probe devices in natural order for users convenience 1976 * (i.e. master first, then representors from lowest to highest ID). 1977 */ 1978 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 1979 /* Device specific configuration. */ 1980 switch (pci_dev->id.device_id) { 1981 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1982 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1983 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1984 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1985 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 1986 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 1987 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF: 1988 dev_config_vf = 1; 1989 break; 1990 default: 1991 dev_config_vf = 0; 1992 break; 1993 } 1994 for (i = 0; i != ns; ++i) { 1995 uint32_t restore; 1996 1997 /* Default configuration. */ 1998 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 1999 dev_config.vf = dev_config_vf; 2000 dev_config.mps = MLX5_ARG_UNSET; 2001 dev_config.dbnc = MLX5_ARG_UNSET; 2002 dev_config.rx_vec_en = 1; 2003 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2004 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2005 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2006 dev_config.txqs_inline = MLX5_ARG_UNSET; 2007 dev_config.vf_nl_en = 1; 2008 dev_config.mr_ext_memseg_en = 1; 2009 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2010 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2011 dev_config.dv_esw_en = 1; 2012 dev_config.dv_flow_en = 1; 2013 dev_config.decap_en = 1; 2014 dev_config.log_hp_size = MLX5_ARG_UNSET; 2015 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2016 &list[i], 2017 &dev_config); 2018 if (!list[i].eth_dev) { 2019 if (rte_errno != EBUSY && rte_errno != EEXIST) 2020 break; 2021 /* Device is disabled or already spawned. Ignore it. */ 2022 continue; 2023 } 2024 restore = list[i].eth_dev->data->dev_flags; 2025 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2026 /* Restore non-PCI flags cleared by the above call. */ 2027 list[i].eth_dev->data->dev_flags |= restore; 2028 rte_eth_dev_probing_finish(list[i].eth_dev); 2029 } 2030 if (i != ns) { 2031 DRV_LOG(ERR, 2032 "probe of PCI device " PCI_PRI_FMT " aborted after" 2033 " encountering an error: %s", 2034 pci_dev->addr.domain, pci_dev->addr.bus, 2035 pci_dev->addr.devid, pci_dev->addr.function, 2036 strerror(rte_errno)); 2037 ret = -rte_errno; 2038 /* Roll back. */ 2039 while (i--) { 2040 if (!list[i].eth_dev) 2041 continue; 2042 mlx5_dev_close(list[i].eth_dev); 2043 /* mac_addrs must not be freed because in dev_private */ 2044 list[i].eth_dev->data->mac_addrs = NULL; 2045 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2046 } 2047 /* Restore original error. */ 2048 rte_errno = -ret; 2049 } else { 2050 ret = 0; 2051 } 2052 exit: 2053 /* 2054 * Do the routine cleanup: 2055 * - close opened Netlink sockets 2056 * - free allocated spawn data array 2057 * - free the Infiniband device list 2058 */ 2059 if (nl_rdma >= 0) 2060 close(nl_rdma); 2061 if (nl_route >= 0) 2062 close(nl_route); 2063 if (list) 2064 mlx5_free(list); 2065 MLX5_ASSERT(ibv_list); 2066 mlx5_glue->free_device_list(ibv_list); 2067 return ret; 2068 } 2069 2070 static int 2071 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2072 { 2073 char *env; 2074 int value; 2075 2076 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2077 /* Get environment variable to store. */ 2078 env = getenv(MLX5_SHUT_UP_BF); 2079 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2080 if (config->dbnc == MLX5_ARG_UNSET) 2081 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2082 else 2083 setenv(MLX5_SHUT_UP_BF, 2084 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2085 return value; 2086 } 2087 2088 static void 2089 mlx5_restore_doorbell_mapping_env(int value) 2090 { 2091 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2092 /* Restore the original environment variable state. */ 2093 if (value == MLX5_ARG_UNSET) 2094 unsetenv(MLX5_SHUT_UP_BF); 2095 else 2096 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2097 } 2098 2099 /** 2100 * Extract pdn of PD object using DV API. 2101 * 2102 * @param[in] pd 2103 * Pointer to the verbs PD object. 2104 * @param[out] pdn 2105 * Pointer to the PD object number variable. 2106 * 2107 * @return 2108 * 0 on success, error value otherwise. 2109 */ 2110 int 2111 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2112 { 2113 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2114 struct mlx5dv_obj obj; 2115 struct mlx5dv_pd pd_info; 2116 int ret = 0; 2117 2118 obj.pd.in = pd; 2119 obj.pd.out = &pd_info; 2120 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2121 if (ret) { 2122 DRV_LOG(DEBUG, "Fail to get PD object info"); 2123 return ret; 2124 } 2125 *pdn = pd_info.pdn; 2126 return 0; 2127 #else 2128 (void)pd; 2129 (void)pdn; 2130 return -ENOTSUP; 2131 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2132 } 2133 2134 /** 2135 * Function API to open IB device. 2136 * 2137 * This function calls the Linux glue APIs to open a device. 2138 * 2139 * @param[in] spawn 2140 * Pointer to the IB device attributes (name, port, etc). 2141 * @param[out] config 2142 * Pointer to device configuration structure. 2143 * @param[out] sh 2144 * Pointer to shared context structure. 2145 * 2146 * @return 2147 * 0 on success, a positive error value otherwise. 2148 */ 2149 int 2150 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2151 const struct mlx5_dev_config *config, 2152 struct mlx5_dev_ctx_shared *sh) 2153 { 2154 int dbmap_env; 2155 int err = 0; 2156 2157 sh->numa_node = spawn->pci_dev->device.numa_node; 2158 pthread_mutex_init(&sh->txpp.mutex, NULL); 2159 /* 2160 * Configure environment variable "MLX5_BF_SHUT_UP" 2161 * before the device creation. The rdma_core library 2162 * checks the variable at device creation and 2163 * stores the result internally. 2164 */ 2165 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2166 /* Try to open IB device with DV first, then usual Verbs. */ 2167 errno = 0; 2168 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2169 if (sh->ctx) { 2170 sh->devx = 1; 2171 DRV_LOG(DEBUG, "DevX is supported"); 2172 /* The device is created, no need for environment. */ 2173 mlx5_restore_doorbell_mapping_env(dbmap_env); 2174 } else { 2175 /* The environment variable is still configured. */ 2176 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2177 err = errno ? errno : ENODEV; 2178 /* 2179 * The environment variable is not needed anymore, 2180 * all device creation attempts are completed. 2181 */ 2182 mlx5_restore_doorbell_mapping_env(dbmap_env); 2183 if (!sh->ctx) 2184 return err; 2185 DRV_LOG(DEBUG, "DevX is NOT supported"); 2186 err = 0; 2187 } 2188 return err; 2189 } 2190 2191 /** 2192 * Install shared asynchronous device events handler. 2193 * This function is implemented to support event sharing 2194 * between multiple ports of single IB device. 2195 * 2196 * @param sh 2197 * Pointer to mlx5_dev_ctx_shared object. 2198 */ 2199 void 2200 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2201 { 2202 int ret; 2203 int flags; 2204 2205 sh->intr_handle.fd = -1; 2206 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2207 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2208 F_SETFL, flags | O_NONBLOCK); 2209 if (ret) { 2210 DRV_LOG(INFO, "failed to change file descriptor async event" 2211 " queue"); 2212 } else { 2213 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2214 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2215 if (rte_intr_callback_register(&sh->intr_handle, 2216 mlx5_dev_interrupt_handler, sh)) { 2217 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2218 sh->intr_handle.fd = -1; 2219 } 2220 } 2221 if (sh->devx) { 2222 #ifdef HAVE_IBV_DEVX_ASYNC 2223 sh->intr_handle_devx.fd = -1; 2224 sh->devx_comp = 2225 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2226 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2227 if (!devx_comp) { 2228 DRV_LOG(INFO, "failed to allocate devx_comp."); 2229 return; 2230 } 2231 flags = fcntl(devx_comp->fd, F_GETFL); 2232 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2233 if (ret) { 2234 DRV_LOG(INFO, "failed to change file descriptor" 2235 " devx comp"); 2236 return; 2237 } 2238 sh->intr_handle_devx.fd = devx_comp->fd; 2239 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2240 if (rte_intr_callback_register(&sh->intr_handle_devx, 2241 mlx5_dev_interrupt_handler_devx, sh)) { 2242 DRV_LOG(INFO, "Fail to install the devx shared" 2243 " interrupt."); 2244 sh->intr_handle_devx.fd = -1; 2245 } 2246 #endif /* HAVE_IBV_DEVX_ASYNC */ 2247 } 2248 } 2249 2250 /** 2251 * Uninstall shared asynchronous device events handler. 2252 * This function is implemented to support event sharing 2253 * between multiple ports of single IB device. 2254 * 2255 * @param dev 2256 * Pointer to mlx5_dev_ctx_shared object. 2257 */ 2258 void 2259 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2260 { 2261 if (sh->intr_handle.fd >= 0) 2262 mlx5_intr_callback_unregister(&sh->intr_handle, 2263 mlx5_dev_interrupt_handler, sh); 2264 #ifdef HAVE_IBV_DEVX_ASYNC 2265 if (sh->intr_handle_devx.fd >= 0) 2266 rte_intr_callback_unregister(&sh->intr_handle_devx, 2267 mlx5_dev_interrupt_handler_devx, sh); 2268 if (sh->devx_comp) 2269 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2270 #endif 2271 } 2272 2273 /** 2274 * Read statistics by a named counter. 2275 * 2276 * @param[in] priv 2277 * Pointer to the private device data structure. 2278 * @param[in] ctr_name 2279 * Pointer to the name of the statistic counter to read 2280 * @param[out] stat 2281 * Pointer to read statistic value. 2282 * @return 2283 * 0 on success and stat is valud, 1 if failed to read the value 2284 * rte_errno is set. 2285 * 2286 */ 2287 int 2288 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2289 uint64_t *stat) 2290 { 2291 int fd; 2292 2293 if (priv->sh) { 2294 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2295 priv->sh->ibdev_path, 2296 priv->dev_port, 2297 ctr_name); 2298 fd = open(path, O_RDONLY); 2299 /* 2300 * in switchdev the file location is not per port 2301 * but rather in <ibdev_path>/hw_counters/<file_name>. 2302 */ 2303 if (fd == -1) { 2304 MKSTR(path1, "%s/hw_counters/%s", 2305 priv->sh->ibdev_path, 2306 ctr_name); 2307 fd = open(path1, O_RDONLY); 2308 } 2309 if (fd != -1) { 2310 char buf[21] = {'\0'}; 2311 ssize_t n = read(fd, buf, sizeof(buf)); 2312 2313 close(fd); 2314 if (n != -1) { 2315 *stat = strtoull(buf, NULL, 10); 2316 return 0; 2317 } 2318 } 2319 } 2320 *stat = 0; 2321 return 1; 2322 } 2323 2324 /** 2325 * Set the reg_mr and dereg_mr call backs 2326 * 2327 * @param reg_mr_cb[out] 2328 * Pointer to reg_mr func 2329 * @param dereg_mr_cb[out] 2330 * Pointer to dereg_mr func 2331 * 2332 */ 2333 void 2334 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2335 mlx5_dereg_mr_t *dereg_mr_cb) 2336 { 2337 *reg_mr_cb = mlx5_verbs_ops.reg_mr; 2338 *dereg_mr_cb = mlx5_verbs_ops.dereg_mr; 2339 } 2340 2341 /** 2342 * Remove a MAC address from device 2343 * 2344 * @param dev 2345 * Pointer to Ethernet device structure. 2346 * @param index 2347 * MAC address index. 2348 */ 2349 void 2350 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2351 { 2352 struct mlx5_priv *priv = dev->data->dev_private; 2353 const int vf = priv->config.vf; 2354 2355 if (vf) 2356 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2357 mlx5_ifindex(dev), priv->mac_own, 2358 &dev->data->mac_addrs[index], index); 2359 } 2360 2361 /** 2362 * Adds a MAC address to the device 2363 * 2364 * @param dev 2365 * Pointer to Ethernet device structure. 2366 * @param mac_addr 2367 * MAC address to register. 2368 * @param index 2369 * MAC address index. 2370 * 2371 * @return 2372 * 0 on success, a negative errno value otherwise 2373 */ 2374 int 2375 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2376 uint32_t index) 2377 { 2378 struct mlx5_priv *priv = dev->data->dev_private; 2379 const int vf = priv->config.vf; 2380 int ret = 0; 2381 2382 if (vf) 2383 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2384 mlx5_ifindex(dev), priv->mac_own, 2385 mac, index); 2386 return ret; 2387 } 2388 2389 /** 2390 * Modify a VF MAC address 2391 * 2392 * @param priv 2393 * Pointer to device private data. 2394 * @param mac_addr 2395 * MAC address to modify into. 2396 * @param iface_idx 2397 * Net device interface index 2398 * @param vf_index 2399 * VF index 2400 * 2401 * @return 2402 * 0 on success, a negative errno value otherwise 2403 */ 2404 int 2405 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2406 unsigned int iface_idx, 2407 struct rte_ether_addr *mac_addr, 2408 int vf_index) 2409 { 2410 return mlx5_nl_vf_mac_addr_modify 2411 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2412 } 2413 2414 /** 2415 * Set device promiscuous mode 2416 * 2417 * @param dev 2418 * Pointer to Ethernet device structure. 2419 * @param enable 2420 * 0 - promiscuous is disabled, otherwise - enabled 2421 * 2422 * @return 2423 * 0 on success, a negative error value otherwise 2424 */ 2425 int 2426 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2427 { 2428 struct mlx5_priv *priv = dev->data->dev_private; 2429 2430 return mlx5_nl_promisc(priv->nl_socket_route, 2431 mlx5_ifindex(dev), !!enable); 2432 } 2433 2434 /** 2435 * Set device promiscuous mode 2436 * 2437 * @param dev 2438 * Pointer to Ethernet device structure. 2439 * @param enable 2440 * 0 - all multicase is disabled, otherwise - enabled 2441 * 2442 * @return 2443 * 0 on success, a negative error value otherwise 2444 */ 2445 int 2446 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2447 { 2448 struct mlx5_priv *priv = dev->data->dev_private; 2449 2450 return mlx5_nl_allmulti(priv->nl_socket_route, 2451 mlx5_ifindex(dev), !!enable); 2452 } 2453 2454 /** 2455 * Flush device MAC addresses 2456 * 2457 * @param dev 2458 * Pointer to Ethernet device structure. 2459 * 2460 */ 2461 void 2462 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2463 { 2464 struct mlx5_priv *priv = dev->data->dev_private; 2465 2466 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2467 dev->data->mac_addrs, 2468 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2469 } 2470 2471 const struct eth_dev_ops mlx5_os_dev_ops = { 2472 .dev_configure = mlx5_dev_configure, 2473 .dev_start = mlx5_dev_start, 2474 .dev_stop = mlx5_dev_stop, 2475 .dev_set_link_down = mlx5_set_link_down, 2476 .dev_set_link_up = mlx5_set_link_up, 2477 .dev_close = mlx5_dev_close, 2478 .promiscuous_enable = mlx5_promiscuous_enable, 2479 .promiscuous_disable = mlx5_promiscuous_disable, 2480 .allmulticast_enable = mlx5_allmulticast_enable, 2481 .allmulticast_disable = mlx5_allmulticast_disable, 2482 .link_update = mlx5_link_update, 2483 .stats_get = mlx5_stats_get, 2484 .stats_reset = mlx5_stats_reset, 2485 .xstats_get = mlx5_xstats_get, 2486 .xstats_reset = mlx5_xstats_reset, 2487 .xstats_get_names = mlx5_xstats_get_names, 2488 .fw_version_get = mlx5_fw_version_get, 2489 .dev_infos_get = mlx5_dev_infos_get, 2490 .read_clock = mlx5_txpp_read_clock, 2491 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2492 .vlan_filter_set = mlx5_vlan_filter_set, 2493 .rx_queue_setup = mlx5_rx_queue_setup, 2494 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2495 .tx_queue_setup = mlx5_tx_queue_setup, 2496 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2497 .rx_queue_release = mlx5_rx_queue_release, 2498 .tx_queue_release = mlx5_tx_queue_release, 2499 .rx_queue_start = mlx5_rx_queue_start, 2500 .rx_queue_stop = mlx5_rx_queue_stop, 2501 .tx_queue_start = mlx5_tx_queue_start, 2502 .tx_queue_stop = mlx5_tx_queue_stop, 2503 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2504 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2505 .mac_addr_remove = mlx5_mac_addr_remove, 2506 .mac_addr_add = mlx5_mac_addr_add, 2507 .mac_addr_set = mlx5_mac_addr_set, 2508 .set_mc_addr_list = mlx5_set_mc_addr_list, 2509 .mtu_set = mlx5_dev_set_mtu, 2510 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2511 .vlan_offload_set = mlx5_vlan_offload_set, 2512 .reta_update = mlx5_dev_rss_reta_update, 2513 .reta_query = mlx5_dev_rss_reta_query, 2514 .rss_hash_update = mlx5_rss_hash_update, 2515 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2516 .filter_ctrl = mlx5_dev_filter_ctrl, 2517 .rxq_info_get = mlx5_rxq_info_get, 2518 .txq_info_get = mlx5_txq_info_get, 2519 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2520 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2521 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2522 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2523 .is_removed = mlx5_is_removed, 2524 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2525 .get_module_info = mlx5_get_module_info, 2526 .get_module_eeprom = mlx5_get_module_eeprom, 2527 .hairpin_cap_get = mlx5_hairpin_cap_get, 2528 .mtr_ops_get = mlx5_flow_meter_ops_get, 2529 }; 2530 2531 /* Available operations from secondary process. */ 2532 const struct eth_dev_ops mlx5_os_dev_sec_ops = { 2533 .stats_get = mlx5_stats_get, 2534 .stats_reset = mlx5_stats_reset, 2535 .xstats_get = mlx5_xstats_get, 2536 .xstats_reset = mlx5_xstats_reset, 2537 .xstats_get_names = mlx5_xstats_get_names, 2538 .fw_version_get = mlx5_fw_version_get, 2539 .dev_infos_get = mlx5_dev_infos_get, 2540 .read_clock = mlx5_txpp_read_clock, 2541 .rx_queue_start = mlx5_rx_queue_start, 2542 .rx_queue_stop = mlx5_rx_queue_stop, 2543 .tx_queue_start = mlx5_tx_queue_start, 2544 .tx_queue_stop = mlx5_tx_queue_stop, 2545 .rxq_info_get = mlx5_rxq_info_get, 2546 .txq_info_get = mlx5_txq_info_get, 2547 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2548 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2549 .get_module_info = mlx5_get_module_info, 2550 .get_module_eeprom = mlx5_get_module_eeprom, 2551 }; 2552 2553 /* Available operations in flow isolated mode. */ 2554 const struct eth_dev_ops mlx5_os_dev_ops_isolate = { 2555 .dev_configure = mlx5_dev_configure, 2556 .dev_start = mlx5_dev_start, 2557 .dev_stop = mlx5_dev_stop, 2558 .dev_set_link_down = mlx5_set_link_down, 2559 .dev_set_link_up = mlx5_set_link_up, 2560 .dev_close = mlx5_dev_close, 2561 .promiscuous_enable = mlx5_promiscuous_enable, 2562 .promiscuous_disable = mlx5_promiscuous_disable, 2563 .allmulticast_enable = mlx5_allmulticast_enable, 2564 .allmulticast_disable = mlx5_allmulticast_disable, 2565 .link_update = mlx5_link_update, 2566 .stats_get = mlx5_stats_get, 2567 .stats_reset = mlx5_stats_reset, 2568 .xstats_get = mlx5_xstats_get, 2569 .xstats_reset = mlx5_xstats_reset, 2570 .xstats_get_names = mlx5_xstats_get_names, 2571 .fw_version_get = mlx5_fw_version_get, 2572 .dev_infos_get = mlx5_dev_infos_get, 2573 .read_clock = mlx5_txpp_read_clock, 2574 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2575 .vlan_filter_set = mlx5_vlan_filter_set, 2576 .rx_queue_setup = mlx5_rx_queue_setup, 2577 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2578 .tx_queue_setup = mlx5_tx_queue_setup, 2579 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2580 .rx_queue_release = mlx5_rx_queue_release, 2581 .tx_queue_release = mlx5_tx_queue_release, 2582 .rx_queue_start = mlx5_rx_queue_start, 2583 .rx_queue_stop = mlx5_rx_queue_stop, 2584 .tx_queue_start = mlx5_tx_queue_start, 2585 .tx_queue_stop = mlx5_tx_queue_stop, 2586 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2587 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2588 .mac_addr_remove = mlx5_mac_addr_remove, 2589 .mac_addr_add = mlx5_mac_addr_add, 2590 .mac_addr_set = mlx5_mac_addr_set, 2591 .set_mc_addr_list = mlx5_set_mc_addr_list, 2592 .mtu_set = mlx5_dev_set_mtu, 2593 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2594 .vlan_offload_set = mlx5_vlan_offload_set, 2595 .filter_ctrl = mlx5_dev_filter_ctrl, 2596 .rxq_info_get = mlx5_rxq_info_get, 2597 .txq_info_get = mlx5_txq_info_get, 2598 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2599 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2600 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2601 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2602 .is_removed = mlx5_is_removed, 2603 .get_module_info = mlx5_get_module_info, 2604 .get_module_eeprom = mlx5_get_module_eeprom, 2605 .hairpin_cap_get = mlx5_hairpin_cap_get, 2606 .mtr_ops_get = mlx5_flow_meter_ops_get, 2607 }; 2608