1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_mr.h" 48 #include "mlx5_flow.h" 49 #include "rte_pmd_mlx5.h" 50 #include "mlx5_verbs.h" 51 #include "mlx5_nl.h" 52 #include "mlx5_devx.h" 53 54 #ifndef HAVE_IBV_MLX5_MOD_MPW 55 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 56 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 57 #endif 58 59 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 60 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 61 #endif 62 63 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 64 65 /* Spinlock for mlx5_shared_data allocation. */ 66 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 67 68 /* Process local data for secondary processes. */ 69 static struct mlx5_local_data mlx5_local_data; 70 71 /* rte flow indexed pool configuration. */ 72 static struct mlx5_indexed_pool_config icfg[] = { 73 { 74 .size = sizeof(struct rte_flow), 75 .trunk_size = 64, 76 .need_lock = 1, 77 .release_mem_en = 0, 78 .malloc = mlx5_malloc, 79 .free = mlx5_free, 80 .per_core_cache = 0, 81 .type = "ctl_flow_ipool", 82 }, 83 { 84 .size = sizeof(struct rte_flow), 85 .trunk_size = 64, 86 .grow_trunk = 3, 87 .grow_shift = 2, 88 .need_lock = 1, 89 .release_mem_en = 0, 90 .malloc = mlx5_malloc, 91 .free = mlx5_free, 92 .per_core_cache = 1 << 14, 93 .type = "rte_flow_ipool", 94 }, 95 { 96 .size = sizeof(struct rte_flow), 97 .trunk_size = 64, 98 .grow_trunk = 3, 99 .grow_shift = 2, 100 .need_lock = 1, 101 .release_mem_en = 0, 102 .malloc = mlx5_malloc, 103 .free = mlx5_free, 104 .per_core_cache = 0, 105 .type = "mcp_flow_ipool", 106 }, 107 }; 108 109 /** 110 * Set the completion channel file descriptor interrupt as non-blocking. 111 * 112 * @param[in] rxq_obj 113 * Pointer to RQ channel object, which includes the channel fd 114 * 115 * @param[out] fd 116 * The file descriptor (representing the intetrrupt) used in this channel. 117 * 118 * @return 119 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 120 */ 121 int 122 mlx5_os_set_nonblock_channel_fd(int fd) 123 { 124 int flags; 125 126 flags = fcntl(fd, F_GETFL); 127 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 128 } 129 130 /** 131 * Get mlx5 device attributes. The glue function query_device_ex() is called 132 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 133 * device attributes from the glue out parameter. 134 * 135 * @param dev 136 * Pointer to ibv context. 137 * 138 * @param device_attr 139 * Pointer to mlx5 device attributes. 140 * 141 * @return 142 * 0 on success, non zero error number otherwise 143 */ 144 int 145 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 146 { 147 int err; 148 struct ibv_device_attr_ex attr_ex; 149 memset(device_attr, 0, sizeof(*device_attr)); 150 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 151 if (err) 152 return err; 153 154 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 155 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 156 device_attr->max_sge = attr_ex.orig_attr.max_sge; 157 device_attr->max_cq = attr_ex.orig_attr.max_cq; 158 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 159 device_attr->max_mr = attr_ex.orig_attr.max_mr; 160 device_attr->max_pd = attr_ex.orig_attr.max_pd; 161 device_attr->max_qp = attr_ex.orig_attr.max_qp; 162 device_attr->max_srq = attr_ex.orig_attr.max_srq; 163 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 164 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 165 device_attr->max_rwq_indirection_table_size = 166 attr_ex.rss_caps.max_rwq_indirection_table_size; 167 device_attr->max_tso = attr_ex.tso_caps.max_tso; 168 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 169 170 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 171 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 172 if (err) 173 return err; 174 175 device_attr->flags = dv_attr.flags; 176 device_attr->comp_mask = dv_attr.comp_mask; 177 #ifdef HAVE_IBV_MLX5_MOD_SWP 178 device_attr->sw_parsing_offloads = 179 dv_attr.sw_parsing_caps.sw_parsing_offloads; 180 #endif 181 device_attr->min_single_stride_log_num_of_bytes = 182 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 183 device_attr->max_single_stride_log_num_of_bytes = 184 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 185 device_attr->min_single_wqe_log_num_of_strides = 186 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 187 device_attr->max_single_wqe_log_num_of_strides = 188 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 189 device_attr->stride_supported_qpts = 190 dv_attr.striding_rq_caps.supported_qpts; 191 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 192 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 193 #endif 194 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 195 sizeof(device_attr->fw_ver)); 196 197 return err; 198 } 199 200 /** 201 * Verbs callback to allocate a memory. This function should allocate the space 202 * according to the size provided residing inside a huge page. 203 * Please note that all allocation must respect the alignment from libmlx5 204 * (i.e. currently rte_mem_page_size()). 205 * 206 * @param[in] size 207 * The size in bytes of the memory to allocate. 208 * @param[in] data 209 * A pointer to the callback data. 210 * 211 * @return 212 * Allocated buffer, NULL otherwise and rte_errno is set. 213 */ 214 static void * 215 mlx5_alloc_verbs_buf(size_t size, void *data) 216 { 217 struct mlx5_dev_ctx_shared *sh = data; 218 void *ret; 219 size_t alignment = rte_mem_page_size(); 220 if (alignment == (size_t)-1) { 221 DRV_LOG(ERR, "Failed to get mem page size"); 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 226 MLX5_ASSERT(data != NULL); 227 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 228 if (!ret && size) 229 rte_errno = ENOMEM; 230 return ret; 231 } 232 233 /** 234 * Detect misc5 support or not 235 * 236 * @param[in] priv 237 * Device private data pointer 238 */ 239 #ifdef HAVE_MLX5DV_DR 240 static void 241 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 242 { 243 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 244 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 245 * Case: IPv4--->UDP--->VxLAN--->vni 246 */ 247 void *tbl; 248 struct mlx5_flow_dv_match_params matcher_mask; 249 void *match_m; 250 void *matcher; 251 void *headers_m; 252 void *misc5_m; 253 uint32_t *tunnel_header_m; 254 struct mlx5dv_flow_matcher_attr dv_attr; 255 256 memset(&matcher_mask, 0, sizeof(matcher_mask)); 257 matcher_mask.size = sizeof(matcher_mask.buf); 258 match_m = matcher_mask.buf; 259 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 260 misc5_m = MLX5_ADDR_OF(fte_match_param, 261 match_m, misc_parameters_5); 262 tunnel_header_m = (uint32_t *) 263 MLX5_ADDR_OF(fte_match_set_misc5, 264 misc5_m, tunnel_header_1); 265 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 266 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 268 *tunnel_header_m = 0xffffff; 269 270 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 271 if (!tbl) { 272 DRV_LOG(INFO, "No SW steering support"); 273 return; 274 } 275 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 276 dv_attr.match_mask = (void *)&matcher_mask, 277 dv_attr.match_criteria_enable = 278 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 279 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 280 dv_attr.priority = 3; 281 #ifdef HAVE_MLX5DV_DR_ESWITCH 282 void *misc2_m; 283 if (priv->config.dv_esw_en) { 284 /* FDB enabled reg_c_0 */ 285 dv_attr.match_criteria_enable |= 286 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 287 misc2_m = MLX5_ADDR_OF(fte_match_param, 288 match_m, misc_parameters_2); 289 MLX5_SET(fte_match_set_misc2, misc2_m, 290 metadata_reg_c_0, 0xffff); 291 } 292 #endif 293 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->ctx, 294 &dv_attr, tbl); 295 if (matcher) { 296 priv->sh->misc5_cap = 1; 297 mlx5_glue->dv_destroy_flow_matcher(matcher); 298 } 299 mlx5_glue->dr_destroy_flow_tbl(tbl); 300 #else 301 RTE_SET_USED(priv); 302 #endif 303 } 304 #endif 305 306 /** 307 * Verbs callback to free a memory. 308 * 309 * @param[in] ptr 310 * A pointer to the memory to free. 311 * @param[in] data 312 * A pointer to the callback data. 313 */ 314 static void 315 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 316 { 317 MLX5_ASSERT(data != NULL); 318 mlx5_free(ptr); 319 } 320 321 /** 322 * Initialize DR related data within private structure. 323 * Routine checks the reference counter and does actual 324 * resources creation/initialization only if counter is zero. 325 * 326 * @param[in] priv 327 * Pointer to the private device data structure. 328 * 329 * @return 330 * Zero on success, positive error code otherwise. 331 */ 332 static int 333 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 334 { 335 struct mlx5_dev_ctx_shared *sh = priv->sh; 336 char s[MLX5_NAME_SIZE] __rte_unused; 337 int err; 338 339 MLX5_ASSERT(sh && sh->refcnt); 340 if (sh->refcnt > 1) 341 return 0; 342 err = mlx5_alloc_table_hash_list(priv); 343 if (err) 344 goto error; 345 /* The resources below are only valid with DV support. */ 346 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 347 /* Init port id action list. */ 348 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 349 sh->port_id_action_list = mlx5_list_create(s, sh, true, 350 flow_dv_port_id_create_cb, 351 flow_dv_port_id_match_cb, 352 flow_dv_port_id_remove_cb, 353 flow_dv_port_id_clone_cb, 354 flow_dv_port_id_clone_free_cb); 355 if (!sh->port_id_action_list) 356 goto error; 357 /* Init push vlan action list. */ 358 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 359 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 360 flow_dv_push_vlan_create_cb, 361 flow_dv_push_vlan_match_cb, 362 flow_dv_push_vlan_remove_cb, 363 flow_dv_push_vlan_clone_cb, 364 flow_dv_push_vlan_clone_free_cb); 365 if (!sh->push_vlan_action_list) 366 goto error; 367 /* Init sample action list. */ 368 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 369 sh->sample_action_list = mlx5_list_create(s, sh, true, 370 flow_dv_sample_create_cb, 371 flow_dv_sample_match_cb, 372 flow_dv_sample_remove_cb, 373 flow_dv_sample_clone_cb, 374 flow_dv_sample_clone_free_cb); 375 if (!sh->sample_action_list) 376 goto error; 377 /* Init dest array action list. */ 378 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 379 sh->dest_array_list = mlx5_list_create(s, sh, true, 380 flow_dv_dest_array_create_cb, 381 flow_dv_dest_array_match_cb, 382 flow_dv_dest_array_remove_cb, 383 flow_dv_dest_array_clone_cb, 384 flow_dv_dest_array_clone_free_cb); 385 if (!sh->dest_array_list) 386 goto error; 387 #endif 388 #ifdef HAVE_MLX5DV_DR 389 void *domain; 390 391 /* Reference counter is zero, we should initialize structures. */ 392 domain = mlx5_glue->dr_create_domain(sh->ctx, 393 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 394 if (!domain) { 395 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 396 err = errno; 397 goto error; 398 } 399 sh->rx_domain = domain; 400 domain = mlx5_glue->dr_create_domain(sh->ctx, 401 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 402 if (!domain) { 403 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 404 err = errno; 405 goto error; 406 } 407 sh->tx_domain = domain; 408 #ifdef HAVE_MLX5DV_DR_ESWITCH 409 if (priv->config.dv_esw_en) { 410 domain = mlx5_glue->dr_create_domain 411 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 412 if (!domain) { 413 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 414 err = errno; 415 goto error; 416 } 417 sh->fdb_domain = domain; 418 } 419 /* 420 * The drop action is just some dummy placeholder in rdma-core. It 421 * does not belong to domains and has no any attributes, and, can be 422 * shared by the entire device. 423 */ 424 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 425 if (!sh->dr_drop_action) { 426 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 427 err = errno; 428 goto error; 429 } 430 #endif 431 if (!sh->tunnel_hub && priv->config.dv_miss_info) 432 err = mlx5_alloc_tunnel_hub(sh); 433 if (err) { 434 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 435 goto error; 436 } 437 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 438 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 439 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 440 if (sh->fdb_domain) 441 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 442 } 443 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 444 if (!priv->config.allow_duplicate_pattern) { 445 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 446 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 447 #endif 448 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 449 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 450 if (sh->fdb_domain) 451 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 452 } 453 454 __mlx5_discovery_misc5_cap(priv); 455 #endif /* HAVE_MLX5DV_DR */ 456 sh->default_miss_action = 457 mlx5_glue->dr_create_flow_action_default_miss(); 458 if (!sh->default_miss_action) 459 DRV_LOG(WARNING, "Default miss action is not supported."); 460 return 0; 461 error: 462 /* Rollback the created objects. */ 463 if (sh->rx_domain) { 464 mlx5_glue->dr_destroy_domain(sh->rx_domain); 465 sh->rx_domain = NULL; 466 } 467 if (sh->tx_domain) { 468 mlx5_glue->dr_destroy_domain(sh->tx_domain); 469 sh->tx_domain = NULL; 470 } 471 if (sh->fdb_domain) { 472 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 473 sh->fdb_domain = NULL; 474 } 475 if (sh->dr_drop_action) { 476 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 477 sh->dr_drop_action = NULL; 478 } 479 if (sh->pop_vlan_action) { 480 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 481 sh->pop_vlan_action = NULL; 482 } 483 if (sh->encaps_decaps) { 484 mlx5_hlist_destroy(sh->encaps_decaps); 485 sh->encaps_decaps = NULL; 486 } 487 if (sh->modify_cmds) { 488 mlx5_hlist_destroy(sh->modify_cmds); 489 sh->modify_cmds = NULL; 490 } 491 if (sh->tag_table) { 492 /* tags should be destroyed with flow before. */ 493 mlx5_hlist_destroy(sh->tag_table); 494 sh->tag_table = NULL; 495 } 496 if (sh->tunnel_hub) { 497 mlx5_release_tunnel_hub(sh, priv->dev_port); 498 sh->tunnel_hub = NULL; 499 } 500 mlx5_free_table_hash_list(priv); 501 if (sh->port_id_action_list) { 502 mlx5_list_destroy(sh->port_id_action_list); 503 sh->port_id_action_list = NULL; 504 } 505 if (sh->push_vlan_action_list) { 506 mlx5_list_destroy(sh->push_vlan_action_list); 507 sh->push_vlan_action_list = NULL; 508 } 509 if (sh->sample_action_list) { 510 mlx5_list_destroy(sh->sample_action_list); 511 sh->sample_action_list = NULL; 512 } 513 if (sh->dest_array_list) { 514 mlx5_list_destroy(sh->dest_array_list); 515 sh->dest_array_list = NULL; 516 } 517 return err; 518 } 519 520 /** 521 * Destroy DR related data within private structure. 522 * 523 * @param[in] priv 524 * Pointer to the private device data structure. 525 */ 526 void 527 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 528 { 529 struct mlx5_dev_ctx_shared *sh = priv->sh; 530 531 MLX5_ASSERT(sh && sh->refcnt); 532 if (sh->refcnt > 1) 533 return; 534 #ifdef HAVE_MLX5DV_DR 535 if (sh->rx_domain) { 536 mlx5_glue->dr_destroy_domain(sh->rx_domain); 537 sh->rx_domain = NULL; 538 } 539 if (sh->tx_domain) { 540 mlx5_glue->dr_destroy_domain(sh->tx_domain); 541 sh->tx_domain = NULL; 542 } 543 #ifdef HAVE_MLX5DV_DR_ESWITCH 544 if (sh->fdb_domain) { 545 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 546 sh->fdb_domain = NULL; 547 } 548 if (sh->dr_drop_action) { 549 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 550 sh->dr_drop_action = NULL; 551 } 552 #endif 553 if (sh->pop_vlan_action) { 554 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 555 sh->pop_vlan_action = NULL; 556 } 557 #endif /* HAVE_MLX5DV_DR */ 558 if (sh->default_miss_action) 559 mlx5_glue->destroy_flow_action 560 (sh->default_miss_action); 561 if (sh->encaps_decaps) { 562 mlx5_hlist_destroy(sh->encaps_decaps); 563 sh->encaps_decaps = NULL; 564 } 565 if (sh->modify_cmds) { 566 mlx5_hlist_destroy(sh->modify_cmds); 567 sh->modify_cmds = NULL; 568 } 569 if (sh->tag_table) { 570 /* tags should be destroyed with flow before. */ 571 mlx5_hlist_destroy(sh->tag_table); 572 sh->tag_table = NULL; 573 } 574 if (sh->tunnel_hub) { 575 mlx5_release_tunnel_hub(sh, priv->dev_port); 576 sh->tunnel_hub = NULL; 577 } 578 mlx5_free_table_hash_list(priv); 579 if (sh->port_id_action_list) { 580 mlx5_list_destroy(sh->port_id_action_list); 581 sh->port_id_action_list = NULL; 582 } 583 if (sh->push_vlan_action_list) { 584 mlx5_list_destroy(sh->push_vlan_action_list); 585 sh->push_vlan_action_list = NULL; 586 } 587 if (sh->sample_action_list) { 588 mlx5_list_destroy(sh->sample_action_list); 589 sh->sample_action_list = NULL; 590 } 591 if (sh->dest_array_list) { 592 mlx5_list_destroy(sh->dest_array_list); 593 sh->dest_array_list = NULL; 594 } 595 } 596 597 /** 598 * Initialize shared data between primary and secondary process. 599 * 600 * A memzone is reserved by primary process and secondary processes attach to 601 * the memzone. 602 * 603 * @return 604 * 0 on success, a negative errno value otherwise and rte_errno is set. 605 */ 606 static int 607 mlx5_init_shared_data(void) 608 { 609 const struct rte_memzone *mz; 610 int ret = 0; 611 612 rte_spinlock_lock(&mlx5_shared_data_lock); 613 if (mlx5_shared_data == NULL) { 614 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 615 /* Allocate shared memory. */ 616 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 617 sizeof(*mlx5_shared_data), 618 SOCKET_ID_ANY, 0); 619 if (mz == NULL) { 620 DRV_LOG(ERR, 621 "Cannot allocate mlx5 shared data"); 622 ret = -rte_errno; 623 goto error; 624 } 625 mlx5_shared_data = mz->addr; 626 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 627 rte_spinlock_init(&mlx5_shared_data->lock); 628 } else { 629 /* Lookup allocated shared memory. */ 630 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 631 if (mz == NULL) { 632 DRV_LOG(ERR, 633 "Cannot attach mlx5 shared data"); 634 ret = -rte_errno; 635 goto error; 636 } 637 mlx5_shared_data = mz->addr; 638 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 639 } 640 } 641 error: 642 rte_spinlock_unlock(&mlx5_shared_data_lock); 643 return ret; 644 } 645 646 /** 647 * PMD global initialization. 648 * 649 * Independent from individual device, this function initializes global 650 * per-PMD data structures distinguishing primary and secondary processes. 651 * Hence, each initialization is called once per a process. 652 * 653 * @return 654 * 0 on success, a negative errno value otherwise and rte_errno is set. 655 */ 656 static int 657 mlx5_init_once(void) 658 { 659 struct mlx5_shared_data *sd; 660 struct mlx5_local_data *ld = &mlx5_local_data; 661 int ret = 0; 662 663 if (mlx5_init_shared_data()) 664 return -rte_errno; 665 sd = mlx5_shared_data; 666 MLX5_ASSERT(sd); 667 rte_spinlock_lock(&sd->lock); 668 switch (rte_eal_process_type()) { 669 case RTE_PROC_PRIMARY: 670 if (sd->init_done) 671 break; 672 LIST_INIT(&sd->mem_event_cb_list); 673 rte_rwlock_init(&sd->mem_event_rwlock); 674 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 675 mlx5_mr_mem_event_cb, NULL); 676 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 677 mlx5_mp_os_primary_handle); 678 if (ret) 679 goto out; 680 sd->init_done = true; 681 break; 682 case RTE_PROC_SECONDARY: 683 if (ld->init_done) 684 break; 685 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 686 mlx5_mp_os_secondary_handle); 687 if (ret) 688 goto out; 689 ++sd->secondary_cnt; 690 ld->init_done = true; 691 break; 692 default: 693 break; 694 } 695 out: 696 rte_spinlock_unlock(&sd->lock); 697 return ret; 698 } 699 700 /** 701 * Create the Tx queue DevX/Verbs object. 702 * 703 * @param dev 704 * Pointer to Ethernet device. 705 * @param idx 706 * Queue index in DPDK Tx queue array. 707 * 708 * @return 709 * 0 on success, a negative errno value otherwise and rte_errno is set. 710 */ 711 static int 712 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 713 { 714 struct mlx5_priv *priv = dev->data->dev_private; 715 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 716 struct mlx5_txq_ctrl *txq_ctrl = 717 container_of(txq_data, struct mlx5_txq_ctrl, txq); 718 719 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 720 return mlx5_txq_devx_obj_new(dev, idx); 721 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 722 if (!priv->config.dv_esw_en) 723 return mlx5_txq_devx_obj_new(dev, idx); 724 #endif 725 return mlx5_txq_ibv_obj_new(dev, idx); 726 } 727 728 /** 729 * Release an Tx DevX/verbs queue object. 730 * 731 * @param txq_obj 732 * DevX/Verbs Tx queue object. 733 */ 734 static void 735 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 736 { 737 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 738 mlx5_txq_devx_obj_release(txq_obj); 739 return; 740 } 741 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 742 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 743 mlx5_txq_devx_obj_release(txq_obj); 744 return; 745 } 746 #endif 747 mlx5_txq_ibv_obj_release(txq_obj); 748 } 749 750 /** 751 * DV flow counter mode detect and config. 752 * 753 * @param dev 754 * Pointer to rte_eth_dev structure. 755 * 756 */ 757 static void 758 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 759 { 760 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 761 struct mlx5_priv *priv = dev->data->dev_private; 762 struct mlx5_dev_ctx_shared *sh = priv->sh; 763 bool fallback; 764 765 #ifndef HAVE_IBV_DEVX_ASYNC 766 fallback = true; 767 #else 768 fallback = false; 769 if (!priv->config.devx || !priv->config.dv_flow_en || 770 !priv->config.hca_attr.flow_counters_dump || 771 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 772 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 773 fallback = true; 774 #endif 775 if (fallback) 776 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 777 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 778 priv->config.hca_attr.flow_counters_dump, 779 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 780 /* Initialize fallback mode only on the port initializes sh. */ 781 if (sh->refcnt == 1) 782 sh->cmng.counter_fallback = fallback; 783 else if (fallback != sh->cmng.counter_fallback) 784 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 785 "with others:%d.", PORT_ID(priv), fallback); 786 #endif 787 } 788 789 /** 790 * DR flow drop action support detect. 791 * 792 * @param dev 793 * Pointer to rte_eth_dev structure. 794 * 795 */ 796 static void 797 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 798 { 799 #ifdef HAVE_MLX5DV_DR 800 struct mlx5_priv *priv = dev->data->dev_private; 801 802 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action) 803 return; 804 /** 805 * DR supports drop action placeholder when it is supported; 806 * otherwise, use the queue drop action. 807 */ 808 if (mlx5_flow_discover_dr_action_support(dev)) 809 priv->root_drop_action = priv->drop_queue.hrxq->action; 810 else 811 priv->root_drop_action = priv->sh->dr_drop_action; 812 #endif 813 } 814 815 static void 816 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 817 { 818 struct mlx5_priv *priv = dev->data->dev_private; 819 void *ctx = priv->sh->ctx; 820 821 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 822 if (!priv->q_counters) { 823 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 824 struct ibv_wq *wq; 825 826 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 827 "by DevX - fall-back to use the kernel driver global " 828 "queue counter.", dev->data->port_id); 829 /* Create WQ by kernel and query its queue counter ID. */ 830 if (cq) { 831 wq = mlx5_glue->create_wq(ctx, 832 &(struct ibv_wq_init_attr){ 833 .wq_type = IBV_WQT_RQ, 834 .max_wr = 1, 835 .max_sge = 1, 836 .pd = priv->sh->pd, 837 .cq = cq, 838 }); 839 if (wq) { 840 /* Counter is assigned only on RDY state. */ 841 int ret = mlx5_glue->modify_wq(wq, 842 &(struct ibv_wq_attr){ 843 .attr_mask = IBV_WQ_ATTR_STATE, 844 .wq_state = IBV_WQS_RDY, 845 }); 846 847 if (ret == 0) 848 mlx5_devx_cmd_wq_query(wq, 849 &priv->counter_set_id); 850 claim_zero(mlx5_glue->destroy_wq(wq)); 851 } 852 claim_zero(mlx5_glue->destroy_cq(cq)); 853 } 854 } else { 855 priv->counter_set_id = priv->q_counters->id; 856 } 857 if (priv->counter_set_id == 0) 858 DRV_LOG(INFO, "Part of the port %d statistics will not be " 859 "available.", dev->data->port_id); 860 } 861 862 /** 863 * Check if representor spawn info match devargs. 864 * 865 * @param spawn 866 * Verbs device parameters (name, port, switch_info) to spawn. 867 * @param eth_da 868 * Device devargs to probe. 869 * 870 * @return 871 * Match result. 872 */ 873 static bool 874 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 875 struct rte_eth_devargs *eth_da) 876 { 877 struct mlx5_switch_info *switch_info = &spawn->info; 878 unsigned int p, f; 879 uint16_t id; 880 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 881 eth_da->type); 882 883 switch (eth_da->type) { 884 case RTE_ETH_REPRESENTOR_SF: 885 if (!(spawn->info.port_name == -1 && 886 switch_info->name_type == 887 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 888 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 889 rte_errno = EBUSY; 890 return false; 891 } 892 break; 893 case RTE_ETH_REPRESENTOR_VF: 894 /* Allows HPF representor index -1 as exception. */ 895 if (!(spawn->info.port_name == -1 && 896 switch_info->name_type == 897 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 898 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 899 rte_errno = EBUSY; 900 return false; 901 } 902 break; 903 case RTE_ETH_REPRESENTOR_NONE: 904 rte_errno = EBUSY; 905 return false; 906 default: 907 rte_errno = ENOTSUP; 908 DRV_LOG(ERR, "unsupported representor type"); 909 return false; 910 } 911 /* Check representor ID: */ 912 for (p = 0; p < eth_da->nb_ports; ++p) { 913 if (spawn->pf_bond < 0) { 914 /* For non-LAG mode, allow and ignore pf. */ 915 switch_info->pf_num = eth_da->ports[p]; 916 repr_id = mlx5_representor_id_encode(switch_info, 917 eth_da->type); 918 } 919 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 920 id = MLX5_REPRESENTOR_ID 921 (eth_da->ports[p], eth_da->type, 922 eth_da->representor_ports[f]); 923 if (repr_id == id) 924 return true; 925 } 926 } 927 rte_errno = EBUSY; 928 return false; 929 } 930 931 932 /** 933 * Spawn an Ethernet device from Verbs information. 934 * 935 * @param dpdk_dev 936 * Backing DPDK device. 937 * @param spawn 938 * Verbs device parameters (name, port, switch_info) to spawn. 939 * @param config 940 * Device configuration parameters. 941 * @param config 942 * Device arguments. 943 * 944 * @return 945 * A valid Ethernet device object on success, NULL otherwise and rte_errno 946 * is set. The following errors are defined: 947 * 948 * EBUSY: device is not supposed to be spawned. 949 * EEXIST: device is already spawned 950 */ 951 static struct rte_eth_dev * 952 mlx5_dev_spawn(struct rte_device *dpdk_dev, 953 struct mlx5_dev_spawn_data *spawn, 954 struct mlx5_dev_config *config, 955 struct rte_eth_devargs *eth_da) 956 { 957 const struct mlx5_switch_info *switch_info = &spawn->info; 958 struct mlx5_dev_ctx_shared *sh = NULL; 959 struct ibv_port_attr port_attr; 960 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 961 struct rte_eth_dev *eth_dev = NULL; 962 struct mlx5_priv *priv = NULL; 963 int err = 0; 964 unsigned int hw_padding = 0; 965 unsigned int mps; 966 unsigned int tunnel_en = 0; 967 unsigned int mpls_en = 0; 968 unsigned int swp = 0; 969 unsigned int mprq = 0; 970 unsigned int mprq_min_stride_size_n = 0; 971 unsigned int mprq_max_stride_size_n = 0; 972 unsigned int mprq_min_stride_num_n = 0; 973 unsigned int mprq_max_stride_num_n = 0; 974 struct rte_ether_addr mac; 975 char name[RTE_ETH_NAME_MAX_LEN]; 976 int own_domain_id = 0; 977 uint16_t port_id; 978 struct mlx5_port_info vport_info = { .query_flags = 0 }; 979 int i; 980 981 /* Determine if this port representor is supposed to be spawned. */ 982 if (switch_info->representor && dpdk_dev->devargs && 983 !mlx5_representor_match(spawn, eth_da)) 984 return NULL; 985 /* Build device name. */ 986 if (spawn->pf_bond < 0) { 987 /* Single device. */ 988 if (!switch_info->representor) 989 strlcpy(name, dpdk_dev->name, sizeof(name)); 990 else 991 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 992 dpdk_dev->name, 993 switch_info->name_type == 994 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 995 switch_info->port_name); 996 } else { 997 /* Bonding device. */ 998 if (!switch_info->representor) { 999 err = snprintf(name, sizeof(name), "%s_%s", 1000 dpdk_dev->name, 1001 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1002 } else { 1003 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 1004 dpdk_dev->name, 1005 mlx5_os_get_dev_device_name(spawn->phys_dev), 1006 switch_info->ctrl_num, 1007 switch_info->pf_num, 1008 switch_info->name_type == 1009 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1010 switch_info->port_name); 1011 } 1012 } 1013 if (err >= (int)sizeof(name)) 1014 DRV_LOG(WARNING, "device name overflow %s", name); 1015 /* check if the device is already spawned */ 1016 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1017 rte_errno = EEXIST; 1018 return NULL; 1019 } 1020 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1021 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1022 struct mlx5_mp_id mp_id; 1023 1024 eth_dev = rte_eth_dev_attach_secondary(name); 1025 if (eth_dev == NULL) { 1026 DRV_LOG(ERR, "can not attach rte ethdev"); 1027 rte_errno = ENOMEM; 1028 return NULL; 1029 } 1030 eth_dev->device = dpdk_dev; 1031 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1032 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1033 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1034 err = mlx5_proc_priv_init(eth_dev); 1035 if (err) 1036 return NULL; 1037 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 1038 /* Receive command fd from primary process */ 1039 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 1040 if (err < 0) 1041 goto err_secondary; 1042 /* Remap UAR for Tx queues. */ 1043 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1044 if (err) 1045 goto err_secondary; 1046 /* 1047 * Ethdev pointer is still required as input since 1048 * the primary device is not accessible from the 1049 * secondary process. 1050 */ 1051 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1052 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1053 return eth_dev; 1054 err_secondary: 1055 mlx5_dev_close(eth_dev); 1056 return NULL; 1057 } 1058 /* 1059 * Some parameters ("tx_db_nc" in particularly) are needed in 1060 * advance to create dv/verbs device context. We proceed the 1061 * devargs here to get ones, and later proceed devargs again 1062 * to override some hardware settings. 1063 */ 1064 err = mlx5_args(config, dpdk_dev->devargs); 1065 if (err) { 1066 err = rte_errno; 1067 DRV_LOG(ERR, "failed to process device arguments: %s", 1068 strerror(rte_errno)); 1069 goto error; 1070 } 1071 if (config->dv_miss_info) { 1072 if (switch_info->master || switch_info->representor) 1073 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1074 } 1075 mlx5_malloc_mem_select(config->sys_mem_en); 1076 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 1077 if (!sh) 1078 return NULL; 1079 config->devx = sh->devx; 1080 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 1081 config->dest_tir = 1; 1082 #endif 1083 #ifdef HAVE_IBV_MLX5_MOD_SWP 1084 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 1085 #endif 1086 /* 1087 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1088 * as all ConnectX-5 devices. 1089 */ 1090 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1091 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1092 #endif 1093 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1094 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1095 #endif 1096 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 1097 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1098 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1099 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1100 mps = MLX5_MPW_ENHANCED; 1101 } else { 1102 DRV_LOG(DEBUG, "MPW is supported"); 1103 mps = MLX5_MPW; 1104 } 1105 } else { 1106 DRV_LOG(DEBUG, "MPW isn't supported"); 1107 mps = MLX5_MPW_DISABLED; 1108 } 1109 #ifdef HAVE_IBV_MLX5_MOD_SWP 1110 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1111 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1112 DRV_LOG(DEBUG, "SWP support: %u", swp); 1113 #endif 1114 config->swp = !!swp; 1115 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1116 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1117 struct mlx5dv_striding_rq_caps mprq_caps = 1118 dv_attr.striding_rq_caps; 1119 1120 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1121 mprq_caps.min_single_stride_log_num_of_bytes); 1122 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1123 mprq_caps.max_single_stride_log_num_of_bytes); 1124 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1125 mprq_caps.min_single_wqe_log_num_of_strides); 1126 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1127 mprq_caps.max_single_wqe_log_num_of_strides); 1128 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1129 mprq_caps.supported_qpts); 1130 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1131 mprq = 1; 1132 mprq_min_stride_size_n = 1133 mprq_caps.min_single_stride_log_num_of_bytes; 1134 mprq_max_stride_size_n = 1135 mprq_caps.max_single_stride_log_num_of_bytes; 1136 mprq_min_stride_num_n = 1137 mprq_caps.min_single_wqe_log_num_of_strides; 1138 mprq_max_stride_num_n = 1139 mprq_caps.max_single_wqe_log_num_of_strides; 1140 } 1141 #endif 1142 /* Rx CQE compression is enabled by default. */ 1143 config->cqe_comp = 1; 1144 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1145 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1146 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1147 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1148 (dv_attr.tunnel_offloads_caps & 1149 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 1150 (dv_attr.tunnel_offloads_caps & 1151 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 1152 } 1153 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1154 tunnel_en ? "" : "not "); 1155 #else 1156 DRV_LOG(WARNING, 1157 "tunnel offloading disabled due to old OFED/rdma-core version"); 1158 #endif 1159 config->tunnel_en = tunnel_en; 1160 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1161 mpls_en = ((dv_attr.tunnel_offloads_caps & 1162 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1163 (dv_attr.tunnel_offloads_caps & 1164 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1165 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1166 mpls_en ? "" : "not "); 1167 #else 1168 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1169 " old OFED/rdma-core version or firmware configuration"); 1170 #endif 1171 config->mpls_en = mpls_en; 1172 /* Check port status. */ 1173 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1174 if (err) { 1175 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1176 goto error; 1177 } 1178 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1179 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1180 err = EINVAL; 1181 goto error; 1182 } 1183 if (port_attr.state != IBV_PORT_ACTIVE) 1184 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1185 mlx5_glue->port_state_str(port_attr.state), 1186 port_attr.state); 1187 /* Allocate private eth device data. */ 1188 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1189 sizeof(*priv), 1190 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1191 if (priv == NULL) { 1192 DRV_LOG(ERR, "priv allocation failure"); 1193 err = ENOMEM; 1194 goto error; 1195 } 1196 priv->sh = sh; 1197 priv->dev_port = spawn->phys_port; 1198 priv->pci_dev = spawn->pci_dev; 1199 priv->mtu = RTE_ETHER_MTU; 1200 /* Some internal functions rely on Netlink sockets, open them now. */ 1201 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1202 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1203 priv->representor = !!switch_info->representor; 1204 priv->master = !!switch_info->master; 1205 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1206 priv->vport_meta_tag = 0; 1207 priv->vport_meta_mask = 0; 1208 priv->pf_bond = spawn->pf_bond; 1209 1210 DRV_LOG(DEBUG, 1211 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1212 priv->dev_port, dpdk_dev->bus->name, 1213 priv->pci_dev ? priv->pci_dev->name : "NONE", 1214 priv->master, priv->representor, priv->pf_bond); 1215 1216 /* 1217 * If we have E-Switch we should determine the vport attributes. 1218 * E-Switch may use either source vport field or reg_c[0] metadata 1219 * register to match on vport index. The engaged part of metadata 1220 * register is defined by mask. 1221 */ 1222 if (switch_info->representor || switch_info->master) { 1223 err = mlx5_glue->devx_port_query(sh->ctx, 1224 spawn->phys_port, 1225 &vport_info); 1226 if (err) { 1227 DRV_LOG(WARNING, 1228 "can't query devx port %d on device %s", 1229 spawn->phys_port, 1230 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1231 vport_info.query_flags = 0; 1232 } 1233 } 1234 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1235 priv->vport_meta_tag = vport_info.vport_meta_tag; 1236 priv->vport_meta_mask = vport_info.vport_meta_mask; 1237 if (!priv->vport_meta_mask) { 1238 DRV_LOG(ERR, "vport zero mask for port %d" 1239 " on bonding device %s", 1240 spawn->phys_port, 1241 mlx5_os_get_dev_device_name 1242 (spawn->phys_dev)); 1243 err = ENOTSUP; 1244 goto error; 1245 } 1246 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1247 DRV_LOG(ERR, "invalid vport tag for port %d" 1248 " on bonding device %s", 1249 spawn->phys_port, 1250 mlx5_os_get_dev_device_name 1251 (spawn->phys_dev)); 1252 err = ENOTSUP; 1253 goto error; 1254 } 1255 } 1256 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1257 priv->vport_id = vport_info.vport_id; 1258 } else if (spawn->pf_bond >= 0 && 1259 (switch_info->representor || switch_info->master)) { 1260 DRV_LOG(ERR, "can't deduce vport index for port %d" 1261 " on bonding device %s", 1262 spawn->phys_port, 1263 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1264 err = ENOTSUP; 1265 goto error; 1266 } else { 1267 /* 1268 * Suppose vport index in compatible way. Kernel/rdma_core 1269 * support single E-Switch per PF configurations only and 1270 * vport_id field contains the vport index for associated VF, 1271 * which is deduced from representor port name. 1272 * For example, let's have the IB device port 10, it has 1273 * attached network device eth0, which has port name attribute 1274 * pf0vf2, we can deduce the VF number as 2, and set vport index 1275 * as 3 (2+1). This assigning schema should be changed if the 1276 * multiple E-Switch instances per PF configurations or/and PCI 1277 * subfunctions are added. 1278 */ 1279 priv->vport_id = switch_info->representor ? 1280 switch_info->port_name + 1 : -1; 1281 } 1282 priv->representor_id = mlx5_representor_id_encode(switch_info, 1283 eth_da->type); 1284 /* 1285 * Look for sibling devices in order to reuse their switch domain 1286 * if any, otherwise allocate one. 1287 */ 1288 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1289 const struct mlx5_priv *opriv = 1290 rte_eth_devices[port_id].data->dev_private; 1291 1292 if (!opriv || 1293 opriv->sh != priv->sh || 1294 opriv->domain_id == 1295 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1296 continue; 1297 priv->domain_id = opriv->domain_id; 1298 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1299 priv->dev_port, priv->domain_id); 1300 break; 1301 } 1302 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1303 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1304 if (err) { 1305 err = rte_errno; 1306 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1307 strerror(rte_errno)); 1308 goto error; 1309 } 1310 own_domain_id = 1; 1311 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1312 priv->dev_port, priv->domain_id); 1313 } 1314 /* Override some values set by hardware configuration. */ 1315 mlx5_args(config, dpdk_dev->devargs); 1316 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev); 1317 if (err) 1318 goto error; 1319 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1320 IBV_DEVICE_RAW_IP_CSUM); 1321 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1322 (config->hw_csum ? "" : "not ")); 1323 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1324 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1325 DRV_LOG(DEBUG, "counters are not supported"); 1326 #endif 1327 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1328 if (config->dv_flow_en) { 1329 DRV_LOG(WARNING, "DV flow is not supported"); 1330 config->dv_flow_en = 0; 1331 } 1332 #endif 1333 if (spawn->max_port > UINT8_MAX) { 1334 /* Verbs can't support ports larger than 255 by design. */ 1335 DRV_LOG(ERR, "can't support IB ports > UINT8_MAX"); 1336 err = EINVAL; 1337 goto error; 1338 } 1339 config->ind_table_max_size = 1340 sh->device_attr.max_rwq_indirection_table_size; 1341 /* 1342 * Remove this check once DPDK supports larger/variable 1343 * indirection tables. 1344 */ 1345 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1346 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1347 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1348 config->ind_table_max_size); 1349 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1350 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1351 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1352 (config->hw_vlan_strip ? "" : "not ")); 1353 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1354 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1355 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1356 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1357 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1358 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1359 IBV_DEVICE_PCI_WRITE_END_PADDING); 1360 #endif 1361 if (config->hw_padding && !hw_padding) { 1362 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1363 config->hw_padding = 0; 1364 } else if (config->hw_padding) { 1365 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1366 } 1367 config->tso = (sh->device_attr.max_tso > 0 && 1368 (sh->device_attr.tso_supported_qpts & 1369 (1 << IBV_QPT_RAW_PACKET))); 1370 if (config->tso) 1371 config->tso_max_payload_sz = sh->device_attr.max_tso; 1372 /* 1373 * MPW is disabled by default, while the Enhanced MPW is enabled 1374 * by default. 1375 */ 1376 if (config->mps == MLX5_ARG_UNSET) 1377 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1378 MLX5_MPW_DISABLED; 1379 else 1380 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1381 DRV_LOG(INFO, "%sMPS is %s", 1382 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1383 config->mps == MLX5_MPW ? "legacy " : "", 1384 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1385 if (config->devx) { 1386 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1387 if (err) { 1388 err = -err; 1389 goto error; 1390 } 1391 /* Check relax ordering support. */ 1392 if (!haswell_broadwell_cpu) { 1393 sh->cmng.relaxed_ordering_write = 1394 config->hca_attr.relaxed_ordering_write; 1395 sh->cmng.relaxed_ordering_read = 1396 config->hca_attr.relaxed_ordering_read; 1397 } else { 1398 sh->cmng.relaxed_ordering_read = 0; 1399 sh->cmng.relaxed_ordering_write = 0; 1400 } 1401 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1402 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1403 sh->steering_format_version = 1404 config->hca_attr.steering_format_version; 1405 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1406 /* Check for LRO support. */ 1407 if (config->dest_tir && config->hca_attr.lro_cap && 1408 config->dv_flow_en) { 1409 /* TBD check tunnel lro caps. */ 1410 config->lro.supported = config->hca_attr.lro_cap; 1411 DRV_LOG(DEBUG, "Device supports LRO"); 1412 /* 1413 * If LRO timeout is not configured by application, 1414 * use the minimal supported value. 1415 */ 1416 if (!config->lro.timeout) 1417 config->lro.timeout = 1418 config->hca_attr.lro_timer_supported_periods[0]; 1419 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1420 config->lro.timeout); 1421 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1422 "required for coalescing is %d bytes", 1423 config->hca_attr.lro_min_mss_size); 1424 } 1425 #if defined(HAVE_MLX5DV_DR) && \ 1426 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1427 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1428 if (config->hca_attr.qos.sup && 1429 config->hca_attr.qos.flow_meter_old && 1430 config->dv_flow_en) { 1431 uint8_t reg_c_mask = 1432 config->hca_attr.qos.flow_meter_reg_c_ids; 1433 /* 1434 * Meter needs two REG_C's for color match and pre-sfx 1435 * flow match. Here get the REG_C for color match. 1436 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1437 */ 1438 reg_c_mask &= 0xfc; 1439 if (__builtin_popcount(reg_c_mask) < 1) { 1440 priv->mtr_en = 0; 1441 DRV_LOG(WARNING, "No available register for" 1442 " meter."); 1443 } else { 1444 /* 1445 * The meter color register is used by the 1446 * flow-hit feature as well. 1447 * The flow-hit feature must use REG_C_3 1448 * Prefer REG_C_3 if it is available. 1449 */ 1450 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1451 priv->mtr_color_reg = REG_C_3; 1452 else 1453 priv->mtr_color_reg = ffs(reg_c_mask) 1454 - 1 + REG_C_0; 1455 priv->mtr_en = 1; 1456 priv->mtr_reg_share = 1457 config->hca_attr.qos.flow_meter; 1458 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1459 priv->mtr_color_reg); 1460 } 1461 } 1462 if (config->hca_attr.qos.sup && 1463 config->hca_attr.qos.flow_meter_aso_sup) { 1464 uint32_t log_obj_size = 1465 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1466 if (log_obj_size >= 1467 config->hca_attr.qos.log_meter_aso_granularity && 1468 log_obj_size <= 1469 config->hca_attr.qos.log_meter_aso_max_alloc) 1470 sh->meter_aso_en = 1; 1471 } 1472 if (priv->mtr_en) { 1473 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1474 if (err) { 1475 err = -err; 1476 goto error; 1477 } 1478 } 1479 if (config->hca_attr.flow.tunnel_header_0_1) 1480 sh->tunnel_header_0_1 = 1; 1481 #endif 1482 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1483 if (config->hca_attr.flow_hit_aso && 1484 priv->mtr_color_reg == REG_C_3) { 1485 sh->flow_hit_aso_en = 1; 1486 err = mlx5_flow_aso_age_mng_init(sh); 1487 if (err) { 1488 err = -err; 1489 goto error; 1490 } 1491 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1492 } 1493 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1494 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1495 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1496 if (config->hca_attr.ct_offload && 1497 priv->mtr_color_reg == REG_C_3) { 1498 err = mlx5_flow_aso_ct_mng_init(sh); 1499 if (err) { 1500 err = -err; 1501 goto error; 1502 } 1503 DRV_LOG(DEBUG, "CT ASO is supported."); 1504 sh->ct_aso_en = 1; 1505 } 1506 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1507 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1508 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1509 config->dv_flow_en) { 1510 priv->sampler_en = 1; 1511 DRV_LOG(DEBUG, "Sampler enabled!"); 1512 } else { 1513 priv->sampler_en = 0; 1514 if (!config->hca_attr.log_max_ft_sampler_num) 1515 DRV_LOG(WARNING, 1516 "No available register for sampler."); 1517 else 1518 DRV_LOG(DEBUG, "DV flow is not supported!"); 1519 } 1520 #endif 1521 } 1522 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1523 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1524 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1525 config->cqe_comp = 0; 1526 } 1527 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1528 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1529 DRV_LOG(WARNING, "Flow Tag CQE compression" 1530 " format isn't supported."); 1531 config->cqe_comp = 0; 1532 } 1533 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1534 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1535 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1536 " format isn't supported."); 1537 config->cqe_comp = 0; 1538 } 1539 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1540 config->cqe_comp ? "" : "not "); 1541 if (config->tx_pp) { 1542 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1543 config->hca_attr.dev_freq_khz); 1544 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1545 config->hca_attr.qos.packet_pacing ? "" : "not "); 1546 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1547 config->hca_attr.cross_channel ? "" : "not "); 1548 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1549 config->hca_attr.wqe_index_ignore ? "" : "not "); 1550 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1551 config->hca_attr.non_wire_sq ? "" : "not "); 1552 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1553 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1554 config->hca_attr.log_max_static_sq_wq); 1555 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1556 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1557 if (!config->devx) { 1558 DRV_LOG(ERR, "DevX is required for packet pacing"); 1559 err = ENODEV; 1560 goto error; 1561 } 1562 if (!config->hca_attr.qos.packet_pacing) { 1563 DRV_LOG(ERR, "Packet pacing is not supported"); 1564 err = ENODEV; 1565 goto error; 1566 } 1567 if (!config->hca_attr.cross_channel) { 1568 DRV_LOG(ERR, "Cross channel operations are" 1569 " required for packet pacing"); 1570 err = ENODEV; 1571 goto error; 1572 } 1573 if (!config->hca_attr.wqe_index_ignore) { 1574 DRV_LOG(ERR, "WQE index ignore feature is" 1575 " required for packet pacing"); 1576 err = ENODEV; 1577 goto error; 1578 } 1579 if (!config->hca_attr.non_wire_sq) { 1580 DRV_LOG(ERR, "Non-wire SQ feature is" 1581 " required for packet pacing"); 1582 err = ENODEV; 1583 goto error; 1584 } 1585 if (!config->hca_attr.log_max_static_sq_wq) { 1586 DRV_LOG(ERR, "Static WQE SQ feature is" 1587 " required for packet pacing"); 1588 err = ENODEV; 1589 goto error; 1590 } 1591 if (!config->hca_attr.qos.wqe_rate_pp) { 1592 DRV_LOG(ERR, "WQE rate mode is required" 1593 " for packet pacing"); 1594 err = ENODEV; 1595 goto error; 1596 } 1597 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1598 DRV_LOG(ERR, "DevX does not provide UAR offset," 1599 " can't create queues for packet pacing"); 1600 err = ENODEV; 1601 goto error; 1602 #endif 1603 } 1604 if (config->devx) { 1605 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1606 1607 err = config->hca_attr.access_register_user ? 1608 mlx5_devx_cmd_register_read 1609 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1610 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1611 if (!err) { 1612 uint32_t ts_mode; 1613 1614 /* MTUTC register is read successfully. */ 1615 ts_mode = MLX5_GET(register_mtutc, reg, 1616 time_stamp_mode); 1617 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1618 config->rt_timestamp = 1; 1619 } else { 1620 /* Kernel does not support register reading. */ 1621 if (config->hca_attr.dev_freq_khz == 1622 (NS_PER_S / MS_PER_S)) 1623 config->rt_timestamp = 1; 1624 } 1625 } 1626 /* 1627 * If HW has bug working with tunnel packet decapsulation and 1628 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1629 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1630 */ 1631 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1632 config->hw_fcs_strip = 0; 1633 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1634 (config->hw_fcs_strip ? "" : "not ")); 1635 if (config->mprq.enabled && mprq) { 1636 if (config->mprq.stride_num_n && 1637 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1638 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1639 config->mprq.stride_num_n = 1640 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1641 mprq_min_stride_num_n), 1642 mprq_max_stride_num_n); 1643 DRV_LOG(WARNING, 1644 "the number of strides" 1645 " for Multi-Packet RQ is out of range," 1646 " setting default value (%u)", 1647 1 << config->mprq.stride_num_n); 1648 } 1649 if (config->mprq.stride_size_n && 1650 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1651 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1652 config->mprq.stride_size_n = 1653 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1654 mprq_min_stride_size_n), 1655 mprq_max_stride_size_n); 1656 DRV_LOG(WARNING, 1657 "the size of a stride" 1658 " for Multi-Packet RQ is out of range," 1659 " setting default value (%u)", 1660 1 << config->mprq.stride_size_n); 1661 } 1662 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1663 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1664 } else if (config->mprq.enabled && !mprq) { 1665 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1666 config->mprq.enabled = 0; 1667 } 1668 if (config->max_dump_files_num == 0) 1669 config->max_dump_files_num = 128; 1670 eth_dev = rte_eth_dev_allocate(name); 1671 if (eth_dev == NULL) { 1672 DRV_LOG(ERR, "can not allocate rte ethdev"); 1673 err = ENOMEM; 1674 goto error; 1675 } 1676 if (priv->representor) { 1677 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1678 eth_dev->data->representor_id = priv->representor_id; 1679 } 1680 priv->mp_id.port_id = eth_dev->data->port_id; 1681 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1682 /* 1683 * Store associated network device interface index. This index 1684 * is permanent throughout the lifetime of device. So, we may store 1685 * the ifindex here and use the cached value further. 1686 */ 1687 MLX5_ASSERT(spawn->ifindex); 1688 priv->if_index = spawn->ifindex; 1689 eth_dev->data->dev_private = priv; 1690 priv->dev_data = eth_dev->data; 1691 eth_dev->data->mac_addrs = priv->mac; 1692 eth_dev->device = dpdk_dev; 1693 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1694 /* Configure the first MAC address by default. */ 1695 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1696 DRV_LOG(ERR, 1697 "port %u cannot get MAC address, is mlx5_en" 1698 " loaded? (errno: %s)", 1699 eth_dev->data->port_id, strerror(rte_errno)); 1700 err = ENODEV; 1701 goto error; 1702 } 1703 DRV_LOG(INFO, 1704 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1705 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1706 #ifdef RTE_LIBRTE_MLX5_DEBUG 1707 { 1708 char ifname[MLX5_NAMESIZE]; 1709 1710 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1711 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1712 eth_dev->data->port_id, ifname); 1713 else 1714 DRV_LOG(DEBUG, "port %u ifname is unknown", 1715 eth_dev->data->port_id); 1716 } 1717 #endif 1718 /* Get actual MTU if possible. */ 1719 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1720 if (err) { 1721 err = rte_errno; 1722 goto error; 1723 } 1724 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1725 priv->mtu); 1726 /* Initialize burst functions to prevent crashes before link-up. */ 1727 eth_dev->rx_pkt_burst = removed_rx_burst; 1728 eth_dev->tx_pkt_burst = removed_tx_burst; 1729 eth_dev->dev_ops = &mlx5_dev_ops; 1730 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1731 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1732 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1733 /* Register MAC address. */ 1734 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1735 if (config->vf && config->vf_nl_en) 1736 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1737 mlx5_ifindex(eth_dev), 1738 eth_dev->data->mac_addrs, 1739 MLX5_MAX_MAC_ADDRESSES); 1740 priv->ctrl_flows = 0; 1741 rte_spinlock_init(&priv->flow_list_lock); 1742 TAILQ_INIT(&priv->flow_meters); 1743 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1744 if (!priv->mtr_profile_tbl) 1745 goto error; 1746 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1747 mlx5_glue->dv_set_context_attr(sh->ctx, 1748 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1749 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1750 .alloc = &mlx5_alloc_verbs_buf, 1751 .free = &mlx5_free_verbs_buf, 1752 .data = sh, 1753 })); 1754 /* Bring Ethernet device up. */ 1755 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1756 eth_dev->data->port_id); 1757 mlx5_set_link_up(eth_dev); 1758 /* 1759 * Even though the interrupt handler is not installed yet, 1760 * interrupts will still trigger on the async_fd from 1761 * Verbs context returned by ibv_open_device(). 1762 */ 1763 mlx5_link_update(eth_dev, 0); 1764 #ifdef HAVE_MLX5DV_DR_ESWITCH 1765 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1766 (switch_info->representor || switch_info->master))) 1767 config->dv_esw_en = 0; 1768 #else 1769 config->dv_esw_en = 0; 1770 #endif 1771 /* Detect minimal data bytes to inline. */ 1772 mlx5_set_min_inline(spawn, config); 1773 /* Store device configuration on private structure. */ 1774 priv->config = *config; 1775 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1776 icfg[i].release_mem_en = !!config->reclaim_mode; 1777 if (config->reclaim_mode) 1778 icfg[i].per_core_cache = 0; 1779 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1780 if (!priv->flows[i]) 1781 goto error; 1782 } 1783 /* Create context for virtual machine VLAN workaround. */ 1784 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1785 if (config->dv_flow_en) { 1786 err = mlx5_alloc_shared_dr(priv); 1787 if (err) 1788 goto error; 1789 } 1790 if (config->devx && config->dv_flow_en && config->dest_tir) { 1791 priv->obj_ops = devx_obj_ops; 1792 priv->obj_ops.drop_action_create = 1793 ibv_obj_ops.drop_action_create; 1794 priv->obj_ops.drop_action_destroy = 1795 ibv_obj_ops.drop_action_destroy; 1796 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1797 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1798 #else 1799 if (config->dv_esw_en) 1800 priv->obj_ops.txq_obj_modify = 1801 ibv_obj_ops.txq_obj_modify; 1802 #endif 1803 /* Use specific wrappers for Tx object. */ 1804 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1805 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1806 mlx5_queue_counter_id_prepare(eth_dev); 1807 priv->obj_ops.lb_dummy_queue_create = 1808 mlx5_rxq_ibv_obj_dummy_lb_create; 1809 priv->obj_ops.lb_dummy_queue_release = 1810 mlx5_rxq_ibv_obj_dummy_lb_release; 1811 } else { 1812 priv->obj_ops = ibv_obj_ops; 1813 } 1814 if (config->tx_pp && 1815 (priv->config.dv_esw_en || 1816 priv->obj_ops.txq_obj_new != mlx5_os_txq_obj_new)) { 1817 /* 1818 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1819 * packet pacing and already checked above. 1820 * Hence, we should only make sure the SQs will be created 1821 * with DevX, not with Verbs. 1822 * Verbs allocates the SQ UAR on its own and it can't be shared 1823 * with Clock Queue UAR as required for Tx scheduling. 1824 */ 1825 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1826 err = ENODEV; 1827 goto error; 1828 } 1829 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1830 if (!priv->drop_queue.hrxq) 1831 goto error; 1832 /* Supported Verbs flow priority number detection. */ 1833 err = mlx5_flow_discover_priorities(eth_dev); 1834 if (err < 0) { 1835 err = -err; 1836 goto error; 1837 } 1838 priv->config.flow_prio = err; 1839 if (!priv->config.dv_esw_en && 1840 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1841 DRV_LOG(WARNING, "metadata mode %u is not supported " 1842 "(no E-Switch)", priv->config.dv_xmeta_en); 1843 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1844 } 1845 mlx5_set_metadata_mask(eth_dev); 1846 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1847 !priv->sh->dv_regc0_mask) { 1848 DRV_LOG(ERR, "metadata mode %u is not supported " 1849 "(no metadata reg_c[0] is available)", 1850 priv->config.dv_xmeta_en); 1851 err = ENOTSUP; 1852 goto error; 1853 } 1854 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1855 mlx5_hrxq_create_cb, 1856 mlx5_hrxq_match_cb, 1857 mlx5_hrxq_remove_cb, 1858 mlx5_hrxq_clone_cb, 1859 mlx5_hrxq_clone_free_cb); 1860 if (!priv->hrxqs) 1861 goto error; 1862 rte_rwlock_init(&priv->ind_tbls_lock); 1863 /* Query availability of metadata reg_c's. */ 1864 err = mlx5_flow_discover_mreg_c(eth_dev); 1865 if (err < 0) { 1866 err = -err; 1867 goto error; 1868 } 1869 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1870 DRV_LOG(DEBUG, 1871 "port %u extensive metadata register is not supported", 1872 eth_dev->data->port_id); 1873 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1874 DRV_LOG(ERR, "metadata mode %u is not supported " 1875 "(no metadata registers available)", 1876 priv->config.dv_xmeta_en); 1877 err = ENOTSUP; 1878 goto error; 1879 } 1880 } 1881 if (priv->config.dv_flow_en && 1882 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1883 mlx5_flow_ext_mreg_supported(eth_dev) && 1884 priv->sh->dv_regc0_mask) { 1885 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1886 MLX5_FLOW_MREG_HTABLE_SZ, 1887 false, true, eth_dev, 1888 flow_dv_mreg_create_cb, 1889 flow_dv_mreg_match_cb, 1890 flow_dv_mreg_remove_cb, 1891 flow_dv_mreg_clone_cb, 1892 flow_dv_mreg_clone_free_cb); 1893 if (!priv->mreg_cp_tbl) { 1894 err = ENOMEM; 1895 goto error; 1896 } 1897 } 1898 rte_spinlock_init(&priv->shared_act_sl); 1899 mlx5_flow_counter_mode_config(eth_dev); 1900 mlx5_flow_drop_action_config(eth_dev); 1901 if (priv->config.dv_flow_en) 1902 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1903 return eth_dev; 1904 error: 1905 if (priv) { 1906 if (priv->mreg_cp_tbl) 1907 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1908 if (priv->sh) 1909 mlx5_os_free_shared_dr(priv); 1910 if (priv->nl_socket_route >= 0) 1911 close(priv->nl_socket_route); 1912 if (priv->nl_socket_rdma >= 0) 1913 close(priv->nl_socket_rdma); 1914 if (priv->vmwa_context) 1915 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1916 if (eth_dev && priv->drop_queue.hrxq) 1917 mlx5_drop_action_destroy(eth_dev); 1918 if (priv->mtr_profile_tbl) 1919 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1920 if (own_domain_id) 1921 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1922 if (priv->hrxqs) 1923 mlx5_list_destroy(priv->hrxqs); 1924 mlx5_free(priv); 1925 if (eth_dev != NULL) 1926 eth_dev->data->dev_private = NULL; 1927 } 1928 if (eth_dev != NULL) { 1929 /* mac_addrs must not be freed alone because part of 1930 * dev_private 1931 **/ 1932 eth_dev->data->mac_addrs = NULL; 1933 rte_eth_dev_release_port(eth_dev); 1934 } 1935 if (sh) 1936 mlx5_free_shared_dev_ctx(sh); 1937 MLX5_ASSERT(err > 0); 1938 rte_errno = err; 1939 return NULL; 1940 } 1941 1942 /** 1943 * Comparison callback to sort device data. 1944 * 1945 * This is meant to be used with qsort(). 1946 * 1947 * @param a[in] 1948 * Pointer to pointer to first data object. 1949 * @param b[in] 1950 * Pointer to pointer to second data object. 1951 * 1952 * @return 1953 * 0 if both objects are equal, less than 0 if the first argument is less 1954 * than the second, greater than 0 otherwise. 1955 */ 1956 static int 1957 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1958 { 1959 const struct mlx5_switch_info *si_a = 1960 &((const struct mlx5_dev_spawn_data *)a)->info; 1961 const struct mlx5_switch_info *si_b = 1962 &((const struct mlx5_dev_spawn_data *)b)->info; 1963 int ret; 1964 1965 /* Master device first. */ 1966 ret = si_b->master - si_a->master; 1967 if (ret) 1968 return ret; 1969 /* Then representor devices. */ 1970 ret = si_b->representor - si_a->representor; 1971 if (ret) 1972 return ret; 1973 /* Unidentified devices come last in no specific order. */ 1974 if (!si_a->representor) 1975 return 0; 1976 /* Order representors by name. */ 1977 return si_a->port_name - si_b->port_name; 1978 } 1979 1980 /** 1981 * Match PCI information for possible slaves of bonding device. 1982 * 1983 * @param[in] ibv_dev 1984 * Pointer to Infiniband device structure. 1985 * @param[in] pci_dev 1986 * Pointer to primary PCI address structure to match. 1987 * @param[in] nl_rdma 1988 * Netlink RDMA group socket handle. 1989 * @param[in] owner 1990 * Rerepsentor owner PF index. 1991 * @param[out] bond_info 1992 * Pointer to bonding information. 1993 * 1994 * @return 1995 * negative value if no bonding device found, otherwise 1996 * positive index of slave PF in bonding. 1997 */ 1998 static int 1999 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 2000 const struct rte_pci_addr *pci_dev, 2001 int nl_rdma, uint16_t owner, 2002 struct mlx5_bond_info *bond_info) 2003 { 2004 char ifname[IF_NAMESIZE + 1]; 2005 unsigned int ifindex; 2006 unsigned int np, i; 2007 FILE *bond_file = NULL, *file; 2008 int pf = -1; 2009 int ret; 2010 2011 /* 2012 * Try to get master device name. If something goes 2013 * wrong suppose the lack of kernel support and no 2014 * bonding devices. 2015 */ 2016 memset(bond_info, 0, sizeof(*bond_info)); 2017 if (nl_rdma < 0) 2018 return -1; 2019 if (!strstr(ibv_dev->name, "bond")) 2020 return -1; 2021 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 2022 if (!np) 2023 return -1; 2024 /* 2025 * The Master device might not be on the predefined 2026 * port (not on port index 1, it is not garanted), 2027 * we have to scan all Infiniband device port and 2028 * find master. 2029 */ 2030 for (i = 1; i <= np; ++i) { 2031 /* Check whether Infiniband port is populated. */ 2032 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 2033 if (!ifindex) 2034 continue; 2035 if (!if_indextoname(ifindex, ifname)) 2036 continue; 2037 /* Try to read bonding slave names from sysfs. */ 2038 MKSTR(slaves, 2039 "/sys/class/net/%s/master/bonding/slaves", ifname); 2040 bond_file = fopen(slaves, "r"); 2041 if (bond_file) 2042 break; 2043 } 2044 if (!bond_file) 2045 return -1; 2046 /* Use safe format to check maximal buffer length. */ 2047 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 2048 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 2049 char tmp_str[IF_NAMESIZE + 32]; 2050 struct rte_pci_addr pci_addr; 2051 struct mlx5_switch_info info; 2052 2053 /* Process slave interface names in the loop. */ 2054 snprintf(tmp_str, sizeof(tmp_str), 2055 "/sys/class/net/%s", ifname); 2056 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 2057 DRV_LOG(WARNING, "can not get PCI address" 2058 " for netdev \"%s\"", ifname); 2059 continue; 2060 } 2061 /* Slave interface PCI address match found. */ 2062 snprintf(tmp_str, sizeof(tmp_str), 2063 "/sys/class/net/%s/phys_port_name", ifname); 2064 file = fopen(tmp_str, "rb"); 2065 if (!file) 2066 break; 2067 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 2068 if (fscanf(file, "%32s", tmp_str) == 1) 2069 mlx5_translate_port_name(tmp_str, &info); 2070 fclose(file); 2071 /* Only process PF ports. */ 2072 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 2073 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 2074 continue; 2075 /* Check max bonding member. */ 2076 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 2077 DRV_LOG(WARNING, "bonding index out of range, " 2078 "please increase MLX5_BOND_MAX_PORTS: %s", 2079 tmp_str); 2080 break; 2081 } 2082 /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */ 2083 if (pci_dev->domain == pci_addr.domain && 2084 pci_dev->bus == pci_addr.bus && 2085 pci_dev->devid == pci_addr.devid && 2086 ((pci_dev->function == 0 && 2087 pci_dev->function + owner == pci_addr.function) || 2088 (pci_dev->function == owner && 2089 pci_addr.function == owner))) 2090 pf = info.port_name; 2091 /* Get ifindex. */ 2092 snprintf(tmp_str, sizeof(tmp_str), 2093 "/sys/class/net/%s/ifindex", ifname); 2094 file = fopen(tmp_str, "rb"); 2095 if (!file) 2096 break; 2097 ret = fscanf(file, "%u", &ifindex); 2098 fclose(file); 2099 if (ret != 1) 2100 break; 2101 /* Save bonding info. */ 2102 strncpy(bond_info->ports[info.port_name].ifname, ifname, 2103 sizeof(bond_info->ports[0].ifname)); 2104 bond_info->ports[info.port_name].pci_addr = pci_addr; 2105 bond_info->ports[info.port_name].ifindex = ifindex; 2106 bond_info->n_port++; 2107 } 2108 if (pf >= 0) { 2109 /* Get bond interface info */ 2110 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 2111 bond_info->ifname); 2112 if (ret) 2113 DRV_LOG(ERR, "unable to get bond info: %s", 2114 strerror(rte_errno)); 2115 else 2116 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 2117 ifindex, bond_info->ifindex, bond_info->ifname); 2118 } 2119 return pf; 2120 } 2121 2122 static void 2123 mlx5_os_config_default(struct mlx5_dev_config *config) 2124 { 2125 memset(config, 0, sizeof(*config)); 2126 config->mps = MLX5_ARG_UNSET; 2127 config->dbnc = MLX5_ARG_UNSET; 2128 config->rx_vec_en = 1; 2129 config->txq_inline_max = MLX5_ARG_UNSET; 2130 config->txq_inline_min = MLX5_ARG_UNSET; 2131 config->txq_inline_mpw = MLX5_ARG_UNSET; 2132 config->txqs_inline = MLX5_ARG_UNSET; 2133 config->vf_nl_en = 1; 2134 config->mr_ext_memseg_en = 1; 2135 config->mr_mempool_reg_en = 1; 2136 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2137 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2138 config->dv_esw_en = 1; 2139 config->dv_flow_en = 1; 2140 config->decap_en = 1; 2141 config->log_hp_size = MLX5_ARG_UNSET; 2142 config->allow_duplicate_pattern = 1; 2143 } 2144 2145 /** 2146 * Register a PCI device within bonding. 2147 * 2148 * This function spawns Ethernet devices out of a given PCI device and 2149 * bonding owner PF index. 2150 * 2151 * @param[in] pci_dev 2152 * PCI device information. 2153 * @param[in] req_eth_da 2154 * Requested ethdev device argument. 2155 * @param[in] owner_id 2156 * Requested owner PF port ID within bonding device, default to 0. 2157 * 2158 * @return 2159 * 0 on success, a negative errno value otherwise and rte_errno is set. 2160 */ 2161 static int 2162 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 2163 struct rte_eth_devargs *req_eth_da, 2164 uint16_t owner_id) 2165 { 2166 struct ibv_device **ibv_list; 2167 /* 2168 * Number of found IB Devices matching with requested PCI BDF. 2169 * nd != 1 means there are multiple IB devices over the same 2170 * PCI device and we have representors and master. 2171 */ 2172 unsigned int nd = 0; 2173 /* 2174 * Number of found IB device Ports. nd = 1 and np = 1..n means 2175 * we have the single multiport IB device, and there may be 2176 * representors attached to some of found ports. 2177 */ 2178 unsigned int np = 0; 2179 /* 2180 * Number of DPDK ethernet devices to Spawn - either over 2181 * multiple IB devices or multiple ports of single IB device. 2182 * Actually this is the number of iterations to spawn. 2183 */ 2184 unsigned int ns = 0; 2185 /* 2186 * Bonding device 2187 * < 0 - no bonding device (single one) 2188 * >= 0 - bonding device (value is slave PF index) 2189 */ 2190 int bd = -1; 2191 struct mlx5_dev_spawn_data *list = NULL; 2192 struct mlx5_dev_config dev_config; 2193 unsigned int dev_config_vf; 2194 struct rte_eth_devargs eth_da = *req_eth_da; 2195 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 2196 struct mlx5_bond_info bond_info; 2197 int ret = -1; 2198 2199 errno = 0; 2200 ibv_list = mlx5_glue->get_device_list(&ret); 2201 if (!ibv_list) { 2202 rte_errno = errno ? errno : ENOSYS; 2203 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 2204 return -rte_errno; 2205 } 2206 /* 2207 * First scan the list of all Infiniband devices to find 2208 * matching ones, gathering into the list. 2209 */ 2210 struct ibv_device *ibv_match[ret + 1]; 2211 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2212 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2213 unsigned int i; 2214 2215 while (ret-- > 0) { 2216 struct rte_pci_addr pci_addr; 2217 2218 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 2219 bd = mlx5_device_bond_pci_match 2220 (ibv_list[ret], &owner_pci, nl_rdma, owner_id, 2221 &bond_info); 2222 if (bd >= 0) { 2223 /* 2224 * Bonding device detected. Only one match is allowed, 2225 * the bonding is supported over multi-port IB device, 2226 * there should be no matches on representor PCI 2227 * functions or non VF LAG bonding devices with 2228 * specified address. 2229 */ 2230 if (nd) { 2231 DRV_LOG(ERR, 2232 "multiple PCI match on bonding device" 2233 "\"%s\" found", ibv_list[ret]->name); 2234 rte_errno = ENOENT; 2235 ret = -rte_errno; 2236 goto exit; 2237 } 2238 /* Amend owner pci address if owner PF ID specified. */ 2239 if (eth_da.nb_representor_ports) 2240 owner_pci.function += owner_id; 2241 DRV_LOG(INFO, "PCI information matches for" 2242 " slave %d bonding device \"%s\"", 2243 bd, ibv_list[ret]->name); 2244 ibv_match[nd++] = ibv_list[ret]; 2245 break; 2246 } else { 2247 /* Bonding device not found. */ 2248 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 2249 &pci_addr)) 2250 continue; 2251 if (owner_pci.domain != pci_addr.domain || 2252 owner_pci.bus != pci_addr.bus || 2253 owner_pci.devid != pci_addr.devid || 2254 owner_pci.function != pci_addr.function) 2255 continue; 2256 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2257 ibv_list[ret]->name); 2258 ibv_match[nd++] = ibv_list[ret]; 2259 } 2260 } 2261 ibv_match[nd] = NULL; 2262 if (!nd) { 2263 /* No device matches, just complain and bail out. */ 2264 DRV_LOG(WARNING, 2265 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2266 " are kernel drivers loaded?", 2267 owner_pci.domain, owner_pci.bus, 2268 owner_pci.devid, owner_pci.function); 2269 rte_errno = ENOENT; 2270 ret = -rte_errno; 2271 goto exit; 2272 } 2273 if (nd == 1) { 2274 /* 2275 * Found single matching device may have multiple ports. 2276 * Each port may be representor, we have to check the port 2277 * number and check the representors existence. 2278 */ 2279 if (nl_rdma >= 0) 2280 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2281 if (!np) 2282 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2283 " ports number", ibv_match[0]->name); 2284 if (bd >= 0 && !np) { 2285 DRV_LOG(ERR, "can not get ports" 2286 " for bonding device"); 2287 rte_errno = ENOENT; 2288 ret = -rte_errno; 2289 goto exit; 2290 } 2291 } 2292 /* 2293 * Now we can determine the maximal 2294 * amount of devices to be spawned. 2295 */ 2296 list = mlx5_malloc(MLX5_MEM_ZERO, 2297 sizeof(struct mlx5_dev_spawn_data) * 2298 (np ? np : nd), 2299 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2300 if (!list) { 2301 DRV_LOG(ERR, "spawn data array allocation failure"); 2302 rte_errno = ENOMEM; 2303 ret = -rte_errno; 2304 goto exit; 2305 } 2306 if (bd >= 0 || np > 1) { 2307 /* 2308 * Single IB device with multiple ports found, 2309 * it may be E-Switch master device and representors. 2310 * We have to perform identification through the ports. 2311 */ 2312 MLX5_ASSERT(nl_rdma >= 0); 2313 MLX5_ASSERT(ns == 0); 2314 MLX5_ASSERT(nd == 1); 2315 MLX5_ASSERT(np); 2316 for (i = 1; i <= np; ++i) { 2317 list[ns].bond_info = &bond_info; 2318 list[ns].max_port = np; 2319 list[ns].phys_port = i; 2320 list[ns].phys_dev = ibv_match[0]; 2321 list[ns].eth_dev = NULL; 2322 list[ns].pci_dev = pci_dev; 2323 list[ns].pf_bond = bd; 2324 list[ns].ifindex = mlx5_nl_ifindex 2325 (nl_rdma, 2326 mlx5_os_get_dev_device_name 2327 (list[ns].phys_dev), i); 2328 if (!list[ns].ifindex) { 2329 /* 2330 * No network interface index found for the 2331 * specified port, it means there is no 2332 * representor on this port. It's OK, 2333 * there can be disabled ports, for example 2334 * if sriov_numvfs < sriov_totalvfs. 2335 */ 2336 continue; 2337 } 2338 ret = -1; 2339 if (nl_route >= 0) 2340 ret = mlx5_nl_switch_info 2341 (nl_route, 2342 list[ns].ifindex, 2343 &list[ns].info); 2344 if (ret || (!list[ns].info.representor && 2345 !list[ns].info.master)) { 2346 /* 2347 * We failed to recognize representors with 2348 * Netlink, let's try to perform the task 2349 * with sysfs. 2350 */ 2351 ret = mlx5_sysfs_switch_info 2352 (list[ns].ifindex, 2353 &list[ns].info); 2354 } 2355 if (!ret && bd >= 0) { 2356 switch (list[ns].info.name_type) { 2357 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2358 if (np == 1) { 2359 /* 2360 * Force standalone bonding 2361 * device for ROCE LAG 2362 * confgiurations. 2363 */ 2364 list[ns].info.master = 0; 2365 list[ns].info.representor = 0; 2366 } 2367 if (list[ns].info.port_name == bd) 2368 ns++; 2369 break; 2370 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2371 /* Fallthrough */ 2372 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2373 /* Fallthrough */ 2374 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2375 if (list[ns].info.pf_num == bd) 2376 ns++; 2377 break; 2378 default: 2379 break; 2380 } 2381 continue; 2382 } 2383 if (!ret && (list[ns].info.representor ^ 2384 list[ns].info.master)) 2385 ns++; 2386 } 2387 if (!ns) { 2388 DRV_LOG(ERR, 2389 "unable to recognize master/representors" 2390 " on the IB device with multiple ports"); 2391 rte_errno = ENOENT; 2392 ret = -rte_errno; 2393 goto exit; 2394 } 2395 } else { 2396 /* 2397 * The existence of several matching entries (nd > 1) means 2398 * port representors have been instantiated. No existing Verbs 2399 * call nor sysfs entries can tell them apart, this can only 2400 * be done through Netlink calls assuming kernel drivers are 2401 * recent enough to support them. 2402 * 2403 * In the event of identification failure through Netlink, 2404 * try again through sysfs, then: 2405 * 2406 * 1. A single IB device matches (nd == 1) with single 2407 * port (np=0/1) and is not a representor, assume 2408 * no switch support. 2409 * 2410 * 2. Otherwise no safe assumptions can be made; 2411 * complain louder and bail out. 2412 */ 2413 for (i = 0; i != nd; ++i) { 2414 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2415 list[ns].bond_info = NULL; 2416 list[ns].max_port = 1; 2417 list[ns].phys_port = 1; 2418 list[ns].phys_dev = ibv_match[i]; 2419 list[ns].eth_dev = NULL; 2420 list[ns].pci_dev = pci_dev; 2421 list[ns].pf_bond = -1; 2422 list[ns].ifindex = 0; 2423 if (nl_rdma >= 0) 2424 list[ns].ifindex = mlx5_nl_ifindex 2425 (nl_rdma, 2426 mlx5_os_get_dev_device_name 2427 (list[ns].phys_dev), 1); 2428 if (!list[ns].ifindex) { 2429 char ifname[IF_NAMESIZE]; 2430 2431 /* 2432 * Netlink failed, it may happen with old 2433 * ib_core kernel driver (before 4.16). 2434 * We can assume there is old driver because 2435 * here we are processing single ports IB 2436 * devices. Let's try sysfs to retrieve 2437 * the ifindex. The method works for 2438 * master device only. 2439 */ 2440 if (nd > 1) { 2441 /* 2442 * Multiple devices found, assume 2443 * representors, can not distinguish 2444 * master/representor and retrieve 2445 * ifindex via sysfs. 2446 */ 2447 continue; 2448 } 2449 ret = mlx5_get_ifname_sysfs 2450 (ibv_match[i]->ibdev_path, ifname); 2451 if (!ret) 2452 list[ns].ifindex = 2453 if_nametoindex(ifname); 2454 if (!list[ns].ifindex) { 2455 /* 2456 * No network interface index found 2457 * for the specified device, it means 2458 * there it is neither representor 2459 * nor master. 2460 */ 2461 continue; 2462 } 2463 } 2464 ret = -1; 2465 if (nl_route >= 0) 2466 ret = mlx5_nl_switch_info 2467 (nl_route, 2468 list[ns].ifindex, 2469 &list[ns].info); 2470 if (ret || (!list[ns].info.representor && 2471 !list[ns].info.master)) { 2472 /* 2473 * We failed to recognize representors with 2474 * Netlink, let's try to perform the task 2475 * with sysfs. 2476 */ 2477 ret = mlx5_sysfs_switch_info 2478 (list[ns].ifindex, 2479 &list[ns].info); 2480 } 2481 if (!ret && (list[ns].info.representor ^ 2482 list[ns].info.master)) { 2483 ns++; 2484 } else if ((nd == 1) && 2485 !list[ns].info.representor && 2486 !list[ns].info.master) { 2487 /* 2488 * Single IB device with 2489 * one physical port and 2490 * attached network device. 2491 * May be SRIOV is not enabled 2492 * or there is no representors. 2493 */ 2494 DRV_LOG(INFO, "no E-Switch support detected"); 2495 ns++; 2496 break; 2497 } 2498 } 2499 if (!ns) { 2500 DRV_LOG(ERR, 2501 "unable to recognize master/representors" 2502 " on the multiple IB devices"); 2503 rte_errno = ENOENT; 2504 ret = -rte_errno; 2505 goto exit; 2506 } 2507 /* 2508 * New kernels may add the switch_id attribute for the case 2509 * there is no E-Switch and we wrongly recognized the 2510 * only device as master. Override this if there is the 2511 * single device with single port and new device name 2512 * format present. 2513 */ 2514 if (nd == 1 && 2515 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2516 list[0].info.master = 0; 2517 list[0].info.representor = 0; 2518 } 2519 } 2520 MLX5_ASSERT(ns); 2521 /* 2522 * Sort list to probe devices in natural order for users convenience 2523 * (i.e. master first, then representors from lowest to highest ID). 2524 */ 2525 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2526 /* Device specific configuration. */ 2527 switch (pci_dev->id.device_id) { 2528 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2529 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2530 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2531 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2532 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2533 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2534 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2535 dev_config_vf = 1; 2536 break; 2537 default: 2538 dev_config_vf = 0; 2539 break; 2540 } 2541 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2542 /* Set devargs default values. */ 2543 if (eth_da.nb_mh_controllers == 0) { 2544 eth_da.nb_mh_controllers = 1; 2545 eth_da.mh_controllers[0] = 0; 2546 } 2547 if (eth_da.nb_ports == 0 && ns > 0) { 2548 if (list[0].pf_bond >= 0 && list[0].info.representor) 2549 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2550 pci_dev->device.devargs->args); 2551 eth_da.nb_ports = 1; 2552 eth_da.ports[0] = list[0].info.pf_num; 2553 } 2554 if (eth_da.nb_representor_ports == 0) { 2555 eth_da.nb_representor_ports = 1; 2556 eth_da.representor_ports[0] = 0; 2557 } 2558 } 2559 for (i = 0; i != ns; ++i) { 2560 uint32_t restore; 2561 2562 /* Default configuration. */ 2563 mlx5_os_config_default(&dev_config); 2564 dev_config.vf = dev_config_vf; 2565 list[i].numa_node = pci_dev->device.numa_node; 2566 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2567 &list[i], 2568 &dev_config, 2569 ð_da); 2570 if (!list[i].eth_dev) { 2571 if (rte_errno != EBUSY && rte_errno != EEXIST) 2572 break; 2573 /* Device is disabled or already spawned. Ignore it. */ 2574 continue; 2575 } 2576 restore = list[i].eth_dev->data->dev_flags; 2577 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2578 /** 2579 * Each representor has a dedicated interrupts vector. 2580 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2581 * representor eth_dev object because representor and PF 2582 * share the same PCI address. 2583 * Override representor device with a dedicated 2584 * interrupts handle here. 2585 * Representor interrupts handle is released in mlx5_dev_stop(). 2586 */ 2587 if (list[i].info.representor) { 2588 struct rte_intr_handle *intr_handle; 2589 intr_handle = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 2590 sizeof(*intr_handle), 0, 2591 SOCKET_ID_ANY); 2592 if (!intr_handle) { 2593 DRV_LOG(ERR, 2594 "port %u failed to allocate memory for interrupt handler " 2595 "Rx interrupts will not be supported", 2596 i); 2597 rte_errno = ENOMEM; 2598 ret = -rte_errno; 2599 goto exit; 2600 } 2601 list[i].eth_dev->intr_handle = intr_handle; 2602 } 2603 /* Restore non-PCI flags cleared by the above call. */ 2604 list[i].eth_dev->data->dev_flags |= restore; 2605 rte_eth_dev_probing_finish(list[i].eth_dev); 2606 } 2607 if (i != ns) { 2608 DRV_LOG(ERR, 2609 "probe of PCI device " PCI_PRI_FMT " aborted after" 2610 " encountering an error: %s", 2611 owner_pci.domain, owner_pci.bus, 2612 owner_pci.devid, owner_pci.function, 2613 strerror(rte_errno)); 2614 ret = -rte_errno; 2615 /* Roll back. */ 2616 while (i--) { 2617 if (!list[i].eth_dev) 2618 continue; 2619 mlx5_dev_close(list[i].eth_dev); 2620 /* mac_addrs must not be freed because in dev_private */ 2621 list[i].eth_dev->data->mac_addrs = NULL; 2622 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2623 } 2624 /* Restore original error. */ 2625 rte_errno = -ret; 2626 } else { 2627 ret = 0; 2628 } 2629 exit: 2630 /* 2631 * Do the routine cleanup: 2632 * - close opened Netlink sockets 2633 * - free allocated spawn data array 2634 * - free the Infiniband device list 2635 */ 2636 if (nl_rdma >= 0) 2637 close(nl_rdma); 2638 if (nl_route >= 0) 2639 close(nl_route); 2640 if (list) 2641 mlx5_free(list); 2642 MLX5_ASSERT(ibv_list); 2643 mlx5_glue->free_device_list(ibv_list); 2644 return ret; 2645 } 2646 2647 static int 2648 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2649 struct rte_eth_devargs *eth_da) 2650 { 2651 int ret = 0; 2652 2653 if (dev->devargs == NULL) 2654 return 0; 2655 memset(eth_da, 0, sizeof(*eth_da)); 2656 /* Parse representor information first from class argument. */ 2657 if (dev->devargs->cls_str) 2658 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2659 if (ret != 0) { 2660 DRV_LOG(ERR, "failed to parse device arguments: %s", 2661 dev->devargs->cls_str); 2662 return -rte_errno; 2663 } 2664 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2665 /* Parse legacy device argument */ 2666 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2667 if (ret) { 2668 DRV_LOG(ERR, "failed to parse device arguments: %s", 2669 dev->devargs->args); 2670 return -rte_errno; 2671 } 2672 } 2673 return 0; 2674 } 2675 2676 /** 2677 * Callback to register a PCI device. 2678 * 2679 * This function spawns Ethernet devices out of a given PCI device. 2680 * 2681 * @param[in] pci_dev 2682 * PCI device information. 2683 * 2684 * @return 2685 * 0 on success, a negative errno value otherwise and rte_errno is set. 2686 */ 2687 static int 2688 mlx5_os_pci_probe(struct rte_pci_device *pci_dev) 2689 { 2690 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2691 int ret = 0; 2692 uint16_t p; 2693 2694 ret = mlx5_os_parse_eth_devargs(&pci_dev->device, ð_da); 2695 if (ret != 0) 2696 return ret; 2697 2698 if (eth_da.nb_ports > 0) { 2699 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2700 for (p = 0; p < eth_da.nb_ports; p++) { 2701 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2702 eth_da.ports[p]); 2703 if (ret) 2704 break; 2705 } 2706 if (ret) { 2707 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2708 "aborted due to proding failure of PF %u", 2709 pci_dev->addr.domain, pci_dev->addr.bus, 2710 pci_dev->addr.devid, pci_dev->addr.function, 2711 eth_da.ports[p]); 2712 mlx5_net_remove(&pci_dev->device); 2713 } 2714 } else { 2715 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2716 } 2717 return ret; 2718 } 2719 2720 /* Probe a single SF device on auxiliary bus, no representor support. */ 2721 static int 2722 mlx5_os_auxiliary_probe(struct rte_device *dev) 2723 { 2724 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2725 struct mlx5_dev_config config; 2726 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2727 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2728 struct rte_eth_dev *eth_dev; 2729 int ret = 0; 2730 2731 /* Parse ethdev devargs. */ 2732 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2733 if (ret != 0) 2734 return ret; 2735 /* Set default config data. */ 2736 mlx5_os_config_default(&config); 2737 config.sf = 1; 2738 /* Init spawn data. */ 2739 spawn.max_port = 1; 2740 spawn.phys_port = 1; 2741 spawn.phys_dev = mlx5_os_get_ibv_dev(dev); 2742 if (spawn.phys_dev == NULL) 2743 return -rte_errno; 2744 ret = mlx5_auxiliary_get_ifindex(dev->name); 2745 if (ret < 0) { 2746 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2747 return ret; 2748 } 2749 spawn.ifindex = ret; 2750 spawn.numa_node = dev->numa_node; 2751 /* Spawn device. */ 2752 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da); 2753 if (eth_dev == NULL) 2754 return -rte_errno; 2755 /* Post create. */ 2756 eth_dev->intr_handle = &adev->intr_handle; 2757 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2758 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2759 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2760 eth_dev->data->numa_node = dev->numa_node; 2761 } 2762 rte_eth_dev_probing_finish(eth_dev); 2763 return 0; 2764 } 2765 2766 /** 2767 * Net class driver callback to probe a device. 2768 * 2769 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2770 * 2771 * @param[in] dev 2772 * Pointer to the generic device. 2773 * 2774 * @return 2775 * 0 on success, the function cannot fail. 2776 */ 2777 int 2778 mlx5_os_net_probe(struct rte_device *dev) 2779 { 2780 int ret; 2781 2782 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2783 mlx5_pmd_socket_init(); 2784 ret = mlx5_init_once(); 2785 if (ret) { 2786 DRV_LOG(ERR, "unable to init PMD global data: %s", 2787 strerror(rte_errno)); 2788 return -rte_errno; 2789 } 2790 if (mlx5_dev_is_pci(dev)) 2791 return mlx5_os_pci_probe(RTE_DEV_TO_PCI(dev)); 2792 else 2793 return mlx5_os_auxiliary_probe(dev); 2794 } 2795 2796 static int 2797 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2798 { 2799 char *env; 2800 int value; 2801 2802 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2803 /* Get environment variable to store. */ 2804 env = getenv(MLX5_SHUT_UP_BF); 2805 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2806 if (config->dbnc == MLX5_ARG_UNSET) 2807 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2808 else 2809 setenv(MLX5_SHUT_UP_BF, 2810 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2811 return value; 2812 } 2813 2814 static void 2815 mlx5_restore_doorbell_mapping_env(int value) 2816 { 2817 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2818 /* Restore the original environment variable state. */ 2819 if (value == MLX5_ARG_UNSET) 2820 unsetenv(MLX5_SHUT_UP_BF); 2821 else 2822 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2823 } 2824 2825 /** 2826 * Extract pdn of PD object using DV API. 2827 * 2828 * @param[in] pd 2829 * Pointer to the verbs PD object. 2830 * @param[out] pdn 2831 * Pointer to the PD object number variable. 2832 * 2833 * @return 2834 * 0 on success, error value otherwise. 2835 */ 2836 int 2837 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2838 { 2839 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2840 struct mlx5dv_obj obj; 2841 struct mlx5dv_pd pd_info; 2842 int ret = 0; 2843 2844 obj.pd.in = pd; 2845 obj.pd.out = &pd_info; 2846 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2847 if (ret) { 2848 DRV_LOG(DEBUG, "Fail to get PD object info"); 2849 return ret; 2850 } 2851 *pdn = pd_info.pdn; 2852 return 0; 2853 #else 2854 (void)pd; 2855 (void)pdn; 2856 return -ENOTSUP; 2857 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2858 } 2859 2860 /** 2861 * Function API to open IB device. 2862 * 2863 * This function calls the Linux glue APIs to open a device. 2864 * 2865 * @param[in] spawn 2866 * Pointer to the IB device attributes (name, port, etc). 2867 * @param[out] config 2868 * Pointer to device configuration structure. 2869 * @param[out] sh 2870 * Pointer to shared context structure. 2871 * 2872 * @return 2873 * 0 on success, a positive error value otherwise. 2874 */ 2875 int 2876 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2877 const struct mlx5_dev_config *config, 2878 struct mlx5_dev_ctx_shared *sh) 2879 { 2880 int dbmap_env; 2881 int err = 0; 2882 2883 pthread_mutex_init(&sh->txpp.mutex, NULL); 2884 /* 2885 * Configure environment variable "MLX5_BF_SHUT_UP" 2886 * before the device creation. The rdma_core library 2887 * checks the variable at device creation and 2888 * stores the result internally. 2889 */ 2890 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2891 /* Try to open IB device with DV first, then usual Verbs. */ 2892 errno = 0; 2893 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2894 if (sh->ctx) { 2895 sh->devx = 1; 2896 DRV_LOG(DEBUG, "DevX is supported"); 2897 /* The device is created, no need for environment. */ 2898 mlx5_restore_doorbell_mapping_env(dbmap_env); 2899 } else { 2900 /* The environment variable is still configured. */ 2901 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2902 err = errno ? errno : ENODEV; 2903 /* 2904 * The environment variable is not needed anymore, 2905 * all device creation attempts are completed. 2906 */ 2907 mlx5_restore_doorbell_mapping_env(dbmap_env); 2908 if (!sh->ctx) 2909 return err; 2910 DRV_LOG(DEBUG, "DevX is NOT supported"); 2911 err = 0; 2912 } 2913 if (!err && sh->ctx) { 2914 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2915 mlx5_glue->dv_set_context_attr(sh->ctx, 2916 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2917 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2918 .alloc = &mlx5_alloc_verbs_buf, 2919 .free = &mlx5_free_verbs_buf, 2920 .data = sh, 2921 })); 2922 } 2923 return err; 2924 } 2925 2926 /** 2927 * Install shared asynchronous device events handler. 2928 * This function is implemented to support event sharing 2929 * between multiple ports of single IB device. 2930 * 2931 * @param sh 2932 * Pointer to mlx5_dev_ctx_shared object. 2933 */ 2934 void 2935 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2936 { 2937 int ret; 2938 int flags; 2939 2940 sh->intr_handle.fd = -1; 2941 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2942 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2943 F_SETFL, flags | O_NONBLOCK); 2944 if (ret) { 2945 DRV_LOG(INFO, "failed to change file descriptor async event" 2946 " queue"); 2947 } else { 2948 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2949 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2950 if (rte_intr_callback_register(&sh->intr_handle, 2951 mlx5_dev_interrupt_handler, sh)) { 2952 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2953 sh->intr_handle.fd = -1; 2954 } 2955 } 2956 if (sh->devx) { 2957 #ifdef HAVE_IBV_DEVX_ASYNC 2958 sh->intr_handle_devx.fd = -1; 2959 sh->devx_comp = 2960 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2961 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2962 if (!devx_comp) { 2963 DRV_LOG(INFO, "failed to allocate devx_comp."); 2964 return; 2965 } 2966 flags = fcntl(devx_comp->fd, F_GETFL); 2967 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2968 if (ret) { 2969 DRV_LOG(INFO, "failed to change file descriptor" 2970 " devx comp"); 2971 return; 2972 } 2973 sh->intr_handle_devx.fd = devx_comp->fd; 2974 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2975 if (rte_intr_callback_register(&sh->intr_handle_devx, 2976 mlx5_dev_interrupt_handler_devx, sh)) { 2977 DRV_LOG(INFO, "Fail to install the devx shared" 2978 " interrupt."); 2979 sh->intr_handle_devx.fd = -1; 2980 } 2981 #endif /* HAVE_IBV_DEVX_ASYNC */ 2982 } 2983 } 2984 2985 /** 2986 * Uninstall shared asynchronous device events handler. 2987 * This function is implemented to support event sharing 2988 * between multiple ports of single IB device. 2989 * 2990 * @param dev 2991 * Pointer to mlx5_dev_ctx_shared object. 2992 */ 2993 void 2994 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2995 { 2996 if (sh->intr_handle.fd >= 0) 2997 mlx5_intr_callback_unregister(&sh->intr_handle, 2998 mlx5_dev_interrupt_handler, sh); 2999 #ifdef HAVE_IBV_DEVX_ASYNC 3000 if (sh->intr_handle_devx.fd >= 0) 3001 rte_intr_callback_unregister(&sh->intr_handle_devx, 3002 mlx5_dev_interrupt_handler_devx, sh); 3003 if (sh->devx_comp) 3004 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 3005 #endif 3006 } 3007 3008 /** 3009 * Read statistics by a named counter. 3010 * 3011 * @param[in] priv 3012 * Pointer to the private device data structure. 3013 * @param[in] ctr_name 3014 * Pointer to the name of the statistic counter to read 3015 * @param[out] stat 3016 * Pointer to read statistic value. 3017 * @return 3018 * 0 on success and stat is valud, 1 if failed to read the value 3019 * rte_errno is set. 3020 * 3021 */ 3022 int 3023 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 3024 uint64_t *stat) 3025 { 3026 int fd; 3027 3028 if (priv->sh) { 3029 if (priv->q_counters != NULL && 3030 strcmp(ctr_name, "out_of_buffer") == 0) 3031 return mlx5_devx_cmd_queue_counter_query 3032 (priv->q_counters, 0, (uint32_t *)stat); 3033 MKSTR(path, "%s/ports/%d/hw_counters/%s", 3034 priv->sh->ibdev_path, 3035 priv->dev_port, 3036 ctr_name); 3037 fd = open(path, O_RDONLY); 3038 /* 3039 * in switchdev the file location is not per port 3040 * but rather in <ibdev_path>/hw_counters/<file_name>. 3041 */ 3042 if (fd == -1) { 3043 MKSTR(path1, "%s/hw_counters/%s", 3044 priv->sh->ibdev_path, 3045 ctr_name); 3046 fd = open(path1, O_RDONLY); 3047 } 3048 if (fd != -1) { 3049 char buf[21] = {'\0'}; 3050 ssize_t n = read(fd, buf, sizeof(buf)); 3051 3052 close(fd); 3053 if (n != -1) { 3054 *stat = strtoull(buf, NULL, 10); 3055 return 0; 3056 } 3057 } 3058 } 3059 *stat = 0; 3060 return 1; 3061 } 3062 3063 /** 3064 * Set the reg_mr and dereg_mr call backs 3065 * 3066 * @param reg_mr_cb[out] 3067 * Pointer to reg_mr func 3068 * @param dereg_mr_cb[out] 3069 * Pointer to dereg_mr func 3070 * 3071 */ 3072 void 3073 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 3074 mlx5_dereg_mr_t *dereg_mr_cb) 3075 { 3076 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 3077 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 3078 } 3079 3080 /** 3081 * Remove a MAC address from device 3082 * 3083 * @param dev 3084 * Pointer to Ethernet device structure. 3085 * @param index 3086 * MAC address index. 3087 */ 3088 void 3089 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 3090 { 3091 struct mlx5_priv *priv = dev->data->dev_private; 3092 const int vf = priv->config.vf; 3093 3094 if (vf) 3095 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 3096 mlx5_ifindex(dev), priv->mac_own, 3097 &dev->data->mac_addrs[index], index); 3098 } 3099 3100 /** 3101 * Adds a MAC address to the device 3102 * 3103 * @param dev 3104 * Pointer to Ethernet device structure. 3105 * @param mac_addr 3106 * MAC address to register. 3107 * @param index 3108 * MAC address index. 3109 * 3110 * @return 3111 * 0 on success, a negative errno value otherwise 3112 */ 3113 int 3114 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 3115 uint32_t index) 3116 { 3117 struct mlx5_priv *priv = dev->data->dev_private; 3118 const int vf = priv->config.vf; 3119 int ret = 0; 3120 3121 if (vf) 3122 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 3123 mlx5_ifindex(dev), priv->mac_own, 3124 mac, index); 3125 return ret; 3126 } 3127 3128 /** 3129 * Modify a VF MAC address 3130 * 3131 * @param priv 3132 * Pointer to device private data. 3133 * @param mac_addr 3134 * MAC address to modify into. 3135 * @param iface_idx 3136 * Net device interface index 3137 * @param vf_index 3138 * VF index 3139 * 3140 * @return 3141 * 0 on success, a negative errno value otherwise 3142 */ 3143 int 3144 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 3145 unsigned int iface_idx, 3146 struct rte_ether_addr *mac_addr, 3147 int vf_index) 3148 { 3149 return mlx5_nl_vf_mac_addr_modify 3150 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 3151 } 3152 3153 /** 3154 * Set device promiscuous mode 3155 * 3156 * @param dev 3157 * Pointer to Ethernet device structure. 3158 * @param enable 3159 * 0 - promiscuous is disabled, otherwise - enabled 3160 * 3161 * @return 3162 * 0 on success, a negative error value otherwise 3163 */ 3164 int 3165 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 3166 { 3167 struct mlx5_priv *priv = dev->data->dev_private; 3168 3169 return mlx5_nl_promisc(priv->nl_socket_route, 3170 mlx5_ifindex(dev), !!enable); 3171 } 3172 3173 /** 3174 * Set device promiscuous mode 3175 * 3176 * @param dev 3177 * Pointer to Ethernet device structure. 3178 * @param enable 3179 * 0 - all multicase is disabled, otherwise - enabled 3180 * 3181 * @return 3182 * 0 on success, a negative error value otherwise 3183 */ 3184 int 3185 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 3186 { 3187 struct mlx5_priv *priv = dev->data->dev_private; 3188 3189 return mlx5_nl_allmulti(priv->nl_socket_route, 3190 mlx5_ifindex(dev), !!enable); 3191 } 3192 3193 /** 3194 * Flush device MAC addresses 3195 * 3196 * @param dev 3197 * Pointer to Ethernet device structure. 3198 * 3199 */ 3200 void 3201 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 3202 { 3203 struct mlx5_priv *priv = dev->data->dev_private; 3204 3205 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 3206 dev->data->mac_addrs, 3207 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 3208 } 3209