1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_autoconf.h" 44 #include "mlx5_mr.h" 45 #include "mlx5_flow.h" 46 #include "rte_pmd_mlx5.h" 47 #include "mlx5_verbs.h" 48 #include "mlx5_nl.h" 49 #include "mlx5_devx.h" 50 51 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /** 71 * Set the completion channel file descriptor interrupt as non-blocking. 72 * 73 * @param[in] rxq_obj 74 * Pointer to RQ channel object, which includes the channel fd 75 * 76 * @param[out] fd 77 * The file descriptor (representing the intetrrupt) used in this channel. 78 * 79 * @return 80 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 81 */ 82 int 83 mlx5_os_set_nonblock_channel_fd(int fd) 84 { 85 int flags; 86 87 flags = fcntl(fd, F_GETFL); 88 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 89 } 90 91 /** 92 * Get mlx5 device attributes. The glue function query_device_ex() is called 93 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 94 * device attributes from the glue out parameter. 95 * 96 * @param dev 97 * Pointer to ibv context. 98 * 99 * @param device_attr 100 * Pointer to mlx5 device attributes. 101 * 102 * @return 103 * 0 on success, non zero error number otherwise 104 */ 105 int 106 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 107 { 108 int err; 109 struct ibv_device_attr_ex attr_ex; 110 memset(device_attr, 0, sizeof(*device_attr)); 111 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 112 if (err) 113 return err; 114 115 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 116 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 117 device_attr->max_sge = attr_ex.orig_attr.max_sge; 118 device_attr->max_cq = attr_ex.orig_attr.max_cq; 119 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 120 device_attr->max_mr = attr_ex.orig_attr.max_mr; 121 device_attr->max_pd = attr_ex.orig_attr.max_pd; 122 device_attr->max_qp = attr_ex.orig_attr.max_qp; 123 device_attr->max_srq = attr_ex.orig_attr.max_srq; 124 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 125 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 126 device_attr->max_rwq_indirection_table_size = 127 attr_ex.rss_caps.max_rwq_indirection_table_size; 128 device_attr->max_tso = attr_ex.tso_caps.max_tso; 129 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 130 131 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 132 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 133 if (err) 134 return err; 135 136 device_attr->flags = dv_attr.flags; 137 device_attr->comp_mask = dv_attr.comp_mask; 138 #ifdef HAVE_IBV_MLX5_MOD_SWP 139 device_attr->sw_parsing_offloads = 140 dv_attr.sw_parsing_caps.sw_parsing_offloads; 141 #endif 142 device_attr->min_single_stride_log_num_of_bytes = 143 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 144 device_attr->max_single_stride_log_num_of_bytes = 145 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 146 device_attr->min_single_wqe_log_num_of_strides = 147 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 148 device_attr->max_single_wqe_log_num_of_strides = 149 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 150 device_attr->stride_supported_qpts = 151 dv_attr.striding_rq_caps.supported_qpts; 152 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 153 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 154 #endif 155 156 return err; 157 } 158 159 /** 160 * Verbs callback to allocate a memory. This function should allocate the space 161 * according to the size provided residing inside a huge page. 162 * Please note that all allocation must respect the alignment from libmlx5 163 * (i.e. currently rte_mem_page_size()). 164 * 165 * @param[in] size 166 * The size in bytes of the memory to allocate. 167 * @param[in] data 168 * A pointer to the callback data. 169 * 170 * @return 171 * Allocated buffer, NULL otherwise and rte_errno is set. 172 */ 173 static void * 174 mlx5_alloc_verbs_buf(size_t size, void *data) 175 { 176 struct mlx5_dev_ctx_shared *sh = data; 177 void *ret; 178 size_t alignment = rte_mem_page_size(); 179 if (alignment == (size_t)-1) { 180 DRV_LOG(ERR, "Failed to get mem page size"); 181 rte_errno = ENOMEM; 182 return NULL; 183 } 184 185 MLX5_ASSERT(data != NULL); 186 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 187 if (!ret && size) 188 rte_errno = ENOMEM; 189 return ret; 190 } 191 192 /** 193 * Verbs callback to free a memory. 194 * 195 * @param[in] ptr 196 * A pointer to the memory to free. 197 * @param[in] data 198 * A pointer to the callback data. 199 */ 200 static void 201 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 202 { 203 MLX5_ASSERT(data != NULL); 204 mlx5_free(ptr); 205 } 206 207 /** 208 * Initialize DR related data within private structure. 209 * Routine checks the reference counter and does actual 210 * resources creation/initialization only if counter is zero. 211 * 212 * @param[in] priv 213 * Pointer to the private device data structure. 214 * 215 * @return 216 * Zero on success, positive error code otherwise. 217 */ 218 static int 219 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 220 { 221 struct mlx5_dev_ctx_shared *sh = priv->sh; 222 char s[MLX5_HLIST_NAMESIZE] __rte_unused; 223 int err; 224 225 MLX5_ASSERT(sh && sh->refcnt); 226 if (sh->refcnt > 1) 227 return 0; 228 err = mlx5_alloc_table_hash_list(priv); 229 if (err) 230 goto error; 231 /* The resources below are only valid with DV support. */ 232 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 233 /* Init port id action cache list. */ 234 snprintf(s, sizeof(s), "%s_port_id_action_cache", sh->ibdev_name); 235 mlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh, 236 flow_dv_port_id_create_cb, 237 flow_dv_port_id_match_cb, 238 flow_dv_port_id_remove_cb); 239 /* Init push vlan action cache list. */ 240 snprintf(s, sizeof(s), "%s_push_vlan_action_cache", sh->ibdev_name); 241 mlx5_cache_list_init(&sh->push_vlan_action_list, s, 0, sh, 242 flow_dv_push_vlan_create_cb, 243 flow_dv_push_vlan_match_cb, 244 flow_dv_push_vlan_remove_cb); 245 /* Init sample action cache list. */ 246 snprintf(s, sizeof(s), "%s_sample_action_cache", sh->ibdev_name); 247 mlx5_cache_list_init(&sh->sample_action_list, s, 0, sh, 248 flow_dv_sample_create_cb, 249 flow_dv_sample_match_cb, 250 flow_dv_sample_remove_cb); 251 /* Init dest array action cache list. */ 252 snprintf(s, sizeof(s), "%s_dest_array_cache", sh->ibdev_name); 253 mlx5_cache_list_init(&sh->dest_array_list, s, 0, sh, 254 flow_dv_dest_array_create_cb, 255 flow_dv_dest_array_match_cb, 256 flow_dv_dest_array_remove_cb); 257 /* Create tags hash list table. */ 258 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 259 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0, 260 MLX5_HLIST_WRITE_MOST, 261 flow_dv_tag_create_cb, 262 flow_dv_tag_match_cb, 263 flow_dv_tag_remove_cb); 264 if (!sh->tag_table) { 265 DRV_LOG(ERR, "tags with hash creation failed."); 266 err = ENOMEM; 267 goto error; 268 } 269 sh->tag_table->ctx = sh; 270 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 271 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ, 272 0, MLX5_HLIST_WRITE_MOST | 273 MLX5_HLIST_DIRECT_KEY, 274 flow_dv_modify_create_cb, 275 flow_dv_modify_match_cb, 276 flow_dv_modify_remove_cb); 277 if (!sh->modify_cmds) { 278 DRV_LOG(ERR, "hdr modify hash creation failed"); 279 err = ENOMEM; 280 goto error; 281 } 282 sh->modify_cmds->ctx = sh; 283 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 284 sh->encaps_decaps = mlx5_hlist_create(s, 285 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ, 286 0, MLX5_HLIST_DIRECT_KEY | 287 MLX5_HLIST_WRITE_MOST, 288 flow_dv_encap_decap_create_cb, 289 flow_dv_encap_decap_match_cb, 290 flow_dv_encap_decap_remove_cb); 291 if (!sh->encaps_decaps) { 292 DRV_LOG(ERR, "encap decap hash creation failed"); 293 err = ENOMEM; 294 goto error; 295 } 296 sh->encaps_decaps->ctx = sh; 297 #endif 298 #ifdef HAVE_MLX5DV_DR 299 void *domain; 300 301 /* Reference counter is zero, we should initialize structures. */ 302 domain = mlx5_glue->dr_create_domain(sh->ctx, 303 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 304 if (!domain) { 305 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 306 err = errno; 307 goto error; 308 } 309 sh->rx_domain = domain; 310 domain = mlx5_glue->dr_create_domain(sh->ctx, 311 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 312 if (!domain) { 313 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 314 err = errno; 315 goto error; 316 } 317 sh->tx_domain = domain; 318 #ifdef HAVE_MLX5DV_DR_ESWITCH 319 if (priv->config.dv_esw_en) { 320 domain = mlx5_glue->dr_create_domain 321 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 322 if (!domain) { 323 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 324 err = errno; 325 goto error; 326 } 327 sh->fdb_domain = domain; 328 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 329 } 330 #endif 331 if (!sh->tunnel_hub) 332 err = mlx5_alloc_tunnel_hub(sh); 333 if (err) { 334 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 335 goto error; 336 } 337 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 338 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 339 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 340 if (sh->fdb_domain) 341 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 342 } 343 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 344 #endif /* HAVE_MLX5DV_DR */ 345 sh->default_miss_action = 346 mlx5_glue->dr_create_flow_action_default_miss(); 347 if (!sh->default_miss_action) 348 DRV_LOG(WARNING, "Default miss action is not supported."); 349 return 0; 350 error: 351 /* Rollback the created objects. */ 352 if (sh->rx_domain) { 353 mlx5_glue->dr_destroy_domain(sh->rx_domain); 354 sh->rx_domain = NULL; 355 } 356 if (sh->tx_domain) { 357 mlx5_glue->dr_destroy_domain(sh->tx_domain); 358 sh->tx_domain = NULL; 359 } 360 if (sh->fdb_domain) { 361 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 362 sh->fdb_domain = NULL; 363 } 364 if (sh->esw_drop_action) { 365 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 366 sh->esw_drop_action = NULL; 367 } 368 if (sh->pop_vlan_action) { 369 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 370 sh->pop_vlan_action = NULL; 371 } 372 if (sh->encaps_decaps) { 373 mlx5_hlist_destroy(sh->encaps_decaps); 374 sh->encaps_decaps = NULL; 375 } 376 if (sh->modify_cmds) { 377 mlx5_hlist_destroy(sh->modify_cmds); 378 sh->modify_cmds = NULL; 379 } 380 if (sh->tag_table) { 381 /* tags should be destroyed with flow before. */ 382 mlx5_hlist_destroy(sh->tag_table); 383 sh->tag_table = NULL; 384 } 385 if (sh->tunnel_hub) { 386 mlx5_release_tunnel_hub(sh, priv->dev_port); 387 sh->tunnel_hub = NULL; 388 } 389 mlx5_free_table_hash_list(priv); 390 return err; 391 } 392 393 /** 394 * Destroy DR related data within private structure. 395 * 396 * @param[in] priv 397 * Pointer to the private device data structure. 398 */ 399 void 400 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 401 { 402 struct mlx5_dev_ctx_shared *sh = priv->sh; 403 404 MLX5_ASSERT(sh && sh->refcnt); 405 if (sh->refcnt > 1) 406 return; 407 #ifdef HAVE_MLX5DV_DR 408 if (sh->rx_domain) { 409 mlx5_glue->dr_destroy_domain(sh->rx_domain); 410 sh->rx_domain = NULL; 411 } 412 if (sh->tx_domain) { 413 mlx5_glue->dr_destroy_domain(sh->tx_domain); 414 sh->tx_domain = NULL; 415 } 416 #ifdef HAVE_MLX5DV_DR_ESWITCH 417 if (sh->fdb_domain) { 418 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 419 sh->fdb_domain = NULL; 420 } 421 if (sh->esw_drop_action) { 422 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 423 sh->esw_drop_action = NULL; 424 } 425 #endif 426 if (sh->pop_vlan_action) { 427 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 428 sh->pop_vlan_action = NULL; 429 } 430 #endif /* HAVE_MLX5DV_DR */ 431 if (sh->default_miss_action) 432 mlx5_glue->destroy_flow_action 433 (sh->default_miss_action); 434 if (sh->encaps_decaps) { 435 mlx5_hlist_destroy(sh->encaps_decaps); 436 sh->encaps_decaps = NULL; 437 } 438 if (sh->modify_cmds) { 439 mlx5_hlist_destroy(sh->modify_cmds); 440 sh->modify_cmds = NULL; 441 } 442 if (sh->tag_table) { 443 /* tags should be destroyed with flow before. */ 444 mlx5_hlist_destroy(sh->tag_table); 445 sh->tag_table = NULL; 446 } 447 if (sh->tunnel_hub) { 448 mlx5_release_tunnel_hub(sh, priv->dev_port); 449 sh->tunnel_hub = NULL; 450 } 451 mlx5_cache_list_destroy(&sh->port_id_action_list); 452 mlx5_cache_list_destroy(&sh->push_vlan_action_list); 453 mlx5_free_table_hash_list(priv); 454 } 455 456 /** 457 * Initialize shared data between primary and secondary process. 458 * 459 * A memzone is reserved by primary process and secondary processes attach to 460 * the memzone. 461 * 462 * @return 463 * 0 on success, a negative errno value otherwise and rte_errno is set. 464 */ 465 static int 466 mlx5_init_shared_data(void) 467 { 468 const struct rte_memzone *mz; 469 int ret = 0; 470 471 rte_spinlock_lock(&mlx5_shared_data_lock); 472 if (mlx5_shared_data == NULL) { 473 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 474 /* Allocate shared memory. */ 475 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 476 sizeof(*mlx5_shared_data), 477 SOCKET_ID_ANY, 0); 478 if (mz == NULL) { 479 DRV_LOG(ERR, 480 "Cannot allocate mlx5 shared data"); 481 ret = -rte_errno; 482 goto error; 483 } 484 mlx5_shared_data = mz->addr; 485 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 486 rte_spinlock_init(&mlx5_shared_data->lock); 487 } else { 488 /* Lookup allocated shared memory. */ 489 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 490 if (mz == NULL) { 491 DRV_LOG(ERR, 492 "Cannot attach mlx5 shared data"); 493 ret = -rte_errno; 494 goto error; 495 } 496 mlx5_shared_data = mz->addr; 497 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 498 } 499 } 500 error: 501 rte_spinlock_unlock(&mlx5_shared_data_lock); 502 return ret; 503 } 504 505 /** 506 * PMD global initialization. 507 * 508 * Independent from individual device, this function initializes global 509 * per-PMD data structures distinguishing primary and secondary processes. 510 * Hence, each initialization is called once per a process. 511 * 512 * @return 513 * 0 on success, a negative errno value otherwise and rte_errno is set. 514 */ 515 static int 516 mlx5_init_once(void) 517 { 518 struct mlx5_shared_data *sd; 519 struct mlx5_local_data *ld = &mlx5_local_data; 520 int ret = 0; 521 522 if (mlx5_init_shared_data()) 523 return -rte_errno; 524 sd = mlx5_shared_data; 525 MLX5_ASSERT(sd); 526 rte_spinlock_lock(&sd->lock); 527 switch (rte_eal_process_type()) { 528 case RTE_PROC_PRIMARY: 529 if (sd->init_done) 530 break; 531 LIST_INIT(&sd->mem_event_cb_list); 532 rte_rwlock_init(&sd->mem_event_rwlock); 533 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 534 mlx5_mr_mem_event_cb, NULL); 535 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 536 mlx5_mp_os_primary_handle); 537 if (ret) 538 goto out; 539 sd->init_done = true; 540 break; 541 case RTE_PROC_SECONDARY: 542 if (ld->init_done) 543 break; 544 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 545 mlx5_mp_os_secondary_handle); 546 if (ret) 547 goto out; 548 ++sd->secondary_cnt; 549 ld->init_done = true; 550 break; 551 default: 552 break; 553 } 554 out: 555 rte_spinlock_unlock(&sd->lock); 556 return ret; 557 } 558 559 /** 560 * Create the Tx queue DevX/Verbs object. 561 * 562 * @param dev 563 * Pointer to Ethernet device. 564 * @param idx 565 * Queue index in DPDK Tx queue array. 566 * 567 * @return 568 * 0 on success, a negative errno value otherwise and rte_errno is set. 569 */ 570 static int 571 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 572 { 573 struct mlx5_priv *priv = dev->data->dev_private; 574 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 575 struct mlx5_txq_ctrl *txq_ctrl = 576 container_of(txq_data, struct mlx5_txq_ctrl, txq); 577 578 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 579 return mlx5_txq_devx_obj_new(dev, idx); 580 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 581 if (!priv->config.dv_esw_en) 582 return mlx5_txq_devx_obj_new(dev, idx); 583 #endif 584 return mlx5_txq_ibv_obj_new(dev, idx); 585 } 586 587 /** 588 * Release an Tx DevX/verbs queue object. 589 * 590 * @param txq_obj 591 * DevX/Verbs Tx queue object. 592 */ 593 static void 594 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 595 { 596 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 597 mlx5_txq_devx_obj_release(txq_obj); 598 return; 599 } 600 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 601 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 602 mlx5_txq_devx_obj_release(txq_obj); 603 return; 604 } 605 #endif 606 mlx5_txq_ibv_obj_release(txq_obj); 607 } 608 609 /** 610 * DV flow counter mode detect and config. 611 * 612 * @param dev 613 * Pointer to rte_eth_dev structure. 614 * 615 */ 616 static void 617 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 618 { 619 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 620 struct mlx5_priv *priv = dev->data->dev_private; 621 struct mlx5_dev_ctx_shared *sh = priv->sh; 622 bool fallback; 623 624 #ifndef HAVE_IBV_DEVX_ASYNC 625 fallback = true; 626 #else 627 fallback = false; 628 if (!priv->config.devx || !priv->config.dv_flow_en || 629 !priv->config.hca_attr.flow_counters_dump || 630 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 631 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 632 fallback = true; 633 #endif 634 if (fallback) 635 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 636 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 637 priv->config.hca_attr.flow_counters_dump, 638 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 639 /* Initialize fallback mode only on the port initializes sh. */ 640 if (sh->refcnt == 1) 641 sh->cmng.counter_fallback = fallback; 642 else if (fallback != sh->cmng.counter_fallback) 643 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 644 "with others:%d.", PORT_ID(priv), fallback); 645 #endif 646 } 647 648 static void 649 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 650 { 651 struct mlx5_priv *priv = dev->data->dev_private; 652 void *ctx = priv->sh->ctx; 653 654 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 655 if (!priv->q_counters) { 656 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 657 struct ibv_wq *wq; 658 659 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 660 "by DevX - fall-back to use the kernel driver global " 661 "queue counter.", dev->data->port_id); 662 /* Create WQ by kernel and query its queue counter ID. */ 663 if (cq) { 664 wq = mlx5_glue->create_wq(ctx, 665 &(struct ibv_wq_init_attr){ 666 .wq_type = IBV_WQT_RQ, 667 .max_wr = 1, 668 .max_sge = 1, 669 .pd = priv->sh->pd, 670 .cq = cq, 671 }); 672 if (wq) { 673 /* Counter is assigned only on RDY state. */ 674 int ret = mlx5_glue->modify_wq(wq, 675 &(struct ibv_wq_attr){ 676 .attr_mask = IBV_WQ_ATTR_STATE, 677 .wq_state = IBV_WQS_RDY, 678 }); 679 680 if (ret == 0) 681 mlx5_devx_cmd_wq_query(wq, 682 &priv->counter_set_id); 683 claim_zero(mlx5_glue->destroy_wq(wq)); 684 } 685 claim_zero(mlx5_glue->destroy_cq(cq)); 686 } 687 } else { 688 priv->counter_set_id = priv->q_counters->id; 689 } 690 if (priv->counter_set_id == 0) 691 DRV_LOG(INFO, "Part of the port %d statistics will not be " 692 "available.", dev->data->port_id); 693 } 694 695 /** 696 * Check if representor spawn info match devargs. 697 * 698 * @param spawn 699 * Verbs device parameters (name, port, switch_info) to spawn. 700 * @param eth_da 701 * Device devargs to probe. 702 * 703 * @return 704 * Match result. 705 */ 706 static bool 707 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 708 struct rte_eth_devargs *eth_da) 709 { 710 struct mlx5_switch_info *switch_info = &spawn->info; 711 unsigned int p, f; 712 uint16_t id; 713 uint16_t repr_id = mlx5_representor_id_encode(switch_info); 714 715 switch (eth_da->type) { 716 case RTE_ETH_REPRESENTOR_SF: 717 if (switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 718 rte_errno = EBUSY; 719 return false; 720 } 721 break; 722 case RTE_ETH_REPRESENTOR_VF: 723 /* Allows HPF representor index -1 as exception. */ 724 if (!(spawn->info.port_name == -1 && 725 switch_info->name_type == 726 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 727 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 728 rte_errno = EBUSY; 729 return false; 730 } 731 break; 732 case RTE_ETH_REPRESENTOR_NONE: 733 rte_errno = EBUSY; 734 return false; 735 default: 736 rte_errno = ENOTSUP; 737 DRV_LOG(ERR, "unsupported representor type"); 738 return false; 739 } 740 /* Check representor ID: */ 741 for (p = 0; p < eth_da->nb_ports; ++p) { 742 if (spawn->pf_bond < 0) { 743 /* For non-LAG mode, allow and ignore pf. */ 744 switch_info->pf_num = eth_da->ports[p]; 745 repr_id = mlx5_representor_id_encode(switch_info); 746 } 747 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 748 id = MLX5_REPRESENTOR_ID 749 (eth_da->ports[p], eth_da->type, 750 eth_da->representor_ports[f]); 751 if (repr_id == id) 752 return true; 753 } 754 } 755 rte_errno = EBUSY; 756 return false; 757 } 758 759 760 /** 761 * Spawn an Ethernet device from Verbs information. 762 * 763 * @param dpdk_dev 764 * Backing DPDK device. 765 * @param spawn 766 * Verbs device parameters (name, port, switch_info) to spawn. 767 * @param config 768 * Device configuration parameters. 769 * @param config 770 * Device arguments. 771 * 772 * @return 773 * A valid Ethernet device object on success, NULL otherwise and rte_errno 774 * is set. The following errors are defined: 775 * 776 * EBUSY: device is not supposed to be spawned. 777 * EEXIST: device is already spawned 778 */ 779 static struct rte_eth_dev * 780 mlx5_dev_spawn(struct rte_device *dpdk_dev, 781 struct mlx5_dev_spawn_data *spawn, 782 struct mlx5_dev_config *config, 783 struct rte_eth_devargs *eth_da) 784 { 785 const struct mlx5_switch_info *switch_info = &spawn->info; 786 struct mlx5_dev_ctx_shared *sh = NULL; 787 struct ibv_port_attr port_attr; 788 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 789 struct rte_eth_dev *eth_dev = NULL; 790 struct mlx5_priv *priv = NULL; 791 int err = 0; 792 unsigned int hw_padding = 0; 793 unsigned int mps; 794 unsigned int tunnel_en = 0; 795 unsigned int mpls_en = 0; 796 unsigned int swp = 0; 797 unsigned int mprq = 0; 798 unsigned int mprq_min_stride_size_n = 0; 799 unsigned int mprq_max_stride_size_n = 0; 800 unsigned int mprq_min_stride_num_n = 0; 801 unsigned int mprq_max_stride_num_n = 0; 802 struct rte_ether_addr mac; 803 char name[RTE_ETH_NAME_MAX_LEN]; 804 int own_domain_id = 0; 805 uint16_t port_id; 806 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 807 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 808 #endif 809 810 /* Determine if this port representor is supposed to be spawned. */ 811 if (switch_info->representor && dpdk_dev->devargs && 812 !mlx5_representor_match(spawn, eth_da)) 813 return NULL; 814 /* Build device name. */ 815 if (spawn->pf_bond < 0) { 816 /* Single device. */ 817 if (!switch_info->representor) 818 strlcpy(name, dpdk_dev->name, sizeof(name)); 819 else 820 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 821 dpdk_dev->name, 822 switch_info->name_type == 823 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 824 switch_info->port_name); 825 } else { 826 /* Bonding device. */ 827 if (!switch_info->representor) { 828 err = snprintf(name, sizeof(name), "%s_%s", 829 dpdk_dev->name, 830 mlx5_os_get_dev_device_name(spawn->phys_dev)); 831 } else { 832 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 833 dpdk_dev->name, 834 mlx5_os_get_dev_device_name(spawn->phys_dev), 835 switch_info->ctrl_num, 836 switch_info->pf_num, 837 switch_info->name_type == 838 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 839 switch_info->port_name); 840 } 841 } 842 if (err >= (int)sizeof(name)) 843 DRV_LOG(WARNING, "device name overflow %s", name); 844 /* check if the device is already spawned */ 845 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 846 rte_errno = EEXIST; 847 return NULL; 848 } 849 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 850 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 851 struct mlx5_mp_id mp_id; 852 853 eth_dev = rte_eth_dev_attach_secondary(name); 854 if (eth_dev == NULL) { 855 DRV_LOG(ERR, "can not attach rte ethdev"); 856 rte_errno = ENOMEM; 857 return NULL; 858 } 859 eth_dev->device = dpdk_dev; 860 eth_dev->dev_ops = &mlx5_dev_sec_ops; 861 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 862 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 863 err = mlx5_proc_priv_init(eth_dev); 864 if (err) 865 return NULL; 866 mp_id.port_id = eth_dev->data->port_id; 867 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 868 /* Receive command fd from primary process */ 869 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 870 if (err < 0) 871 goto err_secondary; 872 /* Remap UAR for Tx queues. */ 873 err = mlx5_tx_uar_init_secondary(eth_dev, err); 874 if (err) 875 goto err_secondary; 876 /* 877 * Ethdev pointer is still required as input since 878 * the primary device is not accessible from the 879 * secondary process. 880 */ 881 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 882 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 883 return eth_dev; 884 err_secondary: 885 mlx5_dev_close(eth_dev); 886 return NULL; 887 } 888 /* 889 * Some parameters ("tx_db_nc" in particularly) are needed in 890 * advance to create dv/verbs device context. We proceed the 891 * devargs here to get ones, and later proceed devargs again 892 * to override some hardware settings. 893 */ 894 err = mlx5_args(config, dpdk_dev->devargs); 895 if (err) { 896 err = rte_errno; 897 DRV_LOG(ERR, "failed to process device arguments: %s", 898 strerror(rte_errno)); 899 goto error; 900 } 901 if (config->dv_miss_info) { 902 if (switch_info->master || switch_info->representor) 903 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 904 } 905 mlx5_malloc_mem_select(config->sys_mem_en); 906 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 907 if (!sh) 908 return NULL; 909 config->devx = sh->devx; 910 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 911 config->dest_tir = 1; 912 #endif 913 #ifdef HAVE_IBV_MLX5_MOD_SWP 914 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 915 #endif 916 /* 917 * Multi-packet send is supported by ConnectX-4 Lx PF as well 918 * as all ConnectX-5 devices. 919 */ 920 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 921 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 922 #endif 923 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 924 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 925 #endif 926 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 927 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 928 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 929 DRV_LOG(DEBUG, "enhanced MPW is supported"); 930 mps = MLX5_MPW_ENHANCED; 931 } else { 932 DRV_LOG(DEBUG, "MPW is supported"); 933 mps = MLX5_MPW; 934 } 935 } else { 936 DRV_LOG(DEBUG, "MPW isn't supported"); 937 mps = MLX5_MPW_DISABLED; 938 } 939 #ifdef HAVE_IBV_MLX5_MOD_SWP 940 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 941 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 942 DRV_LOG(DEBUG, "SWP support: %u", swp); 943 #endif 944 config->swp = !!swp; 945 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 946 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 947 struct mlx5dv_striding_rq_caps mprq_caps = 948 dv_attr.striding_rq_caps; 949 950 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 951 mprq_caps.min_single_stride_log_num_of_bytes); 952 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 953 mprq_caps.max_single_stride_log_num_of_bytes); 954 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 955 mprq_caps.min_single_wqe_log_num_of_strides); 956 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 957 mprq_caps.max_single_wqe_log_num_of_strides); 958 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 959 mprq_caps.supported_qpts); 960 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 961 mprq = 1; 962 mprq_min_stride_size_n = 963 mprq_caps.min_single_stride_log_num_of_bytes; 964 mprq_max_stride_size_n = 965 mprq_caps.max_single_stride_log_num_of_bytes; 966 mprq_min_stride_num_n = 967 mprq_caps.min_single_wqe_log_num_of_strides; 968 mprq_max_stride_num_n = 969 mprq_caps.max_single_wqe_log_num_of_strides; 970 } 971 #endif 972 /* Rx CQE compression is enabled by default. */ 973 config->cqe_comp = 1; 974 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 975 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 976 tunnel_en = ((dv_attr.tunnel_offloads_caps & 977 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 978 (dv_attr.tunnel_offloads_caps & 979 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 980 (dv_attr.tunnel_offloads_caps & 981 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 982 } 983 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 984 tunnel_en ? "" : "not "); 985 #else 986 DRV_LOG(WARNING, 987 "tunnel offloading disabled due to old OFED/rdma-core version"); 988 #endif 989 config->tunnel_en = tunnel_en; 990 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 991 mpls_en = ((dv_attr.tunnel_offloads_caps & 992 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 993 (dv_attr.tunnel_offloads_caps & 994 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 995 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 996 mpls_en ? "" : "not "); 997 #else 998 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 999 " old OFED/rdma-core version or firmware configuration"); 1000 #endif 1001 config->mpls_en = mpls_en; 1002 /* Check port status. */ 1003 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1004 if (err) { 1005 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1006 goto error; 1007 } 1008 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1009 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1010 err = EINVAL; 1011 goto error; 1012 } 1013 if (port_attr.state != IBV_PORT_ACTIVE) 1014 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1015 mlx5_glue->port_state_str(port_attr.state), 1016 port_attr.state); 1017 /* Allocate private eth device data. */ 1018 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1019 sizeof(*priv), 1020 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1021 if (priv == NULL) { 1022 DRV_LOG(ERR, "priv allocation failure"); 1023 err = ENOMEM; 1024 goto error; 1025 } 1026 priv->sh = sh; 1027 priv->dev_port = spawn->phys_port; 1028 priv->pci_dev = spawn->pci_dev; 1029 priv->mtu = RTE_ETHER_MTU; 1030 /* Some internal functions rely on Netlink sockets, open them now. */ 1031 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1032 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1033 priv->representor = !!switch_info->representor; 1034 priv->master = !!switch_info->master; 1035 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1036 priv->vport_meta_tag = 0; 1037 priv->vport_meta_mask = 0; 1038 priv->pf_bond = spawn->pf_bond; 1039 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 1040 /* 1041 * The DevX port query API is implemented. E-Switch may use 1042 * either vport or reg_c[0] metadata register to match on 1043 * vport index. The engaged part of metadata register is 1044 * defined by mask. 1045 */ 1046 if (switch_info->representor || switch_info->master) { 1047 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 1048 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 1049 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 1050 &devx_port); 1051 if (err) { 1052 DRV_LOG(WARNING, 1053 "can't query devx port %d on device %s", 1054 spawn->phys_port, 1055 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1056 devx_port.comp_mask = 0; 1057 } 1058 } 1059 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 1060 priv->vport_meta_tag = devx_port.reg_c_0.value; 1061 priv->vport_meta_mask = devx_port.reg_c_0.mask; 1062 if (!priv->vport_meta_mask) { 1063 DRV_LOG(ERR, "vport zero mask for port %d" 1064 " on bonding device %s", 1065 spawn->phys_port, 1066 mlx5_os_get_dev_device_name 1067 (spawn->phys_dev)); 1068 err = ENOTSUP; 1069 goto error; 1070 } 1071 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1072 DRV_LOG(ERR, "invalid vport tag for port %d" 1073 " on bonding device %s", 1074 spawn->phys_port, 1075 mlx5_os_get_dev_device_name 1076 (spawn->phys_dev)); 1077 err = ENOTSUP; 1078 goto error; 1079 } 1080 } 1081 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 1082 priv->vport_id = devx_port.vport_num; 1083 } else if (spawn->pf_bond >= 0) { 1084 DRV_LOG(ERR, "can't deduce vport index for port %d" 1085 " on bonding device %s", 1086 spawn->phys_port, 1087 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1088 err = ENOTSUP; 1089 goto error; 1090 } else { 1091 /* Suppose vport index in compatible way. */ 1092 priv->vport_id = switch_info->representor ? 1093 switch_info->port_name + 1 : -1; 1094 } 1095 #else 1096 /* 1097 * Kernel/rdma_core support single E-Switch per PF configurations 1098 * only and vport_id field contains the vport index for 1099 * associated VF, which is deduced from representor port name. 1100 * For example, let's have the IB device port 10, it has 1101 * attached network device eth0, which has port name attribute 1102 * pf0vf2, we can deduce the VF number as 2, and set vport index 1103 * as 3 (2+1). This assigning schema should be changed if the 1104 * multiple E-Switch instances per PF configurations or/and PCI 1105 * subfunctions are added. 1106 */ 1107 priv->vport_id = switch_info->representor ? 1108 switch_info->port_name + 1 : -1; 1109 #endif 1110 priv->representor_id = mlx5_representor_id_encode(switch_info); 1111 /* 1112 * Look for sibling devices in order to reuse their switch domain 1113 * if any, otherwise allocate one. 1114 */ 1115 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1116 const struct mlx5_priv *opriv = 1117 rte_eth_devices[port_id].data->dev_private; 1118 1119 if (!opriv || 1120 opriv->sh != priv->sh || 1121 opriv->domain_id == 1122 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1123 continue; 1124 priv->domain_id = opriv->domain_id; 1125 break; 1126 } 1127 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1128 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1129 if (err) { 1130 err = rte_errno; 1131 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1132 strerror(rte_errno)); 1133 goto error; 1134 } 1135 own_domain_id = 1; 1136 } 1137 /* Override some values set by hardware configuration. */ 1138 mlx5_args(config, dpdk_dev->devargs); 1139 err = mlx5_dev_check_sibling_config(priv, config); 1140 if (err) 1141 goto error; 1142 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1143 IBV_DEVICE_RAW_IP_CSUM); 1144 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1145 (config->hw_csum ? "" : "not ")); 1146 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1147 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1148 DRV_LOG(DEBUG, "counters are not supported"); 1149 #endif 1150 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1151 if (config->dv_flow_en) { 1152 DRV_LOG(WARNING, "DV flow is not supported"); 1153 config->dv_flow_en = 0; 1154 } 1155 #endif 1156 config->ind_table_max_size = 1157 sh->device_attr.max_rwq_indirection_table_size; 1158 /* 1159 * Remove this check once DPDK supports larger/variable 1160 * indirection tables. 1161 */ 1162 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1163 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1164 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1165 config->ind_table_max_size); 1166 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1167 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1168 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1169 (config->hw_vlan_strip ? "" : "not ")); 1170 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1171 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1172 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1173 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1174 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1175 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1176 IBV_DEVICE_PCI_WRITE_END_PADDING); 1177 #endif 1178 if (config->hw_padding && !hw_padding) { 1179 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1180 config->hw_padding = 0; 1181 } else if (config->hw_padding) { 1182 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1183 } 1184 config->tso = (sh->device_attr.max_tso > 0 && 1185 (sh->device_attr.tso_supported_qpts & 1186 (1 << IBV_QPT_RAW_PACKET))); 1187 if (config->tso) 1188 config->tso_max_payload_sz = sh->device_attr.max_tso; 1189 /* 1190 * MPW is disabled by default, while the Enhanced MPW is enabled 1191 * by default. 1192 */ 1193 if (config->mps == MLX5_ARG_UNSET) 1194 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1195 MLX5_MPW_DISABLED; 1196 else 1197 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1198 DRV_LOG(INFO, "%sMPS is %s", 1199 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1200 config->mps == MLX5_MPW ? "legacy " : "", 1201 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1202 if (config->devx) { 1203 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1204 if (err) { 1205 err = -err; 1206 goto error; 1207 } 1208 /* Check relax ordering support. */ 1209 if (!haswell_broadwell_cpu) { 1210 sh->cmng.relaxed_ordering_write = 1211 config->hca_attr.relaxed_ordering_write; 1212 sh->cmng.relaxed_ordering_read = 1213 config->hca_attr.relaxed_ordering_read; 1214 } else { 1215 sh->cmng.relaxed_ordering_read = 0; 1216 sh->cmng.relaxed_ordering_write = 0; 1217 } 1218 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1219 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1220 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1221 /* Check for LRO support. */ 1222 if (config->dest_tir && config->hca_attr.lro_cap && 1223 config->dv_flow_en) { 1224 /* TBD check tunnel lro caps. */ 1225 config->lro.supported = config->hca_attr.lro_cap; 1226 DRV_LOG(DEBUG, "Device supports LRO"); 1227 /* 1228 * If LRO timeout is not configured by application, 1229 * use the minimal supported value. 1230 */ 1231 if (!config->lro.timeout) 1232 config->lro.timeout = 1233 config->hca_attr.lro_timer_supported_periods[0]; 1234 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1235 config->lro.timeout); 1236 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1237 "required for coalescing is %d bytes", 1238 config->hca_attr.lro_min_mss_size); 1239 } 1240 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 1241 if (config->hca_attr.qos.sup && 1242 config->hca_attr.qos.flow_meter_old && 1243 config->dv_flow_en) { 1244 uint8_t reg_c_mask = 1245 config->hca_attr.qos.flow_meter_reg_c_ids; 1246 /* 1247 * Meter needs two REG_C's for color match and pre-sfx 1248 * flow match. Here get the REG_C for color match. 1249 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1250 */ 1251 reg_c_mask &= 0xfc; 1252 if (__builtin_popcount(reg_c_mask) < 1) { 1253 priv->mtr_en = 0; 1254 DRV_LOG(WARNING, "No available register for" 1255 " meter."); 1256 } else { 1257 /* 1258 * The meter color register is used by the 1259 * flow-hit feature as well. 1260 * The flow-hit feature must use REG_C_3 1261 * Prefer REG_C_3 if it is available. 1262 */ 1263 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1264 priv->mtr_color_reg = REG_C_3; 1265 else 1266 priv->mtr_color_reg = ffs(reg_c_mask) 1267 - 1 + REG_C_0; 1268 priv->mtr_en = 1; 1269 priv->mtr_reg_share = 1270 config->hca_attr.qos.flow_meter; 1271 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1272 priv->mtr_color_reg); 1273 } 1274 } 1275 #endif 1276 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1277 if (config->hca_attr.flow_hit_aso && 1278 priv->mtr_color_reg == REG_C_3) { 1279 sh->flow_hit_aso_en = 1; 1280 err = mlx5_flow_aso_age_mng_init(sh); 1281 if (err) { 1282 err = -err; 1283 goto error; 1284 } 1285 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1286 } 1287 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1288 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1289 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1290 config->dv_flow_en) { 1291 priv->sampler_en = 1; 1292 DRV_LOG(DEBUG, "Sampler enabled!"); 1293 } else { 1294 priv->sampler_en = 0; 1295 if (!config->hca_attr.log_max_ft_sampler_num) 1296 DRV_LOG(WARNING, 1297 "No available register for sampler."); 1298 else 1299 DRV_LOG(DEBUG, "DV flow is not supported!"); 1300 } 1301 #endif 1302 } 1303 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1304 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1305 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1306 config->cqe_comp = 0; 1307 } 1308 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1309 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1310 DRV_LOG(WARNING, "Flow Tag CQE compression" 1311 " format isn't supported."); 1312 config->cqe_comp = 0; 1313 } 1314 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1315 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1316 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1317 " format isn't supported."); 1318 config->cqe_comp = 0; 1319 } 1320 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1321 config->cqe_comp ? "" : "not "); 1322 if (config->tx_pp) { 1323 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1324 config->hca_attr.dev_freq_khz); 1325 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1326 config->hca_attr.qos.packet_pacing ? "" : "not "); 1327 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1328 config->hca_attr.cross_channel ? "" : "not "); 1329 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1330 config->hca_attr.wqe_index_ignore ? "" : "not "); 1331 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1332 config->hca_attr.non_wire_sq ? "" : "not "); 1333 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1334 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1335 config->hca_attr.log_max_static_sq_wq); 1336 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1337 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1338 if (!config->devx) { 1339 DRV_LOG(ERR, "DevX is required for packet pacing"); 1340 err = ENODEV; 1341 goto error; 1342 } 1343 if (!config->hca_attr.qos.packet_pacing) { 1344 DRV_LOG(ERR, "Packet pacing is not supported"); 1345 err = ENODEV; 1346 goto error; 1347 } 1348 if (!config->hca_attr.cross_channel) { 1349 DRV_LOG(ERR, "Cross channel operations are" 1350 " required for packet pacing"); 1351 err = ENODEV; 1352 goto error; 1353 } 1354 if (!config->hca_attr.wqe_index_ignore) { 1355 DRV_LOG(ERR, "WQE index ignore feature is" 1356 " required for packet pacing"); 1357 err = ENODEV; 1358 goto error; 1359 } 1360 if (!config->hca_attr.non_wire_sq) { 1361 DRV_LOG(ERR, "Non-wire SQ feature is" 1362 " required for packet pacing"); 1363 err = ENODEV; 1364 goto error; 1365 } 1366 if (!config->hca_attr.log_max_static_sq_wq) { 1367 DRV_LOG(ERR, "Static WQE SQ feature is" 1368 " required for packet pacing"); 1369 err = ENODEV; 1370 goto error; 1371 } 1372 if (!config->hca_attr.qos.wqe_rate_pp) { 1373 DRV_LOG(ERR, "WQE rate mode is required" 1374 " for packet pacing"); 1375 err = ENODEV; 1376 goto error; 1377 } 1378 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1379 DRV_LOG(ERR, "DevX does not provide UAR offset," 1380 " can't create queues for packet pacing"); 1381 err = ENODEV; 1382 goto error; 1383 #endif 1384 } 1385 if (config->devx) { 1386 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1387 1388 err = config->hca_attr.access_register_user ? 1389 mlx5_devx_cmd_register_read 1390 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1391 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1392 if (!err) { 1393 uint32_t ts_mode; 1394 1395 /* MTUTC register is read successfully. */ 1396 ts_mode = MLX5_GET(register_mtutc, reg, 1397 time_stamp_mode); 1398 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1399 config->rt_timestamp = 1; 1400 } else { 1401 /* Kernel does not support register reading. */ 1402 if (config->hca_attr.dev_freq_khz == 1403 (NS_PER_S / MS_PER_S)) 1404 config->rt_timestamp = 1; 1405 } 1406 } 1407 /* 1408 * If HW has bug working with tunnel packet decapsulation and 1409 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1410 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1411 */ 1412 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1413 config->hw_fcs_strip = 0; 1414 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1415 (config->hw_fcs_strip ? "" : "not ")); 1416 if (config->mprq.enabled && mprq) { 1417 if (config->mprq.stride_num_n && 1418 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1419 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1420 config->mprq.stride_num_n = 1421 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1422 mprq_min_stride_num_n), 1423 mprq_max_stride_num_n); 1424 DRV_LOG(WARNING, 1425 "the number of strides" 1426 " for Multi-Packet RQ is out of range," 1427 " setting default value (%u)", 1428 1 << config->mprq.stride_num_n); 1429 } 1430 if (config->mprq.stride_size_n && 1431 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1432 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1433 config->mprq.stride_size_n = 1434 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1435 mprq_min_stride_size_n), 1436 mprq_max_stride_size_n); 1437 DRV_LOG(WARNING, 1438 "the size of a stride" 1439 " for Multi-Packet RQ is out of range," 1440 " setting default value (%u)", 1441 1 << config->mprq.stride_size_n); 1442 } 1443 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1444 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1445 } else if (config->mprq.enabled && !mprq) { 1446 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1447 config->mprq.enabled = 0; 1448 } 1449 if (config->max_dump_files_num == 0) 1450 config->max_dump_files_num = 128; 1451 eth_dev = rte_eth_dev_allocate(name); 1452 if (eth_dev == NULL) { 1453 DRV_LOG(ERR, "can not allocate rte ethdev"); 1454 err = ENOMEM; 1455 goto error; 1456 } 1457 if (priv->representor) { 1458 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1459 eth_dev->data->representor_id = priv->representor_id; 1460 } 1461 priv->mp_id.port_id = eth_dev->data->port_id; 1462 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1463 /* 1464 * Store associated network device interface index. This index 1465 * is permanent throughout the lifetime of device. So, we may store 1466 * the ifindex here and use the cached value further. 1467 */ 1468 MLX5_ASSERT(spawn->ifindex); 1469 priv->if_index = spawn->ifindex; 1470 if (priv->pf_bond >= 0 && priv->master) { 1471 /* Get bond interface info */ 1472 err = mlx5_sysfs_bond_info(priv->if_index, 1473 &priv->bond_ifindex, 1474 priv->bond_name); 1475 if (err) 1476 DRV_LOG(ERR, "unable to get bond info: %s", 1477 strerror(rte_errno)); 1478 else 1479 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1480 priv->if_index, priv->bond_ifindex, 1481 priv->bond_name); 1482 } 1483 eth_dev->data->dev_private = priv; 1484 priv->dev_data = eth_dev->data; 1485 eth_dev->data->mac_addrs = priv->mac; 1486 eth_dev->device = dpdk_dev; 1487 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1488 /* Configure the first MAC address by default. */ 1489 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1490 DRV_LOG(ERR, 1491 "port %u cannot get MAC address, is mlx5_en" 1492 " loaded? (errno: %s)", 1493 eth_dev->data->port_id, strerror(rte_errno)); 1494 err = ENODEV; 1495 goto error; 1496 } 1497 DRV_LOG(INFO, 1498 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1499 eth_dev->data->port_id, 1500 mac.addr_bytes[0], mac.addr_bytes[1], 1501 mac.addr_bytes[2], mac.addr_bytes[3], 1502 mac.addr_bytes[4], mac.addr_bytes[5]); 1503 #ifdef RTE_LIBRTE_MLX5_DEBUG 1504 { 1505 char ifname[MLX5_NAMESIZE]; 1506 1507 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1508 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1509 eth_dev->data->port_id, ifname); 1510 else 1511 DRV_LOG(DEBUG, "port %u ifname is unknown", 1512 eth_dev->data->port_id); 1513 } 1514 #endif 1515 /* Get actual MTU if possible. */ 1516 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1517 if (err) { 1518 err = rte_errno; 1519 goto error; 1520 } 1521 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1522 priv->mtu); 1523 /* Initialize burst functions to prevent crashes before link-up. */ 1524 eth_dev->rx_pkt_burst = removed_rx_burst; 1525 eth_dev->tx_pkt_burst = removed_tx_burst; 1526 eth_dev->dev_ops = &mlx5_dev_ops; 1527 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1528 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1529 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1530 /* Register MAC address. */ 1531 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1532 if (config->vf && config->vf_nl_en) 1533 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1534 mlx5_ifindex(eth_dev), 1535 eth_dev->data->mac_addrs, 1536 MLX5_MAX_MAC_ADDRESSES); 1537 priv->flows = 0; 1538 priv->ctrl_flows = 0; 1539 rte_spinlock_init(&priv->flow_list_lock); 1540 TAILQ_INIT(&priv->flow_meters); 1541 TAILQ_INIT(&priv->flow_meter_profiles); 1542 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1543 mlx5_glue->dv_set_context_attr(sh->ctx, 1544 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1545 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1546 .alloc = &mlx5_alloc_verbs_buf, 1547 .free = &mlx5_free_verbs_buf, 1548 .data = sh, 1549 })); 1550 /* Bring Ethernet device up. */ 1551 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1552 eth_dev->data->port_id); 1553 mlx5_set_link_up(eth_dev); 1554 /* 1555 * Even though the interrupt handler is not installed yet, 1556 * interrupts will still trigger on the async_fd from 1557 * Verbs context returned by ibv_open_device(). 1558 */ 1559 mlx5_link_update(eth_dev, 0); 1560 #ifdef HAVE_MLX5DV_DR_ESWITCH 1561 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1562 (switch_info->representor || switch_info->master))) 1563 config->dv_esw_en = 0; 1564 #else 1565 config->dv_esw_en = 0; 1566 #endif 1567 /* Detect minimal data bytes to inline. */ 1568 mlx5_set_min_inline(spawn, config); 1569 /* Store device configuration on private structure. */ 1570 priv->config = *config; 1571 /* Create context for virtual machine VLAN workaround. */ 1572 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1573 if (config->dv_flow_en) { 1574 err = mlx5_alloc_shared_dr(priv); 1575 if (err) 1576 goto error; 1577 } 1578 if (config->devx && config->dv_flow_en && config->dest_tir) { 1579 priv->obj_ops = devx_obj_ops; 1580 priv->obj_ops.drop_action_create = 1581 ibv_obj_ops.drop_action_create; 1582 priv->obj_ops.drop_action_destroy = 1583 ibv_obj_ops.drop_action_destroy; 1584 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1585 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1586 #else 1587 if (config->dv_esw_en) 1588 priv->obj_ops.txq_obj_modify = 1589 ibv_obj_ops.txq_obj_modify; 1590 #endif 1591 /* Use specific wrappers for Tx object. */ 1592 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1593 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1594 mlx5_queue_counter_id_prepare(eth_dev); 1595 1596 } else { 1597 priv->obj_ops = ibv_obj_ops; 1598 } 1599 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1600 if (!priv->drop_queue.hrxq) 1601 goto error; 1602 /* Supported Verbs flow priority number detection. */ 1603 err = mlx5_flow_discover_priorities(eth_dev); 1604 if (err < 0) { 1605 err = -err; 1606 goto error; 1607 } 1608 priv->config.flow_prio = err; 1609 if (!priv->config.dv_esw_en && 1610 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1611 DRV_LOG(WARNING, "metadata mode %u is not supported " 1612 "(no E-Switch)", priv->config.dv_xmeta_en); 1613 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1614 } 1615 mlx5_set_metadata_mask(eth_dev); 1616 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1617 !priv->sh->dv_regc0_mask) { 1618 DRV_LOG(ERR, "metadata mode %u is not supported " 1619 "(no metadata reg_c[0] is available)", 1620 priv->config.dv_xmeta_en); 1621 err = ENOTSUP; 1622 goto error; 1623 } 1624 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 1625 mlx5_hrxq_create_cb, 1626 mlx5_hrxq_match_cb, 1627 mlx5_hrxq_remove_cb); 1628 /* Query availability of metadata reg_c's. */ 1629 err = mlx5_flow_discover_mreg_c(eth_dev); 1630 if (err < 0) { 1631 err = -err; 1632 goto error; 1633 } 1634 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1635 DRV_LOG(DEBUG, 1636 "port %u extensive metadata register is not supported", 1637 eth_dev->data->port_id); 1638 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1639 DRV_LOG(ERR, "metadata mode %u is not supported " 1640 "(no metadata registers available)", 1641 priv->config.dv_xmeta_en); 1642 err = ENOTSUP; 1643 goto error; 1644 } 1645 } 1646 if (priv->config.dv_flow_en && 1647 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1648 mlx5_flow_ext_mreg_supported(eth_dev) && 1649 priv->sh->dv_regc0_mask) { 1650 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1651 MLX5_FLOW_MREG_HTABLE_SZ, 1652 0, 0, 1653 flow_dv_mreg_create_cb, 1654 flow_dv_mreg_match_cb, 1655 flow_dv_mreg_remove_cb); 1656 if (!priv->mreg_cp_tbl) { 1657 err = ENOMEM; 1658 goto error; 1659 } 1660 priv->mreg_cp_tbl->ctx = eth_dev; 1661 } 1662 rte_spinlock_init(&priv->shared_act_sl); 1663 mlx5_flow_counter_mode_config(eth_dev); 1664 if (priv->config.dv_flow_en) 1665 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1666 return eth_dev; 1667 error: 1668 if (priv) { 1669 if (priv->mreg_cp_tbl) 1670 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1671 if (priv->sh) 1672 mlx5_os_free_shared_dr(priv); 1673 if (priv->nl_socket_route >= 0) 1674 close(priv->nl_socket_route); 1675 if (priv->nl_socket_rdma >= 0) 1676 close(priv->nl_socket_rdma); 1677 if (priv->vmwa_context) 1678 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1679 if (eth_dev && priv->drop_queue.hrxq) 1680 mlx5_drop_action_destroy(eth_dev); 1681 if (own_domain_id) 1682 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1683 mlx5_cache_list_destroy(&priv->hrxqs); 1684 mlx5_free(priv); 1685 if (eth_dev != NULL) 1686 eth_dev->data->dev_private = NULL; 1687 } 1688 if (eth_dev != NULL) { 1689 /* mac_addrs must not be freed alone because part of 1690 * dev_private 1691 **/ 1692 eth_dev->data->mac_addrs = NULL; 1693 rte_eth_dev_release_port(eth_dev); 1694 } 1695 if (sh) 1696 mlx5_free_shared_dev_ctx(sh); 1697 MLX5_ASSERT(err > 0); 1698 rte_errno = err; 1699 return NULL; 1700 } 1701 1702 /** 1703 * Comparison callback to sort device data. 1704 * 1705 * This is meant to be used with qsort(). 1706 * 1707 * @param a[in] 1708 * Pointer to pointer to first data object. 1709 * @param b[in] 1710 * Pointer to pointer to second data object. 1711 * 1712 * @return 1713 * 0 if both objects are equal, less than 0 if the first argument is less 1714 * than the second, greater than 0 otherwise. 1715 */ 1716 static int 1717 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1718 { 1719 const struct mlx5_switch_info *si_a = 1720 &((const struct mlx5_dev_spawn_data *)a)->info; 1721 const struct mlx5_switch_info *si_b = 1722 &((const struct mlx5_dev_spawn_data *)b)->info; 1723 int ret; 1724 1725 /* Master device first. */ 1726 ret = si_b->master - si_a->master; 1727 if (ret) 1728 return ret; 1729 /* Then representor devices. */ 1730 ret = si_b->representor - si_a->representor; 1731 if (ret) 1732 return ret; 1733 /* Unidentified devices come last in no specific order. */ 1734 if (!si_a->representor) 1735 return 0; 1736 /* Order representors by name. */ 1737 return si_a->port_name - si_b->port_name; 1738 } 1739 1740 /** 1741 * Match PCI information for possible slaves of bonding device. 1742 * 1743 * @param[in] ibv_dev 1744 * Pointer to Infiniband device structure. 1745 * @param[in] pci_dev 1746 * Pointer to primary PCI address structure to match. 1747 * @param[in] nl_rdma 1748 * Netlink RDMA group socket handle. 1749 * @param[in] owner 1750 * Rerepsentor owner PF index. 1751 * 1752 * @return 1753 * negative value if no bonding device found, otherwise 1754 * positive index of slave PF in bonding. 1755 */ 1756 static int 1757 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1758 const struct rte_pci_addr *pci_dev, 1759 int nl_rdma, uint16_t owner) 1760 { 1761 char ifname[IF_NAMESIZE + 1]; 1762 unsigned int ifindex; 1763 unsigned int np, i; 1764 FILE *file = NULL; 1765 int pf = -1; 1766 1767 /* 1768 * Try to get master device name. If something goes 1769 * wrong suppose the lack of kernel support and no 1770 * bonding devices. 1771 */ 1772 if (nl_rdma < 0) 1773 return -1; 1774 if (!strstr(ibv_dev->name, "bond")) 1775 return -1; 1776 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1777 if (!np) 1778 return -1; 1779 /* 1780 * The Master device might not be on the predefined 1781 * port (not on port index 1, it is not garanted), 1782 * we have to scan all Infiniband device port and 1783 * find master. 1784 */ 1785 for (i = 1; i <= np; ++i) { 1786 /* Check whether Infiniband port is populated. */ 1787 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1788 if (!ifindex) 1789 continue; 1790 if (!if_indextoname(ifindex, ifname)) 1791 continue; 1792 /* Try to read bonding slave names from sysfs. */ 1793 MKSTR(slaves, 1794 "/sys/class/net/%s/master/bonding/slaves", ifname); 1795 file = fopen(slaves, "r"); 1796 if (file) 1797 break; 1798 } 1799 if (!file) 1800 return -1; 1801 /* Use safe format to check maximal buffer length. */ 1802 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1803 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1804 char tmp_str[IF_NAMESIZE + 32]; 1805 struct rte_pci_addr pci_addr; 1806 struct mlx5_switch_info info; 1807 1808 /* Process slave interface names in the loop. */ 1809 snprintf(tmp_str, sizeof(tmp_str), 1810 "/sys/class/net/%s", ifname); 1811 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1812 DRV_LOG(WARNING, "can not get PCI address" 1813 " for netdev \"%s\"", ifname); 1814 continue; 1815 } 1816 if (pci_dev->domain != pci_addr.domain || 1817 pci_dev->bus != pci_addr.bus || 1818 pci_dev->devid != pci_addr.devid || 1819 pci_dev->function + owner != pci_addr.function) 1820 continue; 1821 /* Slave interface PCI address match found. */ 1822 fclose(file); 1823 snprintf(tmp_str, sizeof(tmp_str), 1824 "/sys/class/net/%s/phys_port_name", ifname); 1825 file = fopen(tmp_str, "rb"); 1826 if (!file) 1827 break; 1828 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1829 if (fscanf(file, "%32s", tmp_str) == 1) 1830 mlx5_translate_port_name(tmp_str, &info); 1831 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 1832 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1833 pf = info.port_name; 1834 break; 1835 } 1836 if (file) 1837 fclose(file); 1838 return pf; 1839 } 1840 1841 /** 1842 * Register a PCI device within bonding. 1843 * 1844 * This function spawns Ethernet devices out of a given PCI device and 1845 * bonding owner PF index. 1846 * 1847 * @param[in] pci_dev 1848 * PCI device information. 1849 * @param[in] req_eth_da 1850 * Requested ethdev device argument. 1851 * @param[in] owner_id 1852 * Requested owner PF port ID within bonding device, default to 0. 1853 * 1854 * @return 1855 * 0 on success, a negative errno value otherwise and rte_errno is set. 1856 */ 1857 static int 1858 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 1859 struct rte_eth_devargs *req_eth_da, 1860 uint16_t owner_id) 1861 { 1862 struct ibv_device **ibv_list; 1863 /* 1864 * Number of found IB Devices matching with requested PCI BDF. 1865 * nd != 1 means there are multiple IB devices over the same 1866 * PCI device and we have representors and master. 1867 */ 1868 unsigned int nd = 0; 1869 /* 1870 * Number of found IB device Ports. nd = 1 and np = 1..n means 1871 * we have the single multiport IB device, and there may be 1872 * representors attached to some of found ports. 1873 */ 1874 unsigned int np = 0; 1875 /* 1876 * Number of DPDK ethernet devices to Spawn - either over 1877 * multiple IB devices or multiple ports of single IB device. 1878 * Actually this is the number of iterations to spawn. 1879 */ 1880 unsigned int ns = 0; 1881 /* 1882 * Bonding device 1883 * < 0 - no bonding device (single one) 1884 * >= 0 - bonding device (value is slave PF index) 1885 */ 1886 int bd = -1; 1887 struct mlx5_dev_spawn_data *list = NULL; 1888 struct mlx5_dev_config dev_config; 1889 unsigned int dev_config_vf; 1890 struct rte_eth_devargs eth_da = *req_eth_da; 1891 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 1892 int ret = -1; 1893 1894 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1895 mlx5_pmd_socket_init(); 1896 ret = mlx5_init_once(); 1897 if (ret) { 1898 DRV_LOG(ERR, "unable to init PMD global data: %s", 1899 strerror(rte_errno)); 1900 return -rte_errno; 1901 } 1902 errno = 0; 1903 ibv_list = mlx5_glue->get_device_list(&ret); 1904 if (!ibv_list) { 1905 rte_errno = errno ? errno : ENOSYS; 1906 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1907 return -rte_errno; 1908 } 1909 /* 1910 * First scan the list of all Infiniband devices to find 1911 * matching ones, gathering into the list. 1912 */ 1913 struct ibv_device *ibv_match[ret + 1]; 1914 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1915 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1916 unsigned int i; 1917 1918 while (ret-- > 0) { 1919 struct rte_pci_addr pci_addr; 1920 1921 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1922 bd = mlx5_device_bond_pci_match 1923 (ibv_list[ret], &owner_pci, nl_rdma, owner_id); 1924 if (bd >= 0) { 1925 /* 1926 * Bonding device detected. Only one match is allowed, 1927 * the bonding is supported over multi-port IB device, 1928 * there should be no matches on representor PCI 1929 * functions or non VF LAG bonding devices with 1930 * specified address. 1931 */ 1932 if (nd) { 1933 DRV_LOG(ERR, 1934 "multiple PCI match on bonding device" 1935 "\"%s\" found", ibv_list[ret]->name); 1936 rte_errno = ENOENT; 1937 ret = -rte_errno; 1938 goto exit; 1939 } 1940 /* Amend owner pci address if owner PF ID specified. */ 1941 if (eth_da.nb_representor_ports) 1942 owner_pci.function += owner_id; 1943 DRV_LOG(INFO, "PCI information matches for" 1944 " slave %d bonding device \"%s\"", 1945 bd, ibv_list[ret]->name); 1946 ibv_match[nd++] = ibv_list[ret]; 1947 break; 1948 } else { 1949 /* Bonding device not found. */ 1950 if (mlx5_dev_to_pci_addr 1951 (ibv_list[ret]->ibdev_path, &pci_addr)) 1952 continue; 1953 if (owner_pci.domain != pci_addr.domain || 1954 owner_pci.bus != pci_addr.bus || 1955 owner_pci.devid != pci_addr.devid || 1956 owner_pci.function != pci_addr.function) 1957 continue; 1958 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1959 ibv_list[ret]->name); 1960 ibv_match[nd++] = ibv_list[ret]; 1961 } 1962 } 1963 ibv_match[nd] = NULL; 1964 if (!nd) { 1965 /* No device matches, just complain and bail out. */ 1966 DRV_LOG(WARNING, 1967 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1968 " are kernel drivers loaded?", 1969 owner_pci.domain, owner_pci.bus, 1970 owner_pci.devid, owner_pci.function); 1971 rte_errno = ENOENT; 1972 ret = -rte_errno; 1973 goto exit; 1974 } 1975 if (nd == 1) { 1976 /* 1977 * Found single matching device may have multiple ports. 1978 * Each port may be representor, we have to check the port 1979 * number and check the representors existence. 1980 */ 1981 if (nl_rdma >= 0) 1982 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1983 if (!np) 1984 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1985 " ports number", ibv_match[0]->name); 1986 if (bd >= 0 && !np) { 1987 DRV_LOG(ERR, "can not get ports" 1988 " for bonding device"); 1989 rte_errno = ENOENT; 1990 ret = -rte_errno; 1991 goto exit; 1992 } 1993 } 1994 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 1995 if (bd >= 0) { 1996 /* 1997 * This may happen if there is VF LAG kernel support and 1998 * application is compiled with older rdma_core library. 1999 */ 2000 DRV_LOG(ERR, 2001 "No kernel/verbs support for VF LAG bonding found."); 2002 rte_errno = ENOTSUP; 2003 ret = -rte_errno; 2004 goto exit; 2005 } 2006 #endif 2007 /* 2008 * Now we can determine the maximal 2009 * amount of devices to be spawned. 2010 */ 2011 list = mlx5_malloc(MLX5_MEM_ZERO, 2012 sizeof(struct mlx5_dev_spawn_data) * 2013 (np ? np : nd), 2014 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2015 if (!list) { 2016 DRV_LOG(ERR, "spawn data array allocation failure"); 2017 rte_errno = ENOMEM; 2018 ret = -rte_errno; 2019 goto exit; 2020 } 2021 if (bd >= 0 || np > 1) { 2022 /* 2023 * Single IB device with multiple ports found, 2024 * it may be E-Switch master device and representors. 2025 * We have to perform identification through the ports. 2026 */ 2027 MLX5_ASSERT(nl_rdma >= 0); 2028 MLX5_ASSERT(ns == 0); 2029 MLX5_ASSERT(nd == 1); 2030 MLX5_ASSERT(np); 2031 for (i = 1; i <= np; ++i) { 2032 list[ns].max_port = np; 2033 list[ns].phys_port = i; 2034 list[ns].phys_dev = ibv_match[0]; 2035 list[ns].eth_dev = NULL; 2036 list[ns].pci_dev = pci_dev; 2037 list[ns].pf_bond = bd; 2038 list[ns].ifindex = mlx5_nl_ifindex 2039 (nl_rdma, 2040 mlx5_os_get_dev_device_name 2041 (list[ns].phys_dev), i); 2042 if (!list[ns].ifindex) { 2043 /* 2044 * No network interface index found for the 2045 * specified port, it means there is no 2046 * representor on this port. It's OK, 2047 * there can be disabled ports, for example 2048 * if sriov_numvfs < sriov_totalvfs. 2049 */ 2050 continue; 2051 } 2052 ret = -1; 2053 if (nl_route >= 0) 2054 ret = mlx5_nl_switch_info 2055 (nl_route, 2056 list[ns].ifindex, 2057 &list[ns].info); 2058 if (ret || (!list[ns].info.representor && 2059 !list[ns].info.master)) { 2060 /* 2061 * We failed to recognize representors with 2062 * Netlink, let's try to perform the task 2063 * with sysfs. 2064 */ 2065 ret = mlx5_sysfs_switch_info 2066 (list[ns].ifindex, 2067 &list[ns].info); 2068 } 2069 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2070 if (!ret && bd >= 0) { 2071 switch (list[ns].info.name_type) { 2072 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2073 if (list[ns].info.port_name == bd) 2074 ns++; 2075 break; 2076 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2077 /* Fallthrough */ 2078 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2079 /* Fallthrough */ 2080 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2081 if (list[ns].info.pf_num == bd) 2082 ns++; 2083 break; 2084 default: 2085 break; 2086 } 2087 continue; 2088 } 2089 #endif 2090 if (!ret && (list[ns].info.representor ^ 2091 list[ns].info.master)) 2092 ns++; 2093 } 2094 if (!ns) { 2095 DRV_LOG(ERR, 2096 "unable to recognize master/representors" 2097 " on the IB device with multiple ports"); 2098 rte_errno = ENOENT; 2099 ret = -rte_errno; 2100 goto exit; 2101 } 2102 } else { 2103 /* 2104 * The existence of several matching entries (nd > 1) means 2105 * port representors have been instantiated. No existing Verbs 2106 * call nor sysfs entries can tell them apart, this can only 2107 * be done through Netlink calls assuming kernel drivers are 2108 * recent enough to support them. 2109 * 2110 * In the event of identification failure through Netlink, 2111 * try again through sysfs, then: 2112 * 2113 * 1. A single IB device matches (nd == 1) with single 2114 * port (np=0/1) and is not a representor, assume 2115 * no switch support. 2116 * 2117 * 2. Otherwise no safe assumptions can be made; 2118 * complain louder and bail out. 2119 */ 2120 for (i = 0; i != nd; ++i) { 2121 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2122 list[ns].max_port = 1; 2123 list[ns].phys_port = 1; 2124 list[ns].phys_dev = ibv_match[i]; 2125 list[ns].eth_dev = NULL; 2126 list[ns].pci_dev = pci_dev; 2127 list[ns].pf_bond = -1; 2128 list[ns].ifindex = 0; 2129 if (nl_rdma >= 0) 2130 list[ns].ifindex = mlx5_nl_ifindex 2131 (nl_rdma, 2132 mlx5_os_get_dev_device_name 2133 (list[ns].phys_dev), 1); 2134 if (!list[ns].ifindex) { 2135 char ifname[IF_NAMESIZE]; 2136 2137 /* 2138 * Netlink failed, it may happen with old 2139 * ib_core kernel driver (before 4.16). 2140 * We can assume there is old driver because 2141 * here we are processing single ports IB 2142 * devices. Let's try sysfs to retrieve 2143 * the ifindex. The method works for 2144 * master device only. 2145 */ 2146 if (nd > 1) { 2147 /* 2148 * Multiple devices found, assume 2149 * representors, can not distinguish 2150 * master/representor and retrieve 2151 * ifindex via sysfs. 2152 */ 2153 continue; 2154 } 2155 ret = mlx5_get_ifname_sysfs 2156 (ibv_match[i]->ibdev_path, ifname); 2157 if (!ret) 2158 list[ns].ifindex = 2159 if_nametoindex(ifname); 2160 if (!list[ns].ifindex) { 2161 /* 2162 * No network interface index found 2163 * for the specified device, it means 2164 * there it is neither representor 2165 * nor master. 2166 */ 2167 continue; 2168 } 2169 } 2170 ret = -1; 2171 if (nl_route >= 0) 2172 ret = mlx5_nl_switch_info 2173 (nl_route, 2174 list[ns].ifindex, 2175 &list[ns].info); 2176 if (ret || (!list[ns].info.representor && 2177 !list[ns].info.master)) { 2178 /* 2179 * We failed to recognize representors with 2180 * Netlink, let's try to perform the task 2181 * with sysfs. 2182 */ 2183 ret = mlx5_sysfs_switch_info 2184 (list[ns].ifindex, 2185 &list[ns].info); 2186 } 2187 if (!ret && (list[ns].info.representor ^ 2188 list[ns].info.master)) { 2189 ns++; 2190 } else if ((nd == 1) && 2191 !list[ns].info.representor && 2192 !list[ns].info.master) { 2193 /* 2194 * Single IB device with 2195 * one physical port and 2196 * attached network device. 2197 * May be SRIOV is not enabled 2198 * or there is no representors. 2199 */ 2200 DRV_LOG(INFO, "no E-Switch support detected"); 2201 ns++; 2202 break; 2203 } 2204 } 2205 if (!ns) { 2206 DRV_LOG(ERR, 2207 "unable to recognize master/representors" 2208 " on the multiple IB devices"); 2209 rte_errno = ENOENT; 2210 ret = -rte_errno; 2211 goto exit; 2212 } 2213 } 2214 MLX5_ASSERT(ns); 2215 /* 2216 * Sort list to probe devices in natural order for users convenience 2217 * (i.e. master first, then representors from lowest to highest ID). 2218 */ 2219 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2220 /* Device specific configuration. */ 2221 switch (pci_dev->id.device_id) { 2222 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2223 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2224 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2225 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2226 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2227 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2228 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2229 dev_config_vf = 1; 2230 break; 2231 default: 2232 dev_config_vf = 0; 2233 break; 2234 } 2235 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2236 /* Set devargs default values. */ 2237 if (eth_da.nb_mh_controllers == 0) { 2238 eth_da.nb_mh_controllers = 1; 2239 eth_da.mh_controllers[0] = 0; 2240 } 2241 if (eth_da.nb_ports == 0 && ns > 0) { 2242 if (list[0].pf_bond >= 0 && list[0].info.representor) 2243 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2244 pci_dev->device.devargs->args); 2245 eth_da.nb_ports = 1; 2246 eth_da.ports[0] = list[0].info.pf_num; 2247 } 2248 if (eth_da.nb_representor_ports == 0) { 2249 eth_da.nb_representor_ports = 1; 2250 eth_da.representor_ports[0] = 0; 2251 } 2252 } 2253 for (i = 0; i != ns; ++i) { 2254 uint32_t restore; 2255 2256 /* Default configuration. */ 2257 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2258 dev_config.vf = dev_config_vf; 2259 dev_config.mps = MLX5_ARG_UNSET; 2260 dev_config.dbnc = MLX5_ARG_UNSET; 2261 dev_config.rx_vec_en = 1; 2262 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2263 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2264 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2265 dev_config.txqs_inline = MLX5_ARG_UNSET; 2266 dev_config.vf_nl_en = 1; 2267 dev_config.mr_ext_memseg_en = 1; 2268 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2269 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2270 dev_config.dv_esw_en = 1; 2271 dev_config.dv_flow_en = 1; 2272 dev_config.decap_en = 1; 2273 dev_config.log_hp_size = MLX5_ARG_UNSET; 2274 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2275 &list[i], 2276 &dev_config, 2277 ð_da); 2278 if (!list[i].eth_dev) { 2279 if (rte_errno != EBUSY && rte_errno != EEXIST) 2280 break; 2281 /* Device is disabled or already spawned. Ignore it. */ 2282 continue; 2283 } 2284 restore = list[i].eth_dev->data->dev_flags; 2285 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2286 /* Restore non-PCI flags cleared by the above call. */ 2287 list[i].eth_dev->data->dev_flags |= restore; 2288 rte_eth_dev_probing_finish(list[i].eth_dev); 2289 } 2290 if (i != ns) { 2291 DRV_LOG(ERR, 2292 "probe of PCI device " PCI_PRI_FMT " aborted after" 2293 " encountering an error: %s", 2294 owner_pci.domain, owner_pci.bus, 2295 owner_pci.devid, owner_pci.function, 2296 strerror(rte_errno)); 2297 ret = -rte_errno; 2298 /* Roll back. */ 2299 while (i--) { 2300 if (!list[i].eth_dev) 2301 continue; 2302 mlx5_dev_close(list[i].eth_dev); 2303 /* mac_addrs must not be freed because in dev_private */ 2304 list[i].eth_dev->data->mac_addrs = NULL; 2305 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2306 } 2307 /* Restore original error. */ 2308 rte_errno = -ret; 2309 } else { 2310 ret = 0; 2311 } 2312 exit: 2313 /* 2314 * Do the routine cleanup: 2315 * - close opened Netlink sockets 2316 * - free allocated spawn data array 2317 * - free the Infiniband device list 2318 */ 2319 if (nl_rdma >= 0) 2320 close(nl_rdma); 2321 if (nl_route >= 0) 2322 close(nl_route); 2323 if (list) 2324 mlx5_free(list); 2325 MLX5_ASSERT(ibv_list); 2326 mlx5_glue->free_device_list(ibv_list); 2327 return ret; 2328 } 2329 2330 /** 2331 * DPDK callback to register a PCI device. 2332 * 2333 * This function spawns Ethernet devices out of a given PCI device. 2334 * 2335 * @param[in] pci_drv 2336 * PCI driver structure (mlx5_driver). 2337 * @param[in] pci_dev 2338 * PCI device information. 2339 * 2340 * @return 2341 * 0 on success, a negative errno value otherwise and rte_errno is set. 2342 */ 2343 int 2344 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2345 struct rte_pci_device *pci_dev) 2346 { 2347 struct rte_eth_devargs eth_da = { .type = RTE_ETH_REPRESENTOR_NONE }; 2348 int ret = 0; 2349 uint16_t p; 2350 2351 if (pci_dev->device.devargs) { 2352 /* Parse representor information from device argument. */ 2353 if (pci_dev->device.devargs->cls_str) 2354 ret = rte_eth_devargs_parse 2355 (pci_dev->device.devargs->cls_str, ð_da); 2356 if (ret) { 2357 DRV_LOG(ERR, "failed to parse device arguments: %s", 2358 pci_dev->device.devargs->cls_str); 2359 return -rte_errno; 2360 } 2361 if (eth_da.type == RTE_ETH_REPRESENTOR_NONE) { 2362 /* Support legacy device argument */ 2363 ret = rte_eth_devargs_parse 2364 (pci_dev->device.devargs->args, ð_da); 2365 if (ret) { 2366 DRV_LOG(ERR, "failed to parse device arguments: %s", 2367 pci_dev->device.devargs->args); 2368 return -rte_errno; 2369 } 2370 } 2371 } 2372 2373 if (eth_da.nb_ports > 0) { 2374 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2375 for (p = 0; p < eth_da.nb_ports; p++) 2376 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2377 eth_da.ports[p]); 2378 } else { 2379 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2380 } 2381 return ret; 2382 } 2383 2384 static int 2385 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2386 { 2387 char *env; 2388 int value; 2389 2390 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2391 /* Get environment variable to store. */ 2392 env = getenv(MLX5_SHUT_UP_BF); 2393 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2394 if (config->dbnc == MLX5_ARG_UNSET) 2395 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2396 else 2397 setenv(MLX5_SHUT_UP_BF, 2398 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2399 return value; 2400 } 2401 2402 static void 2403 mlx5_restore_doorbell_mapping_env(int value) 2404 { 2405 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2406 /* Restore the original environment variable state. */ 2407 if (value == MLX5_ARG_UNSET) 2408 unsetenv(MLX5_SHUT_UP_BF); 2409 else 2410 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2411 } 2412 2413 /** 2414 * Extract pdn of PD object using DV API. 2415 * 2416 * @param[in] pd 2417 * Pointer to the verbs PD object. 2418 * @param[out] pdn 2419 * Pointer to the PD object number variable. 2420 * 2421 * @return 2422 * 0 on success, error value otherwise. 2423 */ 2424 int 2425 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2426 { 2427 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2428 struct mlx5dv_obj obj; 2429 struct mlx5dv_pd pd_info; 2430 int ret = 0; 2431 2432 obj.pd.in = pd; 2433 obj.pd.out = &pd_info; 2434 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2435 if (ret) { 2436 DRV_LOG(DEBUG, "Fail to get PD object info"); 2437 return ret; 2438 } 2439 *pdn = pd_info.pdn; 2440 return 0; 2441 #else 2442 (void)pd; 2443 (void)pdn; 2444 return -ENOTSUP; 2445 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2446 } 2447 2448 /** 2449 * Function API to open IB device. 2450 * 2451 * This function calls the Linux glue APIs to open a device. 2452 * 2453 * @param[in] spawn 2454 * Pointer to the IB device attributes (name, port, etc). 2455 * @param[out] config 2456 * Pointer to device configuration structure. 2457 * @param[out] sh 2458 * Pointer to shared context structure. 2459 * 2460 * @return 2461 * 0 on success, a positive error value otherwise. 2462 */ 2463 int 2464 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2465 const struct mlx5_dev_config *config, 2466 struct mlx5_dev_ctx_shared *sh) 2467 { 2468 int dbmap_env; 2469 int err = 0; 2470 2471 sh->numa_node = spawn->pci_dev->device.numa_node; 2472 pthread_mutex_init(&sh->txpp.mutex, NULL); 2473 /* 2474 * Configure environment variable "MLX5_BF_SHUT_UP" 2475 * before the device creation. The rdma_core library 2476 * checks the variable at device creation and 2477 * stores the result internally. 2478 */ 2479 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2480 /* Try to open IB device with DV first, then usual Verbs. */ 2481 errno = 0; 2482 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2483 if (sh->ctx) { 2484 sh->devx = 1; 2485 DRV_LOG(DEBUG, "DevX is supported"); 2486 /* The device is created, no need for environment. */ 2487 mlx5_restore_doorbell_mapping_env(dbmap_env); 2488 } else { 2489 /* The environment variable is still configured. */ 2490 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2491 err = errno ? errno : ENODEV; 2492 /* 2493 * The environment variable is not needed anymore, 2494 * all device creation attempts are completed. 2495 */ 2496 mlx5_restore_doorbell_mapping_env(dbmap_env); 2497 if (!sh->ctx) 2498 return err; 2499 DRV_LOG(DEBUG, "DevX is NOT supported"); 2500 err = 0; 2501 } 2502 if (!err && sh->ctx) { 2503 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2504 mlx5_glue->dv_set_context_attr(sh->ctx, 2505 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2506 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2507 .alloc = &mlx5_alloc_verbs_buf, 2508 .free = &mlx5_free_verbs_buf, 2509 .data = sh, 2510 })); 2511 } 2512 return err; 2513 } 2514 2515 /** 2516 * Install shared asynchronous device events handler. 2517 * This function is implemented to support event sharing 2518 * between multiple ports of single IB device. 2519 * 2520 * @param sh 2521 * Pointer to mlx5_dev_ctx_shared object. 2522 */ 2523 void 2524 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2525 { 2526 int ret; 2527 int flags; 2528 2529 sh->intr_handle.fd = -1; 2530 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2531 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2532 F_SETFL, flags | O_NONBLOCK); 2533 if (ret) { 2534 DRV_LOG(INFO, "failed to change file descriptor async event" 2535 " queue"); 2536 } else { 2537 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2538 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2539 if (rte_intr_callback_register(&sh->intr_handle, 2540 mlx5_dev_interrupt_handler, sh)) { 2541 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2542 sh->intr_handle.fd = -1; 2543 } 2544 } 2545 if (sh->devx) { 2546 #ifdef HAVE_IBV_DEVX_ASYNC 2547 sh->intr_handle_devx.fd = -1; 2548 sh->devx_comp = 2549 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2550 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2551 if (!devx_comp) { 2552 DRV_LOG(INFO, "failed to allocate devx_comp."); 2553 return; 2554 } 2555 flags = fcntl(devx_comp->fd, F_GETFL); 2556 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2557 if (ret) { 2558 DRV_LOG(INFO, "failed to change file descriptor" 2559 " devx comp"); 2560 return; 2561 } 2562 sh->intr_handle_devx.fd = devx_comp->fd; 2563 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2564 if (rte_intr_callback_register(&sh->intr_handle_devx, 2565 mlx5_dev_interrupt_handler_devx, sh)) { 2566 DRV_LOG(INFO, "Fail to install the devx shared" 2567 " interrupt."); 2568 sh->intr_handle_devx.fd = -1; 2569 } 2570 #endif /* HAVE_IBV_DEVX_ASYNC */ 2571 } 2572 } 2573 2574 /** 2575 * Uninstall shared asynchronous device events handler. 2576 * This function is implemented to support event sharing 2577 * between multiple ports of single IB device. 2578 * 2579 * @param dev 2580 * Pointer to mlx5_dev_ctx_shared object. 2581 */ 2582 void 2583 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2584 { 2585 if (sh->intr_handle.fd >= 0) 2586 mlx5_intr_callback_unregister(&sh->intr_handle, 2587 mlx5_dev_interrupt_handler, sh); 2588 #ifdef HAVE_IBV_DEVX_ASYNC 2589 if (sh->intr_handle_devx.fd >= 0) 2590 rte_intr_callback_unregister(&sh->intr_handle_devx, 2591 mlx5_dev_interrupt_handler_devx, sh); 2592 if (sh->devx_comp) 2593 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2594 #endif 2595 } 2596 2597 /** 2598 * Read statistics by a named counter. 2599 * 2600 * @param[in] priv 2601 * Pointer to the private device data structure. 2602 * @param[in] ctr_name 2603 * Pointer to the name of the statistic counter to read 2604 * @param[out] stat 2605 * Pointer to read statistic value. 2606 * @return 2607 * 0 on success and stat is valud, 1 if failed to read the value 2608 * rte_errno is set. 2609 * 2610 */ 2611 int 2612 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2613 uint64_t *stat) 2614 { 2615 int fd; 2616 2617 if (priv->sh) { 2618 if (priv->q_counters != NULL && 2619 strcmp(ctr_name, "out_of_buffer") == 0) 2620 return mlx5_devx_cmd_queue_counter_query(priv->sh->ctx, 2621 0, (uint32_t *)stat); 2622 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2623 priv->sh->ibdev_path, 2624 priv->dev_port, 2625 ctr_name); 2626 fd = open(path, O_RDONLY); 2627 /* 2628 * in switchdev the file location is not per port 2629 * but rather in <ibdev_path>/hw_counters/<file_name>. 2630 */ 2631 if (fd == -1) { 2632 MKSTR(path1, "%s/hw_counters/%s", 2633 priv->sh->ibdev_path, 2634 ctr_name); 2635 fd = open(path1, O_RDONLY); 2636 } 2637 if (fd != -1) { 2638 char buf[21] = {'\0'}; 2639 ssize_t n = read(fd, buf, sizeof(buf)); 2640 2641 close(fd); 2642 if (n != -1) { 2643 *stat = strtoull(buf, NULL, 10); 2644 return 0; 2645 } 2646 } 2647 } 2648 *stat = 0; 2649 return 1; 2650 } 2651 2652 /** 2653 * Set the reg_mr and dereg_mr call backs 2654 * 2655 * @param reg_mr_cb[out] 2656 * Pointer to reg_mr func 2657 * @param dereg_mr_cb[out] 2658 * Pointer to dereg_mr func 2659 * 2660 */ 2661 void 2662 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2663 mlx5_dereg_mr_t *dereg_mr_cb) 2664 { 2665 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 2666 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 2667 } 2668 2669 /** 2670 * Remove a MAC address from device 2671 * 2672 * @param dev 2673 * Pointer to Ethernet device structure. 2674 * @param index 2675 * MAC address index. 2676 */ 2677 void 2678 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2679 { 2680 struct mlx5_priv *priv = dev->data->dev_private; 2681 const int vf = priv->config.vf; 2682 2683 if (vf) 2684 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2685 mlx5_ifindex(dev), priv->mac_own, 2686 &dev->data->mac_addrs[index], index); 2687 } 2688 2689 /** 2690 * Adds a MAC address to the device 2691 * 2692 * @param dev 2693 * Pointer to Ethernet device structure. 2694 * @param mac_addr 2695 * MAC address to register. 2696 * @param index 2697 * MAC address index. 2698 * 2699 * @return 2700 * 0 on success, a negative errno value otherwise 2701 */ 2702 int 2703 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2704 uint32_t index) 2705 { 2706 struct mlx5_priv *priv = dev->data->dev_private; 2707 const int vf = priv->config.vf; 2708 int ret = 0; 2709 2710 if (vf) 2711 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2712 mlx5_ifindex(dev), priv->mac_own, 2713 mac, index); 2714 return ret; 2715 } 2716 2717 /** 2718 * Modify a VF MAC address 2719 * 2720 * @param priv 2721 * Pointer to device private data. 2722 * @param mac_addr 2723 * MAC address to modify into. 2724 * @param iface_idx 2725 * Net device interface index 2726 * @param vf_index 2727 * VF index 2728 * 2729 * @return 2730 * 0 on success, a negative errno value otherwise 2731 */ 2732 int 2733 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2734 unsigned int iface_idx, 2735 struct rte_ether_addr *mac_addr, 2736 int vf_index) 2737 { 2738 return mlx5_nl_vf_mac_addr_modify 2739 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2740 } 2741 2742 /** 2743 * Set device promiscuous mode 2744 * 2745 * @param dev 2746 * Pointer to Ethernet device structure. 2747 * @param enable 2748 * 0 - promiscuous is disabled, otherwise - enabled 2749 * 2750 * @return 2751 * 0 on success, a negative error value otherwise 2752 */ 2753 int 2754 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2755 { 2756 struct mlx5_priv *priv = dev->data->dev_private; 2757 2758 return mlx5_nl_promisc(priv->nl_socket_route, 2759 mlx5_ifindex(dev), !!enable); 2760 } 2761 2762 /** 2763 * Set device promiscuous mode 2764 * 2765 * @param dev 2766 * Pointer to Ethernet device structure. 2767 * @param enable 2768 * 0 - all multicase is disabled, otherwise - enabled 2769 * 2770 * @return 2771 * 0 on success, a negative error value otherwise 2772 */ 2773 int 2774 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2775 { 2776 struct mlx5_priv *priv = dev->data->dev_private; 2777 2778 return mlx5_nl_allmulti(priv->nl_socket_route, 2779 mlx5_ifindex(dev), !!enable); 2780 } 2781 2782 /** 2783 * Flush device MAC addresses 2784 * 2785 * @param dev 2786 * Pointer to Ethernet device structure. 2787 * 2788 */ 2789 void 2790 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2791 { 2792 struct mlx5_priv *priv = dev->data->dev_private; 2793 2794 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2795 dev->data->mac_addrs, 2796 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2797 } 2798