1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #ifndef _IONIC_LIF_H_ 6 #define _IONIC_LIF_H_ 7 8 #include <inttypes.h> 9 10 #include <rte_ethdev.h> 11 #include <rte_ether.h> 12 13 #include "ionic_osdep.h" 14 #include "ionic_dev.h" 15 #include "ionic_rx_filter.h" 16 17 #define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */ 18 #define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */ 19 20 #define IONIC_MBUF_BULK_ALLOC 64 /* Multiple of 4 */ 21 22 #define IONIC_RSS_OFFLOAD_ALL ( \ 23 IONIC_RSS_TYPE_IPV4 | \ 24 IONIC_RSS_TYPE_IPV4_TCP | \ 25 IONIC_RSS_TYPE_IPV4_UDP | \ 26 IONIC_RSS_TYPE_IPV6 | \ 27 IONIC_RSS_TYPE_IPV6_TCP | \ 28 IONIC_RSS_TYPE_IPV6_UDP) 29 30 #define IONIC_GET_SG_CNTR_IDX(num_sg_elems) (num_sg_elems) 31 32 struct ionic_tx_stats { 33 uint64_t packets; 34 uint64_t bytes; 35 uint64_t drop; 36 uint64_t stop; 37 uint64_t no_csum; 38 uint64_t tso; 39 }; 40 41 struct ionic_rx_stats { 42 uint64_t packets; 43 uint64_t bytes; 44 uint64_t bad_cq_status; 45 uint64_t bad_len; 46 uint64_t mtods; 47 }; 48 49 #define IONIC_QCQ_F_INITED BIT(0) 50 #define IONIC_QCQ_F_SG BIT(1) 51 #define IONIC_QCQ_F_DEFERRED BIT(4) 52 #define IONIC_QCQ_F_CMB BIT(5) 53 #define IONIC_QCQ_F_CSUM_L3 BIT(7) 54 #define IONIC_QCQ_F_CSUM_UDP BIT(8) 55 #define IONIC_QCQ_F_CSUM_TCP BIT(9) 56 #define IONIC_QCQ_F_FAST_FREE BIT(10) 57 58 /* Queue / Completion Queue */ 59 struct ionic_qcq { 60 struct ionic_queue q; /**< Queue */ 61 struct ionic_cq cq; /**< Completion Queue */ 62 struct ionic_lif *lif; /**< LIF */ 63 const struct rte_memzone *base_z; 64 void *base; 65 rte_iova_t base_pa; 66 }; 67 68 struct ionic_admin_qcq { 69 struct ionic_qcq qcq; 70 uint16_t flags; 71 }; 72 73 struct ionic_notify_qcq { 74 struct ionic_qcq qcq; 75 uint16_t flags; 76 77 struct ionic_intr_info intr; 78 }; 79 80 struct ionic_rx_qcq { 81 /* cacheline0, cacheline1 */ 82 struct ionic_qcq qcq; 83 84 /* cacheline2 */ 85 struct rte_mempool *mb_pool; 86 uint64_t rearm_data; 87 uint64_t rearm_seg_data; 88 uint64_t last_wdog_cycles; 89 uint64_t wdog_ms; 90 uint16_t frame_size; /* Based on configured MTU */ 91 uint16_t hdr_seg_size; /* Length of first segment of RX chain */ 92 uint16_t seg_size; /* Length of all subsequent segments */ 93 uint16_t flags; 94 uint16_t mb_idx; 95 96 /* cacheline3 (inside stats) */ 97 struct ionic_rx_stats stats; 98 99 /* cacheline4+ */ 100 struct rte_mbuf *mbs[IONIC_MBUF_BULK_ALLOC] __rte_cache_aligned; 101 }; 102 103 struct ionic_tx_qcq { 104 /* cacheline0, cacheline1 */ 105 struct ionic_qcq qcq; 106 107 /* cacheline2 */ 108 uint64_t last_wdog_cycles; 109 uint16_t num_segs_fw; /* # segs supported by current FW */ 110 uint16_t free_thresh; 111 uint16_t flags; 112 113 struct ionic_tx_stats stats; 114 }; 115 116 #define IONIC_Q_TO_QCQ(_q) container_of(_q, struct ionic_qcq, q) 117 #define IONIC_CQ_TO_QCQ(_cq) container_of(_cq, struct ionic_qcq, cq) 118 119 struct ionic_qtype_info { 120 uint8_t version; 121 uint8_t supported; 122 uint64_t features; 123 uint16_t desc_sz; 124 uint16_t comp_sz; 125 uint16_t sg_desc_sz; 126 uint16_t max_sg_elems; 127 uint16_t sg_desc_stride; 128 }; 129 130 #define IONIC_LIF_F_INITED BIT(0) 131 #define IONIC_LIF_F_LINK_CHECK_NEEDED BIT(1) 132 #define IONIC_LIF_F_UP BIT(2) 133 #define IONIC_LIF_F_FW_RESET BIT(3) 134 #define IONIC_LIF_F_Q_IN_CMB BIT(4) 135 136 #define IONIC_LIF_NAME_MAX_SZ (32) 137 138 struct ionic_lif { 139 struct ionic_adapter *adapter; 140 struct rte_eth_dev *eth_dev; 141 uint16_t port_id; /**< Device port identifier */ 142 uint16_t frame_size; 143 uint32_t hw_index; 144 uint32_t state; 145 uint32_t ntxqcqs; 146 uint32_t nrxqcqs; 147 rte_spinlock_t adminq_lock; 148 rte_spinlock_t adminq_service_lock; 149 struct ionic_admin_qcq *adminqcq; 150 struct ionic_notify_qcq *notifyqcq; 151 struct ionic_tx_qcq **txqcqs; 152 struct ionic_rx_qcq **rxqcqs; 153 struct ionic_rx_filters rx_filters; 154 struct ionic_doorbell __iomem *kern_dbpage; 155 uint64_t last_eid; 156 uint64_t features; 157 uint32_t hw_features; 158 uint32_t rx_mode; 159 char name[IONIC_LIF_NAME_MAX_SZ]; 160 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 161 uint16_t rss_types; 162 uint8_t rss_hash_key[IONIC_RSS_HASH_KEY_SIZE]; 163 uint8_t *rss_ind_tbl; 164 rte_iova_t rss_ind_tbl_pa; 165 const struct rte_memzone *rss_ind_tbl_z; 166 uint32_t rss_ind_tbl_nrxqcqs; 167 uint32_t info_sz; 168 struct ionic_lif_info *info; 169 rte_iova_t info_pa; 170 const struct rte_memzone *info_z; 171 172 struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX]; 173 uint8_t qtype_ver[IONIC_QTYPE_MAX]; 174 175 struct rte_eth_stats stats_base; 176 struct ionic_lif_stats lif_stats_base; 177 }; 178 179 int ionic_lif_identify(struct ionic_adapter *adapter); 180 int ionic_lifs_size(struct ionic_adapter *ionic); 181 182 int ionic_lif_alloc(struct ionic_lif *lif); 183 void ionic_lif_free(struct ionic_lif *lif); 184 void ionic_lif_free_queues(struct ionic_lif *lif); 185 186 int ionic_lif_init(struct ionic_lif *lif); 187 void ionic_lif_deinit(struct ionic_lif *lif); 188 189 int ionic_lif_start(struct ionic_lif *lif); 190 void ionic_lif_stop(struct ionic_lif *lif); 191 192 void ionic_lif_configure(struct ionic_lif *lif); 193 void ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask); 194 void ionic_lif_configure_rx_sg_offload(struct ionic_lif *lif); 195 void ionic_lif_reset(struct ionic_lif *lif); 196 197 int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr); 198 199 int ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb, 200 void *cb_arg); 201 202 int ionic_lif_change_mtu(struct ionic_lif *lif, uint32_t new_mtu); 203 204 int ionic_dev_add_mac(struct rte_eth_dev *eth_dev, 205 struct rte_ether_addr *mac_addr, 206 uint32_t index __rte_unused, uint32_t pool __rte_unused); 207 void ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, 208 uint32_t index __rte_unused); 209 int ionic_dev_set_mac(struct rte_eth_dev *eth_dev, 210 struct rte_ether_addr *mac_addr); 211 int ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id, 212 int on); 213 int ionic_dev_promiscuous_enable(struct rte_eth_dev *dev); 214 int ionic_dev_promiscuous_disable(struct rte_eth_dev *dev); 215 int ionic_dev_allmulticast_enable(struct rte_eth_dev *dev); 216 int ionic_dev_allmulticast_disable(struct rte_eth_dev *dev); 217 218 int ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, 219 uint32_t index, uint16_t nrxq_descs, struct rte_mempool *mp, 220 struct ionic_rx_qcq **qcq_out); 221 int ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, 222 uint32_t index, uint16_t ntxq_descs, 223 struct ionic_tx_qcq **qcq_out); 224 void ionic_qcq_free(struct ionic_qcq *qcq); 225 226 int ionic_lif_rxq_init(struct ionic_rx_qcq *rxq); 227 void ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq); 228 229 int ionic_lif_txq_init(struct ionic_tx_qcq *txq); 230 void ionic_lif_txq_deinit(struct ionic_tx_qcq *txq); 231 232 int ionic_lif_rss_config(struct ionic_lif *lif, const uint16_t types, 233 const uint8_t *key, const uint32_t *indir); 234 235 int ionic_lif_set_features(struct ionic_lif *lif); 236 237 void ionic_lif_get_stats(const struct ionic_lif *lif, 238 struct rte_eth_stats *stats); 239 void ionic_lif_reset_stats(struct ionic_lif *lif); 240 241 void ionic_lif_get_hw_stats(struct ionic_lif *lif, 242 struct ionic_lif_stats *stats); 243 void ionic_lif_reset_hw_stats(struct ionic_lif *lif); 244 245 int ionic_notifyq_handler(struct ionic_lif *lif, int budget); 246 247 #endif /* _IONIC_LIF_H_ */ 248