1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #ifndef _IONIC_LIF_H_ 6 #define _IONIC_LIF_H_ 7 8 #include <inttypes.h> 9 10 #include <rte_ethdev.h> 11 #include <rte_ether.h> 12 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_rx_filter.h" 16 17 #define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */ 18 #define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */ 19 20 #define IONIC_MBUF_BULK_ALLOC 64 /* Multiple of 4 */ 21 22 #define IONIC_RSS_OFFLOAD_ALL ( \ 23 IONIC_RSS_TYPE_IPV4 | \ 24 IONIC_RSS_TYPE_IPV4_TCP | \ 25 IONIC_RSS_TYPE_IPV4_UDP | \ 26 IONIC_RSS_TYPE_IPV6 | \ 27 IONIC_RSS_TYPE_IPV6_TCP | \ 28 IONIC_RSS_TYPE_IPV6_UDP) 29 30 #define IONIC_GET_SG_CNTR_IDX(num_sg_elems) (num_sg_elems) 31 32 struct ionic_tx_stats { 33 uint64_t packets; 34 uint64_t bytes; 35 uint64_t comps; 36 uint64_t drop; 37 uint64_t stop; 38 uint64_t no_csum; 39 uint64_t tso; 40 }; 41 42 struct ionic_rx_stats { 43 uint64_t packets; 44 uint64_t bytes; 45 uint64_t bad_cq_status; 46 uint64_t bad_len; 47 uint64_t mtods; 48 }; 49 50 #define IONIC_QCQ_F_INITED BIT(0) 51 #define IONIC_QCQ_F_SG BIT(1) 52 #define IONIC_QCQ_F_DEFERRED BIT(4) 53 #define IONIC_QCQ_F_CMB BIT(5) 54 #define IONIC_QCQ_F_CSUM_L3 BIT(7) 55 #define IONIC_QCQ_F_CSUM_UDP BIT(8) 56 #define IONIC_QCQ_F_CSUM_TCP BIT(9) 57 #define IONIC_QCQ_F_FAST_FREE BIT(10) 58 59 /* Queue / Completion Queue */ 60 struct ionic_qcq { 61 struct ionic_queue q; /**< Queue */ 62 struct ionic_cq cq; /**< Completion Queue */ 63 struct ionic_lif *lif; /**< LIF */ 64 const struct rte_memzone *base_z; 65 void *base; 66 rte_iova_t base_pa; 67 }; 68 69 struct ionic_admin_qcq { 70 struct ionic_qcq qcq; 71 uint16_t flags; 72 }; 73 74 struct ionic_notify_qcq { 75 struct ionic_qcq qcq; 76 uint16_t flags; 77 78 struct ionic_intr_info intr; 79 }; 80 81 struct ionic_rx_qcq { 82 /* cacheline0, cacheline1 */ 83 struct ionic_qcq qcq; 84 85 /* cacheline2 */ 86 struct rte_mempool *mb_pool; 87 uint64_t rearm_data; 88 uint64_t rearm_seg_data; 89 uint64_t last_wdog_cycles; 90 uint64_t wdog_ms; 91 uint16_t frame_size; /* Based on configured MTU */ 92 uint16_t hdr_seg_size; /* Length of first segment of RX chain */ 93 uint16_t seg_size; /* Length of all subsequent segments */ 94 uint16_t flags; 95 uint16_t mb_idx; 96 97 /* cacheline3 (inside stats) */ 98 struct ionic_rx_stats stats; 99 100 /* cacheline4+ */ 101 alignas(RTE_CACHE_LINE_SIZE) struct rte_mbuf *mbs[IONIC_MBUF_BULK_ALLOC]; 102 103 struct ionic_admin_ctx admin_ctx; 104 }; 105 106 struct ionic_tx_qcq { 107 /* cacheline0, cacheline1 */ 108 struct ionic_qcq qcq; 109 110 /* cacheline2 */ 111 uint64_t last_wdog_cycles; 112 uint16_t num_segs_fw; /* # segs supported by current FW */ 113 uint16_t free_thresh; 114 uint16_t flags; 115 116 struct ionic_tx_stats stats; 117 118 struct ionic_admin_ctx admin_ctx; 119 }; 120 121 #define IONIC_Q_TO_QCQ(_q) container_of(_q, struct ionic_qcq, q) 122 #define IONIC_CQ_TO_QCQ(_cq) container_of(_cq, struct ionic_qcq, cq) 123 124 struct ionic_qtype_info { 125 uint8_t version; 126 uint8_t supported; 127 uint64_t features; 128 uint16_t desc_sz; 129 uint16_t comp_sz; 130 uint16_t sg_desc_sz; 131 uint16_t max_sg_elems; 132 uint16_t sg_desc_stride; 133 }; 134 135 #define IONIC_LIF_F_INITED BIT(0) 136 #define IONIC_LIF_F_LINK_CHECK_NEEDED BIT(1) 137 #define IONIC_LIF_F_UP BIT(2) 138 #define IONIC_LIF_F_FW_RESET BIT(3) 139 #define IONIC_LIF_F_Q_IN_CMB BIT(4) 140 141 #define IONIC_LIF_NAME_MAX_SZ (32) 142 143 struct ionic_lif { 144 struct ionic_adapter *adapter; 145 struct rte_eth_dev *eth_dev; 146 uint16_t port_id; /**< Device port identifier */ 147 uint16_t frame_size; 148 uint32_t hw_index; 149 uint32_t state; 150 uint32_t ntxqcqs; 151 uint32_t nrxqcqs; 152 rte_spinlock_t adminq_lock; 153 rte_spinlock_t adminq_service_lock; 154 struct ionic_admin_qcq *adminqcq; 155 struct ionic_notify_qcq *notifyqcq; 156 struct ionic_tx_qcq **txqcqs; 157 struct ionic_rx_qcq **rxqcqs; 158 struct ionic_rx_filters rx_filters; 159 struct ionic_doorbell __iomem *kern_dbpage; 160 uint64_t last_eid; 161 uint64_t features; 162 uint32_t hw_features; 163 uint32_t rx_mode; 164 char name[IONIC_LIF_NAME_MAX_SZ]; 165 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 166 uint16_t rss_types; 167 uint8_t rss_hash_key[IONIC_RSS_HASH_KEY_SIZE]; 168 uint8_t *rss_ind_tbl; 169 rte_iova_t rss_ind_tbl_pa; 170 const struct rte_memzone *rss_ind_tbl_z; 171 uint32_t rss_ind_tbl_nrxqcqs; 172 uint32_t info_sz; 173 struct ionic_lif_info *info; 174 rte_iova_t info_pa; 175 const struct rte_memzone *info_z; 176 177 struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX]; 178 uint8_t qtype_ver[IONIC_QTYPE_MAX]; 179 180 struct rte_eth_stats stats_base; 181 struct ionic_lif_stats lif_stats_base; 182 }; 183 184 int ionic_lif_identify(struct ionic_adapter *adapter); 185 int ionic_lifs_size(struct ionic_adapter *ionic); 186 187 int ionic_lif_alloc(struct ionic_lif *lif); 188 void ionic_lif_free(struct ionic_lif *lif); 189 void ionic_lif_free_queues(struct ionic_lif *lif); 190 191 int ionic_lif_init(struct ionic_lif *lif); 192 void ionic_lif_deinit(struct ionic_lif *lif); 193 194 int ionic_lif_start(struct ionic_lif *lif); 195 void ionic_lif_stop(struct ionic_lif *lif); 196 197 void ionic_lif_configure(struct ionic_lif *lif); 198 void ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask); 199 void ionic_lif_configure_rx_sg_offload(struct ionic_lif *lif); 200 void ionic_lif_reset(struct ionic_lif *lif); 201 202 int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr); 203 204 int ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb, 205 void *cb_arg); 206 207 int ionic_lif_change_mtu(struct ionic_lif *lif, uint32_t new_mtu); 208 209 int ionic_dev_add_mac(struct rte_eth_dev *eth_dev, 210 struct rte_ether_addr *mac_addr, 211 uint32_t index __rte_unused, uint32_t pool __rte_unused); 212 void ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, 213 uint32_t index __rte_unused); 214 int ionic_dev_set_mac(struct rte_eth_dev *eth_dev, 215 struct rte_ether_addr *mac_addr); 216 int ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id, 217 int on); 218 int ionic_dev_promiscuous_enable(struct rte_eth_dev *dev); 219 int ionic_dev_promiscuous_disable(struct rte_eth_dev *dev); 220 int ionic_dev_allmulticast_enable(struct rte_eth_dev *dev); 221 int ionic_dev_allmulticast_disable(struct rte_eth_dev *dev); 222 223 int ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, 224 uint32_t index, uint16_t nrxq_descs, struct rte_mempool *mp, 225 struct ionic_rx_qcq **qcq_out); 226 int ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, 227 uint32_t index, uint16_t ntxq_descs, 228 struct ionic_tx_qcq **qcq_out); 229 void ionic_qcq_free(struct ionic_qcq *qcq); 230 231 int ionic_lif_rxq_init_nowait(struct ionic_rx_qcq *rxq); 232 void ionic_lif_rxq_init_done(struct ionic_rx_qcq *rxq); 233 void ionic_lif_rxq_deinit_nowait(struct ionic_rx_qcq *rxq); 234 void ionic_lif_rxq_stats(struct ionic_rx_qcq *rxq); 235 236 int ionic_lif_txq_init_nowait(struct ionic_tx_qcq *txq); 237 void ionic_lif_txq_init_done(struct ionic_tx_qcq *txq); 238 void ionic_lif_txq_deinit_nowait(struct ionic_tx_qcq *txq); 239 void ionic_lif_txq_stats(struct ionic_tx_qcq *txq); 240 241 int ionic_lif_rss_config(struct ionic_lif *lif, const uint16_t types, 242 const uint8_t *key, const uint32_t *indir); 243 244 int ionic_lif_set_features(struct ionic_lif *lif); 245 246 void ionic_lif_get_stats(const struct ionic_lif *lif, 247 struct rte_eth_stats *stats); 248 void ionic_lif_reset_stats(struct ionic_lif *lif); 249 250 void ionic_lif_get_hw_stats(struct ionic_lif *lif, 251 struct ionic_lif_stats *stats); 252 void ionic_lif_reset_hw_stats(struct ionic_lif *lif); 253 254 int ionic_notifyq_handler(struct ionic_lif *lif, int budget); 255 256 #endif /* _IONIC_LIF_H_ */ 257