1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-3-Clause */ 2 /* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #pragma pack(push, 1) 8 9 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 10 #define IONIC_DEV_INFO_VERSION 1 11 #define IONIC_IFNAMSIZ 16 12 13 /** 14 * Commands 15 */ 16 enum ionic_cmd_opcode { 17 IONIC_CMD_NOP = 0, 18 19 /* Device commands */ 20 IONIC_CMD_IDENTIFY = 1, 21 IONIC_CMD_INIT = 2, 22 IONIC_CMD_RESET = 3, 23 IONIC_CMD_GETATTR = 4, 24 IONIC_CMD_SETATTR = 5, 25 26 /* Port commands */ 27 IONIC_CMD_PORT_IDENTIFY = 10, 28 IONIC_CMD_PORT_INIT = 11, 29 IONIC_CMD_PORT_RESET = 12, 30 IONIC_CMD_PORT_GETATTR = 13, 31 IONIC_CMD_PORT_SETATTR = 14, 32 33 /* LIF commands */ 34 IONIC_CMD_LIF_IDENTIFY = 20, 35 IONIC_CMD_LIF_INIT = 21, 36 IONIC_CMD_LIF_RESET = 22, 37 IONIC_CMD_LIF_GETATTR = 23, 38 IONIC_CMD_LIF_SETATTR = 24, 39 40 IONIC_CMD_RX_MODE_SET = 30, 41 IONIC_CMD_RX_FILTER_ADD = 31, 42 IONIC_CMD_RX_FILTER_DEL = 32, 43 44 /* Queue commands */ 45 IONIC_CMD_Q_INIT = 40, 46 IONIC_CMD_Q_CONTROL = 41, 47 48 /* RDMA commands */ 49 IONIC_CMD_RDMA_RESET_LIF = 50, 50 IONIC_CMD_RDMA_CREATE_EQ = 51, 51 IONIC_CMD_RDMA_CREATE_CQ = 52, 52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 53 54 /* QoS commands */ 55 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 56 IONIC_CMD_QOS_CLASS_INIT = 241, 57 IONIC_CMD_QOS_CLASS_RESET = 242, 58 59 /* Firmware commands */ 60 IONIC_CMD_FW_DOWNLOAD = 254, 61 IONIC_CMD_FW_CONTROL = 255, 62 }; 63 64 /** 65 * Command Return codes 66 */ 67 enum ionic_status_code { 68 IONIC_RC_SUCCESS = 0, /* Success */ 69 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 70 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 71 IONIC_RC_EIO = 3, /* I/O error */ 72 IONIC_RC_EPERM = 4, /* Permission denied */ 73 IONIC_RC_EQID = 5, /* Bad qid */ 74 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 75 IONIC_RC_ENOENT = 7, /* No such element */ 76 IONIC_RC_EINTR = 8, /* operation interrupted */ 77 IONIC_RC_EAGAIN = 9, /* Try again */ 78 IONIC_RC_ENOMEM = 10, /* Out of memory */ 79 IONIC_RC_EFAULT = 11, /* Bad address */ 80 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 81 IONIC_RC_EEXIST = 13, /* object already exists */ 82 IONIC_RC_EINVAL = 14, /* Invalid argument */ 83 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 84 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 85 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 86 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 87 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 88 IONIC_RC_ERROR = 29, /* Generic error */ 89 90 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 91 }; 92 93 enum ionic_notifyq_opcode { 94 IONIC_EVENT_LINK_CHANGE = 1, 95 IONIC_EVENT_RESET = 2, 96 IONIC_EVENT_HEARTBEAT = 3, 97 IONIC_EVENT_LOG = 4, 98 }; 99 100 /** 101 * struct cmd - General admin command format 102 * @opcode: Opcode for the command 103 * @lif_index: LIF index 104 * @cmd_data: Opcode-specific command bytes 105 */ 106 struct ionic_admin_cmd { 107 u8 opcode; 108 u8 rsvd; 109 __le16 lif_index; 110 u8 cmd_data[60]; 111 }; 112 113 /** 114 * struct ionic_admin_comp - General admin command completion format 115 * @status: The status of the command (enum status_code) 116 * @comp_index: The index in the descriptor ring for which this 117 * is the completion. 118 * @cmd_data: Command-specific bytes. 119 * @color: Color bit. (Always 0 for commands issued to the 120 * Device Cmd Registers.) 121 */ 122 struct ionic_admin_comp { 123 u8 status; 124 u8 rsvd; 125 __le16 comp_index; 126 u8 cmd_data[11]; 127 u8 color; 128 #define IONIC_COMP_COLOR_MASK 0x80 129 }; 130 131 static inline u8 color_match(u8 color, u8 done_color) 132 { 133 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 134 } 135 136 /** 137 * struct ionic_nop_cmd - NOP command 138 * @opcode: opcode 139 */ 140 struct ionic_nop_cmd { 141 u8 opcode; 142 u8 rsvd[63]; 143 }; 144 145 /** 146 * struct ionic_nop_comp - NOP command completion 147 * @status: The status of the command (enum status_code) 148 */ 149 struct ionic_nop_comp { 150 u8 status; 151 u8 rsvd[15]; 152 }; 153 154 /** 155 * struct ionic_dev_init_cmd - Device init command 156 * @opcode: opcode 157 * @type: device type 158 */ 159 struct ionic_dev_init_cmd { 160 u8 opcode; 161 u8 type; 162 u8 rsvd[62]; 163 }; 164 165 /** 166 * struct init_comp - Device init command completion 167 * @status: The status of the command (enum status_code) 168 */ 169 struct ionic_dev_init_comp { 170 u8 status; 171 u8 rsvd[15]; 172 }; 173 174 /** 175 * struct ionic_dev_reset_cmd - Device reset command 176 * @opcode: opcode 177 */ 178 struct ionic_dev_reset_cmd { 179 u8 opcode; 180 u8 rsvd[63]; 181 }; 182 183 /** 184 * struct reset_comp - Reset command completion 185 * @status: The status of the command (enum status_code) 186 */ 187 struct ionic_dev_reset_comp { 188 u8 status; 189 u8 rsvd[15]; 190 }; 191 192 #define IONIC_IDENTITY_VERSION_1 1 193 194 /** 195 * struct ionic_dev_identify_cmd - Driver/device identify command 196 * @opcode: opcode 197 * @ver: Highest version of identify supported by driver 198 */ 199 struct ionic_dev_identify_cmd { 200 u8 opcode; 201 u8 ver; 202 u8 rsvd[62]; 203 }; 204 205 /** 206 * struct dev_identify_comp - Driver/device identify command completion 207 * @status: The status of the command (enum status_code) 208 * @ver: Version of identify returned by device 209 */ 210 struct ionic_dev_identify_comp { 211 u8 status; 212 u8 ver; 213 u8 rsvd[14]; 214 }; 215 216 enum ionic_os_type { 217 IONIC_OS_TYPE_LINUX = 1, 218 IONIC_OS_TYPE_WIN = 2, 219 IONIC_OS_TYPE_DPDK = 3, 220 IONIC_OS_TYPE_FREEBSD = 4, 221 IONIC_OS_TYPE_IPXE = 5, 222 IONIC_OS_TYPE_ESXI = 6, 223 }; 224 225 /** 226 * union drv_identity - driver identity information 227 * @os_type: OS type (see enum os_type) 228 * @os_dist: OS distribution, numeric format 229 * @os_dist_str: OS distribution, string format 230 * @kernel_ver: Kernel version, numeric format 231 * @kernel_ver_str: Kernel version, string format 232 * @driver_ver_str: Driver version, string format 233 */ 234 union ionic_drv_identity { 235 struct { 236 __le32 os_type; 237 __le32 os_dist; 238 char os_dist_str[128]; 239 __le32 kernel_ver; 240 char kernel_ver_str[32]; 241 char driver_ver_str[32]; 242 }; 243 __le32 words[512]; 244 }; 245 246 /** 247 * union dev_identity - device identity information 248 * @version: Version of device identify 249 * @type: Identify type (0 for now) 250 * @nports: Number of ports provisioned 251 * @nlifs: Number of LIFs provisioned 252 * @nintrs: Number of interrupts provisioned 253 * @ndbpgs_per_lif: Number of doorbell pages per LIF 254 * @intr_coal_mult: Interrupt coalescing multiplication factor. 255 * Scale user-supplied interrupt coalescing 256 * value in usecs to device units using: 257 * device units = usecs * mult / div 258 * @intr_coal_div: Interrupt coalescing division factor. 259 * Scale user-supplied interrupt coalescing 260 * value in usecs to device units using: 261 * device units = usecs * mult / div 262 * 263 */ 264 union ionic_dev_identity { 265 struct { 266 u8 version; 267 u8 type; 268 u8 rsvd[2]; 269 u8 nports; 270 u8 rsvd2[3]; 271 __le32 nlifs; 272 __le32 nintrs; 273 __le32 ndbpgs_per_lif; 274 __le32 intr_coal_mult; 275 __le32 intr_coal_div; 276 }; 277 __le32 words[512]; 278 }; 279 280 enum ionic_lif_type { 281 IONIC_LIF_TYPE_CLASSIC = 0, 282 IONIC_LIF_TYPE_MACVLAN = 1, 283 IONIC_LIF_TYPE_NETQUEUE = 2, 284 }; 285 286 /** 287 * struct ionic_lif_identify_cmd - lif identify command 288 * @opcode: opcode 289 * @type: lif type (enum lif_type) 290 * @ver: version of identify returned by device 291 */ 292 struct ionic_lif_identify_cmd { 293 u8 opcode; 294 u8 type; 295 u8 ver; 296 u8 rsvd[61]; 297 }; 298 299 /** 300 * struct ionic_lif_identify_comp - lif identify command completion 301 * @status: status of the command (enum status_code) 302 * @ver: version of identify returned by device 303 */ 304 struct ionic_lif_identify_comp { 305 u8 status; 306 u8 ver; 307 u8 rsvd2[14]; 308 }; 309 310 enum ionic_lif_capability { 311 IONIC_LIF_CAP_ETH = BIT(0), 312 IONIC_LIF_CAP_RDMA = BIT(1), 313 }; 314 315 /** 316 * Logical Queue Types 317 */ 318 enum ionic_logical_qtype { 319 IONIC_QTYPE_ADMINQ = 0, 320 IONIC_QTYPE_NOTIFYQ = 1, 321 IONIC_QTYPE_RXQ = 2, 322 IONIC_QTYPE_TXQ = 3, 323 IONIC_QTYPE_EQ = 4, 324 IONIC_QTYPE_MAX = 16, 325 }; 326 327 /** 328 * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue 329 * type. 330 * @qtype: Hardware Queue Type. 331 * @qid_count: Number of Queue IDs of the logical type. 332 * @qid_base: Minimum Queue ID of the logical type. 333 */ 334 struct ionic_lif_logical_qtype { 335 u8 qtype; 336 u8 rsvd[3]; 337 __le32 qid_count; 338 __le32 qid_base; 339 }; 340 341 enum ionic_lif_state { 342 IONIC_LIF_DISABLE = 0, 343 IONIC_LIF_ENABLE = 1, 344 IONIC_LIF_HANG_RESET = 2, 345 }; 346 347 /** 348 * LIF configuration 349 * @state: lif state (enum lif_state) 350 * @name: lif name 351 * @mtu: mtu 352 * @mac: station mac address 353 * @features: features (enum ionic_eth_hw_features) 354 * @queue_count: queue counts per queue-type 355 */ 356 union ionic_lif_config { 357 struct { 358 u8 state; 359 u8 rsvd[3]; 360 char name[IONIC_IFNAMSIZ]; 361 __le32 mtu; 362 u8 mac[6]; 363 u8 rsvd2[2]; 364 __le64 features; 365 __le32 queue_count[IONIC_QTYPE_MAX]; 366 }; 367 __le32 words[64]; 368 }; 369 370 /** 371 * struct ionic_lif_identity - lif identity information (type-specific) 372 * 373 * @capabilities LIF capabilities 374 * 375 * Ethernet: 376 * @version: Ethernet identify structure version. 377 * @features: Ethernet features supported on this lif type. 378 * @max_ucast_filters: Number of perfect unicast addresses supported. 379 * @max_mcast_filters: Number of perfect multicast addresses supported. 380 * @min_frame_size: Minimum size of frames to be sent 381 * @max_frame_size: Maximum size of frames to be sent 382 * @config: LIF config struct with features, mtu, mac, q counts 383 * 384 * RDMA: 385 * @version: RDMA version of opcodes and queue descriptors. 386 * @qp_opcodes: Number of rdma queue pair opcodes supported. 387 * @admin_opcodes: Number of rdma admin opcodes supported. 388 * @npts_per_lif: Page table size per lif 389 * @nmrs_per_lif: Number of memory regions per lif 390 * @nahs_per_lif: Number of address handles per lif 391 * @max_stride: Max work request stride. 392 * @cl_stride: Cache line stride. 393 * @pte_stride: Page table entry stride. 394 * @rrq_stride: Remote RQ work request stride. 395 * @rsq_stride: Remote SQ work request stride. 396 * @dcqcn_profiles: Number of DCQCN profiles 397 * @aq_qtype: RDMA Admin Qtype. 398 * @sq_qtype: RDMA Send Qtype. 399 * @rq_qtype: RDMA Receive Qtype. 400 * @cq_qtype: RDMA Completion Qtype. 401 * @eq_qtype: RDMA Event Qtype. 402 */ 403 union ionic_lif_identity { 404 struct { 405 __le64 capabilities; 406 407 struct { 408 u8 version; 409 u8 rsvd[3]; 410 __le32 max_ucast_filters; 411 __le32 max_mcast_filters; 412 __le16 rss_ind_tbl_sz; 413 __le32 min_frame_size; 414 __le32 max_frame_size; 415 u8 rsvd2[106]; 416 union ionic_lif_config config; 417 } eth; 418 419 struct { 420 u8 version; 421 u8 qp_opcodes; 422 u8 admin_opcodes; 423 u8 rsvd; 424 __le32 npts_per_lif; 425 __le32 nmrs_per_lif; 426 __le32 nahs_per_lif; 427 u8 max_stride; 428 u8 cl_stride; 429 u8 pte_stride; 430 u8 rrq_stride; 431 u8 rsq_stride; 432 u8 dcqcn_profiles; 433 u8 rsvd_dimensions[10]; 434 struct ionic_lif_logical_qtype aq_qtype; 435 struct ionic_lif_logical_qtype sq_qtype; 436 struct ionic_lif_logical_qtype rq_qtype; 437 struct ionic_lif_logical_qtype cq_qtype; 438 struct ionic_lif_logical_qtype eq_qtype; 439 } rdma; 440 }; 441 __le32 words[512]; 442 }; 443 444 /** 445 * struct ionic_lif_init_cmd - LIF init command 446 * @opcode: opcode 447 * @type: LIF type (enum lif_type) 448 * @index: LIF index 449 * @info_pa: destination address for lif info (struct ionic_lif_info) 450 */ 451 struct ionic_lif_init_cmd { 452 u8 opcode; 453 u8 type; 454 __le16 index; 455 __le32 rsvd; 456 __le64 info_pa; 457 u8 rsvd2[48]; 458 }; 459 460 /** 461 * struct ionic_lif_init_comp - LIF init command completion 462 * @status: The status of the command (enum status_code) 463 */ 464 struct ionic_lif_init_comp { 465 u8 status; 466 u8 rsvd; 467 __le16 hw_index; 468 u8 rsvd2[12]; 469 }; 470 471 /** 472 * struct ionic_q_init_cmd - Queue init command 473 * @opcode: opcode 474 * @type: Logical queue type 475 * @ver: Queue version (defines opcode/descriptor scope) 476 * @lif_index: LIF index 477 * @index: (lif, qtype) relative admin queue index 478 * @intr_index: Interrupt control register index 479 * @pid: Process ID 480 * @flags: 481 * IRQ: Interrupt requested on completion 482 * ENA: Enable the queue. If ENA=0 the queue is initialized 483 * but remains disabled, to be later enabled with the 484 * Queue Enable command. If ENA=1, then queue is 485 * initialized and then enabled. 486 * SG: Enable Scatter-Gather on the queue. 487 * in number of descs. The actual ring size is 488 * (1 << ring_size). For example, to 489 * select a ring size of 64 descriptors write 490 * ring_size = 6. The minimum ring_size value is 2 491 * for a ring size of 4 descriptors. The maximum 492 * ring_size value is 16 for a ring size of 64k 493 * descriptors. Values of ring_size <2 and >16 are 494 * reserved. 495 * EQ: Enable the Event Queue 496 * @cos: Class of service for this queue. 497 * @ring_size: Queue ring size, encoded as a log2(size) 498 * @ring_base: Queue ring base address 499 * @cq_ring_base: Completion queue ring base address 500 * @sg_ring_base: Scatter/Gather ring base address 501 * @eq_index: Event queue index 502 */ 503 struct ionic_q_init_cmd { 504 u8 opcode; 505 u8 rsvd; 506 __le16 lif_index; 507 u8 type; 508 u8 ver; 509 u8 rsvd1[2]; 510 __le32 index; 511 __le16 pid; 512 __le16 intr_index; 513 __le16 flags; 514 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 515 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 516 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 517 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 518 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 519 u8 cos; 520 u8 ring_size; 521 __le64 ring_base; 522 __le64 cq_ring_base; 523 __le64 sg_ring_base; 524 __le32 eq_index; 525 u8 rsvd2[16]; 526 }; 527 528 /** 529 * struct ionic_q_init_comp - Queue init command completion 530 * @status: The status of the command (enum status_code) 531 * @ver: Queue version (defines opcode/descriptor scope) 532 * @comp_index: The index in the descriptor ring for which this 533 * is the completion. 534 * @hw_index: Hardware Queue ID 535 * @hw_type: Hardware Queue type 536 * @color: Color 537 */ 538 struct ionic_q_init_comp { 539 u8 status; 540 u8 ver; 541 __le16 comp_index; 542 __le32 hw_index; 543 u8 hw_type; 544 u8 rsvd2[6]; 545 u8 color; 546 }; 547 548 /* the device's internal addressing uses up to 52 bits */ 549 #define IONIC_ADDR_LEN 52 550 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 551 552 enum ionic_txq_desc_opcode { 553 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 554 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 555 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 556 IONIC_TXQ_DESC_OPCODE_TSO = 3, 557 }; 558 559 /** 560 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 561 * @opcode: Tx operation, see TXQ_DESC_OPCODE_*: 562 * 563 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 564 * 565 * Non-offload send. No segmentation, 566 * fragmentation or checksum calc/insertion is 567 * performed by device; packet is prepared 568 * to send by software stack and requires 569 * no further manipulation from device. 570 * 571 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 572 * 573 * Offload 16-bit L4 checksum 574 * calculation/insertion. The device will 575 * calculate the L4 checksum value and 576 * insert the result in the packet's L4 577 * header checksum field. The L4 checksum 578 * is calculated starting at @csum_start bytes 579 * into the packet to the end of the packet. 580 * The checksum insertion position is given 581 * in @csum_offset. This feature is only 582 * applicable to protocols such as TCP, UDP 583 * and ICMP where a standard (i.e. the 584 * 'IP-style' checksum) one's complement 585 * 16-bit checksum is used, using an IP 586 * pseudo-header to seed the calculation. 587 * Software will preload the L4 checksum 588 * field with the IP pseudo-header checksum. 589 * 590 * For tunnel encapsulation, @csum_start and 591 * @csum_offset refer to the inner L4 592 * header. Supported tunnels encapsulations 593 * are: IPIP, GRE, and UDP. If the @encap 594 * is clear, no further processing by the 595 * device is required; software will 596 * calculate the outer header checksums. If 597 * the @encap is set, the device will 598 * offload the outer header checksums using 599 * LCO (local checksum offload) (see 600 * Documentation/networking/checksum- 601 * offloads.txt for more info). 602 * 603 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 604 * 605 * Offload 16-bit checksum computation to hardware. 606 * If @csum_l3 is set then the packet's L3 checksum is 607 * updated. Similarly, if @csum_l4 is set the the L4 608 * checksum is updated. If @encap is set then encap header 609 * checksums are also updated. 610 * 611 * IONIC_TXQ_DESC_OPCODE_TSO: 612 * 613 * Device performs TCP segmentation offload 614 * (TSO). @hdr_len is the number of bytes 615 * to the end of TCP header (the offset to 616 * the TCP payload). @mss is the desired 617 * MSS, the TCP payload length for each 618 * segment. The device will calculate/ 619 * insert IP (IPv4 only) and TCP checksums 620 * for each segment. In the first data 621 * buffer containing the header template, 622 * the driver will set IPv4 checksum to 0 623 * and preload TCP checksum with the IP 624 * pseudo header calculated with IP length = 0. 625 * 626 * Supported tunnel encapsulations are IPIP, 627 * layer-3 GRE, and UDP. @hdr_len includes 628 * both outer and inner headers. The driver 629 * will set IPv4 checksum to zero and 630 * preload TCP checksum with IP pseudo 631 * header on the inner header. 632 * 633 * TCP ECN offload is supported. The device 634 * will set CWR flag in the first segment if 635 * CWR is set in the template header, and 636 * clear CWR in remaining segments. 637 * @flags: 638 * vlan: 639 * Insert an L2 VLAN header using @vlan_tci. 640 * encap: 641 * Calculate encap header checksum. 642 * csum_l3: 643 * Compute L3 header checksum. 644 * csum_l4: 645 * Compute L4 header checksum. 646 * tso_sot: 647 * TSO start 648 * tso_eot: 649 * TSO end 650 * @num_sg_elems: Number of scatter-gather elements in SG 651 * descriptor 652 * @addr: First data buffer's DMA address. 653 * (Subsequent data buffers are on txq_sg_desc). 654 * @len: First data buffer's length, in bytes 655 * @vlan_tci: VLAN tag to insert in the packet (if requested 656 * by @V-bit). Includes .1p and .1q tags 657 * @hdr_len: Length of packet headers, including 658 * encapsulating outer header, if applicable. 659 * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and 660 * TXQ_DESC_OPCODE_TSO. Should be set to zero for 661 * all other modes. For 662 * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 663 * of headers up to inner-most L4 header. For 664 * TXQ_DESC_OPCODE_TSO, @hdr_len is up to 665 * inner-most L4 payload, so inclusive of 666 * inner-most L4 header. 667 * @mss: Desired MSS value for TSO. Only applicable for 668 * TXQ_DESC_OPCODE_TSO. 669 * @csum_start: Offset into inner-most L3 header of checksum 670 * @csum_offset: Offset into inner-most L4 header of checksum 671 */ 672 673 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 674 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 675 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 676 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 677 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 678 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 679 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 680 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 681 682 /* common flags */ 683 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 684 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 685 686 /* flags for csum_hw opcode */ 687 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 688 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 689 690 /* flags for tso opcode */ 691 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 692 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 693 694 struct ionic_txq_desc { 695 __le64 cmd; 696 __le16 len; 697 union { 698 __le16 vlan_tci; 699 __le16 hword0; 700 }; 701 union { 702 __le16 csum_start; 703 __le16 hdr_len; 704 __le16 hword1; 705 }; 706 union { 707 __le16 csum_offset; 708 __le16 mss; 709 __le16 hword2; 710 }; 711 }; 712 713 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 714 u8 nsge, u64 addr) 715 { 716 u64 cmd; 717 718 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << 719 IONIC_TXQ_DESC_OPCODE_SHIFT; 720 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << 721 IONIC_TXQ_DESC_FLAGS_SHIFT; 722 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 723 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 724 725 return cmd; 726 }; 727 728 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 729 u8 *nsge, u64 *addr) 730 { 731 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & 732 IONIC_TXQ_DESC_OPCODE_MASK; 733 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & 734 IONIC_TXQ_DESC_FLAGS_MASK; 735 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 736 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 737 }; 738 739 #define IONIC_TX_MAX_SG_ELEMS 8 740 #define IONIC_RX_MAX_SG_ELEMS 8 741 742 /** 743 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 744 * @addr: DMA address of SG element data buffer 745 * @len: Length of SG element data buffer, in bytes 746 */ 747 struct ionic_txq_sg_desc { 748 struct ionic_txq_sg_elem { 749 __le64 addr; 750 __le16 len; 751 __le16 rsvd[3]; 752 } elems[IONIC_TX_MAX_SG_ELEMS]; 753 }; 754 755 /** 756 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 757 * @status: The status of the command (enum status_code) 758 * @comp_index: The index in the descriptor ring for which this 759 * is the completion. 760 * @color: Color bit. 761 */ 762 struct ionic_txq_comp { 763 u8 status; 764 u8 rsvd; 765 __le16 comp_index; 766 u8 rsvd2[11]; 767 u8 color; 768 }; 769 770 enum ionic_rxq_desc_opcode { 771 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 772 IONIC_RXQ_DESC_OPCODE_SG = 1, 773 }; 774 775 /** 776 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 777 * @opcode: Rx operation, see RXQ_DESC_OPCODE_*: 778 * 779 * RXQ_DESC_OPCODE_SIMPLE: 780 * 781 * Receive full packet into data buffer 782 * starting at @addr. Results of 783 * receive, including actual bytes received, 784 * are recorded in Rx completion descriptor. 785 * 786 * @len: Data buffer's length, in bytes. 787 * @addr: Data buffer's DMA address 788 */ 789 struct ionic_rxq_desc { 790 u8 opcode; 791 u8 rsvd[5]; 792 __le16 len; 793 __le64 addr; 794 }; 795 796 /** 797 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 798 * @addr: DMA address of SG element data buffer 799 * @len: Length of SG element data buffer, in bytes 800 */ 801 struct ionic_rxq_sg_desc { 802 struct ionic_rxq_sg_elem { 803 __le64 addr; 804 __le16 len; 805 __le16 rsvd[3]; 806 } elems[IONIC_RX_MAX_SG_ELEMS]; 807 }; 808 809 /** 810 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 811 * @status: The status of the command (enum status_code) 812 * @num_sg_elems: Number of SG elements used by this descriptor 813 * @comp_index: The index in the descriptor ring for which this 814 * is the completion. 815 * @rss_hash: 32-bit RSS hash 816 * @csum: 16-bit sum of the packet's L2 payload. 817 * If the packet's L2 payload is odd length, an extra 818 * zero-value byte is included in the @csum calculation but 819 * not included in @len. 820 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 821 * set. Includes .1p and .1q tags. 822 * @len: Received packet length, in bytes. Excludes FCS. 823 * @csum_calc L2 payload checksum is computed or not 824 * @csum_tcp_ok: The TCP checksum calculated by the device 825 * matched the checksum in the receive packet's 826 * TCP header 827 * @csum_tcp_bad: The TCP checksum calculated by the device did 828 * not match the checksum in the receive packet's 829 * TCP header. 830 * @csum_udp_ok: The UDP checksum calculated by the device 831 * matched the checksum in the receive packet's 832 * UDP header 833 * @csum_udp_bad: The UDP checksum calculated by the device did 834 * not match the checksum in the receive packet's 835 * UDP header. 836 * @csum_ip_ok: The IPv4 checksum calculated by the device 837 * matched the checksum in the receive packet's 838 * first IPv4 header. If the receive packet 839 * contains both a tunnel IPv4 header and a 840 * transport IPv4 header, the device validates the 841 * checksum for the both IPv4 headers. 842 * @csum_ip_bad: The IPv4 checksum calculated by the device did 843 * not match the checksum in the receive packet's 844 * first IPv4 header. If the receive packet 845 * contains both a tunnel IPv4 header and a 846 * transport IPv4 header, the device validates the 847 * checksum for both IP headers. 848 * @VLAN: VLAN header was stripped and placed in @vlan_tci. 849 * @pkt_type: Packet type 850 * @color: Color bit. 851 */ 852 struct ionic_rxq_comp { 853 u8 status; 854 u8 num_sg_elems; 855 __le16 comp_index; 856 __le32 rss_hash; 857 __le16 csum; 858 __le16 vlan_tci; 859 __le16 len; 860 u8 csum_flags; 861 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 862 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 863 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 864 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 865 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 866 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 867 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 868 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 869 u8 pkt_type_color; 870 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 871 }; 872 873 enum ionic_pkt_type { 874 IONIC_PKT_TYPE_NON_IP = 0x000, 875 IONIC_PKT_TYPE_IPV4 = 0x001, 876 IONIC_PKT_TYPE_IPV4_TCP = 0x003, 877 IONIC_PKT_TYPE_IPV4_UDP = 0x005, 878 IONIC_PKT_TYPE_IPV6 = 0x008, 879 IONIC_PKT_TYPE_IPV6_TCP = 0x018, 880 IONIC_PKT_TYPE_IPV6_UDP = 0x028, 881 }; 882 883 enum ionic_eth_hw_features { 884 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 885 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 886 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 887 IONIC_ETH_HW_RX_HASH = BIT(3), 888 IONIC_ETH_HW_RX_CSUM = BIT(4), 889 IONIC_ETH_HW_TX_SG = BIT(5), 890 IONIC_ETH_HW_RX_SG = BIT(6), 891 IONIC_ETH_HW_TX_CSUM = BIT(7), 892 IONIC_ETH_HW_TSO = BIT(8), 893 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 894 IONIC_ETH_HW_TSO_ECN = BIT(10), 895 IONIC_ETH_HW_TSO_GRE = BIT(11), 896 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 897 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 898 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 899 IONIC_ETH_HW_TSO_UDP = BIT(15), 900 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 901 }; 902 903 /** 904 * struct ionic_q_control_cmd - Queue control command 905 * @opcode: opcode 906 * @type: Queue type 907 * @lif_index: LIF index 908 * @index: Queue index 909 * @oper: Operation (enum q_control_oper) 910 */ 911 struct ionic_q_control_cmd { 912 u8 opcode; 913 u8 type; 914 __le16 lif_index; 915 __le32 index; 916 u8 oper; 917 u8 rsvd[55]; 918 }; 919 920 typedef struct ionic_admin_comp ionic_q_control_comp; 921 922 enum q_control_oper { 923 IONIC_Q_DISABLE = 0, 924 IONIC_Q_ENABLE = 1, 925 IONIC_Q_HANG_RESET = 2, 926 }; 927 928 /** 929 * Physical connection type 930 */ 931 enum ionic_phy_type { 932 IONIC_PHY_TYPE_NONE = 0, 933 IONIC_PHY_TYPE_COPPER = 1, 934 IONIC_PHY_TYPE_FIBER = 2, 935 }; 936 937 /** 938 * Transceiver status 939 */ 940 enum ionic_xcvr_state { 941 IONIC_XCVR_STATE_REMOVED = 0, 942 IONIC_XCVR_STATE_INSERTED = 1, 943 IONIC_XCVR_STATE_PENDING = 2, 944 IONIC_XCVR_STATE_SPROM_READ = 3, 945 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 946 }; 947 948 /** 949 * Supported link modes 950 */ 951 enum ionic_xcvr_pid { 952 IONIC_XCVR_PID_UNKNOWN = 0, 953 954 /* CU */ 955 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 956 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 957 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 958 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 959 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 960 961 /* Fiber */ 962 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 963 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 964 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 965 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 966 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 967 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 968 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 969 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 970 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 971 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 972 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 973 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 974 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 975 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 976 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 977 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 978 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 979 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 980 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 981 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 982 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 983 }; 984 985 /** 986 * Port types 987 */ 988 enum ionic_port_type { 989 IONIC_PORT_TYPE_NONE = 0, /* port type not configured */ 990 IONIC_PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */ 991 IONIC_PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */ 992 }; 993 994 /** 995 * Port config state 996 */ 997 enum ionic_port_admin_state { 998 IONIC_PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */ 999 IONIC_PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */ 1000 IONIC_PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */ 1001 }; 1002 1003 /** 1004 * Port operational status 1005 */ 1006 enum ionic_port_oper_status { 1007 IONIC_PORT_OPER_STATUS_NONE = 0, /* port is disabled */ 1008 IONIC_PORT_OPER_STATUS_UP = 1, /* port is linked up */ 1009 IONIC_PORT_OPER_STATUS_DOWN = 2, /* port link status is down */ 1010 }; 1011 1012 /** 1013 * Ethernet Forward error correction (fec) modes 1014 */ 1015 enum ionic_port_fec_type { 1016 IONIC_PORT_FEC_TYPE_NONE = 0, /* Disabled */ 1017 IONIC_PORT_FEC_TYPE_FC = 1, /* FireCode */ 1018 IONIC_PORT_FEC_TYPE_RS = 2, /* ReedSolomon */ 1019 }; 1020 1021 /** 1022 * Ethernet pause (flow control) modes 1023 */ 1024 enum ionic_port_pause_type { 1025 IONIC_PORT_PAUSE_TYPE_NONE = 0, /* Disable Pause */ 1026 IONIC_PORT_PAUSE_TYPE_LINK = 1, /* Link level pause */ 1027 IONIC_PORT_PAUSE_TYPE_PFC = 2, /* Priority-Flow control */ 1028 }; 1029 1030 /** 1031 * Loopback modes 1032 */ 1033 enum ionic_port_loopback_mode { 1034 IONIC_PORT_LOOPBACK_MODE_NONE = 0, /* Disable loopback */ 1035 IONIC_PORT_LOOPBACK_MODE_MAC = 1, /* MAC loopback */ 1036 IONIC_PORT_LOOPBACK_MODE_PHY = 2, /* PHY/Serdes loopback */ 1037 }; 1038 1039 /** 1040 * Transceiver Status information 1041 * @state: Transceiver status (enum ionic_xcvr_state) 1042 * @phy: Physical connection type (enum ionic_phy_type) 1043 * @pid: Transceiver link mode (enum pid) 1044 * @sprom: Transceiver sprom contents 1045 */ 1046 struct ionic_xcvr_status { 1047 u8 state; 1048 u8 phy; 1049 __le16 pid; 1050 u8 sprom[256]; 1051 }; 1052 1053 /** 1054 * Port configuration 1055 * @speed: port speed (in Mbps) 1056 * @mtu: mtu 1057 * @state: port admin state (enum port_admin_state) 1058 * @an_enable: autoneg enable 1059 * @fec_type: fec type (enum ionic_port_fec_type) 1060 * @pause_type: pause type (enum ionic_port_pause_type) 1061 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1062 */ 1063 union ionic_port_config { 1064 struct { 1065 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1066 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1067 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1068 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1069 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1070 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1071 __le32 speed; 1072 __le32 mtu; 1073 u8 state; 1074 u8 an_enable; 1075 u8 fec_type; 1076 #define IONIC_PAUSE_TYPE_MASK 0x0f 1077 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1078 #define IONIC_PAUSE_F_TX 0x10 1079 #define IONIC_PAUSE_F_RX 0x20 1080 u8 pause_type; 1081 u8 loopback_mode; 1082 }; 1083 __le32 words[64]; 1084 }; 1085 1086 /** 1087 * Port Status information 1088 * @status: link status (enum ionic_port_oper_status) 1089 * @id: port id 1090 * @speed: link speed (in Mbps) 1091 * @xcvr: transceiver status 1092 */ 1093 struct ionic_port_status { 1094 __le32 id; 1095 __le32 speed; 1096 u8 status; 1097 u8 rsvd[51]; 1098 struct ionic_xcvr_status xcvr; 1099 }; 1100 1101 /** 1102 * struct ionic_port_identify_cmd - Port identify command 1103 * @opcode: opcode 1104 * @index: port index 1105 * @ver: Highest version of identify supported by driver 1106 */ 1107 struct ionic_port_identify_cmd { 1108 u8 opcode; 1109 u8 index; 1110 u8 ver; 1111 u8 rsvd[61]; 1112 }; 1113 1114 /** 1115 * struct ionic_port_identify_comp - Port identify command completion 1116 * @status: The status of the command (enum status_code) 1117 * @ver: Version of identify returned by device 1118 */ 1119 struct ionic_port_identify_comp { 1120 u8 status; 1121 u8 ver; 1122 u8 rsvd[14]; 1123 }; 1124 1125 /** 1126 * struct ionic_port_init_cmd - Port initialization command 1127 * @opcode: opcode 1128 * @index: port index 1129 * @info_pa: destination address for port info (struct ionic_port_info) 1130 */ 1131 struct ionic_port_init_cmd { 1132 u8 opcode; 1133 u8 index; 1134 u8 rsvd[6]; 1135 __le64 info_pa; 1136 u8 rsvd2[48]; 1137 }; 1138 1139 /** 1140 * struct ionic_port_init_comp - Port initialization command completion 1141 * @status: The status of the command (enum status_code) 1142 */ 1143 struct ionic_port_init_comp { 1144 u8 status; 1145 u8 rsvd[15]; 1146 }; 1147 1148 /** 1149 * struct ionic_port_reset_cmd - Port reset command 1150 * @opcode: opcode 1151 * @index: port index 1152 */ 1153 struct ionic_port_reset_cmd { 1154 u8 opcode; 1155 u8 index; 1156 u8 rsvd[62]; 1157 }; 1158 1159 /** 1160 * struct ionic_port_reset_comp - Port reset command completion 1161 * @status: The status of the command (enum status_code) 1162 */ 1163 struct ionic_port_reset_comp { 1164 u8 status; 1165 u8 rsvd[15]; 1166 }; 1167 1168 /** 1169 * enum stats_ctl_cmd - List of commands for stats control 1170 */ 1171 enum ionic_stats_ctl_cmd { 1172 IONIC_STATS_CTL_RESET = 0, 1173 }; 1174 1175 1176 /** 1177 * enum ionic_port_attr - List of device attributes 1178 */ 1179 enum ionic_port_attr { 1180 IONIC_PORT_ATTR_STATE = 0, 1181 IONIC_PORT_ATTR_SPEED = 1, 1182 IONIC_PORT_ATTR_MTU = 2, 1183 IONIC_PORT_ATTR_AUTONEG = 3, 1184 IONIC_PORT_ATTR_FEC = 4, 1185 IONIC_PORT_ATTR_PAUSE = 5, 1186 IONIC_PORT_ATTR_LOOPBACK = 6, 1187 IONIC_PORT_ATTR_STATS_CTRL = 7, 1188 }; 1189 1190 /** 1191 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1192 * @opcode: Opcode 1193 * @index: port index 1194 * @attr: Attribute type (enum ionic_port_attr) 1195 */ 1196 struct ionic_port_setattr_cmd { 1197 u8 opcode; 1198 u8 index; 1199 u8 attr; 1200 u8 rsvd; 1201 union { 1202 u8 state; 1203 __le32 speed; 1204 __le32 mtu; 1205 u8 an_enable; 1206 u8 fec_type; 1207 u8 pause_type; 1208 u8 loopback_mode; 1209 u8 stats_ctl; 1210 u8 rsvd2[60]; 1211 }; 1212 }; 1213 1214 /** 1215 * struct ionic_port_setattr_comp - Port set attr command completion 1216 * @status: The status of the command (enum status_code) 1217 * @color: Color bit 1218 */ 1219 struct ionic_port_setattr_comp { 1220 u8 status; 1221 u8 rsvd[14]; 1222 u8 color; 1223 }; 1224 1225 /** 1226 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1227 * @opcode: Opcode 1228 * @index: port index 1229 * @attr: Attribute type (enum ionic_port_attr) 1230 */ 1231 struct ionic_port_getattr_cmd { 1232 u8 opcode; 1233 u8 index; 1234 u8 attr; 1235 u8 rsvd[61]; 1236 }; 1237 1238 /** 1239 * struct ionic_port_getattr_comp - Port get attr command completion 1240 * @status: The status of the command (enum status_code) 1241 * @color: Color bit 1242 */ 1243 struct ionic_port_getattr_comp { 1244 u8 status; 1245 u8 rsvd[3]; 1246 union { 1247 u8 state; 1248 __le32 speed; 1249 __le32 mtu; 1250 u8 an_enable; 1251 u8 fec_type; 1252 u8 pause_type; 1253 u8 loopback_mode; 1254 u8 rsvd2[11]; 1255 }; 1256 u8 color; 1257 }; 1258 1259 /** 1260 * struct ionic_lif_status - Lif status register 1261 * @eid: most recent NotifyQ event id 1262 * @port_num: port the lif is connected to 1263 * @link_status: port status (enum ionic_port_oper_status) 1264 * @link_speed: speed of link in Mbps 1265 * @link_down_count: number of times link status changes 1266 */ 1267 struct ionic_lif_status { 1268 __le64 eid; 1269 u8 port_num; 1270 u8 rsvd; 1271 __le16 link_status; 1272 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1273 __le16 link_down_count; 1274 u8 rsvd2[46]; 1275 }; 1276 1277 /** 1278 * struct ionic_lif_reset_cmd - LIF reset command 1279 * @opcode: opcode 1280 * @index: LIF index 1281 */ 1282 struct ionic_lif_reset_cmd { 1283 u8 opcode; 1284 u8 rsvd; 1285 __le16 index; 1286 __le32 rsvd2[15]; 1287 }; 1288 1289 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1290 1291 enum ionic_dev_state { 1292 IONIC_DEV_DISABLE = 0, 1293 IONIC_DEV_ENABLE = 1, 1294 IONIC_DEV_HANG_RESET = 2, 1295 }; 1296 1297 /** 1298 * enum ionic_dev_attr - List of device attributes 1299 */ 1300 enum ionic_dev_attr { 1301 IONIC_DEV_ATTR_STATE = 0, 1302 IONIC_DEV_ATTR_NAME = 1, 1303 IONIC_DEV_ATTR_FEATURES = 2, 1304 }; 1305 1306 /** 1307 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1308 * @opcode: Opcode 1309 * @attr: Attribute type (enum ionic_dev_attr) 1310 * @state: Device state (enum ionic_dev_state) 1311 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1312 * @features: Device features 1313 */ 1314 struct ionic_dev_setattr_cmd { 1315 u8 opcode; 1316 u8 attr; 1317 __le16 rsvd; 1318 union { 1319 u8 state; 1320 char name[IONIC_IFNAMSIZ]; 1321 __le64 features; 1322 u8 rsvd2[60]; 1323 }; 1324 }; 1325 1326 /** 1327 * struct ionic_dev_setattr_comp - Device set attr command completion 1328 * @status: The status of the command (enum status_code) 1329 * @features: Device features 1330 * @color: Color bit 1331 */ 1332 struct ionic_dev_setattr_comp { 1333 u8 status; 1334 u8 rsvd[3]; 1335 union { 1336 __le64 features; 1337 u8 rsvd2[11]; 1338 }; 1339 u8 color; 1340 }; 1341 1342 /** 1343 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1344 * @opcode: opcode 1345 * @attr: Attribute type (enum ionic_dev_attr) 1346 */ 1347 struct ionic_dev_getattr_cmd { 1348 u8 opcode; 1349 u8 attr; 1350 u8 rsvd[62]; 1351 }; 1352 1353 /** 1354 * struct ionic_dev_setattr_comp - Device set attr command completion 1355 * @status: The status of the command (enum status_code) 1356 * @features: Device features 1357 * @color: Color bit 1358 */ 1359 struct ionic_dev_getattr_comp { 1360 u8 status; 1361 u8 rsvd[3]; 1362 union { 1363 __le64 features; 1364 u8 rsvd2[11]; 1365 }; 1366 u8 color; 1367 }; 1368 1369 /** 1370 * RSS parameters 1371 */ 1372 #define IONIC_RSS_HASH_KEY_SIZE 40 1373 1374 enum ionic_rss_hash_types { 1375 IONIC_RSS_TYPE_IPV4 = BIT(0), 1376 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1377 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1378 IONIC_RSS_TYPE_IPV6 = BIT(3), 1379 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1380 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1381 }; 1382 1383 /** 1384 * enum ionic_lif_attr - List of LIF attributes 1385 */ 1386 enum ionic_lif_attr { 1387 IONIC_LIF_ATTR_STATE = 0, 1388 IONIC_LIF_ATTR_NAME = 1, 1389 IONIC_LIF_ATTR_MTU = 2, 1390 IONIC_LIF_ATTR_MAC = 3, 1391 IONIC_LIF_ATTR_FEATURES = 4, 1392 IONIC_LIF_ATTR_RSS = 5, 1393 IONIC_LIF_ATTR_STATS_CTRL = 6, 1394 }; 1395 1396 /** 1397 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1398 * @opcode: Opcode 1399 * @type: Attribute type (enum ionic_lif_attr) 1400 * @index: LIF index 1401 * @state: lif state (enum lif_state) 1402 * @name: The netdev name string, 0 terminated 1403 * @mtu: Mtu 1404 * @mac: Station mac 1405 * @features: Features (enum ionic_eth_hw_features) 1406 * @rss: RSS properties 1407 * @types: The hash types to enable (see rss_hash_types). 1408 * @key: The hash secret key. 1409 * @addr: Address for the indirection table shared memory. 1410 * @stats_ctl: stats control commands (enum stats_ctl_cmd) 1411 */ 1412 struct ionic_lif_setattr_cmd { 1413 u8 opcode; 1414 u8 attr; 1415 __le16 index; 1416 union { 1417 u8 state; 1418 char name[IONIC_IFNAMSIZ]; 1419 __le32 mtu; 1420 u8 mac[6]; 1421 __le64 features; 1422 struct { 1423 __le16 types; 1424 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1425 u8 rsvd[6]; 1426 __le64 addr; 1427 } rss; 1428 u8 stats_ctl; 1429 u8 rsvd[60]; 1430 }; 1431 }; 1432 1433 /** 1434 * struct ionic_lif_setattr_comp - LIF set attr command completion 1435 * @status: The status of the command (enum status_code) 1436 * @comp_index: The index in the descriptor ring for which this 1437 * is the completion. 1438 * @features: features (enum ionic_eth_hw_features) 1439 * @color: Color bit 1440 */ 1441 struct ionic_lif_setattr_comp { 1442 u8 status; 1443 u8 rsvd; 1444 __le16 comp_index; 1445 union { 1446 __le64 features; 1447 u8 rsvd2[11]; 1448 }; 1449 u8 color; 1450 }; 1451 1452 /** 1453 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1454 * @opcode: Opcode 1455 * @attr: Attribute type (enum ionic_lif_attr) 1456 * @index: LIF index 1457 */ 1458 struct ionic_lif_getattr_cmd { 1459 u8 opcode; 1460 u8 attr; 1461 __le16 index; 1462 u8 rsvd[60]; 1463 }; 1464 1465 /** 1466 * struct ionic_lif_getattr_comp - LIF get attr command completion 1467 * @status: The status of the command (enum status_code) 1468 * @comp_index: The index in the descriptor ring for which this 1469 * is the completion. 1470 * @state: lif state (enum lif_state) 1471 * @name: The netdev name string, 0 terminated 1472 * @mtu: Mtu 1473 * @mac: Station mac 1474 * @features: Features (enum ionic_eth_hw_features) 1475 * @color: Color bit 1476 */ 1477 struct ionic_lif_getattr_comp { 1478 u8 status; 1479 u8 rsvd; 1480 __le16 comp_index; 1481 union { 1482 u8 state; 1483 __le32 mtu; 1484 u8 mac[6]; 1485 __le64 features; 1486 u8 rsvd2[11]; 1487 }; 1488 u8 color; 1489 }; 1490 1491 enum ionic_rx_mode { 1492 IONIC_RX_MODE_F_UNICAST = BIT(0), 1493 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1494 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1495 IONIC_RX_MODE_F_PROMISC = BIT(3), 1496 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1497 }; 1498 1499 /** 1500 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1501 * @opcode: opcode 1502 * @lif_index: LIF index 1503 * @rx_mode: Rx mode flags: 1504 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets. 1505 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets. 1506 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets. 1507 * IONIC_RX_MODE_F_PROMISC: Accept any packets. 1508 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets. 1509 */ 1510 struct ionic_rx_mode_set_cmd { 1511 u8 opcode; 1512 u8 rsvd; 1513 __le16 lif_index; 1514 __le16 rx_mode; 1515 __le16 rsvd2[29]; 1516 }; 1517 1518 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1519 1520 enum ionic_rx_filter_match_type { 1521 IONIC_RX_FILTER_MATCH_VLAN = 0, 1522 IONIC_RX_FILTER_MATCH_MAC, 1523 IONIC_RX_FILTER_MATCH_MAC_VLAN, 1524 }; 1525 1526 /** 1527 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 1528 * @opcode: opcode 1529 * @qtype: Queue type 1530 * @lif_index: LIF index 1531 * @qid: Queue ID 1532 * @match: Rx filter match type. (See IONIC_RX_FILTER_MATCH_xxx) 1533 * @vlan: VLAN ID 1534 * @addr: MAC address (network-byte order) 1535 */ 1536 struct ionic_rx_filter_add_cmd { 1537 u8 opcode; 1538 u8 qtype; 1539 __le16 lif_index; 1540 __le32 qid; 1541 __le16 match; 1542 union { 1543 struct { 1544 __le16 vlan; 1545 } vlan; 1546 struct { 1547 u8 addr[6]; 1548 } mac; 1549 struct { 1550 __le16 vlan; 1551 u8 addr[6]; 1552 } mac_vlan; 1553 u8 rsvd[54]; 1554 }; 1555 }; 1556 1557 /** 1558 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 1559 * @status: The status of the command (enum status_code) 1560 * @comp_index: The index in the descriptor ring for which this 1561 * is the completion. 1562 * @filter_id: Filter ID 1563 * @color: Color bit. 1564 */ 1565 struct ionic_rx_filter_add_comp { 1566 u8 status; 1567 u8 rsvd; 1568 __le16 comp_index; 1569 __le32 filter_id; 1570 u8 rsvd2[7]; 1571 u8 color; 1572 }; 1573 1574 /** 1575 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 1576 * @opcode: opcode 1577 * @lif_index: LIF index 1578 * @filter_id: Filter ID 1579 */ 1580 struct ionic_rx_filter_del_cmd { 1581 u8 opcode; 1582 u8 rsvd; 1583 __le16 lif_index; 1584 __le32 filter_id; 1585 u8 rsvd2[56]; 1586 }; 1587 1588 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 1589 1590 /** 1591 * struct ionic_qos_identify_cmd - QoS identify command 1592 * @opcode: opcode 1593 * @ver: Highest version of identify supported by driver 1594 * 1595 */ 1596 struct ionic_qos_identify_cmd { 1597 u8 opcode; 1598 u8 ver; 1599 u8 rsvd[62]; 1600 }; 1601 1602 /** 1603 * struct ionic_qos_identify_comp - QoS identify command completion 1604 * @status: The status of the command (enum status_code) 1605 * @ver: Version of identify returned by device 1606 */ 1607 struct ionic_qos_identify_comp { 1608 u8 status; 1609 u8 ver; 1610 u8 rsvd[14]; 1611 }; 1612 1613 #define IONIC_QOS_CLASS_MAX 7 1614 #define IONIC_QOS_CLASS_NAME_SZ 32 1615 #define IONIC_QOS_DSCP_MAX_VALUES 64 1616 1617 /** 1618 * enum ionic_qos_class 1619 */ 1620 enum ionic_qos_class { 1621 IONIC_QOS_CLASS_DEFAULT = 0, 1622 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 1623 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 1624 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 1625 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 1626 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 1627 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 1628 }; 1629 1630 /** 1631 * enum ionic_qos_class_type - Traffic classification criteria 1632 */ 1633 enum ionic_qos_class_type { 1634 IONIC_QOS_CLASS_TYPE_NONE = 0, 1635 IONIC_QOS_CLASS_TYPE_PCP = 1, /* Dot1Q pcp */ 1636 IONIC_QOS_CLASS_TYPE_DSCP = 2, /* IP dscp */ 1637 }; 1638 1639 /** 1640 * enum ionic_qos_sched_type - Qos class scheduling type 1641 */ 1642 enum ionic_qos_sched_type { 1643 /* Strict priority */ 1644 IONIC_QOS_SCHED_TYPE_STRICT = 0, 1645 /* Deficit weighted round-robin */ 1646 IONIC_QOS_SCHED_TYPE_DWRR = 1, 1647 }; 1648 1649 /** 1650 * union ionic_qos_config - Qos configuration structure 1651 * @flags: Configuration flags 1652 * IONIC_QOS_CONFIG_F_ENABLE enable 1653 * IONIC_QOS_CONFIG_F_DROP drop/nodrop 1654 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 1655 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 1656 * @sched_type: Qos class scheduling type (enum ionic_qos_sched_type) 1657 * @class_type: Qos class type (enum ionic_qos_class_type) 1658 * @pause_type: Qos pause type (enum qos_pause_type) 1659 * @name: Qos class name 1660 * @mtu: MTU of the class 1661 * @pfc_dot1q_pcp: Pcp value for pause frames (valid iff F_NODROP) 1662 * @dwrr_weight: Qos class scheduling weight 1663 * @strict_rlmt: Rate limit for strict priority scheduling 1664 * @rw_dot1q_pcp: Rewrite dot1q pcp to this value 1665 * (valid iff F_RW_DOT1Q_PCP) 1666 * @rw_ip_dscp: Rewrite ip dscp to this value 1667 * (valid iff F_RW_IP_DSCP) 1668 * @dot1q_pcp: Dot1q pcp value 1669 * @ndscp: Number of valid dscp values in the ip_dscp field 1670 * @ip_dscp: IP dscp values 1671 */ 1672 union ionic_qos_config { 1673 struct { 1674 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 1675 #define IONIC_QOS_CONFIG_F_DROP BIT(1) 1676 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 1677 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 1678 u8 flags; 1679 u8 sched_type; 1680 u8 class_type; 1681 u8 pause_type; 1682 char name[IONIC_QOS_CLASS_NAME_SZ]; 1683 __le32 mtu; 1684 /* flow control */ 1685 u8 pfc_cos; 1686 /* scheduler */ 1687 union { 1688 u8 dwrr_weight; 1689 __le64 strict_rlmt; 1690 }; 1691 /* marking */ 1692 union { 1693 u8 rw_dot1q_pcp; 1694 u8 rw_ip_dscp; 1695 }; 1696 /* classification */ 1697 union { 1698 u8 dot1q_pcp; 1699 struct { 1700 u8 ndscp; 1701 u8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES]; 1702 }; 1703 }; 1704 }; 1705 __le32 words[64]; 1706 }; 1707 1708 /** 1709 * union ionic_qos_identity - QoS identity structure 1710 * @version: Version of the identify structure 1711 * @type: QoS system type 1712 * @nclasses: Number of usable QoS classes 1713 * @config: Current configuration of classes 1714 */ 1715 union ionic_qos_identity { 1716 struct { 1717 u8 version; 1718 u8 type; 1719 u8 rsvd[62]; 1720 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 1721 }; 1722 __le32 words[512]; 1723 }; 1724 1725 /** 1726 * struct qos_init_cmd - QoS config init command 1727 * @opcode: Opcode 1728 * @group: Qos class id 1729 * @info_pa: destination address for qos info 1730 */ 1731 struct ionic_qos_init_cmd { 1732 u8 opcode; 1733 u8 group; 1734 u8 rsvd[6]; 1735 __le64 info_pa; 1736 u8 rsvd1[48]; 1737 }; 1738 1739 typedef struct ionic_admin_comp ionic_qos_init_comp; 1740 1741 /** 1742 * struct ionic_qos_reset_cmd - Qos config reset command 1743 * @opcode: Opcode 1744 */ 1745 struct ionic_qos_reset_cmd { 1746 u8 opcode; 1747 u8 group; 1748 u8 rsvd[62]; 1749 }; 1750 1751 typedef struct ionic_admin_comp ionic_qos_reset_comp; 1752 1753 /** 1754 * struct ionic_fw_download_cmd - Firmware download command 1755 * @opcode: opcode 1756 * @addr: dma address of the firmware buffer 1757 * @offset: offset of the firmware buffer within the full image 1758 * @length: number of valid bytes in the firmware buffer 1759 */ 1760 struct ionic_fw_download_cmd { 1761 u8 opcode; 1762 u8 rsvd[3]; 1763 __le32 offset; 1764 __le64 addr; 1765 __le32 length; 1766 }; 1767 1768 typedef struct ionic_admin_comp ionic_fw_download_comp; 1769 1770 enum ionic_fw_control_oper { 1771 IONIC_FW_RESET = 0, /* Reset firmware */ 1772 IONIC_FW_INSTALL = 1, /* Install firmware */ 1773 IONIC_FW_ACTIVATE = 2, /* Activate firmware */ 1774 }; 1775 1776 /** 1777 * struct ionic_fw_control_cmd - Firmware control command 1778 * @opcode: opcode 1779 * @oper: firmware control operation (enum ionic_fw_control_oper) 1780 * @slot: slot to activate 1781 */ 1782 struct ionic_fw_control_cmd { 1783 u8 opcode; 1784 u8 rsvd[3]; 1785 u8 oper; 1786 u8 slot; 1787 u8 rsvd1[58]; 1788 }; 1789 1790 /** 1791 * struct ionic_fw_control_comp - Firmware control copletion 1792 * @opcode: opcode 1793 * @slot: slot where the firmware was installed 1794 */ 1795 struct ionic_fw_control_comp { 1796 u8 status; 1797 u8 rsvd; 1798 __le16 comp_index; 1799 u8 slot; 1800 u8 rsvd1[10]; 1801 u8 color; 1802 }; 1803 1804 /****************************************************************** 1805 ******************* RDMA Commands ******************************** 1806 ******************************************************************/ 1807 1808 /** 1809 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 1810 * @opcode: opcode 1811 * @lif_index: lif index 1812 * 1813 * There is no rdma specific dev command completion struct. Completion uses 1814 * the common struct ionic_admin_comp. Only the status is indicated. 1815 * Nonzero status means the LIF does not support rdma. 1816 **/ 1817 struct ionic_rdma_reset_cmd { 1818 u8 opcode; 1819 u8 rsvd; 1820 __le16 lif_index; 1821 u8 rsvd2[60]; 1822 }; 1823 1824 /** 1825 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 1826 * @opcode: opcode, 52, 53 1827 * @lif_index lif index 1828 * @qid_ver: (qid | (rdma version << 24)) 1829 * @cid: intr, eq_id, or cq_id 1830 * @dbid: doorbell page id 1831 * @depth_log2: log base two of queue depth 1832 * @stride_log2: log base two of queue stride 1833 * @dma_addr: address of the queue memory 1834 * @xxx_table_index: temporary, but should not need pgtbl for contig. queues. 1835 * 1836 * The same command struct is used to create an rdma event queue, completion 1837 * queue, or rdma admin queue. The cid is an interrupt number for an event 1838 * queue, an event queue id for a completion queue, or a completion queue id 1839 * for an rdma admin queue. 1840 * 1841 * The queue created via a dev command must be contiguous in dma space. 1842 * 1843 * The dev commands are intended only to be used during driver initialization, 1844 * to create queues supporting the rdma admin queue. Other queues, and other 1845 * types of rdma resources like memory regions, will be created and registered 1846 * via the rdma admin queue, and will support a more complete interface 1847 * providing scatter gather lists for larger, scattered queue buffers and 1848 * memory registration. 1849 * 1850 * There is no rdma specific dev command completion struct. Completion uses 1851 * the common struct ionic_admin_comp. Only the status is indicated. 1852 **/ 1853 struct ionic_rdma_queue_cmd { 1854 u8 opcode; 1855 u8 rsvd; 1856 __le16 lif_index; 1857 __le32 qid_ver; 1858 __le32 cid; 1859 __le16 dbid; 1860 u8 depth_log2; 1861 u8 stride_log2; 1862 __le64 dma_addr; 1863 u8 rsvd2[36]; 1864 __le32 xxx_table_index; 1865 }; 1866 1867 /****************************************************************** 1868 ******************* Notify Events ******************************** 1869 ******************************************************************/ 1870 1871 /** 1872 * struct ionic_notifyq_event 1873 * @eid: event number 1874 * @ecode: event code 1875 * @data: unspecified data about the event 1876 * 1877 * This is the generic event report struct from which the other 1878 * actual events will be formed. 1879 */ 1880 struct ionic_notifyq_event { 1881 __le64 eid; 1882 __le16 ecode; 1883 u8 data[54]; 1884 }; 1885 1886 /** 1887 * struct ionic_link_change_event 1888 * @eid: event number 1889 * @ecode: event code = EVENT_OPCODE_LINK_CHANGE 1890 * @link_status: link up or down, with error bits (enum port_status) 1891 * @link_speed: speed of the network link 1892 * 1893 * Sent when the network link state changes between UP and DOWN 1894 */ 1895 struct ionic_link_change_event { 1896 __le64 eid; 1897 __le16 ecode; 1898 __le16 link_status; 1899 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 1900 u8 rsvd[48]; 1901 }; 1902 1903 /** 1904 * struct ionic_reset_event 1905 * @eid: event number 1906 * @ecode: event code = EVENT_OPCODE_RESET 1907 * @reset_code: reset type 1908 * @state: 0=pending, 1=complete, 2=error 1909 * 1910 * Sent when the NIC or some subsystem is going to be or 1911 * has been reset. 1912 */ 1913 struct ionic_reset_event { 1914 __le64 eid; 1915 __le16 ecode; 1916 u8 reset_code; 1917 u8 state; 1918 u8 rsvd[52]; 1919 }; 1920 1921 /** 1922 * struct ionic_heartbeat_event 1923 * @eid: event number 1924 * @ecode: event code = EVENT_OPCODE_HEARTBEAT 1925 * 1926 * Sent periodically by the NIC to indicate continued health 1927 */ 1928 struct ionic_heartbeat_event { 1929 __le64 eid; 1930 __le16 ecode; 1931 u8 rsvd[54]; 1932 }; 1933 1934 /** 1935 * struct ionic_log_event 1936 * @eid: event number 1937 * @ecode: event code = EVENT_OPCODE_LOG 1938 * @data: log data 1939 * 1940 * Sent to notify the driver of an internal error. 1941 */ 1942 struct ionic_log_event { 1943 __le64 eid; 1944 __le16 ecode; 1945 u8 data[54]; 1946 }; 1947 1948 /** 1949 * struct ionic_port_stats 1950 */ 1951 struct ionic_port_stats { 1952 __le64 frames_rx_ok; 1953 __le64 frames_rx_all; 1954 __le64 frames_rx_bad_fcs; 1955 __le64 frames_rx_bad_all; 1956 __le64 octets_rx_ok; 1957 __le64 octets_rx_all; 1958 __le64 frames_rx_unicast; 1959 __le64 frames_rx_multicast; 1960 __le64 frames_rx_broadcast; 1961 __le64 frames_rx_pause; 1962 __le64 frames_rx_bad_length; 1963 __le64 frames_rx_undersized; 1964 __le64 frames_rx_oversized; 1965 __le64 frames_rx_fragments; 1966 __le64 frames_rx_jabber; 1967 __le64 frames_rx_pripause; 1968 __le64 frames_rx_stomped_crc; 1969 __le64 frames_rx_too_long; 1970 __le64 frames_rx_vlan_good; 1971 __le64 frames_rx_dropped; 1972 __le64 frames_rx_less_than_64b; 1973 __le64 frames_rx_64b; 1974 __le64 frames_rx_65b_127b; 1975 __le64 frames_rx_128b_255b; 1976 __le64 frames_rx_256b_511b; 1977 __le64 frames_rx_512b_1023b; 1978 __le64 frames_rx_1024b_1518b; 1979 __le64 frames_rx_1519b_2047b; 1980 __le64 frames_rx_2048b_4095b; 1981 __le64 frames_rx_4096b_8191b; 1982 __le64 frames_rx_8192b_9215b; 1983 __le64 frames_rx_other; 1984 __le64 frames_tx_ok; 1985 __le64 frames_tx_all; 1986 __le64 frames_tx_bad; 1987 __le64 octets_tx_ok; 1988 __le64 octets_tx_total; 1989 __le64 frames_tx_unicast; 1990 __le64 frames_tx_multicast; 1991 __le64 frames_tx_broadcast; 1992 __le64 frames_tx_pause; 1993 __le64 frames_tx_pripause; 1994 __le64 frames_tx_vlan; 1995 __le64 frames_tx_less_than_64b; 1996 __le64 frames_tx_64b; 1997 __le64 frames_tx_65b_127b; 1998 __le64 frames_tx_128b_255b; 1999 __le64 frames_tx_256b_511b; 2000 __le64 frames_tx_512b_1023b; 2001 __le64 frames_tx_1024b_1518b; 2002 __le64 frames_tx_1519b_2047b; 2003 __le64 frames_tx_2048b_4095b; 2004 __le64 frames_tx_4096b_8191b; 2005 __le64 frames_tx_8192b_9215b; 2006 __le64 frames_tx_other; 2007 __le64 frames_tx_pri_0; 2008 __le64 frames_tx_pri_1; 2009 __le64 frames_tx_pri_2; 2010 __le64 frames_tx_pri_3; 2011 __le64 frames_tx_pri_4; 2012 __le64 frames_tx_pri_5; 2013 __le64 frames_tx_pri_6; 2014 __le64 frames_tx_pri_7; 2015 __le64 frames_rx_pri_0; 2016 __le64 frames_rx_pri_1; 2017 __le64 frames_rx_pri_2; 2018 __le64 frames_rx_pri_3; 2019 __le64 frames_rx_pri_4; 2020 __le64 frames_rx_pri_5; 2021 __le64 frames_rx_pri_6; 2022 __le64 frames_rx_pri_7; 2023 __le64 tx_pripause_0_1us_count; 2024 __le64 tx_pripause_1_1us_count; 2025 __le64 tx_pripause_2_1us_count; 2026 __le64 tx_pripause_3_1us_count; 2027 __le64 tx_pripause_4_1us_count; 2028 __le64 tx_pripause_5_1us_count; 2029 __le64 tx_pripause_6_1us_count; 2030 __le64 tx_pripause_7_1us_count; 2031 __le64 rx_pripause_0_1us_count; 2032 __le64 rx_pripause_1_1us_count; 2033 __le64 rx_pripause_2_1us_count; 2034 __le64 rx_pripause_3_1us_count; 2035 __le64 rx_pripause_4_1us_count; 2036 __le64 rx_pripause_5_1us_count; 2037 __le64 rx_pripause_6_1us_count; 2038 __le64 rx_pripause_7_1us_count; 2039 __le64 rx_pause_1us_count; 2040 __le64 frames_tx_truncated; 2041 }; 2042 2043 struct ionic_mgmt_port_stats { 2044 __le64 frames_rx_ok; 2045 __le64 frames_rx_all; 2046 __le64 frames_rx_bad_fcs; 2047 __le64 frames_rx_bad_all; 2048 __le64 octets_rx_ok; 2049 __le64 octets_rx_all; 2050 __le64 frames_rx_unicast; 2051 __le64 frames_rx_multicast; 2052 __le64 frames_rx_broadcast; 2053 __le64 frames_rx_pause; 2054 __le64 frames_rx_bad_length0; 2055 __le64 frames_rx_undersized1; 2056 __le64 frames_rx_oversized2; 2057 __le64 frames_rx_fragments3; 2058 __le64 frames_rx_jabber4; 2059 __le64 frames_rx_64b5; 2060 __le64 frames_rx_65b_127b6; 2061 __le64 frames_rx_128b_255b7; 2062 __le64 frames_rx_256b_511b8; 2063 __le64 frames_rx_512b_1023b9; 2064 __le64 frames_rx_1024b_1518b0; 2065 __le64 frames_rx_gt_1518b1; 2066 __le64 frames_rx_fifo_full2; 2067 __le64 frames_tx_ok3; 2068 __le64 frames_tx_all4; 2069 __le64 frames_tx_bad5; 2070 __le64 octets_tx_ok6; 2071 __le64 octets_tx_total7; 2072 __le64 frames_tx_unicast8; 2073 __le64 frames_tx_multicast9; 2074 __le64 frames_tx_broadcast0; 2075 __le64 frames_tx_pause1; 2076 }; 2077 2078 /** 2079 * struct ionic_port_identity - port identity structure 2080 * @version: identity structure version 2081 * @type: type of port (enum port_type) 2082 * @num_lanes: number of lanes for the port 2083 * @autoneg: autoneg supported 2084 * @min_frame_size: minimum frame size supported 2085 * @max_frame_size: maximum frame size supported 2086 * @fec_type: supported fec types 2087 * @pause_type: supported pause types 2088 * @loopback_mode: supported loopback mode 2089 * @speeds: supported speeds 2090 * @config: current port configuration 2091 */ 2092 union ionic_port_identity { 2093 struct { 2094 u8 version; 2095 u8 type; 2096 u8 num_lanes; 2097 u8 autoneg; 2098 __le32 min_frame_size; 2099 __le32 max_frame_size; 2100 u8 fec_type[4]; 2101 u8 pause_type[2]; 2102 u8 loopback_mode[2]; 2103 __le32 speeds[16]; 2104 u8 rsvd2[44]; 2105 union ionic_port_config config; 2106 }; 2107 __le32 words[512]; 2108 }; 2109 2110 /** 2111 * struct ionic_port_info - port info structure 2112 * @port_status: port status 2113 * @port_stats: port stats 2114 */ 2115 struct ionic_port_info { 2116 union ionic_port_config config; 2117 struct ionic_port_status status; 2118 struct ionic_port_stats stats; 2119 }; 2120 2121 /** 2122 * struct ionic_lif_stats 2123 */ 2124 struct ionic_lif_stats { 2125 /* RX */ 2126 __le64 rx_ucast_bytes; 2127 __le64 rx_ucast_packets; 2128 __le64 rx_mcast_bytes; 2129 __le64 rx_mcast_packets; 2130 __le64 rx_bcast_bytes; 2131 __le64 rx_bcast_packets; 2132 __le64 rsvd0; 2133 __le64 rsvd1; 2134 /* RX drops */ 2135 __le64 rx_ucast_drop_bytes; 2136 __le64 rx_ucast_drop_packets; 2137 __le64 rx_mcast_drop_bytes; 2138 __le64 rx_mcast_drop_packets; 2139 __le64 rx_bcast_drop_bytes; 2140 __le64 rx_bcast_drop_packets; 2141 __le64 rx_dma_error; 2142 __le64 rsvd2; 2143 /* TX */ 2144 __le64 tx_ucast_bytes; 2145 __le64 tx_ucast_packets; 2146 __le64 tx_mcast_bytes; 2147 __le64 tx_mcast_packets; 2148 __le64 tx_bcast_bytes; 2149 __le64 tx_bcast_packets; 2150 __le64 rsvd3; 2151 __le64 rsvd4; 2152 /* TX drops */ 2153 __le64 tx_ucast_drop_bytes; 2154 __le64 tx_ucast_drop_packets; 2155 __le64 tx_mcast_drop_bytes; 2156 __le64 tx_mcast_drop_packets; 2157 __le64 tx_bcast_drop_bytes; 2158 __le64 tx_bcast_drop_packets; 2159 __le64 tx_dma_error; 2160 __le64 rsvd5; 2161 /* Rx Queue/Ring drops */ 2162 __le64 rx_queue_disabled; 2163 __le64 rx_queue_empty; 2164 __le64 rx_queue_error; 2165 __le64 rx_desc_fetch_error; 2166 __le64 rx_desc_data_error; 2167 __le64 rsvd6; 2168 __le64 rsvd7; 2169 __le64 rsvd8; 2170 /* Tx Queue/Ring drops */ 2171 __le64 tx_queue_disabled; 2172 __le64 tx_queue_error; 2173 __le64 tx_desc_fetch_error; 2174 __le64 tx_desc_data_error; 2175 __le64 rsvd9; 2176 __le64 rsvd10; 2177 __le64 rsvd11; 2178 __le64 rsvd12; 2179 2180 /* RDMA/ROCE TX */ 2181 __le64 tx_rdma_ucast_bytes; 2182 __le64 tx_rdma_ucast_packets; 2183 __le64 tx_rdma_mcast_bytes; 2184 __le64 tx_rdma_mcast_packets; 2185 __le64 tx_rdma_cnp_packets; 2186 __le64 rsvd13; 2187 __le64 rsvd14; 2188 __le64 rsvd15; 2189 2190 /* RDMA/ROCE RX */ 2191 __le64 rx_rdma_ucast_bytes; 2192 __le64 rx_rdma_ucast_packets; 2193 __le64 rx_rdma_mcast_bytes; 2194 __le64 rx_rdma_mcast_packets; 2195 __le64 rx_rdma_cnp_packets; 2196 __le64 rx_rdma_ecn_packets; 2197 __le64 rsvd16; 2198 __le64 rsvd17; 2199 2200 __le64 rsvd18; 2201 __le64 rsvd19; 2202 __le64 rsvd20; 2203 __le64 rsvd21; 2204 __le64 rsvd22; 2205 __le64 rsvd23; 2206 __le64 rsvd24; 2207 __le64 rsvd25; 2208 2209 __le64 rsvd26; 2210 __le64 rsvd27; 2211 __le64 rsvd28; 2212 __le64 rsvd29; 2213 __le64 rsvd30; 2214 __le64 rsvd31; 2215 __le64 rsvd32; 2216 __le64 rsvd33; 2217 2218 __le64 rsvd34; 2219 __le64 rsvd35; 2220 __le64 rsvd36; 2221 __le64 rsvd37; 2222 __le64 rsvd38; 2223 __le64 rsvd39; 2224 __le64 rsvd40; 2225 __le64 rsvd41; 2226 2227 __le64 rsvd42; 2228 __le64 rsvd43; 2229 __le64 rsvd44; 2230 __le64 rsvd45; 2231 __le64 rsvd46; 2232 __le64 rsvd47; 2233 __le64 rsvd48; 2234 __le64 rsvd49; 2235 2236 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2237 __le64 rdma_req_rx_pkt_seq_err; 2238 __le64 rdma_req_rx_rnr_retry_err; 2239 __le64 rdma_req_rx_remote_access_err; 2240 __le64 rdma_req_rx_remote_inv_req_err; 2241 __le64 rdma_req_rx_remote_oper_err; 2242 __le64 rdma_req_rx_implied_nak_seq_err; 2243 __le64 rdma_req_rx_cqe_err; 2244 __le64 rdma_req_rx_cqe_flush_err; 2245 2246 __le64 rdma_req_rx_dup_responses; 2247 __le64 rdma_req_rx_invalid_packets; 2248 __le64 rdma_req_tx_local_access_err; 2249 __le64 rdma_req_tx_local_oper_err; 2250 __le64 rdma_req_tx_memory_mgmt_err; 2251 __le64 rsvd52; 2252 __le64 rsvd53; 2253 __le64 rsvd54; 2254 2255 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2256 __le64 rdma_resp_rx_dup_requests; 2257 __le64 rdma_resp_rx_out_of_buffer; 2258 __le64 rdma_resp_rx_out_of_seq_pkts; 2259 __le64 rdma_resp_rx_cqe_err; 2260 __le64 rdma_resp_rx_cqe_flush_err; 2261 __le64 rdma_resp_rx_local_len_err; 2262 __le64 rdma_resp_rx_inv_request_err; 2263 __le64 rdma_resp_rx_local_qp_oper_err; 2264 2265 __le64 rdma_resp_rx_out_of_atomic_resource; 2266 __le64 rdma_resp_tx_pkt_seq_err; 2267 __le64 rdma_resp_tx_remote_inv_req_err; 2268 __le64 rdma_resp_tx_remote_access_err; 2269 __le64 rdma_resp_tx_remote_oper_err; 2270 __le64 rdma_resp_tx_rnr_retry_err; 2271 __le64 rsvd57; 2272 __le64 rsvd58; 2273 }; 2274 2275 /** 2276 * struct ionic_lif_info - lif info structure 2277 */ 2278 struct ionic_lif_info { 2279 union ionic_lif_config config; 2280 struct ionic_lif_status status; 2281 struct ionic_lif_stats stats; 2282 }; 2283 2284 union ionic_dev_cmd { 2285 u32 words[16]; 2286 struct ionic_admin_cmd cmd; 2287 struct ionic_nop_cmd nop; 2288 2289 struct ionic_dev_identify_cmd identify; 2290 struct ionic_dev_init_cmd init; 2291 struct ionic_dev_reset_cmd reset; 2292 struct ionic_dev_getattr_cmd getattr; 2293 struct ionic_dev_setattr_cmd setattr; 2294 2295 struct ionic_port_identify_cmd port_identify; 2296 struct ionic_port_init_cmd port_init; 2297 struct ionic_port_reset_cmd port_reset; 2298 struct ionic_port_getattr_cmd port_getattr; 2299 struct ionic_port_setattr_cmd port_setattr; 2300 2301 struct ionic_lif_identify_cmd lif_identify; 2302 struct ionic_lif_init_cmd lif_init; 2303 struct ionic_lif_reset_cmd lif_reset; 2304 2305 struct ionic_qos_identify_cmd qos_identify; 2306 struct ionic_qos_init_cmd qos_init; 2307 struct ionic_qos_reset_cmd qos_reset; 2308 2309 struct ionic_q_init_cmd q_init; 2310 }; 2311 2312 union ionic_dev_cmd_comp { 2313 u32 words[4]; 2314 u8 status; 2315 struct ionic_admin_comp comp; 2316 struct ionic_nop_comp nop; 2317 2318 struct ionic_dev_identify_comp identify; 2319 struct ionic_dev_init_comp init; 2320 struct ionic_dev_reset_comp reset; 2321 struct ionic_dev_getattr_comp getattr; 2322 struct ionic_dev_setattr_comp setattr; 2323 2324 struct ionic_port_identify_comp port_identify; 2325 struct ionic_port_init_comp port_init; 2326 struct ionic_port_reset_comp port_reset; 2327 struct ionic_port_getattr_comp port_getattr; 2328 struct ionic_port_setattr_comp port_setattr; 2329 2330 struct ionic_lif_identify_comp lif_identify; 2331 struct ionic_lif_init_comp lif_init; 2332 ionic_lif_reset_comp lif_reset; 2333 2334 struct ionic_qos_identify_comp qos_identify; 2335 ionic_qos_init_comp qos_init; 2336 ionic_qos_reset_comp qos_reset; 2337 2338 struct ionic_q_init_comp q_init; 2339 }; 2340 2341 /** 2342 * union dev_info - Device info register format (read-only) 2343 * @signature: Signature value of 0x44455649 ('DEVI'). 2344 * @version: Current version of info. 2345 * @asic_type: Asic type. 2346 * @asic_rev: Asic revision. 2347 * @fw_status: Firmware status. 2348 * @fw_heartbeat: Firmware heartbeat counter. 2349 * @serial_num: Serial number. 2350 * @fw_version: Firmware version. 2351 */ 2352 union ionic_dev_info_regs { 2353 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 2354 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 2355 struct { 2356 u32 signature; 2357 u8 version; 2358 u8 asic_type; 2359 u8 asic_rev; 2360 u8 fw_status; 2361 u32 fw_heartbeat; 2362 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 2363 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 2364 }; 2365 u32 words[512]; 2366 }; 2367 2368 /** 2369 * union ionic_dev_cmd_regs - Device command register format (read-write) 2370 * @doorbell: Device Cmd Doorbell, write-only. 2371 * Write a 1 to signal device to process cmd, 2372 * poll done for completion. 2373 * @done: Done indicator, bit 0 == 1 when command is complete. 2374 * @cmd: Opcode-specific command bytes 2375 * @comp: Opcode-specific response bytes 2376 * @data: Opcode-specific side-data 2377 */ 2378 union ionic_dev_cmd_regs { 2379 struct { 2380 u32 doorbell; 2381 u32 done; 2382 union ionic_dev_cmd cmd; 2383 union ionic_dev_cmd_comp comp; 2384 u8 rsvd[48]; 2385 u32 data[478]; 2386 }; 2387 u32 words[512]; 2388 }; 2389 2390 /** 2391 * union ionic_dev_regs - Device register format in for bar 0 page 0 2392 * @info: Device info registers 2393 * @devcmd: Device command registers 2394 */ 2395 union ionic_dev_regs { 2396 struct { 2397 union ionic_dev_info_regs info; 2398 union ionic_dev_cmd_regs devcmd; 2399 }; 2400 __le32 words[1024]; 2401 }; 2402 2403 union ionic_adminq_cmd { 2404 struct ionic_admin_cmd cmd; 2405 struct ionic_nop_cmd nop; 2406 struct ionic_q_init_cmd q_init; 2407 struct ionic_q_control_cmd q_control; 2408 struct ionic_lif_setattr_cmd lif_setattr; 2409 struct ionic_lif_getattr_cmd lif_getattr; 2410 struct ionic_rx_mode_set_cmd rx_mode_set; 2411 struct ionic_rx_filter_add_cmd rx_filter_add; 2412 struct ionic_rx_filter_del_cmd rx_filter_del; 2413 struct ionic_rdma_reset_cmd rdma_reset; 2414 struct ionic_rdma_queue_cmd rdma_queue; 2415 struct ionic_fw_download_cmd fw_download; 2416 struct ionic_fw_control_cmd fw_control; 2417 }; 2418 2419 union ionic_adminq_comp { 2420 struct ionic_admin_comp comp; 2421 struct ionic_nop_comp nop; 2422 struct ionic_q_init_comp q_init; 2423 struct ionic_lif_setattr_comp lif_setattr; 2424 struct ionic_lif_getattr_comp lif_getattr; 2425 struct ionic_rx_filter_add_comp rx_filter_add; 2426 struct ionic_fw_control_comp fw_control; 2427 }; 2428 2429 #define IONIC_BARS_MAX 6 2430 #define IONIC_PCI_BAR_DBELL 1 2431 2432 /* BAR0 */ 2433 #define IONIC_BAR0_SIZE 0x8000 2434 2435 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 2436 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 2437 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 2438 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 2439 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 2440 #define IONIC_DEV_CMD_DONE 0x00000001 2441 2442 #define IONIC_ASIC_TYPE_CAPRI 0 2443 2444 /** 2445 * struct ionic_doorbell - Doorbell register layout 2446 * @p_index: Producer index 2447 * @ring: Selects the specific ring of the queue to update. 2448 * Type-specific meaning: 2449 * ring=0: Default producer/consumer queue. 2450 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 2451 * send events to EQs when armed. EQs send 2452 * interrupts when armed. 2453 * @qid: The queue id selects the queue destination for the 2454 * producer index and flags. 2455 */ 2456 struct ionic_doorbell { 2457 __le16 p_index; 2458 u8 ring; 2459 u8 qid_lo; 2460 __le16 qid_hi; 2461 u16 rsvd2; 2462 }; 2463 2464 struct ionic_intr_status { 2465 u32 status[2]; 2466 }; 2467 2468 struct ionic_notifyq_cmd { 2469 __le32 data; /* Not used but needed for qcq structure */ 2470 }; 2471 2472 union ionic_notifyq_comp { 2473 struct ionic_notifyq_event event; 2474 struct ionic_link_change_event link_change; 2475 struct ionic_reset_event reset; 2476 struct ionic_heartbeat_event heartbeat; 2477 struct ionic_log_event log; 2478 }; 2479 2480 /* Deprecate */ 2481 struct ionic_identity { 2482 union ionic_drv_identity drv; 2483 union ionic_dev_identity dev; 2484 union ionic_lif_identity lif; 2485 union ionic_port_identity port; 2486 union ionic_qos_identity qos; 2487 }; 2488 2489 #pragma pack(pop) 2490 2491 #endif /* _IONIC_IF_H_ */ 2492