1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #ifndef _IONIC_IF_H_ 6 #define _IONIC_IF_H_ 7 8 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 9 #define IONIC_DEV_INFO_VERSION 1 10 #define IONIC_IFNAMSIZ 16 11 12 /** 13 * enum ionic_cmd_opcode - Device commands 14 */ 15 enum ionic_cmd_opcode { 16 IONIC_CMD_NOP = 0, 17 18 /* Device commands */ 19 IONIC_CMD_IDENTIFY = 1, 20 IONIC_CMD_INIT = 2, 21 IONIC_CMD_RESET = 3, 22 IONIC_CMD_GETATTR = 4, 23 IONIC_CMD_SETATTR = 5, 24 25 /* Port commands */ 26 IONIC_CMD_PORT_IDENTIFY = 10, 27 IONIC_CMD_PORT_INIT = 11, 28 IONIC_CMD_PORT_RESET = 12, 29 IONIC_CMD_PORT_GETATTR = 13, 30 IONIC_CMD_PORT_SETATTR = 14, 31 32 /* LIF commands */ 33 IONIC_CMD_LIF_IDENTIFY = 20, 34 IONIC_CMD_LIF_INIT = 21, 35 IONIC_CMD_LIF_RESET = 22, 36 IONIC_CMD_LIF_GETATTR = 23, 37 IONIC_CMD_LIF_SETATTR = 24, 38 39 IONIC_CMD_RX_MODE_SET = 30, 40 IONIC_CMD_RX_FILTER_ADD = 31, 41 IONIC_CMD_RX_FILTER_DEL = 32, 42 43 /* Queue commands */ 44 IONIC_CMD_Q_IDENTIFY = 39, 45 IONIC_CMD_Q_INIT = 40, 46 IONIC_CMD_Q_CONTROL = 41, 47 48 /* RDMA commands */ 49 IONIC_CMD_RDMA_RESET_LIF = 50, 50 IONIC_CMD_RDMA_CREATE_EQ = 51, 51 IONIC_CMD_RDMA_CREATE_CQ = 52, 52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 53 54 /* SR/IOV commands */ 55 IONIC_CMD_VF_GETATTR = 60, 56 IONIC_CMD_VF_SETATTR = 61, 57 58 /* QoS commands */ 59 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 60 IONIC_CMD_QOS_CLASS_INIT = 241, 61 IONIC_CMD_QOS_CLASS_RESET = 242, 62 IONIC_CMD_QOS_CLASS_UPDATE = 243, 63 IONIC_CMD_QOS_CLEAR_STATS = 244, 64 IONIC_CMD_QOS_RESET = 245, 65 66 /* Firmware commands */ 67 IONIC_CMD_FW_DOWNLOAD = 254, 68 IONIC_CMD_FW_CONTROL = 255, 69 }; 70 71 /** 72 * enum ionic_status_code - Device command return codes 73 */ 74 enum ionic_status_code { 75 IONIC_RC_SUCCESS = 0, /* Success */ 76 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 77 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 78 IONIC_RC_EIO = 3, /* I/O error */ 79 IONIC_RC_EPERM = 4, /* Permission denied */ 80 IONIC_RC_EQID = 5, /* Bad qid */ 81 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 82 IONIC_RC_ENOENT = 7, /* No such element */ 83 IONIC_RC_EINTR = 8, /* operation interrupted */ 84 IONIC_RC_EAGAIN = 9, /* Try again */ 85 IONIC_RC_ENOMEM = 10, /* Out of memory */ 86 IONIC_RC_EFAULT = 11, /* Bad address */ 87 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 88 IONIC_RC_EEXIST = 13, /* object already exists */ 89 IONIC_RC_EINVAL = 14, /* Invalid argument */ 90 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 91 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 92 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 93 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 94 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 95 IONIC_RC_ERROR = 29, /* Generic error */ 96 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 97 IONIC_RC_EVFID = 31, /* VF ID does not exist */ 98 }; 99 100 enum ionic_notifyq_opcode { 101 IONIC_EVENT_LINK_CHANGE = 1, 102 IONIC_EVENT_RESET = 2, 103 IONIC_EVENT_HEARTBEAT = 3, 104 IONIC_EVENT_LOG = 4, 105 IONIC_EVENT_XCVR = 5, 106 }; 107 108 /** 109 * struct ionic_admin_cmd - General admin command format 110 * @opcode: Opcode for the command 111 * @lif_index: LIF index 112 * @cmd_data: Opcode-specific command bytes 113 */ 114 struct ionic_admin_cmd { 115 u8 opcode; 116 u8 rsvd; 117 __le16 lif_index; 118 u8 cmd_data[60]; 119 }; 120 121 /** 122 * struct ionic_admin_comp - General admin command completion format 123 * @status: Status of the command (enum ionic_status_code) 124 * @comp_index: Index in the descriptor ring for which this is the completion 125 * @cmd_data: Command-specific bytes 126 * @color: Color bit (Always 0 for commands issued to the 127 * Device Cmd Registers) 128 */ 129 struct ionic_admin_comp { 130 u8 status; 131 u8 rsvd; 132 __le16 comp_index; 133 u8 cmd_data[11]; 134 u8 color; 135 #define IONIC_COMP_COLOR_MASK 0x80 136 }; 137 138 static inline u8 color_match(u8 color, u8 done_color) 139 { 140 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 141 } 142 143 /** 144 * struct ionic_nop_cmd - NOP command 145 * @opcode: opcode 146 */ 147 struct ionic_nop_cmd { 148 u8 opcode; 149 u8 rsvd[63]; 150 }; 151 152 /** 153 * struct ionic_nop_comp - NOP command completion 154 * @status: Status of the command (enum ionic_status_code) 155 */ 156 struct ionic_nop_comp { 157 u8 status; 158 u8 rsvd[15]; 159 }; 160 161 /** 162 * struct ionic_dev_init_cmd - Device init command 163 * @opcode: opcode 164 * @type: Device type 165 */ 166 struct ionic_dev_init_cmd { 167 u8 opcode; 168 u8 type; 169 u8 rsvd[62]; 170 }; 171 172 /** 173 * struct ionic_dev_init_comp - Device init command completion 174 * @status: Status of the command (enum ionic_status_code) 175 */ 176 struct ionic_dev_init_comp { 177 u8 status; 178 u8 rsvd[15]; 179 }; 180 181 /** 182 * struct ionic_dev_reset_cmd - Device reset command 183 * @opcode: opcode 184 */ 185 struct ionic_dev_reset_cmd { 186 u8 opcode; 187 u8 rsvd[63]; 188 }; 189 190 /** 191 * struct ionic_dev_reset_comp - Reset command completion 192 * @status: Status of the command (enum ionic_status_code) 193 */ 194 struct ionic_dev_reset_comp { 195 u8 status; 196 u8 rsvd[15]; 197 }; 198 199 #define IONIC_IDENTITY_VERSION_1 1 200 201 /** 202 * struct ionic_dev_identify_cmd - Driver/device identify command 203 * @opcode: opcode 204 * @ver: Highest version of identify supported by driver 205 */ 206 struct ionic_dev_identify_cmd { 207 u8 opcode; 208 u8 ver; 209 u8 rsvd[62]; 210 }; 211 212 /** 213 * struct ionic_dev_identify_comp - Driver/device identify command completion 214 * @status: Status of the command (enum ionic_status_code) 215 * @ver: Version of identify returned by device 216 */ 217 struct ionic_dev_identify_comp { 218 u8 status; 219 u8 ver; 220 u8 rsvd[14]; 221 }; 222 223 enum ionic_os_type { 224 IONIC_OS_TYPE_LINUX = 1, 225 IONIC_OS_TYPE_WIN = 2, 226 IONIC_OS_TYPE_DPDK = 3, 227 IONIC_OS_TYPE_FREEBSD = 4, 228 IONIC_OS_TYPE_IPXE = 5, 229 IONIC_OS_TYPE_ESXI = 6, 230 }; 231 232 /** 233 * union ionic_drv_identity - driver identity information 234 * @os_type: OS type (see enum ionic_os_type) 235 * @os_dist: OS distribution, numeric format 236 * @os_dist_str: OS distribution, string format 237 * @kernel_ver: Kernel version, numeric format 238 * @kernel_ver_str: Kernel version, string format 239 * @driver_ver_str: Driver version, string format 240 */ 241 union ionic_drv_identity { 242 struct { 243 __le32 os_type; 244 __le32 os_dist; 245 char os_dist_str[128]; 246 __le32 kernel_ver; 247 char kernel_ver_str[32]; 248 char driver_ver_str[32]; 249 }; 250 __le32 words[478]; 251 }; 252 253 /** 254 * union ionic_dev_identity - device identity information 255 * @version: Version of device identify 256 * @type: Identify type (0 for now) 257 * @nports: Number of ports provisioned 258 * @nlifs: Number of LIFs provisioned 259 * @nintrs: Number of interrupts provisioned 260 * @ndbpgs_per_lif: Number of doorbell pages per LIF 261 * @intr_coal_mult: Interrupt coalescing multiplication factor 262 * Scale user-supplied interrupt coalescing 263 * value in usecs to device units using: 264 * device units = usecs * mult / div 265 * @intr_coal_div: Interrupt coalescing division factor 266 * Scale user-supplied interrupt coalescing 267 * value in usecs to device units using: 268 * device units = usecs * mult / div 269 * @eq_count: Number of shared event queues 270 */ 271 union ionic_dev_identity { 272 struct { 273 u8 version; 274 u8 type; 275 u8 rsvd[2]; 276 u8 nports; 277 u8 rsvd2[3]; 278 __le32 nlifs; 279 __le32 nintrs; 280 __le32 ndbpgs_per_lif; 281 __le32 intr_coal_mult; 282 __le32 intr_coal_div; 283 __le32 eq_count; 284 }; 285 __le32 words[478]; 286 }; 287 288 enum ionic_lif_type { 289 IONIC_LIF_TYPE_CLASSIC = 0, 290 IONIC_LIF_TYPE_MACVLAN = 1, 291 IONIC_LIF_TYPE_NETQUEUE = 2, 292 }; 293 294 /** 295 * struct ionic_lif_identify_cmd - LIF identify command 296 * @opcode: opcode 297 * @type: LIF type (enum ionic_lif_type) 298 * @ver: Version of identify returned by device 299 */ 300 struct ionic_lif_identify_cmd { 301 u8 opcode; 302 u8 type; 303 u8 ver; 304 u8 rsvd[61]; 305 }; 306 307 /** 308 * struct ionic_lif_identify_comp - LIF identify command completion 309 * @status: Status of the command (enum ionic_status_code) 310 * @ver: Version of identify returned by device 311 */ 312 struct ionic_lif_identify_comp { 313 u8 status; 314 u8 ver; 315 u8 rsvd2[14]; 316 }; 317 318 /** 319 * enum ionic_lif_capability - LIF capabilities 320 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 321 * @IONIC_LIF_CAP_RDMA: LIF support RDMA 322 */ 323 enum ionic_lif_capability { 324 IONIC_LIF_CAP_ETH = BIT(0), 325 IONIC_LIF_CAP_RDMA = BIT(1), 326 }; 327 328 /** 329 * enum ionic_logical_qtype - Logical Queue Types 330 * @IONIC_QTYPE_ADMINQ: Administrative Queue 331 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 332 * @IONIC_QTYPE_RXQ: Receive Queue 333 * @IONIC_QTYPE_TXQ: Transmit Queue 334 * @IONIC_QTYPE_EQ: Event Queue 335 * @IONIC_QTYPE_MAX: Max queue type supported 336 */ 337 enum ionic_logical_qtype { 338 IONIC_QTYPE_ADMINQ = 0, 339 IONIC_QTYPE_NOTIFYQ = 1, 340 IONIC_QTYPE_RXQ = 2, 341 IONIC_QTYPE_TXQ = 3, 342 IONIC_QTYPE_EQ = 4, 343 IONIC_QTYPE_MAX = 16, 344 }; 345 346 /** 347 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 348 * @qtype: Hardware Queue Type 349 * @qid_count: Number of Queue IDs of the logical type 350 * @qid_base: Minimum Queue ID of the logical type 351 */ 352 struct ionic_lif_logical_qtype { 353 u8 qtype; 354 u8 rsvd[3]; 355 __le32 qid_count; 356 __le32 qid_base; 357 }; 358 359 /** 360 * enum ionic_lif_state - LIF state 361 * @IONIC_LIF_DISABLE: LIF disabled 362 * @IONIC_LIF_ENABLE: LIF enabled 363 * @IONIC_LIF_QUIESCE: LIF Quiesced 364 */ 365 enum ionic_lif_state { 366 IONIC_LIF_QUIESCE = 0, 367 IONIC_LIF_ENABLE = 1, 368 IONIC_LIF_DISABLE = 2, 369 }; 370 371 /** 372 * union ionic_lif_config - LIF configuration 373 * @state: LIF state (enum ionic_lif_state) 374 * @name: LIF name 375 * @mtu: MTU 376 * @mac: Station MAC address 377 * @vlan: Default Vlan ID 378 * @features: Features (enum ionic_eth_hw_features) 379 * @queue_count: Queue counts per queue-type 380 */ 381 union ionic_lif_config { 382 struct __rte_packed_begin { 383 u8 state; 384 u8 rsvd[3]; 385 char name[IONIC_IFNAMSIZ]; 386 __le32 mtu; 387 u8 mac[6]; 388 __le16 vlan; 389 __le64 features; 390 __le32 queue_count[IONIC_QTYPE_MAX]; 391 } __rte_packed_end; 392 __le32 words[64]; 393 }; 394 395 /** 396 * struct ionic_lif_identity - LIF identity information (type-specific) 397 * 398 * @capabilities: LIF capabilities 399 * 400 * @eth: Ethernet identify structure 401 * @version: Ethernet identify structure version 402 * @max_ucast_filters: Number of perfect unicast addresses supported 403 * @max_mcast_filters: Number of perfect multicast addresses supported 404 * @min_mtu: Minimum MTU of frames to be sent 405 * @max_mtu: Maximum MTU of frames to be sent 406 * @config: LIF config struct with features, mtu, mac, q counts 407 * 408 * @rdma: RDMA identify structure 409 * @version: RDMA version of opcodes and queue descriptors 410 * @qp_opcodes: Number of RDMA queue pair opcodes supported 411 * @admin_opcodes: Number of RDMA admin opcodes supported 412 * @npts_per_lif: Page table size per LIF 413 * @nmrs_per_lif: Number of memory regions per LIF 414 * @nahs_per_lif: Number of address handles per LIF 415 * @max_stride: Max work request stride 416 * @cl_stride: Cache line stride 417 * @pte_stride: Page table entry stride 418 * @rrq_stride: Remote RQ work request stride 419 * @rsq_stride: Remote SQ work request stride 420 * @dcqcn_profiles: Number of DCQCN profiles 421 * @aq_qtype: RDMA Admin Qtype 422 * @sq_qtype: RDMA Send Qtype 423 * @rq_qtype: RDMA Receive Qtype 424 * @cq_qtype: RDMA Completion Qtype 425 * @eq_qtype: RDMA Event Qtype 426 */ 427 union ionic_lif_identity { 428 struct __rte_packed_begin { 429 __le64 capabilities; 430 431 struct __rte_packed_begin { 432 u8 version; 433 u8 rsvd[3]; 434 __le32 max_ucast_filters; 435 __le32 max_mcast_filters; 436 __le16 rss_ind_tbl_sz; 437 __le32 min_mtu; 438 __le32 max_mtu; 439 u8 rsvd2[106]; 440 union ionic_lif_config config; 441 } __rte_packed_end eth; 442 443 struct __rte_packed_begin { 444 u8 version; 445 u8 qp_opcodes; 446 u8 admin_opcodes; 447 u8 rsvd; 448 __le32 npts_per_lif; 449 __le32 nmrs_per_lif; 450 __le32 nahs_per_lif; 451 u8 max_stride; 452 u8 cl_stride; 453 u8 pte_stride; 454 u8 rrq_stride; 455 u8 rsq_stride; 456 u8 dcqcn_profiles; 457 u8 rsvd_dimensions[10]; 458 struct ionic_lif_logical_qtype aq_qtype; 459 struct ionic_lif_logical_qtype sq_qtype; 460 struct ionic_lif_logical_qtype rq_qtype; 461 struct ionic_lif_logical_qtype cq_qtype; 462 struct ionic_lif_logical_qtype eq_qtype; 463 } __rte_packed_end rdma; 464 } __rte_packed_end; 465 __le32 words[478]; 466 }; 467 468 /** 469 * struct ionic_lif_init_cmd - LIF init command 470 * @opcode: Opcode 471 * @type: LIF type (enum ionic_lif_type) 472 * @index: LIF index 473 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 474 */ 475 struct ionic_lif_init_cmd { 476 u8 opcode; 477 u8 type; 478 __le16 index; 479 __le32 rsvd; 480 __le64 info_pa; 481 u8 rsvd2[48]; 482 }; 483 484 /** 485 * struct ionic_lif_init_comp - LIF init command completion 486 * @status: Status of the command (enum ionic_status_code) 487 * @hw_index: Hardware index of the initialized LIF 488 */ 489 struct ionic_lif_init_comp { 490 u8 status; 491 u8 rsvd; 492 __le16 hw_index; 493 u8 rsvd2[12]; 494 }; 495 496 /** 497 * struct ionic_q_identify_cmd - queue identify command 498 * @opcode: opcode 499 * @lif_type: LIF type (enum ionic_lif_type) 500 * @type: Logical queue type (enum ionic_logical_qtype) 501 * @ver: Highest queue type version that the driver supports 502 */ 503 struct ionic_q_identify_cmd { 504 u8 opcode; 505 u8 rsvd; 506 __le16 lif_type; 507 u8 type; 508 u8 ver; 509 u8 rsvd2[58]; 510 }; 511 512 /** 513 * struct ionic_q_identify_comp - queue identify command completion 514 * @status: Status of the command (enum ionic_status_code) 515 * @comp_index: Index in the descriptor ring for which this is the completion 516 * @ver: Queue type version that can be used with FW 517 */ 518 struct ionic_q_identify_comp { 519 u8 status; 520 u8 rsvd; 521 __le16 comp_index; 522 u8 ver; 523 u8 rsvd2[11]; 524 }; 525 526 /** 527 * union ionic_q_identity - queue identity information 528 * @version: Queue type version that can be used with FW 529 * @supported: Bitfield of queue versions, first bit = ver 0 530 * @features: Queue features 531 * @desc_sz: Descriptor size 532 * @comp_sz: Completion descriptor size 533 * @sg_desc_sz: Scatter/Gather descriptor size 534 * @max_sg_elems: Maximum number of Scatter/Gather elements 535 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 536 */ 537 union ionic_q_identity { 538 struct { 539 u8 version; 540 u8 supported; 541 u8 rsvd[6]; 542 #define IONIC_QIDENT_F_CQ 0x01 /* queue has completion ring */ 543 #define IONIC_QIDENT_F_SG 0x02 /* queue has scatter/gather ring */ 544 #define IONIC_QIDENT_F_EQ 0x04 /* queue can use event queue */ 545 #define IONIC_QIDENT_F_CMB 0x08 /* queue is in cmb bar */ 546 __le64 features; 547 __le16 desc_sz; 548 __le16 comp_sz; 549 __le16 sg_desc_sz; 550 __le16 max_sg_elems; 551 __le16 sg_desc_stride; 552 }; 553 __le32 words[478]; 554 }; 555 556 /** 557 * struct ionic_q_init_cmd - Queue init command 558 * @opcode: opcode 559 * @type: Logical queue type 560 * @ver: Queue type version 561 * @lif_index: LIF index 562 * @index: (LIF, qtype) relative admin queue index 563 * @intr_index: Interrupt control register index, or Event queue index 564 * @pid: Process ID 565 * @flags: 566 * IRQ: Interrupt requested on completion 567 * ENA: Enable the queue. If ENA=0 the queue is initialized 568 * but remains disabled, to be later enabled with the 569 * Queue Enable command. If ENA=1, then queue is 570 * initialized and then enabled. 571 * SG: Enable Scatter-Gather on the queue. 572 * in number of descs. The actual ring size is 573 * (1 << ring_size). For example, to 574 * select a ring size of 64 descriptors write 575 * ring_size = 6. The minimum ring_size value is 2 576 * for a ring size of 4 descriptors. The maximum 577 * ring_size value is 16 for a ring size of 64k 578 * descriptors. Values of ring_size <2 and >16 are 579 * reserved. 580 * EQ: Enable the Event Queue 581 * @cos: Class of service for this queue 582 * @ring_size: Queue ring size, encoded as a log2(size) 583 * @ring_base: Queue ring base address 584 * @cq_ring_base: Completion queue ring base address 585 * @sg_ring_base: Scatter/Gather ring base address 586 */ 587 struct __rte_packed_begin ionic_q_init_cmd { 588 u8 opcode; 589 u8 rsvd; 590 __le16 lif_index; 591 u8 type; 592 u8 ver; 593 u8 rsvd1[2]; 594 __le32 index; 595 __le16 pid; 596 __le16 intr_index; 597 __le16 flags; 598 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 599 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 600 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 601 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 602 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 603 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 604 u8 cos; 605 u8 ring_size; 606 __le64 ring_base; 607 __le64 cq_ring_base; 608 __le64 sg_ring_base; 609 u8 rsvd2[20]; 610 } __rte_packed_end; 611 612 /** 613 * struct ionic_q_init_comp - Queue init command completion 614 * @status: Status of the command (enum ionic_status_code) 615 * @comp_index: Index in the descriptor ring for which this is the completion 616 * @hw_index: Hardware Queue ID 617 * @hw_type: Hardware Queue type 618 * @color: Color 619 */ 620 struct ionic_q_init_comp { 621 u8 status; 622 u8 rsvd; 623 __le16 comp_index; 624 __le32 hw_index; 625 u8 hw_type; 626 u8 rsvd2[6]; 627 u8 color; 628 }; 629 630 /* the device's internal addressing uses up to 52 bits */ 631 #define IONIC_ADDR_LEN 52 632 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 633 634 enum ionic_txq_desc_opcode { 635 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 636 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 637 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 638 IONIC_TXQ_DESC_OPCODE_TSO = 3, 639 }; 640 641 /** 642 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 643 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 644 * 645 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 646 * Non-offload send. No segmentation, 647 * fragmentation or checksum calc/insertion is 648 * performed by device; packet is prepared 649 * to send by software stack and requires 650 * no further manipulation from device. 651 * 652 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 653 * Offload 16-bit L4 checksum 654 * calculation/insertion. The device will 655 * calculate the L4 checksum value and 656 * insert the result in the packet's L4 657 * header checksum field. The L4 checksum 658 * is calculated starting at @csum_start bytes 659 * into the packet to the end of the packet. 660 * The checksum insertion position is given 661 * in @csum_offset, which is the offset from 662 * @csum_start to the checksum field in the L4 663 * header. This feature is only applicable to 664 * protocols such as TCP, UDP and ICMP where a 665 * standard (i.e. the 'IP-style' checksum) 666 * one's complement 16-bit checksum is used, 667 * using an IP pseudo-header to seed the 668 * calculation. Software will preload the L4 669 * checksum field with the IP pseudo-header 670 * checksum. 671 * 672 * For tunnel encapsulation, @csum_start and 673 * @csum_offset refer to the inner L4 674 * header. Supported tunnels encapsulations 675 * are: IPIP, GRE, and UDP. If the @encap 676 * is clear, no further processing by the 677 * device is required; software will 678 * calculate the outer header checksums. If 679 * the @encap is set, the device will 680 * offload the outer header checksums using 681 * LCO (local checksum offload) (see 682 * Documentation/networking/checksum-offloads.rst 683 * for more info). 684 * 685 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 686 * Offload 16-bit checksum computation to hardware. 687 * If @csum_l3 is set then the packet's L3 checksum is 688 * updated. Similarly, if @csum_l4 is set the L4 689 * checksum is updated. If @encap is set then encap header 690 * checksums are also updated. 691 * 692 * IONIC_TXQ_DESC_OPCODE_TSO: 693 * Device performs TCP segmentation offload 694 * (TSO). @hdr_len is the number of bytes 695 * to the end of TCP header (the offset to 696 * the TCP payload). @mss is the desired 697 * MSS, the TCP payload length for each 698 * segment. The device will calculate/ 699 * insert IP (IPv4 only) and TCP checksums 700 * for each segment. In the first data 701 * buffer containing the header template, 702 * the driver will set IPv4 checksum to 0 703 * and preload TCP checksum with the IP 704 * pseudo header calculated with IP length = 0. 705 * 706 * Supported tunnel encapsulations are IPIP, 707 * layer-3 GRE, and UDP. @hdr_len includes 708 * both outer and inner headers. The driver 709 * will set IPv4 checksum to zero and 710 * preload TCP checksum with IP pseudo 711 * header on the inner header. 712 * 713 * TCP ECN offload is supported. The device 714 * will set CWR flag in the first segment if 715 * CWR is set in the template header, and 716 * clear CWR in remaining segments. 717 * @flags: 718 * vlan: 719 * Insert an L2 VLAN header using @vlan_tci 720 * encap: 721 * Calculate encap header checksum 722 * csum_l3: 723 * Compute L3 header checksum 724 * csum_l4: 725 * Compute L4 header checksum 726 * tso_sot: 727 * TSO start 728 * tso_eot: 729 * TSO end 730 * @num_sg_elems: Number of scatter-gather elements in SG 731 * descriptor 732 * @addr: First data buffer's DMA address 733 * (Subsequent data buffers are on txq_sg_desc) 734 * @len: First data buffer's length, in bytes 735 * @vlan_tci: VLAN tag to insert in the packet (if requested 736 * by @V-bit). Includes .1p and .1q tags 737 * @hdr_len: Length of packet headers, including 738 * encapsulating outer header, if applicable 739 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 740 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 741 * all other modes. For 742 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 743 * of headers up to inner-most L4 header. For 744 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 745 * inner-most L4 payload, so inclusive of 746 * inner-most L4 header. 747 * @mss: Desired MSS value for TSO; only applicable for 748 * IONIC_TXQ_DESC_OPCODE_TSO 749 * @csum_start: Offset from packet to first byte checked in L4 checksum 750 * @csum_offset: Offset from csum_start to L4 checksum field 751 */ 752 struct ionic_txq_desc { 753 __le64 cmd; 754 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 755 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 756 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 757 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 758 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 759 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 760 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 761 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 762 763 /* common flags */ 764 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 765 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 766 767 /* flags for csum_hw opcode */ 768 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 769 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 770 771 /* flags for tso opcode */ 772 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 773 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 774 775 __le16 len; 776 union { 777 __le16 vlan_tci; 778 __le16 hword0; 779 }; 780 union { 781 __le16 csum_start; 782 __le16 hdr_len; 783 __le16 hword1; 784 }; 785 union { 786 __le16 csum_offset; 787 __le16 mss; 788 __le16 hword2; 789 }; 790 }; 791 792 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 793 u8 nsge, u64 addr) 794 { 795 u64 cmd; 796 797 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << 798 IONIC_TXQ_DESC_OPCODE_SHIFT; 799 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << 800 IONIC_TXQ_DESC_FLAGS_SHIFT; 801 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << 802 IONIC_TXQ_DESC_NSGE_SHIFT; 803 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << 804 IONIC_TXQ_DESC_ADDR_SHIFT; 805 806 return cmd; 807 }; 808 809 static inline void 810 decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 811 u8 *nsge, u64 *addr) 812 { 813 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & 814 IONIC_TXQ_DESC_OPCODE_MASK; 815 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & 816 IONIC_TXQ_DESC_FLAGS_MASK; 817 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & 818 IONIC_TXQ_DESC_NSGE_MASK; 819 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & 820 IONIC_TXQ_DESC_ADDR_MASK; 821 }; 822 823 /** 824 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 825 * @addr: DMA address of SG element data buffer 826 * @len: Length of SG element data buffer, in bytes 827 */ 828 struct ionic_txq_sg_elem { 829 __le64 addr; 830 __le16 len; 831 __le16 rsvd[3]; 832 }; 833 834 /** 835 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 836 * @elems: Scatter-gather elements 837 */ 838 struct ionic_txq_sg_desc { 839 #define IONIC_TX_MAX_SG_ELEMS 8 840 #define IONIC_TX_SG_DESC_STRIDE 8 841 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 842 }; 843 844 struct ionic_txq_sg_desc_v1 { 845 #define IONIC_TX_MAX_SG_ELEMS_V1 15 846 #define IONIC_TX_SG_DESC_STRIDE_V1 16 847 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 848 }; 849 850 /** 851 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 852 * @status: Status of the command (enum ionic_status_code) 853 * @comp_index: Index in the descriptor ring for which this is the completion 854 * @color: Color bit 855 */ 856 struct ionic_txq_comp { 857 u8 status; 858 u8 rsvd; 859 __le16 comp_index; 860 u8 rsvd2[11]; 861 u8 color; 862 }; 863 864 enum ionic_rxq_desc_opcode { 865 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 866 IONIC_RXQ_DESC_OPCODE_SG = 1, 867 }; 868 869 /** 870 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 871 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 872 * 873 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 874 * Receive full packet into data buffer 875 * starting at @addr. Results of 876 * receive, including actual bytes received, 877 * are recorded in Rx completion descriptor. 878 * 879 * @len: Data buffer's length, in bytes 880 * @addr: Data buffer's DMA address 881 */ 882 struct ionic_rxq_desc { 883 u8 opcode; 884 u8 rsvd[5]; 885 __le16 len; 886 __le64 addr; 887 }; 888 889 /** 890 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 891 * @addr: DMA address of SG element data buffer 892 * @len: Length of SG element data buffer, in bytes 893 */ 894 struct ionic_rxq_sg_elem { 895 __le64 addr; 896 __le16 len; 897 __le16 rsvd[3]; 898 }; 899 900 /** 901 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 902 * @elems: Scatter-gather elements 903 */ 904 struct ionic_rxq_sg_desc { 905 #define IONIC_RX_MAX_SG_ELEMS 8 906 #define IONIC_RX_SG_DESC_STRIDE 8 907 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 908 }; 909 910 /** 911 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 912 * @status: Status of the command (enum ionic_status_code) 913 * @num_sg_elems: Number of SG elements used by this descriptor 914 * @comp_index: Index in the descriptor ring for which this is the completion 915 * @rss_hash: 32-bit RSS hash 916 * @csum: 16-bit sum of the packet's L2 payload 917 * If the packet's L2 payload is odd length, an extra 918 * zero-value byte is included in the @csum calculation but 919 * not included in @len. 920 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 921 * set. Includes .1p and .1q tags. 922 * @len: Received packet length, in bytes. Excludes FCS. 923 * @csum_calc L2 payload checksum is computed or not 924 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 925 * 926 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 927 * The TCP checksum calculated by the device 928 * matched the checksum in the receive packet's 929 * TCP header. 930 * 931 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 932 * The TCP checksum calculated by the device did 933 * not match the checksum in the receive packet's 934 * TCP header. 935 * 936 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 937 * The UDP checksum calculated by the device 938 * matched the checksum in the receive packet's 939 * UDP header 940 * 941 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 942 * The UDP checksum calculated by the device did 943 * not match the checksum in the receive packet's 944 * UDP header. 945 * 946 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 947 * The IPv4 checksum calculated by the device 948 * matched the checksum in the receive packet's 949 * first IPv4 header. If the receive packet 950 * contains both a tunnel IPv4 header and a 951 * transport IPv4 header, the device validates the 952 * checksum for the both IPv4 headers. 953 * 954 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 955 * The IPv4 checksum calculated by the device did 956 * not match the checksum in the receive packet's 957 * first IPv4 header. If the receive packet 958 * contains both a tunnel IPv4 header and a 959 * transport IPv4 header, the device validates the 960 * checksum for both IP headers. 961 * 962 * IONIC_RXQ_COMP_CSUM_F_VLAN: 963 * The VLAN header was stripped and placed in @vlan_tci. 964 * 965 * IONIC_RXQ_COMP_CSUM_F_CALC: 966 * The checksum was calculated by the device. 967 * 968 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 969 */ 970 struct ionic_rxq_comp { 971 u8 status; 972 u8 num_sg_elems; 973 __le16 comp_index; 974 __le32 rss_hash; 975 __le16 csum; 976 __le16 vlan_tci; 977 __le16 len; 978 u8 csum_flags; 979 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 980 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 981 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 982 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 983 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 984 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 985 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 986 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 987 u8 pkt_type_color; 988 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 989 }; 990 991 enum ionic_pkt_type { 992 IONIC_PKT_TYPE_NON_IP = 0x00, 993 IONIC_PKT_TYPE_IPV4 = 0x01, 994 IONIC_PKT_TYPE_IPV4_TCP = 0x03, 995 IONIC_PKT_TYPE_IPV4_UDP = 0x05, 996 IONIC_PKT_TYPE_IPV6 = 0x08, 997 IONIC_PKT_TYPE_IPV6_TCP = 0x18, 998 IONIC_PKT_TYPE_IPV6_UDP = 0x28, 999 /* below types are only used if encap offloads are enabled on lif */ 1000 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 1001 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 1002 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 1003 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 1004 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 1005 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 1006 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 1007 }; 1008 1009 enum ionic_eth_hw_features { 1010 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1011 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1012 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1013 IONIC_ETH_HW_RX_HASH = BIT(3), 1014 IONIC_ETH_HW_RX_CSUM = BIT(4), 1015 IONIC_ETH_HW_TX_SG = BIT(5), 1016 IONIC_ETH_HW_RX_SG = BIT(6), 1017 IONIC_ETH_HW_TX_CSUM = BIT(7), 1018 IONIC_ETH_HW_TSO = BIT(8), 1019 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1020 IONIC_ETH_HW_TSO_ECN = BIT(10), 1021 IONIC_ETH_HW_TSO_GRE = BIT(11), 1022 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1023 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1024 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1025 IONIC_ETH_HW_TSO_UDP = BIT(15), 1026 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1027 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 1028 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 1029 IONIC_ETH_HW_TSO_GENEVE = BIT(19) 1030 }; 1031 1032 /** 1033 * struct ionic_q_control_cmd - Queue control command 1034 * @opcode: opcode 1035 * @type: Queue type 1036 * @lif_index: LIF index 1037 * @index: Queue index 1038 * @oper: Operation (enum ionic_q_control_oper) 1039 */ 1040 struct ionic_q_control_cmd { 1041 u8 opcode; 1042 u8 type; 1043 __le16 lif_index; 1044 __le32 index; 1045 u8 oper; 1046 u8 rsvd[55]; 1047 }; 1048 1049 typedef struct ionic_admin_comp ionic_q_control_comp; 1050 1051 enum ionic_q_control_oper { 1052 IONIC_Q_DISABLE = 0, 1053 IONIC_Q_ENABLE = 1, 1054 IONIC_Q_HANG_RESET = 2, 1055 }; 1056 1057 /** 1058 * enum ionic_phy_type - Physical connection type 1059 * @IONIC_PHY_TYPE_NONE: No PHY installed 1060 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1061 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1062 */ 1063 enum ionic_phy_type { 1064 IONIC_PHY_TYPE_NONE = 0, 1065 IONIC_PHY_TYPE_COPPER = 1, 1066 IONIC_PHY_TYPE_FIBER = 2, 1067 }; 1068 1069 /** 1070 * enum ionic_xcvr_state - Transceiver status 1071 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1072 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1073 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1074 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1075 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1076 */ 1077 enum ionic_xcvr_state { 1078 IONIC_XCVR_STATE_REMOVED = 0, 1079 IONIC_XCVR_STATE_INSERTED = 1, 1080 IONIC_XCVR_STATE_PENDING = 2, 1081 IONIC_XCVR_STATE_SPROM_READ = 3, 1082 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1083 }; 1084 1085 /** 1086 * enum ionic_xcvr_pid - Supported link modes 1087 */ 1088 enum ionic_xcvr_pid { 1089 IONIC_XCVR_PID_UNKNOWN = 0, 1090 1091 /* CU */ 1092 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1093 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1094 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1095 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1096 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1097 1098 /* Fiber */ 1099 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1100 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1101 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1102 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1103 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1104 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1105 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1106 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1107 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1108 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1109 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1110 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1111 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1112 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1113 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1114 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1115 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1116 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1117 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1118 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1119 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1120 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1121 }; 1122 1123 /** 1124 * enum ionic_port_admin_state - Port config state 1125 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1126 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1127 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1128 */ 1129 enum ionic_port_admin_state { 1130 IONIC_PORT_ADMIN_STATE_NONE = 0, 1131 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1132 IONIC_PORT_ADMIN_STATE_UP = 2, 1133 }; 1134 1135 /** 1136 * enum ionic_port_oper_status - Port operational status 1137 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1138 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1139 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1140 */ 1141 enum ionic_port_oper_status { 1142 IONIC_PORT_OPER_STATUS_NONE = 0, 1143 IONIC_PORT_OPER_STATUS_UP = 1, 1144 IONIC_PORT_OPER_STATUS_DOWN = 2, 1145 }; 1146 1147 /** 1148 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1149 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1150 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1151 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1152 */ 1153 enum ionic_port_fec_type { 1154 IONIC_PORT_FEC_TYPE_NONE = 0, 1155 IONIC_PORT_FEC_TYPE_FC = 1, 1156 IONIC_PORT_FEC_TYPE_RS = 2, 1157 }; 1158 1159 /** 1160 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1161 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1162 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1163 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1164 */ 1165 enum ionic_port_pause_type { 1166 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1167 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1168 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1169 }; 1170 1171 /** 1172 * enum ionic_port_loopback_mode - Loopback modes 1173 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1174 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1175 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1176 */ 1177 enum ionic_port_loopback_mode { 1178 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1179 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1180 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1181 }; 1182 1183 /** 1184 * struct ionic_xcvr_status - Transceiver Status information 1185 * @state: Transceiver status (enum ionic_xcvr_state) 1186 * @phy: Physical connection type (enum ionic_phy_type) 1187 * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1188 * @sprom: Transceiver sprom contents 1189 */ 1190 struct ionic_xcvr_status { 1191 u8 state; 1192 u8 phy; 1193 __le16 pid; 1194 u8 sprom[256]; 1195 }; 1196 1197 /** 1198 * union ionic_port_config - Port configuration 1199 * @speed: port speed (in Mbps) 1200 * @mtu: mtu 1201 * @state: port admin state (enum ionic_port_admin_state) 1202 * @an_enable: autoneg enable 1203 * @fec_type: fec type (enum ionic_port_fec_type) 1204 * @pause_type: pause type (enum ionic_port_pause_type) 1205 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1206 */ 1207 union ionic_port_config { 1208 struct { 1209 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1210 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1211 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1212 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1213 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1214 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1215 __le32 speed; 1216 __le32 mtu; 1217 u8 state; 1218 u8 an_enable; 1219 u8 fec_type; 1220 #define IONIC_PAUSE_TYPE_MASK 0x0f 1221 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1222 #define IONIC_PAUSE_F_TX 0x10 1223 #define IONIC_PAUSE_F_RX 0x20 1224 u8 pause_type; 1225 u8 loopback_mode; 1226 }; 1227 __le32 words[64]; 1228 }; 1229 1230 /** 1231 * struct ionic_port_status - Port Status information 1232 * @status: link status (enum ionic_port_oper_status) 1233 * @id: port id 1234 * @speed: link speed (in Mbps) 1235 * @link_down_count: number of times link went from up to down 1236 * @fec_type: fec type (enum ionic_port_fec_type) 1237 * @xcvr: transceiver status 1238 */ 1239 struct __rte_packed_begin ionic_port_status { 1240 __le32 id; 1241 __le32 speed; 1242 u8 status; 1243 __le16 link_down_count; 1244 u8 fec_type; 1245 u8 rsvd[48]; 1246 struct ionic_xcvr_status xcvr; 1247 } __rte_packed_end; 1248 1249 /** 1250 * struct ionic_port_identify_cmd - Port identify command 1251 * @opcode: opcode 1252 * @index: port index 1253 * @ver: Highest version of identify supported by driver 1254 */ 1255 struct ionic_port_identify_cmd { 1256 u8 opcode; 1257 u8 index; 1258 u8 ver; 1259 u8 rsvd[61]; 1260 }; 1261 1262 /** 1263 * struct ionic_port_identify_comp - Port identify command completion 1264 * @status: Status of the command (enum ionic_status_code) 1265 * @ver: Version of identify returned by device 1266 */ 1267 struct ionic_port_identify_comp { 1268 u8 status; 1269 u8 ver; 1270 u8 rsvd[14]; 1271 }; 1272 1273 /** 1274 * struct ionic_port_init_cmd - Port initialization command 1275 * @opcode: opcode 1276 * @index: port index 1277 * @info_pa: destination address for port info (struct ionic_port_info) 1278 */ 1279 struct ionic_port_init_cmd { 1280 u8 opcode; 1281 u8 index; 1282 u8 rsvd[6]; 1283 __le64 info_pa; 1284 u8 rsvd2[48]; 1285 }; 1286 1287 /** 1288 * struct ionic_port_init_comp - Port initialization command completion 1289 * @status: Status of the command (enum ionic_status_code) 1290 */ 1291 struct ionic_port_init_comp { 1292 u8 status; 1293 u8 rsvd[15]; 1294 }; 1295 1296 /** 1297 * struct ionic_port_reset_cmd - Port reset command 1298 * @opcode: opcode 1299 * @index: port index 1300 */ 1301 struct ionic_port_reset_cmd { 1302 u8 opcode; 1303 u8 index; 1304 u8 rsvd[62]; 1305 }; 1306 1307 /** 1308 * struct ionic_port_reset_comp - Port reset command completion 1309 * @status: Status of the command (enum ionic_status_code) 1310 */ 1311 struct ionic_port_reset_comp { 1312 u8 status; 1313 u8 rsvd[15]; 1314 }; 1315 1316 /** 1317 * enum ionic_stats_ctl_cmd - List of commands for stats control 1318 * @IONIC_STATS_CTL_RESET: Reset statistics 1319 */ 1320 enum ionic_stats_ctl_cmd { 1321 IONIC_STATS_CTL_RESET = 0, 1322 }; 1323 1324 /** 1325 * enum ionic_port_attr - List of device attributes 1326 * @IONIC_PORT_ATTR_STATE: Port state attribute 1327 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1328 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1329 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute 1330 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1331 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1332 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1333 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1334 */ 1335 enum ionic_port_attr { 1336 IONIC_PORT_ATTR_STATE = 0, 1337 IONIC_PORT_ATTR_SPEED = 1, 1338 IONIC_PORT_ATTR_MTU = 2, 1339 IONIC_PORT_ATTR_AUTONEG = 3, 1340 IONIC_PORT_ATTR_FEC = 4, 1341 IONIC_PORT_ATTR_PAUSE = 5, 1342 IONIC_PORT_ATTR_LOOPBACK = 6, 1343 IONIC_PORT_ATTR_STATS_CTRL = 7, 1344 }; 1345 1346 /** 1347 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1348 * @opcode: Opcode 1349 * @index: Port index 1350 * @attr: Attribute type (enum ionic_port_attr) 1351 * @state: Port state 1352 * @speed: Port speed 1353 * @mtu: Port MTU 1354 * @an_enable: Port autonegotiation setting 1355 * @fec_type: Port FEC type setting 1356 * @pause_type: Port pause type setting 1357 * @loopback_mode: Port loopback mode 1358 * @stats_ctl: Port stats setting 1359 */ 1360 struct ionic_port_setattr_cmd { 1361 u8 opcode; 1362 u8 index; 1363 u8 attr; 1364 u8 rsvd; 1365 union { 1366 u8 state; 1367 __le32 speed; 1368 __le32 mtu; 1369 u8 an_enable; 1370 u8 fec_type; 1371 u8 pause_type; 1372 u8 loopback_mode; 1373 u8 stats_ctl; 1374 u8 rsvd2[60]; 1375 }; 1376 }; 1377 1378 /** 1379 * struct ionic_port_setattr_comp - Port set attr command completion 1380 * @status: Status of the command (enum ionic_status_code) 1381 * @color: Color bit 1382 */ 1383 struct ionic_port_setattr_comp { 1384 u8 status; 1385 u8 rsvd[14]; 1386 u8 color; 1387 }; 1388 1389 /** 1390 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1391 * @opcode: Opcode 1392 * @index: port index 1393 * @attr: Attribute type (enum ionic_port_attr) 1394 */ 1395 struct ionic_port_getattr_cmd { 1396 u8 opcode; 1397 u8 index; 1398 u8 attr; 1399 u8 rsvd[61]; 1400 }; 1401 1402 /** 1403 * struct ionic_port_getattr_comp - Port get attr command completion 1404 * @status: Status of the command (enum ionic_status_code) 1405 * @state: Port state 1406 * @speed: Port speed 1407 * @mtu: Port MTU 1408 * @an_enable: Port autonegotiation setting 1409 * @fec_type: Port FEC type setting 1410 * @pause_type: Port pause type setting 1411 * @loopback_mode: Port loopback mode 1412 * @color: Color bit 1413 */ 1414 struct ionic_port_getattr_comp { 1415 u8 status; 1416 u8 rsvd[3]; 1417 union __rte_packed_begin { 1418 u8 state; 1419 __le32 speed; 1420 __le32 mtu; 1421 u8 an_enable; 1422 u8 fec_type; 1423 u8 pause_type; 1424 u8 loopback_mode; 1425 u8 rsvd2[11]; 1426 } __rte_packed_end; 1427 u8 color; 1428 }; 1429 1430 /** 1431 * struct ionic_lif_status - LIF status register 1432 * @eid: most recent NotifyQ event id 1433 * @port_num: port the LIF is connected to 1434 * @link_status: port status (enum ionic_port_oper_status) 1435 * @link_speed: speed of link in Mbps 1436 * @link_down_count: number of times link went from up to down 1437 */ 1438 struct ionic_lif_status { 1439 __le64 eid; 1440 u8 port_num; 1441 u8 rsvd; 1442 __le16 link_status; 1443 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1444 __le16 link_down_count; 1445 u8 rsvd2[46]; 1446 }; 1447 1448 /** 1449 * struct ionic_lif_reset_cmd - LIF reset command 1450 * @opcode: opcode 1451 * @index: LIF index 1452 */ 1453 struct ionic_lif_reset_cmd { 1454 u8 opcode; 1455 u8 rsvd; 1456 __le16 index; 1457 __le32 rsvd2[15]; 1458 }; 1459 1460 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1461 1462 enum ionic_dev_state { 1463 IONIC_DEV_DISABLE = 0, 1464 IONIC_DEV_ENABLE = 1, 1465 IONIC_DEV_HANG_RESET = 2, 1466 }; 1467 1468 /** 1469 * enum ionic_dev_attr - List of device attributes 1470 * @IONIC_DEV_ATTR_STATE: Device state attribute 1471 * @IONIC_DEV_ATTR_NAME: Device name attribute 1472 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1473 */ 1474 enum ionic_dev_attr { 1475 IONIC_DEV_ATTR_STATE = 0, 1476 IONIC_DEV_ATTR_NAME = 1, 1477 IONIC_DEV_ATTR_FEATURES = 2, 1478 }; 1479 1480 /** 1481 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1482 * @opcode: Opcode 1483 * @attr: Attribute type (enum ionic_dev_attr) 1484 * @state: Device state (enum ionic_dev_state) 1485 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1486 * @features: Device features 1487 */ 1488 struct ionic_dev_setattr_cmd { 1489 u8 opcode; 1490 u8 attr; 1491 __le16 rsvd; 1492 union __rte_packed_begin { 1493 u8 state; 1494 char name[IONIC_IFNAMSIZ]; 1495 __le64 features; 1496 u8 rsvd2[60]; 1497 } __rte_packed_end; 1498 }; 1499 1500 /** 1501 * struct ionic_dev_setattr_comp - Device set attr command completion 1502 * @status: Status of the command (enum ionic_status_code) 1503 * @features: Device features 1504 * @color: Color bit 1505 */ 1506 struct ionic_dev_setattr_comp { 1507 u8 status; 1508 u8 rsvd[3]; 1509 union __rte_packed_begin { 1510 __le64 features; 1511 u8 rsvd2[11]; 1512 } __rte_packed_end; 1513 u8 color; 1514 }; 1515 1516 /** 1517 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1518 * @opcode: opcode 1519 * @attr: Attribute type (enum ionic_dev_attr) 1520 */ 1521 struct ionic_dev_getattr_cmd { 1522 u8 opcode; 1523 u8 attr; 1524 u8 rsvd[62]; 1525 }; 1526 1527 /** 1528 * struct ionic_dev_setattr_comp - Device set attr command completion 1529 * @status: Status of the command (enum ionic_status_code) 1530 * @features: Device features 1531 * @color: Color bit 1532 */ 1533 struct ionic_dev_getattr_comp { 1534 u8 status; 1535 u8 rsvd[3]; 1536 union __rte_packed_begin { 1537 __le64 features; 1538 u8 rsvd2[11]; 1539 } __rte_packed_end; 1540 u8 color; 1541 }; 1542 1543 /** 1544 * RSS parameters 1545 */ 1546 #define IONIC_RSS_HASH_KEY_SIZE 40 1547 1548 enum ionic_rss_hash_types { 1549 IONIC_RSS_TYPE_IPV4 = BIT(0), 1550 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1551 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1552 IONIC_RSS_TYPE_IPV6 = BIT(3), 1553 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1554 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1555 }; 1556 1557 /** 1558 * enum ionic_lif_attr - List of LIF attributes 1559 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1560 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1561 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1562 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1563 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1564 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1565 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1566 */ 1567 enum ionic_lif_attr { 1568 IONIC_LIF_ATTR_STATE = 0, 1569 IONIC_LIF_ATTR_NAME = 1, 1570 IONIC_LIF_ATTR_MTU = 2, 1571 IONIC_LIF_ATTR_MAC = 3, 1572 IONIC_LIF_ATTR_FEATURES = 4, 1573 IONIC_LIF_ATTR_RSS = 5, 1574 IONIC_LIF_ATTR_STATS_CTRL = 6, 1575 }; 1576 1577 /** 1578 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1579 * @opcode: Opcode 1580 * @attr: Attribute type (enum ionic_lif_attr) 1581 * @index: LIF index 1582 * @state: LIF state (enum ionic_lif_state) 1583 * @name: The netdev name string, 0 terminated 1584 * @mtu: Mtu 1585 * @mac: Station mac 1586 * @features: Features (enum ionic_eth_hw_features) 1587 * @rss: RSS properties 1588 * @types: The hash types to enable (see rss_hash_types) 1589 * @key: The hash secret key 1590 * @addr: Address for the indirection table shared memory 1591 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1592 */ 1593 struct ionic_lif_setattr_cmd { 1594 u8 opcode; 1595 u8 attr; 1596 __le16 index; 1597 union __rte_packed_begin { 1598 u8 state; 1599 char name[IONIC_IFNAMSIZ]; 1600 __le32 mtu; 1601 u8 mac[6]; 1602 __le64 features; 1603 struct { 1604 __le16 types; 1605 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1606 u8 rsvd[6]; 1607 __le64 addr; 1608 } rss; 1609 u8 stats_ctl; 1610 u8 rsvd[60]; 1611 } __rte_packed_end; 1612 }; 1613 1614 /** 1615 * struct ionic_lif_setattr_comp - LIF set attr command completion 1616 * @status: Status of the command (enum ionic_status_code) 1617 * @comp_index: Index in the descriptor ring for which this is the completion 1618 * @features: features (enum ionic_eth_hw_features) 1619 * @color: Color bit 1620 */ 1621 struct ionic_lif_setattr_comp { 1622 u8 status; 1623 u8 rsvd; 1624 __le16 comp_index; 1625 union __rte_packed_begin { 1626 __le64 features; 1627 u8 rsvd2[11]; 1628 } __rte_packed_end; 1629 u8 color; 1630 }; 1631 1632 /** 1633 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1634 * @opcode: Opcode 1635 * @attr: Attribute type (enum ionic_lif_attr) 1636 * @index: LIF index 1637 */ 1638 struct ionic_lif_getattr_cmd { 1639 u8 opcode; 1640 u8 attr; 1641 __le16 index; 1642 u8 rsvd[60]; 1643 }; 1644 1645 /** 1646 * struct ionic_lif_getattr_comp - LIF get attr command completion 1647 * @status: Status of the command (enum ionic_status_code) 1648 * @comp_index: Index in the descriptor ring for which this is the completion 1649 * @state: LIF state (enum ionic_lif_state) 1650 * @name: The netdev name string, 0 terminated 1651 * @mtu: Mtu 1652 * @mac: Station mac 1653 * @features: Features (enum ionic_eth_hw_features) 1654 * @color: Color bit 1655 */ 1656 struct ionic_lif_getattr_comp { 1657 u8 status; 1658 u8 rsvd; 1659 __le16 comp_index; 1660 union __rte_packed_begin { 1661 u8 state; 1662 __le32 mtu; 1663 u8 mac[6]; 1664 __le64 features; 1665 u8 rsvd2[11]; 1666 } __rte_packed_end; 1667 u8 color; 1668 }; 1669 1670 enum ionic_rx_mode { 1671 IONIC_RX_MODE_F_UNICAST = BIT(0), 1672 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1673 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1674 IONIC_RX_MODE_F_PROMISC = BIT(3), 1675 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1676 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 1677 }; 1678 1679 /** 1680 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1681 * @opcode: opcode 1682 * @lif_index: LIF index 1683 * @rx_mode: Rx mode flags: 1684 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 1685 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 1686 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 1687 * IONIC_RX_MODE_F_PROMISC: Accept any packets 1688 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 1689 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 1690 */ 1691 struct ionic_rx_mode_set_cmd { 1692 u8 opcode; 1693 u8 rsvd; 1694 __le16 lif_index; 1695 __le16 rx_mode; 1696 __le16 rsvd2[29]; 1697 }; 1698 1699 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1700 1701 enum ionic_rx_filter_match_type { 1702 IONIC_RX_FILTER_MATCH_VLAN = 0, 1703 IONIC_RX_FILTER_MATCH_MAC, 1704 IONIC_RX_FILTER_MATCH_MAC_VLAN, 1705 }; 1706 1707 /** 1708 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 1709 * @opcode: opcode 1710 * @qtype: Queue type 1711 * @lif_index: LIF index 1712 * @qid: Queue ID 1713 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 1714 * @vlan: VLAN filter 1715 * @vlan: VLAN ID 1716 * @mac: MAC filter 1717 * @addr: MAC address (network-byte order) 1718 * @mac_vlan: MACVLAN filter 1719 * @vlan: VLAN ID 1720 * @addr: MAC address (network-byte order) 1721 */ 1722 struct ionic_rx_filter_add_cmd { 1723 u8 opcode; 1724 u8 qtype; 1725 __le16 lif_index; 1726 __le32 qid; 1727 __le16 match; 1728 union { 1729 struct { 1730 __le16 vlan; 1731 } vlan; 1732 struct { 1733 u8 addr[6]; 1734 } mac; 1735 struct { 1736 __le16 vlan; 1737 u8 addr[6]; 1738 } mac_vlan; 1739 u8 rsvd[54]; 1740 }; 1741 }; 1742 1743 /** 1744 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 1745 * @status: Status of the command (enum ionic_status_code) 1746 * @comp_index: Index in the descriptor ring for which this is the completion 1747 * @filter_id: Filter ID 1748 * @color: Color bit 1749 */ 1750 struct ionic_rx_filter_add_comp { 1751 u8 status; 1752 u8 rsvd; 1753 __le16 comp_index; 1754 __le32 filter_id; 1755 u8 rsvd2[7]; 1756 u8 color; 1757 }; 1758 1759 /** 1760 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 1761 * @opcode: opcode 1762 * @lif_index: LIF index 1763 * @filter_id: Filter ID 1764 */ 1765 struct ionic_rx_filter_del_cmd { 1766 u8 opcode; 1767 u8 rsvd; 1768 __le16 lif_index; 1769 __le32 filter_id; 1770 u8 rsvd2[56]; 1771 }; 1772 1773 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 1774 1775 enum ionic_vf_attr { 1776 IONIC_VF_ATTR_SPOOFCHK = 1, 1777 IONIC_VF_ATTR_TRUST = 2, 1778 IONIC_VF_ATTR_MAC = 3, 1779 IONIC_VF_ATTR_LINKSTATE = 4, 1780 IONIC_VF_ATTR_VLAN = 5, 1781 IONIC_VF_ATTR_RATE = 6, 1782 IONIC_VF_ATTR_STATSADDR = 7, 1783 }; 1784 1785 /** 1786 * enum ionic_vf_link_status - Virtual Function link status 1787 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 1788 * @IONIC_VF_LINK_STATUS_UP: Link always up 1789 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 1790 */ 1791 enum ionic_vf_link_status { 1792 IONIC_VF_LINK_STATUS_AUTO = 0, 1793 IONIC_VF_LINK_STATUS_UP = 1, 1794 IONIC_VF_LINK_STATUS_DOWN = 2, 1795 }; 1796 1797 /** 1798 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 1799 * @opcode: Opcode 1800 * @attr: Attribute type (enum ionic_vf_attr) 1801 * @vf_index: VF index 1802 * @macaddr: mac address 1803 * @vlanid: vlan ID 1804 * @maxrate: max Tx rate in Mbps 1805 * @spoofchk: enable address spoof checking 1806 * @trust: enable VF trust 1807 * @linkstate: set link up or down 1808 * @stats_pa: set DMA address for VF stats 1809 */ 1810 struct ionic_vf_setattr_cmd { 1811 u8 opcode; 1812 u8 attr; 1813 __le16 vf_index; 1814 union __rte_packed_begin { 1815 u8 macaddr[6]; 1816 __le16 vlanid; 1817 __le32 maxrate; 1818 u8 spoofchk; 1819 u8 trust; 1820 u8 linkstate; 1821 __le64 stats_pa; 1822 u8 pad[60]; 1823 } __rte_packed_end; 1824 }; 1825 1826 struct ionic_vf_setattr_comp { 1827 u8 status; 1828 u8 attr; 1829 __le16 vf_index; 1830 __le16 comp_index; 1831 u8 rsvd[9]; 1832 u8 color; 1833 }; 1834 1835 /** 1836 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 1837 * @opcode: Opcode 1838 * @attr: Attribute type (enum ionic_vf_attr) 1839 * @vf_index: VF index 1840 */ 1841 struct ionic_vf_getattr_cmd { 1842 u8 opcode; 1843 u8 attr; 1844 __le16 vf_index; 1845 u8 rsvd[60]; 1846 }; 1847 1848 struct ionic_vf_getattr_comp { 1849 u8 status; 1850 u8 attr; 1851 __le16 vf_index; 1852 union __rte_packed_begin { 1853 u8 macaddr[6]; 1854 __le16 vlanid; 1855 __le32 maxrate; 1856 u8 spoofchk; 1857 u8 trust; 1858 u8 linkstate; 1859 __le64 stats_pa; 1860 u8 pad[11]; 1861 } __rte_packed_end; 1862 u8 color; 1863 }; 1864 1865 /** 1866 * struct ionic_qos_identify_cmd - QoS identify command 1867 * @opcode: opcode 1868 * @ver: Highest version of identify supported by driver 1869 * 1870 */ 1871 struct ionic_qos_identify_cmd { 1872 u8 opcode; 1873 u8 ver; 1874 u8 rsvd[62]; 1875 }; 1876 1877 /** 1878 * struct ionic_qos_identify_comp - QoS identify command completion 1879 * @status: Status of the command (enum ionic_status_code) 1880 * @ver: Version of identify returned by device 1881 */ 1882 struct ionic_qos_identify_comp { 1883 u8 status; 1884 u8 ver; 1885 u8 rsvd[14]; 1886 }; 1887 1888 #define IONIC_QOS_TC_MAX 8 1889 #define IONIC_QOS_ALL_TC 0xFF 1890 /* Capri max supported, should be renamed. */ 1891 #define IONIC_QOS_CLASS_MAX 7 1892 #define IONIC_QOS_PCP_MAX 8 1893 #define IONIC_QOS_CLASS_NAME_SZ 32 1894 #define IONIC_QOS_DSCP_MAX 64 1895 #define IONIC_QOS_ALL_PCP 0xFF 1896 #define IONIC_DSCP_BLOCK_SIZE 8 1897 1898 /** 1899 * enum ionic_qos_class 1900 */ 1901 enum ionic_qos_class { 1902 IONIC_QOS_CLASS_DEFAULT = 0, 1903 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 1904 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 1905 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 1906 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 1907 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 1908 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 1909 }; 1910 1911 /** 1912 * enum ionic_qos_class_type - Traffic classification criteria 1913 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 1914 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 1915 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 1916 */ 1917 enum ionic_qos_class_type { 1918 IONIC_QOS_CLASS_TYPE_NONE = 0, 1919 IONIC_QOS_CLASS_TYPE_PCP = 1, 1920 IONIC_QOS_CLASS_TYPE_DSCP = 2, 1921 }; 1922 1923 /** 1924 * enum ionic_qos_sched_type - QoS class scheduling type 1925 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 1926 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 1927 */ 1928 enum ionic_qos_sched_type { 1929 IONIC_QOS_SCHED_TYPE_STRICT = 0, 1930 IONIC_QOS_SCHED_TYPE_DWRR = 1, 1931 }; 1932 1933 /** 1934 * union ionic_qos_config - QoS configuration structure 1935 * @flags: Configuration flags 1936 * IONIC_QOS_CONFIG_F_ENABLE enable 1937 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 1938 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 1939 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 1940 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 1941 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 1942 * @class_type: QoS class type (enum ionic_qos_class_type) 1943 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 1944 * @name: QoS class name 1945 * @mtu: MTU of the class 1946 * @pfc_cos: Priority-Flow Control class of service 1947 * @dwrr_weight: QoS class scheduling weight 1948 * @strict_rlmt: Rate limit for strict priority scheduling 1949 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) 1950 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) 1951 * @dot1q_pcp: Dot1q pcp value 1952 * @ndscp: Number of valid dscp values in the ip_dscp field 1953 * @ip_dscp: IP dscp values 1954 */ 1955 union ionic_qos_config { 1956 struct __rte_packed_begin { 1957 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 1958 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 1959 /* Used to rewrite PCP or DSCP value. */ 1960 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 1961 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 1962 /* Non-disruptive TC update */ 1963 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 1964 u8 flags; 1965 u8 sched_type; 1966 u8 class_type; 1967 u8 pause_type; 1968 char name[IONIC_QOS_CLASS_NAME_SZ]; 1969 __le32 mtu; 1970 /* flow control */ 1971 u8 pfc_cos; 1972 /* scheduler */ 1973 union { 1974 u8 dwrr_weight; 1975 __le64 strict_rlmt; 1976 }; 1977 /* marking */ 1978 /* Used to rewrite PCP or DSCP value. */ 1979 union { 1980 u8 rw_dot1q_pcp; 1981 u8 rw_ip_dscp; 1982 }; 1983 /* classification */ 1984 union { 1985 u8 dot1q_pcp; 1986 struct { 1987 u8 ndscp; 1988 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 1989 }; 1990 }; 1991 } __rte_packed_end; 1992 __le32 words[64]; 1993 }; 1994 1995 /** 1996 * union ionic_qos_identity - QoS identity structure 1997 * @version: Version of the identify structure 1998 * @type: QoS system type 1999 * @nclasses: Number of usable QoS classes 2000 * @config: Current configuration of classes 2001 */ 2002 union ionic_qos_identity { 2003 struct { 2004 u8 version; 2005 u8 type; 2006 u8 rsvd[62]; 2007 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2008 }; 2009 __le32 words[478]; 2010 }; 2011 2012 /** 2013 * struct ionic_qos_init_cmd - QoS config init command 2014 * @opcode: Opcode 2015 * @group: QoS class id 2016 * @info_pa: destination address for qos info 2017 */ 2018 struct ionic_qos_init_cmd { 2019 u8 opcode; 2020 u8 group; 2021 u8 rsvd[6]; 2022 __le64 info_pa; 2023 u8 rsvd1[48]; 2024 }; 2025 2026 typedef struct ionic_admin_comp ionic_qos_init_comp; 2027 2028 /** 2029 * struct ionic_qos_reset_cmd - QoS config reset command 2030 * @opcode: Opcode 2031 * @group: QoS class id 2032 */ 2033 struct ionic_qos_reset_cmd { 2034 u8 opcode; 2035 u8 group; 2036 u8 rsvd[62]; 2037 }; 2038 2039 /** 2040 * struct ionic_qos_clear_port_stats_cmd - Qos config reset command 2041 * @opcode: Opcode 2042 */ 2043 struct ionic_qos_clear_stats_cmd { 2044 u8 opcode; 2045 u8 group_bitmap; 2046 u8 rsvd[62]; 2047 }; 2048 2049 typedef struct ionic_admin_comp ionic_qos_reset_comp; 2050 2051 /** 2052 * struct ionic_fw_download_cmd - Firmware download command 2053 * @opcode: opcode 2054 * @addr: dma address of the firmware buffer 2055 * @offset: offset of the firmware buffer within the full image 2056 * @length: number of valid bytes in the firmware buffer 2057 */ 2058 struct ionic_fw_download_cmd { 2059 u8 opcode; 2060 u8 rsvd[3]; 2061 __le32 offset; 2062 __le64 addr; 2063 __le32 length; 2064 }; 2065 2066 typedef struct ionic_admin_comp ionic_fw_download_comp; 2067 2068 /** 2069 * enum ionic_fw_control_oper - FW control operations 2070 * @IONIC_FW_RESET: Reset firmware 2071 * @IONIC_FW_INSTALL: Install firmware 2072 * @IONIC_FW_ACTIVATE: Activate firmware 2073 */ 2074 enum ionic_fw_control_oper { 2075 IONIC_FW_RESET = 0, 2076 IONIC_FW_INSTALL = 1, 2077 IONIC_FW_ACTIVATE = 2, 2078 }; 2079 2080 /** 2081 * struct ionic_fw_control_cmd - Firmware control command 2082 * @opcode: opcode 2083 * @oper: firmware control operation (enum ionic_fw_control_oper) 2084 * @slot: slot to activate 2085 */ 2086 struct ionic_fw_control_cmd { 2087 u8 opcode; 2088 u8 rsvd[3]; 2089 u8 oper; 2090 u8 slot; 2091 u8 rsvd1[58]; 2092 }; 2093 2094 /** 2095 * struct ionic_fw_control_comp - Firmware control completion 2096 * @status: Status of the command (enum ionic_status_code) 2097 * @comp_index: Index in the descriptor ring for which this is the completion 2098 * @slot: Slot where the firmware was installed 2099 * @color: Color bit 2100 */ 2101 struct ionic_fw_control_comp { 2102 u8 status; 2103 u8 rsvd; 2104 __le16 comp_index; 2105 u8 slot; 2106 u8 rsvd1[10]; 2107 u8 color; 2108 }; 2109 2110 /****************************************************************** 2111 ******************* RDMA Commands ******************************** 2112 ******************************************************************/ 2113 2114 /** 2115 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2116 * @opcode: opcode 2117 * @lif_index: LIF index 2118 * 2119 * There is no RDMA specific dev command completion struct. Completion uses 2120 * the common struct ionic_admin_comp. Only the status is indicated. 2121 * Nonzero status means the LIF does not support RDMA. 2122 **/ 2123 struct ionic_rdma_reset_cmd { 2124 u8 opcode; 2125 u8 rsvd; 2126 __le16 lif_index; 2127 u8 rsvd2[60]; 2128 }; 2129 2130 /** 2131 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2132 * @opcode: opcode, 52, 53 2133 * @lif_index: LIF index 2134 * @qid_ver: (qid | (RDMA version << 24)) 2135 * @cid: intr, eq_id, or cq_id 2136 * @dbid: doorbell page id 2137 * @depth_log2: log base two of queue depth 2138 * @stride_log2: log base two of queue stride 2139 * @dma_addr: address of the queue memory 2140 * 2141 * The same command struct is used to create an RDMA event queue, completion 2142 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2143 * queue, an event queue id for a completion queue, or a completion queue id 2144 * for an RDMA admin queue. 2145 * 2146 * The queue created via a dev command must be contiguous in dma space. 2147 * 2148 * The dev commands are intended only to be used during driver initialization, 2149 * to create queues supporting the RDMA admin queue. Other queues, and other 2150 * types of RDMA resources like memory regions, will be created and registered 2151 * via the RDMA admin queue, and will support a more complete interface 2152 * providing scatter gather lists for larger, scattered queue buffers and 2153 * memory registration. 2154 * 2155 * There is no RDMA specific dev command completion struct. Completion uses 2156 * the common struct ionic_admin_comp. Only the status is indicated. 2157 **/ 2158 struct ionic_rdma_queue_cmd { 2159 u8 opcode; 2160 u8 rsvd; 2161 __le16 lif_index; 2162 __le32 qid_ver; 2163 __le32 cid; 2164 __le16 dbid; 2165 u8 depth_log2; 2166 u8 stride_log2; 2167 __le64 dma_addr; 2168 u8 rsvd2[40]; 2169 }; 2170 2171 /****************************************************************** 2172 ******************* Notify Events ******************************** 2173 ******************************************************************/ 2174 2175 /** 2176 * struct ionic_notifyq_event - Generic event reporting structure 2177 * @eid: event number 2178 * @ecode: event code 2179 * @data: unspecified data about the event 2180 * 2181 * This is the generic event report struct from which the other 2182 * actual events will be formed. 2183 */ 2184 struct ionic_notifyq_event { 2185 __le64 eid; 2186 __le16 ecode; 2187 u8 data[54]; 2188 }; 2189 2190 /** 2191 * struct ionic_link_change_event - Link change event notification 2192 * @eid: event number 2193 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2194 * @link_status: link up/down, with error bits (enum ionic_port_status) 2195 * @link_speed: speed of the network link 2196 * 2197 * Sent when the network link state changes between UP and DOWN 2198 */ 2199 struct ionic_link_change_event { 2200 __le64 eid; 2201 __le16 ecode; 2202 __le16 link_status; 2203 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2204 u8 rsvd[48]; 2205 }; 2206 2207 /** 2208 * struct ionic_reset_event - Reset event notification 2209 * @eid: event number 2210 * @ecode: event code = IONIC_EVENT_RESET 2211 * @reset_code: reset type 2212 * @state: 0=pending, 1=complete, 2=error 2213 * 2214 * Sent when the NIC or some subsystem is going to be or 2215 * has been reset. 2216 */ 2217 struct ionic_reset_event { 2218 __le64 eid; 2219 __le16 ecode; 2220 u8 reset_code; 2221 u8 state; 2222 u8 rsvd[52]; 2223 }; 2224 2225 /** 2226 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2227 * @eid: event number 2228 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2229 */ 2230 struct ionic_heartbeat_event { 2231 __le64 eid; 2232 __le16 ecode; 2233 u8 rsvd[54]; 2234 }; 2235 2236 /** 2237 * struct ionic_log_event - Sent to notify the driver of an internal error 2238 * @eid: event number 2239 * @ecode: event code = IONIC_EVENT_LOG 2240 * @data: log data 2241 */ 2242 struct ionic_log_event { 2243 __le64 eid; 2244 __le16 ecode; 2245 u8 data[54]; 2246 }; 2247 2248 /** 2249 * struct ionic_xcvr_event - Transceiver change event 2250 * @eid: event number 2251 * @ecode: event code = IONIC_EVENT_XCVR 2252 */ 2253 struct ionic_xcvr_event { 2254 __le64 eid; 2255 __le16 ecode; 2256 u8 rsvd[54]; 2257 }; 2258 2259 /** 2260 * struct ionic_port_stats - Port statistics structure 2261 */ 2262 struct ionic_port_stats { 2263 __le64 frames_rx_ok; 2264 __le64 frames_rx_all; 2265 __le64 frames_rx_bad_fcs; 2266 __le64 frames_rx_bad_all; 2267 __le64 octets_rx_ok; 2268 __le64 octets_rx_all; 2269 __le64 frames_rx_unicast; 2270 __le64 frames_rx_multicast; 2271 __le64 frames_rx_broadcast; 2272 __le64 frames_rx_pause; 2273 __le64 frames_rx_bad_length; 2274 __le64 frames_rx_undersized; 2275 __le64 frames_rx_oversized; 2276 __le64 frames_rx_fragments; 2277 __le64 frames_rx_jabber; 2278 __le64 frames_rx_pripause; 2279 __le64 frames_rx_stomped_crc; 2280 __le64 frames_rx_too_long; 2281 __le64 frames_rx_vlan_good; 2282 __le64 frames_rx_dropped; 2283 __le64 frames_rx_less_than_64b; 2284 __le64 frames_rx_64b; 2285 __le64 frames_rx_65b_127b; 2286 __le64 frames_rx_128b_255b; 2287 __le64 frames_rx_256b_511b; 2288 __le64 frames_rx_512b_1023b; 2289 __le64 frames_rx_1024b_1518b; 2290 __le64 frames_rx_1519b_2047b; 2291 __le64 frames_rx_2048b_4095b; 2292 __le64 frames_rx_4096b_8191b; 2293 __le64 frames_rx_8192b_9215b; 2294 __le64 frames_rx_other; 2295 __le64 frames_tx_ok; 2296 __le64 frames_tx_all; 2297 __le64 frames_tx_bad; 2298 __le64 octets_tx_ok; 2299 __le64 octets_tx_total; 2300 __le64 frames_tx_unicast; 2301 __le64 frames_tx_multicast; 2302 __le64 frames_tx_broadcast; 2303 __le64 frames_tx_pause; 2304 __le64 frames_tx_pripause; 2305 __le64 frames_tx_vlan; 2306 __le64 frames_tx_less_than_64b; 2307 __le64 frames_tx_64b; 2308 __le64 frames_tx_65b_127b; 2309 __le64 frames_tx_128b_255b; 2310 __le64 frames_tx_256b_511b; 2311 __le64 frames_tx_512b_1023b; 2312 __le64 frames_tx_1024b_1518b; 2313 __le64 frames_tx_1519b_2047b; 2314 __le64 frames_tx_2048b_4095b; 2315 __le64 frames_tx_4096b_8191b; 2316 __le64 frames_tx_8192b_9215b; 2317 __le64 frames_tx_other; 2318 __le64 frames_tx_pri_0; 2319 __le64 frames_tx_pri_1; 2320 __le64 frames_tx_pri_2; 2321 __le64 frames_tx_pri_3; 2322 __le64 frames_tx_pri_4; 2323 __le64 frames_tx_pri_5; 2324 __le64 frames_tx_pri_6; 2325 __le64 frames_tx_pri_7; 2326 __le64 frames_rx_pri_0; 2327 __le64 frames_rx_pri_1; 2328 __le64 frames_rx_pri_2; 2329 __le64 frames_rx_pri_3; 2330 __le64 frames_rx_pri_4; 2331 __le64 frames_rx_pri_5; 2332 __le64 frames_rx_pri_6; 2333 __le64 frames_rx_pri_7; 2334 __le64 tx_pripause_0_1us_count; 2335 __le64 tx_pripause_1_1us_count; 2336 __le64 tx_pripause_2_1us_count; 2337 __le64 tx_pripause_3_1us_count; 2338 __le64 tx_pripause_4_1us_count; 2339 __le64 tx_pripause_5_1us_count; 2340 __le64 tx_pripause_6_1us_count; 2341 __le64 tx_pripause_7_1us_count; 2342 __le64 rx_pripause_0_1us_count; 2343 __le64 rx_pripause_1_1us_count; 2344 __le64 rx_pripause_2_1us_count; 2345 __le64 rx_pripause_3_1us_count; 2346 __le64 rx_pripause_4_1us_count; 2347 __le64 rx_pripause_5_1us_count; 2348 __le64 rx_pripause_6_1us_count; 2349 __le64 rx_pripause_7_1us_count; 2350 __le64 rx_pause_1us_count; 2351 __le64 frames_tx_truncated; 2352 }; 2353 2354 struct ionic_mgmt_port_stats { 2355 __le64 frames_rx_ok; 2356 __le64 frames_rx_all; 2357 __le64 frames_rx_bad_fcs; 2358 __le64 frames_rx_bad_all; 2359 __le64 octets_rx_ok; 2360 __le64 octets_rx_all; 2361 __le64 frames_rx_unicast; 2362 __le64 frames_rx_multicast; 2363 __le64 frames_rx_broadcast; 2364 __le64 frames_rx_pause; 2365 __le64 frames_rx_bad_length; 2366 __le64 frames_rx_undersized; 2367 __le64 frames_rx_oversized; 2368 __le64 frames_rx_fragments; 2369 __le64 frames_rx_jabber; 2370 __le64 frames_rx_64b; 2371 __le64 frames_rx_65b_127b; 2372 __le64 frames_rx_128b_255b; 2373 __le64 frames_rx_256b_511b; 2374 __le64 frames_rx_512b_1023b; 2375 __le64 frames_rx_1024b_1518b; 2376 __le64 frames_rx_gt_1518b; 2377 __le64 frames_rx_fifo_full; 2378 __le64 frames_tx_ok; 2379 __le64 frames_tx_all; 2380 __le64 frames_tx_bad; 2381 __le64 octets_tx_ok; 2382 __le64 octets_tx_total; 2383 __le64 frames_tx_unicast; 2384 __le64 frames_tx_multicast; 2385 __le64 frames_tx_broadcast; 2386 __le64 frames_tx_pause; 2387 }; 2388 2389 enum ionic_pb_buffer_drop_stats { 2390 IONIC_BUFFER_INTRINSIC_DROP = 0, 2391 IONIC_BUFFER_DISCARDED, 2392 IONIC_BUFFER_ADMITTED, 2393 IONIC_BUFFER_OUT_OF_CELLS_DROP, 2394 IONIC_BUFFER_OUT_OF_CELLS_DROP_2, 2395 IONIC_BUFFER_OUT_OF_CREDIT_DROP, 2396 IONIC_BUFFER_TRUNCATION_DROP, 2397 IONIC_BUFFER_PORT_DISABLED_DROP, 2398 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, 2399 IONIC_BUFFER_SPAN_TAIL_DROP, 2400 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, 2401 IONIC_BUFFER_ENQUEUE_ERROR_DROP, 2402 IONIC_BUFFER_INVALID_PORT_DROP, 2403 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, 2404 IONIC_BUFFER_DROP_MAX, 2405 }; 2406 2407 enum ionic_oflow_drop_stats { 2408 IONIC_OFLOW_OCCUPANCY_DROP, 2409 IONIC_OFLOW_EMERGENCY_STOP_DROP, 2410 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP, 2411 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP, 2412 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP, 2413 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP, 2414 IONIC_OFLOW_DROP_MAX, 2415 }; 2416 2417 /** 2418 * struct port_pb_stats - packet buffers system stats 2419 * uses ionic_pb_buffer_drop_stats for drop_counts[] 2420 */ 2421 struct ionic_port_pb_stats { 2422 __le64 sop_count_in; 2423 __le64 eop_count_in; 2424 __le64 sop_count_out; 2425 __le64 eop_count_out; 2426 __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; 2427 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2428 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; 2429 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; 2430 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX]; 2431 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX]; 2432 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX]; 2433 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX]; 2434 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX]; 2435 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX]; 2436 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX]; 2437 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2438 }; 2439 2440 /** 2441 * enum ionic_port_type - Port types 2442 * @IONIC_ETH_UNKNOWN: Port type not configured 2443 * @IONIC_ETH_HOST: Port carries ethernet traffic (inband) 2444 * @IONIC_ETH_HOST_MGMT: Port carries mgmt traffic (out-of-band) 2445 * @IONIC_ETH_MNIC_OOB_MGMT: 2446 * @IONIC_ETH_MNIC_INTERNAL_MGMT: 2447 * @IONIC_ETH_MNIC_INBAND_MGMT: 2448 * @IONIC_ETH_MNIC_CPU: 2449 * @IONIC_ETH_MNIC_LEARN: 2450 * @IONIC_ETH_MNIC_CONTROL: 2451 */ 2452 enum ionic_port_type { 2453 IONIC_ETH_UNKNOWN, 2454 IONIC_ETH_HOST, 2455 IONIC_ETH_HOST_MGMT, 2456 IONIC_ETH_MNIC_OOB_MGMT, 2457 IONIC_ETH_MNIC_INTERNAL_MGMT, 2458 IONIC_ETH_MNIC_INBAND_MGMT, 2459 IONIC_ETH_MNIC_CPU, 2460 IONIC_ETH_MNIC_LEARN, 2461 IONIC_ETH_MNIC_CONTROL, 2462 }; 2463 2464 /** 2465 * struct ionic_port_identity - port identity structure 2466 * @version: identity structure version 2467 * @type: type of port (enum ionic_port_type) 2468 * @num_lanes: number of lanes for the port 2469 * @autoneg: autoneg supported 2470 * @min_frame_size: minimum frame size supported 2471 * @max_frame_size: maximum frame size supported 2472 * @fec_type: supported fec types 2473 * @pause_type: supported pause types 2474 * @loopback_mode: supported loopback mode 2475 * @speeds: supported speeds 2476 * @config: current port configuration 2477 */ 2478 union ionic_port_identity { 2479 struct { 2480 u8 version; 2481 u8 type; 2482 u8 num_lanes; 2483 u8 autoneg; 2484 __le32 min_frame_size; 2485 __le32 max_frame_size; 2486 u8 fec_type[4]; 2487 u8 pause_type[2]; 2488 u8 loopback_mode[2]; 2489 __le32 speeds[16]; 2490 u8 rsvd2[44]; 2491 union ionic_port_config config; 2492 }; 2493 __le32 words[478]; 2494 }; 2495 2496 /** 2497 * struct ionic_port_info - port info structure 2498 * @config: Port configuration data 2499 * @status: Port status data 2500 * @stats: Port statistics data 2501 * @mgmt_stats: Port management statistics data 2502 * @port_pb_drop_stats: uplink pb drop stats 2503 */ 2504 struct ionic_port_info { 2505 union ionic_port_config config; 2506 struct ionic_port_status status; 2507 union { 2508 struct ionic_port_stats stats; 2509 struct ionic_mgmt_port_stats mgmt_stats; 2510 }; 2511 /* room for pb_stats to start at 2k offset */ 2512 u8 rsvd[760]; 2513 struct ionic_port_pb_stats pb_stats; 2514 }; 2515 2516 /** 2517 * struct ionic_lif_stats - LIF statistics structure 2518 */ 2519 struct ionic_lif_stats { 2520 /* RX */ 2521 __le64 rx_ucast_bytes; 2522 __le64 rx_ucast_packets; 2523 __le64 rx_mcast_bytes; 2524 __le64 rx_mcast_packets; 2525 __le64 rx_bcast_bytes; 2526 __le64 rx_bcast_packets; 2527 __le64 rsvd0; 2528 __le64 rsvd1; 2529 /* RX drops */ 2530 __le64 rx_ucast_drop_bytes; 2531 __le64 rx_ucast_drop_packets; 2532 __le64 rx_mcast_drop_bytes; 2533 __le64 rx_mcast_drop_packets; 2534 __le64 rx_bcast_drop_bytes; 2535 __le64 rx_bcast_drop_packets; 2536 __le64 rx_dma_error; 2537 __le64 rsvd2; 2538 /* TX */ 2539 __le64 tx_ucast_bytes; 2540 __le64 tx_ucast_packets; 2541 __le64 tx_mcast_bytes; 2542 __le64 tx_mcast_packets; 2543 __le64 tx_bcast_bytes; 2544 __le64 tx_bcast_packets; 2545 __le64 rsvd3; 2546 __le64 rsvd4; 2547 /* TX drops */ 2548 __le64 tx_ucast_drop_bytes; 2549 __le64 tx_ucast_drop_packets; 2550 __le64 tx_mcast_drop_bytes; 2551 __le64 tx_mcast_drop_packets; 2552 __le64 tx_bcast_drop_bytes; 2553 __le64 tx_bcast_drop_packets; 2554 __le64 tx_dma_error; 2555 __le64 rsvd5; 2556 /* Rx Queue/Ring drops */ 2557 __le64 rx_queue_disabled; 2558 __le64 rx_queue_empty; 2559 __le64 rx_queue_error; 2560 __le64 rx_desc_fetch_error; 2561 __le64 rx_desc_data_error; 2562 __le64 rsvd6; 2563 __le64 rsvd7; 2564 __le64 rsvd8; 2565 /* Tx Queue/Ring drops */ 2566 __le64 tx_queue_disabled; 2567 __le64 tx_queue_error; 2568 __le64 tx_desc_fetch_error; 2569 __le64 tx_desc_data_error; 2570 __le64 tx_queue_empty; 2571 __le64 rsvd10; 2572 __le64 rsvd11; 2573 __le64 rsvd12; 2574 2575 /* RDMA/ROCE TX */ 2576 __le64 tx_rdma_ucast_bytes; 2577 __le64 tx_rdma_ucast_packets; 2578 __le64 tx_rdma_mcast_bytes; 2579 __le64 tx_rdma_mcast_packets; 2580 __le64 tx_rdma_cnp_packets; 2581 __le64 rsvd13; 2582 __le64 rsvd14; 2583 __le64 rsvd15; 2584 2585 /* RDMA/ROCE RX */ 2586 __le64 rx_rdma_ucast_bytes; 2587 __le64 rx_rdma_ucast_packets; 2588 __le64 rx_rdma_mcast_bytes; 2589 __le64 rx_rdma_mcast_packets; 2590 __le64 rx_rdma_cnp_packets; 2591 __le64 rx_rdma_ecn_packets; 2592 __le64 rsvd16; 2593 __le64 rsvd17; 2594 2595 __le64 flex1; 2596 __le64 flex2; 2597 __le64 flex3; 2598 __le64 flex4; 2599 __le64 flex5; 2600 __le64 flex6; 2601 __le64 flex7; 2602 __le64 flex8; 2603 2604 __le64 flex9; 2605 __le64 flex10; 2606 __le64 flex11; 2607 __le64 flex12; 2608 __le64 flex13; 2609 __le64 flex14; 2610 __le64 flex15; 2611 __le64 flex16; 2612 2613 __le64 flex17; 2614 __le64 flex18; 2615 __le64 flex19; 2616 __le64 flex20; 2617 __le64 flex21; 2618 __le64 flex22; 2619 __le64 flex23; 2620 __le64 flex24; 2621 2622 __le64 flex25; 2623 __le64 flex26; 2624 __le64 flex27; 2625 __le64 flex28; 2626 __le64 flex29; 2627 __le64 flex30; 2628 __le64 flex31; 2629 __le64 flex32; 2630 2631 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2632 __le64 rdma_req_rx_pkt_seq_err; 2633 __le64 rdma_req_rx_rnr_retry_err; 2634 __le64 rdma_req_rx_remote_access_err; 2635 __le64 rdma_req_rx_remote_inv_req_err; 2636 __le64 rdma_req_rx_remote_oper_err; 2637 __le64 rdma_req_rx_implied_nak_seq_err; 2638 __le64 rdma_req_rx_cqe_err; 2639 __le64 rdma_req_rx_cqe_flush_err; 2640 2641 __le64 rdma_req_rx_dup_responses; 2642 __le64 rdma_req_rx_invalid_packets; 2643 __le64 rdma_req_tx_local_access_err; 2644 __le64 rdma_req_tx_local_oper_err; 2645 __le64 rdma_req_tx_memory_mgmt_err; 2646 __le64 rsvd52; 2647 __le64 rsvd53; 2648 __le64 rsvd54; 2649 2650 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2651 __le64 rdma_resp_rx_dup_requests; 2652 __le64 rdma_resp_rx_out_of_buffer; 2653 __le64 rdma_resp_rx_out_of_seq_pkts; 2654 __le64 rdma_resp_rx_cqe_err; 2655 __le64 rdma_resp_rx_cqe_flush_err; 2656 __le64 rdma_resp_rx_local_len_err; 2657 __le64 rdma_resp_rx_inv_request_err; 2658 __le64 rdma_resp_rx_local_qp_oper_err; 2659 2660 __le64 rdma_resp_rx_out_of_atomic_resource; 2661 __le64 rdma_resp_tx_pkt_seq_err; 2662 __le64 rdma_resp_tx_remote_inv_req_err; 2663 __le64 rdma_resp_tx_remote_access_err; 2664 __le64 rdma_resp_tx_remote_oper_err; 2665 __le64 rdma_resp_tx_rnr_retry_err; 2666 __le64 rsvd57; 2667 __le64 rsvd58; 2668 }; 2669 2670 /** 2671 * struct ionic_lif_info - LIF info structure 2672 * @config: LIF configuration structure 2673 * @status: LIF status structure 2674 * @stats: LIF statistics structure 2675 */ 2676 struct ionic_lif_info { 2677 union ionic_lif_config config; 2678 struct ionic_lif_status status; 2679 struct ionic_lif_stats stats; 2680 }; 2681 2682 union ionic_dev_cmd { 2683 u32 words[16]; 2684 struct ionic_admin_cmd cmd; 2685 struct ionic_nop_cmd nop; 2686 2687 struct ionic_dev_identify_cmd identify; 2688 struct ionic_dev_init_cmd init; 2689 struct ionic_dev_reset_cmd reset; 2690 struct ionic_dev_getattr_cmd getattr; 2691 struct ionic_dev_setattr_cmd setattr; 2692 2693 struct ionic_port_identify_cmd port_identify; 2694 struct ionic_port_init_cmd port_init; 2695 struct ionic_port_reset_cmd port_reset; 2696 struct ionic_port_getattr_cmd port_getattr; 2697 struct ionic_port_setattr_cmd port_setattr; 2698 2699 struct ionic_vf_setattr_cmd vf_setattr; 2700 struct ionic_vf_getattr_cmd vf_getattr; 2701 2702 struct ionic_lif_identify_cmd lif_identify; 2703 struct ionic_lif_init_cmd lif_init; 2704 struct ionic_lif_reset_cmd lif_reset; 2705 2706 struct ionic_qos_identify_cmd qos_identify; 2707 struct ionic_qos_init_cmd qos_init; 2708 struct ionic_qos_reset_cmd qos_reset; 2709 struct ionic_qos_clear_stats_cmd qos_clear_stats; 2710 2711 struct ionic_q_identify_cmd q_identify; 2712 struct ionic_q_init_cmd q_init; 2713 struct ionic_q_control_cmd q_control; 2714 }; 2715 2716 union ionic_dev_cmd_comp { 2717 u32 words[4]; 2718 u8 status; 2719 struct ionic_admin_comp comp; 2720 struct ionic_nop_comp nop; 2721 2722 struct ionic_dev_identify_comp identify; 2723 struct ionic_dev_init_comp init; 2724 struct ionic_dev_reset_comp reset; 2725 struct ionic_dev_getattr_comp getattr; 2726 struct ionic_dev_setattr_comp setattr; 2727 2728 struct ionic_port_identify_comp port_identify; 2729 struct ionic_port_init_comp port_init; 2730 struct ionic_port_reset_comp port_reset; 2731 struct ionic_port_getattr_comp port_getattr; 2732 struct ionic_port_setattr_comp port_setattr; 2733 2734 struct ionic_vf_setattr_comp vf_setattr; 2735 struct ionic_vf_getattr_comp vf_getattr; 2736 2737 struct ionic_lif_identify_comp lif_identify; 2738 struct ionic_lif_init_comp lif_init; 2739 ionic_lif_reset_comp lif_reset; 2740 2741 struct ionic_qos_identify_comp qos_identify; 2742 ionic_qos_init_comp qos_init; 2743 ionic_qos_reset_comp qos_reset; 2744 2745 struct ionic_q_identify_comp q_identify; 2746 struct ionic_q_init_comp q_init; 2747 }; 2748 2749 /** 2750 * union ionic_dev_info_regs - Device info register format (read-only) 2751 * @signature: Signature value of 0x44455649 ('DEVI') 2752 * @version: Current version of info 2753 * @asic_type: Asic type 2754 * @asic_rev: Asic revision 2755 * @fw_status: Firmware status 2756 * @fw_heartbeat: Firmware heartbeat counter 2757 * @serial_num: Serial number 2758 * @fw_version: Firmware version 2759 */ 2760 union ionic_dev_info_regs { 2761 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 2762 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 2763 struct { 2764 u32 signature; 2765 u8 version; 2766 u8 asic_type; 2767 u8 asic_rev; 2768 #define IONIC_FW_STS_F_RUNNING 0x1 2769 u8 fw_status; 2770 u32 fw_heartbeat; 2771 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 2772 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 2773 }; 2774 u32 words[512]; 2775 }; 2776 2777 /** 2778 * union ionic_dev_cmd_regs - Device command register format (read-write) 2779 * @doorbell: Device Cmd Doorbell, write-only 2780 * Write a 1 to signal device to process cmd, 2781 * poll done for completion. 2782 * @done: Done indicator, bit 0 == 1 when command is complete 2783 * @cmd: Opcode-specific command bytes 2784 * @comp: Opcode-specific response bytes 2785 * @data: Opcode-specific side-data 2786 */ 2787 union ionic_dev_cmd_regs { 2788 struct __rte_packed_begin { 2789 u32 doorbell; 2790 u32 done; 2791 union ionic_dev_cmd cmd; 2792 union ionic_dev_cmd_comp comp; 2793 u8 rsvd[48]; 2794 u32 data[478]; 2795 } __rte_packed_end; 2796 u32 words[512]; 2797 }; 2798 2799 /** 2800 * union ionic_dev_regs - Device register format for bar 0 page 0 2801 * @info: Device info registers 2802 * @devcmd: Device command registers 2803 */ 2804 union ionic_dev_regs { 2805 struct __rte_packed_begin { 2806 union ionic_dev_info_regs info; 2807 union ionic_dev_cmd_regs devcmd; 2808 } __rte_packed_end; 2809 __le32 words[1024]; 2810 }; 2811 2812 union ionic_adminq_cmd { 2813 struct ionic_admin_cmd cmd; 2814 struct ionic_nop_cmd nop; 2815 struct ionic_q_identify_cmd q_identify; 2816 struct ionic_q_init_cmd q_init; 2817 struct ionic_q_control_cmd q_control; 2818 struct ionic_lif_setattr_cmd lif_setattr; 2819 struct ionic_lif_getattr_cmd lif_getattr; 2820 struct ionic_rx_mode_set_cmd rx_mode_set; 2821 struct ionic_rx_filter_add_cmd rx_filter_add; 2822 struct ionic_rx_filter_del_cmd rx_filter_del; 2823 struct ionic_rdma_reset_cmd rdma_reset; 2824 struct ionic_rdma_queue_cmd rdma_queue; 2825 struct ionic_fw_download_cmd fw_download; 2826 struct ionic_fw_control_cmd fw_control; 2827 }; 2828 2829 union ionic_adminq_comp { 2830 struct ionic_admin_comp comp; 2831 struct ionic_nop_comp nop; 2832 struct ionic_q_identify_comp q_identify; 2833 struct ionic_q_init_comp q_init; 2834 struct ionic_lif_setattr_comp lif_setattr; 2835 struct ionic_lif_getattr_comp lif_getattr; 2836 struct ionic_rx_filter_add_comp rx_filter_add; 2837 struct ionic_fw_control_comp fw_control; 2838 }; 2839 2840 struct ionic_notifyq_cmd { 2841 __le32 data; /* Not used but needed for qcq structure */ 2842 }; 2843 2844 union ionic_notifyq_comp { 2845 struct ionic_notifyq_event event; 2846 struct ionic_link_change_event link_change; 2847 struct ionic_reset_event reset; 2848 struct ionic_heartbeat_event heartbeat; 2849 struct ionic_log_event log; 2850 }; 2851 2852 /** 2853 * struct ionic_eq_comp - Event queue completion descriptor 2854 * 2855 * @code: Event code, see enum ionic_eq_comp_code 2856 * @lif_index: To which LIF the event pertains 2857 * @qid: To which queue id the event pertains 2858 * @gen_color: Event queue wrap counter, init 1, incr each wrap 2859 */ 2860 struct ionic_eq_comp { 2861 __le16 code; 2862 __le16 lif_index; 2863 __le32 qid; 2864 u8 rsvd[7]; 2865 u8 gen_color; 2866 }; 2867 2868 enum ionic_eq_comp_code { 2869 IONIC_EQ_COMP_CODE_NONE = 0, 2870 IONIC_EQ_COMP_CODE_RX_COMP = 1, 2871 IONIC_EQ_COMP_CODE_TX_COMP = 2, 2872 }; 2873 2874 /* Deprecate */ 2875 struct ionic_identity { 2876 union ionic_drv_identity drv; 2877 union ionic_dev_identity dev; 2878 union ionic_lif_identity lif; 2879 union ionic_port_identity port; 2880 union ionic_qos_identity qos; 2881 union ionic_q_identity txq; 2882 }; 2883 2884 #endif /* _IONIC_IF_H_ */ 2885