1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #ifndef _ICE_RXTX_H_ 6 #define _ICE_RXTX_H_ 7 8 #include "../common/tx.h" 9 #include "ice_ethdev.h" 10 11 #define ICE_ALIGN_RING_DESC 32 12 #define ICE_MIN_RING_DESC 64 13 #define ICE_MAX_RING_DESC (8192 - 32) 14 #define ICE_DMA_MEM_ALIGN 4096 15 #define ICE_RING_BASE_ALIGN 128 16 17 #define ICE_RX_MAX_BURST 32 18 #define ICE_TX_MAX_BURST 32 19 20 /* Maximal number of segments to split. */ 21 #define ICE_RX_MAX_NSEG 2 22 23 #define ICE_CHK_Q_ENA_COUNT 100 24 #define ICE_CHK_Q_ENA_INTERVAL_US 100 25 26 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC 27 #define ice_rx_flex_desc ice_16b_rx_flex_desc 28 #else 29 #define ice_rx_flex_desc ice_32b_rx_flex_desc 30 #endif 31 32 #define ICE_SUPPORT_CHAIN_NUM 5 33 34 #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP 35 36 #define ICE_VPMD_RX_BURST 32 37 #define ICE_VPMD_TX_BURST 32 38 #define ICE_RXQ_REARM_THRESH 64 39 #define ICE_MAX_RX_BURST ICE_RXQ_REARM_THRESH 40 #define ICE_TX_MAX_FREE_BUF_SZ 64 41 #define ICE_DESCS_PER_LOOP 4 42 43 #define ICE_FDIR_PKT_LEN 512 44 45 #define ICE_RXDID_COMMS_OVS 22 46 47 #define ICE_TX_MIN_PKT_LEN 17 48 49 #define ICE_TX_OFFLOAD_MASK ( \ 50 RTE_MBUF_F_TX_OUTER_IPV6 | \ 51 RTE_MBUF_F_TX_OUTER_IPV4 | \ 52 RTE_MBUF_F_TX_OUTER_IP_CKSUM | \ 53 RTE_MBUF_F_TX_VLAN | \ 54 RTE_MBUF_F_TX_IPV6 | \ 55 RTE_MBUF_F_TX_IPV4 | \ 56 RTE_MBUF_F_TX_IP_CKSUM | \ 57 RTE_MBUF_F_TX_L4_MASK | \ 58 RTE_MBUF_F_TX_IEEE1588_TMST | \ 59 RTE_MBUF_F_TX_TCP_SEG | \ 60 RTE_MBUF_F_TX_QINQ | \ 61 RTE_MBUF_F_TX_TUNNEL_MASK | \ 62 RTE_MBUF_F_TX_UDP_SEG | \ 63 RTE_MBUF_F_TX_OUTER_UDP_CKSUM) 64 65 #define ICE_TX_OFFLOAD_NOTSUP_MASK \ 66 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ICE_TX_OFFLOAD_MASK) 67 68 extern uint64_t ice_timestamp_dynflag; 69 extern int ice_timestamp_dynfield_offset; 70 71 /* Max header size can be 2K - 64 bytes */ 72 #define ICE_RX_HDR_BUF_SIZE (2048 - 64) 73 74 /* Max data buffer size must be 16K - 128 bytes */ 75 #define ICE_RX_MAX_DATA_BUF_SIZE (16 * 1024 - 128) 76 77 #define ICE_HEADER_SPLIT_ENA BIT(0) 78 79 #define ICE_TX_MTU_SEG_MAX 8 80 81 typedef void (*ice_rx_release_mbufs_t)(struct ice_rx_queue *rxq); 82 typedef void (*ice_tx_release_mbufs_t)(struct ice_tx_queue *txq); 83 typedef void (*ice_rxd_to_pkt_fields_t)(struct ice_rx_queue *rxq, 84 struct rte_mbuf *mb, 85 volatile union ice_rx_flex_desc *rxdp); 86 87 struct ice_rx_entry { 88 struct rte_mbuf *mbuf; 89 }; 90 91 enum ice_rx_dtype { 92 ICE_RX_DTYPE_NO_SPLIT = 0, 93 ICE_RX_DTYPE_HEADER_SPLIT = 1, 94 ICE_RX_DTYPE_SPLIT_ALWAYS = 2, 95 }; 96 97 struct ice_rx_queue { 98 struct rte_mempool *mp; /* mbuf pool to populate RX ring */ 99 volatile union ice_rx_flex_desc *rx_ring;/* RX ring virtual address */ 100 rte_iova_t rx_ring_dma; /* RX ring DMA address */ 101 struct ice_rx_entry *sw_ring; /* address of RX soft ring */ 102 uint16_t nb_rx_desc; /* number of RX descriptors */ 103 uint16_t rx_free_thresh; /* max free RX desc to hold */ 104 uint16_t rx_tail; /* current value of tail */ 105 uint16_t nb_rx_hold; /* number of held free RX desc */ 106 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */ 107 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */ 108 uint16_t rx_nb_avail; /**< number of staged packets ready */ 109 uint16_t rx_next_avail; /**< index of next staged packets */ 110 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */ 111 struct rte_mbuf fake_mbuf; /**< dummy mbuf */ 112 struct rte_mbuf *rx_stage[ICE_RX_MAX_BURST * 2]; 113 114 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */ 115 uint16_t rxrearm_start; /**< the idx we start the re-arming from */ 116 uint64_t mbuf_initializer; /**< value to init mbufs */ 117 118 uint16_t port_id; /* device port ID */ 119 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */ 120 uint8_t fdir_enabled; /* 0 if FDIR disabled, 1 when enabled */ 121 uint16_t queue_id; /* RX queue index */ 122 uint16_t reg_idx; /* RX queue register index */ 123 uint8_t drop_en; /* if not 0, set register bit */ 124 volatile uint8_t *qrx_tail; /* register address of tail */ 125 struct ice_vsi *vsi; /* the VSI this queue belongs to */ 126 uint16_t rx_buf_len; /* The packet buffer size */ 127 uint16_t rx_hdr_len; /* The header buffer size */ 128 uint16_t max_pkt_len; /* Maximum packet length */ 129 bool q_set; /* indicate if rx queue has been configured */ 130 bool rx_deferred_start; /* don't start this queue in dev start */ 131 uint8_t proto_xtr; /* Protocol extraction from flexible descriptor */ 132 int xtr_field_offs; /*Protocol extraction matedata offset*/ 133 uint64_t xtr_ol_flag; /* Protocol extraction offload flag */ 134 uint32_t rxdid; /* Receive Flex Descriptor profile ID */ 135 ice_rx_release_mbufs_t rx_rel_mbufs; 136 uint64_t offloads; 137 uint32_t time_high; 138 uint32_t hw_register_set; 139 const struct rte_memzone *mz; 140 uint32_t hw_time_high; /* high 32 bits of timestamp */ 141 uint32_t hw_time_low; /* low 32 bits of timestamp */ 142 uint64_t hw_time_update; /* SW time of HW record updating */ 143 struct rte_eth_rxseg_split rxseg[ICE_RX_MAX_NSEG]; 144 uint32_t rxseg_nb; 145 bool ts_enable; /* if rxq timestamp is enabled */ 146 }; 147 148 struct ice_tx_queue { 149 uint16_t nb_tx_desc; /* number of TX descriptors */ 150 rte_iova_t tx_ring_dma; /* TX ring DMA address */ 151 volatile struct ice_tx_desc *tx_ring; /* TX ring virtual address */ 152 struct ci_tx_entry *sw_ring; /* virtual address of SW ring */ 153 uint16_t tx_tail; /* current value of tail register */ 154 volatile uint8_t *qtx_tail; /* register address of tail */ 155 uint16_t nb_tx_used; /* number of TX desc used since RS bit set */ 156 /* index to last TX descriptor to have been cleaned */ 157 uint16_t last_desc_cleaned; 158 /* Total number of TX descriptors ready to be allocated. */ 159 uint16_t nb_tx_free; 160 /* Start freeing TX buffers if there are less free descriptors than 161 * this value. 162 */ 163 uint16_t tx_free_thresh; 164 /* Number of TX descriptors to use before RS bit is set. */ 165 uint16_t tx_rs_thresh; 166 uint8_t pthresh; /**< Prefetch threshold register. */ 167 uint8_t hthresh; /**< Host threshold register. */ 168 uint8_t wthresh; /**< Write-back threshold reg. */ 169 uint16_t port_id; /* Device port identifier. */ 170 uint16_t queue_id; /* TX queue index. */ 171 uint32_t q_teid; /* TX schedule node id. */ 172 uint16_t reg_idx; 173 uint64_t offloads; 174 struct ice_vsi *vsi; /* the VSI this queue belongs to */ 175 uint16_t tx_next_dd; 176 uint16_t tx_next_rs; 177 uint64_t mbuf_errors; 178 bool tx_deferred_start; /* don't start this queue in dev start */ 179 bool q_set; /* indicate if tx queue has been configured */ 180 ice_tx_release_mbufs_t tx_rel_mbufs; 181 const struct rte_memzone *mz; 182 }; 183 184 /* Offload features */ 185 union ice_tx_offload { 186 uint64_t data; 187 struct { 188 uint64_t l2_len:7; /* L2 (MAC) Header Length. */ 189 uint64_t l3_len:9; /* L3 (IP) Header Length. */ 190 uint64_t l4_len:8; /* L4 Header Length. */ 191 uint64_t tso_segsz:16; /* TCP TSO segment size */ 192 uint64_t outer_l2_len:8; /* outer L2 Header Length */ 193 uint64_t outer_l3_len:16; /* outer L3 Header Length */ 194 }; 195 }; 196 197 /* Rx Flex Descriptor for Comms Package Profile 198 * RxDID Profile ID 22 (swap Hash and FlowID) 199 * Flex-field 0: Flow ID lower 16-bits 200 * Flex-field 1: Flow ID upper 16-bits 201 * Flex-field 2: RSS hash lower 16-bits 202 * Flex-field 3: RSS hash upper 16-bits 203 * Flex-field 4: AUX0 204 * Flex-field 5: AUX1 205 */ 206 struct ice_32b_rx_flex_desc_comms_ovs { 207 /* Qword 0 */ 208 u8 rxdid; 209 u8 mir_id_umb_cast; 210 __le16 ptype_flexi_flags0; 211 __le16 pkt_len; 212 __le16 hdr_len_sph_flex_flags1; 213 214 /* Qword 1 */ 215 __le16 status_error0; 216 __le16 l2tag1; 217 __le32 flow_id; 218 219 /* Qword 2 */ 220 __le16 status_error1; 221 u8 flexi_flags2; 222 u8 ts_low; 223 __le16 l2tag2_1st; 224 __le16 l2tag2_2nd; 225 226 /* Qword 3 */ 227 __le32 rss_hash; 228 union { 229 struct { 230 __le16 aux0; 231 __le16 aux1; 232 } flex; 233 __le32 ts_high; 234 } flex_ts; 235 }; 236 237 int ice_rx_queue_setup(struct rte_eth_dev *dev, 238 uint16_t queue_idx, 239 uint16_t nb_desc, 240 unsigned int socket_id, 241 const struct rte_eth_rxconf *rx_conf, 242 struct rte_mempool *mp); 243 int ice_tx_queue_setup(struct rte_eth_dev *dev, 244 uint16_t queue_idx, 245 uint16_t nb_desc, 246 unsigned int socket_id, 247 const struct rte_eth_txconf *tx_conf); 248 int ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 249 int ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 250 int ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 251 int ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 252 int ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 253 int ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 254 int ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 255 int ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 256 void ice_rx_queue_release(void *rxq); 257 void ice_tx_queue_release(void *txq); 258 void ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 259 void ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 260 void ice_free_queues(struct rte_eth_dev *dev); 261 int ice_fdir_setup_tx_resources(struct ice_pf *pf); 262 int ice_fdir_setup_rx_resources(struct ice_pf *pf); 263 uint16_t ice_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 264 uint16_t nb_pkts); 265 uint16_t ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 266 uint16_t nb_pkts); 267 void ice_set_rx_function(struct rte_eth_dev *dev); 268 uint16_t ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, 269 uint16_t nb_pkts); 270 void ice_set_tx_function_flag(struct rte_eth_dev *dev, 271 struct ice_tx_queue *txq); 272 void ice_set_tx_function(struct rte_eth_dev *dev); 273 uint32_t ice_rx_queue_count(void *rx_queue); 274 void ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 275 struct rte_eth_rxq_info *qinfo); 276 void ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 277 struct rte_eth_txq_info *qinfo); 278 int ice_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 279 struct rte_eth_burst_mode *mode); 280 int ice_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 281 struct rte_eth_burst_mode *mode); 282 int ice_rx_descriptor_status(void *rx_queue, uint16_t offset); 283 int ice_tx_descriptor_status(void *tx_queue, uint16_t offset); 284 void ice_set_default_ptype_table(struct rte_eth_dev *dev); 285 const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev, 286 size_t *no_of_elements); 287 void ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, 288 uint32_t rxdid); 289 290 int ice_rx_vec_dev_check(struct rte_eth_dev *dev); 291 int ice_tx_vec_dev_check(struct rte_eth_dev *dev); 292 int ice_rxq_vec_setup(struct ice_rx_queue *rxq); 293 int ice_txq_vec_setup(struct ice_tx_queue *txq); 294 uint16_t ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, 295 uint16_t nb_pkts); 296 uint16_t ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, 297 uint16_t nb_pkts); 298 uint16_t ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, 299 uint16_t nb_pkts); 300 uint16_t ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts, 301 uint16_t nb_pkts); 302 uint16_t ice_recv_pkts_vec_avx2_offload(void *rx_queue, struct rte_mbuf **rx_pkts, 303 uint16_t nb_pkts); 304 uint16_t ice_recv_scattered_pkts_vec_avx2(void *rx_queue, 305 struct rte_mbuf **rx_pkts, 306 uint16_t nb_pkts); 307 uint16_t ice_recv_scattered_pkts_vec_avx2_offload(void *rx_queue, 308 struct rte_mbuf **rx_pkts, 309 uint16_t nb_pkts); 310 uint16_t ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, 311 uint16_t nb_pkts); 312 uint16_t ice_xmit_pkts_vec_avx2_offload(void *tx_queue, struct rte_mbuf **tx_pkts, 313 uint16_t nb_pkts); 314 uint16_t ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts, 315 uint16_t nb_pkts); 316 uint16_t ice_recv_pkts_vec_avx512_offload(void *rx_queue, 317 struct rte_mbuf **rx_pkts, 318 uint16_t nb_pkts); 319 uint16_t ice_recv_scattered_pkts_vec_avx512(void *rx_queue, 320 struct rte_mbuf **rx_pkts, 321 uint16_t nb_pkts); 322 uint16_t ice_recv_scattered_pkts_vec_avx512_offload(void *rx_queue, 323 struct rte_mbuf **rx_pkts, 324 uint16_t nb_pkts); 325 uint16_t ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts, 326 uint16_t nb_pkts); 327 uint16_t ice_xmit_pkts_vec_avx512_offload(void *tx_queue, 328 struct rte_mbuf **tx_pkts, 329 uint16_t nb_pkts); 330 int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc); 331 int ice_tx_done_cleanup(void *txq, uint32_t free_cnt); 332 int ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); 333 334 #define FDIR_PARSING_ENABLE_PER_QUEUE(ad, on) do { \ 335 int i; \ 336 for (i = 0; i < (ad)->pf.dev_data->nb_rx_queues; i++) { \ 337 struct ice_rx_queue *rxq = (ad)->pf.dev_data->rx_queues[i]; \ 338 if (!rxq) \ 339 continue; \ 340 rxq->fdir_enabled = on; \ 341 } \ 342 PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \ 343 } while (0) 344 345 /* Enable/disable flow director parsing from Rx descriptor in data path. */ 346 static inline 347 void ice_fdir_rx_parsing_enable(struct ice_adapter *ad, bool on) 348 { 349 if (on) { 350 /* Enable flow director parsing from Rx descriptor */ 351 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on); 352 ad->fdir_ref_cnt++; 353 } else { 354 if (ad->fdir_ref_cnt >= 1) { 355 ad->fdir_ref_cnt--; 356 357 if (ad->fdir_ref_cnt == 0) 358 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on); 359 } 360 } 361 } 362 363 #define ICE_TIMESYNC_REG_WRAP_GUARD_BAND 10000 364 365 /* Helper function to convert a 32b nanoseconds timestamp to 64b. */ 366 static inline 367 uint64_t ice_tstamp_convert_32b_64b(struct ice_hw *hw, struct ice_adapter *ad, 368 uint32_t flag, uint32_t in_timestamp) 369 { 370 uint8_t tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; 371 const uint64_t mask = 0xFFFFFFFF; 372 uint32_t hi, lo, lo2, delta; 373 uint64_t ns; 374 375 if (flag) { 376 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 377 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); 378 379 /* 380 * On typical system, the delta between lo and lo2 is ~1000ns, 381 * so 10000 seems a large-enough but not overly-big guard band. 382 */ 383 if (lo > (UINT32_MAX - ICE_TIMESYNC_REG_WRAP_GUARD_BAND)) 384 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 385 else 386 lo2 = lo; 387 388 if (lo2 < lo) { 389 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 390 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); 391 } 392 393 ad->time_hw = ((uint64_t)hi << 32) | lo; 394 } 395 396 delta = (in_timestamp - (uint32_t)(ad->time_hw & mask)); 397 if (delta > (mask / 2)) { 398 delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp); 399 ns = ad->time_hw - delta; 400 } else { 401 ns = ad->time_hw + delta; 402 } 403 404 return ns; 405 } 406 407 #endif /* _ICE_RXTX_H_ */ 408