1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #ifndef _ICE_RXTX_H_ 6 #define _ICE_RXTX_H_ 7 8 #include "../common/tx.h" 9 #include "ice_ethdev.h" 10 11 #define ICE_ALIGN_RING_DESC 32 12 #define ICE_MIN_RING_DESC 64 13 #define ICE_MAX_RING_DESC (8192 - 32) 14 #define ICE_DMA_MEM_ALIGN 4096 15 #define ICE_RING_BASE_ALIGN 128 16 17 #define ICE_RX_MAX_BURST 32 18 #define ICE_TX_MAX_BURST 32 19 20 /* Maximal number of segments to split. */ 21 #define ICE_RX_MAX_NSEG 2 22 23 #define ICE_CHK_Q_ENA_COUNT 100 24 #define ICE_CHK_Q_ENA_INTERVAL_US 100 25 26 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC 27 #define ice_rx_flex_desc ice_16b_rx_flex_desc 28 #else 29 #define ice_rx_flex_desc ice_32b_rx_flex_desc 30 #endif 31 32 #define ICE_SUPPORT_CHAIN_NUM 5 33 34 #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP 35 36 #define ICE_VPMD_RX_BURST 32 37 #define ICE_VPMD_TX_BURST 32 38 #define ICE_RXQ_REARM_THRESH 64 39 #define ICE_MAX_RX_BURST ICE_RXQ_REARM_THRESH 40 #define ICE_TX_MAX_FREE_BUF_SZ 64 41 #define ICE_DESCS_PER_LOOP 4 42 43 #define ICE_FDIR_PKT_LEN 512 44 45 #define ICE_RXDID_COMMS_OVS 22 46 47 #define ICE_TX_MIN_PKT_LEN 17 48 49 #define ICE_TX_OFFLOAD_MASK ( \ 50 RTE_MBUF_F_TX_OUTER_IPV6 | \ 51 RTE_MBUF_F_TX_OUTER_IPV4 | \ 52 RTE_MBUF_F_TX_OUTER_IP_CKSUM | \ 53 RTE_MBUF_F_TX_VLAN | \ 54 RTE_MBUF_F_TX_IPV6 | \ 55 RTE_MBUF_F_TX_IPV4 | \ 56 RTE_MBUF_F_TX_IP_CKSUM | \ 57 RTE_MBUF_F_TX_L4_MASK | \ 58 RTE_MBUF_F_TX_IEEE1588_TMST | \ 59 RTE_MBUF_F_TX_TCP_SEG | \ 60 RTE_MBUF_F_TX_QINQ | \ 61 RTE_MBUF_F_TX_TUNNEL_MASK | \ 62 RTE_MBUF_F_TX_UDP_SEG | \ 63 RTE_MBUF_F_TX_OUTER_UDP_CKSUM) 64 65 #define ICE_TX_OFFLOAD_NOTSUP_MASK \ 66 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ICE_TX_OFFLOAD_MASK) 67 68 extern uint64_t ice_timestamp_dynflag; 69 extern int ice_timestamp_dynfield_offset; 70 71 /* Max header size can be 2K - 64 bytes */ 72 #define ICE_RX_HDR_BUF_SIZE (2048 - 64) 73 74 /* Max data buffer size must be 16K - 128 bytes */ 75 #define ICE_RX_MAX_DATA_BUF_SIZE (16 * 1024 - 128) 76 77 #define ICE_HEADER_SPLIT_ENA BIT(0) 78 79 #define ICE_TX_MTU_SEG_MAX 8 80 81 typedef void (*ice_rx_release_mbufs_t)(struct ice_rx_queue *rxq); 82 typedef void (*ice_rxd_to_pkt_fields_t)(struct ice_rx_queue *rxq, 83 struct rte_mbuf *mb, 84 volatile union ice_rx_flex_desc *rxdp); 85 86 struct ice_rx_entry { 87 struct rte_mbuf *mbuf; 88 }; 89 90 enum ice_rx_dtype { 91 ICE_RX_DTYPE_NO_SPLIT = 0, 92 ICE_RX_DTYPE_HEADER_SPLIT = 1, 93 ICE_RX_DTYPE_SPLIT_ALWAYS = 2, 94 }; 95 96 struct ice_rx_queue { 97 struct rte_mempool *mp; /* mbuf pool to populate RX ring */ 98 volatile union ice_rx_flex_desc *rx_ring;/* RX ring virtual address */ 99 rte_iova_t rx_ring_dma; /* RX ring DMA address */ 100 struct ice_rx_entry *sw_ring; /* address of RX soft ring */ 101 uint16_t nb_rx_desc; /* number of RX descriptors */ 102 uint16_t rx_free_thresh; /* max free RX desc to hold */ 103 uint16_t rx_tail; /* current value of tail */ 104 uint16_t nb_rx_hold; /* number of held free RX desc */ 105 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */ 106 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */ 107 uint16_t rx_nb_avail; /**< number of staged packets ready */ 108 uint16_t rx_next_avail; /**< index of next staged packets */ 109 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */ 110 struct rte_mbuf fake_mbuf; /**< dummy mbuf */ 111 struct rte_mbuf *rx_stage[ICE_RX_MAX_BURST * 2]; 112 113 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */ 114 uint16_t rxrearm_start; /**< the idx we start the re-arming from */ 115 uint64_t mbuf_initializer; /**< value to init mbufs */ 116 117 uint16_t port_id; /* device port ID */ 118 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */ 119 uint8_t fdir_enabled; /* 0 if FDIR disabled, 1 when enabled */ 120 uint16_t queue_id; /* RX queue index */ 121 uint16_t reg_idx; /* RX queue register index */ 122 uint8_t drop_en; /* if not 0, set register bit */ 123 volatile uint8_t *qrx_tail; /* register address of tail */ 124 struct ice_vsi *vsi; /* the VSI this queue belongs to */ 125 uint16_t rx_buf_len; /* The packet buffer size */ 126 uint16_t rx_hdr_len; /* The header buffer size */ 127 uint16_t max_pkt_len; /* Maximum packet length */ 128 bool q_set; /* indicate if rx queue has been configured */ 129 bool rx_deferred_start; /* don't start this queue in dev start */ 130 uint8_t proto_xtr; /* Protocol extraction from flexible descriptor */ 131 int xtr_field_offs; /*Protocol extraction matedata offset*/ 132 uint64_t xtr_ol_flag; /* Protocol extraction offload flag */ 133 uint32_t rxdid; /* Receive Flex Descriptor profile ID */ 134 ice_rx_release_mbufs_t rx_rel_mbufs; 135 uint64_t offloads; 136 uint32_t time_high; 137 uint32_t hw_register_set; 138 const struct rte_memzone *mz; 139 uint32_t hw_time_high; /* high 32 bits of timestamp */ 140 uint32_t hw_time_low; /* low 32 bits of timestamp */ 141 uint64_t hw_time_update; /* SW time of HW record updating */ 142 struct rte_eth_rxseg_split rxseg[ICE_RX_MAX_NSEG]; 143 uint32_t rxseg_nb; 144 bool ts_enable; /* if rxq timestamp is enabled */ 145 }; 146 147 /* Offload features */ 148 union ice_tx_offload { 149 uint64_t data; 150 struct { 151 uint64_t l2_len:7; /* L2 (MAC) Header Length. */ 152 uint64_t l3_len:9; /* L3 (IP) Header Length. */ 153 uint64_t l4_len:8; /* L4 Header Length. */ 154 uint64_t tso_segsz:16; /* TCP TSO segment size */ 155 uint64_t outer_l2_len:8; /* outer L2 Header Length */ 156 uint64_t outer_l3_len:16; /* outer L3 Header Length */ 157 }; 158 }; 159 160 /* Rx Flex Descriptor for Comms Package Profile 161 * RxDID Profile ID 22 (swap Hash and FlowID) 162 * Flex-field 0: Flow ID lower 16-bits 163 * Flex-field 1: Flow ID upper 16-bits 164 * Flex-field 2: RSS hash lower 16-bits 165 * Flex-field 3: RSS hash upper 16-bits 166 * Flex-field 4: AUX0 167 * Flex-field 5: AUX1 168 */ 169 struct ice_32b_rx_flex_desc_comms_ovs { 170 /* Qword 0 */ 171 u8 rxdid; 172 u8 mir_id_umb_cast; 173 __le16 ptype_flexi_flags0; 174 __le16 pkt_len; 175 __le16 hdr_len_sph_flex_flags1; 176 177 /* Qword 1 */ 178 __le16 status_error0; 179 __le16 l2tag1; 180 __le32 flow_id; 181 182 /* Qword 2 */ 183 __le16 status_error1; 184 u8 flexi_flags2; 185 u8 ts_low; 186 __le16 l2tag2_1st; 187 __le16 l2tag2_2nd; 188 189 /* Qword 3 */ 190 __le32 rss_hash; 191 union { 192 struct { 193 __le16 aux0; 194 __le16 aux1; 195 } flex; 196 __le32 ts_high; 197 } flex_ts; 198 }; 199 200 int ice_rx_queue_setup(struct rte_eth_dev *dev, 201 uint16_t queue_idx, 202 uint16_t nb_desc, 203 unsigned int socket_id, 204 const struct rte_eth_rxconf *rx_conf, 205 struct rte_mempool *mp); 206 int ice_tx_queue_setup(struct rte_eth_dev *dev, 207 uint16_t queue_idx, 208 uint16_t nb_desc, 209 unsigned int socket_id, 210 const struct rte_eth_txconf *tx_conf); 211 int ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 212 int ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 213 int ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 214 int ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 215 int ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 216 int ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 217 int ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 218 int ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 219 void ice_rx_queue_release(void *rxq); 220 void ice_tx_queue_release(void *txq); 221 void ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 222 void ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 223 void ice_free_queues(struct rte_eth_dev *dev); 224 int ice_fdir_setup_tx_resources(struct ice_pf *pf); 225 int ice_fdir_setup_rx_resources(struct ice_pf *pf); 226 uint16_t ice_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 227 uint16_t nb_pkts); 228 uint16_t ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 229 uint16_t nb_pkts); 230 void ice_set_rx_function(struct rte_eth_dev *dev); 231 uint16_t ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, 232 uint16_t nb_pkts); 233 void ice_set_tx_function_flag(struct rte_eth_dev *dev, 234 struct ci_tx_queue *txq); 235 void ice_set_tx_function(struct rte_eth_dev *dev); 236 uint32_t ice_rx_queue_count(void *rx_queue); 237 void ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 238 struct rte_eth_rxq_info *qinfo); 239 void ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 240 struct rte_eth_txq_info *qinfo); 241 int ice_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 242 struct rte_eth_burst_mode *mode); 243 int ice_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 244 struct rte_eth_burst_mode *mode); 245 int ice_rx_descriptor_status(void *rx_queue, uint16_t offset); 246 int ice_tx_descriptor_status(void *tx_queue, uint16_t offset); 247 void ice_set_default_ptype_table(struct rte_eth_dev *dev); 248 const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev, 249 size_t *no_of_elements); 250 void ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, 251 uint32_t rxdid); 252 253 int ice_rx_vec_dev_check(struct rte_eth_dev *dev); 254 int ice_tx_vec_dev_check(struct rte_eth_dev *dev); 255 int ice_rxq_vec_setup(struct ice_rx_queue *rxq); 256 int ice_txq_vec_setup(struct ci_tx_queue *txq); 257 uint16_t ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, 258 uint16_t nb_pkts); 259 uint16_t ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, 260 uint16_t nb_pkts); 261 uint16_t ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, 262 uint16_t nb_pkts); 263 uint16_t ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts, 264 uint16_t nb_pkts); 265 uint16_t ice_recv_pkts_vec_avx2_offload(void *rx_queue, struct rte_mbuf **rx_pkts, 266 uint16_t nb_pkts); 267 uint16_t ice_recv_scattered_pkts_vec_avx2(void *rx_queue, 268 struct rte_mbuf **rx_pkts, 269 uint16_t nb_pkts); 270 uint16_t ice_recv_scattered_pkts_vec_avx2_offload(void *rx_queue, 271 struct rte_mbuf **rx_pkts, 272 uint16_t nb_pkts); 273 uint16_t ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, 274 uint16_t nb_pkts); 275 uint16_t ice_xmit_pkts_vec_avx2_offload(void *tx_queue, struct rte_mbuf **tx_pkts, 276 uint16_t nb_pkts); 277 uint16_t ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts, 278 uint16_t nb_pkts); 279 uint16_t ice_recv_pkts_vec_avx512_offload(void *rx_queue, 280 struct rte_mbuf **rx_pkts, 281 uint16_t nb_pkts); 282 uint16_t ice_recv_scattered_pkts_vec_avx512(void *rx_queue, 283 struct rte_mbuf **rx_pkts, 284 uint16_t nb_pkts); 285 uint16_t ice_recv_scattered_pkts_vec_avx512_offload(void *rx_queue, 286 struct rte_mbuf **rx_pkts, 287 uint16_t nb_pkts); 288 uint16_t ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts, 289 uint16_t nb_pkts); 290 uint16_t ice_xmit_pkts_vec_avx512_offload(void *tx_queue, 291 struct rte_mbuf **tx_pkts, 292 uint16_t nb_pkts); 293 int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc); 294 int ice_tx_done_cleanup(void *txq, uint32_t free_cnt); 295 int ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); 296 297 #define FDIR_PARSING_ENABLE_PER_QUEUE(ad, on) do { \ 298 int i; \ 299 for (i = 0; i < (ad)->pf.dev_data->nb_rx_queues; i++) { \ 300 struct ice_rx_queue *rxq = (ad)->pf.dev_data->rx_queues[i]; \ 301 if (!rxq) \ 302 continue; \ 303 rxq->fdir_enabled = on; \ 304 } \ 305 PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \ 306 } while (0) 307 308 /* Enable/disable flow director parsing from Rx descriptor in data path. */ 309 static inline 310 void ice_fdir_rx_parsing_enable(struct ice_adapter *ad, bool on) 311 { 312 if (on) { 313 /* Enable flow director parsing from Rx descriptor */ 314 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on); 315 ad->fdir_ref_cnt++; 316 } else { 317 if (ad->fdir_ref_cnt >= 1) { 318 ad->fdir_ref_cnt--; 319 320 if (ad->fdir_ref_cnt == 0) 321 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on); 322 } 323 } 324 } 325 326 #define ICE_TIMESYNC_REG_WRAP_GUARD_BAND 10000 327 328 /* Helper function to convert a 32b nanoseconds timestamp to 64b. */ 329 static inline 330 uint64_t ice_tstamp_convert_32b_64b(struct ice_hw *hw, struct ice_adapter *ad, 331 uint32_t flag, uint32_t in_timestamp) 332 { 333 uint8_t tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; 334 const uint64_t mask = 0xFFFFFFFF; 335 uint32_t hi, lo, lo2, delta; 336 uint64_t ns; 337 338 if (flag) { 339 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 340 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); 341 342 /* 343 * On typical system, the delta between lo and lo2 is ~1000ns, 344 * so 10000 seems a large-enough but not overly-big guard band. 345 */ 346 if (lo > (UINT32_MAX - ICE_TIMESYNC_REG_WRAP_GUARD_BAND)) 347 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 348 else 349 lo2 = lo; 350 351 if (lo2 < lo) { 352 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 353 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); 354 } 355 356 ad->time_hw = ((uint64_t)hi << 32) | lo; 357 } 358 359 delta = (in_timestamp - (uint32_t)(ad->time_hw & mask)); 360 if (delta > (mask / 2)) { 361 delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp); 362 ns = ad->time_hw - delta; 363 } else { 364 ns = ad->time_hw + delta; 365 } 366 367 return ns; 368 } 369 370 #endif /* _ICE_RXTX_H_ */ 371