1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <ethdev_pci.h> 7 8 #include <ctype.h> 9 #include <fcntl.h> 10 #include <stdio.h> 11 #include <sys/types.h> 12 #include <sys/stat.h> 13 #include <unistd.h> 14 #include <math.h> 15 16 #include <rte_tailq.h> 17 #include <rte_os_shim.h> 18 19 #include "eal_firmware.h" 20 21 #include "base/ice_sched.h" 22 #include "base/ice_flow.h" 23 #include "base/ice_dcb.h" 24 #include "base/ice_common.h" 25 #include "base/ice_ptp_hw.h" 26 27 #include "ice_ethdev.h" 28 #include "ice_rxtx.h" 29 #include "ice_generic_flow.h" 30 31 /* devargs */ 32 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" 33 #define ICE_DEFAULT_MAC_DISABLE "default-mac-disable" 34 #define ICE_PROTO_XTR_ARG "proto_xtr" 35 #define ICE_FIELD_OFFS_ARG "field_offs" 36 #define ICE_FIELD_NAME_ARG "field_name" 37 #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask" 38 #define ICE_ONE_PPS_OUT_ARG "pps_out" 39 #define ICE_RX_LOW_LATENCY_ARG "rx_low_latency" 40 #define ICE_MBUF_CHECK_ARG "mbuf_check" 41 #define ICE_DDP_FILENAME_ARG "ddp_pkg_file" 42 #define ICE_DDP_LOAD_SCHED_ARG "ddp_load_sched_topo" 43 #define ICE_TM_LEVELS_ARG "tm_sched_levels" 44 45 #define ICE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 46 47 uint64_t ice_timestamp_dynflag; 48 int ice_timestamp_dynfield_offset = -1; 49 50 static const char * const ice_valid_args[] = { 51 ICE_SAFE_MODE_SUPPORT_ARG, 52 ICE_PROTO_XTR_ARG, 53 ICE_FIELD_OFFS_ARG, 54 ICE_FIELD_NAME_ARG, 55 ICE_HW_DEBUG_MASK_ARG, 56 ICE_ONE_PPS_OUT_ARG, 57 ICE_RX_LOW_LATENCY_ARG, 58 ICE_DEFAULT_MAC_DISABLE, 59 ICE_MBUF_CHECK_ARG, 60 ICE_DDP_FILENAME_ARG, 61 ICE_DDP_LOAD_SCHED_ARG, 62 ICE_TM_LEVELS_ARG, 63 NULL 64 }; 65 66 #define PPS_OUT_DELAY_NS 1 67 68 /* Maximum number of VSI */ 69 #define ICE_MAX_NUM_VSIS (768UL) 70 71 /* The 119 bit offset of the LAN Rx queue context is the L2TSEL control bit. */ 72 #define ICE_L2TSEL_QRX_CONTEXT_REG_IDX 3 73 #define ICE_L2TSEL_BIT_OFFSET 23 74 enum ice_l2tsel { 75 ICE_L2TSEL_EXTRACT_FIRST_TAG_L2TAG2_2ND, 76 ICE_L2TSEL_EXTRACT_FIRST_TAG_L2TAG1, 77 }; 78 79 struct proto_xtr_ol_flag { 80 const struct rte_mbuf_dynflag param; 81 bool required; 82 }; 83 84 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX]; 85 86 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = { 87 [PROTO_XTR_VLAN] = { 88 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" }}, 89 [PROTO_XTR_IPV4] = { 90 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" }}, 91 [PROTO_XTR_IPV6] = { 92 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" }}, 93 [PROTO_XTR_IPV6_FLOW] = { 94 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" }}, 95 [PROTO_XTR_TCP] = { 96 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" }}, 97 [PROTO_XTR_IP_OFFSET] = { 98 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" }} 99 }; 100 101 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package" 102 #define ICE_COMMS_PKG_NAME "ICE COMMS Package" 103 #define ICE_MAX_RES_DESC_NUM 1024 104 105 static int ice_dev_configure(struct rte_eth_dev *dev); 106 static int ice_dev_start(struct rte_eth_dev *dev); 107 static int ice_dev_stop(struct rte_eth_dev *dev); 108 static int ice_dev_close(struct rte_eth_dev *dev); 109 static int ice_dev_reset(struct rte_eth_dev *dev); 110 static int ice_dev_info_get(struct rte_eth_dev *dev, 111 struct rte_eth_dev_info *dev_info); 112 static int ice_phy_conf_link(struct ice_hw *hw, 113 u16 force_speed, 114 bool link_up); 115 static int ice_link_update(struct rte_eth_dev *dev, 116 int wait_to_complete); 117 static int ice_dev_set_link_up(struct rte_eth_dev *dev); 118 static int ice_dev_set_link_down(struct rte_eth_dev *dev); 119 static int ice_dev_led_on(struct rte_eth_dev *dev); 120 static int ice_dev_led_off(struct rte_eth_dev *dev); 121 122 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 123 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 124 static int ice_rss_reta_update(struct rte_eth_dev *dev, 125 struct rte_eth_rss_reta_entry64 *reta_conf, 126 uint16_t reta_size); 127 static int ice_rss_reta_query(struct rte_eth_dev *dev, 128 struct rte_eth_rss_reta_entry64 *reta_conf, 129 uint16_t reta_size); 130 static int ice_rss_hash_update(struct rte_eth_dev *dev, 131 struct rte_eth_rss_conf *rss_conf); 132 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 133 struct rte_eth_rss_conf *rss_conf); 134 static int ice_promisc_enable(struct rte_eth_dev *dev); 135 static int ice_promisc_disable(struct rte_eth_dev *dev); 136 static int ice_allmulti_enable(struct rte_eth_dev *dev); 137 static int ice_allmulti_disable(struct rte_eth_dev *dev); 138 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 139 uint16_t vlan_id, 140 int on); 141 static int ice_macaddr_set(struct rte_eth_dev *dev, 142 struct rte_ether_addr *mac_addr); 143 static int ice_macaddr_add(struct rte_eth_dev *dev, 144 struct rte_ether_addr *mac_addr, 145 __rte_unused uint32_t index, 146 uint32_t pool); 147 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 148 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 149 uint16_t queue_id); 150 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 151 uint16_t queue_id); 152 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 153 size_t fw_size); 154 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 155 uint16_t pvid, int on); 156 static int ice_vlan_tpid_set(struct rte_eth_dev *dev, 157 enum rte_vlan_type vlan_type, 158 uint16_t tpid); 159 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 160 static int ice_get_eeprom(struct rte_eth_dev *dev, 161 struct rte_dev_eeprom_info *eeprom); 162 static int ice_get_module_info(struct rte_eth_dev *dev, 163 struct rte_eth_dev_module_info *modinfo); 164 static int ice_get_module_eeprom(struct rte_eth_dev *dev, 165 struct rte_dev_eeprom_info *info); 166 static int ice_stats_get(struct rte_eth_dev *dev, 167 struct rte_eth_stats *stats); 168 static int ice_stats_reset(struct rte_eth_dev *dev); 169 static int ice_xstats_get(struct rte_eth_dev *dev, 170 struct rte_eth_xstat *xstats, unsigned int n); 171 static int ice_xstats_get_names(struct rte_eth_dev *dev, 172 struct rte_eth_xstat_name *xstats_names, 173 unsigned int limit); 174 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev, 175 const struct rte_flow_ops **ops); 176 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 177 struct rte_eth_udp_tunnel *udp_tunnel); 178 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 179 struct rte_eth_udp_tunnel *udp_tunnel); 180 static int ice_timesync_enable(struct rte_eth_dev *dev); 181 static int ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 182 struct timespec *timestamp, 183 uint32_t flags); 184 static int ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 185 struct timespec *timestamp); 186 static int ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 187 static int ice_timesync_adjust_freq(struct rte_eth_dev *dev, int64_t ppm); 188 static int ice_timesync_read_time(struct rte_eth_dev *dev, 189 struct timespec *timestamp); 190 static int ice_timesync_write_time(struct rte_eth_dev *dev, 191 const struct timespec *timestamp); 192 static int ice_timesync_disable(struct rte_eth_dev *dev); 193 static int ice_fec_get_capability(struct rte_eth_dev *dev, struct rte_eth_fec_capa *speed_fec_capa, 194 unsigned int num); 195 static int ice_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa); 196 static int ice_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa); 197 static const uint32_t *ice_buffer_split_supported_hdr_ptypes_get(struct rte_eth_dev *dev, 198 size_t *no_of_elements); 199 200 static const struct rte_pci_id pci_id_ice_map[] = { 201 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) }, 202 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) }, 203 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) }, 204 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) }, 205 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) }, 206 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 207 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 208 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 209 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) }, 210 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) }, 211 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) }, 212 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) }, 213 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) }, 214 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) }, 215 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) }, 216 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) }, 217 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822_SI_DFLT) }, 218 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) }, 219 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) }, 220 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) }, 221 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) }, 222 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) }, 223 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) }, 224 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) }, 225 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) }, 226 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) }, 227 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E824S) }, 228 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_BACKPLANE) }, 229 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_QSFP) }, 230 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_SFP) }, 231 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C825X) }, 232 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_SGMII) }, 233 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_BACKPLANE) }, 234 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_QSFP56) }, 235 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_SFP) }, 236 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830C_BACKPLANE) }, 237 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_L_BACKPLANE) }, 238 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830C_QSFP) }, 239 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_L_QSFP) }, 240 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830C_SFP) }, 241 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_L_SFP) }, 242 { .vendor_id = 0, /* sentinel */ }, 243 }; 244 245 static int 246 ice_tm_ops_get(struct rte_eth_dev *dev __rte_unused, 247 void *arg) 248 { 249 if (!arg) 250 return -EINVAL; 251 252 *(const void **)arg = &ice_tm_ops; 253 254 return 0; 255 } 256 257 static const struct eth_dev_ops ice_eth_dev_ops = { 258 .dev_configure = ice_dev_configure, 259 .dev_start = ice_dev_start, 260 .dev_stop = ice_dev_stop, 261 .dev_close = ice_dev_close, 262 .dev_reset = ice_dev_reset, 263 .dev_set_link_up = ice_dev_set_link_up, 264 .dev_set_link_down = ice_dev_set_link_down, 265 .dev_led_on = ice_dev_led_on, 266 .dev_led_off = ice_dev_led_off, 267 .rx_queue_start = ice_rx_queue_start, 268 .rx_queue_stop = ice_rx_queue_stop, 269 .tx_queue_start = ice_tx_queue_start, 270 .tx_queue_stop = ice_tx_queue_stop, 271 .rx_queue_setup = ice_rx_queue_setup, 272 .rx_queue_release = ice_dev_rx_queue_release, 273 .tx_queue_setup = ice_tx_queue_setup, 274 .tx_queue_release = ice_dev_tx_queue_release, 275 .dev_infos_get = ice_dev_info_get, 276 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 277 .link_update = ice_link_update, 278 .mtu_set = ice_mtu_set, 279 .mac_addr_set = ice_macaddr_set, 280 .mac_addr_add = ice_macaddr_add, 281 .mac_addr_remove = ice_macaddr_remove, 282 .vlan_filter_set = ice_vlan_filter_set, 283 .vlan_offload_set = ice_vlan_offload_set, 284 .reta_update = ice_rss_reta_update, 285 .reta_query = ice_rss_reta_query, 286 .rss_hash_update = ice_rss_hash_update, 287 .rss_hash_conf_get = ice_rss_hash_conf_get, 288 .promiscuous_enable = ice_promisc_enable, 289 .promiscuous_disable = ice_promisc_disable, 290 .allmulticast_enable = ice_allmulti_enable, 291 .allmulticast_disable = ice_allmulti_disable, 292 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 293 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 294 .fw_version_get = ice_fw_version_get, 295 .vlan_pvid_set = ice_vlan_pvid_set, 296 .vlan_tpid_set = ice_vlan_tpid_set, 297 .rxq_info_get = ice_rxq_info_get, 298 .txq_info_get = ice_txq_info_get, 299 .rx_burst_mode_get = ice_rx_burst_mode_get, 300 .tx_burst_mode_get = ice_tx_burst_mode_get, 301 .get_eeprom_length = ice_get_eeprom_length, 302 .get_eeprom = ice_get_eeprom, 303 .get_module_info = ice_get_module_info, 304 .get_module_eeprom = ice_get_module_eeprom, 305 .stats_get = ice_stats_get, 306 .stats_reset = ice_stats_reset, 307 .xstats_get = ice_xstats_get, 308 .xstats_get_names = ice_xstats_get_names, 309 .xstats_reset = ice_stats_reset, 310 .flow_ops_get = ice_dev_flow_ops_get, 311 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, 312 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, 313 .tx_done_cleanup = ice_tx_done_cleanup, 314 .get_monitor_addr = ice_get_monitor_addr, 315 .timesync_enable = ice_timesync_enable, 316 .timesync_read_rx_timestamp = ice_timesync_read_rx_timestamp, 317 .timesync_read_tx_timestamp = ice_timesync_read_tx_timestamp, 318 .timesync_adjust_time = ice_timesync_adjust_time, 319 .timesync_adjust_freq = ice_timesync_adjust_freq, 320 .timesync_read_time = ice_timesync_read_time, 321 .timesync_write_time = ice_timesync_write_time, 322 .timesync_disable = ice_timesync_disable, 323 .tm_ops_get = ice_tm_ops_get, 324 .fec_get_capability = ice_fec_get_capability, 325 .fec_get = ice_fec_get, 326 .fec_set = ice_fec_set, 327 .buffer_split_supported_hdr_ptypes_get = ice_buffer_split_supported_hdr_ptypes_get, 328 }; 329 330 /* store statistics names and its offset in stats structure */ 331 struct ice_xstats_name_off { 332 char name[RTE_ETH_XSTATS_NAME_SIZE]; 333 unsigned int offset; 334 }; 335 336 static const struct ice_xstats_name_off ice_stats_strings[] = { 337 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 338 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 339 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 340 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)}, 341 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 342 rx_unknown_protocol)}, 343 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 344 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 345 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 346 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)}, 347 }; 348 349 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 350 sizeof(ice_stats_strings[0])) 351 352 static const struct ice_xstats_name_off ice_mbuf_strings[] = { 353 {"tx_mbuf_error_packets", offsetof(struct ice_mbuf_stats, tx_pkt_errors)}, 354 }; 355 356 #define ICE_NB_MBUF_XSTATS (sizeof(ice_mbuf_strings) / sizeof(ice_mbuf_strings[0])) 357 358 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 359 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 360 tx_dropped_link_down)}, 361 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 362 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 363 illegal_bytes)}, 364 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 365 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 366 mac_local_faults)}, 367 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 368 mac_remote_faults)}, 369 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 370 rx_len_errors)}, 371 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 372 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 373 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 374 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 375 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 376 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 377 rx_size_127)}, 378 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 379 rx_size_255)}, 380 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 381 rx_size_511)}, 382 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 383 rx_size_1023)}, 384 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 385 rx_size_1522)}, 386 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 387 rx_size_big)}, 388 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 389 rx_undersize)}, 390 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 391 rx_oversize)}, 392 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 393 mac_short_pkt_dropped)}, 394 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 395 rx_fragments)}, 396 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 397 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 398 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 399 tx_size_127)}, 400 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 401 tx_size_255)}, 402 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 403 tx_size_511)}, 404 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 405 tx_size_1023)}, 406 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 407 tx_size_1522)}, 408 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 409 tx_size_big)}, 410 }; 411 412 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 413 sizeof(ice_hw_port_strings[0])) 414 415 static void 416 ice_init_controlq_parameter(struct ice_hw *hw) 417 { 418 /* fields for adminq */ 419 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 420 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 421 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 422 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 423 424 /* fields for mailboxq, DPDK used as PF host */ 425 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 426 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 427 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 428 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 429 430 /* fields for sideband queue */ 431 hw->sbq.num_rq_entries = ICE_SBQ_LEN; 432 hw->sbq.num_sq_entries = ICE_SBQ_LEN; 433 hw->sbq.rq_buf_size = ICE_SBQ_MAX_BUF_LEN; 434 hw->sbq.sq_buf_size = ICE_SBQ_MAX_BUF_LEN; 435 436 } 437 438 static int 439 lookup_proto_xtr_type(const char *xtr_name) 440 { 441 static struct { 442 const char *name; 443 enum proto_xtr_type type; 444 } xtr_type_map[] = { 445 { "vlan", PROTO_XTR_VLAN }, 446 { "ipv4", PROTO_XTR_IPV4 }, 447 { "ipv6", PROTO_XTR_IPV6 }, 448 { "ipv6_flow", PROTO_XTR_IPV6_FLOW }, 449 { "tcp", PROTO_XTR_TCP }, 450 { "ip_offset", PROTO_XTR_IP_OFFSET }, 451 }; 452 uint32_t i; 453 454 for (i = 0; i < RTE_DIM(xtr_type_map); i++) { 455 if (strcmp(xtr_name, xtr_type_map[i].name) == 0) 456 return xtr_type_map[i].type; 457 } 458 459 return -1; 460 } 461 462 /* 463 * Parse elem, the elem could be single number/range or '(' ')' group 464 * 1) A single number elem, it's just a simple digit. e.g. 9 465 * 2) A single range elem, two digits with a '-' between. e.g. 2-6 466 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6) 467 * Within group elem, '-' used for a range separator; 468 * ',' used for a single number. 469 */ 470 static int 471 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs) 472 { 473 const char *str = input; 474 char *end = NULL; 475 uint32_t min, max; 476 uint32_t idx; 477 478 while (isblank(*str)) 479 str++; 480 481 if (!isdigit(*str) && *str != '(') 482 return -1; 483 484 /* process single number or single range of number */ 485 if (*str != '(') { 486 errno = 0; 487 idx = strtoul(str, &end, 10); 488 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 489 return -1; 490 491 while (isblank(*end)) 492 end++; 493 494 min = idx; 495 max = idx; 496 497 /* process single <number>-<number> */ 498 if (*end == '-') { 499 end++; 500 while (isblank(*end)) 501 end++; 502 if (!isdigit(*end)) 503 return -1; 504 505 errno = 0; 506 idx = strtoul(end, &end, 10); 507 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 508 return -1; 509 510 max = idx; 511 while (isblank(*end)) 512 end++; 513 } 514 515 if (*end != ':') 516 return -1; 517 518 for (idx = RTE_MIN(min, max); 519 idx <= RTE_MAX(min, max); idx++) 520 devargs->proto_xtr[idx] = xtr_type; 521 522 return 0; 523 } 524 525 /* process set within bracket */ 526 str++; 527 while (isblank(*str)) 528 str++; 529 if (*str == '\0') 530 return -1; 531 532 min = ICE_MAX_QUEUE_NUM; 533 do { 534 /* go ahead to the first digit */ 535 while (isblank(*str)) 536 str++; 537 if (!isdigit(*str)) 538 return -1; 539 540 /* get the digit value */ 541 errno = 0; 542 idx = strtoul(str, &end, 10); 543 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 544 return -1; 545 546 /* go ahead to separator '-',',' and ')' */ 547 while (isblank(*end)) 548 end++; 549 if (*end == '-') { 550 if (min == ICE_MAX_QUEUE_NUM) 551 min = idx; 552 else /* avoid continuous '-' */ 553 return -1; 554 } else if (*end == ',' || *end == ')') { 555 max = idx; 556 if (min == ICE_MAX_QUEUE_NUM) 557 min = idx; 558 559 for (idx = RTE_MIN(min, max); 560 idx <= RTE_MAX(min, max); idx++) 561 devargs->proto_xtr[idx] = xtr_type; 562 563 min = ICE_MAX_QUEUE_NUM; 564 } else { 565 return -1; 566 } 567 568 str = end + 1; 569 } while (*end != ')' && *end != '\0'); 570 571 return 0; 572 } 573 574 static int 575 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs) 576 { 577 const char *queue_start; 578 uint32_t idx; 579 int xtr_type; 580 char xtr_name[32]; 581 582 while (isblank(*queues)) 583 queues++; 584 585 if (*queues != '[') { 586 xtr_type = lookup_proto_xtr_type(queues); 587 if (xtr_type < 0) 588 return -1; 589 590 devargs->proto_xtr_dflt = xtr_type; 591 592 return 0; 593 } 594 595 queues++; 596 do { 597 while (isblank(*queues)) 598 queues++; 599 if (*queues == '\0') 600 return -1; 601 602 queue_start = queues; 603 604 /* go across a complete bracket */ 605 if (*queue_start == '(') { 606 queues += strcspn(queues, ")"); 607 if (*queues != ')') 608 return -1; 609 } 610 611 /* scan the separator ':' */ 612 queues += strcspn(queues, ":"); 613 if (*queues++ != ':') 614 return -1; 615 while (isblank(*queues)) 616 queues++; 617 618 for (idx = 0; ; idx++) { 619 if (isblank(queues[idx]) || 620 queues[idx] == ',' || 621 queues[idx] == ']' || 622 queues[idx] == '\0') 623 break; 624 625 if (idx > sizeof(xtr_name) - 2) 626 return -1; 627 628 xtr_name[idx] = queues[idx]; 629 } 630 xtr_name[idx] = '\0'; 631 xtr_type = lookup_proto_xtr_type(xtr_name); 632 if (xtr_type < 0) 633 return -1; 634 635 queues += idx; 636 637 while (isblank(*queues) || *queues == ',' || *queues == ']') 638 queues++; 639 640 if (parse_queue_set(queue_start, xtr_type, devargs) < 0) 641 return -1; 642 } while (*queues != '\0'); 643 644 return 0; 645 } 646 647 static int 648 handle_proto_xtr_arg(__rte_unused const char *key, const char *value, 649 void *extra_args) 650 { 651 struct ice_devargs *devargs = extra_args; 652 653 if (value == NULL || extra_args == NULL) 654 return -EINVAL; 655 656 if (parse_queue_proto_xtr(value, devargs) < 0) { 657 PMD_DRV_LOG(ERR, 658 "The protocol extraction parameter is wrong : '%s'", 659 value); 660 return -1; 661 } 662 663 return 0; 664 } 665 666 static int 667 handle_field_offs_arg(__rte_unused const char *key, const char *value, 668 void *offs_args) 669 { 670 uint8_t *offset = offs_args; 671 672 if (value == NULL || offs_args == NULL) 673 return -EINVAL; 674 675 if (!isdigit(*value)) 676 return -1; 677 678 *offset = atoi(value); 679 680 return 0; 681 } 682 683 static int 684 handle_field_name_arg(__rte_unused const char *key, const char *value, 685 void *name_args) 686 { 687 char *name = name_args; 688 int ret; 689 690 if (name == NULL || name_args == NULL) 691 return -EINVAL; 692 if (isdigit(*value)) 693 return -1; 694 695 ret = strlcpy(name, value, RTE_MBUF_DYN_NAMESIZE); 696 if (ret < 0 || ret >= RTE_MBUF_DYN_NAMESIZE) { 697 PMD_DRV_LOG(ERR, 698 "The protocol extraction field name too long : '%s'", 699 name); 700 return -1; 701 } 702 return 0; 703 } 704 705 static int 706 handle_ddp_filename_arg(__rte_unused const char *key, const char *value, void *name_args) 707 { 708 const char **filename = name_args; 709 if (strlen(value) >= ICE_MAX_PKG_FILENAME_SIZE) { 710 PMD_DRV_LOG(ERR, "The DDP package filename is too long : '%s'", value); 711 return -1; 712 } 713 *filename = strdup(value); 714 return 0; 715 } 716 717 static void 718 ice_check_proto_xtr_support(struct ice_hw *hw) 719 { 720 #define FLX_REG(val, fld, idx) \ 721 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \ 722 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S) 723 static struct { 724 uint32_t rxdid; 725 uint8_t opcode; 726 uint8_t protid_0; 727 uint8_t protid_1; 728 } xtr_sets[] = { 729 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN, 730 ICE_RX_OPC_EXTRACT, 731 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O}, 732 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4, 733 ICE_RX_OPC_EXTRACT, 734 ICE_PROT_IPV4_OF_OR_S, 735 ICE_PROT_IPV4_OF_OR_S }, 736 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6, 737 ICE_RX_OPC_EXTRACT, 738 ICE_PROT_IPV6_OF_OR_S, 739 ICE_PROT_IPV6_OF_OR_S }, 740 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW, 741 ICE_RX_OPC_EXTRACT, 742 ICE_PROT_IPV6_OF_OR_S, 743 ICE_PROT_IPV6_OF_OR_S }, 744 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP, 745 ICE_RX_OPC_EXTRACT, 746 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL }, 747 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET, 748 ICE_RX_OPC_PROTID, 749 ICE_PROT_IPV4_OF_OR_S, 750 ICE_PROT_IPV6_OF_OR_S }, 751 }; 752 uint32_t i; 753 754 for (i = 0; i < RTE_DIM(xtr_sets); i++) { 755 uint32_t rxdid = xtr_sets[i].rxdid; 756 uint32_t v; 757 758 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) { 759 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid)); 760 761 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 && 762 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode) 763 ice_proto_xtr_hw_support[i] = true; 764 } 765 766 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) { 767 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid)); 768 769 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 && 770 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode) 771 ice_proto_xtr_hw_support[i] = true; 772 } 773 } 774 } 775 776 static int 777 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 778 uint32_t num) 779 { 780 struct pool_entry *entry; 781 782 if (!pool || !num) 783 return -EINVAL; 784 785 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 786 if (!entry) { 787 PMD_INIT_LOG(ERR, 788 "Failed to allocate memory for resource pool"); 789 return -ENOMEM; 790 } 791 792 /* queue heap initialize */ 793 pool->num_free = num; 794 pool->num_alloc = 0; 795 pool->base = base; 796 LIST_INIT(&pool->alloc_list); 797 LIST_INIT(&pool->free_list); 798 799 /* Initialize element */ 800 entry->base = 0; 801 entry->len = num; 802 803 LIST_INSERT_HEAD(&pool->free_list, entry, next); 804 return 0; 805 } 806 807 static int 808 ice_res_pool_alloc(struct ice_res_pool_info *pool, 809 uint16_t num) 810 { 811 struct pool_entry *entry, *valid_entry; 812 813 if (!pool || !num) { 814 PMD_INIT_LOG(ERR, "Invalid parameter"); 815 return -EINVAL; 816 } 817 818 if (pool->num_free < num) { 819 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 820 num, pool->num_free); 821 return -ENOMEM; 822 } 823 824 valid_entry = NULL; 825 /* Lookup in free list and find most fit one */ 826 LIST_FOREACH(entry, &pool->free_list, next) { 827 if (entry->len >= num) { 828 /* Find best one */ 829 if (entry->len == num) { 830 valid_entry = entry; 831 break; 832 } 833 if (!valid_entry || 834 valid_entry->len > entry->len) 835 valid_entry = entry; 836 } 837 } 838 839 /* Not find one to satisfy the request, return */ 840 if (!valid_entry) { 841 PMD_INIT_LOG(ERR, "No valid entry found"); 842 return -ENOMEM; 843 } 844 /** 845 * The entry have equal queue number as requested, 846 * remove it from alloc_list. 847 */ 848 if (valid_entry->len == num) { 849 LIST_REMOVE(valid_entry, next); 850 } else { 851 /** 852 * The entry have more numbers than requested, 853 * create a new entry for alloc_list and minus its 854 * queue base and number in free_list. 855 */ 856 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 857 if (!entry) { 858 PMD_INIT_LOG(ERR, 859 "Failed to allocate memory for " 860 "resource pool"); 861 return -ENOMEM; 862 } 863 entry->base = valid_entry->base; 864 entry->len = num; 865 valid_entry->base += num; 866 valid_entry->len -= num; 867 valid_entry = entry; 868 } 869 870 /* Insert it into alloc list, not sorted */ 871 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 872 873 pool->num_free -= valid_entry->len; 874 pool->num_alloc += valid_entry->len; 875 876 return valid_entry->base + pool->base; 877 } 878 879 static void 880 ice_res_pool_destroy(struct ice_res_pool_info *pool) 881 { 882 struct pool_entry *entry, *next_entry; 883 884 if (!pool) 885 return; 886 887 for (entry = LIST_FIRST(&pool->alloc_list); 888 entry && (next_entry = LIST_NEXT(entry, next), 1); 889 entry = next_entry) { 890 LIST_REMOVE(entry, next); 891 rte_free(entry); 892 } 893 894 for (entry = LIST_FIRST(&pool->free_list); 895 entry && (next_entry = LIST_NEXT(entry, next), 1); 896 entry = next_entry) { 897 LIST_REMOVE(entry, next); 898 rte_free(entry); 899 } 900 901 pool->num_free = 0; 902 pool->num_alloc = 0; 903 pool->base = 0; 904 LIST_INIT(&pool->alloc_list); 905 LIST_INIT(&pool->free_list); 906 } 907 908 static void 909 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 910 { 911 /* Set VSI LUT selection */ 912 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 913 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 914 /* Set Hash scheme */ 915 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 916 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 917 /* enable TC */ 918 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 919 } 920 921 static int 922 ice_vsi_config_tc_queue_mapping(struct ice_hw *hw, struct ice_vsi *vsi, 923 struct ice_aqc_vsi_props *info, 924 uint8_t enabled_tcmap) 925 { 926 uint16_t fls, qp_idx; 927 928 /* default tc 0 now. Multi-TC supporting need to be done later. 929 * Configure TC and queue mapping parameters, for enabled TC, 930 * allocate qpnum_per_tc queues to this traffic. 931 */ 932 if (enabled_tcmap != 0x01) { 933 PMD_INIT_LOG(ERR, "only TC0 is supported"); 934 return -ENOTSUP; 935 } 936 937 /* vector 0 is reserved and 1 vector for ctrl vsi */ 938 if (vsi->adapter->hw.func_caps.common_cap.num_msix_vectors < 2) { 939 vsi->nb_qps = 0; 940 } else { 941 vsi->nb_qps = RTE_MIN 942 ((uint16_t)vsi->adapter->hw.func_caps.common_cap.num_msix_vectors - 2, 943 RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC)); 944 945 /* cap max QPs to what the HW reports as num-children for each layer. 946 * Multiply num_children for each layer from the entry_point layer to 947 * the qgroup, or second-last layer. 948 * Avoid any potential overflow by using uint32_t type and breaking loop 949 * once we have a number greater than the already configured max. 950 */ 951 uint32_t max_sched_vsi_nodes = 1; 952 for (uint8_t i = hw->sw_entry_point_layer; i < hw->num_tx_sched_layers - 1; i++) { 953 max_sched_vsi_nodes *= hw->max_children[i]; 954 if (max_sched_vsi_nodes >= vsi->nb_qps) 955 break; 956 } 957 vsi->nb_qps = RTE_MIN(vsi->nb_qps, max_sched_vsi_nodes); 958 } 959 960 /* nb_qps(hex) -> fls */ 961 /* 0000 -> 0 */ 962 /* 0001 -> 0 */ 963 /* 0002 -> 1 */ 964 /* 0003 ~ 0004 -> 2 */ 965 /* 0005 ~ 0008 -> 3 */ 966 /* 0009 ~ 0010 -> 4 */ 967 /* 0011 ~ 0020 -> 5 */ 968 /* 0021 ~ 0040 -> 6 */ 969 /* 0041 ~ 0080 -> 7 */ 970 /* 0081 ~ 0100 -> 8 */ 971 fls = (vsi->nb_qps == 0) ? 0 : rte_fls_u32(vsi->nb_qps - 1); 972 973 qp_idx = 0; 974 /* Set tc and queue mapping with VSI */ 975 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 976 ICE_AQ_VSI_TC_Q_OFFSET_S) | 977 (fls << ICE_AQ_VSI_TC_Q_NUM_S)); 978 979 /* Associate queue number with VSI */ 980 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 981 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 982 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 983 info->valid_sections |= 984 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 985 /* Set the info.ingress_table and info.egress_table 986 * for UP translate table. Now just set it to 1:1 map by default 987 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 988 */ 989 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 990 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 991 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 992 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 993 return 0; 994 } 995 996 static int 997 ice_init_mac_address(struct rte_eth_dev *dev) 998 { 999 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1000 struct ice_adapter *ad = (struct ice_adapter *)hw->back; 1001 1002 if (!rte_is_unicast_ether_addr 1003 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) { 1004 PMD_INIT_LOG(ERR, "Invalid MAC address"); 1005 return -EINVAL; 1006 } 1007 1008 rte_ether_addr_copy( 1009 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr, 1010 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); 1011 1012 dev->data->mac_addrs = 1013 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0); 1014 if (!dev->data->mac_addrs) { 1015 PMD_INIT_LOG(ERR, 1016 "Failed to allocate memory to store mac address"); 1017 return -ENOMEM; 1018 } 1019 /* store it to dev data */ 1020 if (ad->devargs.default_mac_disable != 1) 1021 rte_ether_addr_copy((struct rte_ether_addr *)hw->port_info[0].mac.perm_addr, 1022 &dev->data->mac_addrs[0]); 1023 return 0; 1024 } 1025 1026 /* Find out specific MAC filter */ 1027 static struct ice_mac_filter * 1028 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr) 1029 { 1030 struct ice_mac_filter *f; 1031 1032 TAILQ_FOREACH(f, &vsi->mac_list, next) { 1033 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 1034 return f; 1035 } 1036 1037 return NULL; 1038 } 1039 1040 static int 1041 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 1042 { 1043 struct ice_fltr_list_entry *m_list_itr = NULL; 1044 struct ice_mac_filter *f; 1045 struct LIST_HEAD_TYPE list_head; 1046 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1047 struct ice_adapter *ad = (struct ice_adapter *)hw->back; 1048 int ret = 0; 1049 1050 if (ad->devargs.default_mac_disable == 1 && rte_is_same_ether_addr(mac_addr, 1051 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr)) { 1052 PMD_DRV_LOG(ERR, "This Default MAC filter is disabled."); 1053 return 0; 1054 } 1055 /* If it's added and configured, return */ 1056 f = ice_find_mac_filter(vsi, mac_addr); 1057 if (f) { 1058 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 1059 return 0; 1060 } 1061 1062 INIT_LIST_HEAD(&list_head); 1063 1064 m_list_itr = (struct ice_fltr_list_entry *) 1065 ice_malloc(hw, sizeof(*m_list_itr)); 1066 if (!m_list_itr) { 1067 ret = -ENOMEM; 1068 goto DONE; 1069 } 1070 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 1071 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 1072 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1073 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1074 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 1075 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 1076 m_list_itr->fltr_info.vsi_handle = vsi->idx; 1077 1078 LIST_ADD(&m_list_itr->list_entry, &list_head); 1079 1080 /* Add the mac */ 1081 ret = ice_add_mac(hw, &list_head); 1082 if (ret != ICE_SUCCESS) { 1083 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 1084 ret = -EINVAL; 1085 goto DONE; 1086 } 1087 /* Add the mac addr into mac list */ 1088 f = rte_zmalloc(NULL, sizeof(*f), 0); 1089 if (!f) { 1090 PMD_DRV_LOG(ERR, "failed to allocate memory"); 1091 ret = -ENOMEM; 1092 goto DONE; 1093 } 1094 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr); 1095 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 1096 vsi->mac_num++; 1097 1098 ret = 0; 1099 1100 DONE: 1101 rte_free(m_list_itr); 1102 return ret; 1103 } 1104 1105 static int 1106 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 1107 { 1108 struct ice_fltr_list_entry *m_list_itr = NULL; 1109 struct ice_mac_filter *f; 1110 struct LIST_HEAD_TYPE list_head; 1111 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1112 int ret = 0; 1113 1114 /* Can't find it, return an error */ 1115 f = ice_find_mac_filter(vsi, mac_addr); 1116 if (!f) 1117 return -EINVAL; 1118 1119 INIT_LIST_HEAD(&list_head); 1120 1121 m_list_itr = (struct ice_fltr_list_entry *) 1122 ice_malloc(hw, sizeof(*m_list_itr)); 1123 if (!m_list_itr) { 1124 ret = -ENOMEM; 1125 goto DONE; 1126 } 1127 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 1128 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 1129 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1130 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1131 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 1132 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 1133 m_list_itr->fltr_info.vsi_handle = vsi->idx; 1134 1135 LIST_ADD(&m_list_itr->list_entry, &list_head); 1136 1137 /* remove the mac filter */ 1138 ret = ice_remove_mac(hw, &list_head); 1139 if (ret != ICE_SUCCESS) { 1140 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 1141 ret = -EINVAL; 1142 goto DONE; 1143 } 1144 1145 /* Remove the mac addr from mac list */ 1146 TAILQ_REMOVE(&vsi->mac_list, f, next); 1147 rte_free(f); 1148 vsi->mac_num--; 1149 1150 ret = 0; 1151 DONE: 1152 rte_free(m_list_itr); 1153 return ret; 1154 } 1155 1156 /* Find out specific VLAN filter */ 1157 static struct ice_vlan_filter * 1158 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan) 1159 { 1160 struct ice_vlan_filter *f; 1161 1162 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 1163 if (vlan->tpid == f->vlan_info.vlan.tpid && 1164 vlan->vid == f->vlan_info.vlan.vid) 1165 return f; 1166 } 1167 1168 return NULL; 1169 } 1170 1171 static int 1172 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan) 1173 { 1174 struct ice_fltr_list_entry *v_list_itr = NULL; 1175 struct ice_vlan_filter *f; 1176 struct LIST_HEAD_TYPE list_head; 1177 struct ice_hw *hw; 1178 int ret = 0; 1179 1180 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID) 1181 return -EINVAL; 1182 1183 hw = ICE_VSI_TO_HW(vsi); 1184 1185 /* If it's added and configured, return. */ 1186 f = ice_find_vlan_filter(vsi, vlan); 1187 if (f) { 1188 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 1189 return 0; 1190 } 1191 1192 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 1193 return 0; 1194 1195 INIT_LIST_HEAD(&list_head); 1196 1197 v_list_itr = (struct ice_fltr_list_entry *) 1198 ice_malloc(hw, sizeof(*v_list_itr)); 1199 if (!v_list_itr) { 1200 ret = -ENOMEM; 1201 goto DONE; 1202 } 1203 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid; 1204 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid; 1205 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true; 1206 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1207 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1208 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 1209 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 1210 v_list_itr->fltr_info.vsi_handle = vsi->idx; 1211 1212 LIST_ADD(&v_list_itr->list_entry, &list_head); 1213 1214 /* Add the vlan */ 1215 ret = ice_add_vlan(hw, &list_head); 1216 if (ret != ICE_SUCCESS) { 1217 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 1218 ret = -EINVAL; 1219 goto DONE; 1220 } 1221 1222 /* Add vlan into vlan list */ 1223 f = rte_zmalloc(NULL, sizeof(*f), 0); 1224 if (!f) { 1225 PMD_DRV_LOG(ERR, "failed to allocate memory"); 1226 ret = -ENOMEM; 1227 goto DONE; 1228 } 1229 f->vlan_info.vlan.tpid = vlan->tpid; 1230 f->vlan_info.vlan.vid = vlan->vid; 1231 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 1232 vsi->vlan_num++; 1233 1234 ret = 0; 1235 1236 DONE: 1237 rte_free(v_list_itr); 1238 return ret; 1239 } 1240 1241 static int 1242 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan) 1243 { 1244 struct ice_fltr_list_entry *v_list_itr = NULL; 1245 struct ice_vlan_filter *f; 1246 struct LIST_HEAD_TYPE list_head; 1247 struct ice_hw *hw; 1248 int ret = 0; 1249 1250 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID) 1251 return -EINVAL; 1252 1253 hw = ICE_VSI_TO_HW(vsi); 1254 1255 /* Can't find it, return an error */ 1256 f = ice_find_vlan_filter(vsi, vlan); 1257 if (!f) 1258 return -EINVAL; 1259 1260 INIT_LIST_HEAD(&list_head); 1261 1262 v_list_itr = (struct ice_fltr_list_entry *) 1263 ice_malloc(hw, sizeof(*v_list_itr)); 1264 if (!v_list_itr) { 1265 ret = -ENOMEM; 1266 goto DONE; 1267 } 1268 1269 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid; 1270 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid; 1271 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true; 1272 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1273 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1274 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 1275 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 1276 v_list_itr->fltr_info.vsi_handle = vsi->idx; 1277 1278 LIST_ADD(&v_list_itr->list_entry, &list_head); 1279 1280 /* remove the vlan filter */ 1281 ret = ice_remove_vlan(hw, &list_head); 1282 if (ret != ICE_SUCCESS) { 1283 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 1284 ret = -EINVAL; 1285 goto DONE; 1286 } 1287 1288 /* Remove the vlan id from vlan list */ 1289 TAILQ_REMOVE(&vsi->vlan_list, f, next); 1290 rte_free(f); 1291 vsi->vlan_num--; 1292 1293 ret = 0; 1294 DONE: 1295 rte_free(v_list_itr); 1296 return ret; 1297 } 1298 1299 static int 1300 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 1301 { 1302 struct ice_mac_filter *m_f; 1303 struct ice_vlan_filter *v_f; 1304 void *temp; 1305 int ret = 0; 1306 1307 if (!vsi || !vsi->mac_num) 1308 return -EINVAL; 1309 1310 RTE_TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) { 1311 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 1312 if (ret != ICE_SUCCESS) { 1313 ret = -EINVAL; 1314 goto DONE; 1315 } 1316 } 1317 1318 if (vsi->vlan_num == 0) 1319 return 0; 1320 1321 RTE_TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) { 1322 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan); 1323 if (ret != ICE_SUCCESS) { 1324 ret = -EINVAL; 1325 goto DONE; 1326 } 1327 } 1328 1329 DONE: 1330 return ret; 1331 } 1332 1333 /* Enable IRQ0 */ 1334 static void 1335 ice_pf_enable_irq0(struct ice_hw *hw) 1336 { 1337 /* reset the registers */ 1338 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 1339 ICE_READ_REG(hw, PFINT_OICR); 1340 1341 #ifdef ICE_LSE_SPT 1342 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 1343 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 1344 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 1345 1346 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 1347 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 1348 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 1349 PFINT_OICR_CTL_ITR_INDX_M) | 1350 PFINT_OICR_CTL_CAUSE_ENA_M); 1351 1352 ICE_WRITE_REG(hw, PFINT_FW_CTL, 1353 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 1354 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 1355 PFINT_FW_CTL_ITR_INDX_M) | 1356 PFINT_FW_CTL_CAUSE_ENA_M); 1357 #else 1358 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 1359 #endif 1360 1361 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1362 GLINT_DYN_CTL_INTENA_M | 1363 GLINT_DYN_CTL_CLEARPBA_M | 1364 GLINT_DYN_CTL_ITR_INDX_M); 1365 1366 ice_flush(hw); 1367 } 1368 1369 /* Disable IRQ0 */ 1370 static void 1371 ice_pf_disable_irq0(struct ice_hw *hw) 1372 { 1373 /* Disable all interrupt types */ 1374 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1375 ice_flush(hw); 1376 } 1377 1378 #ifdef ICE_LSE_SPT 1379 static void 1380 ice_handle_aq_msg(struct rte_eth_dev *dev) 1381 { 1382 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1383 struct ice_ctl_q_info *cq = &hw->adminq; 1384 struct ice_rq_event_info event; 1385 uint16_t pending, opcode; 1386 int ret; 1387 1388 event.buf_len = ICE_AQ_MAX_BUF_LEN; 1389 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 1390 if (!event.msg_buf) { 1391 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 1392 return; 1393 } 1394 1395 pending = 1; 1396 while (pending) { 1397 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 1398 1399 if (ret != ICE_SUCCESS) { 1400 PMD_DRV_LOG(INFO, 1401 "Failed to read msg from AdminQ, " 1402 "adminq_err: %u", 1403 hw->adminq.sq_last_status); 1404 break; 1405 } 1406 opcode = rte_le_to_cpu_16(event.desc.opcode); 1407 1408 switch (opcode) { 1409 case ice_aqc_opc_get_link_status: 1410 ret = ice_link_update(dev, 0); 1411 if (!ret) 1412 rte_eth_dev_callback_process 1413 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1414 break; 1415 default: 1416 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 1417 opcode); 1418 break; 1419 } 1420 } 1421 rte_free(event.msg_buf); 1422 } 1423 #endif 1424 1425 /** 1426 * Interrupt handler triggered by NIC for handling 1427 * specific interrupt. 1428 * 1429 * @param handle 1430 * Pointer to interrupt handle. 1431 * @param param 1432 * The address of parameter (struct rte_eth_dev *) registered before. 1433 * 1434 * @return 1435 * void 1436 */ 1437 static void 1438 ice_interrupt_handler(void *param) 1439 { 1440 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1441 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1442 uint32_t oicr; 1443 uint32_t reg; 1444 uint8_t pf_num; 1445 uint8_t event; 1446 uint16_t queue; 1447 int ret; 1448 #ifdef ICE_LSE_SPT 1449 uint32_t int_fw_ctl; 1450 #endif 1451 1452 /* Disable interrupt */ 1453 ice_pf_disable_irq0(hw); 1454 1455 /* read out interrupt causes */ 1456 oicr = ICE_READ_REG(hw, PFINT_OICR); 1457 #ifdef ICE_LSE_SPT 1458 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1459 #endif 1460 1461 /* No interrupt event indicated */ 1462 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1463 PMD_DRV_LOG(INFO, "No interrupt event"); 1464 goto done; 1465 } 1466 1467 #ifdef ICE_LSE_SPT 1468 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1469 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1470 ice_handle_aq_msg(dev); 1471 } 1472 #else 1473 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1474 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1475 ret = ice_link_update(dev, 0); 1476 if (!ret) 1477 rte_eth_dev_callback_process 1478 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1479 } 1480 #endif 1481 1482 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1483 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1484 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1485 if (reg & GL_MDET_TX_PQM_VALID_M) { 1486 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1487 GL_MDET_TX_PQM_PF_NUM_S; 1488 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1489 GL_MDET_TX_PQM_MAL_TYPE_S; 1490 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1491 GL_MDET_TX_PQM_QNUM_S; 1492 1493 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1494 "%d by PQM on TX queue %d PF# %d", 1495 event, queue, pf_num); 1496 } 1497 1498 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1499 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1500 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1501 GL_MDET_TX_TCLAN_PF_NUM_S; 1502 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1503 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1504 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1505 GL_MDET_TX_TCLAN_QNUM_S; 1506 1507 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1508 "%d by TCLAN on TX queue %d PF# %d", 1509 event, queue, pf_num); 1510 } 1511 1512 reg = ICE_READ_REG(hw, GL_MDET_TX_TDPU); 1513 if (reg & GL_MDET_TX_TDPU_VALID_M) { 1514 pf_num = (reg & GL_MDET_TX_TDPU_PF_NUM_M) >> 1515 GL_MDET_TX_TDPU_PF_NUM_S; 1516 event = (reg & GL_MDET_TX_TDPU_MAL_TYPE_M) >> 1517 GL_MDET_TX_TDPU_MAL_TYPE_S; 1518 queue = (reg & GL_MDET_TX_TDPU_QNUM_M) >> 1519 GL_MDET_TX_TDPU_QNUM_S; 1520 1521 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1522 "%d by TDPU on TX queue %d PF# %d", 1523 event, queue, pf_num); 1524 } 1525 } 1526 done: 1527 /* Enable interrupt */ 1528 ice_pf_enable_irq0(hw); 1529 rte_intr_ack(dev->intr_handle); 1530 } 1531 1532 static void 1533 ice_init_proto_xtr(struct rte_eth_dev *dev) 1534 { 1535 struct ice_adapter *ad = 1536 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1537 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1538 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1539 const struct proto_xtr_ol_flag *ol_flag; 1540 bool proto_xtr_enable = false; 1541 int offset, field_offs; 1542 uint16_t i; 1543 1544 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0); 1545 if (unlikely(pf->proto_xtr == NULL)) { 1546 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table"); 1547 return; 1548 } 1549 1550 for (i = 0; i < pf->lan_nb_qps; i++) { 1551 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ? 1552 ad->devargs.proto_xtr[i] : 1553 ad->devargs.proto_xtr_dflt; 1554 1555 if (pf->proto_xtr[i] != PROTO_XTR_NONE) { 1556 uint8_t type = pf->proto_xtr[i]; 1557 1558 ice_proto_xtr_ol_flag_params[type].required = true; 1559 proto_xtr_enable = true; 1560 } 1561 } 1562 1563 if (likely(!proto_xtr_enable)) { 1564 ad->devargs.xtr_field_offs = -1; 1565 return; 1566 } 1567 1568 ice_check_proto_xtr_support(hw); 1569 1570 /*check mbuf dynfield*/ 1571 field_offs = rte_mbuf_dynfield_lookup(ad->devargs.xtr_field_name, NULL); 1572 if (ad->devargs.xtr_field_offs == field_offs) { 1573 PMD_DRV_LOG(DEBUG, 1574 "Protocol extraction metadata offset in mbuf is : %d", 1575 ad->devargs.xtr_field_offs); 1576 } else { 1577 PMD_DRV_LOG(ERR, "Invalid field offset or name, no match dynfield, [%d],[%s]", 1578 ad->devargs.xtr_field_offs, ad->devargs.xtr_field_name); 1579 ad->devargs.xtr_field_offs = -1; 1580 return; 1581 } 1582 1583 PMD_DRV_LOG(DEBUG, 1584 "Protocol extraction metadata offset in mbuf is : %d", 1585 ad->devargs.xtr_field_offs); 1586 1587 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) { 1588 ol_flag = &ice_proto_xtr_ol_flag_params[i]; 1589 1590 ad->devargs.xtr_flag_offs[i] = 0xff; 1591 1592 if (!ol_flag->required) 1593 continue; 1594 1595 if (!ice_proto_xtr_hw_support[i]) { 1596 PMD_DRV_LOG(ERR, 1597 "Protocol extraction type %u is not supported in hardware", 1598 i); 1599 ad->devargs.xtr_field_offs = -1; 1600 break; 1601 } 1602 1603 offset = rte_mbuf_dynflag_register(&ol_flag->param); 1604 if (unlikely(offset == -1)) { 1605 PMD_DRV_LOG(ERR, 1606 "Protocol extraction offload '%s' failed to register with error %d", 1607 ol_flag->param.name, -rte_errno); 1608 1609 ad->devargs.xtr_field_offs = -1; 1610 break; 1611 } 1612 1613 PMD_DRV_LOG(DEBUG, 1614 "Protocol extraction offload '%s' offset in mbuf is : %d", 1615 ol_flag->param.name, offset); 1616 1617 ad->devargs.xtr_flag_offs[i] = offset; 1618 } 1619 } 1620 1621 /* Initialize SW parameters of PF */ 1622 static int 1623 ice_pf_sw_init(struct rte_eth_dev *dev) 1624 { 1625 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1626 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1627 1628 pf->lan_nb_qp_max = 1629 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1630 hw->func_caps.common_cap.num_rxq); 1631 1632 pf->lan_nb_qps = pf->lan_nb_qp_max; 1633 1634 ice_init_proto_xtr(dev); 1635 1636 if (hw->func_caps.fd_fltr_guar > 0 || 1637 hw->func_caps.fd_fltr_best_effort > 0) { 1638 pf->flags |= ICE_FLAG_FDIR; 1639 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR; 1640 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps; 1641 } else { 1642 pf->fdir_nb_qps = 0; 1643 } 1644 pf->fdir_qp_offset = 0; 1645 1646 return 0; 1647 } 1648 1649 struct ice_vsi * 1650 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1651 { 1652 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1653 struct ice_vsi *vsi = NULL; 1654 struct ice_vsi_ctx vsi_ctx; 1655 int ret; 1656 struct rte_ether_addr broadcast = { 1657 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1658 struct rte_ether_addr mac_addr; 1659 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1660 uint8_t tc_bitmap = 0x1; 1661 uint16_t cfg; 1662 1663 /* hw->num_lports = 1 in NIC mode */ 1664 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1665 if (!vsi) 1666 return NULL; 1667 1668 vsi->idx = pf->next_vsi_idx; 1669 pf->next_vsi_idx++; 1670 vsi->type = type; 1671 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1672 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1673 vsi->vlan_anti_spoof_on = 0; 1674 vsi->vlan_filter_on = 1; 1675 TAILQ_INIT(&vsi->mac_list); 1676 TAILQ_INIT(&vsi->vlan_list); 1677 1678 /* Be sync with RTE_ETH_RSS_RETA_SIZE_x maximum value definition */ 1679 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > 1680 RTE_ETH_RSS_RETA_SIZE_512 ? RTE_ETH_RSS_RETA_SIZE_512 : 1681 hw->func_caps.common_cap.rss_table_size; 1682 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; 1683 1684 /* Defines the type of outer tag expected */ 1685 pf->outer_ethertype = RTE_ETHER_TYPE_VLAN; 1686 1687 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1688 switch (type) { 1689 case ICE_VSI_PF: 1690 vsi->nb_qps = pf->lan_nb_qps; 1691 vsi->base_queue = 1; 1692 ice_vsi_config_default_rss(&vsi_ctx.info); 1693 vsi_ctx.alloc_from_pool = true; 1694 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1695 /* switch_id is queried by get_switch_config aq, which is done 1696 * by ice_init_hw 1697 */ 1698 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1699 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1700 /* Allow all untagged or tagged packets */ 1701 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; 1702 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; 1703 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1704 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1705 if (ice_is_dvm_ena(hw)) { 1706 vsi_ctx.info.outer_vlan_flags = 1707 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL << 1708 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) & 1709 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M; 1710 vsi_ctx.info.outer_vlan_flags |= 1711 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 << 1712 ICE_AQ_VSI_OUTER_TAG_TYPE_S) & 1713 ICE_AQ_VSI_OUTER_TAG_TYPE_M; 1714 vsi_ctx.info.outer_vlan_flags |= 1715 (ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING << 1716 ICE_AQ_VSI_OUTER_VLAN_EMODE_S); 1717 } 1718 1719 /* FDIR */ 1720 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID | 1721 ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1722 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1723 cfg = ICE_AQ_VSI_FD_ENABLE; 1724 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1725 vsi_ctx.info.max_fd_fltr_dedicated = 1726 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar); 1727 vsi_ctx.info.max_fd_fltr_shared = 1728 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort); 1729 1730 /* Enable VLAN/UP trip */ 1731 ret = ice_vsi_config_tc_queue_mapping(hw, vsi, 1732 &vsi_ctx.info, 1733 ICE_DEFAULT_TCMAP); 1734 if (ret) { 1735 PMD_INIT_LOG(ERR, 1736 "tc queue mapping with vsi failed, " 1737 "err = %d", 1738 ret); 1739 goto fail_mem; 1740 } 1741 1742 break; 1743 case ICE_VSI_CTRL: 1744 vsi->nb_qps = pf->fdir_nb_qps; 1745 vsi->base_queue = ICE_FDIR_QUEUE_ID; 1746 vsi_ctx.alloc_from_pool = true; 1747 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1748 1749 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1750 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1751 cfg = ICE_AQ_VSI_FD_PROG_ENABLE; 1752 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1753 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1754 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1755 ret = ice_vsi_config_tc_queue_mapping(hw, vsi, 1756 &vsi_ctx.info, 1757 ICE_DEFAULT_TCMAP); 1758 if (ret) { 1759 PMD_INIT_LOG(ERR, 1760 "tc queue mapping with vsi failed, " 1761 "err = %d", 1762 ret); 1763 goto fail_mem; 1764 } 1765 break; 1766 default: 1767 /* for other types of VSI */ 1768 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1769 goto fail_mem; 1770 } 1771 1772 /* VF has MSIX interrupt in VF range, don't allocate here */ 1773 if (type == ICE_VSI_PF) { 1774 ret = ice_res_pool_alloc(&pf->msix_pool, 1775 RTE_MIN(vsi->nb_qps, 1776 RTE_MAX_RXTX_INTR_VEC_ID)); 1777 if (ret < 0) { 1778 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1779 vsi->vsi_id, ret); 1780 } 1781 vsi->msix_intr = ret; 1782 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1783 } else if (type == ICE_VSI_CTRL) { 1784 ret = ice_res_pool_alloc(&pf->msix_pool, 1); 1785 if (ret < 0) { 1786 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", 1787 vsi->vsi_id, ret); 1788 } 1789 vsi->msix_intr = ret; 1790 vsi->nb_msix = 1; 1791 } else { 1792 vsi->msix_intr = 0; 1793 vsi->nb_msix = 0; 1794 } 1795 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1796 if (ret != ICE_SUCCESS) { 1797 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1798 goto fail_mem; 1799 } 1800 /* store vsi information is SW structure */ 1801 vsi->vsi_id = vsi_ctx.vsi_num; 1802 vsi->info = vsi_ctx.info; 1803 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1804 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1805 1806 if (type == ICE_VSI_PF) { 1807 /* MAC configuration */ 1808 rte_ether_addr_copy((struct rte_ether_addr *) 1809 hw->port_info->mac.perm_addr, 1810 &pf->dev_addr); 1811 1812 rte_ether_addr_copy(&pf->dev_addr, &mac_addr); 1813 ret = ice_add_mac_filter(vsi, &mac_addr); 1814 if (ret != ICE_SUCCESS) 1815 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1816 1817 rte_ether_addr_copy(&broadcast, &mac_addr); 1818 ret = ice_add_mac_filter(vsi, &mac_addr); 1819 if (ret != ICE_SUCCESS) 1820 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1821 } 1822 1823 /* At the beginning, only TC0. */ 1824 /* What we need here is the maximum number of the TX queues. 1825 * Currently vsi->nb_qps means it. 1826 * Correct it if any change. 1827 */ 1828 max_txqs[0] = vsi->nb_qps; 1829 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1830 tc_bitmap, max_txqs); 1831 if (ret != ICE_SUCCESS) 1832 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1833 1834 return vsi; 1835 fail_mem: 1836 rte_free(vsi); 1837 pf->next_vsi_idx--; 1838 return NULL; 1839 } 1840 1841 static int 1842 ice_send_driver_ver(struct ice_hw *hw) 1843 { 1844 struct ice_driver_ver dv; 1845 1846 /* we don't have driver version use 0 for dummy */ 1847 dv.major_ver = 0; 1848 dv.minor_ver = 0; 1849 dv.build_ver = 0; 1850 dv.subbuild_ver = 0; 1851 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1852 1853 return ice_aq_send_driver_ver(hw, &dv, NULL); 1854 } 1855 1856 static int 1857 ice_pf_setup(struct ice_pf *pf) 1858 { 1859 struct ice_adapter *ad = ICE_PF_TO_ADAPTER(pf); 1860 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1861 struct ice_vsi *vsi; 1862 uint16_t unused; 1863 1864 /* Clear all stats counters */ 1865 pf->offset_loaded = false; 1866 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1867 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1868 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1869 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1870 1871 /* force guaranteed filter pool for PF */ 1872 ice_alloc_fd_guar_item(hw, &unused, 1873 hw->func_caps.fd_fltr_guar); 1874 /* force shared filter pool for PF */ 1875 ice_alloc_fd_shrd_item(hw, &unused, 1876 hw->func_caps.fd_fltr_best_effort); 1877 1878 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1879 if (!vsi) { 1880 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1881 return -EINVAL; 1882 } 1883 1884 /* set the number of hidden Tx scheduler layers. If no devargs parameter to 1885 * set the number of exposed levels, the default is to expose all levels, 1886 * except the TC layer. 1887 * 1888 * If the number of exposed levels is set, we check that it's not greater 1889 * than the HW can provide (in which case we do nothing except log a warning), 1890 * and then set the hidden layers to be the total number of levels minus the 1891 * requested visible number. 1892 */ 1893 pf->tm_conf.hidden_layers = hw->port_info->has_tc; 1894 if (ad->devargs.tm_exposed_levels != 0) { 1895 const uint8_t avail_layers = hw->num_tx_sched_layers - hw->port_info->has_tc; 1896 const uint8_t req_layers = ad->devargs.tm_exposed_levels; 1897 if (req_layers > avail_layers) { 1898 PMD_INIT_LOG(WARNING, "The number of TM scheduler exposed levels exceeds the number of supported levels (%u)", 1899 avail_layers); 1900 PMD_INIT_LOG(WARNING, "Setting scheduler layers to %u", avail_layers); 1901 } else { 1902 pf->tm_conf.hidden_layers = hw->num_tx_sched_layers - req_layers; 1903 } 1904 } 1905 1906 pf->main_vsi = vsi; 1907 rte_spinlock_init(&pf->link_lock); 1908 1909 return 0; 1910 } 1911 1912 static enum ice_pkg_type 1913 ice_load_pkg_type(struct ice_hw *hw) 1914 { 1915 enum ice_pkg_type package_type; 1916 1917 /* store the activated package type (OS default or Comms) */ 1918 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME, 1919 ICE_PKG_NAME_SIZE)) 1920 package_type = ICE_PKG_TYPE_OS_DEFAULT; 1921 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME, 1922 ICE_PKG_NAME_SIZE)) 1923 package_type = ICE_PKG_TYPE_COMMS; 1924 else 1925 package_type = ICE_PKG_TYPE_UNKNOWN; 1926 1927 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)", 1928 hw->active_pkg_ver.major, hw->active_pkg_ver.minor, 1929 hw->active_pkg_ver.update, hw->active_pkg_ver.draft, 1930 hw->active_pkg_name, 1931 ice_is_dvm_ena(hw) ? "double" : "single"); 1932 1933 return package_type; 1934 } 1935 1936 static int ice_read_customized_path(char *pkg_file, uint16_t buff_len) 1937 { 1938 int fp, n; 1939 1940 fp = open(ICE_PKG_FILE_CUSTOMIZED_PATH, O_RDONLY); 1941 if (fp < 0) { 1942 PMD_INIT_LOG(INFO, "Failed to read CUSTOMIZED_PATH"); 1943 return -EIO; 1944 } 1945 1946 n = read(fp, pkg_file, buff_len - 1); 1947 if (n > 0) { 1948 if (pkg_file[n - 1] == '\n') 1949 n--; 1950 pkg_file[n] = '\0'; 1951 } 1952 1953 close(fp); 1954 return n; 1955 } 1956 1957 int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn) 1958 { 1959 struct ice_hw *hw = &adapter->hw; 1960 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE]; 1961 char customized_path[ICE_MAX_PKG_FILENAME_SIZE]; 1962 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; 1963 void *buf; 1964 size_t bufsz; 1965 int err; 1966 1967 /* first read any explicitly referenced DDP file*/ 1968 if (adapter->devargs.ddp_filename != NULL) { 1969 strlcpy(pkg_file, adapter->devargs.ddp_filename, sizeof(pkg_file)); 1970 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) { 1971 goto load_fw; 1972 } else { 1973 PMD_INIT_LOG(ERR, "Cannot load DDP file: %s", pkg_file); 1974 return -1; 1975 } 1976 } 1977 1978 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); 1979 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, 1980 "ice-%016" PRIx64 ".pkg", dsn); 1981 1982 if (ice_read_customized_path(customized_path, ICE_MAX_PKG_FILENAME_SIZE) > 0) { 1983 if (use_dsn) { 1984 snprintf(pkg_file, RTE_DIM(pkg_file), "%s/%s", 1985 customized_path, opt_ddp_filename); 1986 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) 1987 goto load_fw; 1988 } 1989 snprintf(pkg_file, RTE_DIM(pkg_file), "%s/%s", customized_path, "ice.pkg"); 1990 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) 1991 goto load_fw; 1992 } 1993 1994 if (!use_dsn) 1995 goto no_dsn; 1996 1997 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES, 1998 ICE_MAX_PKG_FILENAME_SIZE); 1999 strcat(pkg_file, opt_ddp_filename); 2000 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) 2001 goto load_fw; 2002 2003 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT, 2004 ICE_MAX_PKG_FILENAME_SIZE); 2005 strcat(pkg_file, opt_ddp_filename); 2006 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) 2007 goto load_fw; 2008 2009 no_dsn: 2010 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE); 2011 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0) 2012 goto load_fw; 2013 2014 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE); 2015 if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) { 2016 PMD_INIT_LOG(ERR, "failed to search file path"); 2017 return -1; 2018 } 2019 2020 load_fw: 2021 PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file); 2022 2023 err = ice_copy_and_init_pkg(hw, buf, bufsz, adapter->devargs.ddp_load_sched); 2024 if (!ice_is_init_pkg_successful(err)) { 2025 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d", err); 2026 free(buf); 2027 return -1; 2028 } 2029 2030 /* store the loaded pkg type info */ 2031 adapter->active_pkg_type = ice_load_pkg_type(hw); 2032 2033 free(buf); 2034 return 0; 2035 } 2036 2037 static void 2038 ice_base_queue_get(struct ice_pf *pf) 2039 { 2040 uint32_t reg; 2041 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2042 2043 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC); 2044 if (reg & PFLAN_RX_QALLOC_VALID_M) { 2045 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M; 2046 } else { 2047 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue" 2048 " index"); 2049 } 2050 } 2051 2052 static int 2053 parse_bool(const char *key, const char *value, void *args) 2054 { 2055 int *i = args; 2056 2057 if (value == NULL || value[0] == '\0') { 2058 PMD_DRV_LOG(WARNING, "key:\"%s\", requires a value, which must be 0 or 1", key); 2059 return -1; 2060 } 2061 if (value[1] != '\0' || (value[0] != '0' && value[0] != '1')) { 2062 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", value must be 0 or 1", 2063 value, key); 2064 return -1; 2065 } 2066 2067 *i = (value[0] == '1'); 2068 return 0; 2069 } 2070 2071 static int 2072 parse_u64(const char *key, const char *value, void *args) 2073 { 2074 u64 *num = (u64 *)args; 2075 u64 tmp; 2076 2077 errno = 0; 2078 tmp = strtoull(value, NULL, 16); 2079 if (errno) { 2080 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64", 2081 key, value); 2082 return -1; 2083 } 2084 2085 *num = tmp; 2086 2087 return 0; 2088 } 2089 2090 static int 2091 parse_tx_sched_levels(const char *key, const char *value, void *args) 2092 { 2093 uint8_t *num = args; 2094 long tmp; 2095 char *endptr; 2096 2097 errno = 0; 2098 tmp = strtol(value, &endptr, 0); 2099 /* the value needs two stage validation, since the actual number of available 2100 * levels is not known at this point. Initially just validate that it is in 2101 * the correct range, between 3 and 8. Later validation will check that the 2102 * available layers on a particular port is higher than the value specified here. 2103 */ 2104 if (errno || *endptr != '\0' || 2105 tmp < (ICE_VSI_LAYER_OFFSET - 1) || tmp >= ICE_TM_MAX_LAYERS) { 2106 PMD_DRV_LOG(WARNING, "%s: Invalid value \"%s\", should be in range [%d, %d]", 2107 key, value, ICE_VSI_LAYER_OFFSET - 1, ICE_TM_MAX_LAYERS - 1); 2108 return -1; 2109 } 2110 2111 *num = tmp; 2112 2113 return 0; 2114 } 2115 2116 static int 2117 lookup_pps_type(const char *pps_name) 2118 { 2119 static struct { 2120 const char *name; 2121 enum pps_type type; 2122 } pps_type_map[] = { 2123 { "pin", PPS_PIN }, 2124 }; 2125 2126 uint32_t i; 2127 2128 for (i = 0; i < RTE_DIM(pps_type_map); i++) { 2129 if (strcmp(pps_name, pps_type_map[i].name) == 0) 2130 return pps_type_map[i].type; 2131 } 2132 2133 return -1; 2134 } 2135 2136 static int 2137 parse_pin_set(const char *input, int pps_type, struct ice_devargs *devargs) 2138 { 2139 const char *str = input; 2140 char *end = NULL; 2141 uint32_t idx; 2142 2143 while (isblank(*str)) 2144 str++; 2145 2146 if (!isdigit(*str)) 2147 return -1; 2148 2149 if (pps_type == PPS_PIN) { 2150 idx = strtoul(str, &end, 10); 2151 if (end == NULL || idx >= ICE_MAX_PIN_NUM) 2152 return -1; 2153 while (isblank(*end)) 2154 end++; 2155 if (*end != ']') 2156 return -1; 2157 2158 devargs->pin_idx = idx; 2159 devargs->pps_out_ena = 1; 2160 2161 return 0; 2162 } 2163 2164 return -1; 2165 } 2166 2167 static int 2168 parse_pps_out_parameter(const char *pins, struct ice_devargs *devargs) 2169 { 2170 const char *pin_start; 2171 uint32_t idx; 2172 int pps_type; 2173 char pps_name[32]; 2174 2175 while (isblank(*pins)) 2176 pins++; 2177 2178 pins++; 2179 while (isblank(*pins)) 2180 pins++; 2181 if (*pins == '\0') 2182 return -1; 2183 2184 for (idx = 0; ; idx++) { 2185 if (isblank(pins[idx]) || 2186 pins[idx] == ':' || 2187 pins[idx] == '\0') 2188 break; 2189 2190 pps_name[idx] = pins[idx]; 2191 } 2192 pps_name[idx] = '\0'; 2193 pps_type = lookup_pps_type(pps_name); 2194 if (pps_type < 0) 2195 return -1; 2196 2197 pins += idx; 2198 2199 pins += strcspn(pins, ":"); 2200 if (*pins++ != ':') 2201 return -1; 2202 while (isblank(*pins)) 2203 pins++; 2204 2205 pin_start = pins; 2206 2207 while (isblank(*pins)) 2208 pins++; 2209 2210 if (parse_pin_set(pin_start, pps_type, devargs) < 0) 2211 return -1; 2212 2213 return 0; 2214 } 2215 2216 static int 2217 handle_pps_out_arg(__rte_unused const char *key, const char *value, 2218 void *extra_args) 2219 { 2220 struct ice_devargs *devargs = extra_args; 2221 2222 if (value == NULL || extra_args == NULL) 2223 return -EINVAL; 2224 2225 if (parse_pps_out_parameter(value, devargs) < 0) { 2226 PMD_DRV_LOG(ERR, 2227 "The GPIO pin parameter is wrong : '%s'", 2228 value); 2229 return -1; 2230 } 2231 2232 return 0; 2233 } 2234 2235 static int 2236 ice_parse_mbuf_check(__rte_unused const char *key, const char *value, void *args) 2237 { 2238 char *cur; 2239 char *tmp; 2240 int str_len; 2241 int valid_len; 2242 2243 int ret = 0; 2244 uint64_t *mc_flags = args; 2245 char *str2 = strdup(value); 2246 if (str2 == NULL) 2247 return -1; 2248 2249 str_len = strlen(str2); 2250 if (str_len == 0) { 2251 ret = -1; 2252 goto err_end; 2253 } 2254 2255 /* Try stripping the outer square brackets of the parameter string. */ 2256 str_len = strlen(str2); 2257 if (str2[0] == '[' && str2[str_len - 1] == ']') { 2258 if (str_len < 3) { 2259 ret = -1; 2260 goto err_end; 2261 } 2262 valid_len = str_len - 2; 2263 memmove(str2, str2 + 1, valid_len); 2264 memset(str2 + valid_len, '\0', 2); 2265 } 2266 2267 cur = strtok_r(str2, ",", &tmp); 2268 while (cur != NULL) { 2269 if (!strcmp(cur, "mbuf")) 2270 *mc_flags |= ICE_MBUF_CHECK_F_TX_MBUF; 2271 else if (!strcmp(cur, "size")) 2272 *mc_flags |= ICE_MBUF_CHECK_F_TX_SIZE; 2273 else if (!strcmp(cur, "segment")) 2274 *mc_flags |= ICE_MBUF_CHECK_F_TX_SEGMENT; 2275 else if (!strcmp(cur, "offload")) 2276 *mc_flags |= ICE_MBUF_CHECK_F_TX_OFFLOAD; 2277 else 2278 PMD_DRV_LOG(ERR, "Unsupported diagnostic type: %s", cur); 2279 cur = strtok_r(NULL, ",", &tmp); 2280 } 2281 2282 err_end: 2283 free(str2); 2284 return ret; 2285 } 2286 2287 static int ice_parse_devargs(struct rte_eth_dev *dev) 2288 { 2289 struct ice_adapter *ad = 2290 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2291 struct rte_devargs *devargs = dev->device->devargs; 2292 struct rte_kvargs *kvlist; 2293 int ret; 2294 2295 if (devargs == NULL) 2296 return 0; 2297 2298 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args); 2299 if (kvlist == NULL) { 2300 PMD_INIT_LOG(ERR, "Invalid kvargs key"); 2301 return -EINVAL; 2302 } 2303 2304 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE; 2305 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE, 2306 sizeof(ad->devargs.proto_xtr)); 2307 2308 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG, 2309 &handle_proto_xtr_arg, &ad->devargs); 2310 if (ret) 2311 goto bail; 2312 2313 ret = rte_kvargs_process(kvlist, ICE_FIELD_OFFS_ARG, 2314 &handle_field_offs_arg, &ad->devargs.xtr_field_offs); 2315 if (ret) 2316 goto bail; 2317 2318 ret = rte_kvargs_process(kvlist, ICE_FIELD_NAME_ARG, 2319 &handle_field_name_arg, &ad->devargs.xtr_field_name); 2320 if (ret) 2321 goto bail; 2322 2323 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, 2324 &parse_bool, &ad->devargs.safe_mode_support); 2325 if (ret) 2326 goto bail; 2327 2328 ret = rte_kvargs_process(kvlist, ICE_DEFAULT_MAC_DISABLE, 2329 &parse_bool, &ad->devargs.default_mac_disable); 2330 if (ret) 2331 goto bail; 2332 2333 ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG, 2334 &parse_u64, &ad->hw.debug_mask); 2335 if (ret) 2336 goto bail; 2337 2338 ret = rte_kvargs_process(kvlist, ICE_ONE_PPS_OUT_ARG, 2339 &handle_pps_out_arg, &ad->devargs); 2340 if (ret) 2341 goto bail; 2342 2343 ret = rte_kvargs_process(kvlist, ICE_MBUF_CHECK_ARG, 2344 &ice_parse_mbuf_check, &ad->devargs.mbuf_check); 2345 if (ret) 2346 goto bail; 2347 2348 ret = rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY_ARG, 2349 &parse_bool, &ad->devargs.rx_low_latency); 2350 if (ret) 2351 goto bail; 2352 2353 ret = rte_kvargs_process(kvlist, ICE_DDP_FILENAME_ARG, 2354 &handle_ddp_filename_arg, &ad->devargs.ddp_filename); 2355 if (ret) 2356 goto bail; 2357 2358 ret = rte_kvargs_process(kvlist, ICE_DDP_LOAD_SCHED_ARG, 2359 &parse_bool, &ad->devargs.ddp_load_sched); 2360 if (ret) 2361 goto bail; 2362 2363 ret = rte_kvargs_process(kvlist, ICE_TM_LEVELS_ARG, 2364 &parse_tx_sched_levels, &ad->devargs.tm_exposed_levels); 2365 if (ret) 2366 goto bail; 2367 2368 bail: 2369 rte_kvargs_free(kvlist); 2370 return ret; 2371 } 2372 2373 static int 2374 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, 2375 uint16_t num, uint16_t desc_id, 2376 uint16_t *prof_buf, uint16_t *num_prof) 2377 { 2378 struct ice_aqc_res_elem *resp_buf; 2379 int ret; 2380 uint16_t buf_len; 2381 bool res_shared = 1; 2382 struct ice_aq_desc aq_desc; 2383 struct ice_sq_cd *cd = NULL; 2384 struct ice_aqc_get_allocd_res_desc *cmd = 2385 &aq_desc.params.get_res_desc; 2386 2387 buf_len = sizeof(*resp_buf) * num; 2388 resp_buf = ice_malloc(hw, buf_len); 2389 if (!resp_buf) 2390 return -ENOMEM; 2391 2392 ice_fill_dflt_direct_cmd_desc(&aq_desc, 2393 ice_aqc_opc_get_allocd_res_desc); 2394 2395 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) & 2396 ICE_AQC_RES_TYPE_M) | (res_shared ? 2397 ICE_AQC_RES_TYPE_FLAG_SHARED : 0)); 2398 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id); 2399 2400 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd); 2401 if (!ret) 2402 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc); 2403 else 2404 goto exit; 2405 2406 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) * 2407 (*num_prof), ICE_NONDMA_TO_NONDMA); 2408 2409 exit: 2410 rte_free(resp_buf); 2411 return ret; 2412 } 2413 static int 2414 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type) 2415 { 2416 int ret; 2417 uint16_t prof_id; 2418 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM]; 2419 uint16_t first_desc = 1; 2420 uint16_t num_prof = 0; 2421 2422 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM, 2423 first_desc, prof_buf, &num_prof); 2424 if (ret) { 2425 PMD_INIT_LOG(ERR, "Failed to get fxp resource"); 2426 return ret; 2427 } 2428 2429 for (prof_id = 0; prof_id < num_prof; prof_id++) { 2430 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]); 2431 if (ret) { 2432 PMD_INIT_LOG(ERR, "Failed to free fxp resource"); 2433 return ret; 2434 } 2435 } 2436 return 0; 2437 } 2438 2439 static int 2440 ice_reset_fxp_resource(struct ice_hw *hw) 2441 { 2442 int ret; 2443 2444 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID); 2445 if (ret) { 2446 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource"); 2447 return ret; 2448 } 2449 2450 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID); 2451 if (ret) { 2452 PMD_INIT_LOG(ERR, "Failed to clearup rss resource"); 2453 return ret; 2454 } 2455 2456 return 0; 2457 } 2458 2459 static void 2460 ice_rss_ctx_init(struct ice_pf *pf) 2461 { 2462 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx)); 2463 } 2464 2465 static uint64_t 2466 ice_get_supported_rxdid(struct ice_hw *hw) 2467 { 2468 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */ 2469 uint32_t regval; 2470 int i; 2471 2472 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1); 2473 2474 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) { 2475 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0)); 2476 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) 2477 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) 2478 supported_rxdid |= BIT(i); 2479 } 2480 return supported_rxdid; 2481 } 2482 2483 static void ice_ptp_init_info(struct rte_eth_dev *dev) 2484 { 2485 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2486 struct ice_adapter *ad = 2487 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2488 2489 switch (hw->phy_model) { 2490 case ICE_PHY_ETH56G: 2491 ad->ptp_tx_block = hw->pf_id; 2492 ad->ptp_tx_index = 0; 2493 break; 2494 case ICE_PHY_E810: 2495 case ICE_PHY_E830: 2496 ad->ptp_tx_block = hw->port_info->lport; 2497 ad->ptp_tx_index = 0; 2498 break; 2499 case ICE_PHY_E822: 2500 ad->ptp_tx_block = hw->pf_id / ICE_PORTS_PER_QUAD; 2501 ad->ptp_tx_index = (hw->pf_id % ICE_PORTS_PER_QUAD) * 2502 ICE_PORTS_PER_PHY_E822 * ICE_QUADS_PER_PHY_E822; 2503 break; 2504 default: 2505 PMD_DRV_LOG(WARNING, "Unsupported PHY model"); 2506 break; 2507 } 2508 } 2509 2510 static int 2511 ice_dev_init(struct rte_eth_dev *dev) 2512 { 2513 struct rte_pci_device *pci_dev; 2514 struct rte_intr_handle *intr_handle; 2515 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2516 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2517 struct ice_adapter *ad = 2518 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2519 struct ice_vsi *vsi; 2520 int ret; 2521 #ifndef RTE_EXEC_ENV_WINDOWS 2522 off_t pos; 2523 uint32_t dsn_low, dsn_high; 2524 uint64_t dsn; 2525 bool use_dsn; 2526 #endif 2527 2528 dev->dev_ops = &ice_eth_dev_ops; 2529 dev->rx_queue_count = ice_rx_queue_count; 2530 dev->rx_descriptor_status = ice_rx_descriptor_status; 2531 dev->tx_descriptor_status = ice_tx_descriptor_status; 2532 dev->rx_pkt_burst = ice_recv_pkts; 2533 dev->tx_pkt_burst = ice_xmit_pkts; 2534 dev->tx_pkt_prepare = ice_prep_pkts; 2535 2536 /* for secondary processes, we don't initialise any further as primary 2537 * has already done this work. 2538 */ 2539 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2540 ice_set_rx_function(dev); 2541 ice_set_tx_function(dev); 2542 return 0; 2543 } 2544 2545 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2546 2547 ice_set_default_ptype_table(dev); 2548 pci_dev = RTE_DEV_TO_PCI(dev->device); 2549 intr_handle = pci_dev->intr_handle; 2550 2551 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2552 pf->dev_data = dev->data; 2553 hw->back = pf->adapter; 2554 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 2555 hw->vendor_id = pci_dev->id.vendor_id; 2556 hw->device_id = pci_dev->id.device_id; 2557 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2558 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 2559 hw->bus.device = pci_dev->addr.devid; 2560 hw->bus.func = pci_dev->addr.function; 2561 2562 ret = ice_parse_devargs(dev); 2563 if (ret) { 2564 PMD_INIT_LOG(ERR, "Failed to parse devargs"); 2565 return -EINVAL; 2566 } 2567 2568 ice_init_controlq_parameter(hw); 2569 2570 ret = ice_init_hw(hw); 2571 if (ret) { 2572 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 2573 return -EINVAL; 2574 } 2575 2576 #ifndef RTE_EXEC_ENV_WINDOWS 2577 use_dsn = false; 2578 dsn = 0; 2579 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN); 2580 if (pos) { 2581 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 || 2582 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) { 2583 PMD_INIT_LOG(ERR, "Failed to read pci config space"); 2584 } else { 2585 use_dsn = true; 2586 dsn = (uint64_t)dsn_high << 32 | dsn_low; 2587 } 2588 } else { 2589 PMD_INIT_LOG(ERR, "Failed to read device serial number"); 2590 } 2591 2592 ret = ice_load_pkg(pf->adapter, use_dsn, dsn); 2593 if (ret == 0) { 2594 ret = ice_init_hw_tbls(hw); 2595 if (ret) { 2596 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d", ret); 2597 rte_free(hw->pkg_copy); 2598 } 2599 } 2600 2601 if (ret) { 2602 if (ad->devargs.safe_mode_support == 0) { 2603 PMD_INIT_LOG(ERR, "Failed to load the DDP package," 2604 "Use safe-mode-support=1 to enter Safe Mode"); 2605 goto err_init_fw; 2606 } 2607 2608 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 2609 "Entering Safe Mode"); 2610 ad->is_safe_mode = 1; 2611 } 2612 #endif 2613 2614 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 2615 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 2616 hw->api_maj_ver, hw->api_min_ver); 2617 2618 ice_pf_sw_init(dev); 2619 ret = ice_init_mac_address(dev); 2620 if (ret) { 2621 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 2622 goto err_init_mac; 2623 } 2624 2625 ret = ice_res_pool_init(&pf->msix_pool, 1, 2626 hw->func_caps.common_cap.num_msix_vectors - 1); 2627 if (ret) { 2628 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 2629 goto err_msix_pool_init; 2630 } 2631 2632 ret = ice_pf_setup(pf); 2633 if (ret) { 2634 PMD_INIT_LOG(ERR, "Failed to setup PF"); 2635 goto err_pf_setup; 2636 } 2637 2638 ret = ice_send_driver_ver(hw); 2639 if (ret) { 2640 PMD_INIT_LOG(ERR, "Failed to send driver version"); 2641 goto err_pf_setup; 2642 } 2643 2644 vsi = pf->main_vsi; 2645 2646 ret = ice_aq_stop_lldp(hw, true, false, NULL); 2647 if (ret != ICE_SUCCESS) 2648 PMD_INIT_LOG(DEBUG, "lldp has already stopped"); 2649 ret = ice_init_dcb(hw, true); 2650 if (ret != ICE_SUCCESS) 2651 PMD_INIT_LOG(DEBUG, "Failed to init DCB"); 2652 /* Forward LLDP packets to default VSI */ 2653 ret = ice_lldp_fltr_add_remove(hw, vsi->vsi_id, true); 2654 if (ret != ICE_SUCCESS) 2655 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp"); 2656 /* register callback func to eal lib */ 2657 rte_intr_callback_register(intr_handle, 2658 ice_interrupt_handler, dev); 2659 2660 ice_pf_enable_irq0(hw); 2661 2662 /* enable uio intr after callback register */ 2663 rte_intr_enable(intr_handle); 2664 2665 /* get base queue pairs index in the device */ 2666 ice_base_queue_get(pf); 2667 2668 /* Initialize RSS context for gtpu_eh */ 2669 ice_rss_ctx_init(pf); 2670 2671 /* Initialize TM configuration */ 2672 ice_tm_conf_init(dev); 2673 2674 /* Initialize PHY model */ 2675 ice_ptp_init_phy_model(hw); 2676 2677 /* Initialize PTP info */ 2678 ice_ptp_init_info(dev); 2679 2680 if (hw->phy_model == ICE_PHY_E822) { 2681 ret = ice_start_phy_timer_e822(hw, hw->pf_id, true); 2682 if (ret) 2683 PMD_INIT_LOG(ERR, "Failed to start phy timer"); 2684 } 2685 2686 if (!ad->is_safe_mode) { 2687 ad->disabled_engine_mask |= BIT(ICE_FLOW_ENGINE_ACL); 2688 ret = ice_flow_init(ad); 2689 if (ret) { 2690 PMD_INIT_LOG(ERR, "Failed to initialize flow"); 2691 goto err_flow_init; 2692 } 2693 } 2694 2695 ret = ice_reset_fxp_resource(hw); 2696 if (ret) { 2697 PMD_INIT_LOG(ERR, "Failed to reset fxp resource"); 2698 goto err_flow_init; 2699 } 2700 2701 pf->supported_rxdid = ice_get_supported_rxdid(hw); 2702 2703 /* reset all stats of the device, including pf and main vsi */ 2704 ice_stats_reset(dev); 2705 2706 return 0; 2707 2708 err_flow_init: 2709 ice_flow_uninit(ad); 2710 rte_intr_disable(intr_handle); 2711 ice_pf_disable_irq0(hw); 2712 rte_intr_callback_unregister(intr_handle, 2713 ice_interrupt_handler, dev); 2714 err_pf_setup: 2715 ice_res_pool_destroy(&pf->msix_pool); 2716 err_msix_pool_init: 2717 rte_free(dev->data->mac_addrs); 2718 dev->data->mac_addrs = NULL; 2719 err_init_mac: 2720 rte_free(pf->proto_xtr); 2721 #ifndef RTE_EXEC_ENV_WINDOWS 2722 err_init_fw: 2723 #endif 2724 ice_deinit_hw(hw); 2725 2726 return ret; 2727 } 2728 2729 int 2730 ice_release_vsi(struct ice_vsi *vsi) 2731 { 2732 struct ice_hw *hw; 2733 struct ice_vsi_ctx vsi_ctx; 2734 int ret, error = 0; 2735 2736 if (!vsi) 2737 return error; 2738 2739 hw = ICE_VSI_TO_HW(vsi); 2740 2741 ice_remove_all_mac_vlan_filters(vsi); 2742 2743 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 2744 2745 vsi_ctx.vsi_num = vsi->vsi_id; 2746 vsi_ctx.info = vsi->info; 2747 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 2748 if (ret != ICE_SUCCESS) { 2749 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 2750 error = -1; 2751 } 2752 2753 rte_free(vsi->rss_lut); 2754 rte_free(vsi->rss_key); 2755 rte_free(vsi); 2756 return error; 2757 } 2758 2759 void 2760 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 2761 { 2762 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; 2763 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2764 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2765 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2766 uint16_t msix_intr, i; 2767 2768 /* disable interrupt and also clear all the exist config */ 2769 for (i = 0; i < vsi->nb_qps; i++) { 2770 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 2771 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 2772 rte_wmb(); 2773 } 2774 2775 if (rte_intr_allow_others(intr_handle)) 2776 /* vfio-pci */ 2777 for (i = 0; i < vsi->nb_msix; i++) { 2778 msix_intr = vsi->msix_intr + i; 2779 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 2780 GLINT_DYN_CTL_WB_ON_ITR_M); 2781 } 2782 else 2783 /* igb_uio */ 2784 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 2785 } 2786 2787 static int 2788 ice_dev_stop(struct rte_eth_dev *dev) 2789 { 2790 struct rte_eth_dev_data *data = dev->data; 2791 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2792 struct ice_vsi *main_vsi = pf->main_vsi; 2793 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2794 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2795 uint16_t i; 2796 2797 /* avoid stopping again */ 2798 if (pf->adapter_stopped) 2799 return 0; 2800 2801 /* stop and clear all Rx queues */ 2802 for (i = 0; i < data->nb_rx_queues; i++) 2803 ice_rx_queue_stop(dev, i); 2804 2805 /* stop and clear all Tx queues */ 2806 for (i = 0; i < data->nb_tx_queues; i++) 2807 ice_tx_queue_stop(dev, i); 2808 2809 /* disable all queue interrupts */ 2810 ice_vsi_disable_queues_intr(main_vsi); 2811 2812 if (pf->init_link_up) 2813 ice_dev_set_link_up(dev); 2814 else 2815 ice_dev_set_link_down(dev); 2816 2817 /* Clean datapath event and queue/vec mapping */ 2818 rte_intr_efd_disable(intr_handle); 2819 rte_intr_vec_list_free(intr_handle); 2820 2821 pf->adapter_stopped = true; 2822 dev->data->dev_started = 0; 2823 2824 return 0; 2825 } 2826 2827 static int 2828 ice_dev_close(struct rte_eth_dev *dev) 2829 { 2830 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2831 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2832 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2833 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 2834 struct ice_adapter *ad = 2835 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2836 int ret; 2837 uint32_t val; 2838 uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned; 2839 uint32_t pin_idx = ad->devargs.pin_idx; 2840 2841 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2842 return 0; 2843 2844 /* Since stop will make link down, then the link event will be 2845 * triggered, disable the irq firstly. 2846 */ 2847 ice_pf_disable_irq0(hw); 2848 2849 /* Unregister callback func from eal lib, use sync version to 2850 * make sure all active interrupt callbacks is done, then it's 2851 * safe to free all resources. 2852 */ 2853 rte_intr_callback_unregister_sync(intr_handle, 2854 ice_interrupt_handler, dev); 2855 2856 ret = ice_dev_stop(dev); 2857 2858 if (!ad->is_safe_mode) 2859 ice_flow_uninit(ad); 2860 2861 /* release all queue resource */ 2862 ice_free_queues(dev); 2863 2864 ice_res_pool_destroy(&pf->msix_pool); 2865 ice_release_vsi(pf->main_vsi); 2866 ice_sched_cleanup_all(hw); 2867 ice_free_hw_tbls(hw); 2868 rte_free(hw->port_info); 2869 hw->port_info = NULL; 2870 free((void *)(uintptr_t)ad->devargs.ddp_filename); 2871 ad->devargs.ddp_filename = NULL; 2872 ice_shutdown_all_ctrlq(hw, true); 2873 rte_free(pf->proto_xtr); 2874 pf->proto_xtr = NULL; 2875 2876 /* Uninit TM configuration */ 2877 ice_tm_conf_uninit(dev); 2878 2879 if (ad->devargs.pps_out_ena) { 2880 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0); 2881 ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0); 2882 ICE_WRITE_REG(hw, GLTSYN_TGT_L(pin_idx, timer), 0); 2883 ICE_WRITE_REG(hw, GLTSYN_TGT_H(pin_idx, timer), 0); 2884 2885 val = GLGEN_GPIO_CTL_PIN_DIR_M; 2886 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(pin_idx), val); 2887 } 2888 2889 /* disable uio intr before callback unregister */ 2890 rte_intr_disable(intr_handle); 2891 2892 return ret; 2893 } 2894 2895 static int 2896 ice_dev_uninit(struct rte_eth_dev *dev) 2897 { 2898 ice_dev_close(dev); 2899 2900 return 0; 2901 } 2902 2903 static bool 2904 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg) 2905 { 2906 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false; 2907 } 2908 2909 static void 2910 hash_cfg_reset(struct ice_rss_hash_cfg *cfg) 2911 { 2912 cfg->hash_flds = 0; 2913 cfg->addl_hdrs = 0; 2914 cfg->symm = 0; 2915 cfg->hdr_type = ICE_RSS_OUTER_HEADERS; 2916 } 2917 2918 static int 2919 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2920 { 2921 int status; 2922 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2923 struct ice_vsi *vsi = pf->main_vsi; 2924 2925 if (!is_hash_cfg_valid(cfg)) 2926 return -ENOENT; 2927 2928 status = ice_rem_rss_cfg(hw, vsi->idx, cfg); 2929 if (status && status != ICE_ERR_DOES_NOT_EXIST) { 2930 PMD_DRV_LOG(ERR, 2931 "ice_rem_rss_cfg failed for VSI:%d, error:%d", 2932 vsi->idx, status); 2933 return -EBUSY; 2934 } 2935 2936 return 0; 2937 } 2938 2939 static int 2940 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2941 { 2942 int status; 2943 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2944 struct ice_vsi *vsi = pf->main_vsi; 2945 2946 if (!is_hash_cfg_valid(cfg)) 2947 return -ENOENT; 2948 2949 status = ice_add_rss_cfg(hw, vsi->idx, cfg); 2950 if (status) { 2951 PMD_DRV_LOG(ERR, 2952 "ice_add_rss_cfg failed for VSI:%d, error:%d", 2953 vsi->idx, status); 2954 return -EBUSY; 2955 } 2956 2957 return 0; 2958 } 2959 2960 static int 2961 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 2962 { 2963 int ret; 2964 2965 ret = ice_hash_moveout(pf, cfg); 2966 if (ret && (ret != -ENOENT)) 2967 return ret; 2968 2969 hash_cfg_reset(cfg); 2970 2971 return 0; 2972 } 2973 2974 static int 2975 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 2976 u8 ctx_idx) 2977 { 2978 int ret; 2979 2980 switch (ctx_idx) { 2981 case ICE_HASH_GTPU_CTX_EH_IP: 2982 ret = ice_hash_remove(pf, 2983 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 2984 if (ret && (ret != -ENOENT)) 2985 return ret; 2986 2987 ret = ice_hash_remove(pf, 2988 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 2989 if (ret && (ret != -ENOENT)) 2990 return ret; 2991 2992 ret = ice_hash_remove(pf, 2993 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 2994 if (ret && (ret != -ENOENT)) 2995 return ret; 2996 2997 ret = ice_hash_remove(pf, 2998 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 2999 if (ret && (ret != -ENOENT)) 3000 return ret; 3001 3002 ret = ice_hash_remove(pf, 3003 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 3004 if (ret && (ret != -ENOENT)) 3005 return ret; 3006 3007 ret = ice_hash_remove(pf, 3008 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 3009 if (ret && (ret != -ENOENT)) 3010 return ret; 3011 3012 ret = ice_hash_remove(pf, 3013 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 3014 if (ret && (ret != -ENOENT)) 3015 return ret; 3016 3017 ret = ice_hash_remove(pf, 3018 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 3019 if (ret && (ret != -ENOENT)) 3020 return ret; 3021 3022 break; 3023 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 3024 ret = ice_hash_remove(pf, 3025 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 3026 if (ret && (ret != -ENOENT)) 3027 return ret; 3028 3029 ret = ice_hash_remove(pf, 3030 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 3031 if (ret && (ret != -ENOENT)) 3032 return ret; 3033 3034 ret = ice_hash_moveout(pf, 3035 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 3036 if (ret && (ret != -ENOENT)) 3037 return ret; 3038 3039 ret = ice_hash_moveout(pf, 3040 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 3041 if (ret && (ret != -ENOENT)) 3042 return ret; 3043 3044 ret = ice_hash_moveout(pf, 3045 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 3046 if (ret && (ret != -ENOENT)) 3047 return ret; 3048 3049 ret = ice_hash_moveout(pf, 3050 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 3051 if (ret && (ret != -ENOENT)) 3052 return ret; 3053 3054 break; 3055 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 3056 ret = ice_hash_remove(pf, 3057 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 3058 if (ret && (ret != -ENOENT)) 3059 return ret; 3060 3061 ret = ice_hash_remove(pf, 3062 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 3063 if (ret && (ret != -ENOENT)) 3064 return ret; 3065 3066 ret = ice_hash_moveout(pf, 3067 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 3068 if (ret && (ret != -ENOENT)) 3069 return ret; 3070 3071 ret = ice_hash_moveout(pf, 3072 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 3073 if (ret && (ret != -ENOENT)) 3074 return ret; 3075 3076 ret = ice_hash_moveout(pf, 3077 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 3078 if (ret && (ret != -ENOENT)) 3079 return ret; 3080 3081 ret = ice_hash_moveout(pf, 3082 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 3083 if (ret && (ret != -ENOENT)) 3084 return ret; 3085 3086 break; 3087 case ICE_HASH_GTPU_CTX_UP_IP: 3088 ret = ice_hash_remove(pf, 3089 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 3090 if (ret && (ret != -ENOENT)) 3091 return ret; 3092 3093 ret = ice_hash_remove(pf, 3094 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 3095 if (ret && (ret != -ENOENT)) 3096 return ret; 3097 3098 ret = ice_hash_moveout(pf, 3099 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 3100 if (ret && (ret != -ENOENT)) 3101 return ret; 3102 3103 ret = ice_hash_moveout(pf, 3104 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 3105 if (ret && (ret != -ENOENT)) 3106 return ret; 3107 3108 ret = ice_hash_moveout(pf, 3109 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 3110 if (ret && (ret != -ENOENT)) 3111 return ret; 3112 3113 break; 3114 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 3115 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 3116 ret = ice_hash_moveout(pf, 3117 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 3118 if (ret && (ret != -ENOENT)) 3119 return ret; 3120 3121 ret = ice_hash_moveout(pf, 3122 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 3123 if (ret && (ret != -ENOENT)) 3124 return ret; 3125 3126 ret = ice_hash_moveout(pf, 3127 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 3128 if (ret && (ret != -ENOENT)) 3129 return ret; 3130 3131 break; 3132 case ICE_HASH_GTPU_CTX_DW_IP: 3133 ret = ice_hash_remove(pf, 3134 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 3135 if (ret && (ret != -ENOENT)) 3136 return ret; 3137 3138 ret = ice_hash_remove(pf, 3139 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 3140 if (ret && (ret != -ENOENT)) 3141 return ret; 3142 3143 ret = ice_hash_moveout(pf, 3144 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 3145 if (ret && (ret != -ENOENT)) 3146 return ret; 3147 3148 ret = ice_hash_moveout(pf, 3149 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 3150 if (ret && (ret != -ENOENT)) 3151 return ret; 3152 3153 ret = ice_hash_moveout(pf, 3154 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 3155 if (ret && (ret != -ENOENT)) 3156 return ret; 3157 3158 break; 3159 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 3160 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 3161 ret = ice_hash_moveout(pf, 3162 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 3163 if (ret && (ret != -ENOENT)) 3164 return ret; 3165 3166 ret = ice_hash_moveout(pf, 3167 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 3168 if (ret && (ret != -ENOENT)) 3169 return ret; 3170 3171 ret = ice_hash_moveout(pf, 3172 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 3173 if (ret && (ret != -ENOENT)) 3174 return ret; 3175 3176 break; 3177 default: 3178 break; 3179 } 3180 3181 return 0; 3182 } 3183 3184 static u8 calc_gtpu_ctx_idx(uint32_t hdr) 3185 { 3186 u8 eh_idx, ip_idx; 3187 3188 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) 3189 eh_idx = 0; 3190 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP) 3191 eh_idx = 1; 3192 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN) 3193 eh_idx = 2; 3194 else 3195 return ICE_HASH_GTPU_CTX_MAX; 3196 3197 ip_idx = 0; 3198 if (hdr & ICE_FLOW_SEG_HDR_UDP) 3199 ip_idx = 1; 3200 else if (hdr & ICE_FLOW_SEG_HDR_TCP) 3201 ip_idx = 2; 3202 3203 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)) 3204 return eh_idx * 3 + ip_idx; 3205 else 3206 return ICE_HASH_GTPU_CTX_MAX; 3207 } 3208 3209 static int 3210 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr) 3211 { 3212 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 3213 3214 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 3215 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4, 3216 gtpu_ctx_idx); 3217 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 3218 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6, 3219 gtpu_ctx_idx); 3220 3221 return 0; 3222 } 3223 3224 static int 3225 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx, 3226 u8 ctx_idx, struct ice_rss_hash_cfg *cfg) 3227 { 3228 int ret; 3229 3230 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX) 3231 ctx->ctx[ctx_idx] = *cfg; 3232 3233 switch (ctx_idx) { 3234 case ICE_HASH_GTPU_CTX_EH_IP: 3235 break; 3236 case ICE_HASH_GTPU_CTX_EH_IP_UDP: 3237 ret = ice_hash_moveback(pf, 3238 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 3239 if (ret && (ret != -ENOENT)) 3240 return ret; 3241 3242 ret = ice_hash_moveback(pf, 3243 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]); 3244 if (ret && (ret != -ENOENT)) 3245 return ret; 3246 3247 ret = ice_hash_moveback(pf, 3248 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 3249 if (ret && (ret != -ENOENT)) 3250 return ret; 3251 3252 ret = ice_hash_moveback(pf, 3253 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]); 3254 if (ret && (ret != -ENOENT)) 3255 return ret; 3256 3257 break; 3258 case ICE_HASH_GTPU_CTX_EH_IP_TCP: 3259 ret = ice_hash_moveback(pf, 3260 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]); 3261 if (ret && (ret != -ENOENT)) 3262 return ret; 3263 3264 ret = ice_hash_moveback(pf, 3265 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]); 3266 if (ret && (ret != -ENOENT)) 3267 return ret; 3268 3269 ret = ice_hash_moveback(pf, 3270 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]); 3271 if (ret && (ret != -ENOENT)) 3272 return ret; 3273 3274 ret = ice_hash_moveback(pf, 3275 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]); 3276 if (ret && (ret != -ENOENT)) 3277 return ret; 3278 3279 break; 3280 case ICE_HASH_GTPU_CTX_UP_IP: 3281 case ICE_HASH_GTPU_CTX_UP_IP_UDP: 3282 case ICE_HASH_GTPU_CTX_UP_IP_TCP: 3283 case ICE_HASH_GTPU_CTX_DW_IP: 3284 case ICE_HASH_GTPU_CTX_DW_IP_UDP: 3285 case ICE_HASH_GTPU_CTX_DW_IP_TCP: 3286 ret = ice_hash_moveback(pf, 3287 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]); 3288 if (ret && (ret != -ENOENT)) 3289 return ret; 3290 3291 ret = ice_hash_moveback(pf, 3292 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]); 3293 if (ret && (ret != -ENOENT)) 3294 return ret; 3295 3296 ret = ice_hash_moveback(pf, 3297 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]); 3298 if (ret && (ret != -ENOENT)) 3299 return ret; 3300 3301 break; 3302 default: 3303 break; 3304 } 3305 3306 return 0; 3307 } 3308 3309 static int 3310 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg) 3311 { 3312 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs); 3313 3314 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4) 3315 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4, 3316 gtpu_ctx_idx, cfg); 3317 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6) 3318 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6, 3319 gtpu_ctx_idx, cfg); 3320 3321 return 0; 3322 } 3323 3324 static void 3325 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr) 3326 { 3327 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr); 3328 3329 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX) 3330 return; 3331 3332 if (hdr & ICE_FLOW_SEG_HDR_IPV4) 3333 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]); 3334 else if (hdr & ICE_FLOW_SEG_HDR_IPV6) 3335 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]); 3336 } 3337 3338 int 3339 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 3340 struct ice_rss_hash_cfg *cfg) 3341 { 3342 struct ice_hw *hw = ICE_PF_TO_HW(pf); 3343 int ret; 3344 3345 ret = ice_rem_rss_cfg(hw, vsi_id, cfg); 3346 if (ret && ret != ICE_ERR_DOES_NOT_EXIST) 3347 PMD_DRV_LOG(ERR, "remove rss cfg failed"); 3348 3349 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs); 3350 3351 return 0; 3352 } 3353 3354 int 3355 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, 3356 struct ice_rss_hash_cfg *cfg) 3357 { 3358 struct ice_hw *hw = ICE_PF_TO_HW(pf); 3359 int ret; 3360 3361 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs); 3362 if (ret) 3363 PMD_DRV_LOG(ERR, "add rss cfg pre failed"); 3364 3365 ret = ice_add_rss_cfg(hw, vsi_id, cfg); 3366 if (ret) 3367 PMD_DRV_LOG(ERR, "add rss cfg failed"); 3368 3369 ret = ice_add_rss_cfg_post(pf, cfg); 3370 if (ret) 3371 PMD_DRV_LOG(ERR, "add rss cfg post failed"); 3372 3373 return 0; 3374 } 3375 3376 static void 3377 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf) 3378 { 3379 struct ice_hw *hw = ICE_PF_TO_HW(pf); 3380 struct ice_vsi *vsi = pf->main_vsi; 3381 struct ice_rss_hash_cfg cfg; 3382 int ret; 3383 3384 #define ICE_RSS_HF_ALL ( \ 3385 RTE_ETH_RSS_IPV4 | \ 3386 RTE_ETH_RSS_IPV6 | \ 3387 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ 3388 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \ 3389 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ 3390 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 3391 RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \ 3392 RTE_ETH_RSS_NONFRAG_IPV6_SCTP) 3393 3394 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx); 3395 if (ret) 3396 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d", 3397 __func__, ret); 3398 3399 cfg.symm = 0; 3400 cfg.hdr_type = ICE_RSS_OUTER_HEADERS; 3401 /* Configure RSS for IPv4 with src/dst addr as input set */ 3402 if (rss_hf & RTE_ETH_RSS_IPV4) { 3403 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3404 cfg.hash_flds = ICE_FLOW_HASH_IPV4; 3405 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3406 if (ret) 3407 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", 3408 __func__, ret); 3409 } 3410 3411 /* Configure RSS for IPv6 with src/dst addr as input set */ 3412 if (rss_hf & RTE_ETH_RSS_IPV6) { 3413 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3414 cfg.hash_flds = ICE_FLOW_HASH_IPV6; 3415 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3416 if (ret) 3417 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", 3418 __func__, ret); 3419 } 3420 3421 /* Configure RSS for udp4 with src/dst addr and port as input set */ 3422 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) { 3423 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 | 3424 ICE_FLOW_SEG_HDR_IPV_OTHER; 3425 cfg.hash_flds = ICE_HASH_UDP_IPV4; 3426 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3427 if (ret) 3428 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", 3429 __func__, ret); 3430 } 3431 3432 /* Configure RSS for udp6 with src/dst addr and port as input set */ 3433 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) { 3434 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 | 3435 ICE_FLOW_SEG_HDR_IPV_OTHER; 3436 cfg.hash_flds = ICE_HASH_UDP_IPV6; 3437 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3438 if (ret) 3439 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", 3440 __func__, ret); 3441 } 3442 3443 /* Configure RSS for tcp4 with src/dst addr and port as input set */ 3444 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) { 3445 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 | 3446 ICE_FLOW_SEG_HDR_IPV_OTHER; 3447 cfg.hash_flds = ICE_HASH_TCP_IPV4; 3448 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3449 if (ret) 3450 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", 3451 __func__, ret); 3452 } 3453 3454 /* Configure RSS for tcp6 with src/dst addr and port as input set */ 3455 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) { 3456 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 | 3457 ICE_FLOW_SEG_HDR_IPV_OTHER; 3458 cfg.hash_flds = ICE_HASH_TCP_IPV6; 3459 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3460 if (ret) 3461 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", 3462 __func__, ret); 3463 } 3464 3465 /* Configure RSS for sctp4 with src/dst addr and port as input set */ 3466 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_SCTP) { 3467 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 | 3468 ICE_FLOW_SEG_HDR_IPV_OTHER; 3469 cfg.hash_flds = ICE_HASH_SCTP_IPV4; 3470 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3471 if (ret) 3472 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 3473 __func__, ret); 3474 } 3475 3476 /* Configure RSS for sctp6 with src/dst addr and port as input set */ 3477 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_SCTP) { 3478 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 | 3479 ICE_FLOW_SEG_HDR_IPV_OTHER; 3480 cfg.hash_flds = ICE_HASH_SCTP_IPV6; 3481 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3482 if (ret) 3483 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 3484 __func__, ret); 3485 } 3486 3487 if (rss_hf & RTE_ETH_RSS_IPV4) { 3488 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 | 3489 ICE_FLOW_SEG_HDR_IPV_OTHER; 3490 cfg.hash_flds = ICE_FLOW_HASH_IPV4; 3491 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3492 if (ret) 3493 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d", 3494 __func__, ret); 3495 } 3496 3497 if (rss_hf & RTE_ETH_RSS_IPV6) { 3498 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 | 3499 ICE_FLOW_SEG_HDR_IPV_OTHER; 3500 cfg.hash_flds = ICE_FLOW_HASH_IPV6; 3501 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3502 if (ret) 3503 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d", 3504 __func__, ret); 3505 } 3506 3507 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) { 3508 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP | 3509 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3510 cfg.hash_flds = ICE_HASH_UDP_IPV4; 3511 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3512 if (ret) 3513 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d", 3514 __func__, ret); 3515 } 3516 3517 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) { 3518 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP | 3519 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3520 cfg.hash_flds = ICE_HASH_UDP_IPV6; 3521 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3522 if (ret) 3523 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d", 3524 __func__, ret); 3525 } 3526 3527 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) { 3528 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP | 3529 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3530 cfg.hash_flds = ICE_HASH_TCP_IPV4; 3531 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3532 if (ret) 3533 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d", 3534 __func__, ret); 3535 } 3536 3537 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) { 3538 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP | 3539 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER; 3540 cfg.hash_flds = ICE_HASH_TCP_IPV6; 3541 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg); 3542 if (ret) 3543 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d", 3544 __func__, ret); 3545 } 3546 3547 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL; 3548 } 3549 3550 static void 3551 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size) 3552 { 3553 static struct ice_aqc_get_set_rss_keys default_key; 3554 static bool default_key_done; 3555 uint8_t *key = (uint8_t *)&default_key; 3556 size_t i; 3557 3558 if (rss_key_size > sizeof(default_key)) { 3559 PMD_DRV_LOG(WARNING, 3560 "requested size %u is larger than default %zu, " 3561 "only %zu bytes are gotten for key", 3562 rss_key_size, sizeof(default_key), 3563 sizeof(default_key)); 3564 } 3565 3566 if (!default_key_done) { 3567 /* Calculate the default hash key */ 3568 for (i = 0; i < sizeof(default_key); i++) 3569 key[i] = (uint8_t)rte_rand(); 3570 default_key_done = true; 3571 } 3572 rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key))); 3573 } 3574 3575 static int ice_init_rss(struct ice_pf *pf) 3576 { 3577 struct ice_hw *hw = ICE_PF_TO_HW(pf); 3578 struct ice_vsi *vsi = pf->main_vsi; 3579 struct rte_eth_dev_data *dev_data = pf->dev_data; 3580 struct ice_aq_get_set_rss_lut_params lut_params; 3581 struct rte_eth_rss_conf *rss_conf; 3582 struct ice_aqc_get_set_rss_keys key; 3583 uint16_t i, nb_q; 3584 int ret = 0; 3585 bool is_safe_mode = pf->adapter->is_safe_mode; 3586 uint32_t reg; 3587 3588 rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf; 3589 nb_q = dev_data->nb_rx_queues; 3590 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + 3591 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE; 3592 vsi->rss_lut_size = pf->hash_lut_size; 3593 3594 if (nb_q == 0) { 3595 PMD_DRV_LOG(WARNING, 3596 "RSS is not supported as rx queues number is zero"); 3597 return 0; 3598 } 3599 3600 if (is_safe_mode) { 3601 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode"); 3602 return 0; 3603 } 3604 3605 if (!vsi->rss_key) { 3606 vsi->rss_key = rte_zmalloc(NULL, 3607 vsi->rss_key_size, 0); 3608 if (vsi->rss_key == NULL) { 3609 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3610 return -ENOMEM; 3611 } 3612 } 3613 if (!vsi->rss_lut) { 3614 vsi->rss_lut = rte_zmalloc(NULL, 3615 vsi->rss_lut_size, 0); 3616 if (vsi->rss_lut == NULL) { 3617 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 3618 rte_free(vsi->rss_key); 3619 vsi->rss_key = NULL; 3620 return -ENOMEM; 3621 } 3622 } 3623 /* configure RSS key */ 3624 if (!rss_conf->rss_key) 3625 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size); 3626 else 3627 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 3628 RTE_MIN(rss_conf->rss_key_len, 3629 vsi->rss_key_size)); 3630 3631 rte_memcpy(key.standard_rss_key, vsi->rss_key, 3632 ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE); 3633 rte_memcpy(key.extended_hash_key, 3634 &vsi->rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE], 3635 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE); 3636 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 3637 if (ret) 3638 goto out; 3639 3640 /* init RSS LUT table */ 3641 for (i = 0; i < vsi->rss_lut_size; i++) 3642 vsi->rss_lut[i] = i % nb_q; 3643 3644 lut_params.vsi_handle = vsi->idx; 3645 lut_params.lut_size = vsi->rss_lut_size; 3646 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; 3647 lut_params.lut = vsi->rss_lut; 3648 lut_params.global_lut_id = 0; 3649 ret = ice_aq_set_rss_lut(hw, &lut_params); 3650 if (ret) 3651 goto out; 3652 3653 /* Enable registers for symmetric_toeplitz function. */ 3654 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id)); 3655 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) | 3656 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S); 3657 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg); 3658 3659 /* RSS hash configuration */ 3660 ice_rss_hash_set(pf, rss_conf->rss_hf); 3661 3662 return 0; 3663 out: 3664 rte_free(vsi->rss_key); 3665 vsi->rss_key = NULL; 3666 rte_free(vsi->rss_lut); 3667 vsi->rss_lut = NULL; 3668 return -EINVAL; 3669 } 3670 3671 static int 3672 ice_dev_configure(struct rte_eth_dev *dev) 3673 { 3674 struct ice_adapter *ad = 3675 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 3676 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3677 int ret; 3678 3679 /* Initialize to TRUE. If any of Rx queues doesn't meet the 3680 * bulk allocation or vector Rx preconditions we will reset it. 3681 */ 3682 ad->rx_bulk_alloc_allowed = true; 3683 ad->tx_simple_allowed = true; 3684 3685 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 3686 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 3687 3688 if (dev->data->nb_rx_queues) { 3689 ret = ice_init_rss(pf); 3690 if (ret) { 3691 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 3692 return ret; 3693 } 3694 } 3695 3696 return 0; 3697 } 3698 3699 static void 3700 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 3701 int base_queue, int nb_queue) 3702 { 3703 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3704 uint32_t val, val_tx; 3705 int rx_low_latency, i; 3706 3707 rx_low_latency = vsi->adapter->devargs.rx_low_latency; 3708 for (i = 0; i < nb_queue; i++) { 3709 /*do actual bind*/ 3710 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 3711 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 3712 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 3713 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 3714 3715 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 3716 base_queue + i, msix_vect); 3717 3718 /* set ITR0 value */ 3719 if (rx_low_latency) { 3720 /** 3721 * Empirical configuration for optimal real time 3722 * latency reduced interrupt throttling to 2us 3723 */ 3724 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1); 3725 ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 3726 QRX_ITR_NO_EXPR_M); 3727 } else { 3728 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); 3729 ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0); 3730 } 3731 3732 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 3733 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 3734 } 3735 } 3736 3737 void 3738 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 3739 { 3740 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; 3741 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3742 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3743 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3744 uint16_t msix_vect = vsi->msix_intr; 3745 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, 3746 rte_intr_nb_efd_get(intr_handle)); 3747 uint16_t queue_idx = 0; 3748 int record = 0; 3749 int i; 3750 3751 /* clear Rx/Tx queue interrupt */ 3752 for (i = 0; i < vsi->nb_used_qps; i++) { 3753 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 3754 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 3755 } 3756 3757 /* PF bind interrupt */ 3758 if (rte_intr_dp_is_en(intr_handle)) { 3759 queue_idx = 0; 3760 record = 1; 3761 } 3762 3763 for (i = 0; i < vsi->nb_used_qps; i++) { 3764 if (nb_msix <= 1) { 3765 if (!rte_intr_allow_others(intr_handle)) 3766 msix_vect = ICE_MISC_VEC_ID; 3767 3768 /* uio mapping all queue to one msix_vect */ 3769 __vsi_queues_bind_intr(vsi, msix_vect, 3770 vsi->base_queue + i, 3771 vsi->nb_used_qps - i); 3772 3773 for (; !!record && i < vsi->nb_used_qps; i++) 3774 rte_intr_vec_list_index_set(intr_handle, 3775 queue_idx + i, msix_vect); 3776 3777 break; 3778 } 3779 3780 /* vfio 1:1 queue/msix_vect mapping */ 3781 __vsi_queues_bind_intr(vsi, msix_vect, 3782 vsi->base_queue + i, 1); 3783 3784 if (!!record) 3785 rte_intr_vec_list_index_set(intr_handle, 3786 queue_idx + i, 3787 msix_vect); 3788 3789 msix_vect++; 3790 nb_msix--; 3791 } 3792 } 3793 3794 void 3795 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 3796 { 3797 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; 3798 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3799 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3800 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3801 uint16_t msix_intr, i; 3802 3803 if (rte_intr_allow_others(intr_handle)) 3804 for (i = 0; i < vsi->nb_used_qps; i++) { 3805 msix_intr = vsi->msix_intr + i; 3806 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 3807 GLINT_DYN_CTL_INTENA_M | 3808 GLINT_DYN_CTL_CLEARPBA_M | 3809 GLINT_DYN_CTL_ITR_INDX_M | 3810 GLINT_DYN_CTL_WB_ON_ITR_M); 3811 } 3812 else 3813 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 3814 GLINT_DYN_CTL_INTENA_M | 3815 GLINT_DYN_CTL_CLEARPBA_M | 3816 GLINT_DYN_CTL_ITR_INDX_M | 3817 GLINT_DYN_CTL_WB_ON_ITR_M); 3818 } 3819 3820 static int 3821 ice_rxq_intr_setup(struct rte_eth_dev *dev) 3822 { 3823 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3824 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3825 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3826 struct ice_vsi *vsi = pf->main_vsi; 3827 uint32_t intr_vector = 0; 3828 3829 rte_intr_disable(intr_handle); 3830 3831 /* check and configure queue intr-vector mapping */ 3832 if ((rte_intr_cap_multiple(intr_handle) || 3833 !RTE_ETH_DEV_SRIOV(dev).active) && 3834 dev->data->dev_conf.intr_conf.rxq != 0) { 3835 intr_vector = dev->data->nb_rx_queues; 3836 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 3837 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 3838 ICE_MAX_INTR_QUEUE_NUM); 3839 return -ENOTSUP; 3840 } 3841 if (rte_intr_efd_enable(intr_handle, intr_vector)) 3842 return -1; 3843 } 3844 3845 if (rte_intr_dp_is_en(intr_handle)) { 3846 if (rte_intr_vec_list_alloc(intr_handle, NULL, 3847 dev->data->nb_rx_queues)) { 3848 PMD_DRV_LOG(ERR, 3849 "Failed to allocate %d rx_queues intr_vec", 3850 dev->data->nb_rx_queues); 3851 return -ENOMEM; 3852 } 3853 } 3854 3855 /* Map queues with MSIX interrupt */ 3856 vsi->nb_used_qps = dev->data->nb_rx_queues; 3857 ice_vsi_queues_bind_intr(vsi); 3858 3859 /* Enable interrupts for all the queues */ 3860 ice_vsi_enable_queues_intr(vsi); 3861 3862 rte_intr_enable(intr_handle); 3863 3864 return 0; 3865 } 3866 3867 static int 3868 ice_get_link_info_safe(struct ice_pf *pf, bool ena_lse, 3869 struct ice_link_status *link) 3870 { 3871 struct ice_hw *hw = ICE_PF_TO_HW(pf); 3872 int ret; 3873 3874 rte_spinlock_lock(&pf->link_lock); 3875 3876 ret = ice_aq_get_link_info(hw->port_info, ena_lse, link, NULL); 3877 3878 rte_spinlock_unlock(&pf->link_lock); 3879 3880 return ret; 3881 } 3882 3883 static void 3884 ice_get_init_link_status(struct rte_eth_dev *dev) 3885 { 3886 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3887 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3888 struct ice_link_status link_status; 3889 int ret; 3890 3891 ret = ice_get_link_info_safe(pf, enable_lse, &link_status); 3892 if (ret != ICE_SUCCESS) { 3893 PMD_DRV_LOG(ERR, "Failed to get link info"); 3894 pf->init_link_up = false; 3895 return; 3896 } 3897 3898 if (link_status.link_info & ICE_AQ_LINK_UP) 3899 pf->init_link_up = true; 3900 else 3901 pf->init_link_up = false; 3902 } 3903 3904 static int 3905 ice_pps_out_cfg(struct ice_hw *hw, int idx, int timer) 3906 { 3907 uint64_t current_time, start_time; 3908 uint32_t hi, lo, lo2, func, val; 3909 3910 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer)); 3911 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer)); 3912 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(timer)); 3913 3914 if (lo2 < lo) { 3915 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer)); 3916 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer)); 3917 } 3918 3919 current_time = ((uint64_t)hi << 32) | lo; 3920 3921 start_time = (current_time + NSEC_PER_SEC) / 3922 NSEC_PER_SEC * NSEC_PER_SEC; 3923 start_time = start_time - PPS_OUT_DELAY_NS; 3924 3925 func = 8 + idx + timer * 4; 3926 val = GLGEN_GPIO_CTL_PIN_DIR_M | 3927 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & 3928 GLGEN_GPIO_CTL_PIN_FUNC_M); 3929 3930 /* Write clkout with half of period value */ 3931 ICE_WRITE_REG(hw, GLTSYN_CLKO(idx, timer), NSEC_PER_SEC / 2); 3932 3933 /* Write TARGET time register */ 3934 ICE_WRITE_REG(hw, GLTSYN_TGT_L(idx, timer), start_time & 0xffffffff); 3935 ICE_WRITE_REG(hw, GLTSYN_TGT_H(idx, timer), start_time >> 32); 3936 3937 /* Write AUX_OUT register */ 3938 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(idx, timer), 3939 GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M); 3940 3941 /* Write GPIO CTL register */ 3942 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(idx), val); 3943 3944 return 0; 3945 } 3946 3947 static int 3948 ice_dev_start(struct rte_eth_dev *dev) 3949 { 3950 struct rte_eth_dev_data *data = dev->data; 3951 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3952 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3953 struct ice_vsi *vsi = pf->main_vsi; 3954 struct ice_adapter *ad = 3955 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 3956 uint16_t nb_rxq = 0; 3957 uint16_t nb_txq, i; 3958 uint16_t max_frame_size; 3959 int mask, ret; 3960 uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned; 3961 uint32_t pin_idx = ad->devargs.pin_idx; 3962 ice_declare_bitmap(pmask, ICE_PROMISC_MAX); 3963 ice_zero_bitmap(pmask, ICE_PROMISC_MAX); 3964 3965 /* program Tx queues' context in hardware */ 3966 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 3967 ret = ice_tx_queue_start(dev, nb_txq); 3968 if (ret) { 3969 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 3970 goto tx_err; 3971 } 3972 } 3973 3974 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { 3975 /* Register mbuf field and flag for Rx timestamp */ 3976 ret = rte_mbuf_dyn_rx_timestamp_register(&ice_timestamp_dynfield_offset, 3977 &ice_timestamp_dynflag); 3978 if (ret) { 3979 PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp"); 3980 goto tx_err; 3981 } 3982 } 3983 3984 /* program Rx queues' context in hardware*/ 3985 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 3986 ret = ice_rx_queue_start(dev, nb_rxq); 3987 if (ret) { 3988 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 3989 goto rx_err; 3990 } 3991 } 3992 3993 ice_set_rx_function(dev); 3994 ice_set_tx_function(dev); 3995 3996 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 3997 RTE_ETH_VLAN_EXTEND_MASK; 3998 if (ice_is_dvm_ena(hw)) 3999 mask |= RTE_ETH_QINQ_STRIP_MASK; 4000 4001 ret = ice_vlan_offload_set(dev, mask); 4002 if (ret) { 4003 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 4004 goto rx_err; 4005 } 4006 4007 /* enable Rx interrupt and mapping Rx queue to interrupt vector */ 4008 if (ice_rxq_intr_setup(dev)) 4009 return -EIO; 4010 4011 /* Enable receiving broadcast packets and transmitting packets */ 4012 ice_set_bit(ICE_PROMISC_BCAST_RX, pmask); 4013 ice_set_bit(ICE_PROMISC_BCAST_TX, pmask); 4014 ice_set_bit(ICE_PROMISC_UCAST_TX, pmask); 4015 ice_set_bit(ICE_PROMISC_MCAST_TX, pmask); 4016 4017 ret = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 4018 if (ret != ICE_SUCCESS) 4019 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 4020 4021 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 4022 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 4023 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 4024 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 4025 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 4026 ICE_AQ_LINK_EVENT_AN_COMPLETED | 4027 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 4028 NULL); 4029 if (ret != ICE_SUCCESS) 4030 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 4031 4032 ice_get_init_link_status(dev); 4033 4034 ice_dev_set_link_up(dev); 4035 4036 /* Call get_link_info aq command to enable/disable LSE */ 4037 ice_link_update(dev, 1); 4038 4039 pf->adapter_stopped = false; 4040 4041 /* Set the max frame size to default value*/ 4042 max_frame_size = pf->dev_data->mtu ? 4043 pf->dev_data->mtu + ICE_ETH_OVERHEAD : 4044 ICE_FRAME_SIZE_MAX; 4045 4046 /* Set the max frame size to HW*/ 4047 ice_aq_set_mac_cfg(hw, max_frame_size, false, NULL); 4048 4049 if (ad->devargs.pps_out_ena) { 4050 ret = ice_pps_out_cfg(hw, pin_idx, timer); 4051 if (ret) { 4052 PMD_DRV_LOG(ERR, "Fail to configure 1pps out"); 4053 goto rx_err; 4054 } 4055 } 4056 4057 return 0; 4058 4059 /* stop the started queues if failed to start all queues */ 4060 rx_err: 4061 for (i = 0; i < nb_rxq; i++) 4062 ice_rx_queue_stop(dev, i); 4063 tx_err: 4064 for (i = 0; i < nb_txq; i++) 4065 ice_tx_queue_stop(dev, i); 4066 4067 return -EIO; 4068 } 4069 4070 static int 4071 ice_dev_reset(struct rte_eth_dev *dev) 4072 { 4073 int ret; 4074 4075 if (dev->data->sriov.active) 4076 return -ENOTSUP; 4077 4078 ret = ice_dev_uninit(dev); 4079 if (ret) { 4080 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 4081 return -ENXIO; 4082 } 4083 4084 ret = ice_dev_init(dev); 4085 if (ret) { 4086 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 4087 return -ENXIO; 4088 } 4089 4090 return 0; 4091 } 4092 4093 static int 4094 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 4095 { 4096 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4097 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4098 struct ice_vsi *vsi = pf->main_vsi; 4099 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 4100 bool is_safe_mode = pf->adapter->is_safe_mode; 4101 u64 phy_type_low; 4102 u64 phy_type_high; 4103 4104 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 4105 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 4106 dev_info->max_rx_queues = vsi->nb_qps; 4107 dev_info->max_tx_queues = vsi->nb_qps; 4108 dev_info->max_mac_addrs = vsi->max_macaddrs; 4109 dev_info->max_vfs = pci_dev->max_vfs; 4110 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 4111 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 4112 4113 dev_info->rx_offload_capa = 4114 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 4115 RTE_ETH_RX_OFFLOAD_KEEP_CRC | 4116 RTE_ETH_RX_OFFLOAD_SCATTER | 4117 RTE_ETH_RX_OFFLOAD_VLAN_FILTER; 4118 dev_info->tx_offload_capa = 4119 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 4120 RTE_ETH_TX_OFFLOAD_TCP_TSO | 4121 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 4122 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 4123 dev_info->flow_type_rss_offloads = 0; 4124 4125 if (!is_safe_mode) { 4126 dev_info->rx_offload_capa |= 4127 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 4128 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 4129 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 4130 RTE_ETH_RX_OFFLOAD_QINQ_STRIP | 4131 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 4132 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | 4133 RTE_ETH_RX_OFFLOAD_RSS_HASH | 4134 RTE_ETH_RX_OFFLOAD_TIMESTAMP | 4135 RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT; 4136 dev_info->tx_offload_capa |= 4137 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | 4138 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 4139 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 4140 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 4141 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 4142 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 4143 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | 4144 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | 4145 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | 4146 RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO | 4147 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO; 4148 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 4149 } 4150 4151 dev_info->rx_queue_offload_capa = RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT; 4152 dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 4153 4154 dev_info->reta_size = pf->hash_lut_size; 4155 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 4156 4157 dev_info->default_rxconf = (struct rte_eth_rxconf) { 4158 .rx_thresh = { 4159 .pthresh = ICE_DEFAULT_RX_PTHRESH, 4160 .hthresh = ICE_DEFAULT_RX_HTHRESH, 4161 .wthresh = ICE_DEFAULT_RX_WTHRESH, 4162 }, 4163 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 4164 .rx_drop_en = 0, 4165 .offloads = 0, 4166 }; 4167 4168 dev_info->default_txconf = (struct rte_eth_txconf) { 4169 .tx_thresh = { 4170 .pthresh = ICE_DEFAULT_TX_PTHRESH, 4171 .hthresh = ICE_DEFAULT_TX_HTHRESH, 4172 .wthresh = ICE_DEFAULT_TX_WTHRESH, 4173 }, 4174 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 4175 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 4176 .offloads = 0, 4177 }; 4178 4179 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 4180 .nb_max = ICE_MAX_RING_DESC, 4181 .nb_min = ICE_MIN_RING_DESC, 4182 .nb_align = ICE_ALIGN_RING_DESC, 4183 }; 4184 4185 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 4186 .nb_max = ICE_MAX_RING_DESC, 4187 .nb_min = ICE_MIN_RING_DESC, 4188 .nb_align = ICE_ALIGN_RING_DESC, 4189 .nb_mtu_seg_max = ICE_TX_MTU_SEG_MAX, 4190 .nb_seg_max = ICE_MAX_RING_DESC, 4191 }; 4192 4193 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M | 4194 RTE_ETH_LINK_SPEED_100M | 4195 RTE_ETH_LINK_SPEED_1G | 4196 RTE_ETH_LINK_SPEED_2_5G | 4197 RTE_ETH_LINK_SPEED_5G | 4198 RTE_ETH_LINK_SPEED_10G | 4199 RTE_ETH_LINK_SPEED_20G | 4200 RTE_ETH_LINK_SPEED_25G; 4201 4202 phy_type_low = hw->port_info->phy.phy_type_low; 4203 phy_type_high = hw->port_info->phy.phy_type_high; 4204 4205 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 4206 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_50G; 4207 4208 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 4209 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 4210 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100G; 4211 4212 if (ICE_PHY_TYPE_SUPPORT_200G_HIGH(phy_type_high)) 4213 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_200G; 4214 4215 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 4216 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 4217 4218 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 4219 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 4220 dev_info->default_rxportconf.nb_queues = 1; 4221 dev_info->default_txportconf.nb_queues = 1; 4222 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 4223 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 4224 4225 dev_info->rx_seg_capa.max_nseg = ICE_RX_MAX_NSEG; 4226 dev_info->rx_seg_capa.multi_pools = 1; 4227 dev_info->rx_seg_capa.offset_allowed = 0; 4228 dev_info->rx_seg_capa.offset_align_log2 = 0; 4229 4230 return 0; 4231 } 4232 4233 static inline int 4234 ice_atomic_read_link_status(struct rte_eth_dev *dev, 4235 struct rte_eth_link *link) 4236 { 4237 struct rte_eth_link *dst = link; 4238 struct rte_eth_link *src = &dev->data->dev_link; 4239 4240 /* NOTE: review for potential ordering optimization */ 4241 if (!rte_atomic_compare_exchange_strong_explicit((uint64_t __rte_atomic *)dst, 4242 (uint64_t *)dst, *(uint64_t *)src, 4243 rte_memory_order_seq_cst, rte_memory_order_seq_cst)) 4244 return -1; 4245 4246 return 0; 4247 } 4248 4249 static inline int 4250 ice_atomic_write_link_status(struct rte_eth_dev *dev, 4251 struct rte_eth_link *link) 4252 { 4253 struct rte_eth_link *dst = &dev->data->dev_link; 4254 struct rte_eth_link *src = link; 4255 4256 /* NOTE: review for potential ordering optimization */ 4257 if (!rte_atomic_compare_exchange_strong_explicit((uint64_t __rte_atomic *)dst, 4258 (uint64_t *)dst, *(uint64_t *)src, 4259 rte_memory_order_seq_cst, rte_memory_order_seq_cst)) 4260 return -1; 4261 4262 return 0; 4263 } 4264 4265 static int 4266 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4267 { 4268 #define CHECK_INTERVAL 50 /* 50ms */ 4269 #define MAX_REPEAT_TIME 40 /* 2s (40 * 50ms) in total */ 4270 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4271 struct ice_link_status link_status; 4272 struct rte_eth_link link, old; 4273 int status; 4274 unsigned int rep_cnt = MAX_REPEAT_TIME; 4275 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 4276 4277 memset(&link, 0, sizeof(link)); 4278 memset(&old, 0, sizeof(old)); 4279 memset(&link_status, 0, sizeof(link_status)); 4280 ice_atomic_read_link_status(dev, &old); 4281 4282 do { 4283 /* Get link status information from hardware */ 4284 status = ice_get_link_info_safe(pf, enable_lse, &link_status); 4285 if (status != ICE_SUCCESS) { 4286 link.link_speed = RTE_ETH_SPEED_NUM_100M; 4287 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 4288 PMD_DRV_LOG(ERR, "Failed to get link info"); 4289 goto out; 4290 } 4291 4292 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 4293 if (!wait_to_complete || link.link_status) 4294 break; 4295 4296 rte_delay_ms(CHECK_INTERVAL); 4297 } while (--rep_cnt); 4298 4299 if (!link.link_status) 4300 goto out; 4301 4302 /* Full-duplex operation at all supported speeds */ 4303 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 4304 4305 /* Parse the link status */ 4306 switch (link_status.link_speed) { 4307 case ICE_AQ_LINK_SPEED_10MB: 4308 link.link_speed = RTE_ETH_SPEED_NUM_10M; 4309 break; 4310 case ICE_AQ_LINK_SPEED_100MB: 4311 link.link_speed = RTE_ETH_SPEED_NUM_100M; 4312 break; 4313 case ICE_AQ_LINK_SPEED_1000MB: 4314 link.link_speed = RTE_ETH_SPEED_NUM_1G; 4315 break; 4316 case ICE_AQ_LINK_SPEED_2500MB: 4317 link.link_speed = RTE_ETH_SPEED_NUM_2_5G; 4318 break; 4319 case ICE_AQ_LINK_SPEED_5GB: 4320 link.link_speed = RTE_ETH_SPEED_NUM_5G; 4321 break; 4322 case ICE_AQ_LINK_SPEED_10GB: 4323 link.link_speed = RTE_ETH_SPEED_NUM_10G; 4324 break; 4325 case ICE_AQ_LINK_SPEED_20GB: 4326 link.link_speed = RTE_ETH_SPEED_NUM_20G; 4327 break; 4328 case ICE_AQ_LINK_SPEED_25GB: 4329 link.link_speed = RTE_ETH_SPEED_NUM_25G; 4330 break; 4331 case ICE_AQ_LINK_SPEED_40GB: 4332 link.link_speed = RTE_ETH_SPEED_NUM_40G; 4333 break; 4334 case ICE_AQ_LINK_SPEED_50GB: 4335 link.link_speed = RTE_ETH_SPEED_NUM_50G; 4336 break; 4337 case ICE_AQ_LINK_SPEED_100GB: 4338 link.link_speed = RTE_ETH_SPEED_NUM_100G; 4339 break; 4340 case ICE_AQ_LINK_SPEED_200GB: 4341 link.link_speed = RTE_ETH_SPEED_NUM_200G; 4342 break; 4343 case ICE_AQ_LINK_SPEED_UNKNOWN: 4344 PMD_DRV_LOG(ERR, "Unknown link speed"); 4345 link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN; 4346 break; 4347 default: 4348 PMD_DRV_LOG(ERR, "None link speed"); 4349 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 4350 break; 4351 } 4352 4353 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 4354 RTE_ETH_LINK_SPEED_FIXED); 4355 4356 out: 4357 ice_atomic_write_link_status(dev, &link); 4358 if (link.link_status == old.link_status) 4359 return -1; 4360 4361 return 0; 4362 } 4363 4364 static inline uint16_t 4365 ice_parse_link_speeds(uint16_t link_speeds) 4366 { 4367 uint16_t link_speed = ICE_AQ_LINK_SPEED_UNKNOWN; 4368 4369 if (link_speeds & RTE_ETH_LINK_SPEED_200G) 4370 link_speed |= ICE_AQ_LINK_SPEED_200GB; 4371 if (link_speeds & RTE_ETH_LINK_SPEED_100G) 4372 link_speed |= ICE_AQ_LINK_SPEED_100GB; 4373 if (link_speeds & RTE_ETH_LINK_SPEED_50G) 4374 link_speed |= ICE_AQ_LINK_SPEED_50GB; 4375 if (link_speeds & RTE_ETH_LINK_SPEED_40G) 4376 link_speed |= ICE_AQ_LINK_SPEED_40GB; 4377 if (link_speeds & RTE_ETH_LINK_SPEED_25G) 4378 link_speed |= ICE_AQ_LINK_SPEED_25GB; 4379 if (link_speeds & RTE_ETH_LINK_SPEED_20G) 4380 link_speed |= ICE_AQ_LINK_SPEED_20GB; 4381 if (link_speeds & RTE_ETH_LINK_SPEED_10G) 4382 link_speed |= ICE_AQ_LINK_SPEED_10GB; 4383 if (link_speeds & RTE_ETH_LINK_SPEED_5G) 4384 link_speed |= ICE_AQ_LINK_SPEED_5GB; 4385 if (link_speeds & RTE_ETH_LINK_SPEED_2_5G) 4386 link_speed |= ICE_AQ_LINK_SPEED_2500MB; 4387 if (link_speeds & RTE_ETH_LINK_SPEED_1G) 4388 link_speed |= ICE_AQ_LINK_SPEED_1000MB; 4389 if (link_speeds & RTE_ETH_LINK_SPEED_100M) 4390 link_speed |= ICE_AQ_LINK_SPEED_100MB; 4391 4392 return link_speed; 4393 } 4394 4395 static int 4396 ice_apply_link_speed(struct rte_eth_dev *dev) 4397 { 4398 uint16_t speed; 4399 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4400 struct rte_eth_conf *conf = &dev->data->dev_conf; 4401 4402 if (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 4403 conf->link_speeds = RTE_ETH_LINK_SPEED_200G | 4404 RTE_ETH_LINK_SPEED_100G | 4405 RTE_ETH_LINK_SPEED_50G | 4406 RTE_ETH_LINK_SPEED_40G | 4407 RTE_ETH_LINK_SPEED_25G | 4408 RTE_ETH_LINK_SPEED_20G | 4409 RTE_ETH_LINK_SPEED_10G | 4410 RTE_ETH_LINK_SPEED_5G | 4411 RTE_ETH_LINK_SPEED_2_5G | 4412 RTE_ETH_LINK_SPEED_1G | 4413 RTE_ETH_LINK_SPEED_100M; 4414 } 4415 speed = ice_parse_link_speeds(conf->link_speeds); 4416 4417 return ice_phy_conf_link(hw, speed, true); 4418 } 4419 4420 static int 4421 ice_phy_conf_link(struct ice_hw *hw, 4422 u16 link_speeds_bitmap, 4423 bool link_up) 4424 { 4425 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 4426 struct ice_port_info *pi = hw->port_info; 4427 struct ice_aqc_get_phy_caps_data *phy_caps; 4428 int err; 4429 u64 phy_type_low = 0; 4430 u64 phy_type_high = 0; 4431 4432 phy_caps = (struct ice_aqc_get_phy_caps_data *) 4433 ice_malloc(hw, sizeof(*phy_caps)); 4434 if (!phy_caps) 4435 return ICE_ERR_NO_MEMORY; 4436 4437 if (!pi) 4438 return -EIO; 4439 4440 4441 if (ice_fw_supports_report_dflt_cfg(pi->hw)) 4442 err = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_DFLT_CFG, 4443 phy_caps, NULL); 4444 else 4445 err = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 4446 phy_caps, NULL); 4447 if (err) 4448 goto done; 4449 4450 ice_update_phy_type(&phy_type_low, &phy_type_high, link_speeds_bitmap); 4451 4452 if (link_speeds_bitmap == ICE_LINK_SPEED_UNKNOWN) { 4453 cfg.phy_type_low = phy_caps->phy_type_low; 4454 cfg.phy_type_high = phy_caps->phy_type_high; 4455 } else if (phy_type_low & phy_caps->phy_type_low || 4456 phy_type_high & phy_caps->phy_type_high) { 4457 cfg.phy_type_low = phy_type_low & phy_caps->phy_type_low; 4458 cfg.phy_type_high = phy_type_high & phy_caps->phy_type_high; 4459 } else { 4460 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!"); 4461 cfg.phy_type_low = phy_caps->phy_type_low; 4462 cfg.phy_type_high = phy_caps->phy_type_high; 4463 } 4464 4465 cfg.caps = phy_caps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 4466 cfg.low_power_ctrl_an = phy_caps->low_power_ctrl_an; 4467 cfg.eee_cap = phy_caps->eee_cap; 4468 cfg.eeer_value = phy_caps->eeer_value; 4469 cfg.link_fec_opt = phy_caps->link_fec_options; 4470 if (link_up) 4471 cfg.caps |= ICE_AQ_PHY_ENA_LINK; 4472 else 4473 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK; 4474 4475 err = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 4476 4477 done: 4478 ice_free(hw, phy_caps); 4479 return err; 4480 } 4481 4482 static int 4483 ice_dev_set_link_up(struct rte_eth_dev *dev) 4484 { 4485 return ice_apply_link_speed(dev); 4486 } 4487 4488 static int 4489 ice_dev_set_link_down(struct rte_eth_dev *dev) 4490 { 4491 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4492 uint8_t speed = ICE_LINK_SPEED_UNKNOWN; 4493 4494 return ice_phy_conf_link(hw, speed, false); 4495 } 4496 4497 static int 4498 ice_dev_led_on(struct rte_eth_dev *dev) 4499 { 4500 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4501 int status = ice_aq_set_port_id_led(hw->port_info, false, NULL); 4502 4503 return status == ICE_SUCCESS ? 0 : -ENOTSUP; 4504 } 4505 4506 static int 4507 ice_dev_led_off(struct rte_eth_dev *dev) 4508 { 4509 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4510 int status = ice_aq_set_port_id_led(hw->port_info, true, NULL); 4511 4512 return status == ICE_SUCCESS ? 0 : -ENOTSUP; 4513 } 4514 4515 static int 4516 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu __rte_unused) 4517 { 4518 /* mtu setting is forbidden if port is start */ 4519 if (dev->data->dev_started != 0) { 4520 PMD_DRV_LOG(ERR, 4521 "port %d must be stopped before configuration", 4522 dev->data->port_id); 4523 return -EBUSY; 4524 } 4525 4526 return 0; 4527 } 4528 4529 static int ice_macaddr_set(struct rte_eth_dev *dev, 4530 struct rte_ether_addr *mac_addr) 4531 { 4532 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4533 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4534 struct ice_vsi *vsi = pf->main_vsi; 4535 struct ice_mac_filter *f; 4536 uint8_t flags = 0; 4537 int ret; 4538 4539 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 4540 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 4541 return -EINVAL; 4542 } 4543 4544 TAILQ_FOREACH(f, &vsi->mac_list, next) { 4545 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 4546 break; 4547 } 4548 4549 if (!f) { 4550 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 4551 return -EIO; 4552 } 4553 4554 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 4555 if (ret != ICE_SUCCESS) { 4556 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 4557 return -EIO; 4558 } 4559 ret = ice_add_mac_filter(vsi, mac_addr); 4560 if (ret != ICE_SUCCESS) { 4561 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 4562 return -EIO; 4563 } 4564 rte_ether_addr_copy(mac_addr, &pf->dev_addr); 4565 4566 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 4567 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 4568 if (ret != ICE_SUCCESS) 4569 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 4570 4571 return 0; 4572 } 4573 4574 /* Add a MAC address, and update filters */ 4575 static int 4576 ice_macaddr_add(struct rte_eth_dev *dev, 4577 struct rte_ether_addr *mac_addr, 4578 __rte_unused uint32_t index, 4579 __rte_unused uint32_t pool) 4580 { 4581 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4582 struct ice_vsi *vsi = pf->main_vsi; 4583 int ret; 4584 4585 ret = ice_add_mac_filter(vsi, mac_addr); 4586 if (ret != ICE_SUCCESS) { 4587 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 4588 return -EINVAL; 4589 } 4590 4591 return ICE_SUCCESS; 4592 } 4593 4594 /* Remove a MAC address, and update filters */ 4595 static void 4596 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 4597 { 4598 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4599 struct ice_vsi *vsi = pf->main_vsi; 4600 struct rte_eth_dev_data *data = dev->data; 4601 struct rte_ether_addr *macaddr; 4602 int ret; 4603 4604 macaddr = &data->mac_addrs[index]; 4605 ret = ice_remove_mac_filter(vsi, macaddr); 4606 if (ret) { 4607 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 4608 return; 4609 } 4610 } 4611 4612 static int 4613 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 4614 { 4615 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4616 struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id); 4617 struct ice_vsi *vsi = pf->main_vsi; 4618 int ret; 4619 4620 PMD_INIT_FUNC_TRACE(); 4621 4622 /** 4623 * Vlan 0 is the generic filter for untagged packets 4624 * and can't be removed or added by user. 4625 */ 4626 if (vlan_id == 0) 4627 return 0; 4628 4629 if (on) { 4630 ret = ice_add_vlan_filter(vsi, &vlan); 4631 if (ret < 0) { 4632 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 4633 return -EINVAL; 4634 } 4635 } else { 4636 ret = ice_remove_vlan_filter(vsi, &vlan); 4637 if (ret < 0) { 4638 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 4639 return -EINVAL; 4640 } 4641 } 4642 4643 return 0; 4644 } 4645 4646 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are 4647 * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8) 4648 * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via 4649 * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID. 4650 * 4651 * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic 4652 * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged 4653 * traffic in SVM, since the VLAN TPID isn't part of filtering. 4654 * 4655 * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be 4656 * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is 4657 * part of filtering. 4658 */ 4659 static int 4660 ice_vsi_add_vlan_zero(struct ice_vsi *vsi) 4661 { 4662 struct ice_vlan vlan; 4663 int err; 4664 4665 vlan = ICE_VLAN(0, 0); 4666 err = ice_add_vlan_filter(vsi, &vlan); 4667 if (err) { 4668 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0"); 4669 return err; 4670 } 4671 4672 /* in SVM both VLAN 0 filters are identical */ 4673 if (!ice_is_dvm_ena(&vsi->adapter->hw)) 4674 return 0; 4675 4676 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0); 4677 err = ice_add_vlan_filter(vsi, &vlan); 4678 if (err) { 4679 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode"); 4680 return err; 4681 } 4682 4683 return 0; 4684 } 4685 4686 /* 4687 * Delete the VLAN 0 filters in the same manner that they were added in 4688 * ice_vsi_add_vlan_zero. 4689 */ 4690 static int 4691 ice_vsi_del_vlan_zero(struct ice_vsi *vsi) 4692 { 4693 struct ice_vlan vlan; 4694 int err; 4695 4696 vlan = ICE_VLAN(0, 0); 4697 err = ice_remove_vlan_filter(vsi, &vlan); 4698 if (err) { 4699 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0"); 4700 return err; 4701 } 4702 4703 /* in SVM both VLAN 0 filters are identical */ 4704 if (!ice_is_dvm_ena(&vsi->adapter->hw)) 4705 return 0; 4706 4707 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0); 4708 err = ice_remove_vlan_filter(vsi, &vlan); 4709 if (err) { 4710 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode"); 4711 return err; 4712 } 4713 4714 return 0; 4715 } 4716 4717 /* Configure vlan filter on or off */ 4718 static int 4719 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 4720 { 4721 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4722 struct ice_vsi_ctx ctxt; 4723 uint8_t sw_flags2; 4724 int ret = 0; 4725 4726 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 4727 4728 if (on) 4729 vsi->info.sw_flags2 |= sw_flags2; 4730 else 4731 vsi->info.sw_flags2 &= ~sw_flags2; 4732 4733 vsi->info.sw_id = hw->port_info->sw_id; 4734 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 4735 ctxt.info.valid_sections = 4736 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 4737 ICE_AQ_VSI_PROP_SECURITY_VALID); 4738 ctxt.vsi_num = vsi->vsi_id; 4739 4740 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4741 if (ret) { 4742 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 4743 on ? "enable" : "disable"); 4744 return -EINVAL; 4745 } else { 4746 vsi->info.valid_sections |= 4747 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 4748 ICE_AQ_VSI_PROP_SECURITY_VALID); 4749 } 4750 4751 /* consist with other drivers, allow untagged packet when vlan filter on */ 4752 if (on) 4753 ret = ice_vsi_add_vlan_zero(vsi); 4754 else 4755 ret = ice_vsi_del_vlan_zero(vsi); 4756 4757 return 0; 4758 } 4759 4760 /* Manage VLAN stripping for the VSI for Rx */ 4761 static int 4762 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena) 4763 { 4764 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4765 struct ice_vsi_ctx ctxt; 4766 int status, err = 0; 4767 4768 /* do not allow modifying VLAN stripping when a port VLAN is configured 4769 * on this VSI 4770 */ 4771 if (vsi->info.port_based_inner_vlan) 4772 return 0; 4773 4774 memset(&ctxt, 0, sizeof(ctxt)); 4775 4776 if (ena) 4777 /* Strip VLAN tag from Rx packet and put it in the desc */ 4778 ctxt.info.inner_vlan_flags = 4779 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH; 4780 else 4781 /* Disable stripping. Leave tag in packet */ 4782 ctxt.info.inner_vlan_flags = 4783 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; 4784 4785 /* Allow all packets untagged/tagged */ 4786 ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; 4787 4788 ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 4789 4790 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4791 if (status) { 4792 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping", 4793 ena ? "enable" : "disable"); 4794 err = -EIO; 4795 } else { 4796 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags; 4797 } 4798 4799 return err; 4800 } 4801 4802 static int 4803 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi) 4804 { 4805 return ice_vsi_manage_vlan_stripping(vsi, true); 4806 } 4807 4808 static int 4809 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi) 4810 { 4811 return ice_vsi_manage_vlan_stripping(vsi, false); 4812 } 4813 4814 /** 4815 * tpid_to_vsi_outer_vlan_type - convert from TPID to VSI context based tag_type 4816 * @tpid: tpid used to translate into VSI context based tag_type 4817 * @tag_type: output variable to hold the VSI context based tag type 4818 */ 4819 static int tpid_to_vsi_outer_vlan_type(u16 tpid, u8 *tag_type) 4820 { 4821 switch (tpid) { 4822 case RTE_ETHER_TYPE_VLAN: 4823 *tag_type = ICE_AQ_VSI_OUTER_TAG_VLAN_8100; 4824 break; 4825 case RTE_ETHER_TYPE_QINQ: 4826 *tag_type = ICE_AQ_VSI_OUTER_TAG_STAG; 4827 break; 4828 case RTE_ETHER_TYPE_QINQ1: 4829 *tag_type = ICE_AQ_VSI_OUTER_TAG_VLAN_9100; 4830 break; 4831 default: 4832 *tag_type = 0; 4833 return -EINVAL; 4834 } 4835 4836 return 0; 4837 } 4838 4839 /** 4840 * ice_is_supported_port_vlan_proto - make sure the vlan_proto is supported 4841 * @hw: hardware structure used to check the VLAN mode 4842 * @vlan_proto: VLAN TPID being checked 4843 * 4844 * If the device is configured in Double VLAN Mode (DVM), it supports three 4845 * types: RTE_ETHER_TYPE_VLAN, RTE_ETHER_TYPE_QINQ1 and RTE_ETHER_TYPE_QINQ. If the device is 4846 * configured in Single VLAN Mode (SVM), then only RTE_ETHER_TYPE_VLAN is supported. 4847 */ 4848 static bool 4849 ice_is_supported_port_vlan_proto(struct ice_hw *hw, u16 vlan_proto) 4850 { 4851 bool is_supported = false; 4852 4853 switch (vlan_proto) { 4854 case RTE_ETHER_TYPE_VLAN: 4855 is_supported = true; 4856 break; 4857 case RTE_ETHER_TYPE_QINQ: 4858 if (ice_is_dvm_ena(hw)) 4859 is_supported = true; 4860 break; 4861 case RTE_ETHER_TYPE_QINQ1: 4862 if (ice_is_dvm_ena(hw)) 4863 is_supported = true; 4864 break; 4865 } 4866 4867 return is_supported; 4868 } 4869 4870 /** 4871 * ice_vsi_ena_outer_stripping - enable outer VLAN stripping 4872 * @vsi: VSI to configure 4873 * @tpid: TPID to enable outer VLAN stripping for 4874 * 4875 * Enable outer VLAN stripping via VSI context. This function should only be 4876 * used if DVM is supported. 4877 * 4878 * Since the VSI context only supports a single TPID for insertion and 4879 * stripping, setting the TPID for stripping will affect the TPID for insertion. 4880 * Callers need to be aware of this limitation. 4881 * 4882 * Only modify outer VLAN stripping settings and the VLAN TPID. Outer VLAN 4883 * insertion settings are unmodified. 4884 * 4885 * This enables hardware to strip a VLAN tag with the specified TPID to be 4886 * stripped from the packet and placed in the receive descriptor. 4887 */ 4888 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi, u16 tpid) 4889 { 4890 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4891 struct ice_vsi_ctx ctxt; 4892 int status, err = 0; 4893 u8 tag_type; 4894 4895 /* do not allow modifying VLAN stripping when a port VLAN is configured 4896 * on this VSI 4897 */ 4898 if (vsi->info.port_based_outer_vlan) 4899 return 0; 4900 4901 if (tpid_to_vsi_outer_vlan_type(tpid, &tag_type)) 4902 return -EINVAL; 4903 4904 memset(&ctxt, 0, sizeof(ctxt)); 4905 4906 ctxt.info.valid_sections = 4907 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 4908 /* clear current outer VLAN strip settings */ 4909 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags & 4910 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M); 4911 ctxt.info.outer_vlan_flags |= 4912 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH << 4913 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) | 4914 ((tag_type << ICE_AQ_VSI_OUTER_TAG_TYPE_S) & 4915 ICE_AQ_VSI_OUTER_TAG_TYPE_M); 4916 4917 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4918 if (status) { 4919 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping"); 4920 err = -EIO; 4921 } else { 4922 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags; 4923 } 4924 4925 return err; 4926 } 4927 4928 static int 4929 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi) 4930 { 4931 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4932 struct ice_vsi_ctx ctxt; 4933 int status, err = 0; 4934 4935 if (vsi->info.port_based_outer_vlan) 4936 return 0; 4937 4938 memset(&ctxt, 0, sizeof(ctxt)); 4939 4940 ctxt.info.valid_sections = 4941 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 4942 /* clear current outer VLAN strip settings */ 4943 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags & 4944 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M; 4945 ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING << 4946 ICE_AQ_VSI_OUTER_VLAN_EMODE_S; 4947 4948 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 4949 if (status) { 4950 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping"); 4951 err = -EIO; 4952 } else { 4953 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags; 4954 } 4955 4956 return err; 4957 } 4958 4959 static int 4960 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena) 4961 { 4962 int ret; 4963 4964 if (ena) 4965 ret = ice_vsi_ena_inner_stripping(vsi); 4966 else 4967 ret = ice_vsi_dis_inner_stripping(vsi); 4968 4969 return ret; 4970 } 4971 4972 /** 4973 * ice_vsi_update_l2tsel - update l2tsel field for all Rx rings on this VSI 4974 * @vsi: VSI used to update l2tsel on 4975 * @l2tsel: l2tsel setting requested 4976 * 4977 * Use the l2tsel setting to update all of the Rx queue context bits for l2tsel. 4978 * This will modify which descriptor field the first offloaded VLAN will be 4979 * stripped into. 4980 */ 4981 static void ice_vsi_update_l2tsel(struct ice_vsi *vsi, enum ice_l2tsel l2tsel) 4982 { 4983 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4984 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 4985 struct rte_eth_dev_data *dev_data = pf->dev_data; 4986 u32 l2tsel_bit; 4987 uint16_t i; 4988 4989 if (l2tsel == ICE_L2TSEL_EXTRACT_FIRST_TAG_L2TAG2_2ND) 4990 l2tsel_bit = 0; 4991 else 4992 l2tsel_bit = BIT(ICE_L2TSEL_BIT_OFFSET); 4993 4994 for (i = 0; i < dev_data->nb_rx_queues; i++) { 4995 u32 qrx_context_offset; 4996 u32 regval; 4997 4998 qrx_context_offset = 4999 QRX_CONTEXT(ICE_L2TSEL_QRX_CONTEXT_REG_IDX, i); 5000 5001 regval = rd32(hw, qrx_context_offset); 5002 regval &= ~BIT(ICE_L2TSEL_BIT_OFFSET); 5003 regval |= l2tsel_bit; 5004 wr32(hw, qrx_context_offset, regval); 5005 } 5006 } 5007 5008 /* Configure outer vlan stripping on or off in QinQ mode */ 5009 static int 5010 ice_vsi_config_outer_vlan_stripping(struct ice_vsi *vsi, bool on) 5011 { 5012 uint16_t outer_ethertype = vsi->adapter->pf.outer_ethertype; 5013 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 5014 int err = 0; 5015 5016 if (vsi->vsi_id >= ICE_MAX_NUM_VSIS) { 5017 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum"); 5018 return -EINVAL; 5019 } 5020 5021 if (!ice_is_dvm_ena(hw)) { 5022 PMD_DRV_LOG(ERR, "Single VLAN mode (SVM) does not support qinq"); 5023 return -EOPNOTSUPP; 5024 } 5025 5026 if (on) { 5027 err = ice_vsi_ena_outer_stripping(vsi, outer_ethertype); 5028 if (!err) { 5029 enum ice_l2tsel l2tsel = 5030 ICE_L2TSEL_EXTRACT_FIRST_TAG_L2TAG2_2ND; 5031 5032 /* PF tells the VF that the outer VLAN tag is always 5033 * extracted to VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2 and 5034 * inner is always extracted to 5035 * VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1. This is needed to 5036 * support outer stripping so the first tag always ends 5037 * up in L2TAG2_2ND and the second/inner tag, if 5038 * enabled, is extracted in L2TAG1. 5039 */ 5040 ice_vsi_update_l2tsel(vsi, l2tsel); 5041 } 5042 } else { 5043 err = ice_vsi_dis_outer_stripping(vsi); 5044 if (!err) { 5045 enum ice_l2tsel l2tsel = 5046 ICE_L2TSEL_EXTRACT_FIRST_TAG_L2TAG1; 5047 5048 /* PF tells the VF that the outer VLAN tag is always 5049 * extracted to VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2 and 5050 * inner is always extracted to 5051 * VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1. This is needed to 5052 * support inner stripping while outer stripping is 5053 * disabled so that the first and only tag is extracted 5054 * in L2TAG1. 5055 */ 5056 ice_vsi_update_l2tsel(vsi, l2tsel); 5057 } 5058 } 5059 5060 return err; 5061 } 5062 5063 static int 5064 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5065 { 5066 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5067 struct ice_vsi *vsi = pf->main_vsi; 5068 struct rte_eth_rxmode *rxmode; 5069 5070 rxmode = &dev->data->dev_conf.rxmode; 5071 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 5072 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 5073 ice_vsi_config_vlan_filter(vsi, true); 5074 else 5075 ice_vsi_config_vlan_filter(vsi, false); 5076 } 5077 5078 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 5079 if (!ice_is_dvm_ena(hw)) { 5080 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 5081 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 5082 ice_vsi_config_vlan_stripping(vsi, true); 5083 else 5084 ice_vsi_config_vlan_stripping(vsi, false); 5085 } 5086 5087 if (mask & RTE_ETH_QINQ_STRIP_MASK) { 5088 PMD_DRV_LOG(ERR, "Single VLAN mode (SVM) does not support qinq"); 5089 return -ENOTSUP; 5090 } 5091 } else { 5092 if ((mask & RTE_ETH_VLAN_STRIP_MASK) | 5093 (mask & RTE_ETH_QINQ_STRIP_MASK)) { 5094 if (rxmode->offloads & (RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 5095 RTE_ETH_RX_OFFLOAD_QINQ_STRIP)) 5096 ice_vsi_config_outer_vlan_stripping(vsi, true); 5097 else 5098 ice_vsi_config_outer_vlan_stripping(vsi, false); 5099 } 5100 5101 if (mask & RTE_ETH_QINQ_STRIP_MASK) { 5102 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) 5103 ice_vsi_config_vlan_stripping(vsi, true); 5104 else 5105 ice_vsi_config_vlan_stripping(vsi, false); 5106 } 5107 } 5108 5109 return 0; 5110 } 5111 5112 static int 5113 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 5114 { 5115 struct ice_aq_get_set_rss_lut_params lut_params; 5116 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 5117 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 5118 int ret; 5119 5120 if (!lut) 5121 return -EINVAL; 5122 5123 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 5124 lut_params.vsi_handle = vsi->idx; 5125 lut_params.lut_size = lut_size; 5126 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; 5127 lut_params.lut = lut; 5128 lut_params.global_lut_id = 0; 5129 ret = ice_aq_get_rss_lut(hw, &lut_params); 5130 if (ret) { 5131 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 5132 return -EINVAL; 5133 } 5134 } else { 5135 uint64_t *lut_dw = (uint64_t *)lut; 5136 uint16_t i, lut_size_dw = lut_size / 4; 5137 5138 for (i = 0; i < lut_size_dw; i++) 5139 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 5140 } 5141 5142 return 0; 5143 } 5144 5145 static int 5146 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 5147 { 5148 struct ice_aq_get_set_rss_lut_params lut_params; 5149 struct ice_pf *pf; 5150 struct ice_hw *hw; 5151 int ret; 5152 5153 if (!vsi || !lut) 5154 return -EINVAL; 5155 5156 pf = ICE_VSI_TO_PF(vsi); 5157 hw = ICE_VSI_TO_HW(vsi); 5158 5159 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 5160 lut_params.vsi_handle = vsi->idx; 5161 lut_params.lut_size = lut_size; 5162 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF; 5163 lut_params.lut = lut; 5164 lut_params.global_lut_id = 0; 5165 ret = ice_aq_set_rss_lut(hw, &lut_params); 5166 if (ret) { 5167 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 5168 return -EINVAL; 5169 } 5170 } else { 5171 uint64_t *lut_dw = (uint64_t *)lut; 5172 uint16_t i, lut_size_dw = lut_size / 4; 5173 5174 for (i = 0; i < lut_size_dw; i++) 5175 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 5176 5177 ice_flush(hw); 5178 } 5179 5180 return 0; 5181 } 5182 5183 static int 5184 ice_rss_reta_update(struct rte_eth_dev *dev, 5185 struct rte_eth_rss_reta_entry64 *reta_conf, 5186 uint16_t reta_size) 5187 { 5188 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5189 uint16_t i, lut_size = pf->hash_lut_size; 5190 uint16_t idx, shift; 5191 uint8_t *lut; 5192 int ret; 5193 5194 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 && 5195 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 && 5196 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) { 5197 PMD_DRV_LOG(ERR, 5198 "The size of hash lookup table configured (%d)" 5199 "doesn't match the number hardware can " 5200 "supported (128, 512, 2048)", 5201 reta_size); 5202 return -EINVAL; 5203 } 5204 5205 /* It MUST use the current LUT size to get the RSS lookup table, 5206 * otherwise if will fail with -100 error code. 5207 */ 5208 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0); 5209 if (!lut) { 5210 PMD_DRV_LOG(ERR, "No memory can be allocated"); 5211 return -ENOMEM; 5212 } 5213 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size); 5214 if (ret) 5215 goto out; 5216 5217 for (i = 0; i < reta_size; i++) { 5218 idx = i / RTE_ETH_RETA_GROUP_SIZE; 5219 shift = i % RTE_ETH_RETA_GROUP_SIZE; 5220 if (reta_conf[idx].mask & (1ULL << shift)) 5221 lut[i] = reta_conf[idx].reta[shift]; 5222 } 5223 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 5224 if (ret == 0 && lut_size != reta_size) { 5225 PMD_DRV_LOG(INFO, 5226 "The size of hash lookup table is changed from (%d) to (%d)", 5227 lut_size, reta_size); 5228 pf->hash_lut_size = reta_size; 5229 } 5230 5231 out: 5232 rte_free(lut); 5233 5234 return ret; 5235 } 5236 5237 static int 5238 ice_rss_reta_query(struct rte_eth_dev *dev, 5239 struct rte_eth_rss_reta_entry64 *reta_conf, 5240 uint16_t reta_size) 5241 { 5242 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5243 uint16_t i, lut_size = pf->hash_lut_size; 5244 uint16_t idx, shift; 5245 uint8_t *lut; 5246 int ret; 5247 5248 if (reta_size != lut_size) { 5249 PMD_DRV_LOG(ERR, 5250 "The size of hash lookup table configured (%d)" 5251 "doesn't match the number hardware can " 5252 "supported (%d)", 5253 reta_size, lut_size); 5254 return -EINVAL; 5255 } 5256 5257 lut = rte_zmalloc(NULL, reta_size, 0); 5258 if (!lut) { 5259 PMD_DRV_LOG(ERR, "No memory can be allocated"); 5260 return -ENOMEM; 5261 } 5262 5263 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 5264 if (ret) 5265 goto out; 5266 5267 for (i = 0; i < reta_size; i++) { 5268 idx = i / RTE_ETH_RETA_GROUP_SIZE; 5269 shift = i % RTE_ETH_RETA_GROUP_SIZE; 5270 if (reta_conf[idx].mask & (1ULL << shift)) 5271 reta_conf[idx].reta[shift] = lut[i]; 5272 } 5273 5274 out: 5275 rte_free(lut); 5276 5277 return ret; 5278 } 5279 5280 static int 5281 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 5282 { 5283 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 5284 int ret = 0; 5285 5286 if (!key || key_len == 0) { 5287 PMD_DRV_LOG(DEBUG, "No key to be configured"); 5288 return 0; 5289 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 5290 sizeof(uint32_t)) { 5291 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 5292 return -EINVAL; 5293 } 5294 5295 struct ice_aqc_get_set_rss_keys *key_dw = 5296 (struct ice_aqc_get_set_rss_keys *)key; 5297 5298 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 5299 if (ret) { 5300 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 5301 ret = -EINVAL; 5302 } 5303 5304 return ret; 5305 } 5306 5307 static int 5308 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 5309 { 5310 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 5311 int ret; 5312 5313 if (!key || !key_len) 5314 return -EINVAL; 5315 5316 ret = ice_aq_get_rss_key 5317 (hw, vsi->idx, 5318 (struct ice_aqc_get_set_rss_keys *)key); 5319 if (ret) { 5320 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 5321 return -EINVAL; 5322 } 5323 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 5324 5325 return 0; 5326 } 5327 5328 static int 5329 ice_rss_hash_update(struct rte_eth_dev *dev, 5330 struct rte_eth_rss_conf *rss_conf) 5331 { 5332 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5333 struct ice_vsi *vsi = pf->main_vsi; 5334 int status; 5335 5336 /* set hash key */ 5337 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 5338 if (status) 5339 return status; 5340 5341 if (rss_conf->rss_hf == 0) 5342 pf->rss_hf = 0; 5343 5344 /* RSS hash configuration */ 5345 ice_rss_hash_set(pf, rss_conf->rss_hf); 5346 5347 return 0; 5348 } 5349 5350 static int 5351 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 5352 struct rte_eth_rss_conf *rss_conf) 5353 { 5354 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5355 struct ice_vsi *vsi = pf->main_vsi; 5356 5357 ice_get_rss_key(vsi, rss_conf->rss_key, 5358 &rss_conf->rss_key_len); 5359 5360 rss_conf->rss_hf = pf->rss_hf; 5361 return 0; 5362 } 5363 5364 static int 5365 ice_promisc_enable(struct rte_eth_dev *dev) 5366 { 5367 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5368 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5369 struct ice_vsi *vsi = pf->main_vsi; 5370 int status, ret = 0; 5371 ice_declare_bitmap(pmask, ICE_PROMISC_MAX); 5372 ice_zero_bitmap(pmask, ICE_PROMISC_MAX); 5373 5374 ice_set_bit(ICE_PROMISC_UCAST_RX, pmask); 5375 ice_set_bit(ICE_PROMISC_UCAST_TX, pmask); 5376 ice_set_bit(ICE_PROMISC_MCAST_RX, pmask); 5377 ice_set_bit(ICE_PROMISC_MCAST_TX, pmask); 5378 5379 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 5380 switch (status) { 5381 case ICE_ERR_ALREADY_EXISTS: 5382 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled"); 5383 case ICE_SUCCESS: 5384 break; 5385 default: 5386 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 5387 ret = -EAGAIN; 5388 } 5389 5390 return ret; 5391 } 5392 5393 static int 5394 ice_promisc_disable(struct rte_eth_dev *dev) 5395 { 5396 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5397 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5398 struct ice_vsi *vsi = pf->main_vsi; 5399 int status, ret = 0; 5400 ice_declare_bitmap(pmask, ICE_PROMISC_MAX); 5401 ice_zero_bitmap(pmask, ICE_PROMISC_MAX); 5402 5403 if (dev->data->all_multicast == 1) { 5404 ice_set_bit(ICE_PROMISC_UCAST_RX, pmask); 5405 ice_set_bit(ICE_PROMISC_UCAST_TX, pmask); 5406 } else { 5407 ice_set_bit(ICE_PROMISC_UCAST_RX, pmask); 5408 ice_set_bit(ICE_PROMISC_UCAST_TX, pmask); 5409 ice_set_bit(ICE_PROMISC_MCAST_RX, pmask); 5410 ice_set_bit(ICE_PROMISC_MCAST_TX, pmask); 5411 } 5412 5413 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 5414 if (status != ICE_SUCCESS) { 5415 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 5416 ret = -EAGAIN; 5417 } 5418 5419 return ret; 5420 } 5421 5422 static int 5423 ice_allmulti_enable(struct rte_eth_dev *dev) 5424 { 5425 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5426 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5427 struct ice_vsi *vsi = pf->main_vsi; 5428 int status, ret = 0; 5429 ice_declare_bitmap(pmask, ICE_PROMISC_MAX); 5430 ice_zero_bitmap(pmask, ICE_PROMISC_MAX); 5431 5432 ice_set_bit(ICE_PROMISC_MCAST_RX, pmask); 5433 ice_set_bit(ICE_PROMISC_MCAST_TX, pmask); 5434 5435 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 5436 5437 switch (status) { 5438 case ICE_ERR_ALREADY_EXISTS: 5439 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled"); 5440 case ICE_SUCCESS: 5441 break; 5442 default: 5443 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 5444 ret = -EAGAIN; 5445 } 5446 5447 return ret; 5448 } 5449 5450 static int 5451 ice_allmulti_disable(struct rte_eth_dev *dev) 5452 { 5453 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5454 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5455 struct ice_vsi *vsi = pf->main_vsi; 5456 int status, ret = 0; 5457 ice_declare_bitmap(pmask, ICE_PROMISC_MAX); 5458 ice_zero_bitmap(pmask, ICE_PROMISC_MAX); 5459 5460 if (dev->data->promiscuous == 1) 5461 return 0; /* must remain in all_multicast mode */ 5462 5463 ice_set_bit(ICE_PROMISC_MCAST_RX, pmask); 5464 ice_set_bit(ICE_PROMISC_MCAST_TX, pmask); 5465 5466 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 5467 if (status != ICE_SUCCESS) { 5468 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 5469 ret = -EAGAIN; 5470 } 5471 5472 return ret; 5473 } 5474 5475 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 5476 uint16_t queue_id) 5477 { 5478 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 5479 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5480 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5481 uint32_t val; 5482 uint16_t msix_intr; 5483 5484 msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id); 5485 5486 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 5487 GLINT_DYN_CTL_ITR_INDX_M; 5488 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 5489 5490 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 5491 rte_intr_ack(pci_dev->intr_handle); 5492 5493 return 0; 5494 } 5495 5496 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 5497 uint16_t queue_id) 5498 { 5499 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 5500 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 5501 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5502 uint16_t msix_intr; 5503 5504 msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id); 5505 5506 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 5507 5508 return 0; 5509 } 5510 5511 static int 5512 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 5513 { 5514 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5515 u8 ver, patch; 5516 u16 build; 5517 int ret; 5518 5519 ver = hw->flash.orom.major; 5520 patch = hw->flash.orom.patch; 5521 build = hw->flash.orom.build; 5522 5523 ret = snprintf(fw_version, fw_size, 5524 "%x.%02x 0x%08x %d.%d.%d", 5525 hw->flash.nvm.major, 5526 hw->flash.nvm.minor, 5527 hw->flash.nvm.eetrack, 5528 ver, build, patch); 5529 if (ret < 0) 5530 return -EINVAL; 5531 5532 /* add the size of '\0' */ 5533 ret += 1; 5534 if (fw_size < (size_t)ret) 5535 return ret; 5536 else 5537 return 0; 5538 } 5539 5540 static int 5541 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 5542 { 5543 struct ice_hw *hw; 5544 struct ice_vsi_ctx ctxt; 5545 uint8_t vlan_flags = 0; 5546 int ret; 5547 5548 if (!vsi || !info) { 5549 PMD_DRV_LOG(ERR, "invalid parameters"); 5550 return -EINVAL; 5551 } 5552 5553 if (info->on) { 5554 vsi->info.port_based_inner_vlan = info->config.pvid; 5555 /** 5556 * If insert pvid is enabled, only tagged pkts are 5557 * allowed to be sent out. 5558 */ 5559 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | 5560 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; 5561 } else { 5562 vsi->info.port_based_inner_vlan = 0; 5563 if (info->config.reject.tagged == 0) 5564 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED; 5565 5566 if (info->config.reject.untagged == 0) 5567 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; 5568 } 5569 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | 5570 ICE_AQ_VSI_INNER_VLAN_EMODE_M); 5571 vsi->info.inner_vlan_flags |= vlan_flags; 5572 memset(&ctxt, 0, sizeof(ctxt)); 5573 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 5574 ctxt.info.valid_sections = 5575 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 5576 ctxt.vsi_num = vsi->vsi_id; 5577 5578 hw = ICE_VSI_TO_HW(vsi); 5579 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 5580 if (ret != ICE_SUCCESS) { 5581 PMD_DRV_LOG(ERR, 5582 "update VSI for VLAN insert failed, err %d", 5583 ret); 5584 return -EINVAL; 5585 } 5586 5587 vsi->info.valid_sections |= 5588 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 5589 5590 return ret; 5591 } 5592 5593 /** 5594 * ice_vsi_set_outer_port_vlan - set the outer port VLAN and related settings 5595 * @vsi: VSI to configure 5596 * @vlan_info: packed u16 that contains the VLAN prio and ID 5597 * @tpid: TPID of the port VLAN 5598 * 5599 * Set the port VLAN prio, ID, and TPID. 5600 * 5601 * Enable VLAN pruning so the VSI doesn't receive any traffic that doesn't match 5602 * a VLAN prune rule. The caller should take care to add a VLAN prune rule that 5603 * matches the port VLAN ID and TPID. 5604 * 5605 * Tell hardware to strip outer VLAN tagged packets on receive and don't put 5606 * them in the receive descriptor. VSI(s) in port VLANs should not be aware of 5607 * the port VLAN ID or TPID they are assigned to. 5608 * 5609 * Tell hardware to prevent outer VLAN tag insertion on transmit and only allow 5610 * untagged outer packets from the transmit descriptor. 5611 * 5612 * Also, tell the hardware to insert the port VLAN on transmit. 5613 */ 5614 static int 5615 ice_vsi_set_outer_port_vlan(struct ice_vsi *vsi, u16 vlan_info, u16 tpid) 5616 { 5617 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 5618 struct ice_vsi_ctx ctxt; 5619 int status, err = 0; 5620 u8 tag_type; 5621 5622 if (tpid_to_vsi_outer_vlan_type(tpid, &tag_type)) 5623 return -EINVAL; 5624 5625 memset(&ctxt, 0, sizeof(ctxt)); 5626 5627 ctxt.info = vsi->info; 5628 5629 ctxt.info.sw_flags2 |= ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 5630 5631 ctxt.info.port_based_outer_vlan = rte_cpu_to_le_16(vlan_info); 5632 ctxt.info.outer_vlan_flags = 5633 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW << 5634 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) | 5635 ((tag_type << ICE_AQ_VSI_OUTER_TAG_TYPE_S) & 5636 ICE_AQ_VSI_OUTER_TAG_TYPE_M) | 5637 ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC | 5638 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED << 5639 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) | 5640 ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT; 5641 ctxt.info.valid_sections = 5642 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID | 5643 ICE_AQ_VSI_PROP_SW_VALID); 5644 5645 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 5646 if (status != ICE_SUCCESS) { 5647 PMD_DRV_LOG(ERR, 5648 "update VSI for setting outer port based VLAN failed, err %d", 5649 status); 5650 err = -EINVAL; 5651 } else { 5652 vsi->info.port_based_outer_vlan = ctxt.info.port_based_outer_vlan; 5653 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags; 5654 vsi->info.sw_flags2 = ctxt.info.sw_flags2; 5655 } 5656 5657 return err; 5658 } 5659 5660 /** 5661 * ice_vsi_dis_outer_insertion - disable outer VLAN insertion 5662 * @vsi: VSI to configure 5663 * @info: vlan pvid info 5664 * 5665 * Disable outer VLAN insertion via VSI context. This function should only be 5666 * used if DVM is supported. 5667 * 5668 * Only modify the outer VLAN insertion settings. The VLAN TPID and outer VLAN 5669 * settings are unmodified. 5670 * 5671 * This tells the hardware to not allow VLAN tagged packets in the transmit 5672 * descriptor. This enables software offloaded VLAN insertion and disables 5673 * hardware offloaded VLAN insertion. 5674 */ 5675 static int ice_vsi_dis_outer_insertion(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 5676 { 5677 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 5678 struct ice_vsi_ctx ctxt; 5679 uint8_t vlan_flags = 0; 5680 int status, err = 0; 5681 5682 memset(&ctxt, 0, sizeof(ctxt)); 5683 5684 ctxt.info.valid_sections = 5685 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 5686 ctxt.info.port_based_inner_vlan = 0; 5687 /* clear current outer VLAN insertion settings */ 5688 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags & 5689 ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT | 5690 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M); 5691 if (info->config.reject.tagged == 0) 5692 vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED; 5693 if (info->config.reject.untagged == 0) 5694 vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED; 5695 ctxt.info.outer_vlan_flags |= 5696 ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC | 5697 ((vlan_flags << 5698 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) & 5699 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M); 5700 5701 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 5702 if (!status) { 5703 PMD_DRV_LOG(ERR, 5704 "update VSI for disabling outer VLAN insertion failed, err %d", 5705 status); 5706 err = -EINVAL; 5707 } else { 5708 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags; 5709 vsi->info.port_based_inner_vlan = ctxt.info.port_based_inner_vlan; 5710 } 5711 5712 return err; 5713 } 5714 5715 static int 5716 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 5717 { 5718 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5719 struct ice_vsi *vsi = pf->main_vsi; 5720 struct rte_eth_dev_data *data = pf->dev_data; 5721 struct ice_vsi_vlan_pvid_info info; 5722 int ret; 5723 5724 memset(&info, 0, sizeof(info)); 5725 info.on = on; 5726 if (info.on) { 5727 info.config.pvid = pvid; 5728 } else { 5729 info.config.reject.tagged = 5730 data->dev_conf.txmode.hw_vlan_reject_tagged; 5731 info.config.reject.untagged = 5732 data->dev_conf.txmode.hw_vlan_reject_untagged; 5733 } 5734 5735 if (ice_is_dvm_ena(&vsi->adapter->hw)) { 5736 if (on) 5737 return ice_vsi_set_outer_port_vlan(vsi, pvid, pf->outer_ethertype); 5738 else 5739 return ice_vsi_dis_outer_insertion(vsi, &info); 5740 } 5741 5742 ret = ice_vsi_vlan_pvid_set(vsi, &info); 5743 if (ret < 0) { 5744 PMD_DRV_LOG(ERR, "Failed to set pvid."); 5745 return -EINVAL; 5746 } 5747 5748 return 0; 5749 } 5750 5751 static int ice_vsi_ena_outer_insertion(struct ice_vsi *vsi, uint16_t tpid) 5752 { 5753 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 5754 struct ice_vsi_ctx ctxt; 5755 int status, err = 0; 5756 u8 tag_type; 5757 /* do not allow modifying VLAN stripping when a port VLAN is configured 5758 * on this VSI 5759 */ 5760 if (vsi->info.port_based_outer_vlan) 5761 return 0; 5762 5763 if (tpid_to_vsi_outer_vlan_type(tpid, &tag_type)) 5764 return -EINVAL; 5765 5766 memset(&ctxt, 0, sizeof(ctxt)); 5767 ctxt.info.valid_sections = 5768 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 5769 /* clear current outer VLAN insertion settings */ 5770 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags & 5771 ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT | 5772 ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC | 5773 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M | 5774 ICE_AQ_VSI_OUTER_TAG_TYPE_M); 5775 ctxt.info.outer_vlan_flags |= 5776 ((ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL << 5777 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) & 5778 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M) | 5779 ((tag_type << ICE_AQ_VSI_OUTER_TAG_TYPE_S) & 5780 ICE_AQ_VSI_OUTER_TAG_TYPE_M); 5781 5782 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 5783 if (status) { 5784 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping"); 5785 err = -EIO; 5786 } else { 5787 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags; 5788 } 5789 5790 return err; 5791 } 5792 5793 static int 5794 ice_vlan_tpid_set(struct rte_eth_dev *dev, 5795 enum rte_vlan_type vlan_type, 5796 uint16_t tpid) 5797 { 5798 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5799 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5800 struct ice_vsi *vsi = pf->main_vsi; 5801 uint64_t qinq = dev->data->dev_conf.rxmode.offloads & 5802 RTE_ETH_RX_OFFLOAD_QINQ_STRIP; 5803 int err = 0; 5804 5805 if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER && 5806 vlan_type != RTE_ETH_VLAN_TYPE_OUTER) || 5807 (!qinq && vlan_type == RTE_ETH_VLAN_TYPE_INNER) || 5808 !ice_is_supported_port_vlan_proto(hw, tpid)) { 5809 PMD_DRV_LOG(ERR, 5810 "Unsupported vlan type."); 5811 return -EINVAL; 5812 } 5813 5814 err = ice_vsi_ena_outer_insertion(vsi, tpid); 5815 if (!err) 5816 pf->outer_ethertype = tpid; 5817 5818 return err; 5819 } 5820 5821 static int 5822 ice_get_eeprom_length(struct rte_eth_dev *dev) 5823 { 5824 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5825 5826 return hw->flash.flash_size; 5827 } 5828 5829 static int 5830 ice_get_eeprom(struct rte_eth_dev *dev, 5831 struct rte_dev_eeprom_info *eeprom) 5832 { 5833 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5834 uint8_t *data = eeprom->data; 5835 int status; 5836 5837 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 5838 5839 status = ice_acquire_nvm(hw, ICE_RES_READ); 5840 if (status) { 5841 PMD_DRV_LOG(ERR, "acquire nvm failed."); 5842 return -EIO; 5843 } 5844 5845 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length, 5846 data, false); 5847 5848 ice_release_nvm(hw); 5849 5850 if (status) { 5851 PMD_DRV_LOG(ERR, "EEPROM read failed."); 5852 return -EIO; 5853 } 5854 5855 return 0; 5856 } 5857 5858 static int 5859 ice_get_module_info(struct rte_eth_dev *dev, 5860 struct rte_eth_dev_module_info *modinfo) 5861 { 5862 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5863 u8 sff8472_comp = 0; 5864 u8 sff8472_swap = 0; 5865 u8 sff8636_rev = 0; 5866 u8 value = 0; 5867 int status; 5868 5869 status = ice_aq_sff_eeprom(hw, 0, ICE_I2C_EEPROM_DEV_ADDR, 0x00, 0x00, 5870 0, &value, 1, 0, NULL); 5871 if (status) 5872 return -EIO; 5873 5874 switch (value) { 5875 case ICE_MODULE_TYPE_SFP: 5876 status = ice_aq_sff_eeprom(hw, 0, ICE_I2C_EEPROM_DEV_ADDR, 5877 ICE_MODULE_SFF_8472_COMP, 0x00, 0, 5878 &sff8472_comp, 1, 0, NULL); 5879 if (status) 5880 return -EIO; 5881 status = ice_aq_sff_eeprom(hw, 0, ICE_I2C_EEPROM_DEV_ADDR, 5882 ICE_MODULE_SFF_8472_SWAP, 0x00, 0, 5883 &sff8472_swap, 1, 0, NULL); 5884 if (status) 5885 return -EIO; 5886 5887 if (sff8472_swap & ICE_MODULE_SFF_ADDR_MODE) { 5888 modinfo->type = ICE_MODULE_SFF_8079; 5889 modinfo->eeprom_len = ICE_MODULE_SFF_8079_LEN; 5890 } else if (sff8472_comp && 5891 (sff8472_swap & ICE_MODULE_SFF_DIAG_CAPAB)) { 5892 modinfo->type = ICE_MODULE_SFF_8472; 5893 modinfo->eeprom_len = ICE_MODULE_SFF_8472_LEN; 5894 } else { 5895 modinfo->type = ICE_MODULE_SFF_8079; 5896 modinfo->eeprom_len = ICE_MODULE_SFF_8079_LEN; 5897 } 5898 break; 5899 case ICE_MODULE_TYPE_QSFP_PLUS: 5900 case ICE_MODULE_TYPE_QSFP28: 5901 status = ice_aq_sff_eeprom(hw, 0, ICE_I2C_EEPROM_DEV_ADDR, 5902 ICE_MODULE_REVISION_ADDR, 0x00, 0, 5903 &sff8636_rev, 1, 0, NULL); 5904 if (status) 5905 return -EIO; 5906 /* Check revision compliance */ 5907 if (sff8636_rev > 0x02) { 5908 /* Module is SFF-8636 compliant */ 5909 modinfo->type = ICE_MODULE_SFF_8636; 5910 modinfo->eeprom_len = ICE_MODULE_QSFP_MAX_LEN; 5911 } else { 5912 modinfo->type = ICE_MODULE_SFF_8436; 5913 modinfo->eeprom_len = ICE_MODULE_QSFP_MAX_LEN; 5914 } 5915 break; 5916 default: 5917 PMD_DRV_LOG(WARNING, "SFF Module Type not recognized."); 5918 return -EINVAL; 5919 } 5920 return 0; 5921 } 5922 5923 static int 5924 ice_get_module_eeprom(struct rte_eth_dev *dev, 5925 struct rte_dev_eeprom_info *info) 5926 { 5927 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5928 #define SFF_READ_BLOCK_SIZE 8 5929 #define I2C_BUSY_TRY_TIMES 4 5930 #define I2C_USLEEP_MIN_TIME 1500 5931 #define I2C_USLEEP_MAX_TIME 2500 5932 uint8_t value[SFF_READ_BLOCK_SIZE] = {0}; 5933 uint8_t addr = ICE_I2C_EEPROM_DEV_ADDR; 5934 uint8_t *data = NULL; 5935 bool is_sfp = false; 5936 uint32_t i, j; 5937 uint32_t offset = 0; 5938 uint8_t page = 0; 5939 int status; 5940 5941 if (!info || !info->length || !info->data) 5942 return -EINVAL; 5943 5944 status = ice_aq_sff_eeprom(hw, 0, addr, offset, page, 0, value, 1, 0, 5945 NULL); 5946 if (status) 5947 return -EIO; 5948 5949 if (value[0] == ICE_MODULE_TYPE_SFP) 5950 is_sfp = true; 5951 5952 data = info->data; 5953 memset(data, 0, info->length); 5954 for (i = 0; i < info->length; i += SFF_READ_BLOCK_SIZE) { 5955 offset = i + info->offset; 5956 page = 0; 5957 5958 /* Check if we need to access the other memory page */ 5959 if (is_sfp) { 5960 if (offset >= ICE_MODULE_SFF_8079_LEN) { 5961 offset -= ICE_MODULE_SFF_8079_LEN; 5962 addr = ICE_I2C_EEPROM_DEV_ADDR2; 5963 } 5964 } else { 5965 while (offset >= ICE_MODULE_SFF_8436_LEN) { 5966 /* Compute memory page number and offset. */ 5967 offset -= ICE_MODULE_SFF_8436_LEN / 2; 5968 page++; 5969 } 5970 } 5971 5972 /* Bit 2 of eeprom address 0x02 declares upper 5973 * pages are disabled on QSFP modules. 5974 * SFP modules only ever use page 0. 5975 */ 5976 if (page == 0 || !(data[0x2] & 0x4)) { 5977 /* If i2c bus is busy due to slow page change or 5978 * link management access, call can fail. 5979 * This is normal. So we retry this a few times. 5980 */ 5981 for (j = 0; j < I2C_BUSY_TRY_TIMES; j++) { 5982 status = ice_aq_sff_eeprom(hw, 0, addr, offset, 5983 page, !is_sfp, value, 5984 SFF_READ_BLOCK_SIZE, 5985 0, NULL); 5986 PMD_DRV_LOG(DEBUG, "SFF %02X %02X %02X %X = " 5987 "%02X%02X%02X%02X." 5988 "%02X%02X%02X%02X (%X)", 5989 addr, offset, page, is_sfp, 5990 value[0], value[1], 5991 value[2], value[3], 5992 value[4], value[5], 5993 value[6], value[7], 5994 status); 5995 if (status) { 5996 usleep_range(I2C_USLEEP_MIN_TIME, 5997 I2C_USLEEP_MAX_TIME); 5998 memset(value, 0, SFF_READ_BLOCK_SIZE); 5999 continue; 6000 } 6001 break; 6002 } 6003 6004 /* Make sure we have enough room for the new block */ 6005 if ((i + SFF_READ_BLOCK_SIZE) <= info->length) 6006 memcpy(data + i, value, SFF_READ_BLOCK_SIZE); 6007 } 6008 } 6009 6010 return 0; 6011 } 6012 6013 static void 6014 ice_stat_update_32(struct ice_hw *hw, 6015 uint32_t reg, 6016 bool offset_loaded, 6017 uint64_t *offset, 6018 uint64_t *stat) 6019 { 6020 uint64_t new_data; 6021 6022 new_data = (uint64_t)ICE_READ_REG(hw, reg); 6023 if (!offset_loaded) 6024 *offset = new_data; 6025 6026 if (new_data >= *offset) 6027 *stat = (uint64_t)(new_data - *offset); 6028 else 6029 *stat = (uint64_t)((new_data + 6030 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 6031 - *offset); 6032 } 6033 6034 static void 6035 ice_stat_update_40(struct ice_hw *hw, 6036 uint32_t hireg, 6037 uint32_t loreg, 6038 bool offset_loaded, 6039 uint64_t *offset, 6040 uint64_t *stat) 6041 { 6042 uint64_t new_data; 6043 6044 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 6045 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 6046 ICE_32_BIT_WIDTH; 6047 6048 if (!offset_loaded) 6049 *offset = new_data; 6050 6051 if (new_data >= *offset) 6052 *stat = new_data - *offset; 6053 else 6054 *stat = (uint64_t)((new_data + 6055 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 6056 *offset); 6057 6058 *stat &= ICE_40_BIT_MASK; 6059 } 6060 6061 /* Get all the statistics of a VSI */ 6062 static void 6063 ice_update_vsi_stats(struct ice_vsi *vsi) 6064 { 6065 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 6066 struct ice_eth_stats *nes = &vsi->eth_stats; 6067 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 6068 int idx = rte_le_to_cpu_16(vsi->vsi_id); 6069 6070 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 6071 vsi->offset_loaded, &oes->rx_bytes, 6072 &nes->rx_bytes); 6073 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 6074 vsi->offset_loaded, &oes->rx_unicast, 6075 &nes->rx_unicast); 6076 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 6077 vsi->offset_loaded, &oes->rx_multicast, 6078 &nes->rx_multicast); 6079 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 6080 vsi->offset_loaded, &oes->rx_broadcast, 6081 &nes->rx_broadcast); 6082 /* enlarge the limitation when rx_bytes overflowed */ 6083 if (vsi->offset_loaded) { 6084 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes) 6085 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 6086 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes); 6087 } 6088 vsi->old_rx_bytes = nes->rx_bytes; 6089 /* exclude CRC bytes */ 6090 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 6091 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 6092 6093 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 6094 &oes->rx_discards, &nes->rx_discards); 6095 /* GLV_REPC not supported */ 6096 /* GLV_RMPC not supported */ 6097 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 6098 &oes->rx_unknown_protocol, 6099 &nes->rx_unknown_protocol); 6100 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 6101 vsi->offset_loaded, &oes->tx_bytes, 6102 &nes->tx_bytes); 6103 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 6104 vsi->offset_loaded, &oes->tx_unicast, 6105 &nes->tx_unicast); 6106 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 6107 vsi->offset_loaded, &oes->tx_multicast, 6108 &nes->tx_multicast); 6109 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 6110 vsi->offset_loaded, &oes->tx_broadcast, 6111 &nes->tx_broadcast); 6112 /* GLV_TDPC not supported */ 6113 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 6114 &oes->tx_errors, &nes->tx_errors); 6115 /* enlarge the limitation when tx_bytes overflowed */ 6116 if (vsi->offset_loaded) { 6117 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes) 6118 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 6119 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes); 6120 } 6121 vsi->old_tx_bytes = nes->tx_bytes; 6122 vsi->offset_loaded = true; 6123 6124 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 6125 vsi->vsi_id); 6126 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 6127 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 6128 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 6129 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 6130 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 6131 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 6132 nes->rx_unknown_protocol); 6133 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 6134 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 6135 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 6136 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 6137 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 6138 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 6139 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 6140 vsi->vsi_id); 6141 } 6142 6143 static void 6144 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 6145 { 6146 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 6147 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 6148 6149 /* Get statistics of struct ice_eth_stats */ 6150 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 6151 GLPRT_GORCL(hw->port_info->lport), 6152 pf->offset_loaded, &os->eth.rx_bytes, 6153 &ns->eth.rx_bytes); 6154 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 6155 GLPRT_UPRCL(hw->port_info->lport), 6156 pf->offset_loaded, &os->eth.rx_unicast, 6157 &ns->eth.rx_unicast); 6158 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 6159 GLPRT_MPRCL(hw->port_info->lport), 6160 pf->offset_loaded, &os->eth.rx_multicast, 6161 &ns->eth.rx_multicast); 6162 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 6163 GLPRT_BPRCL(hw->port_info->lport), 6164 pf->offset_loaded, &os->eth.rx_broadcast, 6165 &ns->eth.rx_broadcast); 6166 ice_stat_update_32(hw, PRTRPB_RDPC, 6167 pf->offset_loaded, &os->eth.rx_discards, 6168 &ns->eth.rx_discards); 6169 /* enlarge the limitation when rx_bytes overflowed */ 6170 if (pf->offset_loaded) { 6171 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes) 6172 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 6173 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes); 6174 } 6175 pf->old_rx_bytes = ns->eth.rx_bytes; 6176 6177 /* Workaround: CRC size should not be included in byte statistics, 6178 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 6179 * packet. 6180 */ 6181 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 6182 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 6183 6184 /* GLPRT_REPC not supported */ 6185 /* GLPRT_RMPC not supported */ 6186 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 6187 pf->offset_loaded, 6188 &os->eth.rx_unknown_protocol, 6189 &ns->eth.rx_unknown_protocol); 6190 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 6191 GLPRT_GOTCL(hw->port_info->lport), 6192 pf->offset_loaded, &os->eth.tx_bytes, 6193 &ns->eth.tx_bytes); 6194 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 6195 GLPRT_UPTCL(hw->port_info->lport), 6196 pf->offset_loaded, &os->eth.tx_unicast, 6197 &ns->eth.tx_unicast); 6198 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 6199 GLPRT_MPTCL(hw->port_info->lport), 6200 pf->offset_loaded, &os->eth.tx_multicast, 6201 &ns->eth.tx_multicast); 6202 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 6203 GLPRT_BPTCL(hw->port_info->lport), 6204 pf->offset_loaded, &os->eth.tx_broadcast, 6205 &ns->eth.tx_broadcast); 6206 /* enlarge the limitation when tx_bytes overflowed */ 6207 if (pf->offset_loaded) { 6208 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes) 6209 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 6210 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes); 6211 } 6212 pf->old_tx_bytes = ns->eth.tx_bytes; 6213 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 6214 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 6215 6216 /* GLPRT_TEPC not supported */ 6217 6218 /* additional port specific stats */ 6219 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 6220 pf->offset_loaded, &os->tx_dropped_link_down, 6221 &ns->tx_dropped_link_down); 6222 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 6223 pf->offset_loaded, &os->crc_errors, 6224 &ns->crc_errors); 6225 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 6226 pf->offset_loaded, &os->illegal_bytes, 6227 &ns->illegal_bytes); 6228 /* GLPRT_ERRBC not supported */ 6229 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 6230 pf->offset_loaded, &os->mac_local_faults, 6231 &ns->mac_local_faults); 6232 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 6233 pf->offset_loaded, &os->mac_remote_faults, 6234 &ns->mac_remote_faults); 6235 6236 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 6237 pf->offset_loaded, &os->rx_len_errors, 6238 &ns->rx_len_errors); 6239 6240 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 6241 pf->offset_loaded, &os->link_xon_rx, 6242 &ns->link_xon_rx); 6243 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 6244 pf->offset_loaded, &os->link_xoff_rx, 6245 &ns->link_xoff_rx); 6246 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 6247 pf->offset_loaded, &os->link_xon_tx, 6248 &ns->link_xon_tx); 6249 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 6250 pf->offset_loaded, &os->link_xoff_tx, 6251 &ns->link_xoff_tx); 6252 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 6253 GLPRT_PRC64L(hw->port_info->lport), 6254 pf->offset_loaded, &os->rx_size_64, 6255 &ns->rx_size_64); 6256 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 6257 GLPRT_PRC127L(hw->port_info->lport), 6258 pf->offset_loaded, &os->rx_size_127, 6259 &ns->rx_size_127); 6260 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 6261 GLPRT_PRC255L(hw->port_info->lport), 6262 pf->offset_loaded, &os->rx_size_255, 6263 &ns->rx_size_255); 6264 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 6265 GLPRT_PRC511L(hw->port_info->lport), 6266 pf->offset_loaded, &os->rx_size_511, 6267 &ns->rx_size_511); 6268 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 6269 GLPRT_PRC1023L(hw->port_info->lport), 6270 pf->offset_loaded, &os->rx_size_1023, 6271 &ns->rx_size_1023); 6272 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 6273 GLPRT_PRC1522L(hw->port_info->lport), 6274 pf->offset_loaded, &os->rx_size_1522, 6275 &ns->rx_size_1522); 6276 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 6277 GLPRT_PRC9522L(hw->port_info->lport), 6278 pf->offset_loaded, &os->rx_size_big, 6279 &ns->rx_size_big); 6280 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 6281 pf->offset_loaded, &os->rx_undersize, 6282 &ns->rx_undersize); 6283 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 6284 pf->offset_loaded, &os->rx_fragments, 6285 &ns->rx_fragments); 6286 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 6287 pf->offset_loaded, &os->rx_oversize, 6288 &ns->rx_oversize); 6289 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 6290 pf->offset_loaded, &os->rx_jabber, 6291 &ns->rx_jabber); 6292 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 6293 GLPRT_PTC64L(hw->port_info->lport), 6294 pf->offset_loaded, &os->tx_size_64, 6295 &ns->tx_size_64); 6296 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 6297 GLPRT_PTC127L(hw->port_info->lport), 6298 pf->offset_loaded, &os->tx_size_127, 6299 &ns->tx_size_127); 6300 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 6301 GLPRT_PTC255L(hw->port_info->lport), 6302 pf->offset_loaded, &os->tx_size_255, 6303 &ns->tx_size_255); 6304 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 6305 GLPRT_PTC511L(hw->port_info->lport), 6306 pf->offset_loaded, &os->tx_size_511, 6307 &ns->tx_size_511); 6308 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 6309 GLPRT_PTC1023L(hw->port_info->lport), 6310 pf->offset_loaded, &os->tx_size_1023, 6311 &ns->tx_size_1023); 6312 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 6313 GLPRT_PTC1522L(hw->port_info->lport), 6314 pf->offset_loaded, &os->tx_size_1522, 6315 &ns->tx_size_1522); 6316 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 6317 GLPRT_PTC9522L(hw->port_info->lport), 6318 pf->offset_loaded, &os->tx_size_big, 6319 &ns->tx_size_big); 6320 6321 /* GLPRT_MSPDC not supported */ 6322 /* GLPRT_XEC not supported */ 6323 6324 pf->offset_loaded = true; 6325 6326 if (pf->main_vsi) 6327 ice_update_vsi_stats(pf->main_vsi); 6328 } 6329 6330 /* Get all statistics of a port */ 6331 static int 6332 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 6333 { 6334 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6335 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6336 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 6337 6338 /* call read registers - updates values, now write them to struct */ 6339 ice_read_stats_registers(pf, hw); 6340 6341 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 6342 pf->main_vsi->eth_stats.rx_multicast + 6343 pf->main_vsi->eth_stats.rx_broadcast - 6344 pf->main_vsi->eth_stats.rx_discards; 6345 stats->opackets = ns->eth.tx_unicast + 6346 ns->eth.tx_multicast + 6347 ns->eth.tx_broadcast; 6348 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 6349 stats->obytes = ns->eth.tx_bytes; 6350 stats->oerrors = ns->eth.tx_errors + 6351 pf->main_vsi->eth_stats.tx_errors; 6352 6353 /* Rx Errors */ 6354 stats->imissed = ns->eth.rx_discards + 6355 pf->main_vsi->eth_stats.rx_discards; 6356 stats->ierrors = ns->crc_errors + 6357 ns->rx_undersize + 6358 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 6359 6360 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 6361 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 6362 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 6363 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 6364 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 6365 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 6366 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 6367 pf->main_vsi->eth_stats.rx_discards); 6368 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 6369 ns->eth.rx_unknown_protocol); 6370 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 6371 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 6372 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 6373 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 6374 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 6375 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 6376 pf->main_vsi->eth_stats.tx_discards); 6377 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 6378 6379 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 6380 ns->tx_dropped_link_down); 6381 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 6382 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 6383 ns->illegal_bytes); 6384 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 6385 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 6386 ns->mac_local_faults); 6387 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 6388 ns->mac_remote_faults); 6389 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 6390 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 6391 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 6392 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 6393 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 6394 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 6395 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 6396 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 6397 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 6398 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 6399 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 6400 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 6401 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 6402 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 6403 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 6404 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 6405 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 6406 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 6407 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 6408 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 6409 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 6410 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 6411 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 6412 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 6413 return 0; 6414 } 6415 6416 /* Reset the statistics */ 6417 static int 6418 ice_stats_reset(struct rte_eth_dev *dev) 6419 { 6420 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6421 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6422 6423 /* Mark PF and VSI stats to update the offset, aka "reset" */ 6424 pf->offset_loaded = false; 6425 if (pf->main_vsi) 6426 pf->main_vsi->offset_loaded = false; 6427 6428 /* read the stats, reading current register values into offset */ 6429 ice_read_stats_registers(pf, hw); 6430 6431 memset(&pf->mbuf_stats, 0, sizeof(struct ice_mbuf_stats)); 6432 6433 return 0; 6434 } 6435 6436 static uint32_t 6437 ice_xstats_calc_num(void) 6438 { 6439 uint32_t num; 6440 6441 num = ICE_NB_ETH_XSTATS + ICE_NB_MBUF_XSTATS + ICE_NB_HW_PORT_XSTATS; 6442 6443 return num; 6444 } 6445 6446 static void 6447 ice_update_mbuf_stats(struct rte_eth_dev *ethdev, 6448 struct ice_mbuf_stats *mbuf_stats) 6449 { 6450 uint16_t idx; 6451 struct ci_tx_queue *txq; 6452 6453 for (idx = 0; idx < ethdev->data->nb_tx_queues; idx++) { 6454 txq = ethdev->data->tx_queues[idx]; 6455 mbuf_stats->tx_pkt_errors += txq->mbuf_errors; 6456 } 6457 } 6458 6459 static int 6460 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 6461 unsigned int n) 6462 { 6463 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6464 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6465 struct ice_adapter *adapter = 6466 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 6467 struct ice_mbuf_stats mbuf_stats = {0}; 6468 unsigned int i; 6469 unsigned int count; 6470 struct ice_hw_port_stats *hw_stats = &pf->stats; 6471 6472 count = ice_xstats_calc_num(); 6473 if (n < count) 6474 return count; 6475 6476 ice_read_stats_registers(pf, hw); 6477 6478 if (!xstats) 6479 return 0; 6480 6481 count = 0; 6482 6483 if (adapter->devargs.mbuf_check) 6484 ice_update_mbuf_stats(dev, &mbuf_stats); 6485 6486 /* Get stats from ice_eth_stats struct */ 6487 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 6488 xstats[count].value = 6489 *(uint64_t *)((char *)&hw_stats->eth + 6490 ice_stats_strings[i].offset); 6491 xstats[count].id = count; 6492 count++; 6493 } 6494 6495 /* Get stats from ice_mbuf_stats struct */ 6496 for (i = 0; i < ICE_NB_MBUF_XSTATS; i++) { 6497 xstats[count].value = 6498 *(uint64_t *)((char *)&mbuf_stats + ice_mbuf_strings[i].offset); 6499 xstats[count].id = count; 6500 count++; 6501 } 6502 6503 /* Get individual stats from ice_hw_port struct */ 6504 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 6505 xstats[count].value = 6506 *(uint64_t *)((char *)hw_stats + 6507 ice_hw_port_strings[i].offset); 6508 xstats[count].id = count; 6509 count++; 6510 } 6511 6512 return count; 6513 } 6514 6515 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 6516 struct rte_eth_xstat_name *xstats_names, 6517 __rte_unused unsigned int limit) 6518 { 6519 unsigned int count = 0; 6520 unsigned int i; 6521 6522 if (!xstats_names) 6523 return ice_xstats_calc_num(); 6524 6525 /* Note: limit checked in rte_eth_xstats_names() */ 6526 6527 /* Get stats from ice_eth_stats struct */ 6528 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 6529 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 6530 sizeof(xstats_names[count].name)); 6531 count++; 6532 } 6533 6534 /* Get stats from ice_mbuf_stats struct */ 6535 for (i = 0; i < ICE_NB_MBUF_XSTATS; i++) { 6536 strlcpy(xstats_names[count].name, ice_mbuf_strings[i].name, 6537 sizeof(xstats_names[count].name)); 6538 count++; 6539 } 6540 6541 /* Get individual stats from ice_hw_port struct */ 6542 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 6543 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 6544 sizeof(xstats_names[count].name)); 6545 count++; 6546 } 6547 6548 return count; 6549 } 6550 6551 static int 6552 ice_dev_flow_ops_get(struct rte_eth_dev *dev, 6553 const struct rte_flow_ops **ops) 6554 { 6555 if (!dev) 6556 return -EINVAL; 6557 6558 *ops = &ice_flow_ops; 6559 return 0; 6560 } 6561 6562 /* Add UDP tunneling port */ 6563 static int 6564 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 6565 struct rte_eth_udp_tunnel *udp_tunnel) 6566 { 6567 int ret = 0; 6568 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6569 struct ice_adapter *ad = 6570 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 6571 6572 if (udp_tunnel == NULL) 6573 return -EINVAL; 6574 6575 switch (udp_tunnel->prot_type) { 6576 case RTE_ETH_TUNNEL_TYPE_VXLAN: 6577 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); 6578 if (!ret && ad->psr != NULL) 6579 ice_parser_vxlan_tunnel_set(ad->psr, 6580 udp_tunnel->udp_port, true); 6581 break; 6582 default: 6583 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 6584 ret = -EINVAL; 6585 break; 6586 } 6587 6588 return ret; 6589 } 6590 6591 /* Delete UDP tunneling port */ 6592 static int 6593 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 6594 struct rte_eth_udp_tunnel *udp_tunnel) 6595 { 6596 int ret = 0; 6597 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6598 struct ice_adapter *ad = 6599 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 6600 6601 if (udp_tunnel == NULL) 6602 return -EINVAL; 6603 6604 switch (udp_tunnel->prot_type) { 6605 case RTE_ETH_TUNNEL_TYPE_VXLAN: 6606 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); 6607 if (!ret && ad->psr != NULL) 6608 ice_parser_vxlan_tunnel_set(ad->psr, 6609 udp_tunnel->udp_port, false); 6610 break; 6611 default: 6612 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 6613 ret = -EINVAL; 6614 break; 6615 } 6616 6617 return ret; 6618 } 6619 6620 /** 6621 * ice_ptp_write_init - Set PHC time to provided value 6622 * @hw: Hardware private structure 6623 * 6624 * Set the PHC time to CLOCK_REALTIME 6625 */ 6626 static int ice_ptp_write_init(struct ice_hw *hw) 6627 { 6628 uint64_t ns; 6629 struct timespec sys_time; 6630 clock_gettime(CLOCK_REALTIME, &sys_time); 6631 ns = rte_timespec_to_ns(&sys_time); 6632 6633 return ice_ptp_init_time(hw, ns, true); 6634 } 6635 6636 static int 6637 ice_timesync_enable(struct rte_eth_dev *dev) 6638 { 6639 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6640 struct ice_adapter *ad = 6641 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 6642 int ret; 6643 6644 if (dev->data->dev_started && !(dev->data->dev_conf.rxmode.offloads & 6645 RTE_ETH_RX_OFFLOAD_TIMESTAMP)) { 6646 PMD_DRV_LOG(ERR, "Rx timestamp offload not configured"); 6647 return -1; 6648 } 6649 6650 if (hw->func_caps.ts_func_info.src_tmr_owned) { 6651 ret = ice_ptp_init_phc(hw); 6652 if (ret) { 6653 PMD_DRV_LOG(ERR, "Failed to initialize PHC"); 6654 return -1; 6655 } 6656 6657 ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810, true); 6658 if (ret) { 6659 PMD_DRV_LOG(ERR, 6660 "Failed to write PHC increment time value"); 6661 return -1; 6662 } 6663 } 6664 6665 if (!ice_ptp_lock(hw)) { 6666 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore"); 6667 return ICE_ERR_NOT_READY; 6668 } 6669 6670 ret = ice_ptp_write_init(hw); 6671 ice_ptp_unlock(hw); 6672 if (ret) 6673 PMD_INIT_LOG(ERR, "Failed to set current system time to PHC timer"); 6674 6675 ad->ptp_ena = 1; 6676 6677 return 0; 6678 } 6679 6680 static int 6681 ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 6682 struct timespec *timestamp, uint32_t flags) 6683 { 6684 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6685 struct ice_adapter *ad = 6686 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 6687 struct ice_rx_queue *rxq; 6688 uint32_t ts_high; 6689 uint64_t ts_ns; 6690 6691 rxq = dev->data->rx_queues[flags]; 6692 6693 ts_high = rxq->time_high; 6694 ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, ts_high); 6695 *timestamp = rte_ns_to_timespec(ts_ns); 6696 6697 return 0; 6698 } 6699 6700 static int 6701 ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 6702 struct timespec *timestamp) 6703 { 6704 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6705 struct ice_adapter *ad = 6706 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 6707 uint64_t ts_ns, tstamp, tstamp_ready = 0; 6708 uint64_t end_time; 6709 const uint64_t mask = 0xFFFFFFFF; 6710 int ret; 6711 6712 /* Set the end time with a delay of 10 microseconds */ 6713 end_time = rte_get_timer_cycles() + (rte_get_timer_hz() / 100000); 6714 6715 do { 6716 ret = ice_get_phy_tx_tstamp_ready(hw, ad->ptp_tx_block, &tstamp_ready); 6717 if (ret) { 6718 PMD_DRV_LOG(ERR, "Failed to get phy ready for timestamp"); 6719 return -1; 6720 } 6721 6722 if ((tstamp_ready & BIT_ULL(0)) == 0 && rte_get_timer_cycles() > end_time) { 6723 PMD_DRV_LOG(ERR, "Timeout to get phy ready for timestamp"); 6724 return -1; 6725 } 6726 } while ((tstamp_ready & BIT_ULL(0)) == 0); 6727 6728 ret = ice_read_phy_tstamp(hw, ad->ptp_tx_block, ad->ptp_tx_index, &tstamp); 6729 if (ret || tstamp == 0) { 6730 PMD_DRV_LOG(ERR, "Failed to read phy timestamp"); 6731 return -1; 6732 } 6733 6734 ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, (tstamp >> 8) & mask); 6735 *timestamp = rte_ns_to_timespec(ts_ns); 6736 6737 return 0; 6738 } 6739 6740 static int 6741 ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 6742 { 6743 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6744 uint8_t tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; 6745 uint32_t lo, lo2, hi; 6746 uint64_t time, ns; 6747 int ret; 6748 6749 if (delta > INT32_MAX || delta < INT32_MIN) { 6750 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 6751 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); 6752 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 6753 6754 if (lo2 < lo) { 6755 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 6756 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); 6757 } 6758 6759 time = ((uint64_t)hi << 32) | lo; 6760 ns = time + delta; 6761 6762 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(ns)); 6763 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(ns)); 6764 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 6765 6766 ret = ice_ptp_init_time(hw, ns, true); 6767 if (ret) { 6768 PMD_DRV_LOG(ERR, "PTP init time failed, err %d", ret); 6769 return -1; 6770 } 6771 return 0; 6772 } 6773 6774 ret = ice_ptp_adj_clock(hw, delta, true); 6775 if (ret) { 6776 PMD_DRV_LOG(ERR, "PTP adj clock failed, err %d", ret); 6777 return -1; 6778 } 6779 6780 return 0; 6781 } 6782 6783 static int 6784 ice_timesync_adjust_freq(struct rte_eth_dev *dev, int64_t ppm) 6785 { 6786 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6787 int64_t incval, diff = 0; 6788 bool negative = false; 6789 uint64_t div, rem; 6790 uint64_t divisor = 1000000ULL << 16; 6791 int shift; 6792 int ret; 6793 6794 incval = ice_get_base_incval(hw, ICE_SRC_TMR_MODE_NANOSECONDS); 6795 6796 if (ppm < 0) { 6797 negative = true; 6798 ppm = -ppm; 6799 } 6800 6801 /* can incval * ppm overflow ? */ 6802 if (log2(incval) + log2(ppm) > 62) { 6803 rem = ppm % divisor; 6804 div = ppm / divisor; 6805 diff = div * incval; 6806 ppm = rem; 6807 6808 shift = log2(incval) + log2(ppm) - 62; 6809 if (shift > 0) { 6810 /* drop precision */ 6811 ppm >>= shift; 6812 divisor >>= shift; 6813 } 6814 } 6815 6816 if (divisor) 6817 diff = diff + incval * ppm / divisor; 6818 6819 if (negative) 6820 incval -= diff; 6821 else 6822 incval += diff; 6823 6824 ret = ice_ptp_write_incval_locked(hw, incval, true); 6825 if (ret) { 6826 PMD_DRV_LOG(ERR, "PTP failed to set incval, err %d", ret); 6827 return -1; 6828 } 6829 return 0; 6830 } 6831 6832 static int 6833 ice_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 6834 { 6835 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6836 uint64_t ns; 6837 int ret; 6838 6839 ns = rte_timespec_to_ns(ts); 6840 ret = ice_ptp_init_time(hw, ns, true); 6841 if (ret) { 6842 PMD_DRV_LOG(ERR, "PTP init time failed, err %d", ret); 6843 return -1; 6844 } 6845 6846 return 0; 6847 } 6848 6849 static int 6850 ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 6851 { 6852 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6853 uint8_t tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; 6854 uint32_t hi, lo, lo2; 6855 uint64_t time; 6856 6857 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 6858 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); 6859 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 6860 6861 if (lo2 < lo) { 6862 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); 6863 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); 6864 } 6865 6866 time = ((uint64_t)hi << 32) | lo; 6867 *ts = rte_ns_to_timespec(time); 6868 6869 return 0; 6870 } 6871 6872 static int 6873 ice_timesync_disable(struct rte_eth_dev *dev) 6874 { 6875 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6876 struct ice_adapter *ad = 6877 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 6878 uint8_t tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; 6879 uint64_t val; 6880 uint8_t lport; 6881 6882 lport = hw->port_info->lport; 6883 6884 ice_clear_phy_tstamp(hw, lport, 0); 6885 6886 val = ICE_READ_REG(hw, GLTSYN_ENA(tmr_idx)); 6887 val &= ~GLTSYN_ENA_TSYN_ENA_M; 6888 ICE_WRITE_REG(hw, GLTSYN_ENA(tmr_idx), val); 6889 6890 ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(tmr_idx), 0); 6891 ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(tmr_idx), 0); 6892 6893 ad->ptp_ena = 0; 6894 6895 return 0; 6896 } 6897 6898 static const uint32_t * 6899 ice_buffer_split_supported_hdr_ptypes_get(struct rte_eth_dev *dev __rte_unused, 6900 size_t *no_of_elements) 6901 { 6902 /* Buffer split protocol header capability. */ 6903 static const uint32_t ptypes[] = { 6904 /* Non tunneled */ 6905 RTE_PTYPE_L2_ETHER, 6906 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 6907 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP, 6908 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP, 6909 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_SCTP, 6910 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 6911 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP, 6912 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP, 6913 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_SCTP, 6914 6915 /* Tunneled */ 6916 RTE_PTYPE_TUNNEL_GRENAT, 6917 6918 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER, 6919 6920 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 6921 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 6922 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 6923 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 6924 6925 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 6926 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_UDP, 6927 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 6928 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_TCP, 6929 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 6930 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_SCTP, 6931 6932 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 6933 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_UDP, 6934 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 6935 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_TCP, 6936 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 6937 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_SCTP, 6938 6939 }; 6940 6941 *no_of_elements = RTE_DIM(ptypes); 6942 return ptypes; 6943 } 6944 6945 static unsigned int 6946 ice_fec_get_capa_num(struct ice_aqc_get_phy_caps_data *pcaps, 6947 struct rte_eth_fec_capa *speed_fec_capa) 6948 { 6949 unsigned int num = 0; 6950 int auto_fec = (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC) ? 6951 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) : 0; 6952 int link_nofec = (pcaps->link_fec_options & ICE_AQC_PHY_FEC_DIS) ? 6953 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) : 0; 6954 6955 if (pcaps->eee_cap & ICE_AQC_PHY_EEE_EN_100BASE_TX) { 6956 if (speed_fec_capa) { 6957 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_100M; 6958 speed_fec_capa[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6959 } 6960 num++; 6961 } 6962 6963 if (pcaps->eee_cap & (ICE_AQC_PHY_EEE_EN_1000BASE_T | 6964 ICE_AQC_PHY_EEE_EN_1000BASE_KX)) { 6965 if (speed_fec_capa) { 6966 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_1G; 6967 speed_fec_capa[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6968 } 6969 num++; 6970 } 6971 6972 if (pcaps->eee_cap & (ICE_AQC_PHY_EEE_EN_10GBASE_T | 6973 ICE_AQC_PHY_EEE_EN_10GBASE_KR)) { 6974 if (speed_fec_capa) { 6975 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_10G; 6976 speed_fec_capa[num].capa = auto_fec | link_nofec; 6977 6978 if (pcaps->link_fec_options & ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN) 6979 speed_fec_capa[num].capa |= RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 6980 } 6981 num++; 6982 } 6983 6984 if (pcaps->eee_cap & ICE_AQC_PHY_EEE_EN_25GBASE_KR) { 6985 if (speed_fec_capa) { 6986 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_25G; 6987 speed_fec_capa[num].capa = auto_fec | link_nofec; 6988 6989 if (pcaps->link_fec_options & ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN) 6990 speed_fec_capa[num].capa |= RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 6991 6992 if (pcaps->link_fec_options & ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN) 6993 speed_fec_capa[num].capa |= RTE_ETH_FEC_MODE_CAPA_MASK(RS); 6994 } 6995 num++; 6996 } 6997 6998 if (pcaps->eee_cap & ICE_AQC_PHY_EEE_EN_40GBASE_KR4) { 6999 if (speed_fec_capa) { 7000 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_40G; 7001 speed_fec_capa[num].capa = auto_fec | link_nofec; 7002 7003 if (pcaps->link_fec_options & ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN) 7004 speed_fec_capa[num].capa |= RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 7005 } 7006 num++; 7007 } 7008 7009 if (pcaps->eee_cap & (ICE_AQC_PHY_EEE_EN_50GBASE_KR2 | 7010 ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4)) { 7011 if (speed_fec_capa) { 7012 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_50G; 7013 speed_fec_capa[num].capa = auto_fec | link_nofec; 7014 7015 if (pcaps->link_fec_options & ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN) 7016 speed_fec_capa[num].capa |= RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 7017 7018 if (pcaps->link_fec_options & ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN) 7019 speed_fec_capa[num].capa |= RTE_ETH_FEC_MODE_CAPA_MASK(RS); 7020 } 7021 num++; 7022 } 7023 7024 if (pcaps->eee_cap & (ICE_AQC_PHY_EEE_EN_100GBASE_KR4 | 7025 ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4)) { 7026 if (speed_fec_capa) { 7027 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_100G; 7028 speed_fec_capa[num].capa = auto_fec | link_nofec; 7029 7030 if (pcaps->link_fec_options & ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN) 7031 speed_fec_capa[num].capa |= RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 7032 7033 if (pcaps->link_fec_options & ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN) 7034 speed_fec_capa[num].capa |= RTE_ETH_FEC_MODE_CAPA_MASK(RS); 7035 } 7036 num++; 7037 } 7038 7039 return num; 7040 } 7041 7042 static int 7043 ice_fec_get_capability(struct rte_eth_dev *dev, struct rte_eth_fec_capa *speed_fec_capa, 7044 unsigned int num) 7045 { 7046 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7047 struct ice_aqc_get_phy_caps_data pcaps = {0}; 7048 unsigned int capa_num; 7049 int ret; 7050 7051 ret = ice_aq_get_phy_caps(hw->port_info, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 7052 &pcaps, NULL); 7053 if (ret != ICE_SUCCESS) { 7054 PMD_DRV_LOG(ERR, "Failed to get capability information: %d", 7055 ret); 7056 return -ENOTSUP; 7057 } 7058 7059 /* first time to get capa_num */ 7060 capa_num = ice_fec_get_capa_num(&pcaps, NULL); 7061 if (!speed_fec_capa || num < capa_num) 7062 return capa_num; 7063 7064 return ice_fec_get_capa_num(&pcaps, speed_fec_capa); 7065 } 7066 7067 static int 7068 ice_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 7069 { 7070 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7071 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 7072 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 7073 bool link_up; 7074 u32 temp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 7075 struct ice_link_status link_status = {0}; 7076 struct ice_aqc_get_phy_caps_data pcaps = {0}; 7077 struct ice_port_info *pi = hw->port_info; 7078 u8 fec_config; 7079 int ret; 7080 7081 if (!pi) 7082 return -ENOTSUP; 7083 7084 ret = ice_get_link_info_safe(pf, enable_lse, &link_status); 7085 if (ret != ICE_SUCCESS) { 7086 PMD_DRV_LOG(ERR, "Failed to get link information: %d", 7087 ret); 7088 return -ENOTSUP; 7089 } 7090 7091 link_up = link_status.link_info & ICE_AQ_LINK_UP; 7092 7093 ret = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 7094 &pcaps, NULL); 7095 if (ret != ICE_SUCCESS) { 7096 PMD_DRV_LOG(ERR, "Failed to get capability information: %d", 7097 ret); 7098 return -ENOTSUP; 7099 } 7100 7101 /* Get current FEC mode from port info */ 7102 if (link_up) { 7103 switch (link_status.fec_info) { 7104 case ICE_AQ_LINK_25G_KR_FEC_EN: 7105 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 7106 break; 7107 case ICE_AQ_LINK_25G_RS_528_FEC_EN: 7108 /* fall-through */ 7109 case ICE_AQ_LINK_25G_RS_544_FEC_EN: 7110 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 7111 break; 7112 default: 7113 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 7114 break; 7115 } 7116 return 0; 7117 } 7118 7119 if (pcaps.caps & ICE_AQC_PHY_EN_AUTO_FEC) { 7120 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 7121 return 0; 7122 } 7123 7124 fec_config = pcaps.link_fec_options & ICE_AQC_PHY_FEC_MASK; 7125 7126 if (fec_config & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 7127 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 7128 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 7129 ICE_AQC_PHY_FEC_25G_KR_REQ)) 7130 temp_fec_capa |= RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 7131 7132 if (fec_config & (ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN | 7133 ICE_AQC_PHY_FEC_25G_RS_528_REQ | 7134 ICE_AQC_PHY_FEC_25G_RS_544_REQ)) 7135 temp_fec_capa |= RTE_ETH_FEC_MODE_CAPA_MASK(RS); 7136 7137 *fec_capa = temp_fec_capa; 7138 return 0; 7139 } 7140 7141 static int 7142 ice_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa) 7143 { 7144 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7145 struct ice_port_info *pi = hw->port_info; 7146 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 7147 bool fec_auto = false, fec_kr = false, fec_rs = false; 7148 7149 if (!pi) 7150 return -ENOTSUP; 7151 7152 if (fec_capa & ~(RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 7153 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 7154 RTE_ETH_FEC_MODE_CAPA_MASK(RS))) 7155 return -EINVAL; 7156 /* Copy the current user PHY configuration. The current user PHY 7157 * configuration is initialized during probe from PHY capabilities 7158 * software mode, and updated on set PHY configuration. 7159 */ 7160 memcpy(&cfg, &pi->phy.curr_user_phy_cfg, sizeof(cfg)); 7161 7162 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO)) 7163 fec_auto = true; 7164 7165 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER)) 7166 fec_kr = true; 7167 7168 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS)) 7169 fec_rs = true; 7170 7171 if (fec_auto) { 7172 if (fec_kr || fec_rs) { 7173 if (fec_rs) { 7174 cfg.link_fec_opt = ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN | 7175 ICE_AQC_PHY_FEC_25G_RS_528_REQ | 7176 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 7177 } 7178 if (fec_kr) { 7179 cfg.link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 7180 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 7181 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 7182 ICE_AQC_PHY_FEC_25G_KR_REQ; 7183 } 7184 } else { 7185 cfg.link_fec_opt = ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN | 7186 ICE_AQC_PHY_FEC_25G_RS_528_REQ | 7187 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 7188 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 7189 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 7190 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 7191 ICE_AQC_PHY_FEC_25G_KR_REQ; 7192 } 7193 } else { 7194 if (fec_kr ^ fec_rs) { 7195 if (fec_rs) { 7196 cfg.link_fec_opt = ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN | 7197 ICE_AQC_PHY_FEC_25G_RS_528_REQ | 7198 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 7199 } else { 7200 cfg.link_fec_opt = ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 7201 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 7202 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 7203 ICE_AQC_PHY_FEC_25G_KR_REQ; 7204 } 7205 } else { 7206 return -EINVAL; 7207 } 7208 } 7209 7210 /* Recovery of accidentally rewritten bit */ 7211 if (pi->phy.curr_user_phy_cfg.link_fec_opt & 7212 ICE_AQC_PHY_FEC_DIS) 7213 cfg.link_fec_opt |= ICE_AQC_PHY_FEC_DIS; 7214 7215 /* Proceed only if requesting different FEC mode */ 7216 if (pi->phy.curr_user_phy_cfg.link_fec_opt == cfg.link_fec_opt) 7217 return 0; 7218 7219 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 7220 7221 if (ice_aq_set_phy_cfg(pi->hw, pi, &cfg, NULL)) 7222 return -EAGAIN; 7223 7224 return 0; 7225 } 7226 7227 static int 7228 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 7229 struct rte_pci_device *pci_dev) 7230 { 7231 return rte_eth_dev_pci_generic_probe(pci_dev, 7232 sizeof(struct ice_adapter), 7233 ice_dev_init); 7234 } 7235 7236 static int 7237 ice_pci_remove(struct rte_pci_device *pci_dev) 7238 { 7239 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 7240 } 7241 7242 static struct rte_pci_driver rte_ice_pmd = { 7243 .id_table = pci_id_ice_map, 7244 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 7245 .probe = ice_pci_probe, 7246 .remove = ice_pci_remove, 7247 }; 7248 7249 /** 7250 * Driver initialization routine. 7251 * Invoked once at EAL init time. 7252 * Register itself as the [Poll Mode] Driver of PCI devices. 7253 */ 7254 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 7255 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 7256 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 7257 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 7258 ICE_HW_DEBUG_MASK_ARG "=0xXXX" 7259 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>" 7260 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" 7261 ICE_DEFAULT_MAC_DISABLE "=<0|1>" 7262 ICE_DDP_FILENAME_ARG "=</path/to/file>" 7263 ICE_DDP_LOAD_SCHED_ARG "=<0|1>" 7264 ICE_TM_LEVELS_ARG "=<N>" 7265 ICE_RX_LOW_LATENCY_ARG "=<0|1>"); 7266 7267 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE); 7268 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE); 7269 #ifdef RTE_ETHDEV_DEBUG_RX 7270 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG); 7271 #endif 7272 #ifdef RTE_ETHDEV_DEBUG_TX 7273 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG); 7274 #endif 7275 7276 bool is_ice_supported(struct rte_eth_dev *dev) 7277 { 7278 return !strcmp(dev->device->driver->name, rte_ice_pmd.driver.name); 7279 } 7280