1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2020 Intel Corporation 3 */ 4 5 #include <errno.h> 6 #include <stdbool.h> 7 #include <sys/queue.h> 8 #include <sys/types.h> 9 #include <unistd.h> 10 11 #include <rte_interrupts.h> 12 #include <rte_debug.h> 13 #include <rte_pci.h> 14 #include <rte_eal.h> 15 #include <rte_ether.h> 16 #include <ethdev_pci.h> 17 #include <rte_kvargs.h> 18 #include <rte_malloc.h> 19 #include <rte_memzone.h> 20 #include <dev_driver.h> 21 22 #include <iavf_devids.h> 23 24 #include "ice_generic_flow.h" 25 #include "ice_dcf_ethdev.h" 26 #include "ice_rxtx.h" 27 #include "../common/tx.h" 28 29 #define DCF_NUM_MACADDR_MAX 64 30 31 static int dcf_add_del_mc_addr_list(struct ice_dcf_hw *hw, 32 struct rte_ether_addr *mc_addrs, 33 uint32_t mc_addrs_num, bool add); 34 35 static int 36 ice_dcf_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 37 struct rte_eth_udp_tunnel *udp_tunnel); 38 static int 39 ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 40 struct rte_eth_udp_tunnel *udp_tunnel); 41 42 static int 43 ice_dcf_dev_init(struct rte_eth_dev *eth_dev); 44 45 static int 46 ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev); 47 48 static int 49 ice_dcf_cap_check_handler(__rte_unused const char *key, 50 const char *value, __rte_unused void *opaque); 51 52 static int 53 ice_dcf_engine_disabled_handler(__rte_unused const char *key, 54 const char *value, __rte_unused void *opaque); 55 56 struct ice_devarg { 57 enum ice_dcf_devrarg type; 58 const char *key; 59 int (*handler)(__rte_unused const char *key, 60 const char *value, __rte_unused void *opaque); 61 }; 62 63 static const struct ice_devarg ice_devargs_table[] = { 64 {ICE_DCF_DEVARG_CAP, "cap", ice_dcf_cap_check_handler}, 65 {ICE_DCF_DEVARG_ACL, "acl", ice_dcf_engine_disabled_handler}, 66 }; 67 68 struct rte_ice_dcf_xstats_name_off { 69 char name[RTE_ETH_XSTATS_NAME_SIZE]; 70 unsigned int offset; 71 }; 72 73 static const struct rte_ice_dcf_xstats_name_off rte_ice_dcf_stats_strings[] = { 74 {"rx_bytes", offsetof(struct ice_dcf_eth_stats, rx_bytes)}, 75 {"rx_unicast_packets", offsetof(struct ice_dcf_eth_stats, rx_unicast)}, 76 {"rx_multicast_packets", offsetof(struct ice_dcf_eth_stats, rx_multicast)}, 77 {"rx_broadcast_packets", offsetof(struct ice_dcf_eth_stats, rx_broadcast)}, 78 {"rx_dropped_packets", offsetof(struct ice_dcf_eth_stats, rx_discards)}, 79 {"rx_unknown_protocol_packets", offsetof(struct ice_dcf_eth_stats, 80 rx_unknown_protocol)}, 81 {"tx_bytes", offsetof(struct ice_dcf_eth_stats, tx_bytes)}, 82 {"tx_unicast_packets", offsetof(struct ice_dcf_eth_stats, tx_unicast)}, 83 {"tx_multicast_packets", offsetof(struct ice_dcf_eth_stats, tx_multicast)}, 84 {"tx_broadcast_packets", offsetof(struct ice_dcf_eth_stats, tx_broadcast)}, 85 {"tx_dropped_packets", offsetof(struct ice_dcf_eth_stats, tx_discards)}, 86 {"tx_error_packets", offsetof(struct ice_dcf_eth_stats, tx_errors)}, 87 }; 88 89 #define ICE_DCF_NB_XSTATS (sizeof(rte_ice_dcf_stats_strings) / \ 90 sizeof(rte_ice_dcf_stats_strings[0])) 91 92 static uint16_t 93 ice_dcf_recv_pkts(__rte_unused void *rx_queue, 94 __rte_unused struct rte_mbuf **bufs, 95 __rte_unused uint16_t nb_pkts) 96 { 97 return 0; 98 } 99 100 static uint16_t 101 ice_dcf_xmit_pkts(__rte_unused void *tx_queue, 102 __rte_unused struct rte_mbuf **bufs, 103 __rte_unused uint16_t nb_pkts) 104 { 105 return 0; 106 } 107 108 static int 109 ice_dcf_init_rxq(struct rte_eth_dev *dev, struct ice_rx_queue *rxq) 110 { 111 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; 112 struct rte_eth_dev_data *dev_data = dev->data; 113 struct iavf_hw *hw = &dcf_ad->real_hw.avf; 114 uint16_t buf_size, max_pkt_len; 115 116 buf_size = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM; 117 rxq->rx_hdr_len = 0; 118 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size, (1 << ICE_RLAN_CTX_DBUF_S)); 119 rxq->rx_buf_len = RTE_MIN(rxq->rx_buf_len, ICE_RX_MAX_DATA_BUF_SIZE); 120 max_pkt_len = RTE_MIN(ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len, 121 dev->data->mtu + ICE_ETH_OVERHEAD); 122 123 /* Check maximum packet length is set correctly. */ 124 if (max_pkt_len <= RTE_ETHER_MIN_LEN || 125 max_pkt_len > ICE_FRAME_SIZE_MAX) { 126 PMD_DRV_LOG(ERR, "maximum packet length must be " 127 "larger than %u and smaller than %u", 128 (uint32_t)RTE_ETHER_MIN_LEN, 129 (uint32_t)ICE_FRAME_SIZE_MAX); 130 return -EINVAL; 131 } 132 133 rxq->max_pkt_len = max_pkt_len; 134 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) || 135 (rxq->max_pkt_len + 2 * RTE_VLAN_HLEN) > buf_size) { 136 dev_data->scattered_rx = 1; 137 } 138 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id); 139 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); 140 IAVF_WRITE_FLUSH(hw); 141 142 return 0; 143 } 144 145 static int 146 ice_dcf_init_rx_queues(struct rte_eth_dev *dev) 147 { 148 struct ice_rx_queue **rxq = 149 (struct ice_rx_queue **)dev->data->rx_queues; 150 int i, ret; 151 152 for (i = 0; i < dev->data->nb_rx_queues; i++) { 153 if (!rxq[i] || !rxq[i]->q_set) 154 continue; 155 ret = ice_dcf_init_rxq(dev, rxq[i]); 156 if (ret) 157 return ret; 158 } 159 160 ice_set_rx_function(dev); 161 ice_set_tx_function(dev); 162 163 return 0; 164 } 165 166 #define IAVF_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 167 #define IAVF_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 168 169 #define IAVF_ITR_INDEX_DEFAULT 0 170 #define IAVF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 171 #define IAVF_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 172 173 static inline uint16_t 174 iavf_calc_itr_interval(int16_t interval) 175 { 176 if (interval < 0 || interval > IAVF_QUEUE_ITR_INTERVAL_MAX) 177 interval = IAVF_QUEUE_ITR_INTERVAL_DEFAULT; 178 179 /* Convert to hardware count, as writing each 1 represents 2 us */ 180 return interval / 2; 181 } 182 183 static int 184 ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev, 185 struct rte_intr_handle *intr_handle) 186 { 187 struct ice_dcf_adapter *adapter = dev->data->dev_private; 188 struct ice_dcf_hw *hw = &adapter->real_hw; 189 uint16_t interval, i; 190 int vec; 191 192 if (rte_intr_cap_multiple(intr_handle) && 193 dev->data->dev_conf.intr_conf.rxq) { 194 if (rte_intr_efd_enable(intr_handle, dev->data->nb_rx_queues)) 195 return -1; 196 } 197 198 if (rte_intr_dp_is_en(intr_handle)) { 199 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 200 dev->data->nb_rx_queues)) { 201 PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec", 202 dev->data->nb_rx_queues); 203 return -1; 204 } 205 } 206 207 if (!dev->data->dev_conf.intr_conf.rxq || 208 !rte_intr_dp_is_en(intr_handle)) { 209 /* Rx interrupt disabled, Map interrupt only for writeback */ 210 hw->nb_msix = 1; 211 if (hw->vf_res->vf_cap_flags & 212 VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) { 213 /* If WB_ON_ITR supports, enable it */ 214 hw->msix_base = IAVF_RX_VEC_START; 215 /* Set the ITR for index zero, to 2us to make sure that 216 * we leave time for aggregation to occur, but don't 217 * increase latency dramatically. 218 */ 219 IAVF_WRITE_REG(&hw->avf, 220 IAVF_VFINT_DYN_CTLN1(hw->msix_base - 1), 221 (0 << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | 222 IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK | 223 (2UL << IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT)); 224 } else { 225 /* If no WB_ON_ITR offload flags, need to set 226 * interrupt for descriptor write back. 227 */ 228 hw->msix_base = IAVF_MISC_VEC_ID; 229 230 /* set ITR to max */ 231 interval = 232 iavf_calc_itr_interval(IAVF_QUEUE_ITR_INTERVAL_MAX); 233 IAVF_WRITE_REG(&hw->avf, IAVF_VFINT_DYN_CTL01, 234 IAVF_VFINT_DYN_CTL01_INTENA_MASK | 235 (IAVF_ITR_INDEX_DEFAULT << 236 IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) | 237 (interval << 238 IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT)); 239 } 240 IAVF_WRITE_FLUSH(&hw->avf); 241 /* map all queues to the same interrupt */ 242 for (i = 0; i < dev->data->nb_rx_queues; i++) 243 hw->rxq_map[hw->msix_base] |= 1 << i; 244 } else { 245 if (!rte_intr_allow_others(intr_handle)) { 246 hw->nb_msix = 1; 247 hw->msix_base = IAVF_MISC_VEC_ID; 248 for (i = 0; i < dev->data->nb_rx_queues; i++) { 249 hw->rxq_map[hw->msix_base] |= 1 << i; 250 rte_intr_vec_list_index_set(intr_handle, 251 i, IAVF_MISC_VEC_ID); 252 } 253 PMD_DRV_LOG(DEBUG, 254 "vector %u are mapping to all Rx queues", 255 hw->msix_base); 256 } else { 257 /* If Rx interrupt is required, and we can use 258 * multi interrupts, then the vec is from 1 259 */ 260 hw->nb_msix = RTE_MIN(hw->vf_res->max_vectors, 261 rte_intr_nb_efd_get(intr_handle)); 262 hw->msix_base = IAVF_MISC_VEC_ID; 263 vec = IAVF_MISC_VEC_ID; 264 for (i = 0; i < dev->data->nb_rx_queues; i++) { 265 hw->rxq_map[vec] |= 1 << i; 266 rte_intr_vec_list_index_set(intr_handle, 267 i, vec++); 268 if (vec >= hw->nb_msix) 269 vec = IAVF_RX_VEC_START; 270 } 271 PMD_DRV_LOG(DEBUG, 272 "%u vectors are mapping to %u Rx queues", 273 hw->nb_msix, dev->data->nb_rx_queues); 274 } 275 } 276 277 if (ice_dcf_config_irq_map(hw)) { 278 PMD_DRV_LOG(ERR, "config interrupt mapping failed"); 279 return -1; 280 } 281 return 0; 282 } 283 284 static int 285 alloc_rxq_mbufs(struct ice_rx_queue *rxq) 286 { 287 volatile union ice_rx_flex_desc *rxd; 288 struct rte_mbuf *mbuf = NULL; 289 uint64_t dma_addr; 290 uint16_t i; 291 292 for (i = 0; i < rxq->nb_rx_desc; i++) { 293 mbuf = rte_mbuf_raw_alloc(rxq->mp); 294 if (unlikely(!mbuf)) { 295 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX"); 296 return -ENOMEM; 297 } 298 299 rte_mbuf_refcnt_set(mbuf, 1); 300 mbuf->next = NULL; 301 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 302 mbuf->nb_segs = 1; 303 mbuf->port = rxq->port_id; 304 305 dma_addr = 306 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); 307 308 rxd = &rxq->rx_ring[i]; 309 rxd->read.pkt_addr = dma_addr; 310 rxd->read.hdr_addr = 0; 311 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC 312 rxd->read.rsvd1 = 0; 313 rxd->read.rsvd2 = 0; 314 #endif 315 316 rxq->sw_ring[i].mbuf = (void *)mbuf; 317 } 318 319 return 0; 320 } 321 322 static int 323 ice_dcf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) 324 { 325 struct ice_dcf_adapter *ad = dev->data->dev_private; 326 struct iavf_hw *hw = &ad->real_hw.avf; 327 struct ice_rx_queue *rxq; 328 int err = 0; 329 330 if (rx_queue_id >= dev->data->nb_rx_queues) 331 return -EINVAL; 332 333 rxq = dev->data->rx_queues[rx_queue_id]; 334 335 err = alloc_rxq_mbufs(rxq); 336 if (err) { 337 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf"); 338 return err; 339 } 340 341 rte_wmb(); 342 343 /* Init the RX tail register. */ 344 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); 345 IAVF_WRITE_FLUSH(hw); 346 347 /* Ready to switch the queue on */ 348 err = ice_dcf_switch_queue(&ad->real_hw, rx_queue_id, true, true); 349 if (err) { 350 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on", 351 rx_queue_id); 352 return err; 353 } 354 355 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 356 357 return 0; 358 } 359 360 static inline void 361 reset_rx_queue(struct ice_rx_queue *rxq) 362 { 363 uint16_t len; 364 uint32_t i; 365 366 if (!rxq) 367 return; 368 369 len = rxq->nb_rx_desc + ICE_RX_MAX_BURST; 370 371 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++) 372 ((volatile char *)rxq->rx_ring)[i] = 0; 373 374 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf)); 375 376 for (i = 0; i < ICE_RX_MAX_BURST; i++) 377 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf; 378 379 /* for rx bulk */ 380 rxq->rx_nb_avail = 0; 381 rxq->rx_next_avail = 0; 382 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1); 383 384 rxq->rx_tail = 0; 385 rxq->nb_rx_hold = 0; 386 rxq->pkt_first_seg = NULL; 387 rxq->pkt_last_seg = NULL; 388 } 389 390 static inline void 391 reset_tx_queue(struct ci_tx_queue *txq) 392 { 393 struct ci_tx_entry *txe; 394 uint32_t i, size; 395 uint16_t prev; 396 397 if (!txq) { 398 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL"); 399 return; 400 } 401 402 txe = txq->sw_ring; 403 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc; 404 for (i = 0; i < size; i++) 405 ((volatile char *)txq->ice_tx_ring)[i] = 0; 406 407 prev = (uint16_t)(txq->nb_tx_desc - 1); 408 for (i = 0; i < txq->nb_tx_desc; i++) { 409 txq->ice_tx_ring[i].cmd_type_offset_bsz = 410 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE); 411 txe[i].mbuf = NULL; 412 txe[i].last_id = i; 413 txe[prev].next_id = i; 414 prev = i; 415 } 416 417 txq->tx_tail = 0; 418 txq->nb_tx_used = 0; 419 420 txq->last_desc_cleaned = txq->nb_tx_desc - 1; 421 txq->nb_tx_free = txq->nb_tx_desc - 1; 422 423 txq->tx_next_dd = txq->tx_rs_thresh - 1; 424 txq->tx_next_rs = txq->tx_rs_thresh - 1; 425 } 426 427 static int 428 ice_dcf_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) 429 { 430 struct ice_dcf_adapter *ad = dev->data->dev_private; 431 struct ice_dcf_hw *hw = &ad->real_hw; 432 struct ice_rx_queue *rxq; 433 int err; 434 435 if (rx_queue_id >= dev->data->nb_rx_queues) 436 return -EINVAL; 437 438 err = ice_dcf_switch_queue(hw, rx_queue_id, true, false); 439 if (err) { 440 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off", 441 rx_queue_id); 442 return err; 443 } 444 445 rxq = dev->data->rx_queues[rx_queue_id]; 446 rxq->rx_rel_mbufs(rxq); 447 reset_rx_queue(rxq); 448 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 449 450 return 0; 451 } 452 453 static int 454 ice_dcf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) 455 { 456 struct ice_dcf_adapter *ad = dev->data->dev_private; 457 struct iavf_hw *hw = &ad->real_hw.avf; 458 struct ci_tx_queue *txq; 459 int err = 0; 460 461 if (tx_queue_id >= dev->data->nb_tx_queues) 462 return -EINVAL; 463 464 txq = dev->data->tx_queues[tx_queue_id]; 465 466 /* Init the RX tail register. */ 467 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(tx_queue_id); 468 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0); 469 IAVF_WRITE_FLUSH(hw); 470 471 /* Ready to switch the queue on */ 472 err = ice_dcf_switch_queue(&ad->real_hw, tx_queue_id, false, true); 473 474 if (err) { 475 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on", 476 tx_queue_id); 477 return err; 478 } 479 480 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 481 482 return 0; 483 } 484 485 static int 486 ice_dcf_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) 487 { 488 struct ice_dcf_adapter *ad = dev->data->dev_private; 489 struct ice_dcf_hw *hw = &ad->real_hw; 490 struct ci_tx_queue *txq; 491 int err; 492 493 if (tx_queue_id >= dev->data->nb_tx_queues) 494 return -EINVAL; 495 496 err = ice_dcf_switch_queue(hw, tx_queue_id, false, false); 497 if (err) { 498 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off", 499 tx_queue_id); 500 return err; 501 } 502 503 txq = dev->data->tx_queues[tx_queue_id]; 504 ci_txq_release_all_mbufs(txq, false); 505 reset_tx_queue(txq); 506 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 507 508 return 0; 509 } 510 511 static int 512 ice_dcf_start_queues(struct rte_eth_dev *dev) 513 { 514 struct ice_rx_queue *rxq; 515 struct ci_tx_queue *txq; 516 int nb_rxq = 0; 517 int nb_txq, i; 518 519 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) { 520 txq = dev->data->tx_queues[nb_txq]; 521 if (txq->tx_deferred_start) 522 continue; 523 if (ice_dcf_tx_queue_start(dev, nb_txq) != 0) { 524 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_txq); 525 goto tx_err; 526 } 527 } 528 529 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) { 530 rxq = dev->data->rx_queues[nb_rxq]; 531 if (rxq->rx_deferred_start) 532 continue; 533 if (ice_dcf_rx_queue_start(dev, nb_rxq) != 0) { 534 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_rxq); 535 goto rx_err; 536 } 537 } 538 539 return 0; 540 541 /* stop the started queues if failed to start all queues */ 542 rx_err: 543 for (i = 0; i < nb_rxq; i++) 544 ice_dcf_rx_queue_stop(dev, i); 545 tx_err: 546 for (i = 0; i < nb_txq; i++) 547 ice_dcf_tx_queue_stop(dev, i); 548 549 return -1; 550 } 551 552 static int 553 ice_dcf_dev_start(struct rte_eth_dev *dev) 554 { 555 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; 556 struct rte_intr_handle *intr_handle = dev->intr_handle; 557 struct ice_adapter *ad = &dcf_ad->parent; 558 struct ice_dcf_hw *hw = &dcf_ad->real_hw; 559 int ret; 560 561 if (hw->resetting) { 562 PMD_DRV_LOG(ERR, 563 "The DCF has been reset by PF, please reinit first"); 564 return -EIO; 565 } 566 567 if (hw->tm_conf.root && !hw->tm_conf.committed) { 568 PMD_DRV_LOG(ERR, 569 "please call hierarchy_commit() before starting the port"); 570 return -EIO; 571 } 572 573 ad->pf.adapter_stopped = 0; 574 575 hw->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues, 576 dev->data->nb_tx_queues); 577 578 ret = ice_dcf_init_rx_queues(dev); 579 if (ret) { 580 PMD_DRV_LOG(ERR, "Fail to init queues"); 581 return ret; 582 } 583 584 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF) { 585 ret = ice_dcf_init_rss(hw); 586 if (ret) { 587 PMD_DRV_LOG(ERR, "Failed to configure RSS"); 588 return ret; 589 } 590 } 591 592 ret = ice_dcf_configure_queues(hw); 593 if (ret) { 594 PMD_DRV_LOG(ERR, "Fail to config queues"); 595 return ret; 596 } 597 598 ret = ice_dcf_config_rx_queues_irqs(dev, intr_handle); 599 if (ret) { 600 PMD_DRV_LOG(ERR, "Fail to config rx queues' irqs"); 601 return ret; 602 } 603 604 if (dev->data->dev_conf.intr_conf.rxq != 0) { 605 rte_intr_disable(intr_handle); 606 rte_intr_enable(intr_handle); 607 } 608 609 ret = ice_dcf_start_queues(dev); 610 if (ret) { 611 PMD_DRV_LOG(ERR, "Failed to enable queues"); 612 return ret; 613 } 614 615 ret = ice_dcf_add_del_all_mac_addr(hw, hw->eth_dev->data->mac_addrs, 616 true, VIRTCHNL_ETHER_ADDR_PRIMARY); 617 if (ret) { 618 PMD_DRV_LOG(ERR, "Failed to add mac addr"); 619 return ret; 620 } 621 622 if (dcf_ad->mc_addrs_num) { 623 /* flush previous addresses */ 624 ret = dcf_add_del_mc_addr_list(hw, dcf_ad->mc_addrs, 625 dcf_ad->mc_addrs_num, true); 626 if (ret) 627 return ret; 628 } 629 630 631 dev->data->dev_link.link_status = RTE_ETH_LINK_UP; 632 633 return 0; 634 } 635 636 static void 637 ice_dcf_stop_queues(struct rte_eth_dev *dev) 638 { 639 struct ice_dcf_adapter *ad = dev->data->dev_private; 640 struct ice_dcf_hw *hw = &ad->real_hw; 641 struct ice_rx_queue *rxq; 642 struct ci_tx_queue *txq; 643 int ret, i; 644 645 /* Stop All queues */ 646 ret = ice_dcf_disable_queues(hw); 647 if (ret) 648 PMD_DRV_LOG(WARNING, "Fail to stop queues"); 649 650 for (i = 0; i < dev->data->nb_tx_queues; i++) { 651 txq = dev->data->tx_queues[i]; 652 if (!txq) 653 continue; 654 ci_txq_release_all_mbufs(txq, false); 655 reset_tx_queue(txq); 656 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 657 } 658 for (i = 0; i < dev->data->nb_rx_queues; i++) { 659 rxq = dev->data->rx_queues[i]; 660 if (!rxq) 661 continue; 662 rxq->rx_rel_mbufs(rxq); 663 reset_rx_queue(rxq); 664 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 665 } 666 } 667 668 static int 669 ice_dcf_dev_stop(struct rte_eth_dev *dev) 670 { 671 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; 672 struct rte_intr_handle *intr_handle = dev->intr_handle; 673 struct ice_adapter *ad = &dcf_ad->parent; 674 675 if (ad->pf.adapter_stopped == 1) { 676 PMD_DRV_LOG(DEBUG, "Port is already stopped"); 677 return 0; 678 } 679 680 /* Stop the VF representors for this device */ 681 ice_dcf_vf_repr_stop_all(dcf_ad); 682 683 ice_dcf_stop_queues(dev); 684 685 rte_intr_efd_disable(intr_handle); 686 rte_intr_vec_list_free(intr_handle); 687 688 ice_dcf_add_del_all_mac_addr(&dcf_ad->real_hw, 689 dcf_ad->real_hw.eth_dev->data->mac_addrs, 690 false, VIRTCHNL_ETHER_ADDR_PRIMARY); 691 692 if (dcf_ad->mc_addrs_num) 693 /* flush previous addresses */ 694 (void)dcf_add_del_mc_addr_list(&dcf_ad->real_hw, 695 dcf_ad->mc_addrs, 696 dcf_ad->mc_addrs_num, false); 697 698 dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; 699 ad->pf.adapter_stopped = 1; 700 701 return 0; 702 } 703 704 static int 705 ice_dcf_dev_configure(struct rte_eth_dev *dev) 706 { 707 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; 708 struct ice_adapter *ad = &dcf_ad->parent; 709 710 ad->rx_bulk_alloc_allowed = true; 711 ad->tx_simple_allowed = true; 712 713 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 714 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 715 716 return 0; 717 } 718 719 static int 720 ice_dcf_dev_info_get(struct rte_eth_dev *dev, 721 struct rte_eth_dev_info *dev_info) 722 { 723 struct ice_dcf_adapter *adapter = dev->data->dev_private; 724 struct ice_dcf_hw *hw = &adapter->real_hw; 725 726 dev_info->max_mac_addrs = DCF_NUM_MACADDR_MAX; 727 dev_info->max_rx_queues = hw->vsi_res->num_queue_pairs; 728 dev_info->max_tx_queues = hw->vsi_res->num_queue_pairs; 729 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 730 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 731 dev_info->hash_key_size = hw->vf_res->rss_key_size; 732 dev_info->reta_size = hw->vf_res->rss_lut_size; 733 dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL; 734 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 735 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 736 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 737 738 dev_info->rx_offload_capa = 739 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 740 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 741 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 742 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 743 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 744 RTE_ETH_RX_OFFLOAD_SCATTER | 745 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 746 RTE_ETH_RX_OFFLOAD_RSS_HASH; 747 dev_info->tx_offload_capa = 748 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 749 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 750 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 751 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 752 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 753 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 754 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | 755 RTE_ETH_TX_OFFLOAD_TCP_TSO | 756 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | 757 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | 758 RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO | 759 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | 760 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 761 762 dev_info->default_rxconf = (struct rte_eth_rxconf) { 763 .rx_thresh = { 764 .pthresh = ICE_DEFAULT_RX_PTHRESH, 765 .hthresh = ICE_DEFAULT_RX_HTHRESH, 766 .wthresh = ICE_DEFAULT_RX_WTHRESH, 767 }, 768 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 769 .rx_drop_en = 0, 770 .offloads = 0, 771 }; 772 773 dev_info->default_txconf = (struct rte_eth_txconf) { 774 .tx_thresh = { 775 .pthresh = ICE_DEFAULT_TX_PTHRESH, 776 .hthresh = ICE_DEFAULT_TX_HTHRESH, 777 .wthresh = ICE_DEFAULT_TX_WTHRESH, 778 }, 779 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 780 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 781 .offloads = 0, 782 }; 783 784 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 785 .nb_max = ICE_MAX_RING_DESC, 786 .nb_min = ICE_MIN_RING_DESC, 787 .nb_align = ICE_ALIGN_RING_DESC, 788 }; 789 790 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 791 .nb_max = ICE_MAX_RING_DESC, 792 .nb_min = ICE_MIN_RING_DESC, 793 .nb_align = ICE_ALIGN_RING_DESC, 794 }; 795 796 return 0; 797 } 798 799 static int 800 dcf_config_promisc(struct ice_dcf_adapter *adapter, 801 bool enable_unicast, 802 bool enable_multicast) 803 { 804 struct ice_dcf_hw *hw = &adapter->real_hw; 805 struct virtchnl_promisc_info promisc; 806 struct dcf_virtchnl_cmd args; 807 int err; 808 809 promisc.flags = 0; 810 promisc.vsi_id = hw->vsi_res->vsi_id; 811 812 if (enable_unicast) 813 promisc.flags |= FLAG_VF_UNICAST_PROMISC; 814 815 if (enable_multicast) 816 promisc.flags |= FLAG_VF_MULTICAST_PROMISC; 817 818 memset(&args, 0, sizeof(args)); 819 args.v_op = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE; 820 args.req_msg = (uint8_t *)&promisc; 821 args.req_msglen = sizeof(promisc); 822 823 err = ice_dcf_execute_virtchnl_cmd(hw, &args); 824 if (err) { 825 PMD_DRV_LOG(ERR, 826 "fail to execute command VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE"); 827 return err; 828 } 829 830 adapter->promisc_unicast_enabled = enable_unicast; 831 adapter->promisc_multicast_enabled = enable_multicast; 832 return 0; 833 } 834 835 static int 836 ice_dcf_dev_promiscuous_enable(__rte_unused struct rte_eth_dev *dev) 837 { 838 struct ice_dcf_adapter *adapter = dev->data->dev_private; 839 840 if (adapter->promisc_unicast_enabled) { 841 PMD_DRV_LOG(INFO, "promiscuous has been enabled"); 842 return 0; 843 } 844 845 return dcf_config_promisc(adapter, true, 846 adapter->promisc_multicast_enabled); 847 } 848 849 static int 850 ice_dcf_dev_promiscuous_disable(__rte_unused struct rte_eth_dev *dev) 851 { 852 struct ice_dcf_adapter *adapter = dev->data->dev_private; 853 854 if (!adapter->promisc_unicast_enabled) { 855 PMD_DRV_LOG(INFO, "promiscuous has been disabled"); 856 return 0; 857 } 858 859 return dcf_config_promisc(adapter, false, 860 adapter->promisc_multicast_enabled); 861 } 862 863 static int 864 ice_dcf_dev_allmulticast_enable(__rte_unused struct rte_eth_dev *dev) 865 { 866 struct ice_dcf_adapter *adapter = dev->data->dev_private; 867 868 if (adapter->promisc_multicast_enabled) { 869 PMD_DRV_LOG(INFO, "allmulticast has been enabled"); 870 return 0; 871 } 872 873 return dcf_config_promisc(adapter, adapter->promisc_unicast_enabled, 874 true); 875 } 876 877 static int 878 ice_dcf_dev_allmulticast_disable(__rte_unused struct rte_eth_dev *dev) 879 { 880 struct ice_dcf_adapter *adapter = dev->data->dev_private; 881 882 if (!adapter->promisc_multicast_enabled) { 883 PMD_DRV_LOG(INFO, "allmulticast has been disabled"); 884 return 0; 885 } 886 887 return dcf_config_promisc(adapter, adapter->promisc_unicast_enabled, 888 false); 889 } 890 891 static int 892 dcf_dev_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr, 893 __rte_unused uint32_t index, 894 __rte_unused uint32_t pool) 895 { 896 struct ice_dcf_adapter *adapter = dev->data->dev_private; 897 int err; 898 899 if (rte_is_zero_ether_addr(addr)) { 900 PMD_DRV_LOG(ERR, "Invalid Ethernet Address"); 901 return -EINVAL; 902 } 903 904 err = ice_dcf_add_del_all_mac_addr(&adapter->real_hw, addr, true, 905 VIRTCHNL_ETHER_ADDR_EXTRA); 906 if (err) { 907 PMD_DRV_LOG(ERR, "fail to add MAC address"); 908 return err; 909 } 910 911 return 0; 912 } 913 914 static void 915 dcf_dev_del_mac_addr(struct rte_eth_dev *dev, uint32_t index) 916 { 917 struct ice_dcf_adapter *adapter = dev->data->dev_private; 918 struct rte_ether_addr *addr = &dev->data->mac_addrs[index]; 919 int err; 920 921 err = ice_dcf_add_del_all_mac_addr(&adapter->real_hw, addr, false, 922 VIRTCHNL_ETHER_ADDR_EXTRA); 923 if (err) 924 PMD_DRV_LOG(ERR, "fail to remove MAC address"); 925 } 926 927 static int 928 dcf_add_del_mc_addr_list(struct ice_dcf_hw *hw, 929 struct rte_ether_addr *mc_addrs, 930 uint32_t mc_addrs_num, bool add) 931 { 932 struct virtchnl_ether_addr_list *list; 933 struct dcf_virtchnl_cmd args; 934 uint32_t i; 935 int len, err = 0; 936 937 len = sizeof(struct virtchnl_ether_addr_list); 938 len += sizeof(struct virtchnl_ether_addr) * mc_addrs_num; 939 940 list = rte_zmalloc(NULL, len, 0); 941 if (!list) { 942 PMD_DRV_LOG(ERR, "fail to allocate memory"); 943 return -ENOMEM; 944 } 945 946 for (i = 0; i < mc_addrs_num; i++) { 947 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes, 948 sizeof(list->list[i].addr)); 949 list->list[i].type = VIRTCHNL_ETHER_ADDR_EXTRA; 950 } 951 952 list->vsi_id = hw->vsi_res->vsi_id; 953 list->num_elements = mc_addrs_num; 954 955 memset(&args, 0, sizeof(args)); 956 args.v_op = add ? VIRTCHNL_OP_ADD_ETH_ADDR : 957 VIRTCHNL_OP_DEL_ETH_ADDR; 958 args.req_msg = (uint8_t *)list; 959 args.req_msglen = len; 960 err = ice_dcf_execute_virtchnl_cmd(hw, &args); 961 if (err) 962 PMD_DRV_LOG(ERR, "fail to execute command %s", 963 add ? "OP_ADD_ETHER_ADDRESS" : 964 "OP_DEL_ETHER_ADDRESS"); 965 rte_free(list); 966 return err; 967 } 968 969 static int 970 dcf_set_mc_addr_list(struct rte_eth_dev *dev, 971 struct rte_ether_addr *mc_addrs, 972 uint32_t mc_addrs_num) 973 { 974 struct ice_dcf_adapter *adapter = dev->data->dev_private; 975 struct ice_dcf_hw *hw = &adapter->real_hw; 976 uint32_t i; 977 int ret; 978 979 980 if (mc_addrs_num > DCF_NUM_MACADDR_MAX) { 981 PMD_DRV_LOG(ERR, 982 "can't add more than a limited number (%u) of addresses.", 983 (uint32_t)DCF_NUM_MACADDR_MAX); 984 return -EINVAL; 985 } 986 987 for (i = 0; i < mc_addrs_num; i++) { 988 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) { 989 const uint8_t *mac = mc_addrs[i].addr_bytes; 990 991 PMD_DRV_LOG(ERR, 992 "Invalid mac: %02x:%02x:%02x:%02x:%02x:%02x", 993 mac[0], mac[1], mac[2], mac[3], mac[4], 994 mac[5]); 995 return -EINVAL; 996 } 997 } 998 999 if (adapter->mc_addrs_num) { 1000 /* flush previous addresses */ 1001 ret = dcf_add_del_mc_addr_list(hw, adapter->mc_addrs, 1002 adapter->mc_addrs_num, false); 1003 if (ret) 1004 return ret; 1005 } 1006 if (!mc_addrs_num) { 1007 adapter->mc_addrs_num = 0; 1008 return 0; 1009 } 1010 1011 /* add new ones */ 1012 ret = dcf_add_del_mc_addr_list(hw, mc_addrs, mc_addrs_num, true); 1013 if (ret) { 1014 /* if adding mac address list fails, should add the 1015 * previous addresses back. 1016 */ 1017 if (adapter->mc_addrs_num) 1018 (void)dcf_add_del_mc_addr_list(hw, adapter->mc_addrs, 1019 adapter->mc_addrs_num, 1020 true); 1021 return ret; 1022 } 1023 adapter->mc_addrs_num = mc_addrs_num; 1024 memcpy(adapter->mc_addrs, 1025 mc_addrs, mc_addrs_num * sizeof(*mc_addrs)); 1026 1027 return 0; 1028 } 1029 1030 static int 1031 dcf_dev_set_default_mac_addr(struct rte_eth_dev *dev, 1032 struct rte_ether_addr *mac_addr) 1033 { 1034 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1035 struct ice_dcf_hw *hw = &adapter->real_hw; 1036 struct rte_ether_addr *old_addr; 1037 int ret; 1038 1039 old_addr = hw->eth_dev->data->mac_addrs; 1040 if (rte_is_same_ether_addr(old_addr, mac_addr)) 1041 return 0; 1042 1043 ret = ice_dcf_add_del_all_mac_addr(&adapter->real_hw, old_addr, false, 1044 VIRTCHNL_ETHER_ADDR_PRIMARY); 1045 if (ret) 1046 PMD_DRV_LOG(ERR, "Fail to delete old MAC:" 1047 " %02X:%02X:%02X:%02X:%02X:%02X", 1048 old_addr->addr_bytes[0], 1049 old_addr->addr_bytes[1], 1050 old_addr->addr_bytes[2], 1051 old_addr->addr_bytes[3], 1052 old_addr->addr_bytes[4], 1053 old_addr->addr_bytes[5]); 1054 1055 ret = ice_dcf_add_del_all_mac_addr(&adapter->real_hw, mac_addr, true, 1056 VIRTCHNL_ETHER_ADDR_PRIMARY); 1057 if (ret) 1058 PMD_DRV_LOG(ERR, "Fail to add new MAC:" 1059 " %02X:%02X:%02X:%02X:%02X:%02X", 1060 mac_addr->addr_bytes[0], 1061 mac_addr->addr_bytes[1], 1062 mac_addr->addr_bytes[2], 1063 mac_addr->addr_bytes[3], 1064 mac_addr->addr_bytes[4], 1065 mac_addr->addr_bytes[5]); 1066 1067 if (ret) 1068 return -EIO; 1069 1070 rte_ether_addr_copy(mac_addr, hw->eth_dev->data->mac_addrs); 1071 return 0; 1072 } 1073 1074 static int 1075 dcf_add_del_vlan_v2(struct ice_dcf_hw *hw, uint16_t vlanid, bool add) 1076 { 1077 struct virtchnl_vlan_supported_caps *supported_caps = 1078 &hw->vlan_v2_caps.filtering.filtering_support; 1079 struct virtchnl_vlan *vlan_setting; 1080 struct virtchnl_vlan_filter_list_v2 vlan_filter; 1081 struct dcf_virtchnl_cmd args; 1082 uint32_t filtering_caps; 1083 int err; 1084 1085 if (supported_caps->outer) { 1086 filtering_caps = supported_caps->outer; 1087 vlan_setting = &vlan_filter.filters[0].outer; 1088 } else { 1089 filtering_caps = supported_caps->inner; 1090 vlan_setting = &vlan_filter.filters[0].inner; 1091 } 1092 1093 if (!(filtering_caps & VIRTCHNL_VLAN_ETHERTYPE_8100)) 1094 return -ENOTSUP; 1095 1096 memset(&vlan_filter, 0, sizeof(vlan_filter)); 1097 vlan_filter.vport_id = hw->vsi_res->vsi_id; 1098 vlan_filter.num_elements = 1; 1099 vlan_setting->tpid = RTE_ETHER_TYPE_VLAN; 1100 vlan_setting->tci = vlanid; 1101 1102 memset(&args, 0, sizeof(args)); 1103 args.v_op = add ? VIRTCHNL_OP_ADD_VLAN_V2 : VIRTCHNL_OP_DEL_VLAN_V2; 1104 args.req_msg = (uint8_t *)&vlan_filter; 1105 args.req_msglen = sizeof(vlan_filter); 1106 err = ice_dcf_execute_virtchnl_cmd(hw, &args); 1107 if (err) 1108 PMD_DRV_LOG(ERR, "fail to execute command %s", 1109 add ? "OP_ADD_VLAN_V2" : "OP_DEL_VLAN_V2"); 1110 1111 return err; 1112 } 1113 1114 static int 1115 dcf_add_del_vlan(struct ice_dcf_hw *hw, uint16_t vlanid, bool add) 1116 { 1117 struct virtchnl_vlan_filter_list *vlan_list; 1118 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) + 1119 sizeof(uint16_t)]; 1120 struct dcf_virtchnl_cmd args; 1121 int err; 1122 1123 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer; 1124 vlan_list->vsi_id = hw->vsi_res->vsi_id; 1125 vlan_list->num_elements = 1; 1126 vlan_list->vlan_id[0] = vlanid; 1127 1128 memset(&args, 0, sizeof(args)); 1129 args.v_op = add ? VIRTCHNL_OP_ADD_VLAN : VIRTCHNL_OP_DEL_VLAN; 1130 args.req_msg = cmd_buffer; 1131 args.req_msglen = sizeof(cmd_buffer); 1132 err = ice_dcf_execute_virtchnl_cmd(hw, &args); 1133 if (err) 1134 PMD_DRV_LOG(ERR, "fail to execute command %s", 1135 add ? "OP_ADD_VLAN" : "OP_DEL_VLAN"); 1136 1137 return err; 1138 } 1139 1140 static int 1141 dcf_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1142 { 1143 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1144 struct ice_dcf_hw *hw = &adapter->real_hw; 1145 int err; 1146 1147 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) { 1148 err = dcf_add_del_vlan_v2(hw, vlan_id, on); 1149 if (err) 1150 return -EIO; 1151 return 0; 1152 } 1153 1154 if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN)) 1155 return -ENOTSUP; 1156 1157 err = dcf_add_del_vlan(hw, vlan_id, on); 1158 if (err) 1159 return -EIO; 1160 return 0; 1161 } 1162 1163 static void 1164 dcf_iterate_vlan_filters_v2(struct rte_eth_dev *dev, bool enable) 1165 { 1166 struct rte_vlan_filter_conf *vfc = &dev->data->vlan_filter_conf; 1167 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1168 struct ice_dcf_hw *hw = &adapter->real_hw; 1169 uint32_t i, j; 1170 uint64_t ids; 1171 1172 for (i = 0; i < RTE_DIM(vfc->ids); i++) { 1173 if (vfc->ids[i] == 0) 1174 continue; 1175 1176 ids = vfc->ids[i]; 1177 for (j = 0; ids != 0 && j < 64; j++, ids >>= 1) { 1178 if (ids & 1) 1179 dcf_add_del_vlan_v2(hw, 64 * i + j, enable); 1180 } 1181 } 1182 } 1183 1184 static int 1185 dcf_config_vlan_strip_v2(struct ice_dcf_hw *hw, bool enable) 1186 { 1187 struct virtchnl_vlan_supported_caps *stripping_caps = 1188 &hw->vlan_v2_caps.offloads.stripping_support; 1189 struct virtchnl_vlan_setting vlan_strip; 1190 struct dcf_virtchnl_cmd args; 1191 uint32_t *ethertype; 1192 int ret; 1193 1194 if ((stripping_caps->outer & VIRTCHNL_VLAN_ETHERTYPE_8100) && 1195 (stripping_caps->outer & VIRTCHNL_VLAN_TOGGLE)) 1196 ethertype = &vlan_strip.outer_ethertype_setting; 1197 else if ((stripping_caps->inner & VIRTCHNL_VLAN_ETHERTYPE_8100) && 1198 (stripping_caps->inner & VIRTCHNL_VLAN_TOGGLE)) 1199 ethertype = &vlan_strip.inner_ethertype_setting; 1200 else 1201 return -ENOTSUP; 1202 1203 memset(&vlan_strip, 0, sizeof(vlan_strip)); 1204 vlan_strip.vport_id = hw->vsi_res->vsi_id; 1205 *ethertype = VIRTCHNL_VLAN_ETHERTYPE_8100; 1206 1207 memset(&args, 0, sizeof(args)); 1208 args.v_op = enable ? VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2 : 1209 VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2; 1210 args.req_msg = (uint8_t *)&vlan_strip; 1211 args.req_msglen = sizeof(vlan_strip); 1212 ret = ice_dcf_execute_virtchnl_cmd(hw, &args); 1213 if (ret) 1214 PMD_DRV_LOG(ERR, "fail to execute command %s", 1215 enable ? "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2" : 1216 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2"); 1217 1218 return ret; 1219 } 1220 1221 static int 1222 dcf_dev_vlan_offload_set_v2(struct rte_eth_dev *dev, int mask) 1223 { 1224 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1225 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1226 struct ice_dcf_hw *hw = &adapter->real_hw; 1227 bool enable; 1228 int err; 1229 1230 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1231 enable = !!(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER); 1232 1233 dcf_iterate_vlan_filters_v2(dev, enable); 1234 } 1235 1236 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1237 enable = !!(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP); 1238 1239 err = dcf_config_vlan_strip_v2(hw, enable); 1240 /* If not support, the stripping is already disabled by PF */ 1241 if (err == -ENOTSUP && !enable) 1242 err = 0; 1243 if (err) 1244 return -EIO; 1245 } 1246 1247 return 0; 1248 } 1249 1250 static int 1251 dcf_enable_vlan_strip(struct ice_dcf_hw *hw) 1252 { 1253 struct dcf_virtchnl_cmd args; 1254 int ret; 1255 1256 memset(&args, 0, sizeof(args)); 1257 args.v_op = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING; 1258 ret = ice_dcf_execute_virtchnl_cmd(hw, &args); 1259 if (ret) 1260 PMD_DRV_LOG(ERR, 1261 "Failed to execute command of OP_ENABLE_VLAN_STRIPPING"); 1262 1263 return ret; 1264 } 1265 1266 static int 1267 dcf_disable_vlan_strip(struct ice_dcf_hw *hw) 1268 { 1269 struct dcf_virtchnl_cmd args; 1270 int ret; 1271 1272 memset(&args, 0, sizeof(args)); 1273 args.v_op = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING; 1274 ret = ice_dcf_execute_virtchnl_cmd(hw, &args); 1275 if (ret) 1276 PMD_DRV_LOG(ERR, 1277 "Failed to execute command of OP_DISABLE_VLAN_STRIPPING"); 1278 1279 return ret; 1280 } 1281 1282 static int 1283 dcf_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1284 { 1285 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1286 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1287 struct ice_dcf_hw *hw = &adapter->real_hw; 1288 int err; 1289 1290 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) 1291 return dcf_dev_vlan_offload_set_v2(dev, mask); 1292 1293 if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN)) 1294 return -ENOTSUP; 1295 1296 /* Vlan stripping setting */ 1297 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1298 /* Enable or disable VLAN stripping */ 1299 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 1300 err = dcf_enable_vlan_strip(hw); 1301 else 1302 err = dcf_disable_vlan_strip(hw); 1303 1304 if (err) 1305 return -EIO; 1306 } 1307 return 0; 1308 } 1309 1310 static int 1311 ice_dcf_dev_flow_ops_get(struct rte_eth_dev *dev, 1312 const struct rte_flow_ops **ops) 1313 { 1314 if (!dev) 1315 return -EINVAL; 1316 1317 *ops = &ice_flow_ops; 1318 return 0; 1319 } 1320 1321 static int 1322 ice_dcf_dev_rss_reta_update(struct rte_eth_dev *dev, 1323 struct rte_eth_rss_reta_entry64 *reta_conf, 1324 uint16_t reta_size) 1325 { 1326 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1327 struct ice_dcf_hw *hw = &adapter->real_hw; 1328 uint8_t *lut; 1329 uint16_t i, idx, shift; 1330 int ret; 1331 1332 if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) 1333 return -ENOTSUP; 1334 1335 if (reta_size != hw->vf_res->rss_lut_size) { 1336 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 1337 "(%d) doesn't match the number of hardware can " 1338 "support (%d)", reta_size, hw->vf_res->rss_lut_size); 1339 return -EINVAL; 1340 } 1341 1342 lut = rte_zmalloc("rss_lut", reta_size, 0); 1343 if (!lut) { 1344 PMD_DRV_LOG(ERR, "No memory can be allocated"); 1345 return -ENOMEM; 1346 } 1347 /* store the old lut table temporarily */ 1348 rte_memcpy(lut, hw->rss_lut, reta_size); 1349 1350 for (i = 0; i < reta_size; i++) { 1351 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1352 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1353 if (reta_conf[idx].mask & (1ULL << shift)) 1354 lut[i] = reta_conf[idx].reta[shift]; 1355 } 1356 1357 rte_memcpy(hw->rss_lut, lut, reta_size); 1358 /* send virtchnnl ops to configure rss*/ 1359 ret = ice_dcf_configure_rss_lut(hw); 1360 if (ret) /* revert back */ 1361 rte_memcpy(hw->rss_lut, lut, reta_size); 1362 rte_free(lut); 1363 1364 return ret; 1365 } 1366 1367 static int 1368 ice_dcf_dev_rss_reta_query(struct rte_eth_dev *dev, 1369 struct rte_eth_rss_reta_entry64 *reta_conf, 1370 uint16_t reta_size) 1371 { 1372 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1373 struct ice_dcf_hw *hw = &adapter->real_hw; 1374 uint16_t i, idx, shift; 1375 1376 if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) 1377 return -ENOTSUP; 1378 1379 if (reta_size != hw->vf_res->rss_lut_size) { 1380 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 1381 "(%d) doesn't match the number of hardware can " 1382 "support (%d)", reta_size, hw->vf_res->rss_lut_size); 1383 return -EINVAL; 1384 } 1385 1386 for (i = 0; i < reta_size; i++) { 1387 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1388 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1389 if (reta_conf[idx].mask & (1ULL << shift)) 1390 reta_conf[idx].reta[shift] = hw->rss_lut[i]; 1391 } 1392 1393 return 0; 1394 } 1395 1396 static int 1397 ice_dcf_dev_rss_hash_update(struct rte_eth_dev *dev, 1398 struct rte_eth_rss_conf *rss_conf) 1399 { 1400 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1401 struct ice_dcf_hw *hw = &adapter->real_hw; 1402 int ret; 1403 1404 if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) 1405 return -ENOTSUP; 1406 1407 /* HENA setting, it is enabled by default, no change */ 1408 if (!rss_conf->rss_key || rss_conf->rss_key_len == 0) { 1409 PMD_DRV_LOG(DEBUG, "No key to be configured"); 1410 return 0; 1411 } else if (rss_conf->rss_key_len != hw->vf_res->rss_key_size) { 1412 PMD_DRV_LOG(ERR, "The size of hash key configured " 1413 "(%d) doesn't match the size of hardware can " 1414 "support (%d)", rss_conf->rss_key_len, 1415 hw->vf_res->rss_key_size); 1416 return -EINVAL; 1417 } 1418 1419 rte_memcpy(hw->rss_key, rss_conf->rss_key, rss_conf->rss_key_len); 1420 1421 ret = ice_dcf_configure_rss_key(hw); 1422 if (ret) 1423 return ret; 1424 1425 /* Clear existing RSS. */ 1426 ret = ice_dcf_set_hena(hw, 0); 1427 1428 /* It is a workaround, temporarily allow error to be returned 1429 * due to possible lack of PF handling for hena = 0. 1430 */ 1431 if (ret) 1432 PMD_DRV_LOG(WARNING, "fail to clean existing RSS," 1433 "lack PF support"); 1434 1435 /* Set new RSS configuration. */ 1436 ret = ice_dcf_rss_hash_set(hw, rss_conf->rss_hf, true); 1437 if (ret) { 1438 PMD_DRV_LOG(ERR, "fail to set new RSS"); 1439 return ret; 1440 } 1441 1442 return 0; 1443 } 1444 1445 static int 1446 ice_dcf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1447 struct rte_eth_rss_conf *rss_conf) 1448 { 1449 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1450 struct ice_dcf_hw *hw = &adapter->real_hw; 1451 1452 if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) 1453 return -ENOTSUP; 1454 1455 /* Just set it to default value now. */ 1456 rss_conf->rss_hf = ICE_RSS_OFFLOAD_ALL; 1457 1458 if (!rss_conf->rss_key) 1459 return 0; 1460 1461 rss_conf->rss_key_len = hw->vf_res->rss_key_size; 1462 rte_memcpy(rss_conf->rss_key, hw->rss_key, rss_conf->rss_key_len); 1463 1464 return 0; 1465 } 1466 1467 #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4) 1468 #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6) 1469 #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t) 1470 1471 static void 1472 ice_dcf_stat_update_48(uint64_t *offset, uint64_t *stat) 1473 { 1474 if (*stat >= *offset) 1475 *stat = *stat - *offset; 1476 else 1477 *stat = (uint64_t)((*stat + 1478 ((uint64_t)1 << ICE_DCF_48_BIT_WIDTH)) - *offset); 1479 1480 *stat &= ICE_DCF_48_BIT_MASK; 1481 } 1482 1483 static void 1484 ice_dcf_stat_update_32(uint64_t *offset, uint64_t *stat) 1485 { 1486 if (*stat >= *offset) 1487 *stat = (uint64_t)(*stat - *offset); 1488 else 1489 *stat = (uint64_t)((*stat + 1490 ((uint64_t)1 << ICE_DCF_32_BIT_WIDTH)) - *offset); 1491 } 1492 1493 static void 1494 ice_dcf_update_stats(struct virtchnl_eth_stats *oes, 1495 struct virtchnl_eth_stats *nes) 1496 { 1497 ice_dcf_stat_update_48(&oes->rx_bytes, &nes->rx_bytes); 1498 ice_dcf_stat_update_48(&oes->rx_unicast, &nes->rx_unicast); 1499 ice_dcf_stat_update_48(&oes->rx_multicast, &nes->rx_multicast); 1500 ice_dcf_stat_update_48(&oes->rx_broadcast, &nes->rx_broadcast); 1501 ice_dcf_stat_update_32(&oes->rx_discards, &nes->rx_discards); 1502 ice_dcf_stat_update_48(&oes->tx_bytes, &nes->tx_bytes); 1503 ice_dcf_stat_update_48(&oes->tx_unicast, &nes->tx_unicast); 1504 ice_dcf_stat_update_48(&oes->tx_multicast, &nes->tx_multicast); 1505 ice_dcf_stat_update_48(&oes->tx_broadcast, &nes->tx_broadcast); 1506 ice_dcf_stat_update_32(&oes->tx_errors, &nes->tx_errors); 1507 ice_dcf_stat_update_32(&oes->tx_discards, &nes->tx_discards); 1508 } 1509 1510 1511 static int 1512 ice_dcf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1513 { 1514 struct ice_dcf_adapter *ad = dev->data->dev_private; 1515 struct ice_dcf_hw *hw = &ad->real_hw; 1516 struct virtchnl_eth_stats pstats; 1517 int ret; 1518 1519 if (hw->resetting) { 1520 PMD_DRV_LOG(ERR, 1521 "The DCF has been reset by PF, please reinit first"); 1522 return -EIO; 1523 } 1524 1525 ret = ice_dcf_query_stats(hw, &pstats); 1526 if (ret == 0) { 1527 ice_dcf_update_stats(&hw->eth_stats_offset, &pstats); 1528 stats->ipackets = pstats.rx_unicast + pstats.rx_multicast + 1529 pstats.rx_broadcast - pstats.rx_discards; 1530 stats->opackets = pstats.tx_broadcast + pstats.tx_multicast + 1531 pstats.tx_unicast; 1532 stats->imissed = pstats.rx_discards; 1533 stats->oerrors = pstats.tx_errors + pstats.tx_discards; 1534 stats->ibytes = pstats.rx_bytes; 1535 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN; 1536 stats->obytes = pstats.tx_bytes; 1537 } else { 1538 PMD_DRV_LOG(ERR, "Get statistics failed"); 1539 } 1540 return ret; 1541 } 1542 1543 static int 1544 ice_dcf_stats_reset(struct rte_eth_dev *dev) 1545 { 1546 struct ice_dcf_adapter *ad = dev->data->dev_private; 1547 struct ice_dcf_hw *hw = &ad->real_hw; 1548 struct virtchnl_eth_stats pstats; 1549 int ret; 1550 1551 if (hw->resetting) 1552 return 0; 1553 1554 /* read stat values to clear hardware registers */ 1555 ret = ice_dcf_query_stats(hw, &pstats); 1556 if (ret != 0) 1557 return ret; 1558 1559 /* set stats offset base on current values */ 1560 hw->eth_stats_offset = pstats; 1561 1562 return 0; 1563 } 1564 1565 static int ice_dcf_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1566 struct rte_eth_xstat_name *xstats_names, 1567 __rte_unused unsigned int limit) 1568 { 1569 unsigned int i; 1570 1571 if (xstats_names != NULL) 1572 for (i = 0; i < ICE_DCF_NB_XSTATS; i++) { 1573 snprintf(xstats_names[i].name, 1574 sizeof(xstats_names[i].name), 1575 "%s", rte_ice_dcf_stats_strings[i].name); 1576 } 1577 return ICE_DCF_NB_XSTATS; 1578 } 1579 1580 static int ice_dcf_xstats_get(struct rte_eth_dev *dev, 1581 struct rte_eth_xstat *xstats, unsigned int n) 1582 { 1583 int ret; 1584 unsigned int i; 1585 struct ice_dcf_adapter *adapter = 1586 ICE_DCF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1587 struct ice_dcf_hw *hw = &adapter->real_hw; 1588 struct virtchnl_eth_stats *postats = &hw->eth_stats_offset; 1589 struct virtchnl_eth_stats pnstats; 1590 1591 if (n < ICE_DCF_NB_XSTATS) 1592 return ICE_DCF_NB_XSTATS; 1593 1594 ret = ice_dcf_query_stats(hw, &pnstats); 1595 if (ret != 0) 1596 return 0; 1597 1598 if (!xstats) 1599 return 0; 1600 1601 ice_dcf_update_stats(postats, &pnstats); 1602 1603 /* loop over xstats array and values from pstats */ 1604 for (i = 0; i < ICE_DCF_NB_XSTATS; i++) { 1605 xstats[i].id = i; 1606 xstats[i].value = *(uint64_t *)(((char *)&pnstats) + 1607 rte_ice_dcf_stats_strings[i].offset); 1608 } 1609 1610 return ICE_DCF_NB_XSTATS; 1611 } 1612 1613 static void 1614 ice_dcf_free_repr_info(struct ice_dcf_adapter *dcf_adapter) 1615 { 1616 if (dcf_adapter->repr_infos) { 1617 rte_free(dcf_adapter->repr_infos); 1618 dcf_adapter->repr_infos = NULL; 1619 } 1620 } 1621 1622 int 1623 ice_dcf_handle_vf_repr_close(struct ice_dcf_adapter *dcf_adapter, 1624 uint16_t vf_id) 1625 { 1626 struct ice_dcf_repr_info *vf_rep_info; 1627 1628 if (dcf_adapter->num_reprs >= vf_id) { 1629 PMD_DRV_LOG(ERR, "Invalid VF id: %d", vf_id); 1630 return -1; 1631 } 1632 1633 if (!dcf_adapter->repr_infos) 1634 return 0; 1635 1636 vf_rep_info = &dcf_adapter->repr_infos[vf_id]; 1637 vf_rep_info->vf_rep_eth_dev = NULL; 1638 1639 return 0; 1640 } 1641 1642 static int 1643 ice_dcf_init_repr_info(struct ice_dcf_adapter *dcf_adapter) 1644 { 1645 dcf_adapter->repr_infos = 1646 rte_calloc("ice_dcf_rep_info", 1647 dcf_adapter->real_hw.num_vfs, 1648 sizeof(dcf_adapter->repr_infos[0]), 0); 1649 if (!dcf_adapter->repr_infos) { 1650 PMD_DRV_LOG(ERR, "Failed to alloc memory for VF representors"); 1651 return -ENOMEM; 1652 } 1653 1654 return 0; 1655 } 1656 1657 static int 1658 ice_dcf_dev_close(struct rte_eth_dev *dev) 1659 { 1660 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1661 1662 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1663 return 0; 1664 1665 ice_dcf_vf_repr_notify_all(adapter, false); 1666 (void)ice_dcf_dev_stop(dev); 1667 1668 ice_free_queues(dev); 1669 ice_dcf_uninit_parent_adapter(dev); 1670 ice_dcf_uninit_hw(dev, &adapter->real_hw); 1671 1672 return 0; 1673 } 1674 1675 int 1676 ice_dcf_link_update(struct rte_eth_dev *dev, 1677 __rte_unused int wait_to_complete) 1678 { 1679 struct ice_dcf_adapter *ad = dev->data->dev_private; 1680 struct ice_dcf_hw *hw = &ad->real_hw; 1681 struct rte_eth_link new_link; 1682 1683 memset(&new_link, 0, sizeof(new_link)); 1684 1685 /* Only read status info stored in VF, and the info is updated 1686 * when receive LINK_CHANGE event from PF by virtchnl. 1687 */ 1688 switch (hw->link_speed) { 1689 case 10: 1690 new_link.link_speed = RTE_ETH_SPEED_NUM_10M; 1691 break; 1692 case 100: 1693 new_link.link_speed = RTE_ETH_SPEED_NUM_100M; 1694 break; 1695 case 1000: 1696 new_link.link_speed = RTE_ETH_SPEED_NUM_1G; 1697 break; 1698 case 10000: 1699 new_link.link_speed = RTE_ETH_SPEED_NUM_10G; 1700 break; 1701 case 20000: 1702 new_link.link_speed = RTE_ETH_SPEED_NUM_20G; 1703 break; 1704 case 25000: 1705 new_link.link_speed = RTE_ETH_SPEED_NUM_25G; 1706 break; 1707 case 40000: 1708 new_link.link_speed = RTE_ETH_SPEED_NUM_40G; 1709 break; 1710 case 50000: 1711 new_link.link_speed = RTE_ETH_SPEED_NUM_50G; 1712 break; 1713 case 100000: 1714 new_link.link_speed = RTE_ETH_SPEED_NUM_100G; 1715 break; 1716 default: 1717 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE; 1718 break; 1719 } 1720 1721 new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 1722 new_link.link_status = hw->link_up ? RTE_ETH_LINK_UP : 1723 RTE_ETH_LINK_DOWN; 1724 new_link.link_autoneg = !(dev->data->dev_conf.link_speeds & 1725 RTE_ETH_LINK_SPEED_FIXED); 1726 1727 return rte_eth_linkstatus_set(dev, &new_link); 1728 } 1729 1730 static int 1731 ice_dcf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu __rte_unused) 1732 { 1733 /* mtu setting is forbidden if port is start */ 1734 if (dev->data->dev_started != 0) { 1735 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 1736 dev->data->port_id); 1737 return -EBUSY; 1738 } 1739 1740 return 0; 1741 } 1742 1743 bool 1744 ice_dcf_adminq_need_retry(struct ice_adapter *ad) 1745 { 1746 return ad->hw.dcf_enabled && 1747 !rte_atomic_load_explicit(&ad->dcf_state_on, rte_memory_order_relaxed); 1748 } 1749 1750 /* Add UDP tunneling port */ 1751 static int 1752 ice_dcf_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 1753 struct rte_eth_udp_tunnel *udp_tunnel) 1754 { 1755 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1756 struct ice_adapter *parent_adapter = &adapter->parent; 1757 struct ice_hw *parent_hw = &parent_adapter->hw; 1758 int ret = 0; 1759 1760 if (!udp_tunnel) 1761 return -EINVAL; 1762 1763 switch (udp_tunnel->prot_type) { 1764 case RTE_ETH_TUNNEL_TYPE_VXLAN: 1765 ret = ice_create_tunnel(parent_hw, TNL_VXLAN, 1766 udp_tunnel->udp_port); 1767 break; 1768 case RTE_ETH_TUNNEL_TYPE_ECPRI: 1769 ret = ice_create_tunnel(parent_hw, TNL_ECPRI, 1770 udp_tunnel->udp_port); 1771 break; 1772 default: 1773 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 1774 ret = -EINVAL; 1775 break; 1776 } 1777 1778 return ret; 1779 } 1780 1781 /* Delete UDP tunneling port */ 1782 static int 1783 ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 1784 struct rte_eth_udp_tunnel *udp_tunnel) 1785 { 1786 struct ice_dcf_adapter *adapter = dev->data->dev_private; 1787 struct ice_adapter *parent_adapter = &adapter->parent; 1788 struct ice_hw *parent_hw = &parent_adapter->hw; 1789 int ret = 0; 1790 1791 if (!udp_tunnel) 1792 return -EINVAL; 1793 1794 switch (udp_tunnel->prot_type) { 1795 case RTE_ETH_TUNNEL_TYPE_VXLAN: 1796 case RTE_ETH_TUNNEL_TYPE_ECPRI: 1797 ret = ice_destroy_tunnel(parent_hw, udp_tunnel->udp_port, 0); 1798 break; 1799 default: 1800 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 1801 ret = -EINVAL; 1802 break; 1803 } 1804 1805 return ret; 1806 } 1807 1808 static int 1809 ice_dcf_tm_ops_get(struct rte_eth_dev *dev __rte_unused, 1810 void *arg) 1811 { 1812 if (!arg) 1813 return -EINVAL; 1814 1815 *(const void **)arg = &ice_dcf_tm_ops; 1816 1817 return 0; 1818 } 1819 1820 static inline void 1821 ice_dcf_reset_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) 1822 { 1823 ice_dcf_uninit_hw(eth_dev, hw); 1824 ice_dcf_init_hw(eth_dev, hw); 1825 } 1826 1827 /* Check if reset has been triggered by PF */ 1828 static inline bool 1829 ice_dcf_is_reset(struct rte_eth_dev *dev) 1830 { 1831 struct ice_dcf_adapter *ad = dev->data->dev_private; 1832 struct iavf_hw *hw = &ad->real_hw.avf; 1833 1834 return !(IAVF_READ_REG(hw, IAVF_VF_ARQLEN1) & 1835 IAVF_VF_ARQLEN1_ARQENABLE_MASK); 1836 } 1837 1838 static int 1839 ice_dcf_dev_reset(struct rte_eth_dev *dev) 1840 { 1841 struct ice_dcf_adapter *ad = dev->data->dev_private; 1842 struct ice_dcf_hw *hw = &ad->real_hw; 1843 int ret; 1844 1845 if (ice_dcf_is_reset(dev)) { 1846 if (!ad->real_hw.resetting) 1847 ad->real_hw.resetting = true; 1848 PMD_DRV_LOG(ERR, "The DCF has been reset by PF"); 1849 1850 /* 1851 * Simply reset hw to trigger an additional DCF enable/disable 1852 * cycle which help to workaround the issue that kernel driver 1853 * may not clean up resource during previous reset. 1854 */ 1855 ice_dcf_reset_hw(dev, hw); 1856 } 1857 1858 ret = ice_dcf_dev_close(dev); 1859 if (ret) 1860 return ret; 1861 1862 ret = ice_dcf_dev_init(dev); 1863 1864 return ret; 1865 } 1866 1867 static const uint32_t * 1868 ice_dcf_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused, 1869 size_t *no_of_elements) 1870 { 1871 static const uint32_t ptypes[] = { 1872 RTE_PTYPE_L2_ETHER, 1873 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1874 RTE_PTYPE_L4_FRAG, 1875 RTE_PTYPE_L4_ICMP, 1876 RTE_PTYPE_L4_NONFRAG, 1877 RTE_PTYPE_L4_SCTP, 1878 RTE_PTYPE_L4_TCP, 1879 RTE_PTYPE_L4_UDP, 1880 }; 1881 *no_of_elements = RTE_DIM(ptypes); 1882 return ptypes; 1883 } 1884 1885 static const struct eth_dev_ops ice_dcf_eth_dev_ops = { 1886 .dev_start = ice_dcf_dev_start, 1887 .dev_stop = ice_dcf_dev_stop, 1888 .dev_close = ice_dcf_dev_close, 1889 .dev_reset = ice_dcf_dev_reset, 1890 .dev_configure = ice_dcf_dev_configure, 1891 .dev_infos_get = ice_dcf_dev_info_get, 1892 .dev_supported_ptypes_get = ice_dcf_dev_supported_ptypes_get, 1893 .rx_queue_setup = ice_rx_queue_setup, 1894 .tx_queue_setup = ice_tx_queue_setup, 1895 .rx_queue_release = ice_dev_rx_queue_release, 1896 .tx_queue_release = ice_dev_tx_queue_release, 1897 .rx_queue_start = ice_dcf_rx_queue_start, 1898 .tx_queue_start = ice_dcf_tx_queue_start, 1899 .rx_queue_stop = ice_dcf_rx_queue_stop, 1900 .tx_queue_stop = ice_dcf_tx_queue_stop, 1901 .rxq_info_get = ice_rxq_info_get, 1902 .txq_info_get = ice_txq_info_get, 1903 .get_monitor_addr = ice_get_monitor_addr, 1904 .link_update = ice_dcf_link_update, 1905 .stats_get = ice_dcf_stats_get, 1906 .stats_reset = ice_dcf_stats_reset, 1907 .xstats_get = ice_dcf_xstats_get, 1908 .xstats_get_names = ice_dcf_xstats_get_names, 1909 .xstats_reset = ice_dcf_stats_reset, 1910 .promiscuous_enable = ice_dcf_dev_promiscuous_enable, 1911 .promiscuous_disable = ice_dcf_dev_promiscuous_disable, 1912 .allmulticast_enable = ice_dcf_dev_allmulticast_enable, 1913 .allmulticast_disable = ice_dcf_dev_allmulticast_disable, 1914 .mac_addr_add = dcf_dev_add_mac_addr, 1915 .mac_addr_remove = dcf_dev_del_mac_addr, 1916 .set_mc_addr_list = dcf_set_mc_addr_list, 1917 .mac_addr_set = dcf_dev_set_default_mac_addr, 1918 .vlan_filter_set = dcf_dev_vlan_filter_set, 1919 .vlan_offload_set = dcf_dev_vlan_offload_set, 1920 .flow_ops_get = ice_dcf_dev_flow_ops_get, 1921 .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add, 1922 .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del, 1923 .tm_ops_get = ice_dcf_tm_ops_get, 1924 .reta_update = ice_dcf_dev_rss_reta_update, 1925 .reta_query = ice_dcf_dev_rss_reta_query, 1926 .rss_hash_update = ice_dcf_dev_rss_hash_update, 1927 .rss_hash_conf_get = ice_dcf_dev_rss_hash_conf_get, 1928 .tx_done_cleanup = ice_tx_done_cleanup, 1929 .mtu_set = ice_dcf_dev_mtu_set, 1930 }; 1931 1932 static int 1933 ice_dcf_dev_init(struct rte_eth_dev *eth_dev) 1934 { 1935 struct ice_dcf_adapter *adapter = eth_dev->data->dev_private; 1936 struct ice_adapter *parent_adapter = &adapter->parent; 1937 1938 eth_dev->dev_ops = &ice_dcf_eth_dev_ops; 1939 eth_dev->rx_pkt_burst = ice_dcf_recv_pkts; 1940 eth_dev->tx_pkt_burst = ice_dcf_xmit_pkts; 1941 1942 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1943 return 0; 1944 1945 adapter->real_hw.vc_event_msg_cb = ice_dcf_handle_pf_event_msg; 1946 if (ice_dcf_init_hw(eth_dev, &adapter->real_hw) != 0) { 1947 PMD_INIT_LOG(ERR, "Failed to init DCF hardware"); 1948 rte_atomic_store_explicit(&parent_adapter->dcf_state_on, false, 1949 rte_memory_order_relaxed); 1950 return -1; 1951 } 1952 1953 rte_atomic_store_explicit(&parent_adapter->dcf_state_on, true, rte_memory_order_relaxed); 1954 1955 if (ice_dcf_init_parent_adapter(eth_dev) != 0) { 1956 PMD_INIT_LOG(ERR, "Failed to init DCF parent adapter"); 1957 ice_dcf_uninit_hw(eth_dev, &adapter->real_hw); 1958 return -1; 1959 } 1960 1961 ice_dcf_stats_reset(eth_dev); 1962 1963 dcf_config_promisc(adapter, false, false); 1964 ice_dcf_vf_repr_notify_all(adapter, true); 1965 1966 return 0; 1967 } 1968 1969 static int 1970 ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev) 1971 { 1972 struct ice_dcf_adapter *adapter = eth_dev->data->dev_private; 1973 1974 ice_dcf_free_repr_info(adapter); 1975 ice_dcf_dev_close(eth_dev); 1976 1977 return 0; 1978 } 1979 1980 static int 1981 ice_dcf_engine_disabled_handler(__rte_unused const char *key, 1982 const char *value, __rte_unused void *opaque) 1983 { 1984 if (strcmp(value, "off")) 1985 return -1; 1986 1987 return 0; 1988 } 1989 1990 static int 1991 ice_dcf_cap_check_handler(__rte_unused const char *key, 1992 const char *value, __rte_unused void *opaque) 1993 { 1994 if (strcmp(value, "dcf")) 1995 return -1; 1996 1997 return 0; 1998 } 1999 2000 int 2001 ice_devargs_check(struct rte_devargs *devargs, enum ice_dcf_devrarg devarg_type) 2002 { 2003 struct rte_kvargs *kvlist; 2004 unsigned int i = 0; 2005 int ret = 0; 2006 2007 if (devargs == NULL) 2008 return 0; 2009 2010 kvlist = rte_kvargs_parse(devargs->args, NULL); 2011 if (kvlist == NULL) 2012 return 0; 2013 2014 for (i = 0; i < ARRAY_SIZE(ice_devargs_table); i++) { 2015 if (devarg_type == ice_devargs_table[i].type) { 2016 if (!rte_kvargs_count(kvlist, ice_devargs_table[i].key)) 2017 goto exit; 2018 2019 if (rte_kvargs_process(kvlist, ice_devargs_table[i].key, 2020 ice_devargs_table[i].handler, NULL) < 0) 2021 goto exit; 2022 ret = 1; 2023 break; 2024 } 2025 } 2026 exit: 2027 rte_kvargs_free(kvlist); 2028 return ret; 2029 } 2030 2031 static int 2032 eth_ice_dcf_pci_probe(__rte_unused struct rte_pci_driver *pci_drv, 2033 struct rte_pci_device *pci_dev) 2034 { 2035 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 2036 struct ice_dcf_vf_repr_param repr_param; 2037 char repr_name[RTE_ETH_NAME_MAX_LEN]; 2038 struct ice_dcf_adapter *dcf_adapter; 2039 struct rte_eth_dev *dcf_ethdev; 2040 uint16_t dcf_vsi_id; 2041 int i, ret; 2042 2043 if (!ice_devargs_check(pci_dev->device.devargs, ICE_DCF_DEVARG_CAP)) 2044 return 1; 2045 2046 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, ð_da, 1); 2047 if (ret < 0) 2048 return ret; 2049 2050 ret = rte_eth_dev_pci_generic_probe(pci_dev, 2051 sizeof(struct ice_dcf_adapter), 2052 ice_dcf_dev_init); 2053 if (ret || !eth_da.nb_representor_ports) 2054 return ret; 2055 if (eth_da.type != RTE_ETH_REPRESENTOR_VF) 2056 return -ENOTSUP; 2057 2058 dcf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 2059 if (dcf_ethdev == NULL) 2060 return -ENODEV; 2061 2062 dcf_adapter = dcf_ethdev->data->dev_private; 2063 ret = ice_dcf_init_repr_info(dcf_adapter); 2064 if (ret) 2065 return ret; 2066 2067 if (eth_da.nb_representor_ports > dcf_adapter->real_hw.num_vfs || 2068 eth_da.nb_representor_ports >= RTE_MAX_ETHPORTS) { 2069 PMD_DRV_LOG(ERR, "the number of port representors is too large: %u", 2070 eth_da.nb_representor_ports); 2071 ice_dcf_free_repr_info(dcf_adapter); 2072 return -EINVAL; 2073 } 2074 2075 dcf_vsi_id = dcf_adapter->real_hw.vsi_id | VIRTCHNL_DCF_VF_VSI_VALID; 2076 2077 repr_param.dcf_eth_dev = dcf_ethdev; 2078 repr_param.switch_domain_id = 0; 2079 2080 for (i = 0; i < eth_da.nb_representor_ports; i++) { 2081 uint16_t vf_id = eth_da.representor_ports[i]; 2082 struct rte_eth_dev *vf_rep_eth_dev; 2083 2084 if (vf_id >= dcf_adapter->real_hw.num_vfs) { 2085 PMD_DRV_LOG(ERR, "VF ID %u is out of range (0 ~ %u)", 2086 vf_id, dcf_adapter->real_hw.num_vfs - 1); 2087 ret = -EINVAL; 2088 break; 2089 } 2090 2091 if (dcf_adapter->real_hw.vf_vsi_map[vf_id] == dcf_vsi_id) { 2092 PMD_DRV_LOG(ERR, "VF ID %u is DCF's ID.", vf_id); 2093 ret = -EINVAL; 2094 break; 2095 } 2096 2097 repr_param.vf_id = vf_id; 2098 snprintf(repr_name, sizeof(repr_name), "net_%s_representor_%u", 2099 pci_dev->device.name, vf_id); 2100 ret = rte_eth_dev_create(&pci_dev->device, repr_name, 2101 sizeof(struct ice_dcf_vf_repr), 2102 NULL, NULL, ice_dcf_vf_repr_init, 2103 &repr_param); 2104 if (ret) { 2105 PMD_DRV_LOG(ERR, "failed to create DCF VF representor %s", 2106 repr_name); 2107 break; 2108 } 2109 2110 vf_rep_eth_dev = rte_eth_dev_allocated(repr_name); 2111 if (!vf_rep_eth_dev) { 2112 PMD_DRV_LOG(ERR, 2113 "Failed to find the ethdev for DCF VF representor: %s", 2114 repr_name); 2115 ret = -ENODEV; 2116 break; 2117 } 2118 2119 dcf_adapter->repr_infos[vf_id].vf_rep_eth_dev = vf_rep_eth_dev; 2120 dcf_adapter->num_reprs++; 2121 } 2122 2123 return ret; 2124 } 2125 2126 static int 2127 eth_ice_dcf_pci_remove(struct rte_pci_device *pci_dev) 2128 { 2129 struct rte_eth_dev *eth_dev; 2130 2131 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 2132 if (!eth_dev) 2133 return 0; 2134 2135 if (rte_eth_dev_is_repr(eth_dev)) 2136 return rte_eth_dev_pci_generic_remove(pci_dev, 2137 ice_dcf_vf_repr_uninit); 2138 else 2139 return rte_eth_dev_pci_generic_remove(pci_dev, 2140 ice_dcf_dev_uninit); 2141 } 2142 2143 static const struct rte_pci_id pci_id_ice_dcf_map[] = { 2144 { RTE_PCI_DEVICE(IAVF_INTEL_VENDOR_ID, IAVF_DEV_ID_ADAPTIVE_VF) }, 2145 { .vendor_id = 0, /* sentinel */ }, 2146 }; 2147 2148 static struct rte_pci_driver rte_ice_dcf_pmd = { 2149 .id_table = pci_id_ice_dcf_map, 2150 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2151 .probe = eth_ice_dcf_pci_probe, 2152 .remove = eth_ice_dcf_pci_remove, 2153 }; 2154 2155 RTE_PMD_REGISTER_PCI(net_ice_dcf, rte_ice_dcf_pmd); 2156 RTE_PMD_REGISTER_PCI_TABLE(net_ice_dcf, pci_id_ice_dcf_map); 2157 RTE_PMD_REGISTER_KMOD_DEP(net_ice_dcf, "* igb_uio | vfio-pci"); 2158 RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf"); 2159