1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <rte_bus_pci.h> 6 #include <rte_common.h> 7 #include <rte_cycles.h> 8 #include <rte_geneve.h> 9 #include <rte_vxlan.h> 10 #include <ethdev_driver.h> 11 #include <rte_io.h> 12 #include <rte_net.h> 13 #include <rte_malloc.h> 14 #if defined(RTE_ARCH_ARM64) 15 #include <rte_cpuflags.h> 16 #include <rte_vect.h> 17 #endif 18 19 #include "hns3_ethdev.h" 20 #include "hns3_rxtx.h" 21 #include "hns3_regs.h" 22 #include "hns3_logs.h" 23 #include "hns3_mp.h" 24 25 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1) 26 #define HNS3_RX_RING_PREFETCTH_MASK 3 27 28 static void 29 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq) 30 { 31 uint16_t i; 32 33 /* Note: Fake rx queue will not enter here */ 34 if (rxq->sw_ring == NULL) 35 return; 36 37 if (rxq->rx_rearm_nb == 0) { 38 for (i = 0; i < rxq->nb_rx_desc; i++) { 39 if (rxq->sw_ring[i].mbuf != NULL) { 40 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf); 41 rxq->sw_ring[i].mbuf = NULL; 42 } 43 } 44 } else { 45 for (i = rxq->next_to_use; 46 i != rxq->rx_rearm_start; 47 i = (i + 1) % rxq->nb_rx_desc) { 48 if (rxq->sw_ring[i].mbuf != NULL) { 49 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf); 50 rxq->sw_ring[i].mbuf = NULL; 51 } 52 } 53 } 54 55 for (i = 0; i < rxq->bulk_mbuf_num; i++) 56 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]); 57 rxq->bulk_mbuf_num = 0; 58 59 if (rxq->pkt_first_seg) { 60 rte_pktmbuf_free(rxq->pkt_first_seg); 61 rxq->pkt_first_seg = NULL; 62 } 63 } 64 65 static void 66 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq) 67 { 68 uint16_t i; 69 70 /* Note: Fake tx queue will not enter here */ 71 if (txq->sw_ring) { 72 for (i = 0; i < txq->nb_tx_desc; i++) { 73 if (txq->sw_ring[i].mbuf) { 74 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf); 75 txq->sw_ring[i].mbuf = NULL; 76 } 77 } 78 } 79 } 80 81 static void 82 hns3_rx_queue_release(void *queue) 83 { 84 struct hns3_rx_queue *rxq = queue; 85 if (rxq) { 86 hns3_rx_queue_release_mbufs(rxq); 87 if (rxq->mz) 88 rte_memzone_free(rxq->mz); 89 if (rxq->sw_ring) 90 rte_free(rxq->sw_ring); 91 rte_free(rxq); 92 } 93 } 94 95 static void 96 hns3_tx_queue_release(void *queue) 97 { 98 struct hns3_tx_queue *txq = queue; 99 if (txq) { 100 hns3_tx_queue_release_mbufs(txq); 101 if (txq->mz) 102 rte_memzone_free(txq->mz); 103 if (txq->sw_ring) 104 rte_free(txq->sw_ring); 105 if (txq->free) 106 rte_free(txq->free); 107 rte_free(txq); 108 } 109 } 110 111 static void 112 hns3_rx_queue_release_lock(void *queue) 113 { 114 struct hns3_rx_queue *rxq = queue; 115 struct hns3_adapter *hns; 116 117 if (rxq == NULL) 118 return; 119 120 hns = rxq->hns; 121 rte_spinlock_lock(&hns->hw.lock); 122 hns3_rx_queue_release(queue); 123 rte_spinlock_unlock(&hns->hw.lock); 124 } 125 126 void 127 hns3_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id) 128 { 129 hns3_rx_queue_release_lock(dev->data->rx_queues[queue_id]); 130 } 131 132 static void 133 hns3_tx_queue_release_lock(void *queue) 134 { 135 struct hns3_tx_queue *txq = queue; 136 struct hns3_adapter *hns; 137 138 if (txq == NULL) 139 return; 140 141 hns = txq->hns; 142 rte_spinlock_lock(&hns->hw.lock); 143 hns3_tx_queue_release(queue); 144 rte_spinlock_unlock(&hns->hw.lock); 145 } 146 147 void 148 hns3_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id) 149 { 150 hns3_tx_queue_release_lock(dev->data->tx_queues[queue_id]); 151 } 152 153 static void 154 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue) 155 { 156 struct hns3_rx_queue *rxq = queue; 157 struct hns3_adapter *hns; 158 struct hns3_hw *hw; 159 uint16_t idx; 160 161 if (rxq == NULL) 162 return; 163 164 hns = rxq->hns; 165 hw = &hns->hw; 166 idx = rxq->queue_id; 167 if (hw->fkq_data.rx_queues[idx]) { 168 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]); 169 hw->fkq_data.rx_queues[idx] = NULL; 170 } 171 172 /* free fake rx queue arrays */ 173 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) { 174 hw->fkq_data.nb_fake_rx_queues = 0; 175 rte_free(hw->fkq_data.rx_queues); 176 hw->fkq_data.rx_queues = NULL; 177 } 178 } 179 180 static void 181 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue) 182 { 183 struct hns3_tx_queue *txq = queue; 184 struct hns3_adapter *hns; 185 struct hns3_hw *hw; 186 uint16_t idx; 187 188 if (txq == NULL) 189 return; 190 191 hns = txq->hns; 192 hw = &hns->hw; 193 idx = txq->queue_id; 194 if (hw->fkq_data.tx_queues[idx]) { 195 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]); 196 hw->fkq_data.tx_queues[idx] = NULL; 197 } 198 199 /* free fake tx queue arrays */ 200 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) { 201 hw->fkq_data.nb_fake_tx_queues = 0; 202 rte_free(hw->fkq_data.tx_queues); 203 hw->fkq_data.tx_queues = NULL; 204 } 205 } 206 207 static void 208 hns3_free_rx_queues(struct rte_eth_dev *dev) 209 { 210 struct hns3_adapter *hns = dev->data->dev_private; 211 struct hns3_fake_queue_data *fkq_data; 212 struct hns3_hw *hw = &hns->hw; 213 uint16_t nb_rx_q; 214 uint16_t i; 215 216 nb_rx_q = hw->data->nb_rx_queues; 217 for (i = 0; i < nb_rx_q; i++) { 218 if (dev->data->rx_queues[i]) { 219 hns3_rx_queue_release(dev->data->rx_queues[i]); 220 dev->data->rx_queues[i] = NULL; 221 } 222 } 223 224 /* Free fake Rx queues */ 225 fkq_data = &hw->fkq_data; 226 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) { 227 if (fkq_data->rx_queues[i]) 228 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]); 229 } 230 } 231 232 static void 233 hns3_free_tx_queues(struct rte_eth_dev *dev) 234 { 235 struct hns3_adapter *hns = dev->data->dev_private; 236 struct hns3_fake_queue_data *fkq_data; 237 struct hns3_hw *hw = &hns->hw; 238 uint16_t nb_tx_q; 239 uint16_t i; 240 241 nb_tx_q = hw->data->nb_tx_queues; 242 for (i = 0; i < nb_tx_q; i++) { 243 if (dev->data->tx_queues[i]) { 244 hns3_tx_queue_release(dev->data->tx_queues[i]); 245 dev->data->tx_queues[i] = NULL; 246 } 247 } 248 249 /* Free fake Tx queues */ 250 fkq_data = &hw->fkq_data; 251 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) { 252 if (fkq_data->tx_queues[i]) 253 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]); 254 } 255 } 256 257 void 258 hns3_free_all_queues(struct rte_eth_dev *dev) 259 { 260 hns3_free_rx_queues(dev); 261 hns3_free_tx_queues(dev); 262 } 263 264 static int 265 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq) 266 { 267 struct rte_mbuf *mbuf; 268 uint64_t dma_addr; 269 uint16_t i; 270 271 for (i = 0; i < rxq->nb_rx_desc; i++) { 272 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool); 273 if (unlikely(mbuf == NULL)) { 274 hns3_err(hw, "Failed to allocate RXD[%u] for rx queue!", 275 i); 276 hns3_rx_queue_release_mbufs(rxq); 277 return -ENOMEM; 278 } 279 280 rte_mbuf_refcnt_set(mbuf, 1); 281 mbuf->next = NULL; 282 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 283 mbuf->nb_segs = 1; 284 mbuf->port = rxq->port_id; 285 286 rxq->sw_ring[i].mbuf = mbuf; 287 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); 288 rxq->rx_ring[i].addr = dma_addr; 289 rxq->rx_ring[i].rx.bd_base_info = 0; 290 } 291 292 return 0; 293 } 294 295 static int 296 hns3_buf_size2type(uint32_t buf_size) 297 { 298 int bd_size_type; 299 300 switch (buf_size) { 301 case 512: 302 bd_size_type = HNS3_BD_SIZE_512_TYPE; 303 break; 304 case 1024: 305 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 306 break; 307 case 4096: 308 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 309 break; 310 default: 311 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 312 } 313 314 return bd_size_type; 315 } 316 317 static void 318 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq) 319 { 320 uint32_t rx_buf_len = rxq->rx_buf_len; 321 uint64_t dma_addr = rxq->rx_ring_phys_addr; 322 323 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr); 324 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG, 325 (uint32_t)((dma_addr >> 31) >> 1)); 326 327 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG, 328 hns3_buf_size2type(rx_buf_len)); 329 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG, 330 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc)); 331 } 332 333 static void 334 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq) 335 { 336 uint64_t dma_addr = txq->tx_ring_phys_addr; 337 338 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr); 339 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG, 340 (uint32_t)((dma_addr >> 31) >> 1)); 341 342 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG, 343 HNS3_CFG_DESC_NUM(txq->nb_tx_desc)); 344 } 345 346 void 347 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw) 348 { 349 uint16_t nb_rx_q = hw->data->nb_rx_queues; 350 uint16_t nb_tx_q = hw->data->nb_tx_queues; 351 struct hns3_rx_queue *rxq; 352 struct hns3_tx_queue *txq; 353 bool pvid_en; 354 int i; 355 356 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE; 357 for (i = 0; i < hw->cfg_max_queues; i++) { 358 if (i < nb_rx_q) { 359 rxq = hw->data->rx_queues[i]; 360 if (rxq != NULL) 361 rxq->pvid_sw_discard_en = pvid_en; 362 } 363 if (i < nb_tx_q) { 364 txq = hw->data->tx_queues[i]; 365 if (txq != NULL) 366 txq->pvid_sw_shift_en = pvid_en; 367 } 368 } 369 } 370 371 static void 372 hns3_stop_unused_queue(void *tqp_base, enum hns3_ring_type queue_type) 373 { 374 uint32_t reg_offset; 375 uint32_t reg; 376 377 reg_offset = queue_type == HNS3_RING_TYPE_TX ? 378 HNS3_RING_TX_EN_REG : HNS3_RING_RX_EN_REG; 379 reg = hns3_read_reg(tqp_base, reg_offset); 380 reg &= ~BIT(HNS3_RING_EN_B); 381 hns3_write_reg(tqp_base, reg_offset, reg); 382 } 383 384 void 385 hns3_enable_all_queues(struct hns3_hw *hw, bool en) 386 { 387 uint16_t nb_rx_q = hw->data->nb_rx_queues; 388 uint16_t nb_tx_q = hw->data->nb_tx_queues; 389 struct hns3_rx_queue *rxq; 390 struct hns3_tx_queue *txq; 391 uint32_t rcb_reg; 392 void *tqp_base; 393 int i; 394 395 for (i = 0; i < hw->cfg_max_queues; i++) { 396 if (hns3_dev_get_support(hw, INDEP_TXRX)) { 397 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL; 398 txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL; 399 400 tqp_base = (void *)((char *)hw->io_base + 401 hns3_get_tqp_reg_offset(i)); 402 /* 403 * If queue struct is not initialized, it means the 404 * related HW ring has not been initialized yet. 405 * So, these queues should be disabled before enable 406 * the tqps to avoid a HW exception since the queues 407 * are enabled by default. 408 */ 409 if (rxq == NULL) 410 hns3_stop_unused_queue(tqp_base, 411 HNS3_RING_TYPE_RX); 412 if (txq == NULL) 413 hns3_stop_unused_queue(tqp_base, 414 HNS3_RING_TYPE_TX); 415 } else { 416 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : 417 hw->fkq_data.rx_queues[i - nb_rx_q]; 418 419 tqp_base = rxq->io_base; 420 } 421 /* 422 * This is the master switch that used to control the enabling 423 * of a pair of Tx and Rx queues. Both the Rx and Tx point to 424 * the same register 425 */ 426 rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG); 427 if (en) 428 rcb_reg |= BIT(HNS3_RING_EN_B); 429 else 430 rcb_reg &= ~BIT(HNS3_RING_EN_B); 431 hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg); 432 } 433 } 434 435 static void 436 hns3_enable_txq(struct hns3_tx_queue *txq, bool en) 437 { 438 struct hns3_hw *hw = &txq->hns->hw; 439 uint32_t reg; 440 441 if (hns3_dev_get_support(hw, INDEP_TXRX)) { 442 reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG); 443 if (en) 444 reg |= BIT(HNS3_RING_EN_B); 445 else 446 reg &= ~BIT(HNS3_RING_EN_B); 447 hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg); 448 } 449 txq->enabled = en; 450 } 451 452 static void 453 hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en) 454 { 455 struct hns3_hw *hw = &rxq->hns->hw; 456 uint32_t reg; 457 458 if (hns3_dev_get_support(hw, INDEP_TXRX)) { 459 reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG); 460 if (en) 461 reg |= BIT(HNS3_RING_EN_B); 462 else 463 reg &= ~BIT(HNS3_RING_EN_B); 464 hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg); 465 } 466 rxq->enabled = en; 467 } 468 469 int 470 hns3_start_all_txqs(struct rte_eth_dev *dev) 471 { 472 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 473 struct hns3_tx_queue *txq; 474 uint16_t i, j; 475 476 for (i = 0; i < dev->data->nb_tx_queues; i++) { 477 txq = hw->data->tx_queues[i]; 478 if (!txq) { 479 hns3_err(hw, "Tx queue %u not available or setup.", i); 480 goto start_txqs_fail; 481 } 482 /* 483 * Tx queue is enabled by default. Therefore, the Tx queues 484 * needs to be disabled when deferred_start is set. There is 485 * another master switch used to control the enabling of a pair 486 * of Tx and Rx queues. And the master switch is disabled by 487 * default. 488 */ 489 if (txq->tx_deferred_start) 490 hns3_enable_txq(txq, false); 491 else 492 hns3_enable_txq(txq, true); 493 } 494 return 0; 495 496 start_txqs_fail: 497 for (j = 0; j < i; j++) { 498 txq = hw->data->tx_queues[j]; 499 hns3_enable_txq(txq, false); 500 } 501 return -EINVAL; 502 } 503 504 int 505 hns3_start_all_rxqs(struct rte_eth_dev *dev) 506 { 507 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 508 struct hns3_rx_queue *rxq; 509 uint16_t i, j; 510 511 for (i = 0; i < dev->data->nb_rx_queues; i++) { 512 rxq = hw->data->rx_queues[i]; 513 if (!rxq) { 514 hns3_err(hw, "Rx queue %u not available or setup.", i); 515 goto start_rxqs_fail; 516 } 517 /* 518 * Rx queue is enabled by default. Therefore, the Rx queues 519 * needs to be disabled when deferred_start is set. There is 520 * another master switch used to control the enabling of a pair 521 * of Tx and Rx queues. And the master switch is disabled by 522 * default. 523 */ 524 if (rxq->rx_deferred_start) 525 hns3_enable_rxq(rxq, false); 526 else 527 hns3_enable_rxq(rxq, true); 528 } 529 return 0; 530 531 start_rxqs_fail: 532 for (j = 0; j < i; j++) { 533 rxq = hw->data->rx_queues[j]; 534 hns3_enable_rxq(rxq, false); 535 } 536 return -EINVAL; 537 } 538 539 void 540 hns3_restore_tqp_enable_state(struct hns3_hw *hw) 541 { 542 struct hns3_rx_queue *rxq; 543 struct hns3_tx_queue *txq; 544 uint16_t i; 545 546 for (i = 0; i < hw->data->nb_rx_queues; i++) { 547 rxq = hw->data->rx_queues[i]; 548 if (rxq != NULL) 549 hns3_enable_rxq(rxq, rxq->enabled); 550 } 551 552 for (i = 0; i < hw->data->nb_tx_queues; i++) { 553 txq = hw->data->tx_queues[i]; 554 if (txq != NULL) 555 hns3_enable_txq(txq, txq->enabled); 556 } 557 } 558 559 void 560 hns3_stop_all_txqs(struct rte_eth_dev *dev) 561 { 562 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 563 struct hns3_tx_queue *txq; 564 uint16_t i; 565 566 for (i = 0; i < dev->data->nb_tx_queues; i++) { 567 txq = hw->data->tx_queues[i]; 568 if (!txq) 569 continue; 570 hns3_enable_txq(txq, false); 571 } 572 } 573 574 static int 575 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable) 576 { 577 struct hns3_cfg_com_tqp_queue_cmd *req; 578 struct hns3_cmd_desc desc; 579 int ret; 580 581 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data; 582 583 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false); 584 req->tqp_id = rte_cpu_to_le_16(queue_id); 585 req->stream_id = 0; 586 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0); 587 588 ret = hns3_cmd_send(hw, &desc, 1); 589 if (ret) 590 hns3_err(hw, "TQP enable fail, ret = %d", ret); 591 592 return ret; 593 } 594 595 static int 596 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable) 597 { 598 struct hns3_reset_tqp_queue_cmd *req; 599 struct hns3_cmd_desc desc; 600 int ret; 601 602 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false); 603 604 req = (struct hns3_reset_tqp_queue_cmd *)desc.data; 605 req->tqp_id = rte_cpu_to_le_16(queue_id); 606 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0); 607 ret = hns3_cmd_send(hw, &desc, 1); 608 if (ret) 609 hns3_err(hw, "send tqp reset cmd error, queue_id = %u, " 610 "ret = %d", queue_id, ret); 611 612 return ret; 613 } 614 615 static int 616 hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id, 617 uint8_t *reset_status) 618 { 619 struct hns3_reset_tqp_queue_cmd *req; 620 struct hns3_cmd_desc desc; 621 int ret; 622 623 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true); 624 625 req = (struct hns3_reset_tqp_queue_cmd *)desc.data; 626 req->tqp_id = rte_cpu_to_le_16(queue_id); 627 628 ret = hns3_cmd_send(hw, &desc, 1); 629 if (ret) { 630 hns3_err(hw, "get tqp reset status error, queue_id = %u, " 631 "ret = %d.", queue_id, ret); 632 return ret; 633 } 634 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B); 635 return ret; 636 } 637 638 static int 639 hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id) 640 { 641 #define HNS3_TQP_RESET_TRY_MS 200 642 uint16_t wait_time = 0; 643 uint8_t reset_status; 644 int ret; 645 646 /* 647 * In current version VF is not supported when PF is driven by DPDK 648 * driver, all task queue pairs are mapped to PF function, so PF's queue 649 * id is equals to the global queue id in PF range. 650 */ 651 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true); 652 if (ret) { 653 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret); 654 return ret; 655 } 656 657 do { 658 /* Wait for tqp hw reset */ 659 rte_delay_ms(HNS3_POLL_RESPONE_MS); 660 wait_time += HNS3_POLL_RESPONE_MS; 661 ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status); 662 if (ret) 663 goto tqp_reset_fail; 664 665 if (reset_status) 666 break; 667 } while (wait_time < HNS3_TQP_RESET_TRY_MS); 668 669 if (!reset_status) { 670 ret = -ETIMEDOUT; 671 hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d", 672 queue_id, ret); 673 goto tqp_reset_fail; 674 } 675 676 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false); 677 if (ret) 678 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret); 679 680 return ret; 681 682 tqp_reset_fail: 683 hns3_send_reset_tqp_cmd(hw, queue_id, false); 684 return ret; 685 } 686 687 static int 688 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id) 689 { 690 uint8_t msg_data[2]; 691 int ret; 692 693 memcpy(msg_data, &queue_id, sizeof(uint16_t)); 694 695 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data, 696 sizeof(msg_data), true, NULL, 0); 697 if (ret) 698 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.", 699 queue_id, ret); 700 return ret; 701 } 702 703 static int 704 hns3_reset_rcb_cmd(struct hns3_hw *hw, uint8_t *reset_status) 705 { 706 struct hns3_reset_cmd *req; 707 struct hns3_cmd_desc desc; 708 int ret; 709 710 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 711 req = (struct hns3_reset_cmd *)desc.data; 712 hns3_set_bit(req->fun_reset_rcb, HNS3_CFG_RESET_RCB_B, 1); 713 714 /* 715 * The start qid should be the global qid of the first tqp of the 716 * function which should be reset in this port. Since our PF not 717 * support take over of VFs, so we only need to reset function 0, 718 * and its start qid is always 0. 719 */ 720 req->fun_reset_rcb_vqid_start = rte_cpu_to_le_16(0); 721 req->fun_reset_rcb_vqid_num = rte_cpu_to_le_16(hw->cfg_max_queues); 722 723 ret = hns3_cmd_send(hw, &desc, 1); 724 if (ret) { 725 hns3_err(hw, "fail to send rcb reset cmd, ret = %d.", ret); 726 return ret; 727 } 728 729 *reset_status = req->fun_reset_rcb_return_status; 730 return 0; 731 } 732 733 static int 734 hns3pf_reset_all_tqps(struct hns3_hw *hw) 735 { 736 #define HNS3_RESET_RCB_NOT_SUPPORT 0U 737 #define HNS3_RESET_ALL_TQP_SUCCESS 1U 738 uint8_t reset_status; 739 int ret; 740 int i; 741 742 ret = hns3_reset_rcb_cmd(hw, &reset_status); 743 if (ret) 744 return ret; 745 746 /* 747 * If the firmware version is low, it may not support the rcb reset 748 * which means reset all the tqps at a time. In this case, we should 749 * reset tqps one by one. 750 */ 751 if (reset_status == HNS3_RESET_RCB_NOT_SUPPORT) { 752 for (i = 0; i < hw->cfg_max_queues; i++) { 753 ret = hns3pf_reset_tqp(hw, i); 754 if (ret) { 755 hns3_err(hw, 756 "fail to reset tqp, queue_id = %d, ret = %d.", 757 i, ret); 758 return ret; 759 } 760 } 761 } else if (reset_status != HNS3_RESET_ALL_TQP_SUCCESS) { 762 hns3_err(hw, "fail to reset all tqps, reset_status = %u.", 763 reset_status); 764 return -EIO; 765 } 766 767 return 0; 768 } 769 770 static int 771 hns3vf_reset_all_tqps(struct hns3_hw *hw) 772 { 773 #define HNS3VF_RESET_ALL_TQP_DONE 1U 774 uint8_t reset_status; 775 uint8_t msg_data[2]; 776 int ret; 777 int i; 778 779 memset(msg_data, 0, sizeof(uint16_t)); 780 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data, 781 sizeof(msg_data), true, &reset_status, 782 sizeof(reset_status)); 783 if (ret) { 784 hns3_err(hw, "fail to send rcb reset mbx, ret = %d.", ret); 785 return ret; 786 } 787 788 if (reset_status == HNS3VF_RESET_ALL_TQP_DONE) 789 return 0; 790 791 /* 792 * If the firmware version or kernel PF version is low, it may not 793 * support the rcb reset which means reset all the tqps at a time. 794 * In this case, we should reset tqps one by one. 795 */ 796 for (i = 1; i < hw->cfg_max_queues; i++) { 797 ret = hns3vf_reset_tqp(hw, i); 798 if (ret) 799 return ret; 800 } 801 802 return 0; 803 } 804 805 int 806 hns3_reset_all_tqps(struct hns3_adapter *hns) 807 { 808 struct hns3_hw *hw = &hns->hw; 809 int ret, i; 810 811 /* Disable all queues before reset all queues */ 812 for (i = 0; i < hw->cfg_max_queues; i++) { 813 ret = hns3_tqp_enable(hw, i, false); 814 if (ret) { 815 hns3_err(hw, 816 "fail to disable tqps before tqps reset, ret = %d.", 817 ret); 818 return ret; 819 } 820 } 821 822 if (hns->is_vf) 823 return hns3vf_reset_all_tqps(hw); 824 else 825 return hns3pf_reset_all_tqps(hw); 826 } 827 828 static int 829 hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id, 830 enum hns3_ring_type queue_type, bool enable) 831 { 832 struct hns3_reset_tqp_queue_cmd *req; 833 struct hns3_cmd_desc desc; 834 int queue_direction; 835 int ret; 836 837 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false); 838 839 req = (struct hns3_reset_tqp_queue_cmd *)desc.data; 840 req->tqp_id = rte_cpu_to_le_16(queue_id); 841 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1; 842 req->queue_direction = rte_cpu_to_le_16(queue_direction); 843 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0); 844 845 ret = hns3_cmd_send(hw, &desc, 1); 846 if (ret) 847 hns3_err(hw, "send queue reset cmd error, queue_id = %u, " 848 "queue_type = %s, ret = %d.", queue_id, 849 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret); 850 return ret; 851 } 852 853 static int 854 hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id, 855 enum hns3_ring_type queue_type, 856 uint8_t *reset_status) 857 { 858 struct hns3_reset_tqp_queue_cmd *req; 859 struct hns3_cmd_desc desc; 860 int queue_direction; 861 int ret; 862 863 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true); 864 865 req = (struct hns3_reset_tqp_queue_cmd *)desc.data; 866 req->tqp_id = rte_cpu_to_le_16(queue_id); 867 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1; 868 req->queue_direction = rte_cpu_to_le_16(queue_direction); 869 870 ret = hns3_cmd_send(hw, &desc, 1); 871 if (ret) { 872 hns3_err(hw, "get queue reset status error, queue_id = %u " 873 "queue_type = %s, ret = %d.", queue_id, 874 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret); 875 return ret; 876 } 877 878 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B); 879 return ret; 880 } 881 882 static int 883 hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id, 884 enum hns3_ring_type queue_type) 885 { 886 #define HNS3_QUEUE_RESET_TRY_MS 200 887 struct hns3_tx_queue *txq; 888 struct hns3_rx_queue *rxq; 889 uint32_t reset_wait_times; 890 uint32_t max_wait_times; 891 uint8_t reset_status; 892 int ret; 893 894 if (queue_type == HNS3_RING_TYPE_TX) { 895 txq = hw->data->tx_queues[queue_id]; 896 hns3_enable_txq(txq, false); 897 } else { 898 rxq = hw->data->rx_queues[queue_id]; 899 hns3_enable_rxq(rxq, false); 900 } 901 902 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true); 903 if (ret) { 904 hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret); 905 return ret; 906 } 907 908 reset_wait_times = 0; 909 max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS; 910 while (reset_wait_times < max_wait_times) { 911 /* Wait for queue hw reset */ 912 rte_delay_ms(HNS3_POLL_RESPONE_MS); 913 ret = hns3_get_queue_reset_status(hw, queue_id, 914 queue_type, &reset_status); 915 if (ret) 916 goto queue_reset_fail; 917 918 if (reset_status) 919 break; 920 reset_wait_times++; 921 } 922 923 if (!reset_status) { 924 hns3_err(hw, "reset queue timeout, queue_id = %u, " 925 "queue_type = %s", queue_id, 926 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx"); 927 ret = -ETIMEDOUT; 928 goto queue_reset_fail; 929 } 930 931 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false); 932 if (ret) 933 hns3_err(hw, "deassert queue reset fail, ret = %d.", ret); 934 935 return ret; 936 937 queue_reset_fail: 938 hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false); 939 return ret; 940 } 941 942 uint32_t 943 hns3_get_tqp_intr_reg_offset(uint16_t tqp_intr_id) 944 { 945 uint32_t reg_offset; 946 947 /* Need an extend offset to config queues > 64 */ 948 if (tqp_intr_id < HNS3_MIN_EXT_TQP_INTR_ID) 949 reg_offset = HNS3_TQP_INTR_REG_BASE + 950 tqp_intr_id * HNS3_TQP_INTR_LOW_ORDER_OFFSET; 951 else 952 reg_offset = HNS3_TQP_INTR_EXT_REG_BASE + 953 tqp_intr_id / HNS3_MIN_EXT_TQP_INTR_ID * 954 HNS3_TQP_INTR_HIGH_ORDER_OFFSET + 955 tqp_intr_id % HNS3_MIN_EXT_TQP_INTR_ID * 956 HNS3_TQP_INTR_LOW_ORDER_OFFSET; 957 958 return reg_offset; 959 } 960 961 void 962 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id, 963 uint8_t gl_idx, uint16_t gl_value) 964 { 965 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG, 966 HNS3_TQP_INTR_GL1_REG, 967 HNS3_TQP_INTR_GL2_REG}; 968 uint32_t addr, value; 969 970 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX) 971 return; 972 973 addr = offset[gl_idx] + hns3_get_tqp_intr_reg_offset(queue_id); 974 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US) 975 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US; 976 else 977 value = HNS3_GL_USEC_TO_REG(gl_value); 978 979 hns3_write_dev(hw, addr, value); 980 } 981 982 void 983 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value) 984 { 985 uint32_t addr, value; 986 987 if (rl_value > HNS3_TQP_INTR_RL_MAX) 988 return; 989 990 addr = HNS3_TQP_INTR_RL_REG + hns3_get_tqp_intr_reg_offset(queue_id); 991 value = HNS3_RL_USEC_TO_REG(rl_value); 992 if (value > 0) 993 value |= HNS3_TQP_INTR_RL_ENABLE_MASK; 994 995 hns3_write_dev(hw, addr, value); 996 } 997 998 void 999 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value) 1000 { 1001 uint32_t addr; 1002 1003 /* 1004 * int_ql_max == 0 means the hardware does not support QL, 1005 * QL regs config is not permitted if QL is not supported, 1006 * here just return. 1007 */ 1008 if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE) 1009 return; 1010 1011 addr = HNS3_TQP_INTR_TX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id); 1012 hns3_write_dev(hw, addr, ql_value); 1013 1014 addr = HNS3_TQP_INTR_RX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id); 1015 hns3_write_dev(hw, addr, ql_value); 1016 } 1017 1018 static void 1019 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en) 1020 { 1021 uint32_t addr, value; 1022 1023 addr = HNS3_TQP_INTR_CTRL_REG + hns3_get_tqp_intr_reg_offset(queue_id); 1024 value = en ? 1 : 0; 1025 1026 hns3_write_dev(hw, addr, value); 1027 } 1028 1029 /* 1030 * Enable all rx queue interrupt when in interrupt rx mode. 1031 * This api was called before enable queue rx&tx (in normal start or reset 1032 * recover scenes), used to fix hardware rx queue interrupt enable was clear 1033 * when FLR. 1034 */ 1035 void 1036 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en) 1037 { 1038 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1039 uint16_t nb_rx_q = hw->data->nb_rx_queues; 1040 int i; 1041 1042 if (dev->data->dev_conf.intr_conf.rxq == 0) 1043 return; 1044 1045 for (i = 0; i < nb_rx_q; i++) 1046 hns3_queue_intr_enable(hw, i, en); 1047 } 1048 1049 int 1050 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 1051 { 1052 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1053 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1054 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1055 1056 if (dev->data->dev_conf.intr_conf.rxq == 0) 1057 return -ENOTSUP; 1058 1059 hns3_queue_intr_enable(hw, queue_id, true); 1060 1061 return rte_intr_ack(intr_handle); 1062 } 1063 1064 int 1065 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 1066 { 1067 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1068 1069 if (dev->data->dev_conf.intr_conf.rxq == 0) 1070 return -ENOTSUP; 1071 1072 hns3_queue_intr_enable(hw, queue_id, false); 1073 1074 return 0; 1075 } 1076 1077 static int 1078 hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx) 1079 { 1080 struct hns3_hw *hw = &hns->hw; 1081 struct hns3_rx_queue *rxq; 1082 int ret; 1083 1084 PMD_INIT_FUNC_TRACE(); 1085 1086 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx]; 1087 ret = hns3_alloc_rx_queue_mbufs(hw, rxq); 1088 if (ret) { 1089 hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.", 1090 idx, ret); 1091 return ret; 1092 } 1093 1094 rxq->next_to_use = 0; 1095 rxq->rx_rearm_start = 0; 1096 rxq->rx_free_hold = 0; 1097 rxq->rx_rearm_nb = 0; 1098 rxq->pkt_first_seg = NULL; 1099 rxq->pkt_last_seg = NULL; 1100 hns3_init_rx_queue_hw(rxq); 1101 hns3_rxq_vec_setup(rxq); 1102 1103 return 0; 1104 } 1105 1106 static void 1107 hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx) 1108 { 1109 struct hns3_hw *hw = &hns->hw; 1110 struct hns3_rx_queue *rxq; 1111 1112 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx]; 1113 rxq->next_to_use = 0; 1114 rxq->rx_free_hold = 0; 1115 rxq->rx_rearm_start = 0; 1116 rxq->rx_rearm_nb = 0; 1117 hns3_init_rx_queue_hw(rxq); 1118 } 1119 1120 static void 1121 hns3_init_txq(struct hns3_tx_queue *txq) 1122 { 1123 struct hns3_desc *desc; 1124 int i; 1125 1126 /* Clear tx bd */ 1127 desc = txq->tx_ring; 1128 for (i = 0; i < txq->nb_tx_desc; i++) { 1129 desc->tx.tp_fe_sc_vld_ra_ri = 0; 1130 desc++; 1131 } 1132 1133 txq->next_to_use = 0; 1134 txq->next_to_clean = 0; 1135 txq->tx_bd_ready = txq->nb_tx_desc - 1; 1136 hns3_init_tx_queue_hw(txq); 1137 } 1138 1139 static void 1140 hns3_init_tx_ring_tc(struct hns3_adapter *hns) 1141 { 1142 struct hns3_hw *hw = &hns->hw; 1143 struct hns3_tx_queue *txq; 1144 int i, num; 1145 1146 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 1147 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i]; 1148 int j; 1149 1150 if (!tc_queue->enable) 1151 continue; 1152 1153 for (j = 0; j < tc_queue->tqp_count; j++) { 1154 num = tc_queue->tqp_offset + j; 1155 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num]; 1156 if (txq == NULL) 1157 continue; 1158 1159 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc); 1160 } 1161 } 1162 } 1163 1164 static int 1165 hns3_init_rx_queues(struct hns3_adapter *hns) 1166 { 1167 struct hns3_hw *hw = &hns->hw; 1168 struct hns3_rx_queue *rxq; 1169 uint16_t i, j; 1170 int ret; 1171 1172 /* Initialize RSS for queues */ 1173 ret = hns3_config_rss(hns); 1174 if (ret) { 1175 hns3_err(hw, "failed to configure rss, ret = %d.", ret); 1176 return ret; 1177 } 1178 1179 for (i = 0; i < hw->data->nb_rx_queues; i++) { 1180 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i]; 1181 if (!rxq) { 1182 hns3_err(hw, "Rx queue %u not available or setup.", i); 1183 goto out; 1184 } 1185 1186 if (rxq->rx_deferred_start) 1187 continue; 1188 1189 ret = hns3_init_rxq(hns, i); 1190 if (ret) { 1191 hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i, 1192 ret); 1193 goto out; 1194 } 1195 } 1196 1197 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++) 1198 hns3_init_fake_rxq(hns, i); 1199 1200 return 0; 1201 1202 out: 1203 for (j = 0; j < i; j++) { 1204 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j]; 1205 hns3_rx_queue_release_mbufs(rxq); 1206 } 1207 1208 return ret; 1209 } 1210 1211 static int 1212 hns3_init_tx_queues(struct hns3_adapter *hns) 1213 { 1214 struct hns3_hw *hw = &hns->hw; 1215 struct hns3_tx_queue *txq; 1216 uint16_t i; 1217 1218 for (i = 0; i < hw->data->nb_tx_queues; i++) { 1219 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i]; 1220 if (!txq) { 1221 hns3_err(hw, "Tx queue %u not available or setup.", i); 1222 return -EINVAL; 1223 } 1224 1225 if (txq->tx_deferred_start) 1226 continue; 1227 hns3_init_txq(txq); 1228 } 1229 1230 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) { 1231 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i]; 1232 hns3_init_txq(txq); 1233 } 1234 hns3_init_tx_ring_tc(hns); 1235 1236 return 0; 1237 } 1238 1239 /* 1240 * Init all queues. 1241 * Note: just init and setup queues, and don't enable tqps. 1242 */ 1243 int 1244 hns3_init_queues(struct hns3_adapter *hns, bool reset_queue) 1245 { 1246 struct hns3_hw *hw = &hns->hw; 1247 int ret; 1248 1249 if (reset_queue) { 1250 ret = hns3_reset_all_tqps(hns); 1251 if (ret) { 1252 hns3_err(hw, "failed to reset all queues, ret = %d.", 1253 ret); 1254 return ret; 1255 } 1256 } 1257 1258 ret = hns3_init_rx_queues(hns); 1259 if (ret) { 1260 hns3_err(hw, "failed to init rx queues, ret = %d.", ret); 1261 return ret; 1262 } 1263 1264 ret = hns3_init_tx_queues(hns); 1265 if (ret) { 1266 hns3_dev_release_mbufs(hns); 1267 hns3_err(hw, "failed to init tx queues, ret = %d.", ret); 1268 } 1269 1270 return ret; 1271 } 1272 1273 void 1274 hns3_start_tqps(struct hns3_hw *hw) 1275 { 1276 struct hns3_tx_queue *txq; 1277 struct hns3_rx_queue *rxq; 1278 uint16_t i; 1279 1280 hns3_enable_all_queues(hw, true); 1281 1282 for (i = 0; i < hw->data->nb_tx_queues; i++) { 1283 txq = hw->data->tx_queues[i]; 1284 if (txq->enabled) 1285 hw->data->tx_queue_state[i] = 1286 RTE_ETH_QUEUE_STATE_STARTED; 1287 } 1288 1289 for (i = 0; i < hw->data->nb_rx_queues; i++) { 1290 rxq = hw->data->rx_queues[i]; 1291 if (rxq->enabled) 1292 hw->data->rx_queue_state[i] = 1293 RTE_ETH_QUEUE_STATE_STARTED; 1294 } 1295 } 1296 1297 void 1298 hns3_stop_tqps(struct hns3_hw *hw) 1299 { 1300 uint16_t i; 1301 1302 hns3_enable_all_queues(hw, false); 1303 1304 for (i = 0; i < hw->data->nb_tx_queues; i++) 1305 hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1306 1307 for (i = 0; i < hw->data->nb_rx_queues; i++) 1308 hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1309 } 1310 1311 /* 1312 * Iterate over all Rx Queue, and call the callback() function for each Rx 1313 * queue. 1314 * 1315 * @param[in] dev 1316 * The target eth dev. 1317 * @param[in] callback 1318 * The function to call for each queue. 1319 * if callback function return nonzero will stop iterate and return it's value 1320 * @param[in] arg 1321 * The arguments to provide the callback function with. 1322 * 1323 * @return 1324 * 0 on success, otherwise with errno set. 1325 */ 1326 int 1327 hns3_rxq_iterate(struct rte_eth_dev *dev, 1328 int (*callback)(struct hns3_rx_queue *, void *), void *arg) 1329 { 1330 uint32_t i; 1331 int ret; 1332 1333 if (dev->data->rx_queues == NULL) 1334 return -EINVAL; 1335 1336 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1337 ret = callback(dev->data->rx_queues[i], arg); 1338 if (ret != 0) 1339 return ret; 1340 } 1341 1342 return 0; 1343 } 1344 1345 static void* 1346 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev, 1347 struct hns3_queue_info *q_info) 1348 { 1349 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1350 const struct rte_memzone *rx_mz; 1351 struct hns3_rx_queue *rxq; 1352 unsigned int rx_desc; 1353 1354 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue), 1355 RTE_CACHE_LINE_SIZE, q_info->socket_id); 1356 if (rxq == NULL) { 1357 hns3_err(hw, "Failed to allocate memory for No.%u rx ring!", 1358 q_info->idx); 1359 return NULL; 1360 } 1361 1362 /* Allocate rx ring hardware descriptors. */ 1363 rxq->queue_id = q_info->idx; 1364 rxq->nb_rx_desc = q_info->nb_desc; 1365 1366 /* 1367 * Allocate a litter more memory because rx vector functions 1368 * don't check boundaries each time. 1369 */ 1370 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) * 1371 sizeof(struct hns3_desc); 1372 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx, 1373 rx_desc, HNS3_RING_BASE_ALIGN, 1374 q_info->socket_id); 1375 if (rx_mz == NULL) { 1376 hns3_err(hw, "Failed to reserve DMA memory for No.%u rx ring!", 1377 q_info->idx); 1378 hns3_rx_queue_release(rxq); 1379 return NULL; 1380 } 1381 rxq->mz = rx_mz; 1382 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr; 1383 rxq->rx_ring_phys_addr = rx_mz->iova; 1384 1385 hns3_dbg(hw, "No.%u rx descriptors iova 0x%" PRIx64, q_info->idx, 1386 rxq->rx_ring_phys_addr); 1387 1388 return rxq; 1389 } 1390 1391 static int 1392 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, 1393 uint16_t nb_desc, unsigned int socket_id) 1394 { 1395 struct hns3_adapter *hns = dev->data->dev_private; 1396 struct hns3_hw *hw = &hns->hw; 1397 struct hns3_queue_info q_info; 1398 struct hns3_rx_queue *rxq; 1399 uint16_t nb_rx_q; 1400 1401 if (hw->fkq_data.rx_queues[idx]) { 1402 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]); 1403 hw->fkq_data.rx_queues[idx] = NULL; 1404 } 1405 1406 q_info.idx = idx; 1407 q_info.socket_id = socket_id; 1408 q_info.nb_desc = nb_desc; 1409 q_info.type = "hns3 fake RX queue"; 1410 q_info.ring_name = "rx_fake_ring"; 1411 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info); 1412 if (rxq == NULL) { 1413 hns3_err(hw, "Failed to setup No.%u fake rx ring.", idx); 1414 return -ENOMEM; 1415 } 1416 1417 /* Don't need alloc sw_ring, because upper applications don't use it */ 1418 rxq->sw_ring = NULL; 1419 1420 rxq->hns = hns; 1421 rxq->rx_deferred_start = false; 1422 rxq->port_id = dev->data->port_id; 1423 rxq->configured = true; 1424 nb_rx_q = dev->data->nb_rx_queues; 1425 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + 1426 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE); 1427 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE; 1428 1429 rte_spinlock_lock(&hw->lock); 1430 hw->fkq_data.rx_queues[idx] = rxq; 1431 rte_spinlock_unlock(&hw->lock); 1432 1433 return 0; 1434 } 1435 1436 static void* 1437 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev, 1438 struct hns3_queue_info *q_info) 1439 { 1440 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1441 const struct rte_memzone *tx_mz; 1442 struct hns3_tx_queue *txq; 1443 struct hns3_desc *desc; 1444 unsigned int tx_desc; 1445 int i; 1446 1447 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue), 1448 RTE_CACHE_LINE_SIZE, q_info->socket_id); 1449 if (txq == NULL) { 1450 hns3_err(hw, "Failed to allocate memory for No.%u tx ring!", 1451 q_info->idx); 1452 return NULL; 1453 } 1454 1455 /* Allocate tx ring hardware descriptors. */ 1456 txq->queue_id = q_info->idx; 1457 txq->nb_tx_desc = q_info->nb_desc; 1458 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc); 1459 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx, 1460 tx_desc, HNS3_RING_BASE_ALIGN, 1461 q_info->socket_id); 1462 if (tx_mz == NULL) { 1463 hns3_err(hw, "Failed to reserve DMA memory for No.%u tx ring!", 1464 q_info->idx); 1465 hns3_tx_queue_release(txq); 1466 return NULL; 1467 } 1468 txq->mz = tx_mz; 1469 txq->tx_ring = (struct hns3_desc *)tx_mz->addr; 1470 txq->tx_ring_phys_addr = tx_mz->iova; 1471 1472 hns3_dbg(hw, "No.%u tx descriptors iova 0x%" PRIx64, q_info->idx, 1473 txq->tx_ring_phys_addr); 1474 1475 /* Clear tx bd */ 1476 desc = txq->tx_ring; 1477 for (i = 0; i < txq->nb_tx_desc; i++) { 1478 desc->tx.tp_fe_sc_vld_ra_ri = 0; 1479 desc++; 1480 } 1481 1482 return txq; 1483 } 1484 1485 static int 1486 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, 1487 uint16_t nb_desc, unsigned int socket_id) 1488 { 1489 struct hns3_adapter *hns = dev->data->dev_private; 1490 struct hns3_hw *hw = &hns->hw; 1491 struct hns3_queue_info q_info; 1492 struct hns3_tx_queue *txq; 1493 uint16_t nb_tx_q; 1494 1495 if (hw->fkq_data.tx_queues[idx] != NULL) { 1496 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]); 1497 hw->fkq_data.tx_queues[idx] = NULL; 1498 } 1499 1500 q_info.idx = idx; 1501 q_info.socket_id = socket_id; 1502 q_info.nb_desc = nb_desc; 1503 q_info.type = "hns3 fake TX queue"; 1504 q_info.ring_name = "tx_fake_ring"; 1505 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info); 1506 if (txq == NULL) { 1507 hns3_err(hw, "Failed to setup No.%u fake tx ring.", idx); 1508 return -ENOMEM; 1509 } 1510 1511 /* Don't need alloc sw_ring, because upper applications don't use it */ 1512 txq->sw_ring = NULL; 1513 txq->free = NULL; 1514 1515 txq->hns = hns; 1516 txq->tx_deferred_start = false; 1517 txq->port_id = dev->data->port_id; 1518 txq->configured = true; 1519 nb_tx_q = dev->data->nb_tx_queues; 1520 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + 1521 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE); 1522 1523 rte_spinlock_lock(&hw->lock); 1524 hw->fkq_data.tx_queues[idx] = txq; 1525 rte_spinlock_unlock(&hw->lock); 1526 1527 return 0; 1528 } 1529 1530 static int 1531 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues) 1532 { 1533 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues; 1534 void **rxq; 1535 uint16_t i; 1536 1537 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) { 1538 /* first time configuration */ 1539 uint32_t size; 1540 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues; 1541 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size, 1542 RTE_CACHE_LINE_SIZE); 1543 if (hw->fkq_data.rx_queues == NULL) { 1544 hw->fkq_data.nb_fake_rx_queues = 0; 1545 return -ENOMEM; 1546 } 1547 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) { 1548 /* re-configure */ 1549 rxq = hw->fkq_data.rx_queues; 1550 for (i = nb_queues; i < old_nb_queues; i++) 1551 hns3_rx_queue_release_lock(rxq[i]); 1552 1553 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues, 1554 RTE_CACHE_LINE_SIZE); 1555 if (rxq == NULL) 1556 return -ENOMEM; 1557 if (nb_queues > old_nb_queues) { 1558 uint16_t new_qs = nb_queues - old_nb_queues; 1559 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs); 1560 } 1561 1562 hw->fkq_data.rx_queues = rxq; 1563 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) { 1564 rxq = hw->fkq_data.rx_queues; 1565 for (i = nb_queues; i < old_nb_queues; i++) 1566 hns3_rx_queue_release_lock(rxq[i]); 1567 1568 rte_free(hw->fkq_data.rx_queues); 1569 hw->fkq_data.rx_queues = NULL; 1570 } 1571 1572 hw->fkq_data.nb_fake_rx_queues = nb_queues; 1573 1574 return 0; 1575 } 1576 1577 static int 1578 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues) 1579 { 1580 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues; 1581 void **txq; 1582 uint16_t i; 1583 1584 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) { 1585 /* first time configuration */ 1586 uint32_t size; 1587 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues; 1588 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size, 1589 RTE_CACHE_LINE_SIZE); 1590 if (hw->fkq_data.tx_queues == NULL) { 1591 hw->fkq_data.nb_fake_tx_queues = 0; 1592 return -ENOMEM; 1593 } 1594 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) { 1595 /* re-configure */ 1596 txq = hw->fkq_data.tx_queues; 1597 for (i = nb_queues; i < old_nb_queues; i++) 1598 hns3_tx_queue_release_lock(txq[i]); 1599 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues, 1600 RTE_CACHE_LINE_SIZE); 1601 if (txq == NULL) 1602 return -ENOMEM; 1603 if (nb_queues > old_nb_queues) { 1604 uint16_t new_qs = nb_queues - old_nb_queues; 1605 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs); 1606 } 1607 1608 hw->fkq_data.tx_queues = txq; 1609 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) { 1610 txq = hw->fkq_data.tx_queues; 1611 for (i = nb_queues; i < old_nb_queues; i++) 1612 hns3_tx_queue_release_lock(txq[i]); 1613 1614 rte_free(hw->fkq_data.tx_queues); 1615 hw->fkq_data.tx_queues = NULL; 1616 } 1617 hw->fkq_data.nb_fake_tx_queues = nb_queues; 1618 1619 return 0; 1620 } 1621 1622 int 1623 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q, 1624 uint16_t nb_tx_q) 1625 { 1626 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1627 uint16_t rx_need_add_nb_q; 1628 uint16_t tx_need_add_nb_q; 1629 uint16_t port_id; 1630 uint16_t q; 1631 int ret; 1632 1633 if (hns3_dev_get_support(hw, INDEP_TXRX)) 1634 return 0; 1635 1636 /* Setup new number of fake RX/TX queues and reconfigure device. */ 1637 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q; 1638 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q; 1639 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q); 1640 if (ret) { 1641 hns3_err(hw, "Fail to configure fake rx queues: %d", ret); 1642 return ret; 1643 } 1644 1645 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q); 1646 if (ret) { 1647 hns3_err(hw, "Fail to configure fake rx queues: %d", ret); 1648 goto cfg_fake_tx_q_fail; 1649 } 1650 1651 /* Allocate and set up fake RX queue per Ethernet port. */ 1652 port_id = hw->data->port_id; 1653 for (q = 0; q < rx_need_add_nb_q; q++) { 1654 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC, 1655 rte_eth_dev_socket_id(port_id)); 1656 if (ret) 1657 goto setup_fake_rx_q_fail; 1658 } 1659 1660 /* Allocate and set up fake TX queue per Ethernet port. */ 1661 for (q = 0; q < tx_need_add_nb_q; q++) { 1662 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC, 1663 rte_eth_dev_socket_id(port_id)); 1664 if (ret) 1665 goto setup_fake_tx_q_fail; 1666 } 1667 1668 return 0; 1669 1670 setup_fake_tx_q_fail: 1671 setup_fake_rx_q_fail: 1672 (void)hns3_fake_tx_queue_config(hw, 0); 1673 cfg_fake_tx_q_fail: 1674 (void)hns3_fake_rx_queue_config(hw, 0); 1675 1676 return ret; 1677 } 1678 1679 void 1680 hns3_dev_release_mbufs(struct hns3_adapter *hns) 1681 { 1682 struct rte_eth_dev_data *dev_data = hns->hw.data; 1683 struct hns3_rx_queue *rxq; 1684 struct hns3_tx_queue *txq; 1685 int i; 1686 1687 if (dev_data->rx_queues) 1688 for (i = 0; i < dev_data->nb_rx_queues; i++) { 1689 rxq = dev_data->rx_queues[i]; 1690 if (rxq == NULL) 1691 continue; 1692 hns3_rx_queue_release_mbufs(rxq); 1693 } 1694 1695 if (dev_data->tx_queues) 1696 for (i = 0; i < dev_data->nb_tx_queues; i++) { 1697 txq = dev_data->tx_queues[i]; 1698 if (txq == NULL) 1699 continue; 1700 hns3_tx_queue_release_mbufs(txq); 1701 } 1702 } 1703 1704 static int 1705 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len) 1706 { 1707 uint16_t vld_buf_size; 1708 uint16_t num_hw_specs; 1709 uint16_t i; 1710 1711 /* 1712 * hns3 network engine only support to set 4 typical specification, and 1713 * different buffer size will affect the max packet_len and the max 1714 * number of segmentation when hw gro is turned on in receive side. The 1715 * relationship between them is as follows: 1716 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg 1717 * ---------------------|-------------------|---------------- 1718 * HNS3_4K_BD_BUF_SIZE | 60KB | 15 1719 * HNS3_2K_BD_BUF_SIZE | 62KB | 31 1720 * HNS3_1K_BD_BUF_SIZE | 63KB | 63 1721 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63 1722 */ 1723 static const uint16_t hw_rx_buf_size[] = { 1724 HNS3_4K_BD_BUF_SIZE, 1725 HNS3_2K_BD_BUF_SIZE, 1726 HNS3_1K_BD_BUF_SIZE, 1727 HNS3_512_BD_BUF_SIZE 1728 }; 1729 1730 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) - 1731 RTE_PKTMBUF_HEADROOM); 1732 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE) 1733 return -EINVAL; 1734 1735 num_hw_specs = RTE_DIM(hw_rx_buf_size); 1736 for (i = 0; i < num_hw_specs; i++) { 1737 if (vld_buf_size >= hw_rx_buf_size[i]) { 1738 *rx_buf_len = hw_rx_buf_size[i]; 1739 break; 1740 } 1741 } 1742 return 0; 1743 } 1744 1745 static int 1746 hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size, 1747 uint16_t nb_desc) 1748 { 1749 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1750 struct rte_eth_rxmode *rxmode = &hw->data->dev_conf.rxmode; 1751 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 1752 uint16_t min_vec_bds; 1753 1754 /* 1755 * HNS3 hardware network engine set scattered as default. If the driver 1756 * is not work in scattered mode and the pkts greater than buf_size 1757 * but smaller than max_rx_pkt_len will be distributed to multiple BDs. 1758 * Driver cannot handle this situation. 1759 */ 1760 if (!hw->data->scattered_rx && rxmode->max_rx_pkt_len > buf_size) { 1761 hns3_err(hw, "max_rx_pkt_len is not allowed to be set greater " 1762 "than rx_buf_len if scattered is off."); 1763 return -EINVAL; 1764 } 1765 1766 if (pkt_burst == hns3_recv_pkts_vec) { 1767 min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH + 1768 HNS3_DEFAULT_RX_BURST; 1769 if (nb_desc < min_vec_bds || 1770 nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) { 1771 hns3_err(hw, "if Rx burst mode is vector, " 1772 "number of descriptor is required to be " 1773 "bigger than min vector bds:%u, and could be " 1774 "divided by rxq rearm thresh:%u.", 1775 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH); 1776 return -EINVAL; 1777 } 1778 } 1779 return 0; 1780 } 1781 1782 static int 1783 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf, 1784 struct rte_mempool *mp, uint16_t nb_desc, 1785 uint16_t *buf_size) 1786 { 1787 int ret; 1788 1789 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC || 1790 nb_desc % HNS3_ALIGN_RING_DESC) { 1791 hns3_err(hw, "Number (%u) of rx descriptors is invalid", 1792 nb_desc); 1793 return -EINVAL; 1794 } 1795 1796 if (conf->rx_drop_en == 0) 1797 hns3_warn(hw, "if no descriptors available, packets are always " 1798 "dropped and rx_drop_en (1) is fixed on"); 1799 1800 if (hns3_rx_buf_len_calc(mp, buf_size)) { 1801 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! " 1802 "minimal data room size (%u).", 1803 rte_pktmbuf_data_room_size(mp), 1804 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM); 1805 return -EINVAL; 1806 } 1807 1808 if (hw->data->dev_started) { 1809 ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc); 1810 if (ret) { 1811 hns3_err(hw, "Rx queue runtime setup fail."); 1812 return ret; 1813 } 1814 } 1815 1816 return 0; 1817 } 1818 1819 uint32_t 1820 hns3_get_tqp_reg_offset(uint16_t queue_id) 1821 { 1822 uint32_t reg_offset; 1823 1824 /* Need an extend offset to config queue > 1024 */ 1825 if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID) 1826 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE; 1827 else 1828 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET + 1829 (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) * 1830 HNS3_TQP_REG_SIZE; 1831 1832 return reg_offset; 1833 } 1834 1835 int 1836 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, 1837 unsigned int socket_id, const struct rte_eth_rxconf *conf, 1838 struct rte_mempool *mp) 1839 { 1840 struct hns3_adapter *hns = dev->data->dev_private; 1841 struct hns3_hw *hw = &hns->hw; 1842 struct hns3_queue_info q_info; 1843 struct hns3_rx_queue *rxq; 1844 uint16_t rx_buf_size; 1845 int rx_entry_len; 1846 int ret; 1847 1848 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size); 1849 if (ret) 1850 return ret; 1851 1852 if (dev->data->rx_queues[idx]) { 1853 hns3_rx_queue_release(dev->data->rx_queues[idx]); 1854 dev->data->rx_queues[idx] = NULL; 1855 } 1856 1857 q_info.idx = idx; 1858 q_info.socket_id = socket_id; 1859 q_info.nb_desc = nb_desc; 1860 q_info.type = "hns3 RX queue"; 1861 q_info.ring_name = "rx_ring"; 1862 1863 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info); 1864 if (rxq == NULL) { 1865 hns3_err(hw, 1866 "Failed to alloc mem and reserve DMA mem for rx ring!"); 1867 return -ENOMEM; 1868 } 1869 1870 rxq->hns = hns; 1871 rxq->ptype_tbl = &hns->ptype_tbl; 1872 rxq->mb_pool = mp; 1873 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ? 1874 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH; 1875 1876 rxq->rx_deferred_start = conf->rx_deferred_start; 1877 if (rxq->rx_deferred_start && !hns3_dev_get_support(hw, INDEP_TXRX)) { 1878 hns3_warn(hw, "deferred start is not supported."); 1879 rxq->rx_deferred_start = false; 1880 } 1881 1882 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) * 1883 sizeof(struct hns3_entry); 1884 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len, 1885 RTE_CACHE_LINE_SIZE, socket_id); 1886 if (rxq->sw_ring == NULL) { 1887 hns3_err(hw, "Failed to allocate memory for rx sw ring!"); 1888 hns3_rx_queue_release(rxq); 1889 return -ENOMEM; 1890 } 1891 1892 rxq->next_to_use = 0; 1893 rxq->rx_free_hold = 0; 1894 rxq->rx_rearm_start = 0; 1895 rxq->rx_rearm_nb = 0; 1896 rxq->pkt_first_seg = NULL; 1897 rxq->pkt_last_seg = NULL; 1898 rxq->port_id = dev->data->port_id; 1899 /* 1900 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE, 1901 * the pvid_sw_discard_en in the queue struct should not be changed, 1902 * because PVID-related operations do not need to be processed by PMD 1903 * driver. For hns3 VF device, whether it needs to process PVID depends 1904 * on the configuration of PF kernel mode netdevice driver. And the 1905 * related PF configuration is delivered through the mailbox and finally 1906 * reflectd in port_base_vlan_cfg. 1907 */ 1908 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 1909 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state == 1910 HNS3_PORT_BASE_VLAN_ENABLE; 1911 else 1912 rxq->pvid_sw_discard_en = false; 1913 rxq->ptype_en = hns3_dev_get_support(hw, RXD_ADV_LAYOUT) ? true : false; 1914 rxq->configured = true; 1915 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + 1916 idx * HNS3_TQP_REG_SIZE); 1917 rxq->io_base = (void *)((char *)hw->io_base + 1918 hns3_get_tqp_reg_offset(idx)); 1919 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base + 1920 HNS3_RING_RX_HEAD_REG); 1921 rxq->rx_buf_len = rx_buf_size; 1922 memset(&rxq->basic_stats, 0, sizeof(struct hns3_rx_basic_stats)); 1923 memset(&rxq->err_stats, 0, sizeof(struct hns3_rx_bd_errors_stats)); 1924 memset(&rxq->dfx_stats, 0, sizeof(struct hns3_rx_dfx_stats)); 1925 1926 /* CRC len set here is used for amending packet length */ 1927 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 1928 rxq->crc_len = RTE_ETHER_CRC_LEN; 1929 else 1930 rxq->crc_len = 0; 1931 1932 rxq->bulk_mbuf_num = 0; 1933 1934 rte_spinlock_lock(&hw->lock); 1935 dev->data->rx_queues[idx] = rxq; 1936 rte_spinlock_unlock(&hw->lock); 1937 1938 return 0; 1939 } 1940 1941 void 1942 hns3_rx_scattered_reset(struct rte_eth_dev *dev) 1943 { 1944 struct hns3_adapter *hns = dev->data->dev_private; 1945 struct hns3_hw *hw = &hns->hw; 1946 1947 hw->rx_buf_len = 0; 1948 dev->data->scattered_rx = false; 1949 } 1950 1951 void 1952 hns3_rx_scattered_calc(struct rte_eth_dev *dev) 1953 { 1954 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1955 struct hns3_adapter *hns = dev->data->dev_private; 1956 struct hns3_hw *hw = &hns->hw; 1957 struct hns3_rx_queue *rxq; 1958 uint32_t queue_id; 1959 1960 if (dev->data->rx_queues == NULL) 1961 return; 1962 1963 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) { 1964 rxq = dev->data->rx_queues[queue_id]; 1965 if (hw->rx_buf_len == 0) 1966 hw->rx_buf_len = rxq->rx_buf_len; 1967 else 1968 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len, 1969 rxq->rx_buf_len); 1970 } 1971 1972 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SCATTER || 1973 dev_conf->rxmode.max_rx_pkt_len > hw->rx_buf_len) 1974 dev->data->scattered_rx = true; 1975 } 1976 1977 const uint32_t * 1978 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1979 { 1980 static const uint32_t ptypes[] = { 1981 RTE_PTYPE_L2_ETHER, 1982 RTE_PTYPE_L2_ETHER_LLDP, 1983 RTE_PTYPE_L2_ETHER_ARP, 1984 RTE_PTYPE_L3_IPV4, 1985 RTE_PTYPE_L3_IPV4_EXT, 1986 RTE_PTYPE_L3_IPV6, 1987 RTE_PTYPE_L3_IPV6_EXT, 1988 RTE_PTYPE_L4_IGMP, 1989 RTE_PTYPE_L4_ICMP, 1990 RTE_PTYPE_L4_SCTP, 1991 RTE_PTYPE_L4_TCP, 1992 RTE_PTYPE_L4_UDP, 1993 RTE_PTYPE_TUNNEL_GRE, 1994 RTE_PTYPE_INNER_L2_ETHER, 1995 RTE_PTYPE_INNER_L3_IPV4, 1996 RTE_PTYPE_INNER_L3_IPV6, 1997 RTE_PTYPE_INNER_L3_IPV4_EXT, 1998 RTE_PTYPE_INNER_L3_IPV6_EXT, 1999 RTE_PTYPE_INNER_L4_UDP, 2000 RTE_PTYPE_INNER_L4_TCP, 2001 RTE_PTYPE_INNER_L4_SCTP, 2002 RTE_PTYPE_INNER_L4_ICMP, 2003 RTE_PTYPE_TUNNEL_VXLAN, 2004 RTE_PTYPE_TUNNEL_NVGRE, 2005 RTE_PTYPE_UNKNOWN 2006 }; 2007 static const uint32_t adv_layout_ptypes[] = { 2008 RTE_PTYPE_L2_ETHER, 2009 RTE_PTYPE_L2_ETHER_TIMESYNC, 2010 RTE_PTYPE_L2_ETHER_LLDP, 2011 RTE_PTYPE_L2_ETHER_ARP, 2012 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 2013 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 2014 RTE_PTYPE_L4_FRAG, 2015 RTE_PTYPE_L4_NONFRAG, 2016 RTE_PTYPE_L4_UDP, 2017 RTE_PTYPE_L4_TCP, 2018 RTE_PTYPE_L4_SCTP, 2019 RTE_PTYPE_L4_IGMP, 2020 RTE_PTYPE_L4_ICMP, 2021 RTE_PTYPE_TUNNEL_GRE, 2022 RTE_PTYPE_TUNNEL_GRENAT, 2023 RTE_PTYPE_INNER_L2_ETHER, 2024 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 2025 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 2026 RTE_PTYPE_INNER_L4_FRAG, 2027 RTE_PTYPE_INNER_L4_ICMP, 2028 RTE_PTYPE_INNER_L4_NONFRAG, 2029 RTE_PTYPE_INNER_L4_UDP, 2030 RTE_PTYPE_INNER_L4_TCP, 2031 RTE_PTYPE_INNER_L4_SCTP, 2032 RTE_PTYPE_INNER_L4_ICMP, 2033 RTE_PTYPE_UNKNOWN 2034 }; 2035 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2036 2037 if (dev->rx_pkt_burst == hns3_recv_pkts_simple || 2038 dev->rx_pkt_burst == hns3_recv_scattered_pkts || 2039 dev->rx_pkt_burst == hns3_recv_pkts_vec || 2040 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) { 2041 if (hns3_dev_get_support(hw, RXD_ADV_LAYOUT)) 2042 return adv_layout_ptypes; 2043 else 2044 return ptypes; 2045 } 2046 2047 return NULL; 2048 } 2049 2050 static void 2051 hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl) 2052 { 2053 tbl->l3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4; 2054 tbl->l3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6; 2055 tbl->l3table[2] = RTE_PTYPE_L2_ETHER_ARP; 2056 tbl->l3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT; 2057 tbl->l3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT; 2058 tbl->l3table[6] = RTE_PTYPE_L2_ETHER_LLDP; 2059 2060 tbl->l4table[0] = RTE_PTYPE_L4_UDP; 2061 tbl->l4table[1] = RTE_PTYPE_L4_TCP; 2062 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE; 2063 tbl->l4table[3] = RTE_PTYPE_L4_SCTP; 2064 tbl->l4table[4] = RTE_PTYPE_L4_IGMP; 2065 tbl->l4table[5] = RTE_PTYPE_L4_ICMP; 2066 } 2067 2068 static void 2069 hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl) 2070 { 2071 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L2_ETHER | 2072 RTE_PTYPE_INNER_L3_IPV4; 2073 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L2_ETHER | 2074 RTE_PTYPE_INNER_L3_IPV6; 2075 /* There is not a ptype for inner ARP/RARP */ 2076 tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN; 2077 tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN; 2078 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L2_ETHER | 2079 RTE_PTYPE_INNER_L3_IPV4_EXT; 2080 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L2_ETHER | 2081 RTE_PTYPE_INNER_L3_IPV6_EXT; 2082 2083 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP; 2084 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP; 2085 /* There is not a ptype for inner GRE */ 2086 tbl->inner_l4table[2] = RTE_PTYPE_UNKNOWN; 2087 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP; 2088 /* There is not a ptype for inner IGMP */ 2089 tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN; 2090 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP; 2091 2092 tbl->ol3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4; 2093 tbl->ol3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6; 2094 tbl->ol3table[2] = RTE_PTYPE_UNKNOWN; 2095 tbl->ol3table[3] = RTE_PTYPE_UNKNOWN; 2096 tbl->ol3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT; 2097 tbl->ol3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT; 2098 2099 tbl->ol4table[0] = RTE_PTYPE_UNKNOWN; 2100 tbl->ol4table[1] = RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN; 2101 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE; 2102 } 2103 2104 static void 2105 hns3_init_adv_layout_ptype(struct hns3_ptype_table *tbl) 2106 { 2107 uint32_t *ptype = tbl->ptype; 2108 2109 /* Non-tunnel L2 */ 2110 ptype[1] = RTE_PTYPE_L2_ETHER_ARP; 2111 ptype[3] = RTE_PTYPE_L2_ETHER_LLDP; 2112 ptype[8] = RTE_PTYPE_L2_ETHER_TIMESYNC; 2113 2114 /* Non-tunnel IPv4 */ 2115 ptype[17] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2116 RTE_PTYPE_L4_FRAG; 2117 ptype[18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2118 RTE_PTYPE_L4_NONFRAG; 2119 ptype[19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2120 RTE_PTYPE_L4_UDP; 2121 ptype[20] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2122 RTE_PTYPE_L4_TCP; 2123 ptype[21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2124 RTE_PTYPE_TUNNEL_GRE; 2125 ptype[22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2126 RTE_PTYPE_L4_SCTP; 2127 ptype[23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2128 RTE_PTYPE_L4_IGMP; 2129 ptype[24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2130 RTE_PTYPE_L4_ICMP; 2131 /* The next ptype is PTP over IPv4 + UDP */ 2132 ptype[25] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2133 RTE_PTYPE_L4_UDP; 2134 2135 /* IPv4 --> GRE/Teredo/VXLAN */ 2136 ptype[29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2137 RTE_PTYPE_TUNNEL_GRENAT; 2138 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */ 2139 ptype[30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2140 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER; 2141 2142 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */ 2143 ptype[31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2144 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2145 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2146 RTE_PTYPE_INNER_L4_FRAG; 2147 ptype[32] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2148 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2149 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2150 RTE_PTYPE_INNER_L4_NONFRAG; 2151 ptype[33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2152 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2153 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2154 RTE_PTYPE_INNER_L4_UDP; 2155 ptype[34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2156 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2158 RTE_PTYPE_INNER_L4_TCP; 2159 ptype[35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2160 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2161 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2162 RTE_PTYPE_INNER_L4_SCTP; 2163 /* The next ptype's inner L4 is IGMP */ 2164 ptype[36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2165 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2166 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 2167 ptype[37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2168 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2169 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2170 RTE_PTYPE_INNER_L4_ICMP; 2171 2172 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */ 2173 ptype[39] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2174 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2175 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2176 RTE_PTYPE_INNER_L4_FRAG; 2177 ptype[40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2178 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2180 RTE_PTYPE_INNER_L4_NONFRAG; 2181 ptype[41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2182 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2183 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2184 RTE_PTYPE_INNER_L4_UDP; 2185 ptype[42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2186 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2187 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2188 RTE_PTYPE_INNER_L4_TCP; 2189 ptype[43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2190 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2191 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2192 RTE_PTYPE_INNER_L4_SCTP; 2193 /* The next ptype's inner L4 is IGMP */ 2194 ptype[44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2195 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2196 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 2197 ptype[45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2198 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2199 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2200 RTE_PTYPE_INNER_L4_ICMP; 2201 2202 /* Non-tunnel IPv6 */ 2203 ptype[111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2204 RTE_PTYPE_L4_FRAG; 2205 ptype[112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2206 RTE_PTYPE_L4_NONFRAG; 2207 ptype[113] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2208 RTE_PTYPE_L4_UDP; 2209 ptype[114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2210 RTE_PTYPE_L4_TCP; 2211 ptype[115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2212 RTE_PTYPE_TUNNEL_GRE; 2213 ptype[116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2214 RTE_PTYPE_L4_SCTP; 2215 ptype[117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2216 RTE_PTYPE_L4_IGMP; 2217 ptype[118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2218 RTE_PTYPE_L4_ICMP; 2219 /* Special for PTP over IPv6 + UDP */ 2220 ptype[119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2221 RTE_PTYPE_L4_UDP; 2222 2223 /* IPv6 --> GRE/Teredo/VXLAN */ 2224 ptype[123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2225 RTE_PTYPE_TUNNEL_GRENAT; 2226 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */ 2227 ptype[124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2228 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER; 2229 2230 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */ 2231 ptype[125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2232 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2233 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2234 RTE_PTYPE_INNER_L4_FRAG; 2235 ptype[126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2236 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2237 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2238 RTE_PTYPE_INNER_L4_NONFRAG; 2239 ptype[127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2240 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2241 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2242 RTE_PTYPE_INNER_L4_UDP; 2243 ptype[128] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2244 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2246 RTE_PTYPE_INNER_L4_TCP; 2247 ptype[129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2248 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2249 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2250 RTE_PTYPE_INNER_L4_SCTP; 2251 /* The next ptype's inner L4 is IGMP */ 2252 ptype[130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2253 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2254 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 2255 ptype[131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2256 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2258 RTE_PTYPE_INNER_L4_ICMP; 2259 2260 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */ 2261 ptype[133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2262 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2263 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2264 RTE_PTYPE_INNER_L4_FRAG; 2265 ptype[134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2266 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2268 RTE_PTYPE_INNER_L4_NONFRAG; 2269 ptype[135] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2270 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2271 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2272 RTE_PTYPE_INNER_L4_UDP; 2273 ptype[136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2274 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2275 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2276 RTE_PTYPE_INNER_L4_TCP; 2277 ptype[137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2278 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2279 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2280 RTE_PTYPE_INNER_L4_SCTP; 2281 /* The next ptype's inner L4 is IGMP */ 2282 ptype[138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2283 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2284 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 2285 ptype[139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2286 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2287 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2288 RTE_PTYPE_INNER_L4_ICMP; 2289 } 2290 2291 void 2292 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev) 2293 { 2294 struct hns3_adapter *hns = dev->data->dev_private; 2295 struct hns3_ptype_table *tbl = &hns->ptype_tbl; 2296 2297 memset(tbl, 0, sizeof(*tbl)); 2298 2299 hns3_init_non_tunnel_ptype_tbl(tbl); 2300 hns3_init_tunnel_ptype_tbl(tbl); 2301 hns3_init_adv_layout_ptype(tbl); 2302 } 2303 2304 static inline void 2305 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb, 2306 uint32_t l234_info, const struct hns3_desc *rxd) 2307 { 2308 #define HNS3_STRP_STATUS_NUM 0x4 2309 2310 #define HNS3_NO_STRP_VLAN_VLD 0x0 2311 #define HNS3_INNER_STRP_VLAN_VLD 0x1 2312 #define HNS3_OUTER_STRP_VLAN_VLD 0x2 2313 uint32_t strip_status; 2314 uint32_t report_mode; 2315 2316 /* 2317 * Since HW limitation, the vlan tag will always be inserted into RX 2318 * descriptor when strip the tag from packet, driver needs to determine 2319 * reporting which tag to mbuf according to the PVID configuration 2320 * and vlan striped status. 2321 */ 2322 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = { 2323 { 2324 HNS3_NO_STRP_VLAN_VLD, 2325 HNS3_OUTER_STRP_VLAN_VLD, 2326 HNS3_INNER_STRP_VLAN_VLD, 2327 HNS3_OUTER_STRP_VLAN_VLD 2328 }, 2329 { 2330 HNS3_NO_STRP_VLAN_VLD, 2331 HNS3_NO_STRP_VLAN_VLD, 2332 HNS3_NO_STRP_VLAN_VLD, 2333 HNS3_INNER_STRP_VLAN_VLD 2334 } 2335 }; 2336 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M, 2337 HNS3_RXD_STRP_TAGP_S); 2338 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status]; 2339 switch (report_mode) { 2340 case HNS3_NO_STRP_VLAN_VLD: 2341 mb->vlan_tci = 0; 2342 return; 2343 case HNS3_INNER_STRP_VLAN_VLD: 2344 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 2345 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag); 2346 return; 2347 case HNS3_OUTER_STRP_VLAN_VLD: 2348 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 2349 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag); 2350 return; 2351 default: 2352 mb->vlan_tci = 0; 2353 return; 2354 } 2355 } 2356 2357 static inline void 2358 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg, 2359 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq, 2360 uint16_t data_len) 2361 { 2362 uint8_t crc_len = rxq->crc_len; 2363 2364 if (data_len <= crc_len) { 2365 rte_pktmbuf_free_seg(rxm); 2366 first_seg->nb_segs--; 2367 last_seg->data_len = (uint16_t)(last_seg->data_len - 2368 (crc_len - data_len)); 2369 last_seg->next = NULL; 2370 } else 2371 rxm->data_len = (uint16_t)(data_len - crc_len); 2372 } 2373 2374 static inline struct rte_mbuf * 2375 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq) 2376 { 2377 int ret; 2378 2379 if (likely(rxq->bulk_mbuf_num > 0)) 2380 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num]; 2381 2382 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf, 2383 HNS3_BULK_ALLOC_MBUF_NUM); 2384 if (likely(ret == 0)) { 2385 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM; 2386 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num]; 2387 } else 2388 return rte_mbuf_raw_alloc(rxq->mb_pool); 2389 } 2390 2391 static inline void 2392 hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf, 2393 volatile struct hns3_desc *rxd) 2394 { 2395 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns); 2396 uint64_t timestamp = rte_le_to_cpu_64(rxd->timestamp); 2397 2398 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST; 2399 if (hns3_timestamp_rx_dynflag > 0) { 2400 *RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset, 2401 rte_mbuf_timestamp_t *) = timestamp; 2402 mbuf->ol_flags |= hns3_timestamp_rx_dynflag; 2403 } 2404 2405 pf->rx_timestamp = timestamp; 2406 } 2407 2408 uint16_t 2409 hns3_recv_pkts_simple(void *rx_queue, 2410 struct rte_mbuf **rx_pkts, 2411 uint16_t nb_pkts) 2412 { 2413 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */ 2414 volatile struct hns3_desc *rxdp; /* pointer of the current desc */ 2415 struct hns3_rx_queue *rxq; /* RX queue */ 2416 struct hns3_entry *sw_ring; 2417 struct hns3_entry *rxe; 2418 struct hns3_desc rxd; 2419 struct rte_mbuf *nmb; /* pointer of the new mbuf */ 2420 struct rte_mbuf *rxm; 2421 uint32_t bd_base_info; 2422 uint32_t l234_info; 2423 uint32_t ol_info; 2424 uint64_t dma_addr; 2425 uint16_t nb_rx_bd; 2426 uint16_t nb_rx; 2427 uint16_t rx_id; 2428 int ret; 2429 2430 nb_rx = 0; 2431 nb_rx_bd = 0; 2432 rxq = rx_queue; 2433 rx_ring = rxq->rx_ring; 2434 sw_ring = rxq->sw_ring; 2435 rx_id = rxq->next_to_use; 2436 2437 while (nb_rx < nb_pkts) { 2438 rxdp = &rx_ring[rx_id]; 2439 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); 2440 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 2441 break; 2442 2443 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) - 2444 (1u << HNS3_RXD_VLD_B)]; 2445 2446 nmb = hns3_rx_alloc_buffer(rxq); 2447 if (unlikely(nmb == NULL)) { 2448 uint16_t port_id; 2449 2450 port_id = rxq->port_id; 2451 rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++; 2452 break; 2453 } 2454 2455 nb_rx_bd++; 2456 rxe = &sw_ring[rx_id]; 2457 rx_id++; 2458 if (unlikely(rx_id == rxq->nb_rx_desc)) 2459 rx_id = 0; 2460 2461 rte_prefetch0(sw_ring[rx_id].mbuf); 2462 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) { 2463 rte_prefetch0(&rx_ring[rx_id]); 2464 rte_prefetch0(&sw_ring[rx_id]); 2465 } 2466 2467 rxm = rxe->mbuf; 2468 rxm->ol_flags = 0; 2469 rxe->mbuf = nmb; 2470 2471 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) 2472 hns3_rx_ptp_timestamp_handle(rxq, rxm, rxdp); 2473 2474 dma_addr = rte_mbuf_data_iova_default(nmb); 2475 rxdp->addr = rte_cpu_to_le_64(dma_addr); 2476 rxdp->rx.bd_base_info = 0; 2477 2478 rxm->data_off = RTE_PKTMBUF_HEADROOM; 2479 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) - 2480 rxq->crc_len; 2481 rxm->data_len = rxm->pkt_len; 2482 rxm->port = rxq->port_id; 2483 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash); 2484 rxm->ol_flags |= PKT_RX_RSS_HASH; 2485 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) { 2486 rxm->hash.fdir.hi = 2487 rte_le_to_cpu_16(rxd.rx.fd_id); 2488 rxm->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID; 2489 } 2490 rxm->nb_segs = 1; 2491 rxm->next = NULL; 2492 2493 /* Load remained descriptor data and extract necessary fields */ 2494 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info); 2495 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info); 2496 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info, l234_info); 2497 if (unlikely(ret)) 2498 goto pkt_err; 2499 2500 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info); 2501 2502 if (rxm->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) 2503 rxm->ol_flags |= PKT_RX_IEEE1588_PTP; 2504 2505 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd); 2506 2507 /* Increment bytes counter */ 2508 rxq->basic_stats.bytes += rxm->pkt_len; 2509 2510 rx_pkts[nb_rx++] = rxm; 2511 continue; 2512 pkt_err: 2513 rte_pktmbuf_free(rxm); 2514 } 2515 2516 rxq->next_to_use = rx_id; 2517 rxq->rx_free_hold += nb_rx_bd; 2518 if (rxq->rx_free_hold > rxq->rx_free_thresh) { 2519 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold); 2520 rxq->rx_free_hold = 0; 2521 } 2522 2523 return nb_rx; 2524 } 2525 2526 uint16_t 2527 hns3_recv_scattered_pkts(void *rx_queue, 2528 struct rte_mbuf **rx_pkts, 2529 uint16_t nb_pkts) 2530 { 2531 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */ 2532 volatile struct hns3_desc *rxdp; /* pointer of the current desc */ 2533 struct hns3_rx_queue *rxq; /* RX queue */ 2534 struct hns3_entry *sw_ring; 2535 struct hns3_entry *rxe; 2536 struct rte_mbuf *first_seg; 2537 struct rte_mbuf *last_seg; 2538 struct hns3_desc rxd; 2539 struct rte_mbuf *nmb; /* pointer of the new mbuf */ 2540 struct rte_mbuf *rxm; 2541 struct rte_eth_dev *dev; 2542 uint32_t bd_base_info; 2543 uint32_t l234_info; 2544 uint32_t gro_size; 2545 uint32_t ol_info; 2546 uint64_t dma_addr; 2547 uint16_t nb_rx_bd; 2548 uint16_t nb_rx; 2549 uint16_t rx_id; 2550 int ret; 2551 2552 nb_rx = 0; 2553 nb_rx_bd = 0; 2554 rxq = rx_queue; 2555 2556 rx_id = rxq->next_to_use; 2557 rx_ring = rxq->rx_ring; 2558 sw_ring = rxq->sw_ring; 2559 first_seg = rxq->pkt_first_seg; 2560 last_seg = rxq->pkt_last_seg; 2561 2562 while (nb_rx < nb_pkts) { 2563 rxdp = &rx_ring[rx_id]; 2564 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); 2565 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 2566 break; 2567 2568 /* 2569 * The interactive process between software and hardware of 2570 * receiving a new packet in hns3 network engine: 2571 * 1. Hardware network engine firstly writes the packet content 2572 * to the memory pointed by the 'addr' field of the Rx Buffer 2573 * Descriptor, secondly fills the result of parsing the 2574 * packet include the valid field into the Rx Buffer 2575 * Descriptor in one write operation. 2576 * 2. Driver reads the Rx BD's valid field in the loop to check 2577 * whether it's valid, if valid then assign a new address to 2578 * the addr field, clear the valid field, get the other 2579 * information of the packet by parsing Rx BD's other fields, 2580 * finally write back the number of Rx BDs processed by the 2581 * driver to the HNS3_RING_RX_HEAD_REG register to inform 2582 * hardware. 2583 * In the above process, the ordering is very important. We must 2584 * make sure that CPU read Rx BD's other fields only after the 2585 * Rx BD is valid. 2586 * 2587 * There are two type of re-ordering: compiler re-ordering and 2588 * CPU re-ordering under the ARMv8 architecture. 2589 * 1. we use volatile to deal with compiler re-ordering, so you 2590 * can see that rx_ring/rxdp defined with volatile. 2591 * 2. we commonly use memory barrier to deal with CPU 2592 * re-ordering, but the cost is high. 2593 * 2594 * In order to solve the high cost of using memory barrier, we 2595 * use the data dependency order under the ARMv8 architecture, 2596 * for example: 2597 * instr01: load A 2598 * instr02: load B <- A 2599 * the instr02 will always execute after instr01. 2600 * 2601 * To construct the data dependency ordering, we use the 2602 * following assignment: 2603 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) - 2604 * (1u<<HNS3_RXD_VLD_B)] 2605 * Using gcc compiler under the ARMv8 architecture, the related 2606 * assembly code example as follows: 2607 * note: (1u << HNS3_RXD_VLD_B) equal 0x10 2608 * instr01: ldr w26, [x22, #28] --read bd_base_info 2609 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10 2610 * instr03: sub w0, w0, #0x10 --calc (bd_base_info & 2611 * 0x10) - 0x10 2612 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr 2613 * instr05: ldp x2, x3, [x0] 2614 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B 2615 * instr07: ldp x4, x5, [x0, #16] 2616 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B 2617 * the instr05~08 depend on x0's value, x0 depent on w26's 2618 * value, the w26 is the bd_base_info, this form the data 2619 * dependency ordering. 2620 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) - 2621 * (1u<<HNS3_RXD_VLD_B) will always zero, so the 2622 * assignment is correct. 2623 * 2624 * So we use the data dependency ordering instead of memory 2625 * barrier to improve receive performance. 2626 */ 2627 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) - 2628 (1u << HNS3_RXD_VLD_B)]; 2629 2630 nmb = hns3_rx_alloc_buffer(rxq); 2631 if (unlikely(nmb == NULL)) { 2632 dev = &rte_eth_devices[rxq->port_id]; 2633 dev->data->rx_mbuf_alloc_failed++; 2634 break; 2635 } 2636 2637 nb_rx_bd++; 2638 rxe = &sw_ring[rx_id]; 2639 rx_id++; 2640 if (unlikely(rx_id == rxq->nb_rx_desc)) 2641 rx_id = 0; 2642 2643 rte_prefetch0(sw_ring[rx_id].mbuf); 2644 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) { 2645 rte_prefetch0(&rx_ring[rx_id]); 2646 rte_prefetch0(&sw_ring[rx_id]); 2647 } 2648 2649 rxm = rxe->mbuf; 2650 rxe->mbuf = nmb; 2651 2652 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb)); 2653 rxdp->rx.bd_base_info = 0; 2654 rxdp->addr = dma_addr; 2655 2656 if (first_seg == NULL) { 2657 first_seg = rxm; 2658 first_seg->nb_segs = 1; 2659 } else { 2660 first_seg->nb_segs++; 2661 last_seg->next = rxm; 2662 } 2663 2664 rxm->data_off = RTE_PKTMBUF_HEADROOM; 2665 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size); 2666 2667 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { 2668 last_seg = rxm; 2669 rxm->next = NULL; 2670 continue; 2671 } 2672 2673 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) 2674 hns3_rx_ptp_timestamp_handle(rxq, first_seg, rxdp); 2675 2676 /* 2677 * The last buffer of the received packet. packet len from 2678 * buffer description may contains CRC len, packet len should 2679 * subtract it, same as data len. 2680 */ 2681 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len); 2682 2683 /* 2684 * This is the last buffer of the received packet. If the CRC 2685 * is not stripped by the hardware: 2686 * - Subtract the CRC length from the total packet length. 2687 * - If the last buffer only contains the whole CRC or a part 2688 * of it, free the mbuf associated to the last buffer. If part 2689 * of the CRC is also contained in the previous mbuf, subtract 2690 * the length of that CRC part from the data length of the 2691 * previous mbuf. 2692 */ 2693 rxm->next = NULL; 2694 if (unlikely(rxq->crc_len > 0)) { 2695 first_seg->pkt_len -= rxq->crc_len; 2696 recalculate_data_len(first_seg, last_seg, rxm, rxq, 2697 rxm->data_len); 2698 } 2699 2700 first_seg->port = rxq->port_id; 2701 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash); 2702 first_seg->ol_flags = PKT_RX_RSS_HASH; 2703 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) { 2704 first_seg->hash.fdir.hi = 2705 rte_le_to_cpu_16(rxd.rx.fd_id); 2706 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID; 2707 } 2708 2709 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M, 2710 HNS3_RXD_GRO_SIZE_S); 2711 if (gro_size != 0) { 2712 first_seg->ol_flags |= PKT_RX_LRO; 2713 first_seg->tso_segsz = gro_size; 2714 } 2715 2716 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info); 2717 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info); 2718 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info, 2719 l234_info); 2720 if (unlikely(ret)) 2721 goto pkt_err; 2722 2723 first_seg->packet_type = hns3_rx_calc_ptype(rxq, 2724 l234_info, ol_info); 2725 2726 if (first_seg->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) 2727 rxm->ol_flags |= PKT_RX_IEEE1588_PTP; 2728 2729 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd); 2730 2731 /* Increment bytes counter */ 2732 rxq->basic_stats.bytes += first_seg->pkt_len; 2733 2734 rx_pkts[nb_rx++] = first_seg; 2735 first_seg = NULL; 2736 continue; 2737 pkt_err: 2738 rte_pktmbuf_free(first_seg); 2739 first_seg = NULL; 2740 } 2741 2742 rxq->next_to_use = rx_id; 2743 rxq->pkt_first_seg = first_seg; 2744 rxq->pkt_last_seg = last_seg; 2745 2746 rxq->rx_free_hold += nb_rx_bd; 2747 if (rxq->rx_free_hold > rxq->rx_free_thresh) { 2748 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold); 2749 rxq->rx_free_hold = 0; 2750 } 2751 2752 return nb_rx; 2753 } 2754 2755 void __rte_weak 2756 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq) 2757 { 2758 } 2759 2760 int __rte_weak 2761 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev) 2762 { 2763 return -ENOTSUP; 2764 } 2765 2766 uint16_t __rte_weak 2767 hns3_recv_pkts_vec(__rte_unused void *tx_queue, 2768 __rte_unused struct rte_mbuf **rx_pkts, 2769 __rte_unused uint16_t nb_pkts) 2770 { 2771 return 0; 2772 } 2773 2774 uint16_t __rte_weak 2775 hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue, 2776 __rte_unused struct rte_mbuf **rx_pkts, 2777 __rte_unused uint16_t nb_pkts) 2778 { 2779 return 0; 2780 } 2781 2782 int 2783 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2784 struct rte_eth_burst_mode *mode) 2785 { 2786 static const struct { 2787 eth_rx_burst_t pkt_burst; 2788 const char *info; 2789 } burst_infos[] = { 2790 { hns3_recv_pkts_simple, "Scalar Simple" }, 2791 { hns3_recv_scattered_pkts, "Scalar Scattered" }, 2792 { hns3_recv_pkts_vec, "Vector Neon" }, 2793 { hns3_recv_pkts_vec_sve, "Vector Sve" }, 2794 }; 2795 2796 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2797 int ret = -EINVAL; 2798 unsigned int i; 2799 2800 for (i = 0; i < RTE_DIM(burst_infos); i++) { 2801 if (pkt_burst == burst_infos[i].pkt_burst) { 2802 snprintf(mode->info, sizeof(mode->info), "%s", 2803 burst_infos[i].info); 2804 ret = 0; 2805 break; 2806 } 2807 } 2808 2809 return ret; 2810 } 2811 2812 static bool 2813 hns3_get_default_vec_support(void) 2814 { 2815 #if defined(RTE_ARCH_ARM64) 2816 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) 2817 return false; 2818 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) 2819 return true; 2820 #endif 2821 return false; 2822 } 2823 2824 static bool 2825 hns3_get_sve_support(void) 2826 { 2827 #if defined(RTE_HAS_SVE_ACLE) 2828 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) 2829 return false; 2830 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) 2831 return true; 2832 #endif 2833 return false; 2834 } 2835 2836 static eth_rx_burst_t 2837 hns3_get_rx_function(struct rte_eth_dev *dev) 2838 { 2839 struct hns3_adapter *hns = dev->data->dev_private; 2840 uint64_t offloads = dev->data->dev_conf.rxmode.offloads; 2841 bool vec_allowed, sve_allowed, simple_allowed; 2842 bool vec_support; 2843 2844 vec_support = hns3_rx_check_vec_support(dev) == 0; 2845 vec_allowed = vec_support && hns3_get_default_vec_support(); 2846 sve_allowed = vec_support && hns3_get_sve_support(); 2847 simple_allowed = !dev->data->scattered_rx && 2848 (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0; 2849 2850 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) 2851 return hns3_recv_pkts_vec; 2852 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) 2853 return hns3_recv_pkts_vec_sve; 2854 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) 2855 return hns3_recv_pkts_simple; 2856 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON) 2857 return hns3_recv_scattered_pkts; 2858 2859 if (vec_allowed) 2860 return hns3_recv_pkts_vec; 2861 if (simple_allowed) 2862 return hns3_recv_pkts_simple; 2863 2864 return hns3_recv_scattered_pkts; 2865 } 2866 2867 static int 2868 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf, 2869 uint16_t nb_desc, uint16_t *tx_rs_thresh, 2870 uint16_t *tx_free_thresh, uint16_t idx) 2871 { 2872 #define HNS3_TX_RS_FREE_THRESH_GAP 8 2873 uint16_t rs_thresh, free_thresh, fast_free_thresh; 2874 2875 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC || 2876 nb_desc % HNS3_ALIGN_RING_DESC) { 2877 hns3_err(hw, "number (%u) of tx descriptors is invalid", 2878 nb_desc); 2879 return -EINVAL; 2880 } 2881 2882 rs_thresh = (conf->tx_rs_thresh > 0) ? 2883 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH; 2884 free_thresh = (conf->tx_free_thresh > 0) ? 2885 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH; 2886 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh || 2887 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP || 2888 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) { 2889 hns3_err(hw, "tx_rs_thresh (%u) tx_free_thresh (%u) nb_desc " 2890 "(%u) of tx descriptors for port=%u queue=%u check " 2891 "fail!", 2892 rs_thresh, free_thresh, nb_desc, hw->data->port_id, 2893 idx); 2894 return -EINVAL; 2895 } 2896 2897 if (conf->tx_free_thresh == 0) { 2898 /* Fast free Tx memory buffer to improve cache hit rate */ 2899 fast_free_thresh = nb_desc - rs_thresh; 2900 if (fast_free_thresh >= 2901 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH) 2902 free_thresh = fast_free_thresh - 2903 HNS3_TX_FAST_FREE_AHEAD; 2904 } 2905 2906 *tx_rs_thresh = rs_thresh; 2907 *tx_free_thresh = free_thresh; 2908 return 0; 2909 } 2910 2911 static void * 2912 hns3_tx_push_get_queue_tail_reg(struct rte_eth_dev *dev, uint16_t queue_id) 2913 { 2914 #define HNS3_TX_PUSH_TQP_REGION_SIZE 0x10000 2915 #define HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET 64 2916 #define HNS3_TX_PUSH_PCI_BAR_INDEX 4 2917 2918 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 2919 uint8_t bar_id = HNS3_TX_PUSH_PCI_BAR_INDEX; 2920 2921 /* 2922 * If device support Tx push then its PCIe bar45 must exist, and DPDK 2923 * framework will mmap the bar45 default in PCI probe stage. 2924 * 2925 * In the bar45, the first half is for RoCE (RDMA over Converged 2926 * Ethernet), and the second half is for NIC, every TQP occupy 64KB. 2927 * 2928 * The quick doorbell located at 64B offset in the TQP region. 2929 */ 2930 return (char *)pci_dev->mem_resource[bar_id].addr + 2931 (pci_dev->mem_resource[bar_id].len >> 1) + 2932 HNS3_TX_PUSH_TQP_REGION_SIZE * queue_id + 2933 HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET; 2934 } 2935 2936 void 2937 hns3_tx_push_init(struct rte_eth_dev *dev) 2938 { 2939 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2940 volatile uint32_t *reg; 2941 uint32_t val; 2942 2943 if (!hns3_dev_get_support(hw, TX_PUSH)) 2944 return; 2945 2946 reg = (volatile uint32_t *)hns3_tx_push_get_queue_tail_reg(dev, 0); 2947 /* 2948 * Because the size of bar45 is about 8GB size, it may take a long time 2949 * to do the page fault in Tx process when work with vfio-pci, so use 2950 * one read operation to make kernel setup page table mapping for bar45 2951 * in the init stage. 2952 * Note: the bar45 is readable but the result is all 1. 2953 */ 2954 val = *reg; 2955 RTE_SET_USED(val); 2956 } 2957 2958 static void 2959 hns3_tx_push_queue_init(struct rte_eth_dev *dev, 2960 uint16_t queue_id, 2961 struct hns3_tx_queue *txq) 2962 { 2963 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2964 if (!hns3_dev_get_support(hw, TX_PUSH)) { 2965 txq->tx_push_enable = false; 2966 return; 2967 } 2968 2969 txq->io_tail_reg = (volatile void *)hns3_tx_push_get_queue_tail_reg(dev, 2970 queue_id); 2971 txq->tx_push_enable = true; 2972 } 2973 2974 int 2975 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, 2976 unsigned int socket_id, const struct rte_eth_txconf *conf) 2977 { 2978 struct hns3_adapter *hns = dev->data->dev_private; 2979 uint16_t tx_rs_thresh, tx_free_thresh; 2980 struct hns3_hw *hw = &hns->hw; 2981 struct hns3_queue_info q_info; 2982 struct hns3_tx_queue *txq; 2983 int tx_entry_len; 2984 int ret; 2985 2986 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc, 2987 &tx_rs_thresh, &tx_free_thresh, idx); 2988 if (ret) 2989 return ret; 2990 2991 if (dev->data->tx_queues[idx] != NULL) { 2992 hns3_tx_queue_release(dev->data->tx_queues[idx]); 2993 dev->data->tx_queues[idx] = NULL; 2994 } 2995 2996 q_info.idx = idx; 2997 q_info.socket_id = socket_id; 2998 q_info.nb_desc = nb_desc; 2999 q_info.type = "hns3 TX queue"; 3000 q_info.ring_name = "tx_ring"; 3001 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info); 3002 if (txq == NULL) { 3003 hns3_err(hw, 3004 "Failed to alloc mem and reserve DMA mem for tx ring!"); 3005 return -ENOMEM; 3006 } 3007 3008 txq->tx_deferred_start = conf->tx_deferred_start; 3009 if (txq->tx_deferred_start && !hns3_dev_get_support(hw, INDEP_TXRX)) { 3010 hns3_warn(hw, "deferred start is not supported."); 3011 txq->tx_deferred_start = false; 3012 } 3013 3014 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc; 3015 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len, 3016 RTE_CACHE_LINE_SIZE, socket_id); 3017 if (txq->sw_ring == NULL) { 3018 hns3_err(hw, "Failed to allocate memory for tx sw ring!"); 3019 hns3_tx_queue_release(txq); 3020 return -ENOMEM; 3021 } 3022 3023 txq->hns = hns; 3024 txq->next_to_use = 0; 3025 txq->next_to_clean = 0; 3026 txq->tx_bd_ready = txq->nb_tx_desc - 1; 3027 txq->tx_free_thresh = tx_free_thresh; 3028 txq->tx_rs_thresh = tx_rs_thresh; 3029 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array", 3030 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh, 3031 RTE_CACHE_LINE_SIZE, socket_id); 3032 if (!txq->free) { 3033 hns3_err(hw, "failed to allocate tx mbuf free array!"); 3034 hns3_tx_queue_release(txq); 3035 return -ENOMEM; 3036 } 3037 3038 txq->port_id = dev->data->port_id; 3039 /* 3040 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE, 3041 * the pvid_sw_shift_en in the queue struct should not be changed, 3042 * because PVID-related operations do not need to be processed by PMD 3043 * driver. For hns3 VF device, whether it needs to process PVID depends 3044 * on the configuration of PF kernel mode netdev driver. And the 3045 * related PF configuration is delivered through the mailbox and finally 3046 * reflectd in port_base_vlan_cfg. 3047 */ 3048 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 3049 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state == 3050 HNS3_PORT_BASE_VLAN_ENABLE; 3051 else 3052 txq->pvid_sw_shift_en = false; 3053 txq->max_non_tso_bd_num = hw->max_non_tso_bd_num; 3054 txq->configured = true; 3055 txq->io_base = (void *)((char *)hw->io_base + 3056 hns3_get_tqp_reg_offset(idx)); 3057 txq->io_tail_reg = (volatile void *)((char *)txq->io_base + 3058 HNS3_RING_TX_TAIL_REG); 3059 txq->min_tx_pkt_len = hw->min_tx_pkt_len; 3060 txq->tso_mode = hw->tso_mode; 3061 txq->udp_cksum_mode = hw->udp_cksum_mode; 3062 memset(&txq->basic_stats, 0, sizeof(struct hns3_tx_basic_stats)); 3063 memset(&txq->dfx_stats, 0, sizeof(struct hns3_tx_dfx_stats)); 3064 3065 /* 3066 * Call hns3_tx_push_queue_init after assigned io_tail_reg field because 3067 * it may overwrite the io_tail_reg field. 3068 */ 3069 hns3_tx_push_queue_init(dev, idx, txq); 3070 3071 rte_spinlock_lock(&hw->lock); 3072 dev->data->tx_queues[idx] = txq; 3073 rte_spinlock_unlock(&hw->lock); 3074 3075 return 0; 3076 } 3077 3078 static void 3079 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq) 3080 { 3081 uint16_t tx_next_clean = txq->next_to_clean; 3082 uint16_t tx_next_use = txq->next_to_use; 3083 uint16_t tx_bd_ready = txq->tx_bd_ready; 3084 uint16_t tx_bd_max = txq->nb_tx_desc; 3085 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean]; 3086 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean]; 3087 struct rte_mbuf *mbuf; 3088 3089 while ((!(desc->tx.tp_fe_sc_vld_ra_ri & 3090 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))) && 3091 tx_next_use != tx_next_clean) { 3092 mbuf = tx_bak_pkt->mbuf; 3093 if (mbuf) { 3094 rte_pktmbuf_free_seg(mbuf); 3095 tx_bak_pkt->mbuf = NULL; 3096 } 3097 3098 desc++; 3099 tx_bak_pkt++; 3100 tx_next_clean++; 3101 tx_bd_ready++; 3102 3103 if (tx_next_clean >= tx_bd_max) { 3104 tx_next_clean = 0; 3105 desc = txq->tx_ring; 3106 tx_bak_pkt = txq->sw_ring; 3107 } 3108 } 3109 3110 txq->next_to_clean = tx_next_clean; 3111 txq->tx_bd_ready = tx_bd_ready; 3112 } 3113 3114 int 3115 hns3_config_gro(struct hns3_hw *hw, bool en) 3116 { 3117 struct hns3_cfg_gro_status_cmd *req; 3118 struct hns3_cmd_desc desc; 3119 int ret; 3120 3121 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false); 3122 req = (struct hns3_cfg_gro_status_cmd *)desc.data; 3123 3124 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0); 3125 3126 ret = hns3_cmd_send(hw, &desc, 1); 3127 if (ret) 3128 hns3_err(hw, "%s hardware GRO failed, ret = %d", 3129 en ? "enable" : "disable", ret); 3130 3131 return ret; 3132 } 3133 3134 int 3135 hns3_restore_gro_conf(struct hns3_hw *hw) 3136 { 3137 uint64_t offloads; 3138 bool gro_en; 3139 int ret; 3140 3141 offloads = hw->data->dev_conf.rxmode.offloads; 3142 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 3143 ret = hns3_config_gro(hw, gro_en); 3144 if (ret) 3145 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d", 3146 gro_en ? "enabled" : "disabled", ret); 3147 3148 return ret; 3149 } 3150 3151 static inline bool 3152 hns3_pkt_is_tso(struct rte_mbuf *m) 3153 { 3154 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG); 3155 } 3156 3157 static void 3158 hns3_set_tso(struct hns3_desc *desc, uint32_t paylen, struct rte_mbuf *rxm) 3159 { 3160 if (!hns3_pkt_is_tso(rxm)) 3161 return; 3162 3163 if (paylen <= rxm->tso_segsz) 3164 return; 3165 3166 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B)); 3167 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz); 3168 } 3169 3170 static inline void 3171 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm) 3172 { 3173 desc->addr = rte_mbuf_data_iova(rxm); 3174 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm)); 3175 desc->tx.tp_fe_sc_vld_ra_ri |= rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)); 3176 } 3177 3178 static void 3179 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc, 3180 struct rte_mbuf *rxm) 3181 { 3182 uint64_t ol_flags = rxm->ol_flags; 3183 uint32_t hdr_len; 3184 uint32_t paylen; 3185 3186 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len; 3187 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ? 3188 rxm->outer_l2_len + rxm->outer_l3_len : 0; 3189 paylen = rxm->pkt_len - hdr_len; 3190 desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen); 3191 hns3_set_tso(desc, paylen, rxm); 3192 3193 /* 3194 * Currently, hardware doesn't support more than two layers VLAN offload 3195 * in Tx direction based on hns3 network engine. So when the number of 3196 * VLANs in the packets represented by rxm plus the number of VLAN 3197 * offload by hardware such as PVID etc, exceeds two, the packets will 3198 * be discarded or the original VLAN of the packets will be overwitted 3199 * by hardware. When the PF PVID is enabled by calling the API function 3200 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3 3201 * PF kernel ether driver, the outer VLAN tag will always be the PVID. 3202 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should 3203 * be added to the position close to the IP header when PVID is enabled. 3204 */ 3205 if (!txq->pvid_sw_shift_en && ol_flags & (PKT_TX_VLAN_PKT | 3206 PKT_TX_QINQ_PKT)) { 3207 desc->tx.ol_type_vlan_len_msec |= 3208 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B)); 3209 if (ol_flags & PKT_TX_QINQ_PKT) 3210 desc->tx.outer_vlan_tag = 3211 rte_cpu_to_le_16(rxm->vlan_tci_outer); 3212 else 3213 desc->tx.outer_vlan_tag = 3214 rte_cpu_to_le_16(rxm->vlan_tci); 3215 } 3216 3217 if (ol_flags & PKT_TX_QINQ_PKT || 3218 ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_sw_shift_en)) { 3219 desc->tx.type_cs_vlan_tso_len |= 3220 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B)); 3221 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci); 3222 } 3223 3224 if (ol_flags & PKT_TX_IEEE1588_TMST) 3225 desc->tx.tp_fe_sc_vld_ra_ri |= 3226 rte_cpu_to_le_16(BIT(HNS3_TXD_TSYN_B)); 3227 } 3228 3229 static inline int 3230 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf, 3231 struct rte_mbuf **alloc_mbuf) 3232 { 3233 #define MAX_NON_TSO_BD_PER_PKT 18 3234 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT]; 3235 uint16_t i; 3236 3237 /* Allocate enough mbufs */ 3238 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf)) 3239 return -ENOMEM; 3240 3241 for (i = 0; i < nb_new_buf - 1; i++) 3242 pkt_segs[i]->next = pkt_segs[i + 1]; 3243 3244 pkt_segs[nb_new_buf - 1]->next = NULL; 3245 pkt_segs[0]->nb_segs = nb_new_buf; 3246 *alloc_mbuf = pkt_segs[0]; 3247 3248 return 0; 3249 } 3250 3251 static inline void 3252 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt) 3253 { 3254 new_pkt->ol_flags = old_pkt->ol_flags; 3255 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt); 3256 new_pkt->outer_l2_len = old_pkt->outer_l2_len; 3257 new_pkt->outer_l3_len = old_pkt->outer_l3_len; 3258 new_pkt->l2_len = old_pkt->l2_len; 3259 new_pkt->l3_len = old_pkt->l3_len; 3260 new_pkt->l4_len = old_pkt->l4_len; 3261 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer; 3262 new_pkt->vlan_tci = old_pkt->vlan_tci; 3263 } 3264 3265 static int 3266 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt, 3267 uint8_t max_non_tso_bd_num) 3268 { 3269 struct rte_mempool *mb_pool; 3270 struct rte_mbuf *new_mbuf; 3271 struct rte_mbuf *temp_new; 3272 struct rte_mbuf *temp; 3273 uint16_t last_buf_len; 3274 uint16_t nb_new_buf; 3275 uint16_t buf_size; 3276 uint16_t buf_len; 3277 uint16_t len_s; 3278 uint16_t len_d; 3279 uint16_t len; 3280 int ret; 3281 char *s; 3282 char *d; 3283 3284 mb_pool = tx_pkt->pool; 3285 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM; 3286 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1; 3287 if (nb_new_buf > max_non_tso_bd_num) 3288 return -EINVAL; 3289 3290 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size; 3291 if (last_buf_len == 0) 3292 last_buf_len = buf_size; 3293 3294 /* Allocate enough mbufs */ 3295 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf); 3296 if (ret) 3297 return ret; 3298 3299 /* Copy the original packet content to the new mbufs */ 3300 temp = tx_pkt; 3301 s = rte_pktmbuf_mtod(temp, char *); 3302 len_s = rte_pktmbuf_data_len(temp); 3303 temp_new = new_mbuf; 3304 while (temp != NULL && temp_new != NULL) { 3305 d = rte_pktmbuf_mtod(temp_new, char *); 3306 buf_len = temp_new->next == NULL ? last_buf_len : buf_size; 3307 len_d = buf_len; 3308 3309 while (len_d) { 3310 len = RTE_MIN(len_s, len_d); 3311 memcpy(d, s, len); 3312 s = s + len; 3313 d = d + len; 3314 len_d = len_d - len; 3315 len_s = len_s - len; 3316 3317 if (len_s == 0) { 3318 temp = temp->next; 3319 if (temp == NULL) 3320 break; 3321 s = rte_pktmbuf_mtod(temp, char *); 3322 len_s = rte_pktmbuf_data_len(temp); 3323 } 3324 } 3325 3326 temp_new->data_len = buf_len; 3327 temp_new = temp_new->next; 3328 } 3329 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt); 3330 3331 /* free original mbufs */ 3332 rte_pktmbuf_free(tx_pkt); 3333 3334 *new_pkt = new_mbuf; 3335 3336 return 0; 3337 } 3338 3339 static void 3340 hns3_parse_outer_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec) 3341 { 3342 uint32_t tmp = *ol_type_vlan_len_msec; 3343 uint64_t ol_flags = m->ol_flags; 3344 3345 /* (outer) IP header type */ 3346 if (ol_flags & PKT_TX_OUTER_IPV4) { 3347 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) 3348 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, 3349 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM); 3350 else 3351 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, 3352 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_NO_CSUM); 3353 } else if (ol_flags & PKT_TX_OUTER_IPV6) { 3354 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S, 3355 HNS3_OL3T_IPV6); 3356 } 3357 /* OL3 header size, defined in 4 bytes */ 3358 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S, 3359 m->outer_l3_len >> HNS3_L3_LEN_UNIT); 3360 *ol_type_vlan_len_msec = tmp; 3361 } 3362 3363 static int 3364 hns3_parse_inner_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec, 3365 uint32_t *type_cs_vlan_tso_len) 3366 { 3367 #define HNS3_NVGRE_HLEN 8 3368 uint32_t tmp_outer = *ol_type_vlan_len_msec; 3369 uint32_t tmp_inner = *type_cs_vlan_tso_len; 3370 uint64_t ol_flags = m->ol_flags; 3371 uint16_t inner_l2_len; 3372 3373 switch (ol_flags & PKT_TX_TUNNEL_MASK) { 3374 case PKT_TX_TUNNEL_VXLAN_GPE: 3375 case PKT_TX_TUNNEL_GENEVE: 3376 case PKT_TX_TUNNEL_VXLAN: 3377 /* MAC in UDP tunnelling packet, include VxLAN and GENEVE */ 3378 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M, 3379 HNS3_TXD_TUNTYPE_S, HNS3_TUN_MAC_IN_UDP); 3380 /* 3381 * The inner l2 length of mbuf is the sum of outer l4 length, 3382 * tunneling header length and inner l2 length for a tunnel 3383 * packect. But in hns3 tx descriptor, the tunneling header 3384 * length is contained in the field of outer L4 length. 3385 * Therefore, driver need to calculate the outer L4 length and 3386 * inner L2 length. 3387 */ 3388 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, 3389 HNS3_TXD_L4LEN_S, 3390 (uint8_t)RTE_ETHER_VXLAN_HLEN >> 3391 HNS3_L4_LEN_UNIT); 3392 3393 inner_l2_len = m->l2_len - RTE_ETHER_VXLAN_HLEN; 3394 break; 3395 case PKT_TX_TUNNEL_GRE: 3396 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M, 3397 HNS3_TXD_TUNTYPE_S, HNS3_TUN_NVGRE); 3398 /* 3399 * For NVGRE tunnel packect, the outer L4 is empty. So only 3400 * fill the NVGRE header length to the outer L4 field. 3401 */ 3402 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, 3403 HNS3_TXD_L4LEN_S, 3404 (uint8_t)HNS3_NVGRE_HLEN >> HNS3_L4_LEN_UNIT); 3405 3406 inner_l2_len = m->l2_len - HNS3_NVGRE_HLEN; 3407 break; 3408 default: 3409 /* For non UDP / GRE tunneling, drop the tunnel packet */ 3410 return -EINVAL; 3411 } 3412 3413 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S, 3414 inner_l2_len >> HNS3_L2_LEN_UNIT); 3415 /* OL2 header size, defined in 2 bytes */ 3416 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S, 3417 m->outer_l2_len >> HNS3_L2_LEN_UNIT); 3418 3419 *type_cs_vlan_tso_len = tmp_inner; 3420 *ol_type_vlan_len_msec = tmp_outer; 3421 3422 return 0; 3423 } 3424 3425 static int 3426 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, 3427 uint16_t tx_desc_id) 3428 { 3429 struct hns3_desc *tx_ring = txq->tx_ring; 3430 struct hns3_desc *desc = &tx_ring[tx_desc_id]; 3431 uint64_t ol_flags = m->ol_flags; 3432 uint32_t tmp_outer = 0; 3433 uint32_t tmp_inner = 0; 3434 uint32_t tmp_ol4cs; 3435 int ret; 3436 3437 /* 3438 * The tunnel header is contained in the inner L2 header field of the 3439 * mbuf, but for hns3 descriptor, it is contained in the outer L4. So, 3440 * there is a need that switching between them. To avoid multiple 3441 * calculations, the length of the L2 header include the outer and 3442 * inner, will be filled during the parsing of tunnel packects. 3443 */ 3444 if (!(ol_flags & PKT_TX_TUNNEL_MASK)) { 3445 /* 3446 * For non tunnel type the tunnel type id is 0, so no need to 3447 * assign a value to it. Only the inner(normal) L2 header length 3448 * is assigned. 3449 */ 3450 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, 3451 HNS3_TXD_L2LEN_S, m->l2_len >> HNS3_L2_LEN_UNIT); 3452 } else { 3453 /* 3454 * If outer csum is not offload, the outer length may be filled 3455 * with 0. And the length of the outer header is added to the 3456 * inner l2_len. It would lead a cksum error. So driver has to 3457 * calculate the header length. 3458 */ 3459 if (unlikely(!(ol_flags & 3460 (PKT_TX_OUTER_IP_CKSUM | PKT_TX_OUTER_UDP_CKSUM)) && 3461 m->outer_l2_len == 0)) { 3462 struct rte_net_hdr_lens hdr_len; 3463 (void)rte_net_get_ptype(m, &hdr_len, 3464 RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK); 3465 m->outer_l3_len = hdr_len.l3_len; 3466 m->outer_l2_len = hdr_len.l2_len; 3467 m->l2_len = m->l2_len - hdr_len.l2_len - hdr_len.l3_len; 3468 } 3469 hns3_parse_outer_params(m, &tmp_outer); 3470 ret = hns3_parse_inner_params(m, &tmp_outer, &tmp_inner); 3471 if (ret) 3472 return -EINVAL; 3473 } 3474 3475 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer); 3476 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner); 3477 tmp_ol4cs = ol_flags & PKT_TX_OUTER_UDP_CKSUM ? 3478 BIT(HNS3_TXD_OL4CS_B) : 0; 3479 desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs); 3480 3481 return 0; 3482 } 3483 3484 static void 3485 hns3_parse_l3_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len) 3486 { 3487 uint64_t ol_flags = m->ol_flags; 3488 uint32_t l3_type; 3489 uint32_t tmp; 3490 3491 tmp = *type_cs_vlan_tso_len; 3492 if (ol_flags & PKT_TX_IPV4) 3493 l3_type = HNS3_L3T_IPV4; 3494 else if (ol_flags & PKT_TX_IPV6) 3495 l3_type = HNS3_L3T_IPV6; 3496 else 3497 l3_type = HNS3_L3T_NONE; 3498 3499 /* inner(/normal) L3 header size, defined in 4 bytes */ 3500 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S, 3501 m->l3_len >> HNS3_L3_LEN_UNIT); 3502 3503 tmp |= hns3_gen_field_val(HNS3_TXD_L3T_M, HNS3_TXD_L3T_S, l3_type); 3504 3505 /* Enable L3 checksum offloads */ 3506 if (ol_flags & PKT_TX_IP_CKSUM) 3507 tmp |= BIT(HNS3_TXD_L3CS_B); 3508 *type_cs_vlan_tso_len = tmp; 3509 } 3510 3511 static void 3512 hns3_parse_l4_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len) 3513 { 3514 uint64_t ol_flags = m->ol_flags; 3515 uint32_t tmp; 3516 /* Enable L4 checksum offloads */ 3517 switch (ol_flags & (PKT_TX_L4_MASK | PKT_TX_TCP_SEG)) { 3518 case PKT_TX_TCP_CKSUM | PKT_TX_TCP_SEG: 3519 case PKT_TX_TCP_CKSUM: 3520 case PKT_TX_TCP_SEG: 3521 tmp = *type_cs_vlan_tso_len; 3522 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, 3523 HNS3_L4T_TCP); 3524 break; 3525 case PKT_TX_UDP_CKSUM: 3526 tmp = *type_cs_vlan_tso_len; 3527 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, 3528 HNS3_L4T_UDP); 3529 break; 3530 case PKT_TX_SCTP_CKSUM: 3531 tmp = *type_cs_vlan_tso_len; 3532 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, 3533 HNS3_L4T_SCTP); 3534 break; 3535 default: 3536 return; 3537 } 3538 tmp |= BIT(HNS3_TXD_L4CS_B); 3539 tmp |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 3540 m->l4_len >> HNS3_L4_LEN_UNIT); 3541 *type_cs_vlan_tso_len = tmp; 3542 } 3543 3544 static void 3545 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, struct rte_mbuf *m, 3546 uint16_t tx_desc_id) 3547 { 3548 struct hns3_desc *tx_ring = txq->tx_ring; 3549 struct hns3_desc *desc = &tx_ring[tx_desc_id]; 3550 uint32_t value = 0; 3551 3552 hns3_parse_l3_cksum_params(m, &value); 3553 hns3_parse_l4_cksum_params(m, &value); 3554 3555 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value); 3556 } 3557 3558 static bool 3559 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num, 3560 uint32_t max_non_tso_bd_num) 3561 { 3562 struct rte_mbuf *m_first = tx_pkts; 3563 struct rte_mbuf *m_last = tx_pkts; 3564 uint32_t tot_len = 0; 3565 uint32_t hdr_len; 3566 uint32_t i; 3567 3568 /* 3569 * Hardware requires that the sum of the data length of every 8 3570 * consecutive buffers is greater than MSS in hns3 network engine. 3571 * We simplify it by ensuring pkt_headlen + the first 8 consecutive 3572 * frags greater than gso header len + mss, and the remaining 7 3573 * consecutive frags greater than MSS except the last 7 frags. 3574 */ 3575 if (bd_num <= max_non_tso_bd_num) 3576 return false; 3577 3578 for (i = 0; m_last && i < max_non_tso_bd_num - 1; 3579 i++, m_last = m_last->next) 3580 tot_len += m_last->data_len; 3581 3582 if (!m_last) 3583 return true; 3584 3585 /* ensure the first 8 frags is greater than mss + header */ 3586 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len; 3587 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ? 3588 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0; 3589 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len) 3590 return true; 3591 3592 /* 3593 * ensure the sum of the data length of every 7 consecutive buffer 3594 * is greater than mss except the last one. 3595 */ 3596 for (i = 0; m_last && i < bd_num - max_non_tso_bd_num; i++) { 3597 tot_len -= m_first->data_len; 3598 tot_len += m_last->data_len; 3599 3600 if (tot_len < tx_pkts->tso_segsz) 3601 return true; 3602 3603 m_first = m_first->next; 3604 m_last = m_last->next; 3605 } 3606 3607 return false; 3608 } 3609 3610 static bool 3611 hns3_outer_ipv4_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, 3612 uint32_t *l4_proto) 3613 { 3614 struct rte_ipv4_hdr *ipv4_hdr; 3615 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 3616 m->outer_l2_len); 3617 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) 3618 ipv4_hdr->hdr_checksum = 0; 3619 if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { 3620 struct rte_udp_hdr *udp_hdr; 3621 /* 3622 * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo 3623 * header for TSO packets 3624 */ 3625 if (ol_flags & PKT_TX_TCP_SEG) 3626 return true; 3627 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, 3628 m->outer_l2_len + m->outer_l3_len); 3629 udp_hdr->dgram_cksum = rte_ipv4_phdr_cksum(ipv4_hdr, ol_flags); 3630 3631 return true; 3632 } 3633 *l4_proto = ipv4_hdr->next_proto_id; 3634 return false; 3635 } 3636 3637 static bool 3638 hns3_outer_ipv6_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, 3639 uint32_t *l4_proto) 3640 { 3641 struct rte_ipv6_hdr *ipv6_hdr; 3642 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, 3643 m->outer_l2_len); 3644 if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { 3645 struct rte_udp_hdr *udp_hdr; 3646 /* 3647 * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo 3648 * header for TSO packets 3649 */ 3650 if (ol_flags & PKT_TX_TCP_SEG) 3651 return true; 3652 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, 3653 m->outer_l2_len + m->outer_l3_len); 3654 udp_hdr->dgram_cksum = rte_ipv6_phdr_cksum(ipv6_hdr, ol_flags); 3655 3656 return true; 3657 } 3658 *l4_proto = ipv6_hdr->proto; 3659 return false; 3660 } 3661 3662 static void 3663 hns3_outer_header_cksum_prepare(struct rte_mbuf *m) 3664 { 3665 uint64_t ol_flags = m->ol_flags; 3666 uint32_t paylen, hdr_len, l4_proto; 3667 struct rte_udp_hdr *udp_hdr; 3668 3669 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6))) 3670 return; 3671 3672 if (ol_flags & PKT_TX_OUTER_IPV4) { 3673 if (hns3_outer_ipv4_cksum_prepared(m, ol_flags, &l4_proto)) 3674 return; 3675 } else { 3676 if (hns3_outer_ipv6_cksum_prepared(m, ol_flags, &l4_proto)) 3677 return; 3678 } 3679 3680 /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */ 3681 if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) { 3682 hdr_len = m->l2_len + m->l3_len + m->l4_len; 3683 hdr_len += m->outer_l2_len + m->outer_l3_len; 3684 paylen = m->pkt_len - hdr_len; 3685 if (paylen <= m->tso_segsz) 3686 return; 3687 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, 3688 m->outer_l2_len + 3689 m->outer_l3_len); 3690 udp_hdr->dgram_cksum = 0; 3691 } 3692 } 3693 3694 static int 3695 hns3_check_tso_pkt_valid(struct rte_mbuf *m) 3696 { 3697 uint32_t tmp_data_len_sum = 0; 3698 uint16_t nb_buf = m->nb_segs; 3699 uint32_t paylen, hdr_len; 3700 struct rte_mbuf *m_seg; 3701 int i; 3702 3703 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT) 3704 return -EINVAL; 3705 3706 hdr_len = m->l2_len + m->l3_len + m->l4_len; 3707 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ? 3708 m->outer_l2_len + m->outer_l3_len : 0; 3709 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE) 3710 return -EINVAL; 3711 3712 paylen = m->pkt_len - hdr_len; 3713 if (paylen > HNS3_MAX_BD_PAYLEN) 3714 return -EINVAL; 3715 3716 /* 3717 * The TSO header (include outer and inner L2, L3 and L4 header) 3718 * should be provided by three descriptors in maximum in hns3 network 3719 * engine. 3720 */ 3721 m_seg = m; 3722 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf; 3723 i++, m_seg = m_seg->next) { 3724 tmp_data_len_sum += m_seg->data_len; 3725 } 3726 3727 if (hdr_len > tmp_data_len_sum) 3728 return -EINVAL; 3729 3730 return 0; 3731 } 3732 3733 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 3734 static inline int 3735 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m) 3736 { 3737 struct rte_ether_hdr *eh; 3738 struct rte_vlan_hdr *vh; 3739 3740 if (!txq->pvid_sw_shift_en) 3741 return 0; 3742 3743 /* 3744 * Due to hardware limitations, we only support two-layer VLAN hardware 3745 * offload in Tx direction based on hns3 network engine, so when PVID is 3746 * enabled, QinQ insert is no longer supported. 3747 * And when PVID is enabled, in the following two cases: 3748 * i) packets with more than two VLAN tags. 3749 * ii) packets with one VLAN tag while the hardware VLAN insert is 3750 * enabled. 3751 * The packets will be regarded as abnormal packets and discarded by 3752 * hardware in Tx direction. For debugging purposes, a validation check 3753 * for these types of packets is added to the '.tx_pkt_prepare' ops 3754 * implementation function named hns3_prep_pkts to inform users that 3755 * these packets will be discarded. 3756 */ 3757 if (m->ol_flags & PKT_TX_QINQ_PKT) 3758 return -EINVAL; 3759 3760 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *); 3761 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) { 3762 if (m->ol_flags & PKT_TX_VLAN_PKT) 3763 return -EINVAL; 3764 3765 /* Ensure the incoming packet is not a QinQ packet */ 3766 vh = (struct rte_vlan_hdr *)(eh + 1); 3767 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) 3768 return -EINVAL; 3769 } 3770 3771 return 0; 3772 } 3773 #endif 3774 3775 static uint16_t 3776 hns3_udp_cksum_help(struct rte_mbuf *m) 3777 { 3778 uint64_t ol_flags = m->ol_flags; 3779 uint16_t cksum = 0; 3780 uint32_t l4_len; 3781 3782 if (ol_flags & PKT_TX_IPV4) { 3783 struct rte_ipv4_hdr *ipv4_hdr = rte_pktmbuf_mtod_offset(m, 3784 struct rte_ipv4_hdr *, m->l2_len); 3785 l4_len = rte_be_to_cpu_16(ipv4_hdr->total_length) - m->l3_len; 3786 } else { 3787 struct rte_ipv6_hdr *ipv6_hdr = rte_pktmbuf_mtod_offset(m, 3788 struct rte_ipv6_hdr *, m->l2_len); 3789 l4_len = rte_be_to_cpu_16(ipv6_hdr->payload_len); 3790 } 3791 3792 rte_raw_cksum_mbuf(m, m->l2_len + m->l3_len, l4_len, &cksum); 3793 3794 cksum = ~cksum; 3795 /* 3796 * RFC 768:If the computed checksum is zero for UDP, it is transmitted 3797 * as all ones 3798 */ 3799 if (cksum == 0) 3800 cksum = 0xffff; 3801 3802 return (uint16_t)cksum; 3803 } 3804 3805 static bool 3806 hns3_validate_tunnel_cksum(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m) 3807 { 3808 uint64_t ol_flags = m->ol_flags; 3809 struct rte_udp_hdr *udp_hdr; 3810 uint16_t dst_port; 3811 3812 if (tx_queue->udp_cksum_mode == HNS3_SPECIAL_PORT_HW_CKSUM_MODE || 3813 ol_flags & PKT_TX_TUNNEL_MASK || 3814 (ol_flags & PKT_TX_L4_MASK) != PKT_TX_UDP_CKSUM) 3815 return true; 3816 /* 3817 * A UDP packet with the same dst_port as VXLAN\VXLAN_GPE\GENEVE will 3818 * be recognized as a tunnel packet in HW. In this case, if UDP CKSUM 3819 * offload is set and the tunnel mask has not been set, the CKSUM will 3820 * be wrong since the header length is wrong and driver should complete 3821 * the CKSUM to avoid CKSUM error. 3822 */ 3823 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, 3824 m->l2_len + m->l3_len); 3825 dst_port = rte_be_to_cpu_16(udp_hdr->dst_port); 3826 switch (dst_port) { 3827 case RTE_VXLAN_DEFAULT_PORT: 3828 case RTE_VXLAN_GPE_DEFAULT_PORT: 3829 case RTE_GENEVE_DEFAULT_PORT: 3830 udp_hdr->dgram_cksum = hns3_udp_cksum_help(m); 3831 m->ol_flags = ol_flags & ~PKT_TX_L4_MASK; 3832 return false; 3833 default: 3834 return true; 3835 } 3836 } 3837 3838 static int 3839 hns3_prep_pkt_proc(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m) 3840 { 3841 int ret; 3842 3843 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 3844 ret = rte_validate_tx_offload(m); 3845 if (ret != 0) { 3846 rte_errno = -ret; 3847 return ret; 3848 } 3849 3850 ret = hns3_vld_vlan_chk(tx_queue, m); 3851 if (ret != 0) { 3852 rte_errno = EINVAL; 3853 return ret; 3854 } 3855 #endif 3856 if (hns3_pkt_is_tso(m)) { 3857 if (hns3_pkt_need_linearized(m, m->nb_segs, 3858 tx_queue->max_non_tso_bd_num) || 3859 hns3_check_tso_pkt_valid(m)) { 3860 rte_errno = EINVAL; 3861 return -EINVAL; 3862 } 3863 3864 if (tx_queue->tso_mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) { 3865 /* 3866 * (tso mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) means 3867 * hardware support recalculate the TCP pseudo header 3868 * checksum of packets that need TSO, so network driver 3869 * software not need to recalculate it. 3870 */ 3871 hns3_outer_header_cksum_prepare(m); 3872 return 0; 3873 } 3874 } 3875 3876 ret = rte_net_intel_cksum_prepare(m); 3877 if (ret != 0) { 3878 rte_errno = -ret; 3879 return ret; 3880 } 3881 3882 if (!hns3_validate_tunnel_cksum(tx_queue, m)) 3883 return 0; 3884 3885 hns3_outer_header_cksum_prepare(m); 3886 3887 return 0; 3888 } 3889 3890 uint16_t 3891 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, 3892 uint16_t nb_pkts) 3893 { 3894 struct rte_mbuf *m; 3895 uint16_t i; 3896 3897 for (i = 0; i < nb_pkts; i++) { 3898 m = tx_pkts[i]; 3899 if (hns3_prep_pkt_proc(tx_queue, m)) 3900 return i; 3901 } 3902 3903 return i; 3904 } 3905 3906 static int 3907 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id, 3908 struct rte_mbuf *m) 3909 { 3910 struct hns3_desc *tx_ring = txq->tx_ring; 3911 struct hns3_desc *desc = &tx_ring[tx_desc_id]; 3912 3913 /* Enable checksum offloading */ 3914 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) { 3915 /* Fill in tunneling parameters if necessary */ 3916 if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) { 3917 txq->dfx_stats.unsupported_tunnel_pkt_cnt++; 3918 return -EINVAL; 3919 } 3920 3921 hns3_txd_enable_checksum(txq, m, tx_desc_id); 3922 } else { 3923 /* clear the control bit */ 3924 desc->tx.type_cs_vlan_tso_len = 0; 3925 desc->tx.ol_type_vlan_len_msec = 0; 3926 } 3927 3928 return 0; 3929 } 3930 3931 static int 3932 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg, 3933 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq) 3934 { 3935 uint8_t max_non_tso_bd_num; 3936 struct rte_mbuf *new_pkt; 3937 int ret; 3938 3939 if (hns3_pkt_is_tso(*m_seg)) 3940 return 0; 3941 3942 /* 3943 * If packet length is greater than HNS3_MAX_FRAME_LEN 3944 * driver support, the packet will be ignored. 3945 */ 3946 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) { 3947 txq->dfx_stats.over_length_pkt_cnt++; 3948 return -EINVAL; 3949 } 3950 3951 max_non_tso_bd_num = txq->max_non_tso_bd_num; 3952 if (unlikely(nb_buf > max_non_tso_bd_num)) { 3953 txq->dfx_stats.exceed_limit_bd_pkt_cnt++; 3954 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt, 3955 max_non_tso_bd_num); 3956 if (ret) { 3957 txq->dfx_stats.exceed_limit_bd_reassem_fail++; 3958 return ret; 3959 } 3960 *m_seg = new_pkt; 3961 } 3962 3963 return 0; 3964 } 3965 3966 static inline void 3967 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq) 3968 { 3969 struct hns3_entry *tx_entry; 3970 struct hns3_desc *desc; 3971 uint16_t tx_next_clean; 3972 int i; 3973 3974 while (1) { 3975 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh) 3976 break; 3977 3978 /* 3979 * All mbufs can be released only when the VLD bits of all 3980 * descriptors in a batch are cleared. 3981 */ 3982 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) % 3983 txq->nb_tx_desc; 3984 desc = &txq->tx_ring[tx_next_clean]; 3985 for (i = 0; i < txq->tx_rs_thresh; i++) { 3986 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) & 3987 BIT(HNS3_TXD_VLD_B)) 3988 return; 3989 desc--; 3990 } 3991 3992 tx_entry = &txq->sw_ring[txq->next_to_clean]; 3993 3994 for (i = 0; i < txq->tx_rs_thresh; i++) 3995 rte_prefetch0((tx_entry + i)->mbuf); 3996 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) { 3997 rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf); 3998 tx_entry->mbuf = NULL; 3999 } 4000 4001 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc; 4002 txq->tx_bd_ready += txq->tx_rs_thresh; 4003 } 4004 } 4005 4006 static inline void 4007 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts) 4008 { 4009 tx_entry->mbuf = pkts[0]; 4010 } 4011 4012 static inline void 4013 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts) 4014 { 4015 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]); 4016 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]); 4017 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]); 4018 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]); 4019 } 4020 4021 static inline void 4022 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) 4023 { 4024 #define PER_LOOP_NUM 4 4025 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B); 4026 uint64_t dma_addr; 4027 uint32_t i; 4028 4029 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) { 4030 dma_addr = rte_mbuf_data_iova(*pkts); 4031 txdp->addr = rte_cpu_to_le_64(dma_addr); 4032 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); 4033 txdp->tx.paylen_fd_dop_ol4cs = 0; 4034 txdp->tx.type_cs_vlan_tso_len = 0; 4035 txdp->tx.ol_type_vlan_len_msec = 0; 4036 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); 4037 } 4038 } 4039 4040 static inline void 4041 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) 4042 { 4043 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B); 4044 uint64_t dma_addr; 4045 4046 dma_addr = rte_mbuf_data_iova(*pkts); 4047 txdp->addr = rte_cpu_to_le_64(dma_addr); 4048 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); 4049 txdp->tx.paylen_fd_dop_ol4cs = 0; 4050 txdp->tx.type_cs_vlan_tso_len = 0; 4051 txdp->tx.ol_type_vlan_len_msec = 0; 4052 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); 4053 } 4054 4055 static inline void 4056 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq, 4057 struct rte_mbuf **pkts, 4058 uint16_t nb_pkts) 4059 { 4060 #define PER_LOOP_NUM 4 4061 #define PER_LOOP_MASK (PER_LOOP_NUM - 1) 4062 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use]; 4063 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use]; 4064 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK)); 4065 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK)); 4066 uint32_t i; 4067 4068 for (i = 0; i < mainpart; i += PER_LOOP_NUM) { 4069 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i); 4070 hns3_tx_setup_4bd(txdp + i, pkts + i); 4071 4072 /* Increment bytes counter */ 4073 uint32_t j; 4074 for (j = 0; j < PER_LOOP_NUM; j++) 4075 txq->basic_stats.bytes += pkts[i + j]->pkt_len; 4076 } 4077 if (unlikely(leftover > 0)) { 4078 for (i = 0; i < leftover; i++) { 4079 hns3_tx_backup_1mbuf(tx_entry + mainpart + i, 4080 pkts + mainpart + i); 4081 hns3_tx_setup_1bd(txdp + mainpart + i, 4082 pkts + mainpart + i); 4083 4084 /* Increment bytes counter */ 4085 txq->basic_stats.bytes += pkts[mainpart + i]->pkt_len; 4086 } 4087 } 4088 } 4089 4090 uint16_t 4091 hns3_xmit_pkts_simple(void *tx_queue, 4092 struct rte_mbuf **tx_pkts, 4093 uint16_t nb_pkts) 4094 { 4095 struct hns3_tx_queue *txq = tx_queue; 4096 uint16_t nb_tx = 0; 4097 4098 hns3_tx_free_buffer_simple(txq); 4099 4100 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts); 4101 if (unlikely(nb_pkts == 0)) { 4102 if (txq->tx_bd_ready == 0) 4103 txq->dfx_stats.queue_full_cnt++; 4104 return 0; 4105 } 4106 4107 txq->tx_bd_ready -= nb_pkts; 4108 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) { 4109 nb_tx = txq->nb_tx_desc - txq->next_to_use; 4110 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx); 4111 txq->next_to_use = 0; 4112 } 4113 4114 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx); 4115 txq->next_to_use += nb_pkts - nb_tx; 4116 4117 hns3_write_txq_tail_reg(txq, nb_pkts); 4118 4119 return nb_pkts; 4120 } 4121 4122 uint16_t 4123 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 4124 { 4125 struct hns3_tx_queue *txq = tx_queue; 4126 struct hns3_entry *tx_bak_pkt; 4127 struct hns3_desc *tx_ring; 4128 struct rte_mbuf *tx_pkt; 4129 struct rte_mbuf *m_seg; 4130 struct hns3_desc *desc; 4131 uint32_t nb_hold = 0; 4132 uint16_t tx_next_use; 4133 uint16_t tx_pkt_num; 4134 uint16_t tx_bd_max; 4135 uint16_t nb_buf; 4136 uint16_t nb_tx; 4137 uint16_t i; 4138 4139 /* free useless buffer */ 4140 hns3_tx_free_useless_buffer(txq); 4141 4142 tx_next_use = txq->next_to_use; 4143 tx_bd_max = txq->nb_tx_desc; 4144 tx_pkt_num = nb_pkts; 4145 tx_ring = txq->tx_ring; 4146 4147 /* send packets */ 4148 tx_bak_pkt = &txq->sw_ring[tx_next_use]; 4149 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) { 4150 tx_pkt = *tx_pkts++; 4151 4152 nb_buf = tx_pkt->nb_segs; 4153 4154 if (nb_buf > txq->tx_bd_ready) { 4155 txq->dfx_stats.queue_full_cnt++; 4156 if (nb_tx == 0) 4157 return 0; 4158 4159 goto end_of_tx; 4160 } 4161 4162 /* 4163 * If packet length is less than minimum packet length supported 4164 * by hardware in Tx direction, driver need to pad it to avoid 4165 * error. 4166 */ 4167 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) < 4168 txq->min_tx_pkt_len)) { 4169 uint16_t add_len; 4170 char *appended; 4171 4172 add_len = txq->min_tx_pkt_len - 4173 rte_pktmbuf_pkt_len(tx_pkt); 4174 appended = rte_pktmbuf_append(tx_pkt, add_len); 4175 if (appended == NULL) { 4176 txq->dfx_stats.pkt_padding_fail_cnt++; 4177 break; 4178 } 4179 4180 memset(appended, 0, add_len); 4181 } 4182 4183 m_seg = tx_pkt; 4184 4185 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq)) 4186 goto end_of_tx; 4187 4188 if (hns3_parse_cksum(txq, tx_next_use, m_seg)) 4189 goto end_of_tx; 4190 4191 i = 0; 4192 desc = &tx_ring[tx_next_use]; 4193 4194 /* 4195 * If the packet is divided into multiple Tx Buffer Descriptors, 4196 * only need to fill vlan, paylen and tso into the first Tx 4197 * Buffer Descriptor. 4198 */ 4199 hns3_fill_first_desc(txq, desc, m_seg); 4200 4201 do { 4202 desc = &tx_ring[tx_next_use]; 4203 /* 4204 * Fill valid bits, DMA address and data length for each 4205 * Tx Buffer Descriptor. 4206 */ 4207 hns3_fill_per_desc(desc, m_seg); 4208 tx_bak_pkt->mbuf = m_seg; 4209 m_seg = m_seg->next; 4210 tx_next_use++; 4211 tx_bak_pkt++; 4212 if (tx_next_use >= tx_bd_max) { 4213 tx_next_use = 0; 4214 tx_bak_pkt = txq->sw_ring; 4215 } 4216 4217 i++; 4218 } while (m_seg != NULL); 4219 4220 /* Add end flag for the last Tx Buffer Descriptor */ 4221 desc->tx.tp_fe_sc_vld_ra_ri |= 4222 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B)); 4223 4224 /* Increment bytes counter */ 4225 txq->basic_stats.bytes += tx_pkt->pkt_len; 4226 nb_hold += i; 4227 txq->next_to_use = tx_next_use; 4228 txq->tx_bd_ready -= i; 4229 } 4230 4231 end_of_tx: 4232 4233 if (likely(nb_tx)) 4234 hns3_write_txq_tail_reg(txq, nb_hold); 4235 4236 return nb_tx; 4237 } 4238 4239 int __rte_weak 4240 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev) 4241 { 4242 return -ENOTSUP; 4243 } 4244 4245 uint16_t __rte_weak 4246 hns3_xmit_pkts_vec(__rte_unused void *tx_queue, 4247 __rte_unused struct rte_mbuf **tx_pkts, 4248 __rte_unused uint16_t nb_pkts) 4249 { 4250 return 0; 4251 } 4252 4253 uint16_t __rte_weak 4254 hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue, 4255 struct rte_mbuf __rte_unused **tx_pkts, 4256 uint16_t __rte_unused nb_pkts) 4257 { 4258 return 0; 4259 } 4260 4261 int 4262 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 4263 struct rte_eth_burst_mode *mode) 4264 { 4265 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 4266 const char *info = NULL; 4267 4268 if (pkt_burst == hns3_xmit_pkts_simple) 4269 info = "Scalar Simple"; 4270 else if (pkt_burst == hns3_xmit_pkts) 4271 info = "Scalar"; 4272 else if (pkt_burst == hns3_xmit_pkts_vec) 4273 info = "Vector Neon"; 4274 else if (pkt_burst == hns3_xmit_pkts_vec_sve) 4275 info = "Vector Sve"; 4276 4277 if (info == NULL) 4278 return -EINVAL; 4279 4280 snprintf(mode->info, sizeof(mode->info), "%s", info); 4281 4282 return 0; 4283 } 4284 4285 static bool 4286 hns3_tx_check_simple_support(struct rte_eth_dev *dev) 4287 { 4288 uint64_t offloads = dev->data->dev_conf.txmode.offloads; 4289 4290 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4291 if (hns3_dev_get_support(hw, PTP)) 4292 return false; 4293 4294 return (offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)); 4295 } 4296 4297 static bool 4298 hns3_get_tx_prep_needed(struct rte_eth_dev *dev) 4299 { 4300 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 4301 RTE_SET_USED(dev); 4302 /* always perform tx_prepare when debug */ 4303 return true; 4304 #else 4305 #define HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK (\ 4306 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 4307 DEV_TX_OFFLOAD_TCP_CKSUM | \ 4308 DEV_TX_OFFLOAD_UDP_CKSUM | \ 4309 DEV_TX_OFFLOAD_SCTP_CKSUM | \ 4310 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 4311 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \ 4312 DEV_TX_OFFLOAD_TCP_TSO | \ 4313 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 4314 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 4315 DEV_TX_OFFLOAD_GENEVE_TNL_TSO) 4316 4317 uint64_t tx_offload = dev->data->dev_conf.txmode.offloads; 4318 if (tx_offload & HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK) 4319 return true; 4320 4321 return false; 4322 #endif 4323 } 4324 4325 eth_tx_burst_t 4326 hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) 4327 { 4328 struct hns3_adapter *hns = dev->data->dev_private; 4329 bool vec_allowed, sve_allowed, simple_allowed; 4330 bool vec_support, tx_prepare_needed; 4331 4332 vec_support = hns3_tx_check_vec_support(dev) == 0; 4333 vec_allowed = vec_support && hns3_get_default_vec_support(); 4334 sve_allowed = vec_support && hns3_get_sve_support(); 4335 simple_allowed = hns3_tx_check_simple_support(dev); 4336 tx_prepare_needed = hns3_get_tx_prep_needed(dev); 4337 4338 *prep = NULL; 4339 4340 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) 4341 return hns3_xmit_pkts_vec; 4342 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) 4343 return hns3_xmit_pkts_vec_sve; 4344 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) 4345 return hns3_xmit_pkts_simple; 4346 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) { 4347 if (tx_prepare_needed) 4348 *prep = hns3_prep_pkts; 4349 return hns3_xmit_pkts; 4350 } 4351 4352 if (vec_allowed) 4353 return hns3_xmit_pkts_vec; 4354 if (simple_allowed) 4355 return hns3_xmit_pkts_simple; 4356 4357 if (tx_prepare_needed) 4358 *prep = hns3_prep_pkts; 4359 return hns3_xmit_pkts; 4360 } 4361 4362 uint16_t 4363 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused, 4364 struct rte_mbuf **pkts __rte_unused, 4365 uint16_t pkts_n __rte_unused) 4366 { 4367 return 0; 4368 } 4369 4370 static void 4371 hns3_trace_rxtx_function(struct rte_eth_dev *dev) 4372 { 4373 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4374 struct rte_eth_burst_mode rx_mode; 4375 struct rte_eth_burst_mode tx_mode; 4376 4377 memset(&rx_mode, 0, sizeof(rx_mode)); 4378 memset(&tx_mode, 0, sizeof(tx_mode)); 4379 (void)hns3_rx_burst_mode_get(dev, 0, &rx_mode); 4380 (void)hns3_tx_burst_mode_get(dev, 0, &tx_mode); 4381 4382 hns3_dbg(hw, "using rx_pkt_burst: %s, tx_pkt_burst: %s.", 4383 rx_mode.info, tx_mode.info); 4384 } 4385 4386 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) 4387 { 4388 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 4389 struct hns3_adapter *hns = eth_dev->data->dev_private; 4390 eth_tx_prep_t prep = NULL; 4391 4392 if (hns->hw.adapter_state == HNS3_NIC_STARTED && 4393 __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) { 4394 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); 4395 eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status; 4396 eth_dev->tx_pkt_burst = hw->set_link_down ? 4397 hns3_dummy_rxtx_burst : 4398 hns3_get_tx_function(eth_dev, &prep); 4399 eth_dev->tx_pkt_prepare = prep; 4400 eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; 4401 hns3_trace_rxtx_function(eth_dev); 4402 } else { 4403 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst; 4404 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst; 4405 eth_dev->tx_pkt_prepare = NULL; 4406 } 4407 } 4408 4409 void 4410 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 4411 struct rte_eth_rxq_info *qinfo) 4412 { 4413 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id]; 4414 4415 qinfo->mp = rxq->mb_pool; 4416 qinfo->nb_desc = rxq->nb_rx_desc; 4417 qinfo->scattered_rx = dev->data->scattered_rx; 4418 /* Report the HW Rx buffer length to user */ 4419 qinfo->rx_buf_size = rxq->rx_buf_len; 4420 4421 /* 4422 * If there are no available Rx buffer descriptors, incoming packets 4423 * are always dropped by hardware based on hns3 network engine. 4424 */ 4425 qinfo->conf.rx_drop_en = 1; 4426 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 4427 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 4428 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 4429 } 4430 4431 void 4432 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 4433 struct rte_eth_txq_info *qinfo) 4434 { 4435 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id]; 4436 4437 qinfo->nb_desc = txq->nb_tx_desc; 4438 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads; 4439 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh; 4440 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 4441 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 4442 } 4443 4444 int 4445 hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) 4446 { 4447 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4448 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id]; 4449 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4450 int ret; 4451 4452 if (!hns3_dev_get_support(hw, INDEP_TXRX)) 4453 return -ENOTSUP; 4454 4455 rte_spinlock_lock(&hw->lock); 4456 ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX); 4457 if (ret) { 4458 hns3_err(hw, "fail to reset Rx queue %u, ret = %d.", 4459 rx_queue_id, ret); 4460 rte_spinlock_unlock(&hw->lock); 4461 return ret; 4462 } 4463 4464 ret = hns3_init_rxq(hns, rx_queue_id); 4465 if (ret) { 4466 hns3_err(hw, "fail to init Rx queue %u, ret = %d.", 4467 rx_queue_id, ret); 4468 rte_spinlock_unlock(&hw->lock); 4469 return ret; 4470 } 4471 4472 hns3_enable_rxq(rxq, true); 4473 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 4474 rte_spinlock_unlock(&hw->lock); 4475 4476 return ret; 4477 } 4478 4479 static void 4480 hns3_reset_sw_rxq(struct hns3_rx_queue *rxq) 4481 { 4482 rxq->next_to_use = 0; 4483 rxq->rx_rearm_start = 0; 4484 rxq->rx_free_hold = 0; 4485 rxq->rx_rearm_nb = 0; 4486 rxq->pkt_first_seg = NULL; 4487 rxq->pkt_last_seg = NULL; 4488 memset(&rxq->rx_ring[0], 0, rxq->nb_rx_desc * sizeof(struct hns3_desc)); 4489 hns3_rxq_vec_setup(rxq); 4490 } 4491 4492 int 4493 hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) 4494 { 4495 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4496 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id]; 4497 4498 if (!hns3_dev_get_support(hw, INDEP_TXRX)) 4499 return -ENOTSUP; 4500 4501 rte_spinlock_lock(&hw->lock); 4502 hns3_enable_rxq(rxq, false); 4503 4504 hns3_rx_queue_release_mbufs(rxq); 4505 4506 hns3_reset_sw_rxq(rxq); 4507 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 4508 rte_spinlock_unlock(&hw->lock); 4509 4510 return 0; 4511 } 4512 4513 int 4514 hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) 4515 { 4516 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4517 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id]; 4518 int ret; 4519 4520 if (!hns3_dev_get_support(hw, INDEP_TXRX)) 4521 return -ENOTSUP; 4522 4523 rte_spinlock_lock(&hw->lock); 4524 ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX); 4525 if (ret) { 4526 hns3_err(hw, "fail to reset Tx queue %u, ret = %d.", 4527 tx_queue_id, ret); 4528 rte_spinlock_unlock(&hw->lock); 4529 return ret; 4530 } 4531 4532 hns3_init_txq(txq); 4533 hns3_enable_txq(txq, true); 4534 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 4535 rte_spinlock_unlock(&hw->lock); 4536 4537 return ret; 4538 } 4539 4540 int 4541 hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) 4542 { 4543 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4544 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id]; 4545 4546 if (!hns3_dev_get_support(hw, INDEP_TXRX)) 4547 return -ENOTSUP; 4548 4549 rte_spinlock_lock(&hw->lock); 4550 hns3_enable_txq(txq, false); 4551 hns3_tx_queue_release_mbufs(txq); 4552 /* 4553 * All the mbufs in sw_ring are released and all the pointers in sw_ring 4554 * are set to NULL. If this queue is still called by upper layer, 4555 * residual SW status of this txq may cause these pointers in sw_ring 4556 * which have been set to NULL to be released again. To avoid it, 4557 * reinit the txq. 4558 */ 4559 hns3_init_txq(txq); 4560 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 4561 rte_spinlock_unlock(&hw->lock); 4562 4563 return 0; 4564 } 4565 4566 static int 4567 hns3_tx_done_cleanup_full(struct hns3_tx_queue *txq, uint32_t free_cnt) 4568 { 4569 uint16_t next_to_clean = txq->next_to_clean; 4570 uint16_t next_to_use = txq->next_to_use; 4571 uint16_t tx_bd_ready = txq->tx_bd_ready; 4572 struct hns3_entry *tx_pkt = &txq->sw_ring[next_to_clean]; 4573 struct hns3_desc *desc = &txq->tx_ring[next_to_clean]; 4574 uint32_t idx; 4575 4576 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc) 4577 free_cnt = txq->nb_tx_desc; 4578 4579 for (idx = 0; idx < free_cnt; idx++) { 4580 if (next_to_clean == next_to_use) 4581 break; 4582 4583 if (desc->tx.tp_fe_sc_vld_ra_ri & 4584 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B))) 4585 break; 4586 4587 if (tx_pkt->mbuf != NULL) { 4588 rte_pktmbuf_free_seg(tx_pkt->mbuf); 4589 tx_pkt->mbuf = NULL; 4590 } 4591 4592 next_to_clean++; 4593 tx_bd_ready++; 4594 tx_pkt++; 4595 desc++; 4596 if (next_to_clean == txq->nb_tx_desc) { 4597 tx_pkt = txq->sw_ring; 4598 desc = txq->tx_ring; 4599 next_to_clean = 0; 4600 } 4601 } 4602 4603 if (idx > 0) { 4604 txq->next_to_clean = next_to_clean; 4605 txq->tx_bd_ready = tx_bd_ready; 4606 } 4607 4608 return (int)idx; 4609 } 4610 4611 int 4612 hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) 4613 { 4614 struct hns3_tx_queue *q = (struct hns3_tx_queue *)txq; 4615 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id]; 4616 4617 if (dev->tx_pkt_burst == hns3_xmit_pkts) 4618 return hns3_tx_done_cleanup_full(q, free_cnt); 4619 else if (dev->tx_pkt_burst == hns3_dummy_rxtx_burst) 4620 return 0; 4621 else 4622 return -ENOTSUP; 4623 } 4624 4625 int 4626 hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) 4627 { 4628 volatile struct hns3_desc *rxdp; 4629 struct hns3_rx_queue *rxq; 4630 struct rte_eth_dev *dev; 4631 uint32_t bd_base_info; 4632 uint16_t desc_id; 4633 4634 rxq = (struct hns3_rx_queue *)rx_queue; 4635 if (offset >= rxq->nb_rx_desc) 4636 return -EINVAL; 4637 4638 desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc; 4639 rxdp = &rxq->rx_ring[desc_id]; 4640 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); 4641 dev = &rte_eth_devices[rxq->port_id]; 4642 if (dev->rx_pkt_burst == hns3_recv_pkts_simple || 4643 dev->rx_pkt_burst == hns3_recv_scattered_pkts) { 4644 if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold) 4645 return RTE_ETH_RX_DESC_UNAVAIL; 4646 } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec || 4647 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) { 4648 if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb) 4649 return RTE_ETH_RX_DESC_UNAVAIL; 4650 } else { 4651 return RTE_ETH_RX_DESC_UNAVAIL; 4652 } 4653 4654 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 4655 return RTE_ETH_RX_DESC_AVAIL; 4656 else 4657 return RTE_ETH_RX_DESC_DONE; 4658 } 4659 4660 int 4661 hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) 4662 { 4663 volatile struct hns3_desc *txdp; 4664 struct hns3_tx_queue *txq; 4665 struct rte_eth_dev *dev; 4666 uint16_t desc_id; 4667 4668 txq = (struct hns3_tx_queue *)tx_queue; 4669 if (offset >= txq->nb_tx_desc) 4670 return -EINVAL; 4671 4672 dev = &rte_eth_devices[txq->port_id]; 4673 if (dev->tx_pkt_burst != hns3_xmit_pkts_simple && 4674 dev->tx_pkt_burst != hns3_xmit_pkts && 4675 dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve && 4676 dev->tx_pkt_burst != hns3_xmit_pkts_vec) 4677 return RTE_ETH_TX_DESC_UNAVAIL; 4678 4679 desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc; 4680 txdp = &txq->tx_ring[desc_id]; 4681 if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B))) 4682 return RTE_ETH_TX_DESC_FULL; 4683 else 4684 return RTE_ETH_TX_DESC_DONE; 4685 } 4686 4687 uint32_t 4688 hns3_rx_queue_count(void *rx_queue) 4689 { 4690 /* 4691 * Number of BDs that have been processed by the driver 4692 * but have not been notified to the hardware. 4693 */ 4694 uint32_t driver_hold_bd_num; 4695 struct hns3_rx_queue *rxq; 4696 const struct rte_eth_dev *dev; 4697 uint32_t fbd_num; 4698 4699 rxq = rx_queue; 4700 dev = &rte_eth_devices[rxq->port_id]; 4701 4702 fbd_num = hns3_read_dev(rxq, HNS3_RING_RX_FBDNUM_REG); 4703 if (dev->rx_pkt_burst == hns3_recv_pkts_vec || 4704 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) 4705 driver_hold_bd_num = rxq->rx_rearm_nb; 4706 else 4707 driver_hold_bd_num = rxq->rx_free_hold; 4708 4709 if (fbd_num <= driver_hold_bd_num) 4710 return 0; 4711 else 4712 return fbd_num - driver_hold_bd_num; 4713 } 4714 4715 void 4716 hns3_enable_rxd_adv_layout(struct hns3_hw *hw) 4717 { 4718 /* 4719 * If the hardware support rxd advanced layout, then driver enable it 4720 * default. 4721 */ 4722 if (hns3_dev_get_support(hw, RXD_ADV_LAYOUT)) 4723 hns3_write_dev(hw, HNS3_RXD_ADV_LAYOUT_EN_REG, 1); 4724 } 4725 4726 void 4727 hns3_stop_tx_datapath(struct rte_eth_dev *dev) 4728 { 4729 dev->tx_pkt_burst = hns3_dummy_rxtx_burst; 4730 dev->tx_pkt_prepare = NULL; 4731 rte_wmb(); 4732 /* Disable tx datapath on secondary process. */ 4733 hns3_mp_req_stop_tx(dev); 4734 /* Prevent crashes when queues are still in use. */ 4735 rte_delay_ms(dev->data->nb_tx_queues); 4736 } 4737 4738 void 4739 hns3_start_tx_datapath(struct rte_eth_dev *dev) 4740 { 4741 eth_tx_prep_t prep = NULL; 4742 4743 dev->tx_pkt_burst = hns3_get_tx_function(dev, &prep); 4744 dev->tx_pkt_prepare = prep; 4745 hns3_mp_req_start_tx(dev); 4746 } 4747