1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <bus_pci_driver.h> 6 #include <rte_common.h> 7 #include <rte_cycles.h> 8 #include <rte_geneve.h> 9 #include <rte_vxlan.h> 10 #include <ethdev_driver.h> 11 #include <rte_io.h> 12 #include <rte_net.h> 13 #include <rte_malloc.h> 14 #if defined(RTE_ARCH_ARM64) 15 #include <rte_cpuflags.h> 16 #include <rte_vect.h> 17 #endif 18 19 #include "hns3_common.h" 20 #include "hns3_regs.h" 21 #include "hns3_logs.h" 22 #include "hns3_mp.h" 23 #include "hns3_rxtx.h" 24 25 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1) 26 #define HNS3_RX_RING_PREFETCTH_MASK 3 27 28 static void 29 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq) 30 { 31 uint16_t i; 32 33 /* Note: Fake rx queue will not enter here */ 34 if (rxq->sw_ring == NULL) 35 return; 36 37 if (rxq->rx_rearm_nb == 0) { 38 for (i = 0; i < rxq->nb_rx_desc; i++) { 39 if (rxq->sw_ring[i].mbuf != NULL) { 40 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf); 41 rxq->sw_ring[i].mbuf = NULL; 42 } 43 } 44 } else { 45 for (i = rxq->next_to_use; 46 i != rxq->rx_rearm_start; 47 i = (i + 1) % rxq->nb_rx_desc) { 48 if (rxq->sw_ring[i].mbuf != NULL) { 49 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf); 50 rxq->sw_ring[i].mbuf = NULL; 51 } 52 } 53 for (i = 0; i < rxq->rx_rearm_nb; i++) 54 rxq->sw_ring[(rxq->rx_rearm_start + i) % rxq->nb_rx_desc].mbuf = NULL; 55 } 56 57 for (i = 0; i < rxq->bulk_mbuf_num; i++) 58 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]); 59 rxq->bulk_mbuf_num = 0; 60 61 if (rxq->pkt_first_seg) { 62 rte_pktmbuf_free(rxq->pkt_first_seg); 63 rxq->pkt_first_seg = NULL; 64 } 65 } 66 67 static void 68 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq) 69 { 70 uint16_t i; 71 72 /* Note: Fake tx queue will not enter here */ 73 if (txq->sw_ring) { 74 for (i = 0; i < txq->nb_tx_desc; i++) { 75 if (txq->sw_ring[i].mbuf) { 76 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf); 77 txq->sw_ring[i].mbuf = NULL; 78 } 79 } 80 } 81 } 82 83 static void 84 hns3_rx_queue_release(void *queue) 85 { 86 struct hns3_rx_queue *rxq = queue; 87 if (rxq) { 88 hns3_rx_queue_release_mbufs(rxq); 89 if (rxq->mz) { 90 rte_memzone_free(rxq->mz); 91 rxq->mz = NULL; 92 } 93 if (rxq->sw_ring) { 94 rte_free(rxq->sw_ring); 95 rxq->sw_ring = NULL; 96 } 97 rte_free(rxq); 98 } 99 } 100 101 static void 102 hns3_tx_queue_release(void *queue) 103 { 104 struct hns3_tx_queue *txq = queue; 105 if (txq) { 106 hns3_tx_queue_release_mbufs(txq); 107 if (txq->mz) { 108 rte_memzone_free(txq->mz); 109 txq->mz = NULL; 110 } 111 if (txq->sw_ring) { 112 rte_free(txq->sw_ring); 113 txq->sw_ring = NULL; 114 } 115 if (txq->free) { 116 rte_free(txq->free); 117 txq->free = NULL; 118 } 119 rte_free(txq); 120 } 121 } 122 123 static void 124 hns3_rx_queue_release_lock(void *queue) 125 { 126 struct hns3_rx_queue *rxq = queue; 127 struct hns3_adapter *hns; 128 129 if (rxq == NULL) 130 return; 131 132 hns = rxq->hns; 133 rte_spinlock_lock(&hns->hw.lock); 134 hns3_rx_queue_release(queue); 135 rte_spinlock_unlock(&hns->hw.lock); 136 } 137 138 void 139 hns3_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id) 140 { 141 hns3_rx_queue_release_lock(dev->data->rx_queues[queue_id]); 142 } 143 144 static void 145 hns3_tx_queue_release_lock(void *queue) 146 { 147 struct hns3_tx_queue *txq = queue; 148 struct hns3_adapter *hns; 149 150 if (txq == NULL) 151 return; 152 153 hns = txq->hns; 154 rte_spinlock_lock(&hns->hw.lock); 155 hns3_tx_queue_release(queue); 156 rte_spinlock_unlock(&hns->hw.lock); 157 } 158 159 void 160 hns3_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id) 161 { 162 hns3_tx_queue_release_lock(dev->data->tx_queues[queue_id]); 163 } 164 165 static void 166 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue) 167 { 168 struct hns3_rx_queue *rxq = queue; 169 struct hns3_adapter *hns; 170 struct hns3_hw *hw; 171 uint16_t idx; 172 173 if (rxq == NULL) 174 return; 175 176 hns = rxq->hns; 177 hw = &hns->hw; 178 idx = rxq->queue_id; 179 if (hw->fkq_data.rx_queues[idx]) { 180 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]); 181 hw->fkq_data.rx_queues[idx] = NULL; 182 } 183 184 /* free fake rx queue arrays */ 185 if (idx == hw->fkq_data.nb_fake_rx_queues - 1) { 186 hw->fkq_data.nb_fake_rx_queues = 0; 187 rte_free(hw->fkq_data.rx_queues); 188 hw->fkq_data.rx_queues = NULL; 189 } 190 } 191 192 static void 193 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue) 194 { 195 struct hns3_tx_queue *txq = queue; 196 struct hns3_adapter *hns; 197 struct hns3_hw *hw; 198 uint16_t idx; 199 200 if (txq == NULL) 201 return; 202 203 hns = txq->hns; 204 hw = &hns->hw; 205 idx = txq->queue_id; 206 if (hw->fkq_data.tx_queues[idx]) { 207 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]); 208 hw->fkq_data.tx_queues[idx] = NULL; 209 } 210 211 /* free fake tx queue arrays */ 212 if (idx == hw->fkq_data.nb_fake_tx_queues - 1) { 213 hw->fkq_data.nb_fake_tx_queues = 0; 214 rte_free(hw->fkq_data.tx_queues); 215 hw->fkq_data.tx_queues = NULL; 216 } 217 } 218 219 static void 220 hns3_free_rx_queues(struct rte_eth_dev *dev) 221 { 222 struct hns3_adapter *hns = dev->data->dev_private; 223 struct hns3_fake_queue_data *fkq_data; 224 struct hns3_hw *hw = &hns->hw; 225 uint16_t nb_rx_q; 226 uint16_t i; 227 228 nb_rx_q = hw->data->nb_rx_queues; 229 for (i = 0; i < nb_rx_q; i++) { 230 if (dev->data->rx_queues[i]) { 231 hns3_rx_queue_release(dev->data->rx_queues[i]); 232 dev->data->rx_queues[i] = NULL; 233 } 234 } 235 236 /* Free fake Rx queues */ 237 fkq_data = &hw->fkq_data; 238 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) { 239 if (fkq_data->rx_queues[i]) 240 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]); 241 } 242 } 243 244 static void 245 hns3_free_tx_queues(struct rte_eth_dev *dev) 246 { 247 struct hns3_adapter *hns = dev->data->dev_private; 248 struct hns3_fake_queue_data *fkq_data; 249 struct hns3_hw *hw = &hns->hw; 250 uint16_t nb_tx_q; 251 uint16_t i; 252 253 nb_tx_q = hw->data->nb_tx_queues; 254 for (i = 0; i < nb_tx_q; i++) { 255 if (dev->data->tx_queues[i]) { 256 hns3_tx_queue_release(dev->data->tx_queues[i]); 257 dev->data->tx_queues[i] = NULL; 258 } 259 } 260 261 /* Free fake Tx queues */ 262 fkq_data = &hw->fkq_data; 263 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) { 264 if (fkq_data->tx_queues[i]) 265 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]); 266 } 267 } 268 269 void 270 hns3_free_all_queues(struct rte_eth_dev *dev) 271 { 272 hns3_free_rx_queues(dev); 273 hns3_free_tx_queues(dev); 274 } 275 276 static int 277 hns3_check_rx_dma_addr(struct hns3_hw *hw, uint64_t dma_addr) 278 { 279 uint64_t rem; 280 281 rem = dma_addr & (hw->rx_dma_addr_align - 1); 282 if (rem > 0) { 283 hns3_err(hw, "The IO address of the beginning of the mbuf data " 284 "must be %u-byte aligned", hw->rx_dma_addr_align); 285 return -EINVAL; 286 } 287 return 0; 288 } 289 290 static int 291 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq) 292 { 293 struct rte_mbuf *mbuf; 294 uint64_t dma_addr; 295 uint16_t i; 296 int ret; 297 298 for (i = 0; i < rxq->nb_rx_desc; i++) { 299 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool); 300 if (unlikely(mbuf == NULL)) { 301 hns3_err(hw, "Failed to allocate RXD[%u] for rx queue!", 302 i); 303 hns3_rx_queue_release_mbufs(rxq); 304 return -ENOMEM; 305 } 306 307 rte_mbuf_refcnt_set(mbuf, 1); 308 mbuf->next = NULL; 309 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 310 mbuf->nb_segs = 1; 311 mbuf->port = rxq->port_id; 312 313 rxq->sw_ring[i].mbuf = mbuf; 314 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); 315 rxq->rx_ring[i].addr = dma_addr; 316 rxq->rx_ring[i].rx.bd_base_info = 0; 317 318 ret = hns3_check_rx_dma_addr(hw, dma_addr); 319 if (ret != 0) { 320 hns3_rx_queue_release_mbufs(rxq); 321 return ret; 322 } 323 } 324 325 return 0; 326 } 327 328 static int 329 hns3_buf_size2type(uint32_t buf_size) 330 { 331 int bd_size_type; 332 333 switch (buf_size) { 334 case 512: 335 bd_size_type = HNS3_BD_SIZE_512_TYPE; 336 break; 337 case 1024: 338 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 339 break; 340 case 4096: 341 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 342 break; 343 default: 344 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 345 } 346 347 return bd_size_type; 348 } 349 350 static void 351 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq) 352 { 353 uint32_t rx_buf_len = rxq->rx_buf_len; 354 uint64_t dma_addr = rxq->rx_ring_phys_addr; 355 356 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr); 357 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG, 358 (uint32_t)(dma_addr >> 32)); 359 360 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG, 361 hns3_buf_size2type(rx_buf_len)); 362 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG, 363 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc)); 364 } 365 366 static void 367 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq) 368 { 369 uint64_t dma_addr = txq->tx_ring_phys_addr; 370 371 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr); 372 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG, 373 (uint32_t)(dma_addr >> 32)); 374 375 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG, 376 HNS3_CFG_DESC_NUM(txq->nb_tx_desc)); 377 } 378 379 void 380 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw) 381 { 382 uint16_t nb_rx_q = hw->data->nb_rx_queues; 383 uint16_t nb_tx_q = hw->data->nb_tx_queues; 384 struct hns3_rx_queue *rxq; 385 struct hns3_tx_queue *txq; 386 bool pvid_en; 387 int i; 388 389 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE; 390 for (i = 0; i < hw->cfg_max_queues; i++) { 391 if (i < nb_rx_q) { 392 rxq = hw->data->rx_queues[i]; 393 if (rxq != NULL) 394 rxq->pvid_sw_discard_en = pvid_en; 395 } 396 if (i < nb_tx_q) { 397 txq = hw->data->tx_queues[i]; 398 if (txq != NULL) 399 txq->pvid_sw_shift_en = pvid_en; 400 } 401 } 402 } 403 404 static void 405 hns3_stop_unused_queue(void *tqp_base, enum hns3_ring_type queue_type) 406 { 407 uint32_t reg_offset; 408 uint32_t reg; 409 410 reg_offset = queue_type == HNS3_RING_TYPE_TX ? 411 HNS3_RING_TX_EN_REG : HNS3_RING_RX_EN_REG; 412 reg = hns3_read_reg(tqp_base, reg_offset); 413 reg &= ~BIT(HNS3_RING_EN_B); 414 hns3_write_reg(tqp_base, reg_offset, reg); 415 } 416 417 void 418 hns3_enable_all_queues(struct hns3_hw *hw, bool en) 419 { 420 uint16_t nb_rx_q = hw->data->nb_rx_queues; 421 uint16_t nb_tx_q = hw->data->nb_tx_queues; 422 struct hns3_rx_queue *rxq; 423 struct hns3_tx_queue *txq; 424 uint32_t rcb_reg; 425 void *tqp_base; 426 uint16_t i; 427 428 for (i = 0; i < hw->cfg_max_queues; i++) { 429 if (hns3_dev_get_support(hw, INDEP_TXRX)) { 430 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL; 431 txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL; 432 433 tqp_base = (void *)((char *)hw->io_base + 434 hns3_get_tqp_reg_offset(i)); 435 /* 436 * If queue struct is not initialized, it means the 437 * related HW ring has not been initialized yet. 438 * So, these queues should be disabled before enable 439 * the tqps to avoid a HW exception since the queues 440 * are enabled by default. 441 */ 442 if (rxq == NULL) 443 hns3_stop_unused_queue(tqp_base, 444 HNS3_RING_TYPE_RX); 445 if (txq == NULL) 446 hns3_stop_unused_queue(tqp_base, 447 HNS3_RING_TYPE_TX); 448 } else { 449 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : 450 hw->fkq_data.rx_queues[i - nb_rx_q]; 451 452 tqp_base = rxq->io_base; 453 } 454 /* 455 * This is the master switch that used to control the enabling 456 * of a pair of Tx and Rx queues. Both the Rx and Tx point to 457 * the same register 458 */ 459 rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG); 460 if (en) 461 rcb_reg |= BIT(HNS3_RING_EN_B); 462 else 463 rcb_reg &= ~BIT(HNS3_RING_EN_B); 464 hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg); 465 } 466 } 467 468 static void 469 hns3_enable_txq(struct hns3_tx_queue *txq, bool en) 470 { 471 struct hns3_hw *hw = &txq->hns->hw; 472 uint32_t reg; 473 474 if (hns3_dev_get_support(hw, INDEP_TXRX)) { 475 reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG); 476 if (en) 477 reg |= BIT(HNS3_RING_EN_B); 478 else 479 reg &= ~BIT(HNS3_RING_EN_B); 480 hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg); 481 } 482 txq->enabled = en; 483 } 484 485 static void 486 hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en) 487 { 488 struct hns3_hw *hw = &rxq->hns->hw; 489 uint32_t reg; 490 491 if (hns3_dev_get_support(hw, INDEP_TXRX)) { 492 reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG); 493 if (en) 494 reg |= BIT(HNS3_RING_EN_B); 495 else 496 reg &= ~BIT(HNS3_RING_EN_B); 497 hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg); 498 } 499 rxq->enabled = en; 500 } 501 502 int 503 hns3_start_all_txqs(struct rte_eth_dev *dev) 504 { 505 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 506 struct hns3_tx_queue *txq; 507 uint16_t i, j; 508 509 for (i = 0; i < dev->data->nb_tx_queues; i++) { 510 txq = hw->data->tx_queues[i]; 511 if (!txq) { 512 hns3_err(hw, "Tx queue %u not available or setup.", i); 513 goto start_txqs_fail; 514 } 515 /* 516 * Tx queue is enabled by default. Therefore, the Tx queues 517 * needs to be disabled when deferred_start is set. There is 518 * another master switch used to control the enabling of a pair 519 * of Tx and Rx queues. And the master switch is disabled by 520 * default. 521 */ 522 if (txq->tx_deferred_start) 523 hns3_enable_txq(txq, false); 524 else 525 hns3_enable_txq(txq, true); 526 } 527 return 0; 528 529 start_txqs_fail: 530 for (j = 0; j < i; j++) { 531 txq = hw->data->tx_queues[j]; 532 hns3_enable_txq(txq, false); 533 } 534 return -EINVAL; 535 } 536 537 int 538 hns3_start_all_rxqs(struct rte_eth_dev *dev) 539 { 540 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 541 struct hns3_rx_queue *rxq; 542 uint16_t i, j; 543 544 for (i = 0; i < dev->data->nb_rx_queues; i++) { 545 rxq = hw->data->rx_queues[i]; 546 if (!rxq) { 547 hns3_err(hw, "Rx queue %u not available or setup.", i); 548 goto start_rxqs_fail; 549 } 550 /* 551 * Rx queue is enabled by default. Therefore, the Rx queues 552 * needs to be disabled when deferred_start is set. There is 553 * another master switch used to control the enabling of a pair 554 * of Tx and Rx queues. And the master switch is disabled by 555 * default. 556 */ 557 if (rxq->rx_deferred_start) 558 hns3_enable_rxq(rxq, false); 559 else 560 hns3_enable_rxq(rxq, true); 561 } 562 return 0; 563 564 start_rxqs_fail: 565 for (j = 0; j < i; j++) { 566 rxq = hw->data->rx_queues[j]; 567 hns3_enable_rxq(rxq, false); 568 } 569 return -EINVAL; 570 } 571 572 void 573 hns3_restore_tqp_enable_state(struct hns3_hw *hw) 574 { 575 struct hns3_rx_queue *rxq; 576 struct hns3_tx_queue *txq; 577 uint16_t i; 578 579 for (i = 0; i < hw->data->nb_rx_queues; i++) { 580 rxq = hw->data->rx_queues[i]; 581 if (rxq != NULL) 582 hns3_enable_rxq(rxq, rxq->enabled); 583 } 584 585 for (i = 0; i < hw->data->nb_tx_queues; i++) { 586 txq = hw->data->tx_queues[i]; 587 if (txq != NULL) 588 hns3_enable_txq(txq, txq->enabled); 589 } 590 } 591 592 void 593 hns3_stop_all_txqs(struct rte_eth_dev *dev) 594 { 595 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 596 struct hns3_tx_queue *txq; 597 uint16_t i; 598 599 for (i = 0; i < dev->data->nb_tx_queues; i++) { 600 txq = hw->data->tx_queues[i]; 601 if (!txq) 602 continue; 603 hns3_enable_txq(txq, false); 604 } 605 } 606 607 static int 608 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable) 609 { 610 struct hns3_cfg_com_tqp_queue_cmd *req; 611 struct hns3_cmd_desc desc; 612 int ret; 613 614 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data; 615 616 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false); 617 req->tqp_id = rte_cpu_to_le_16(queue_id); 618 req->stream_id = 0; 619 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0); 620 621 ret = hns3_cmd_send(hw, &desc, 1); 622 if (ret) 623 hns3_err(hw, "TQP %s fail, ret = %d", enable ? "enable" : "disable", ret); 624 625 return ret; 626 } 627 628 static int 629 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable) 630 { 631 struct hns3_reset_tqp_queue_cmd *req; 632 struct hns3_cmd_desc desc; 633 int ret; 634 635 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false); 636 637 req = (struct hns3_reset_tqp_queue_cmd *)desc.data; 638 req->tqp_id = rte_cpu_to_le_16(queue_id); 639 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0); 640 ret = hns3_cmd_send(hw, &desc, 1); 641 if (ret) 642 hns3_err(hw, "send tqp reset cmd error, queue_id = %u, ret = %d", 643 queue_id, ret); 644 645 return ret; 646 } 647 648 static int 649 hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id, 650 uint8_t *reset_status) 651 { 652 struct hns3_reset_tqp_queue_cmd *req; 653 struct hns3_cmd_desc desc; 654 int ret; 655 656 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true); 657 658 req = (struct hns3_reset_tqp_queue_cmd *)desc.data; 659 req->tqp_id = rte_cpu_to_le_16(queue_id); 660 661 ret = hns3_cmd_send(hw, &desc, 1); 662 if (ret) { 663 hns3_err(hw, "get tqp reset status error, queue_id = %u, ret = %d.", 664 queue_id, ret); 665 return ret; 666 } 667 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B); 668 return ret; 669 } 670 671 static int 672 hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id) 673 { 674 #define HNS3_TQP_RESET_TRY_MS 200 675 uint16_t wait_time = 0; 676 uint8_t reset_status; 677 int ret; 678 679 /* 680 * In current version VF is not supported when PF is driven by DPDK 681 * driver, all task queue pairs are mapped to PF function, so PF's queue 682 * id is equals to the global queue id in PF range. 683 */ 684 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true); 685 if (ret) { 686 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret); 687 return ret; 688 } 689 690 do { 691 /* Wait for tqp hw reset */ 692 rte_delay_ms(HNS3_POLL_RESPONE_MS); 693 wait_time += HNS3_POLL_RESPONE_MS; 694 ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status); 695 if (ret) 696 goto tqp_reset_fail; 697 698 if (reset_status) 699 break; 700 } while (wait_time < HNS3_TQP_RESET_TRY_MS); 701 702 if (!reset_status) { 703 ret = -ETIMEDOUT; 704 hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d", 705 queue_id, ret); 706 goto tqp_reset_fail; 707 } 708 709 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false); 710 if (ret) 711 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret); 712 713 return ret; 714 715 tqp_reset_fail: 716 hns3_send_reset_tqp_cmd(hw, queue_id, false); 717 return ret; 718 } 719 720 static int 721 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id) 722 { 723 struct hns3_vf_to_pf_msg req; 724 int ret; 725 726 hns3vf_mbx_setup(&req, HNS3_MBX_QUEUE_RESET, 0); 727 memcpy(req.data, &queue_id, sizeof(uint16_t)); 728 ret = hns3vf_mbx_send(hw, &req, true, NULL, 0); 729 if (ret) 730 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.", 731 queue_id, ret); 732 return ret; 733 } 734 735 static int 736 hns3_reset_rcb_cmd(struct hns3_hw *hw, uint8_t *reset_status) 737 { 738 struct hns3_reset_cmd *req; 739 struct hns3_cmd_desc desc; 740 int ret; 741 742 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 743 req = (struct hns3_reset_cmd *)desc.data; 744 hns3_set_bit(req->fun_reset_rcb, HNS3_CFG_RESET_RCB_B, 1); 745 746 /* 747 * The start qid should be the global qid of the first tqp of the 748 * function which should be reset in this port. Since our PF not 749 * support take over of VFs, so we only need to reset function 0, 750 * and its start qid is always 0. 751 */ 752 req->fun_reset_rcb_vqid_start = rte_cpu_to_le_16(0); 753 req->fun_reset_rcb_vqid_num = rte_cpu_to_le_16(hw->cfg_max_queues); 754 755 ret = hns3_cmd_send(hw, &desc, 1); 756 if (ret) { 757 hns3_err(hw, "fail to send rcb reset cmd, ret = %d.", ret); 758 return ret; 759 } 760 761 *reset_status = req->fun_reset_rcb_return_status; 762 return 0; 763 } 764 765 static int 766 hns3pf_reset_all_tqps(struct hns3_hw *hw) 767 { 768 #define HNS3_RESET_RCB_NOT_SUPPORT 0U 769 #define HNS3_RESET_ALL_TQP_SUCCESS 1U 770 uint8_t reset_status; 771 uint16_t i; 772 int ret; 773 774 ret = hns3_reset_rcb_cmd(hw, &reset_status); 775 if (ret) 776 return ret; 777 778 /* 779 * If the firmware version is low, it may not support the rcb reset 780 * which means reset all the tqps at a time. In this case, we should 781 * reset tqps one by one. 782 */ 783 if (reset_status == HNS3_RESET_RCB_NOT_SUPPORT) { 784 for (i = 0; i < hw->cfg_max_queues; i++) { 785 ret = hns3pf_reset_tqp(hw, i); 786 if (ret) { 787 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.", 788 i, ret); 789 return ret; 790 } 791 } 792 } else if (reset_status != HNS3_RESET_ALL_TQP_SUCCESS) { 793 hns3_err(hw, "fail to reset all tqps, reset_status = %u.", 794 reset_status); 795 return -EIO; 796 } 797 798 return 0; 799 } 800 801 static int 802 hns3vf_reset_all_tqps(struct hns3_hw *hw) 803 { 804 #define HNS3VF_RESET_ALL_TQP_DONE 1U 805 struct hns3_vf_to_pf_msg req; 806 uint8_t reset_status; 807 int ret; 808 uint16_t i; 809 810 hns3vf_mbx_setup(&req, HNS3_MBX_QUEUE_RESET, 0); 811 ret = hns3vf_mbx_send(hw, &req, true, 812 &reset_status, sizeof(reset_status)); 813 if (ret) { 814 hns3_err(hw, "fail to send rcb reset mbx, ret = %d.", ret); 815 return ret; 816 } 817 818 if (reset_status == HNS3VF_RESET_ALL_TQP_DONE) 819 return 0; 820 821 /* 822 * If the firmware version or kernel PF version is low, it may not 823 * support the rcb reset which means reset all the tqps at a time. 824 * In this case, we should reset tqps one by one. 825 */ 826 for (i = 1; i < hw->cfg_max_queues; i++) { 827 ret = hns3vf_reset_tqp(hw, i); 828 if (ret) 829 return ret; 830 } 831 832 return 0; 833 } 834 835 int 836 hns3_reset_all_tqps(struct hns3_adapter *hns) 837 { 838 struct hns3_hw *hw = &hns->hw; 839 uint16_t i; 840 int ret; 841 842 /* Disable all queues before reset all queues */ 843 for (i = 0; i < hw->cfg_max_queues; i++) { 844 ret = hns3_tqp_enable(hw, i, false); 845 if (ret) { 846 hns3_err(hw, "fail to disable tqps before tqps reset, ret = %d.", 847 ret); 848 return ret; 849 } 850 } 851 852 if (hns->is_vf) 853 return hns3vf_reset_all_tqps(hw); 854 else 855 return hns3pf_reset_all_tqps(hw); 856 } 857 858 static int 859 hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id, 860 enum hns3_ring_type queue_type, bool enable) 861 { 862 struct hns3_reset_tqp_queue_cmd *req; 863 struct hns3_cmd_desc desc; 864 int ret; 865 866 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false); 867 868 req = (struct hns3_reset_tqp_queue_cmd *)desc.data; 869 req->tqp_id = rte_cpu_to_le_16(queue_id); 870 req->queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1; 871 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0); 872 873 ret = hns3_cmd_send(hw, &desc, 1); 874 if (ret) 875 hns3_err(hw, "send queue reset cmd error, queue_id = %u, " 876 "queue_type = %s, ret = %d.", queue_id, 877 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret); 878 return ret; 879 } 880 881 static int 882 hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id, 883 enum hns3_ring_type queue_type, 884 uint8_t *reset_status) 885 { 886 struct hns3_reset_tqp_queue_cmd *req; 887 struct hns3_cmd_desc desc; 888 int ret; 889 890 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true); 891 892 req = (struct hns3_reset_tqp_queue_cmd *)desc.data; 893 req->tqp_id = rte_cpu_to_le_16(queue_id); 894 req->queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1; 895 896 ret = hns3_cmd_send(hw, &desc, 1); 897 if (ret) { 898 hns3_err(hw, "get queue reset status error, queue_id = %u " 899 "queue_type = %s, ret = %d.", queue_id, 900 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret); 901 return ret; 902 } 903 904 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B); 905 return ret; 906 } 907 908 static int 909 hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id, 910 enum hns3_ring_type queue_type) 911 { 912 #define HNS3_QUEUE_RESET_TRY_MS 200 913 struct hns3_tx_queue *txq; 914 struct hns3_rx_queue *rxq; 915 uint32_t reset_wait_times; 916 uint32_t max_wait_times; 917 uint8_t reset_status; 918 int ret; 919 920 if (queue_type == HNS3_RING_TYPE_TX) { 921 txq = hw->data->tx_queues[queue_id]; 922 hns3_enable_txq(txq, false); 923 } else { 924 rxq = hw->data->rx_queues[queue_id]; 925 hns3_enable_rxq(rxq, false); 926 } 927 928 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true); 929 if (ret) { 930 hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret); 931 return ret; 932 } 933 934 reset_wait_times = 0; 935 max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS; 936 while (reset_wait_times < max_wait_times) { 937 /* Wait for queue hw reset */ 938 rte_delay_ms(HNS3_POLL_RESPONE_MS); 939 ret = hns3_get_queue_reset_status(hw, queue_id, 940 queue_type, &reset_status); 941 if (ret) 942 goto queue_reset_fail; 943 944 if (reset_status) 945 break; 946 reset_wait_times++; 947 } 948 949 if (!reset_status) { 950 hns3_err(hw, "reset queue timeout, queue_id = %u, queue_type = %s", 951 queue_id, 952 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx"); 953 ret = -ETIMEDOUT; 954 goto queue_reset_fail; 955 } 956 957 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false); 958 if (ret) 959 hns3_err(hw, "deassert queue reset fail, ret = %d.", ret); 960 961 return ret; 962 963 queue_reset_fail: 964 hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false); 965 return ret; 966 } 967 968 uint32_t 969 hns3_get_tqp_intr_reg_offset(uint16_t tqp_intr_id) 970 { 971 uint32_t reg_offset; 972 973 /* Need an extend offset to config queues > 64 */ 974 if (tqp_intr_id < HNS3_MIN_EXT_TQP_INTR_ID) 975 reg_offset = HNS3_TQP_INTR_REG_BASE + 976 tqp_intr_id * HNS3_TQP_INTR_LOW_ORDER_OFFSET; 977 else 978 reg_offset = HNS3_TQP_INTR_EXT_REG_BASE + 979 tqp_intr_id / HNS3_MIN_EXT_TQP_INTR_ID * 980 HNS3_TQP_INTR_HIGH_ORDER_OFFSET + 981 tqp_intr_id % HNS3_MIN_EXT_TQP_INTR_ID * 982 HNS3_TQP_INTR_LOW_ORDER_OFFSET; 983 984 return reg_offset; 985 } 986 987 void 988 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id, 989 uint8_t gl_idx, uint16_t gl_value) 990 { 991 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG, 992 HNS3_TQP_INTR_GL1_REG, 993 HNS3_TQP_INTR_GL2_REG}; 994 uint32_t addr, value; 995 996 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX) 997 return; 998 999 addr = offset[gl_idx] + hns3_get_tqp_intr_reg_offset(queue_id); 1000 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US) 1001 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US; 1002 else 1003 value = HNS3_GL_USEC_TO_REG(gl_value); 1004 1005 hns3_write_dev(hw, addr, value); 1006 } 1007 1008 void 1009 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value) 1010 { 1011 uint32_t addr, value; 1012 1013 if (rl_value > HNS3_TQP_INTR_RL_MAX) 1014 return; 1015 1016 addr = HNS3_TQP_INTR_RL_REG + hns3_get_tqp_intr_reg_offset(queue_id); 1017 value = HNS3_RL_USEC_TO_REG(rl_value); 1018 if (value > 0) 1019 value |= HNS3_TQP_INTR_RL_ENABLE_MASK; 1020 1021 hns3_write_dev(hw, addr, value); 1022 } 1023 1024 void 1025 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value) 1026 { 1027 uint32_t addr; 1028 1029 /* 1030 * int_ql_max == 0 means the hardware does not support QL, 1031 * QL regs config is not permitted if QL is not supported, 1032 * here just return. 1033 */ 1034 if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE) 1035 return; 1036 1037 addr = HNS3_TQP_INTR_TX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id); 1038 hns3_write_dev(hw, addr, ql_value); 1039 1040 addr = HNS3_TQP_INTR_RX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id); 1041 hns3_write_dev(hw, addr, ql_value); 1042 } 1043 1044 static void 1045 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en) 1046 { 1047 uint32_t addr, value; 1048 1049 addr = HNS3_TQP_INTR_CTRL_REG + hns3_get_tqp_intr_reg_offset(queue_id); 1050 value = en ? 1 : 0; 1051 1052 hns3_write_dev(hw, addr, value); 1053 } 1054 1055 /* 1056 * Enable all rx queue interrupt when in interrupt rx mode. 1057 * This api was called before enable queue rx&tx (in normal start or reset 1058 * recover scenes), used to fix hardware rx queue interrupt enable was clear 1059 * when FLR. 1060 */ 1061 void 1062 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en) 1063 { 1064 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1065 uint16_t nb_rx_q = hw->data->nb_rx_queues; 1066 uint16_t i; 1067 1068 if (dev->data->dev_conf.intr_conf.rxq == 0) 1069 return; 1070 1071 for (i = 0; i < nb_rx_q; i++) 1072 hns3_queue_intr_enable(hw, i, en); 1073 } 1074 1075 int 1076 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 1077 { 1078 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1079 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1080 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1081 1082 if (dev->data->dev_conf.intr_conf.rxq == 0) 1083 return -ENOTSUP; 1084 1085 hns3_queue_intr_enable(hw, queue_id, true); 1086 1087 return rte_intr_ack(intr_handle); 1088 } 1089 1090 int 1091 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 1092 { 1093 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1094 1095 if (dev->data->dev_conf.intr_conf.rxq == 0) 1096 return -ENOTSUP; 1097 1098 hns3_queue_intr_enable(hw, queue_id, false); 1099 1100 return 0; 1101 } 1102 1103 static int 1104 hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx) 1105 { 1106 struct hns3_hw *hw = &hns->hw; 1107 struct hns3_rx_queue *rxq; 1108 int ret; 1109 1110 PMD_INIT_FUNC_TRACE(); 1111 1112 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx]; 1113 ret = hns3_alloc_rx_queue_mbufs(hw, rxq); 1114 if (ret) { 1115 hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.", 1116 idx, ret); 1117 return ret; 1118 } 1119 1120 rxq->next_to_use = 0; 1121 rxq->rx_rearm_start = 0; 1122 rxq->rx_free_hold = 0; 1123 rxq->rx_rearm_nb = 0; 1124 rxq->pkt_first_seg = NULL; 1125 rxq->pkt_last_seg = NULL; 1126 hns3_init_rx_queue_hw(rxq); 1127 hns3_rxq_vec_setup(rxq); 1128 1129 return 0; 1130 } 1131 1132 static void 1133 hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx) 1134 { 1135 struct hns3_hw *hw = &hns->hw; 1136 struct hns3_rx_queue *rxq; 1137 1138 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx]; 1139 rxq->next_to_use = 0; 1140 rxq->rx_free_hold = 0; 1141 rxq->rx_rearm_start = 0; 1142 rxq->rx_rearm_nb = 0; 1143 hns3_init_rx_queue_hw(rxq); 1144 } 1145 1146 static void 1147 hns3_init_txq(struct hns3_tx_queue *txq) 1148 { 1149 struct hns3_desc *desc; 1150 uint16_t i; 1151 1152 /* Clear tx bd */ 1153 desc = txq->tx_ring; 1154 for (i = 0; i < txq->nb_tx_desc; i++) { 1155 desc->tx.tp_fe_sc_vld_ra_ri = 0; 1156 desc++; 1157 } 1158 1159 txq->next_to_use = 0; 1160 txq->next_to_clean = 0; 1161 txq->tx_bd_ready = txq->nb_tx_desc - 1; 1162 hns3_init_tx_queue_hw(txq); 1163 } 1164 1165 static void 1166 hns3_init_tx_ring_tc(struct hns3_adapter *hns) 1167 { 1168 struct hns3_hw *hw = &hns->hw; 1169 struct hns3_tx_queue *txq; 1170 int i, num; 1171 1172 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 1173 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i]; 1174 uint16_t j; 1175 1176 if (!tc_queue->enable) 1177 continue; 1178 1179 for (j = 0; j < tc_queue->tqp_count; j++) { 1180 num = tc_queue->tqp_offset + j; 1181 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num]; 1182 if (txq == NULL) 1183 continue; 1184 1185 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc); 1186 } 1187 } 1188 } 1189 1190 static int 1191 hns3_init_rx_queues(struct hns3_adapter *hns) 1192 { 1193 struct hns3_hw *hw = &hns->hw; 1194 struct hns3_rx_queue *rxq; 1195 uint16_t i, j; 1196 int ret; 1197 1198 /* Initialize RSS for queues */ 1199 ret = hns3_config_rss(hns); 1200 if (ret) { 1201 hns3_err(hw, "failed to configure rss, ret = %d.", ret); 1202 return ret; 1203 } 1204 1205 for (i = 0; i < hw->data->nb_rx_queues; i++) { 1206 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i]; 1207 if (!rxq) { 1208 hns3_err(hw, "Rx queue %u not available or setup.", i); 1209 goto out; 1210 } 1211 1212 if (rxq->rx_deferred_start) 1213 continue; 1214 1215 ret = hns3_init_rxq(hns, i); 1216 if (ret) { 1217 hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i, 1218 ret); 1219 goto out; 1220 } 1221 } 1222 1223 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++) 1224 hns3_init_fake_rxq(hns, i); 1225 1226 return 0; 1227 1228 out: 1229 for (j = 0; j < i; j++) { 1230 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j]; 1231 if (rxq->rx_deferred_start) 1232 continue; 1233 1234 hns3_rx_queue_release_mbufs(rxq); 1235 } 1236 1237 return ret; 1238 } 1239 1240 static int 1241 hns3_init_tx_queues(struct hns3_adapter *hns) 1242 { 1243 struct hns3_hw *hw = &hns->hw; 1244 struct hns3_tx_queue *txq; 1245 uint16_t i; 1246 1247 for (i = 0; i < hw->data->nb_tx_queues; i++) { 1248 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i]; 1249 if (!txq) { 1250 hns3_err(hw, "Tx queue %u not available or setup.", i); 1251 return -EINVAL; 1252 } 1253 1254 if (txq->tx_deferred_start) 1255 continue; 1256 hns3_init_txq(txq); 1257 } 1258 1259 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) { 1260 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i]; 1261 hns3_init_txq(txq); 1262 } 1263 hns3_init_tx_ring_tc(hns); 1264 1265 return 0; 1266 } 1267 1268 /* 1269 * Init all queues. 1270 * Note: just init and setup queues, and don't enable tqps. 1271 */ 1272 int 1273 hns3_init_queues(struct hns3_adapter *hns, bool reset_queue) 1274 { 1275 struct hns3_hw *hw = &hns->hw; 1276 int ret; 1277 1278 if (reset_queue) { 1279 ret = hns3_reset_all_tqps(hns); 1280 if (ret) { 1281 hns3_err(hw, "failed to reset all queues, ret = %d.", 1282 ret); 1283 return ret; 1284 } 1285 } 1286 1287 ret = hns3_init_rx_queues(hns); 1288 if (ret) { 1289 hns3_err(hw, "failed to init rx queues, ret = %d.", ret); 1290 return ret; 1291 } 1292 1293 ret = hns3_init_tx_queues(hns); 1294 if (ret) { 1295 hns3_dev_release_mbufs(hns); 1296 hns3_err(hw, "failed to init tx queues, ret = %d.", ret); 1297 } 1298 1299 return ret; 1300 } 1301 1302 void 1303 hns3_start_tqps(struct hns3_hw *hw) 1304 { 1305 struct hns3_tx_queue *txq; 1306 struct hns3_rx_queue *rxq; 1307 uint16_t i; 1308 1309 hns3_enable_all_queues(hw, true); 1310 1311 for (i = 0; i < hw->data->nb_tx_queues; i++) { 1312 __rte_assume(i < RTE_MAX_QUEUES_PER_PORT); 1313 txq = hw->data->tx_queues[i]; 1314 if (txq->enabled) 1315 hw->data->tx_queue_state[i] = 1316 RTE_ETH_QUEUE_STATE_STARTED; 1317 } 1318 1319 for (i = 0; i < hw->data->nb_rx_queues; i++) { 1320 __rte_assume(i < RTE_MAX_QUEUES_PER_PORT); 1321 rxq = hw->data->rx_queues[i]; 1322 if (rxq->enabled) 1323 hw->data->rx_queue_state[i] = 1324 RTE_ETH_QUEUE_STATE_STARTED; 1325 } 1326 } 1327 1328 void 1329 hns3_stop_tqps(struct hns3_hw *hw) 1330 { 1331 uint16_t i; 1332 1333 hns3_enable_all_queues(hw, false); 1334 1335 for (i = 0; i < hw->data->nb_tx_queues; i++) 1336 hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1337 1338 for (i = 0; i < hw->data->nb_rx_queues; i++) 1339 hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1340 } 1341 1342 /* 1343 * Iterate over all Rx Queue, and call the callback() function for each Rx 1344 * queue. 1345 * 1346 * @param[in] dev 1347 * The target eth dev. 1348 * @param[in] callback 1349 * The function to call for each queue. 1350 * if callback function return nonzero will stop iterate and return it's value 1351 * @param[in] arg 1352 * The arguments to provide the callback function with. 1353 * 1354 * @return 1355 * 0 on success, otherwise with errno set. 1356 */ 1357 int 1358 hns3_rxq_iterate(struct rte_eth_dev *dev, 1359 int (*callback)(struct hns3_rx_queue *, void *), void *arg) 1360 { 1361 uint32_t i; 1362 int ret; 1363 1364 if (dev->data->rx_queues == NULL) 1365 return -EINVAL; 1366 1367 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1368 ret = callback(dev->data->rx_queues[i], arg); 1369 if (ret != 0) 1370 return ret; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static void* 1377 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev, 1378 struct hns3_queue_info *q_info) 1379 { 1380 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1381 const struct rte_memzone *rx_mz; 1382 struct hns3_rx_queue *rxq; 1383 unsigned int rx_desc; 1384 1385 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue), 1386 RTE_CACHE_LINE_SIZE, q_info->socket_id); 1387 if (rxq == NULL) { 1388 hns3_err(hw, "Failed to allocate memory for No.%u rx ring!", 1389 q_info->idx); 1390 return NULL; 1391 } 1392 1393 /* Allocate rx ring hardware descriptors. */ 1394 rxq->queue_id = q_info->idx; 1395 rxq->nb_rx_desc = q_info->nb_desc; 1396 1397 /* 1398 * Allocate a litter more memory because rx vector functions 1399 * don't check boundaries each time. 1400 */ 1401 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) * 1402 sizeof(struct hns3_desc); 1403 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx, 1404 rx_desc, HNS3_RING_BASE_ALIGN, 1405 q_info->socket_id); 1406 if (rx_mz == NULL) { 1407 hns3_err(hw, "Failed to reserve DMA memory for No.%u rx ring!", 1408 q_info->idx); 1409 hns3_rx_queue_release(rxq); 1410 return NULL; 1411 } 1412 rxq->mz = rx_mz; 1413 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr; 1414 rxq->rx_ring_phys_addr = rx_mz->iova; 1415 1416 return rxq; 1417 } 1418 1419 static int 1420 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, 1421 uint16_t nb_desc, unsigned int socket_id) 1422 { 1423 struct hns3_adapter *hns = dev->data->dev_private; 1424 struct hns3_hw *hw = &hns->hw; 1425 struct hns3_queue_info q_info; 1426 struct hns3_rx_queue *rxq; 1427 uint16_t nb_rx_q; 1428 1429 if (hw->fkq_data.rx_queues[idx]) { 1430 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]); 1431 hw->fkq_data.rx_queues[idx] = NULL; 1432 } 1433 1434 q_info.idx = idx; 1435 q_info.socket_id = socket_id; 1436 q_info.nb_desc = nb_desc; 1437 q_info.type = "hns3 fake RX queue"; 1438 q_info.ring_name = "rx_fake_ring"; 1439 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info); 1440 if (rxq == NULL) { 1441 hns3_err(hw, "Failed to setup No.%u fake rx ring.", idx); 1442 return -ENOMEM; 1443 } 1444 1445 /* Don't need alloc sw_ring, because upper applications don't use it */ 1446 rxq->sw_ring = NULL; 1447 1448 rxq->hns = hns; 1449 rxq->rx_deferred_start = false; 1450 rxq->port_id = dev->data->port_id; 1451 rxq->configured = true; 1452 nb_rx_q = dev->data->nb_rx_queues; 1453 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + 1454 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE); 1455 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE; 1456 1457 rte_spinlock_lock(&hw->lock); 1458 hw->fkq_data.rx_queues[idx] = rxq; 1459 rte_spinlock_unlock(&hw->lock); 1460 1461 return 0; 1462 } 1463 1464 static void* 1465 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev, 1466 struct hns3_queue_info *q_info) 1467 { 1468 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1469 const struct rte_memzone *tx_mz; 1470 struct hns3_tx_queue *txq; 1471 struct hns3_desc *desc; 1472 unsigned int tx_desc; 1473 uint16_t i; 1474 1475 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue), 1476 RTE_CACHE_LINE_SIZE, q_info->socket_id); 1477 if (txq == NULL) { 1478 hns3_err(hw, "Failed to allocate memory for No.%u tx ring!", 1479 q_info->idx); 1480 return NULL; 1481 } 1482 1483 /* Allocate tx ring hardware descriptors. */ 1484 txq->queue_id = q_info->idx; 1485 txq->nb_tx_desc = q_info->nb_desc; 1486 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc); 1487 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx, 1488 tx_desc, HNS3_RING_BASE_ALIGN, 1489 q_info->socket_id); 1490 if (tx_mz == NULL) { 1491 hns3_err(hw, "Failed to reserve DMA memory for No.%u tx ring!", 1492 q_info->idx); 1493 hns3_tx_queue_release(txq); 1494 return NULL; 1495 } 1496 txq->mz = tx_mz; 1497 txq->tx_ring = (struct hns3_desc *)tx_mz->addr; 1498 txq->tx_ring_phys_addr = tx_mz->iova; 1499 1500 /* Clear tx bd */ 1501 desc = txq->tx_ring; 1502 for (i = 0; i < txq->nb_tx_desc; i++) { 1503 desc->tx.tp_fe_sc_vld_ra_ri = 0; 1504 desc++; 1505 } 1506 1507 return txq; 1508 } 1509 1510 static int 1511 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, 1512 uint16_t nb_desc, unsigned int socket_id) 1513 { 1514 struct hns3_adapter *hns = dev->data->dev_private; 1515 struct hns3_hw *hw = &hns->hw; 1516 struct hns3_queue_info q_info; 1517 struct hns3_tx_queue *txq; 1518 uint16_t nb_tx_q; 1519 1520 if (hw->fkq_data.tx_queues[idx] != NULL) { 1521 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]); 1522 hw->fkq_data.tx_queues[idx] = NULL; 1523 } 1524 1525 q_info.idx = idx; 1526 q_info.socket_id = socket_id; 1527 q_info.nb_desc = nb_desc; 1528 q_info.type = "hns3 fake TX queue"; 1529 q_info.ring_name = "tx_fake_ring"; 1530 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info); 1531 if (txq == NULL) { 1532 hns3_err(hw, "Failed to setup No.%u fake tx ring.", idx); 1533 return -ENOMEM; 1534 } 1535 1536 /* Don't need alloc sw_ring, because upper applications don't use it */ 1537 txq->sw_ring = NULL; 1538 txq->free = NULL; 1539 1540 txq->hns = hns; 1541 txq->tx_deferred_start = false; 1542 txq->port_id = dev->data->port_id; 1543 txq->configured = true; 1544 nb_tx_q = dev->data->nb_tx_queues; 1545 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + 1546 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE); 1547 1548 rte_spinlock_lock(&hw->lock); 1549 hw->fkq_data.tx_queues[idx] = txq; 1550 rte_spinlock_unlock(&hw->lock); 1551 1552 return 0; 1553 } 1554 1555 static int 1556 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues) 1557 { 1558 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues; 1559 void **rxq; 1560 uint16_t i; 1561 1562 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) { 1563 /* first time configuration */ 1564 uint32_t size; 1565 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues; 1566 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size, 1567 RTE_CACHE_LINE_SIZE); 1568 if (hw->fkq_data.rx_queues == NULL) { 1569 hw->fkq_data.nb_fake_rx_queues = 0; 1570 return -ENOMEM; 1571 } 1572 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) { 1573 /* re-configure */ 1574 rxq = hw->fkq_data.rx_queues; 1575 for (i = nb_queues; i < old_nb_queues; i++) 1576 hns3_rx_queue_release_lock(rxq[i]); 1577 1578 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues, 1579 RTE_CACHE_LINE_SIZE); 1580 if (rxq == NULL) 1581 return -ENOMEM; 1582 if (nb_queues > old_nb_queues) { 1583 uint16_t new_qs = nb_queues - old_nb_queues; 1584 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs); 1585 } 1586 1587 hw->fkq_data.rx_queues = rxq; 1588 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) { 1589 rxq = hw->fkq_data.rx_queues; 1590 for (i = nb_queues; i < old_nb_queues; i++) 1591 hns3_rx_queue_release_lock(rxq[i]); 1592 1593 rte_free(hw->fkq_data.rx_queues); 1594 hw->fkq_data.rx_queues = NULL; 1595 } 1596 1597 hw->fkq_data.nb_fake_rx_queues = nb_queues; 1598 1599 return 0; 1600 } 1601 1602 static int 1603 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues) 1604 { 1605 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues; 1606 void **txq; 1607 uint16_t i; 1608 1609 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) { 1610 /* first time configuration */ 1611 uint32_t size; 1612 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues; 1613 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size, 1614 RTE_CACHE_LINE_SIZE); 1615 if (hw->fkq_data.tx_queues == NULL) { 1616 hw->fkq_data.nb_fake_tx_queues = 0; 1617 return -ENOMEM; 1618 } 1619 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) { 1620 /* re-configure */ 1621 txq = hw->fkq_data.tx_queues; 1622 for (i = nb_queues; i < old_nb_queues; i++) 1623 hns3_tx_queue_release_lock(txq[i]); 1624 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues, 1625 RTE_CACHE_LINE_SIZE); 1626 if (txq == NULL) 1627 return -ENOMEM; 1628 if (nb_queues > old_nb_queues) { 1629 uint16_t new_qs = nb_queues - old_nb_queues; 1630 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs); 1631 } 1632 1633 hw->fkq_data.tx_queues = txq; 1634 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) { 1635 txq = hw->fkq_data.tx_queues; 1636 for (i = nb_queues; i < old_nb_queues; i++) 1637 hns3_tx_queue_release_lock(txq[i]); 1638 1639 rte_free(hw->fkq_data.tx_queues); 1640 hw->fkq_data.tx_queues = NULL; 1641 } 1642 hw->fkq_data.nb_fake_tx_queues = nb_queues; 1643 1644 return 0; 1645 } 1646 1647 int 1648 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q, 1649 uint16_t nb_tx_q) 1650 { 1651 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1652 uint16_t rx_need_add_nb_q; 1653 uint16_t tx_need_add_nb_q; 1654 uint16_t port_id; 1655 uint16_t q; 1656 int ret; 1657 1658 if (hns3_dev_get_support(hw, INDEP_TXRX)) 1659 return 0; 1660 1661 /* Setup new number of fake RX/TX queues and reconfigure device. */ 1662 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q; 1663 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q; 1664 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q); 1665 if (ret) { 1666 hns3_err(hw, "Fail to configure fake rx queues: %d", ret); 1667 return ret; 1668 } 1669 1670 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q); 1671 if (ret) { 1672 hns3_err(hw, "Fail to configure fake tx queues: %d", ret); 1673 goto cfg_fake_tx_q_fail; 1674 } 1675 1676 /* Allocate and set up fake RX queue per Ethernet port. */ 1677 port_id = hw->data->port_id; 1678 for (q = 0; q < rx_need_add_nb_q; q++) { 1679 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC, 1680 rte_eth_dev_socket_id(port_id)); 1681 if (ret) 1682 goto setup_fake_rx_q_fail; 1683 } 1684 1685 /* Allocate and set up fake TX queue per Ethernet port. */ 1686 for (q = 0; q < tx_need_add_nb_q; q++) { 1687 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC, 1688 rte_eth_dev_socket_id(port_id)); 1689 if (ret) 1690 goto setup_fake_tx_q_fail; 1691 } 1692 1693 return 0; 1694 1695 setup_fake_tx_q_fail: 1696 setup_fake_rx_q_fail: 1697 (void)hns3_fake_tx_queue_config(hw, 0); 1698 cfg_fake_tx_q_fail: 1699 (void)hns3_fake_rx_queue_config(hw, 0); 1700 1701 return ret; 1702 } 1703 1704 void 1705 hns3_dev_release_mbufs(struct hns3_adapter *hns) 1706 { 1707 struct rte_eth_dev_data *dev_data = hns->hw.data; 1708 struct hns3_rx_queue *rxq; 1709 struct hns3_tx_queue *txq; 1710 uint16_t i; 1711 1712 if (dev_data->rx_queues) 1713 for (i = 0; i < dev_data->nb_rx_queues; i++) { 1714 rxq = dev_data->rx_queues[i]; 1715 if (rxq == NULL) 1716 continue; 1717 hns3_rx_queue_release_mbufs(rxq); 1718 } 1719 1720 if (dev_data->tx_queues) 1721 for (i = 0; i < dev_data->nb_tx_queues; i++) { 1722 txq = dev_data->tx_queues[i]; 1723 if (txq == NULL) 1724 continue; 1725 hns3_tx_queue_release_mbufs(txq); 1726 } 1727 } 1728 1729 static int 1730 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len) 1731 { 1732 uint16_t vld_buf_size; 1733 uint16_t num_hw_specs; 1734 uint16_t i; 1735 1736 /* 1737 * hns3 network engine only support to set 4 typical specification, and 1738 * different buffer size will affect the max packet_len and the max 1739 * number of segmentation when hw gro is turned on in receive side. The 1740 * relationship between them is as follows: 1741 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg 1742 * ---------------------|-------------------|---------------- 1743 * HNS3_4K_BD_BUF_SIZE | 60KB | 15 1744 * HNS3_2K_BD_BUF_SIZE | 62KB | 31 1745 * HNS3_1K_BD_BUF_SIZE | 63KB | 63 1746 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63 1747 */ 1748 static const uint16_t hw_rx_buf_size[] = { 1749 HNS3_4K_BD_BUF_SIZE, 1750 HNS3_2K_BD_BUF_SIZE, 1751 HNS3_1K_BD_BUF_SIZE, 1752 HNS3_512_BD_BUF_SIZE 1753 }; 1754 1755 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) - 1756 RTE_PKTMBUF_HEADROOM); 1757 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE) 1758 return -EINVAL; 1759 1760 num_hw_specs = RTE_DIM(hw_rx_buf_size); 1761 for (i = 0; i < num_hw_specs; i++) { 1762 if (vld_buf_size >= hw_rx_buf_size[i]) { 1763 *rx_buf_len = hw_rx_buf_size[i]; 1764 break; 1765 } 1766 } 1767 return 0; 1768 } 1769 1770 static int 1771 hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size, 1772 uint16_t nb_desc) 1773 { 1774 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1775 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 1776 uint32_t frame_size = dev->data->mtu + HNS3_ETH_OVERHEAD; 1777 uint16_t min_vec_bds; 1778 1779 /* 1780 * HNS3 hardware network engine set scattered as default. If the driver 1781 * is not work in scattered mode and the pkts greater than buf_size 1782 * but smaller than frame size will be distributed to multiple BDs. 1783 * Driver cannot handle this situation. 1784 */ 1785 if (!hw->data->scattered_rx && frame_size > buf_size) { 1786 hns3_err(hw, "frame size is not allowed to be set greater " 1787 "than rx_buf_len if scattered is off."); 1788 return -EINVAL; 1789 } 1790 1791 if (pkt_burst == hns3_recv_pkts_vec || 1792 pkt_burst == hns3_recv_pkts_vec_sve) { 1793 min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH + 1794 HNS3_DEFAULT_RX_BURST; 1795 if (nb_desc < min_vec_bds || 1796 nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) { 1797 hns3_err(hw, "if Rx burst mode is vector, " 1798 "number of descriptor is required to be " 1799 "bigger than min vector bds:%u, and could be " 1800 "divided by rxq rearm thresh:%u.", 1801 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH); 1802 return -EINVAL; 1803 } 1804 } 1805 return 0; 1806 } 1807 1808 static int 1809 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf, 1810 struct rte_mempool *mp, uint16_t nb_desc, 1811 uint16_t *buf_size) 1812 { 1813 int ret; 1814 1815 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC || 1816 nb_desc % HNS3_ALIGN_RING_DESC) { 1817 hns3_err(hw, "Number (%u) of rx descriptors is invalid", 1818 nb_desc); 1819 return -EINVAL; 1820 } 1821 1822 if (conf->rx_free_thresh >= nb_desc) { 1823 hns3_err(hw, "rx_free_thresh (%u) must be less than %u", 1824 conf->rx_free_thresh, nb_desc); 1825 return -EINVAL; 1826 } 1827 1828 if (conf->rx_drop_en == 0) 1829 hns3_warn(hw, "if no descriptors available, packets are always " 1830 "dropped and rx_drop_en (1) is fixed on"); 1831 1832 if (hns3_rx_buf_len_calc(mp, buf_size)) { 1833 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! " 1834 "minimal data room size (%u).", 1835 rte_pktmbuf_data_room_size(mp), 1836 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM); 1837 return -EINVAL; 1838 } 1839 1840 if (hw->data->dev_started) { 1841 ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc); 1842 if (ret) { 1843 hns3_err(hw, "Rx queue runtime setup fail."); 1844 return ret; 1845 } 1846 } 1847 1848 return 0; 1849 } 1850 1851 uint32_t 1852 hns3_get_tqp_reg_offset(uint16_t queue_id) 1853 { 1854 uint32_t reg_offset; 1855 1856 /* Need an extend offset to config queue > 1024 */ 1857 if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID) 1858 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE; 1859 else 1860 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET + 1861 (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) * 1862 HNS3_TQP_REG_SIZE; 1863 1864 return reg_offset; 1865 } 1866 1867 int 1868 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, 1869 unsigned int socket_id, const struct rte_eth_rxconf *conf, 1870 struct rte_mempool *mp) 1871 { 1872 struct hns3_adapter *hns = dev->data->dev_private; 1873 struct hns3_hw *hw = &hns->hw; 1874 struct hns3_queue_info q_info; 1875 struct hns3_rx_queue *rxq; 1876 uint16_t rx_buf_size; 1877 int rx_entry_len; 1878 int ret; 1879 1880 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size); 1881 if (ret) 1882 return ret; 1883 1884 if (dev->data->rx_queues[idx]) { 1885 hns3_rx_queue_release(dev->data->rx_queues[idx]); 1886 dev->data->rx_queues[idx] = NULL; 1887 } 1888 1889 q_info.idx = idx; 1890 q_info.socket_id = socket_id; 1891 q_info.nb_desc = nb_desc; 1892 q_info.type = "hns3 RX queue"; 1893 q_info.ring_name = "rx_ring"; 1894 1895 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info); 1896 if (rxq == NULL) { 1897 hns3_err(hw, 1898 "Failed to alloc mem and reserve DMA mem for rx ring!"); 1899 return -ENOMEM; 1900 } 1901 1902 rxq->hns = hns; 1903 rxq->ptype_tbl = &hns->ptype_tbl; 1904 rxq->mb_pool = mp; 1905 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ? 1906 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH; 1907 1908 rxq->rx_deferred_start = conf->rx_deferred_start; 1909 if (rxq->rx_deferred_start && !hns3_dev_get_support(hw, INDEP_TXRX)) { 1910 hns3_warn(hw, "deferred start is not supported."); 1911 rxq->rx_deferred_start = false; 1912 } 1913 1914 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) * 1915 sizeof(struct hns3_entry); 1916 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len, 1917 RTE_CACHE_LINE_SIZE, socket_id); 1918 if (rxq->sw_ring == NULL) { 1919 hns3_err(hw, "Failed to allocate memory for rx sw ring!"); 1920 hns3_rx_queue_release(rxq); 1921 return -ENOMEM; 1922 } 1923 1924 rxq->next_to_use = 0; 1925 rxq->rx_free_hold = 0; 1926 rxq->rx_rearm_start = 0; 1927 rxq->rx_rearm_nb = 0; 1928 rxq->pkt_first_seg = NULL; 1929 rxq->pkt_last_seg = NULL; 1930 rxq->port_id = dev->data->port_id; 1931 /* 1932 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE, 1933 * the pvid_sw_discard_en in the queue struct should not be changed, 1934 * because PVID-related operations do not need to be processed by PMD. 1935 * For hns3 VF device, whether it needs to process PVID depends 1936 * on the configuration of PF kernel mode netdevice driver. And the 1937 * related PF configuration is delivered through the mailbox and finally 1938 * reflected in port_base_vlan_cfg. 1939 */ 1940 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 1941 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state == 1942 HNS3_PORT_BASE_VLAN_ENABLE; 1943 else 1944 rxq->pvid_sw_discard_en = false; 1945 rxq->ptype_en = hns3_dev_get_support(hw, RXD_ADV_LAYOUT) ? true : false; 1946 rxq->configured = true; 1947 rxq->io_base = (void *)((char *)hw->io_base + 1948 hns3_get_tqp_reg_offset(idx)); 1949 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base + 1950 HNS3_RING_RX_HEAD_REG); 1951 rxq->rx_buf_len = rx_buf_size; 1952 memset(&rxq->basic_stats, 0, sizeof(struct hns3_rx_basic_stats)); 1953 memset(&rxq->err_stats, 0, sizeof(struct hns3_rx_bd_errors_stats)); 1954 memset(&rxq->dfx_stats, 0, sizeof(struct hns3_rx_dfx_stats)); 1955 1956 /* CRC len set here is used for amending packet length */ 1957 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) 1958 rxq->crc_len = RTE_ETHER_CRC_LEN; 1959 else 1960 rxq->crc_len = 0; 1961 1962 rxq->bulk_mbuf_num = 0; 1963 1964 rte_spinlock_lock(&hw->lock); 1965 dev->data->rx_queues[idx] = rxq; 1966 rte_spinlock_unlock(&hw->lock); 1967 1968 return 0; 1969 } 1970 1971 void 1972 hns3_rx_scattered_reset(struct rte_eth_dev *dev) 1973 { 1974 struct hns3_adapter *hns = dev->data->dev_private; 1975 struct hns3_hw *hw = &hns->hw; 1976 1977 hw->rx_buf_len = 0; 1978 dev->data->scattered_rx = false; 1979 } 1980 1981 void 1982 hns3_rx_scattered_calc(struct rte_eth_dev *dev) 1983 { 1984 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1985 struct hns3_adapter *hns = dev->data->dev_private; 1986 struct hns3_hw *hw = &hns->hw; 1987 struct hns3_rx_queue *rxq; 1988 uint32_t queue_id; 1989 1990 if (dev->data->rx_queues == NULL) 1991 return; 1992 1993 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) { 1994 rxq = dev->data->rx_queues[queue_id]; 1995 if (hw->rx_buf_len == 0) 1996 hw->rx_buf_len = rxq->rx_buf_len; 1997 else 1998 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len, 1999 rxq->rx_buf_len); 2000 } 2001 2002 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER || 2003 dev->data->mtu + HNS3_ETH_OVERHEAD > hw->rx_buf_len) 2004 dev->data->scattered_rx = true; 2005 } 2006 2007 const uint32_t * 2008 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 2009 { 2010 static const uint32_t ptypes[] = { 2011 RTE_PTYPE_L2_ETHER, 2012 RTE_PTYPE_L2_ETHER_LLDP, 2013 RTE_PTYPE_L2_ETHER_ARP, 2014 RTE_PTYPE_L3_IPV4, 2015 RTE_PTYPE_L3_IPV4_EXT, 2016 RTE_PTYPE_L3_IPV6, 2017 RTE_PTYPE_L3_IPV6_EXT, 2018 RTE_PTYPE_L4_IGMP, 2019 RTE_PTYPE_L4_ICMP, 2020 RTE_PTYPE_L4_SCTP, 2021 RTE_PTYPE_L4_TCP, 2022 RTE_PTYPE_L4_UDP, 2023 RTE_PTYPE_TUNNEL_GRE, 2024 RTE_PTYPE_INNER_L2_ETHER, 2025 RTE_PTYPE_INNER_L3_IPV4, 2026 RTE_PTYPE_INNER_L3_IPV6, 2027 RTE_PTYPE_INNER_L3_IPV4_EXT, 2028 RTE_PTYPE_INNER_L3_IPV6_EXT, 2029 RTE_PTYPE_INNER_L4_UDP, 2030 RTE_PTYPE_INNER_L4_TCP, 2031 RTE_PTYPE_INNER_L4_SCTP, 2032 RTE_PTYPE_INNER_L4_ICMP, 2033 RTE_PTYPE_TUNNEL_GRENAT, 2034 RTE_PTYPE_TUNNEL_NVGRE, 2035 }; 2036 static const uint32_t adv_layout_ptypes[] = { 2037 RTE_PTYPE_L2_ETHER, 2038 RTE_PTYPE_L2_ETHER_TIMESYNC, 2039 RTE_PTYPE_L2_ETHER_LLDP, 2040 RTE_PTYPE_L2_ETHER_ARP, 2041 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 2042 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 2043 RTE_PTYPE_L4_FRAG, 2044 RTE_PTYPE_L4_NONFRAG, 2045 RTE_PTYPE_L4_UDP, 2046 RTE_PTYPE_L4_TCP, 2047 RTE_PTYPE_L4_SCTP, 2048 RTE_PTYPE_L4_IGMP, 2049 RTE_PTYPE_L4_ICMP, 2050 RTE_PTYPE_TUNNEL_GRE, 2051 RTE_PTYPE_TUNNEL_GRENAT, 2052 RTE_PTYPE_INNER_L2_ETHER, 2053 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 2054 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 2055 RTE_PTYPE_INNER_L4_FRAG, 2056 RTE_PTYPE_INNER_L4_ICMP, 2057 RTE_PTYPE_INNER_L4_NONFRAG, 2058 RTE_PTYPE_INNER_L4_UDP, 2059 RTE_PTYPE_INNER_L4_TCP, 2060 RTE_PTYPE_INNER_L4_SCTP, 2061 RTE_PTYPE_INNER_L4_ICMP, 2062 }; 2063 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2064 2065 if (dev->rx_pkt_burst == hns3_recv_pkts_simple || 2066 dev->rx_pkt_burst == hns3_recv_scattered_pkts || 2067 dev->rx_pkt_burst == hns3_recv_pkts_vec || 2068 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) { 2069 if (hns3_dev_get_support(hw, RXD_ADV_LAYOUT)) { 2070 *no_of_elements = RTE_DIM(adv_layout_ptypes); 2071 return adv_layout_ptypes; 2072 } else { 2073 *no_of_elements = RTE_DIM(ptypes); 2074 return ptypes; 2075 } 2076 } 2077 2078 return NULL; 2079 } 2080 2081 static void 2082 hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl) 2083 { 2084 tbl->l3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4; 2085 tbl->l3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6; 2086 tbl->l3table[2] = RTE_PTYPE_L2_ETHER_ARP; 2087 tbl->l3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT; 2088 tbl->l3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT; 2089 tbl->l3table[6] = RTE_PTYPE_L2_ETHER_LLDP; 2090 2091 tbl->l4table[0] = RTE_PTYPE_L4_UDP; 2092 tbl->l4table[1] = RTE_PTYPE_L4_TCP; 2093 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE; 2094 tbl->l4table[3] = RTE_PTYPE_L4_SCTP; 2095 tbl->l4table[4] = RTE_PTYPE_L4_IGMP; 2096 tbl->l4table[5] = RTE_PTYPE_L4_ICMP; 2097 } 2098 2099 static void 2100 hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl) 2101 { 2102 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L2_ETHER | 2103 RTE_PTYPE_INNER_L3_IPV4; 2104 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L2_ETHER | 2105 RTE_PTYPE_INNER_L3_IPV6; 2106 /* There is not a ptype for inner ARP/RARP */ 2107 tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN; 2108 tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN; 2109 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L2_ETHER | 2110 RTE_PTYPE_INNER_L3_IPV4_EXT; 2111 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L2_ETHER | 2112 RTE_PTYPE_INNER_L3_IPV6_EXT; 2113 2114 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP; 2115 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP; 2116 /* There is not a ptype for inner GRE */ 2117 tbl->inner_l4table[2] = RTE_PTYPE_UNKNOWN; 2118 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP; 2119 /* There is not a ptype for inner IGMP */ 2120 tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN; 2121 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP; 2122 2123 tbl->ol3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4; 2124 tbl->ol3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6; 2125 tbl->ol3table[2] = RTE_PTYPE_UNKNOWN; 2126 tbl->ol3table[3] = RTE_PTYPE_UNKNOWN; 2127 tbl->ol3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT; 2128 tbl->ol3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT; 2129 2130 tbl->ol4table[0] = RTE_PTYPE_UNKNOWN; 2131 tbl->ol4table[1] = RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_GRENAT; 2132 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE; 2133 } 2134 2135 static void 2136 hns3_init_adv_layout_ptype(struct hns3_ptype_table *tbl) 2137 { 2138 uint32_t *ptype = tbl->ptype; 2139 2140 /* Non-tunnel L2 */ 2141 ptype[1] = RTE_PTYPE_L2_ETHER_ARP; 2142 ptype[3] = RTE_PTYPE_L2_ETHER_LLDP; 2143 ptype[8] = RTE_PTYPE_L2_ETHER_TIMESYNC; 2144 2145 /* Non-tunnel IPv4 */ 2146 ptype[17] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2147 RTE_PTYPE_L4_FRAG; 2148 ptype[18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2149 RTE_PTYPE_L4_NONFRAG; 2150 ptype[19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2151 RTE_PTYPE_L4_UDP; 2152 ptype[20] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2153 RTE_PTYPE_L4_TCP; 2154 ptype[21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2155 RTE_PTYPE_TUNNEL_GRE; 2156 ptype[22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2157 RTE_PTYPE_L4_SCTP; 2158 ptype[23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2159 RTE_PTYPE_L4_IGMP; 2160 ptype[24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2161 RTE_PTYPE_L4_ICMP; 2162 /* The next ptype is PTP over IPv4 + UDP */ 2163 ptype[25] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2164 RTE_PTYPE_L4_UDP; 2165 2166 /* IPv4 --> GRE/Teredo/VXLAN */ 2167 ptype[29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2168 RTE_PTYPE_TUNNEL_GRENAT; 2169 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */ 2170 ptype[30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2171 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER; 2172 2173 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */ 2174 ptype[31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2175 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2177 RTE_PTYPE_INNER_L4_FRAG; 2178 ptype[32] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2179 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2180 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2181 RTE_PTYPE_INNER_L4_NONFRAG; 2182 ptype[33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2183 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2184 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2185 RTE_PTYPE_INNER_L4_UDP; 2186 ptype[34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2187 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2189 RTE_PTYPE_INNER_L4_TCP; 2190 ptype[35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2191 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2192 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2193 RTE_PTYPE_INNER_L4_SCTP; 2194 /* The next ptype's inner L4 is IGMP */ 2195 ptype[36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2196 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2197 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 2198 ptype[37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2199 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2201 RTE_PTYPE_INNER_L4_ICMP; 2202 2203 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */ 2204 ptype[39] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2205 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2206 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2207 RTE_PTYPE_INNER_L4_FRAG; 2208 ptype[40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2209 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2211 RTE_PTYPE_INNER_L4_NONFRAG; 2212 ptype[41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2213 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2215 RTE_PTYPE_INNER_L4_UDP; 2216 ptype[42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2217 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2218 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2219 RTE_PTYPE_INNER_L4_TCP; 2220 ptype[43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2221 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2222 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2223 RTE_PTYPE_INNER_L4_SCTP; 2224 /* The next ptype's inner L4 is IGMP */ 2225 ptype[44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2226 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2227 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 2228 ptype[45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | 2229 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2230 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2231 RTE_PTYPE_INNER_L4_ICMP; 2232 2233 /* Non-tunnel IPv6 */ 2234 ptype[111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2235 RTE_PTYPE_L4_FRAG; 2236 ptype[112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2237 RTE_PTYPE_L4_NONFRAG; 2238 ptype[113] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2239 RTE_PTYPE_L4_UDP; 2240 ptype[114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2241 RTE_PTYPE_L4_TCP; 2242 ptype[115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2243 RTE_PTYPE_TUNNEL_GRE; 2244 ptype[116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2245 RTE_PTYPE_L4_SCTP; 2246 ptype[117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2247 RTE_PTYPE_L4_IGMP; 2248 ptype[118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2249 RTE_PTYPE_L4_ICMP; 2250 /* Special for PTP over IPv6 + UDP */ 2251 ptype[119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2252 RTE_PTYPE_L4_UDP; 2253 2254 /* IPv6 --> GRE/Teredo/VXLAN */ 2255 ptype[123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2256 RTE_PTYPE_TUNNEL_GRENAT; 2257 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */ 2258 ptype[124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2259 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER; 2260 2261 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */ 2262 ptype[125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2263 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2264 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2265 RTE_PTYPE_INNER_L4_FRAG; 2266 ptype[126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2267 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2268 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2269 RTE_PTYPE_INNER_L4_NONFRAG; 2270 ptype[127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2271 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2272 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2273 RTE_PTYPE_INNER_L4_UDP; 2274 ptype[128] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2275 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2276 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2277 RTE_PTYPE_INNER_L4_TCP; 2278 ptype[129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2279 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2280 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2281 RTE_PTYPE_INNER_L4_SCTP; 2282 /* The next ptype's inner L4 is IGMP */ 2283 ptype[130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2284 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2285 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 2286 ptype[131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2287 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2288 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | 2289 RTE_PTYPE_INNER_L4_ICMP; 2290 2291 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */ 2292 ptype[133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2293 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2294 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2295 RTE_PTYPE_INNER_L4_FRAG; 2296 ptype[134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2297 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2298 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2299 RTE_PTYPE_INNER_L4_NONFRAG; 2300 ptype[135] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2301 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2302 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2303 RTE_PTYPE_INNER_L4_UDP; 2304 ptype[136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2305 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2306 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2307 RTE_PTYPE_INNER_L4_TCP; 2308 ptype[137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2309 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2310 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2311 RTE_PTYPE_INNER_L4_SCTP; 2312 /* The next ptype's inner L4 is IGMP */ 2313 ptype[138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2314 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2315 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 2316 ptype[139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | 2317 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER | 2318 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | 2319 RTE_PTYPE_INNER_L4_ICMP; 2320 } 2321 2322 void 2323 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev) 2324 { 2325 struct hns3_adapter *hns = dev->data->dev_private; 2326 struct hns3_ptype_table *tbl = &hns->ptype_tbl; 2327 2328 memset(tbl, 0, sizeof(*tbl)); 2329 2330 hns3_init_non_tunnel_ptype_tbl(tbl); 2331 hns3_init_tunnel_ptype_tbl(tbl); 2332 hns3_init_adv_layout_ptype(tbl); 2333 } 2334 2335 static inline void 2336 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb, 2337 uint32_t l234_info, const struct hns3_desc *rxd) 2338 { 2339 #define HNS3_STRP_STATUS_NUM 0x4 2340 2341 #define HNS3_NO_STRP_VLAN_VLD 0x0 2342 #define HNS3_INNER_STRP_VLAN_VLD 0x1 2343 #define HNS3_OUTER_STRP_VLAN_VLD 0x2 2344 uint32_t strip_status; 2345 uint32_t report_mode; 2346 2347 /* 2348 * Since HW limitation, the vlan tag will always be inserted into RX 2349 * descriptor when strip the tag from packet, driver needs to determine 2350 * reporting which tag to mbuf according to the PVID configuration 2351 * and vlan striped status. 2352 */ 2353 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = { 2354 { 2355 HNS3_NO_STRP_VLAN_VLD, 2356 HNS3_OUTER_STRP_VLAN_VLD, 2357 HNS3_INNER_STRP_VLAN_VLD, 2358 HNS3_OUTER_STRP_VLAN_VLD 2359 }, 2360 { 2361 HNS3_NO_STRP_VLAN_VLD, 2362 HNS3_NO_STRP_VLAN_VLD, 2363 HNS3_NO_STRP_VLAN_VLD, 2364 HNS3_INNER_STRP_VLAN_VLD 2365 } 2366 }; 2367 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M, 2368 HNS3_RXD_STRP_TAGP_S); 2369 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status]; 2370 switch (report_mode) { 2371 case HNS3_NO_STRP_VLAN_VLD: 2372 mb->vlan_tci = 0; 2373 return; 2374 case HNS3_INNER_STRP_VLAN_VLD: 2375 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED; 2376 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag); 2377 return; 2378 case HNS3_OUTER_STRP_VLAN_VLD: 2379 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED; 2380 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag); 2381 return; 2382 default: 2383 mb->vlan_tci = 0; 2384 return; 2385 } 2386 } 2387 2388 static inline void 2389 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg, 2390 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq, 2391 uint16_t data_len) 2392 { 2393 uint8_t crc_len = rxq->crc_len; 2394 2395 if (data_len <= crc_len) { 2396 rte_pktmbuf_free_seg(rxm); 2397 first_seg->nb_segs--; 2398 last_seg->data_len = (uint16_t)(last_seg->data_len - 2399 (crc_len - data_len)); 2400 last_seg->next = NULL; 2401 } else 2402 rxm->data_len = (uint16_t)(data_len - crc_len); 2403 } 2404 2405 static inline struct rte_mbuf * 2406 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq) 2407 { 2408 int ret; 2409 2410 if (likely(rxq->bulk_mbuf_num > 0)) 2411 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num]; 2412 2413 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf, 2414 HNS3_BULK_ALLOC_MBUF_NUM); 2415 if (likely(ret == 0)) { 2416 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM; 2417 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num]; 2418 } else 2419 return rte_mbuf_raw_alloc(rxq->mb_pool); 2420 } 2421 2422 static void 2423 hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf, 2424 uint64_t timestamp) 2425 { 2426 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns); 2427 2428 mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_TMST; 2429 if (hns3_timestamp_rx_dynflag > 0) { 2430 *RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset, 2431 rte_mbuf_timestamp_t *) = timestamp; 2432 mbuf->ol_flags |= hns3_timestamp_rx_dynflag; 2433 } 2434 2435 pf->rx_timestamp = timestamp; 2436 } 2437 2438 uint16_t 2439 hns3_recv_pkts_simple(void *rx_queue, 2440 struct rte_mbuf **rx_pkts, 2441 uint16_t nb_pkts) 2442 { 2443 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */ 2444 volatile struct hns3_desc *rxdp; /* pointer of the current desc */ 2445 struct hns3_rx_queue *rxq; /* RX queue */ 2446 struct hns3_entry *sw_ring; 2447 struct hns3_entry *rxe; 2448 struct hns3_desc rxd; 2449 struct rte_mbuf *nmb; /* pointer of the new mbuf */ 2450 struct rte_mbuf *rxm; 2451 uint32_t bd_base_info; 2452 uint32_t l234_info; 2453 uint32_t ol_info; 2454 uint64_t dma_addr; 2455 uint16_t nb_rx_bd; 2456 uint16_t nb_rx; 2457 uint16_t rx_id; 2458 int ret; 2459 2460 nb_rx = 0; 2461 nb_rx_bd = 0; 2462 rxq = rx_queue; 2463 rx_ring = rxq->rx_ring; 2464 sw_ring = rxq->sw_ring; 2465 rx_id = rxq->next_to_use; 2466 2467 while (nb_rx < nb_pkts) { 2468 rxdp = &rx_ring[rx_id]; 2469 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); 2470 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 2471 break; 2472 2473 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) - 2474 (1u << HNS3_RXD_VLD_B)]; 2475 2476 nmb = hns3_rx_alloc_buffer(rxq); 2477 if (unlikely(nmb == NULL)) { 2478 rte_eth_devices[rxq->port_id].data-> 2479 rx_mbuf_alloc_failed++; 2480 break; 2481 } 2482 2483 nb_rx_bd++; 2484 rxe = &sw_ring[rx_id]; 2485 rx_id++; 2486 if (unlikely(rx_id == rxq->nb_rx_desc)) 2487 rx_id = 0; 2488 2489 rte_prefetch0(sw_ring[rx_id].mbuf); 2490 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) { 2491 rte_prefetch0(&rx_ring[rx_id]); 2492 rte_prefetch0(&sw_ring[rx_id]); 2493 } 2494 2495 rxm = rxe->mbuf; 2496 rxm->ol_flags = 0; 2497 rxe->mbuf = nmb; 2498 2499 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) 2500 hns3_rx_ptp_timestamp_handle(rxq, rxm, 2501 rte_le_to_cpu_64(rxdp->timestamp)); 2502 2503 dma_addr = rte_mbuf_data_iova_default(nmb); 2504 rxdp->addr = rte_cpu_to_le_64(dma_addr); 2505 rxdp->rx.bd_base_info = 0; 2506 2507 rxm->data_off = RTE_PKTMBUF_HEADROOM; 2508 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) - 2509 rxq->crc_len; 2510 rxm->data_len = rxm->pkt_len; 2511 rxm->port = rxq->port_id; 2512 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash); 2513 rxm->ol_flags |= RTE_MBUF_F_RX_RSS_HASH; 2514 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) { 2515 rxm->hash.fdir.hi = 2516 rte_le_to_cpu_16(rxd.rx.fd_id); 2517 rxm->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID; 2518 } 2519 rxm->nb_segs = 1; 2520 rxm->next = NULL; 2521 2522 /* Load remained descriptor data and extract necessary fields */ 2523 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info); 2524 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info); 2525 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info, l234_info); 2526 if (unlikely(ret)) 2527 goto pkt_err; 2528 2529 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info); 2530 2531 if (rxm->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) 2532 rxm->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP; 2533 2534 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd); 2535 2536 /* Increment bytes counter */ 2537 rxq->basic_stats.bytes += rxm->pkt_len; 2538 2539 rx_pkts[nb_rx++] = rxm; 2540 continue; 2541 pkt_err: 2542 rte_pktmbuf_free(rxm); 2543 } 2544 2545 rxq->next_to_use = rx_id; 2546 rxq->rx_free_hold += nb_rx_bd; 2547 if (rxq->rx_free_hold > rxq->rx_free_thresh) { 2548 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold); 2549 rxq->rx_free_hold = 0; 2550 } 2551 2552 return nb_rx; 2553 } 2554 2555 uint16_t 2556 hns3_recv_scattered_pkts(void *rx_queue, 2557 struct rte_mbuf **rx_pkts, 2558 uint16_t nb_pkts) 2559 { 2560 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */ 2561 volatile struct hns3_desc *rxdp; /* pointer of the current desc */ 2562 struct hns3_rx_queue *rxq; /* RX queue */ 2563 struct hns3_entry *sw_ring; 2564 struct hns3_entry *rxe; 2565 struct rte_mbuf *first_seg; 2566 struct rte_mbuf *last_seg; 2567 struct hns3_desc rxd; 2568 struct rte_mbuf *nmb; /* pointer of the new mbuf */ 2569 struct rte_mbuf *rxm; 2570 struct rte_eth_dev *dev; 2571 uint32_t bd_base_info; 2572 uint64_t timestamp; 2573 uint32_t l234_info; 2574 uint32_t gro_size; 2575 uint32_t ol_info; 2576 uint64_t dma_addr; 2577 uint16_t nb_rx_bd; 2578 uint16_t nb_rx; 2579 uint16_t rx_id; 2580 int ret; 2581 2582 nb_rx = 0; 2583 nb_rx_bd = 0; 2584 rxq = rx_queue; 2585 2586 rx_id = rxq->next_to_use; 2587 rx_ring = rxq->rx_ring; 2588 sw_ring = rxq->sw_ring; 2589 first_seg = rxq->pkt_first_seg; 2590 last_seg = rxq->pkt_last_seg; 2591 2592 while (nb_rx < nb_pkts) { 2593 rxdp = &rx_ring[rx_id]; 2594 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); 2595 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 2596 break; 2597 2598 /* 2599 * The interactive process between software and hardware of 2600 * receiving a new packet in hns3 network engine: 2601 * 1. Hardware network engine firstly writes the packet content 2602 * to the memory pointed by the 'addr' field of the Rx Buffer 2603 * Descriptor, secondly fills the result of parsing the 2604 * packet include the valid field into the Rx Buffer 2605 * Descriptor in one write operation. 2606 * 2. Driver reads the Rx BD's valid field in the loop to check 2607 * whether it's valid, if valid then assign a new address to 2608 * the addr field, clear the valid field, get the other 2609 * information of the packet by parsing Rx BD's other fields, 2610 * finally write back the number of Rx BDs processed by the 2611 * driver to the HNS3_RING_RX_HEAD_REG register to inform 2612 * hardware. 2613 * In the above process, the ordering is very important. We must 2614 * make sure that CPU read Rx BD's other fields only after the 2615 * Rx BD is valid. 2616 * 2617 * There are two type of re-ordering: compiler re-ordering and 2618 * CPU re-ordering under the ARMv8 architecture. 2619 * 1. we use volatile to deal with compiler re-ordering, so you 2620 * can see that rx_ring/rxdp defined with volatile. 2621 * 2. we commonly use memory barrier to deal with CPU 2622 * re-ordering, but the cost is high. 2623 * 2624 * In order to solve the high cost of using memory barrier, we 2625 * use the data dependency order under the ARMv8 architecture, 2626 * for example: 2627 * instr01: load A 2628 * instr02: load B <- A 2629 * the instr02 will always execute after instr01. 2630 * 2631 * To construct the data dependency ordering, we use the 2632 * following assignment: 2633 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) - 2634 * (1u<<HNS3_RXD_VLD_B)] 2635 * Using gcc compiler under the ARMv8 architecture, the related 2636 * assembly code example as follows: 2637 * note: (1u << HNS3_RXD_VLD_B) equal 0x10 2638 * instr01: ldr w26, [x22, #28] --read bd_base_info 2639 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10 2640 * instr03: sub w0, w0, #0x10 --calc (bd_base_info & 2641 * 0x10) - 0x10 2642 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr 2643 * instr05: ldp x2, x3, [x0] 2644 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B 2645 * instr07: ldp x4, x5, [x0, #16] 2646 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B 2647 * the instr05~08 depend on x0's value, x0 depent on w26's 2648 * value, the w26 is the bd_base_info, this form the data 2649 * dependency ordering. 2650 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) - 2651 * (1u<<HNS3_RXD_VLD_B) will always zero, so the 2652 * assignment is correct. 2653 * 2654 * So we use the data dependency ordering instead of memory 2655 * barrier to improve receive performance. 2656 */ 2657 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) - 2658 (1u << HNS3_RXD_VLD_B)]; 2659 RX_BD_LOG(&rxq->hns->hw, DEBUG, &rxd); 2660 2661 nmb = hns3_rx_alloc_buffer(rxq); 2662 if (unlikely(nmb == NULL)) { 2663 dev = &rte_eth_devices[rxq->port_id]; 2664 dev->data->rx_mbuf_alloc_failed++; 2665 break; 2666 } 2667 2668 nb_rx_bd++; 2669 rxe = &sw_ring[rx_id]; 2670 rx_id++; 2671 if (unlikely(rx_id == rxq->nb_rx_desc)) 2672 rx_id = 0; 2673 2674 rte_prefetch0(sw_ring[rx_id].mbuf); 2675 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) { 2676 rte_prefetch0(&rx_ring[rx_id]); 2677 rte_prefetch0(&sw_ring[rx_id]); 2678 } 2679 2680 rxm = rxe->mbuf; 2681 rxe->mbuf = nmb; 2682 2683 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) 2684 timestamp = rte_le_to_cpu_64(rxdp->timestamp); 2685 2686 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb)); 2687 rxdp->rx.bd_base_info = 0; 2688 rxdp->addr = dma_addr; 2689 2690 if (first_seg == NULL) { 2691 first_seg = rxm; 2692 first_seg->nb_segs = 1; 2693 } else { 2694 first_seg->nb_segs++; 2695 last_seg->next = rxm; 2696 } 2697 2698 rxm->data_off = RTE_PKTMBUF_HEADROOM; 2699 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size); 2700 2701 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { 2702 last_seg = rxm; 2703 rxm->next = NULL; 2704 continue; 2705 } 2706 2707 first_seg->ol_flags = 0; 2708 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) 2709 hns3_rx_ptp_timestamp_handle(rxq, first_seg, timestamp); 2710 2711 /* 2712 * The last buffer of the received packet. packet len from 2713 * buffer description may contains CRC len, packet len should 2714 * subtract it, same as data len. 2715 */ 2716 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len); 2717 2718 /* 2719 * This is the last buffer of the received packet. If the CRC 2720 * is not stripped by the hardware: 2721 * - Subtract the CRC length from the total packet length. 2722 * - If the last buffer only contains the whole CRC or a part 2723 * of it, free the mbuf associated to the last buffer. If part 2724 * of the CRC is also contained in the previous mbuf, subtract 2725 * the length of that CRC part from the data length of the 2726 * previous mbuf. 2727 */ 2728 rxm->next = NULL; 2729 if (unlikely(rxq->crc_len > 0)) { 2730 first_seg->pkt_len -= rxq->crc_len; 2731 recalculate_data_len(first_seg, last_seg, rxm, rxq, 2732 rxm->data_len); 2733 } 2734 2735 first_seg->port = rxq->port_id; 2736 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash); 2737 first_seg->ol_flags |= RTE_MBUF_F_RX_RSS_HASH; 2738 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) { 2739 first_seg->hash.fdir.hi = 2740 rte_le_to_cpu_16(rxd.rx.fd_id); 2741 first_seg->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID; 2742 } 2743 2744 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M, 2745 HNS3_RXD_GRO_SIZE_S); 2746 if (gro_size != 0) { 2747 first_seg->ol_flags |= RTE_MBUF_F_RX_LRO; 2748 first_seg->tso_segsz = gro_size; 2749 } 2750 2751 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info); 2752 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info); 2753 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info, 2754 l234_info); 2755 if (unlikely(ret)) 2756 goto pkt_err; 2757 2758 first_seg->packet_type = hns3_rx_calc_ptype(rxq, 2759 l234_info, ol_info); 2760 2761 if (first_seg->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) 2762 rxm->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP; 2763 2764 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd); 2765 2766 /* Increment bytes counter */ 2767 rxq->basic_stats.bytes += first_seg->pkt_len; 2768 2769 rx_pkts[nb_rx++] = first_seg; 2770 first_seg = NULL; 2771 continue; 2772 pkt_err: 2773 rte_pktmbuf_free(first_seg); 2774 first_seg = NULL; 2775 } 2776 2777 rxq->next_to_use = rx_id; 2778 rxq->pkt_first_seg = first_seg; 2779 rxq->pkt_last_seg = last_seg; 2780 2781 rxq->rx_free_hold += nb_rx_bd; 2782 if (rxq->rx_free_hold > rxq->rx_free_thresh) { 2783 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold); 2784 rxq->rx_free_hold = 0; 2785 } 2786 2787 return nb_rx; 2788 } 2789 2790 void __rte_weak 2791 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq) 2792 { 2793 } 2794 2795 int __rte_weak 2796 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev) 2797 { 2798 return -ENOTSUP; 2799 } 2800 2801 uint16_t __rte_weak 2802 hns3_recv_pkts_vec(__rte_unused void *rx_queue, 2803 __rte_unused struct rte_mbuf **rx_pkts, 2804 __rte_unused uint16_t nb_pkts) 2805 { 2806 return 0; 2807 } 2808 2809 uint16_t __rte_weak 2810 hns3_recv_pkts_vec_sve(__rte_unused void *rx_queue, 2811 __rte_unused struct rte_mbuf **rx_pkts, 2812 __rte_unused uint16_t nb_pkts) 2813 { 2814 return 0; 2815 } 2816 2817 int 2818 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2819 struct rte_eth_burst_mode *mode) 2820 { 2821 static const struct { 2822 eth_rx_burst_t pkt_burst; 2823 const char *info; 2824 } burst_infos[] = { 2825 { hns3_recv_pkts_simple, "Scalar Simple" }, 2826 { hns3_recv_scattered_pkts, "Scalar Scattered" }, 2827 { hns3_recv_pkts_vec, "Vector Neon" }, 2828 { hns3_recv_pkts_vec_sve, "Vector Sve" }, 2829 { rte_eth_pkt_burst_dummy, "Dummy" }, 2830 }; 2831 2832 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2833 int ret = -EINVAL; 2834 unsigned int i; 2835 2836 for (i = 0; i < RTE_DIM(burst_infos); i++) { 2837 if (pkt_burst == burst_infos[i].pkt_burst) { 2838 snprintf(mode->info, sizeof(mode->info), "%s", 2839 burst_infos[i].info); 2840 ret = 0; 2841 break; 2842 } 2843 } 2844 2845 return ret; 2846 } 2847 2848 static bool 2849 hns3_get_default_vec_support(void) 2850 { 2851 #if defined(RTE_ARCH_ARM64) 2852 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) 2853 return false; 2854 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) 2855 return true; 2856 #endif 2857 return false; 2858 } 2859 2860 static bool 2861 hns3_get_sve_support(void) 2862 { 2863 #if defined(RTE_HAS_SVE_ACLE) 2864 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) 2865 return false; 2866 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) 2867 return true; 2868 #endif 2869 return false; 2870 } 2871 2872 static eth_rx_burst_t 2873 hns3_get_rx_function(struct rte_eth_dev *dev) 2874 { 2875 struct hns3_adapter *hns = dev->data->dev_private; 2876 uint64_t offloads = dev->data->dev_conf.rxmode.offloads; 2877 bool vec_allowed, sve_allowed, simple_allowed; 2878 bool vec_support; 2879 2880 vec_support = hns3_rx_check_vec_support(dev) == 0; 2881 vec_allowed = vec_support && hns3_get_default_vec_support(); 2882 sve_allowed = vec_support && hns3_get_sve_support(); 2883 simple_allowed = !dev->data->scattered_rx && 2884 (offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) == 0; 2885 2886 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) 2887 return hns3_recv_pkts_vec; 2888 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) 2889 return hns3_recv_pkts_vec_sve; 2890 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) 2891 return hns3_recv_pkts_simple; 2892 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON) 2893 return hns3_recv_scattered_pkts; 2894 2895 if (vec_allowed) 2896 return hns3_recv_pkts_vec; 2897 if (simple_allowed) 2898 return hns3_recv_pkts_simple; 2899 2900 return hns3_recv_scattered_pkts; 2901 } 2902 2903 static int 2904 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf, 2905 uint16_t nb_desc, uint16_t *tx_rs_thresh, 2906 uint16_t *tx_free_thresh, uint16_t idx) 2907 { 2908 #define HNS3_TX_RS_FREE_THRESH_GAP 8 2909 uint16_t rs_thresh, free_thresh, fast_free_thresh; 2910 2911 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC || 2912 nb_desc % HNS3_ALIGN_RING_DESC) { 2913 hns3_err(hw, "number (%u) of tx descriptors is invalid", 2914 nb_desc); 2915 return -EINVAL; 2916 } 2917 2918 rs_thresh = (conf->tx_rs_thresh > 0) ? 2919 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH; 2920 free_thresh = (conf->tx_free_thresh > 0) ? 2921 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH; 2922 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh || 2923 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP || 2924 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) { 2925 hns3_err(hw, "tx_rs_thresh (%u) tx_free_thresh (%u) nb_desc " 2926 "(%u) of tx descriptors for port=%u queue=%u check " 2927 "fail!", 2928 rs_thresh, free_thresh, nb_desc, hw->data->port_id, 2929 idx); 2930 return -EINVAL; 2931 } 2932 2933 if (conf->tx_free_thresh == 0) { 2934 /* Fast free Tx memory buffer to improve cache hit rate */ 2935 fast_free_thresh = nb_desc - rs_thresh; 2936 if (fast_free_thresh >= 2937 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH) 2938 free_thresh = fast_free_thresh - 2939 HNS3_TX_FAST_FREE_AHEAD; 2940 } 2941 2942 *tx_rs_thresh = rs_thresh; 2943 *tx_free_thresh = free_thresh; 2944 return 0; 2945 } 2946 2947 static void * 2948 hns3_tx_push_get_queue_tail_reg(struct rte_eth_dev *dev, uint16_t queue_id) 2949 { 2950 #define HNS3_TX_PUSH_TQP_REGION_SIZE 0x10000 2951 #define HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET 64 2952 #define HNS3_TX_PUSH_PCI_BAR_INDEX 4 2953 2954 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 2955 uint8_t bar_id = HNS3_TX_PUSH_PCI_BAR_INDEX; 2956 2957 /* 2958 * If device support Tx push then its PCIe bar45 must exist, and DPDK 2959 * framework will mmap the bar45 default in PCI probe stage. 2960 * 2961 * In the bar45, the first half is for RoCE (RDMA over Converged 2962 * Ethernet), and the second half is for NIC, every TQP occupy 64KB. 2963 * 2964 * The quick doorbell located at 64B offset in the TQP region. 2965 */ 2966 return (char *)pci_dev->mem_resource[bar_id].addr + 2967 (pci_dev->mem_resource[bar_id].len >> 1) + 2968 HNS3_TX_PUSH_TQP_REGION_SIZE * queue_id + 2969 HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET; 2970 } 2971 2972 void 2973 hns3_tx_push_init(struct rte_eth_dev *dev) 2974 { 2975 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2976 volatile uint32_t *reg; 2977 uint32_t val; 2978 2979 if (!hns3_dev_get_support(hw, TX_PUSH)) 2980 return; 2981 2982 reg = (volatile uint32_t *)hns3_tx_push_get_queue_tail_reg(dev, 0); 2983 /* 2984 * Because the size of bar45 is about 8GB size, it may take a long time 2985 * to do the page fault in Tx process when work with vfio-pci, so use 2986 * one read operation to make kernel setup page table mapping for bar45 2987 * in the init stage. 2988 * Note: the bar45 is readable but the result is all 1. 2989 */ 2990 val = *reg; 2991 RTE_SET_USED(val); 2992 } 2993 2994 static void 2995 hns3_tx_push_queue_init(struct rte_eth_dev *dev, 2996 uint16_t queue_id, 2997 struct hns3_tx_queue *txq) 2998 { 2999 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3000 if (!hns3_dev_get_support(hw, TX_PUSH)) { 3001 txq->tx_push_enable = false; 3002 return; 3003 } 3004 3005 txq->io_tail_reg = (volatile void *)hns3_tx_push_get_queue_tail_reg(dev, 3006 queue_id); 3007 txq->tx_push_enable = true; 3008 } 3009 3010 int 3011 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, 3012 unsigned int socket_id, const struct rte_eth_txconf *conf) 3013 { 3014 struct hns3_adapter *hns = dev->data->dev_private; 3015 uint16_t tx_rs_thresh, tx_free_thresh; 3016 struct hns3_hw *hw = &hns->hw; 3017 struct hns3_queue_info q_info; 3018 struct hns3_tx_queue *txq; 3019 int tx_entry_len; 3020 int ret; 3021 3022 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc, 3023 &tx_rs_thresh, &tx_free_thresh, idx); 3024 if (ret) 3025 return ret; 3026 3027 if (dev->data->tx_queues[idx] != NULL) { 3028 hns3_tx_queue_release(dev->data->tx_queues[idx]); 3029 dev->data->tx_queues[idx] = NULL; 3030 } 3031 3032 q_info.idx = idx; 3033 q_info.socket_id = socket_id; 3034 q_info.nb_desc = nb_desc; 3035 q_info.type = "hns3 TX queue"; 3036 q_info.ring_name = "tx_ring"; 3037 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info); 3038 if (txq == NULL) { 3039 hns3_err(hw, 3040 "Failed to alloc mem and reserve DMA mem for tx ring!"); 3041 return -ENOMEM; 3042 } 3043 3044 txq->tx_deferred_start = conf->tx_deferred_start; 3045 if (txq->tx_deferred_start && !hns3_dev_get_support(hw, INDEP_TXRX)) { 3046 hns3_warn(hw, "deferred start is not supported."); 3047 txq->tx_deferred_start = false; 3048 } 3049 3050 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc; 3051 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len, 3052 RTE_CACHE_LINE_SIZE, socket_id); 3053 if (txq->sw_ring == NULL) { 3054 hns3_err(hw, "Failed to allocate memory for tx sw ring!"); 3055 hns3_tx_queue_release(txq); 3056 return -ENOMEM; 3057 } 3058 3059 txq->hns = hns; 3060 txq->next_to_use = 0; 3061 txq->next_to_clean = 0; 3062 txq->tx_bd_ready = txq->nb_tx_desc - 1; 3063 txq->tx_free_thresh = tx_free_thresh; 3064 txq->tx_rs_thresh = tx_rs_thresh; 3065 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array", 3066 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh, 3067 RTE_CACHE_LINE_SIZE, socket_id); 3068 if (!txq->free) { 3069 hns3_err(hw, "failed to allocate tx mbuf free array!"); 3070 hns3_tx_queue_release(txq); 3071 return -ENOMEM; 3072 } 3073 3074 txq->port_id = dev->data->port_id; 3075 /* 3076 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE, 3077 * the pvid_sw_shift_en in the queue struct should not be changed, 3078 * because PVID-related operations do not need to be processed by PMD. 3079 * For hns3 VF device, whether it needs to process PVID depends 3080 * on the configuration of PF kernel mode netdev driver. And the 3081 * related PF configuration is delivered through the mailbox and finally 3082 * reflected in port_base_vlan_cfg. 3083 */ 3084 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 3085 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state == 3086 HNS3_PORT_BASE_VLAN_ENABLE; 3087 else 3088 txq->pvid_sw_shift_en = false; 3089 3090 if (hns3_dev_get_support(hw, SIMPLE_BD)) 3091 txq->simple_bd_enable = true; 3092 3093 txq->max_non_tso_bd_num = hw->max_non_tso_bd_num; 3094 txq->configured = true; 3095 txq->io_base = (void *)((char *)hw->io_base + 3096 hns3_get_tqp_reg_offset(idx)); 3097 txq->io_tail_reg = (volatile void *)((char *)txq->io_base + 3098 HNS3_RING_TX_TAIL_REG); 3099 txq->min_tx_pkt_len = hw->min_tx_pkt_len; 3100 txq->tso_mode = hw->tso_mode; 3101 txq->udp_cksum_mode = hw->udp_cksum_mode; 3102 txq->mbuf_fast_free_en = !!(dev->data->dev_conf.txmode.offloads & 3103 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE); 3104 memset(&txq->basic_stats, 0, sizeof(struct hns3_tx_basic_stats)); 3105 memset(&txq->dfx_stats, 0, sizeof(struct hns3_tx_dfx_stats)); 3106 3107 /* 3108 * Call hns3_tx_push_queue_init after assigned io_tail_reg field because 3109 * it may overwrite the io_tail_reg field. 3110 */ 3111 hns3_tx_push_queue_init(dev, idx, txq); 3112 3113 rte_spinlock_lock(&hw->lock); 3114 dev->data->tx_queues[idx] = txq; 3115 rte_spinlock_unlock(&hw->lock); 3116 3117 return 0; 3118 } 3119 3120 static void 3121 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq) 3122 { 3123 uint16_t tx_next_clean = txq->next_to_clean; 3124 uint16_t tx_next_use = txq->next_to_use; 3125 uint16_t tx_bd_ready = txq->tx_bd_ready; 3126 uint16_t tx_bd_max = txq->nb_tx_desc; 3127 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean]; 3128 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean]; 3129 struct rte_mbuf *mbuf; 3130 3131 while ((!(desc->tx.tp_fe_sc_vld_ra_ri & 3132 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))) && 3133 tx_next_use != tx_next_clean) { 3134 mbuf = tx_bak_pkt->mbuf; 3135 if (mbuf) { 3136 rte_pktmbuf_free_seg(mbuf); 3137 tx_bak_pkt->mbuf = NULL; 3138 } 3139 3140 desc++; 3141 tx_bak_pkt++; 3142 tx_next_clean++; 3143 tx_bd_ready++; 3144 3145 if (tx_next_clean >= tx_bd_max) { 3146 tx_next_clean = 0; 3147 desc = txq->tx_ring; 3148 tx_bak_pkt = txq->sw_ring; 3149 } 3150 } 3151 3152 txq->next_to_clean = tx_next_clean; 3153 txq->tx_bd_ready = tx_bd_ready; 3154 } 3155 3156 int 3157 hns3_config_gro(struct hns3_hw *hw, bool en) 3158 { 3159 struct hns3_cfg_gro_status_cmd *req; 3160 struct hns3_cmd_desc desc; 3161 int ret; 3162 3163 if (!hns3_dev_get_support(hw, GRO)) 3164 return 0; 3165 3166 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false); 3167 req = (struct hns3_cfg_gro_status_cmd *)desc.data; 3168 3169 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0); 3170 3171 ret = hns3_cmd_send(hw, &desc, 1); 3172 if (ret) 3173 hns3_err(hw, "%s hardware GRO failed, ret = %d", 3174 en ? "enable" : "disable", ret); 3175 3176 return ret; 3177 } 3178 3179 int 3180 hns3_restore_gro_conf(struct hns3_hw *hw) 3181 { 3182 uint64_t offloads; 3183 bool gro_en; 3184 int ret; 3185 3186 offloads = hw->data->dev_conf.rxmode.offloads; 3187 gro_en = offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false; 3188 ret = hns3_config_gro(hw, gro_en); 3189 if (ret) 3190 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d", 3191 gro_en ? "enabled" : "disabled", ret); 3192 3193 return ret; 3194 } 3195 3196 static inline bool 3197 hns3_pkt_is_tso(struct rte_mbuf *m) 3198 { 3199 return (m->tso_segsz != 0 && m->ol_flags & RTE_MBUF_F_TX_TCP_SEG); 3200 } 3201 3202 static void 3203 hns3_set_tso(struct hns3_desc *desc, uint32_t paylen, struct rte_mbuf *rxm) 3204 { 3205 if (!hns3_pkt_is_tso(rxm)) 3206 return; 3207 3208 if (paylen <= rxm->tso_segsz) 3209 return; 3210 3211 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B)); 3212 desc->tx.ckst_mss |= rte_cpu_to_le_16(rxm->tso_segsz); 3213 } 3214 3215 static inline void 3216 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm) 3217 { 3218 desc->addr = rte_mbuf_data_iova(rxm); 3219 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm)); 3220 desc->tx.tp_fe_sc_vld_ra_ri |= rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)); 3221 } 3222 3223 static void 3224 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc, 3225 struct rte_mbuf *rxm) 3226 { 3227 uint64_t ol_flags = rxm->ol_flags; 3228 uint32_t hdr_len; 3229 uint32_t paylen; 3230 3231 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len; 3232 hdr_len += (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ? 3233 rxm->outer_l2_len + rxm->outer_l3_len : 0; 3234 paylen = rxm->pkt_len - hdr_len; 3235 desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen); 3236 hns3_set_tso(desc, paylen, rxm); 3237 3238 /* 3239 * Currently, hardware doesn't support more than two layers VLAN offload 3240 * in Tx direction based on hns3 network engine. So when the number of 3241 * VLANs in the packets represented by rxm plus the number of VLAN 3242 * offload by hardware such as PVID etc, exceeds two, the packets will 3243 * be discarded or the original VLAN of the packets will be overwritten 3244 * by hardware. When the PF PVID is enabled by calling the API function 3245 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3 3246 * PF kernel ether driver, the outer VLAN tag will always be the PVID. 3247 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should 3248 * be added to the position close to the IP header when PVID is enabled. 3249 */ 3250 if (!txq->pvid_sw_shift_en && 3251 ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) { 3252 desc->tx.ol_type_vlan_len_msec |= 3253 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B)); 3254 if (ol_flags & RTE_MBUF_F_TX_QINQ) 3255 desc->tx.outer_vlan_tag = 3256 rte_cpu_to_le_16(rxm->vlan_tci_outer); 3257 else 3258 desc->tx.outer_vlan_tag = 3259 rte_cpu_to_le_16(rxm->vlan_tci); 3260 } 3261 3262 if (ol_flags & RTE_MBUF_F_TX_QINQ || 3263 ((ol_flags & RTE_MBUF_F_TX_VLAN) && txq->pvid_sw_shift_en)) { 3264 desc->tx.type_cs_vlan_tso_len |= 3265 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B)); 3266 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci); 3267 } 3268 3269 if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST) 3270 desc->tx.tp_fe_sc_vld_ra_ri |= 3271 rte_cpu_to_le_16(BIT(HNS3_TXD_TSYN_B)); 3272 } 3273 3274 static inline int 3275 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf, 3276 struct rte_mbuf **alloc_mbuf) 3277 { 3278 #define MAX_NON_TSO_BD_PER_PKT 18 3279 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT]; 3280 uint16_t i; 3281 3282 /* Allocate enough mbufs */ 3283 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf)) 3284 return -ENOMEM; 3285 3286 for (i = 0; i < nb_new_buf - 1; i++) 3287 pkt_segs[i]->next = pkt_segs[i + 1]; 3288 3289 pkt_segs[nb_new_buf - 1]->next = NULL; 3290 pkt_segs[0]->nb_segs = nb_new_buf; 3291 *alloc_mbuf = pkt_segs[0]; 3292 3293 return 0; 3294 } 3295 3296 static inline void 3297 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt) 3298 { 3299 new_pkt->ol_flags = old_pkt->ol_flags; 3300 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt); 3301 new_pkt->outer_l2_len = old_pkt->outer_l2_len; 3302 new_pkt->outer_l3_len = old_pkt->outer_l3_len; 3303 new_pkt->l2_len = old_pkt->l2_len; 3304 new_pkt->l3_len = old_pkt->l3_len; 3305 new_pkt->l4_len = old_pkt->l4_len; 3306 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer; 3307 new_pkt->vlan_tci = old_pkt->vlan_tci; 3308 } 3309 3310 static int 3311 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt, 3312 uint8_t max_non_tso_bd_num) 3313 { 3314 struct rte_mempool *mb_pool; 3315 struct rte_mbuf *new_mbuf; 3316 struct rte_mbuf *temp_new; 3317 struct rte_mbuf *temp; 3318 uint16_t last_buf_len; 3319 uint16_t nb_new_buf; 3320 uint16_t buf_size; 3321 uint16_t buf_len; 3322 uint16_t len_s; 3323 uint16_t len_d; 3324 uint16_t len; 3325 int ret; 3326 char *s; 3327 char *d; 3328 3329 mb_pool = tx_pkt->pool; 3330 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM; 3331 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1; 3332 if (nb_new_buf > max_non_tso_bd_num) 3333 return -EINVAL; 3334 3335 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size; 3336 if (last_buf_len == 0) 3337 last_buf_len = buf_size; 3338 3339 /* Allocate enough mbufs */ 3340 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf); 3341 if (ret) 3342 return ret; 3343 3344 /* Copy the original packet content to the new mbufs */ 3345 temp = tx_pkt; 3346 s = rte_pktmbuf_mtod(temp, char *); 3347 len_s = rte_pktmbuf_data_len(temp); 3348 temp_new = new_mbuf; 3349 while (temp != NULL && temp_new != NULL) { 3350 d = rte_pktmbuf_mtod(temp_new, char *); 3351 buf_len = temp_new->next == NULL ? last_buf_len : buf_size; 3352 len_d = buf_len; 3353 3354 while (len_d) { 3355 len = RTE_MIN(len_s, len_d); 3356 memcpy(d, s, len); 3357 s = s + len; 3358 d = d + len; 3359 len_d = len_d - len; 3360 len_s = len_s - len; 3361 3362 if (len_s == 0) { 3363 temp = temp->next; 3364 if (temp == NULL) 3365 break; 3366 s = rte_pktmbuf_mtod(temp, char *); 3367 len_s = rte_pktmbuf_data_len(temp); 3368 } 3369 } 3370 3371 temp_new->data_len = buf_len; 3372 temp_new = temp_new->next; 3373 } 3374 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt); 3375 3376 /* free original mbufs */ 3377 rte_pktmbuf_free(tx_pkt); 3378 3379 *new_pkt = new_mbuf; 3380 3381 return 0; 3382 } 3383 3384 static void 3385 hns3_parse_outer_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec) 3386 { 3387 uint32_t tmp = *ol_type_vlan_len_msec; 3388 uint64_t ol_flags = m->ol_flags; 3389 3390 /* (outer) IP header type */ 3391 if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) { 3392 if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) 3393 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, 3394 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM); 3395 else 3396 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, 3397 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_NO_CSUM); 3398 } else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6) { 3399 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S, 3400 HNS3_OL3T_IPV6); 3401 } 3402 /* OL3 header size, defined in 4 bytes */ 3403 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S, 3404 m->outer_l3_len >> HNS3_L3_LEN_UNIT); 3405 *ol_type_vlan_len_msec = tmp; 3406 } 3407 3408 static int 3409 hns3_parse_inner_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec, 3410 uint32_t *type_cs_vlan_tso_len) 3411 { 3412 #define HNS3_NVGRE_HLEN 8 3413 uint32_t tmp_outer = *ol_type_vlan_len_msec; 3414 uint32_t tmp_inner = *type_cs_vlan_tso_len; 3415 uint64_t ol_flags = m->ol_flags; 3416 uint16_t inner_l2_len; 3417 3418 switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) { 3419 case RTE_MBUF_F_TX_TUNNEL_VXLAN_GPE: 3420 case RTE_MBUF_F_TX_TUNNEL_GENEVE: 3421 case RTE_MBUF_F_TX_TUNNEL_VXLAN: 3422 /* MAC in UDP tunnelling packet, include VxLAN and GENEVE */ 3423 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M, 3424 HNS3_TXD_TUNTYPE_S, HNS3_TUN_MAC_IN_UDP); 3425 /* 3426 * The inner l2 length of mbuf is the sum of outer l4 length, 3427 * tunneling header length and inner l2 length for a tunnel 3428 * packet. But in hns3 tx descriptor, the tunneling header 3429 * length is contained in the field of outer L4 length. 3430 * Therefore, driver need to calculate the outer L4 length and 3431 * inner L2 length. 3432 */ 3433 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, 3434 HNS3_TXD_L4LEN_S, 3435 (uint8_t)RTE_ETHER_VXLAN_HLEN >> 3436 HNS3_L4_LEN_UNIT); 3437 3438 inner_l2_len = m->l2_len - RTE_ETHER_VXLAN_HLEN; 3439 break; 3440 case RTE_MBUF_F_TX_TUNNEL_GRE: 3441 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M, 3442 HNS3_TXD_TUNTYPE_S, HNS3_TUN_NVGRE); 3443 /* 3444 * For NVGRE tunnel packet, the outer L4 is empty. So only 3445 * fill the NVGRE header length to the outer L4 field. 3446 */ 3447 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, 3448 HNS3_TXD_L4LEN_S, 3449 (uint8_t)HNS3_NVGRE_HLEN >> HNS3_L4_LEN_UNIT); 3450 3451 inner_l2_len = m->l2_len - HNS3_NVGRE_HLEN; 3452 break; 3453 default: 3454 /* For non UDP / GRE tunneling, drop the tunnel packet */ 3455 return -EINVAL; 3456 } 3457 3458 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S, 3459 inner_l2_len >> HNS3_L2_LEN_UNIT); 3460 /* OL2 header size, defined in 2 bytes */ 3461 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S, 3462 m->outer_l2_len >> HNS3_L2_LEN_UNIT); 3463 3464 *type_cs_vlan_tso_len = tmp_inner; 3465 *ol_type_vlan_len_msec = tmp_outer; 3466 3467 return 0; 3468 } 3469 3470 static int 3471 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, 3472 uint16_t tx_desc_id) 3473 { 3474 struct hns3_desc *tx_ring = txq->tx_ring; 3475 struct hns3_desc *desc = &tx_ring[tx_desc_id]; 3476 uint64_t ol_flags = m->ol_flags; 3477 uint32_t tmp_outer = 0; 3478 uint32_t tmp_inner = 0; 3479 uint32_t tmp_ol4cs; 3480 int ret; 3481 3482 /* 3483 * The tunnel header is contained in the inner L2 header field of the 3484 * mbuf, but for hns3 descriptor, it is contained in the outer L4. So, 3485 * there is a need that switching between them. To avoid multiple 3486 * calculations, the length of the L2 header include the outer and 3487 * inner, will be filled during the parsing of tunnel packets. 3488 */ 3489 if (!(ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)) { 3490 /* 3491 * For non tunnel type the tunnel type id is 0, so no need to 3492 * assign a value to it. Only the inner(normal) L2 header length 3493 * is assigned. 3494 */ 3495 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, 3496 HNS3_TXD_L2LEN_S, m->l2_len >> HNS3_L2_LEN_UNIT); 3497 } else { 3498 /* 3499 * If outer csum is not offload, the outer length may be filled 3500 * with 0. And the length of the outer header is added to the 3501 * inner l2_len. It would lead a cksum error. So driver has to 3502 * calculate the header length. 3503 */ 3504 if (unlikely(!(ol_flags & 3505 (RTE_MBUF_F_TX_OUTER_IP_CKSUM | RTE_MBUF_F_TX_OUTER_UDP_CKSUM)) && 3506 m->outer_l2_len == 0)) { 3507 struct rte_net_hdr_lens hdr_len; 3508 (void)rte_net_get_ptype(m, &hdr_len, 3509 RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK); 3510 m->outer_l3_len = hdr_len.l3_len; 3511 m->outer_l2_len = hdr_len.l2_len; 3512 m->l2_len = m->l2_len - hdr_len.l2_len - hdr_len.l3_len; 3513 } 3514 hns3_parse_outer_params(m, &tmp_outer); 3515 ret = hns3_parse_inner_params(m, &tmp_outer, &tmp_inner); 3516 if (ret) 3517 return -EINVAL; 3518 } 3519 3520 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer); 3521 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner); 3522 tmp_ol4cs = ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM ? 3523 BIT(HNS3_TXD_OL4CS_B) : 0; 3524 desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs); 3525 3526 return 0; 3527 } 3528 3529 static void 3530 hns3_parse_l3_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len) 3531 { 3532 uint64_t ol_flags = m->ol_flags; 3533 uint32_t l3_type; 3534 uint32_t tmp; 3535 3536 tmp = *type_cs_vlan_tso_len; 3537 if (ol_flags & RTE_MBUF_F_TX_IPV4) 3538 l3_type = HNS3_L3T_IPV4; 3539 else if (ol_flags & RTE_MBUF_F_TX_IPV6) 3540 l3_type = HNS3_L3T_IPV6; 3541 else 3542 l3_type = HNS3_L3T_NONE; 3543 3544 /* inner(/normal) L3 header size, defined in 4 bytes */ 3545 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S, 3546 m->l3_len >> HNS3_L3_LEN_UNIT); 3547 3548 tmp |= hns3_gen_field_val(HNS3_TXD_L3T_M, HNS3_TXD_L3T_S, l3_type); 3549 3550 /* Enable L3 checksum offloads */ 3551 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) 3552 tmp |= BIT(HNS3_TXD_L3CS_B); 3553 *type_cs_vlan_tso_len = tmp; 3554 } 3555 3556 static void 3557 hns3_parse_l4_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len) 3558 { 3559 uint64_t ol_flags = m->ol_flags; 3560 uint32_t tmp; 3561 /* Enable L4 checksum offloads */ 3562 switch (ol_flags & (RTE_MBUF_F_TX_L4_MASK | RTE_MBUF_F_TX_TCP_SEG)) { 3563 case RTE_MBUF_F_TX_TCP_CKSUM | RTE_MBUF_F_TX_TCP_SEG: 3564 case RTE_MBUF_F_TX_TCP_CKSUM: 3565 case RTE_MBUF_F_TX_TCP_SEG: 3566 tmp = *type_cs_vlan_tso_len; 3567 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, 3568 HNS3_L4T_TCP); 3569 break; 3570 case RTE_MBUF_F_TX_UDP_CKSUM: 3571 tmp = *type_cs_vlan_tso_len; 3572 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, 3573 HNS3_L4T_UDP); 3574 break; 3575 case RTE_MBUF_F_TX_SCTP_CKSUM: 3576 tmp = *type_cs_vlan_tso_len; 3577 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S, 3578 HNS3_L4T_SCTP); 3579 break; 3580 default: 3581 return; 3582 } 3583 tmp |= BIT(HNS3_TXD_L4CS_B); 3584 tmp |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 3585 m->l4_len >> HNS3_L4_LEN_UNIT); 3586 *type_cs_vlan_tso_len = tmp; 3587 } 3588 3589 static void 3590 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, struct rte_mbuf *m, 3591 uint16_t tx_desc_id) 3592 { 3593 struct hns3_desc *tx_ring = txq->tx_ring; 3594 struct hns3_desc *desc = &tx_ring[tx_desc_id]; 3595 uint32_t value = 0; 3596 3597 hns3_parse_l3_cksum_params(m, &value); 3598 hns3_parse_l4_cksum_params(m, &value); 3599 3600 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value); 3601 } 3602 3603 static bool 3604 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num, 3605 uint32_t max_non_tso_bd_num) 3606 { 3607 struct rte_mbuf *m_first = tx_pkts; 3608 struct rte_mbuf *m_last = tx_pkts; 3609 uint32_t tot_len = 0; 3610 uint32_t hdr_len; 3611 uint32_t i; 3612 3613 /* 3614 * Hardware requires that the sum of the data length of every 8 3615 * consecutive buffers is greater than MSS in hns3 network engine. 3616 * We simplify it by ensuring pkt_headlen + the first 8 consecutive 3617 * frags greater than gso header len + mss, and the remaining 7 3618 * consecutive frags greater than MSS except the last 7 frags. 3619 */ 3620 if (bd_num <= max_non_tso_bd_num) 3621 return false; 3622 3623 for (i = 0; m_last && i < max_non_tso_bd_num - 1; 3624 i++, m_last = m_last->next) 3625 tot_len += m_last->data_len; 3626 3627 if (!m_last) 3628 return true; 3629 3630 /* ensure the first 8 frags is greater than mss + header */ 3631 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len; 3632 hdr_len += (tx_pkts->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ? 3633 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0; 3634 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len) 3635 return true; 3636 3637 /* 3638 * ensure the sum of the data length of every 7 consecutive buffer 3639 * is greater than mss except the last one. 3640 */ 3641 for (i = 0; m_last && i < bd_num - max_non_tso_bd_num; i++) { 3642 tot_len -= m_first->data_len; 3643 tot_len += m_last->data_len; 3644 3645 if (tot_len < tx_pkts->tso_segsz) 3646 return true; 3647 3648 m_first = m_first->next; 3649 m_last = m_last->next; 3650 } 3651 3652 return false; 3653 } 3654 3655 static int 3656 hns3_check_tso_pkt_valid(struct rte_mbuf *m) 3657 { 3658 uint32_t tmp_data_len_sum = 0; 3659 uint16_t nb_buf = m->nb_segs; 3660 uint32_t paylen, hdr_len; 3661 struct rte_mbuf *m_seg; 3662 int i; 3663 3664 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT) 3665 return -EINVAL; 3666 3667 hdr_len = m->l2_len + m->l3_len + m->l4_len; 3668 hdr_len += (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ? 3669 m->outer_l2_len + m->outer_l3_len : 0; 3670 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE) 3671 return -EINVAL; 3672 3673 paylen = m->pkt_len - hdr_len; 3674 if (paylen > HNS3_MAX_BD_PAYLEN) 3675 return -EINVAL; 3676 3677 /* 3678 * The TSO header (include outer and inner L2, L3 and L4 header) 3679 * should be provided by three descriptors in maximum in hns3 network 3680 * engine. 3681 */ 3682 m_seg = m; 3683 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf; 3684 i++, m_seg = m_seg->next) { 3685 tmp_data_len_sum += m_seg->data_len; 3686 } 3687 3688 if (hdr_len > tmp_data_len_sum) 3689 return -EINVAL; 3690 3691 return 0; 3692 } 3693 3694 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 3695 static inline int 3696 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m) 3697 { 3698 struct rte_ether_hdr *eh; 3699 struct rte_vlan_hdr *vh; 3700 3701 if (!txq->pvid_sw_shift_en) 3702 return 0; 3703 3704 /* 3705 * Due to hardware limitations, we only support two-layer VLAN hardware 3706 * offload in Tx direction based on hns3 network engine, so when PVID is 3707 * enabled, QinQ insert is no longer supported. 3708 * And when PVID is enabled, in the following two cases: 3709 * i) packets with more than two VLAN tags. 3710 * ii) packets with one VLAN tag while the hardware VLAN insert is 3711 * enabled. 3712 * The packets will be regarded as abnormal packets and discarded by 3713 * hardware in Tx direction. For debugging purposes, a validation check 3714 * for these types of packets is added to the '.tx_pkt_prepare' ops 3715 * implementation function named hns3_prep_pkts to inform users that 3716 * these packets will be discarded. 3717 */ 3718 if (m->ol_flags & RTE_MBUF_F_TX_QINQ) 3719 return -EINVAL; 3720 3721 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *); 3722 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) { 3723 if (m->ol_flags & RTE_MBUF_F_TX_VLAN) 3724 return -EINVAL; 3725 3726 /* Ensure the incoming packet is not a QinQ packet */ 3727 vh = (struct rte_vlan_hdr *)(eh + 1); 3728 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) 3729 return -EINVAL; 3730 } 3731 3732 return 0; 3733 } 3734 #endif 3735 3736 static uint16_t 3737 hns3_udp_cksum_help(struct rte_mbuf *m) 3738 { 3739 uint64_t ol_flags = m->ol_flags; 3740 uint16_t cksum = 0; 3741 uint32_t l4_len; 3742 3743 if (ol_flags & RTE_MBUF_F_TX_IPV4) { 3744 struct rte_ipv4_hdr *ipv4_hdr = rte_pktmbuf_mtod_offset(m, 3745 struct rte_ipv4_hdr *, m->l2_len); 3746 l4_len = rte_be_to_cpu_16(ipv4_hdr->total_length) - m->l3_len; 3747 } else { 3748 struct rte_ipv6_hdr *ipv6_hdr = rte_pktmbuf_mtod_offset(m, 3749 struct rte_ipv6_hdr *, m->l2_len); 3750 l4_len = rte_be_to_cpu_16(ipv6_hdr->payload_len); 3751 } 3752 3753 rte_raw_cksum_mbuf(m, m->l2_len + m->l3_len, l4_len, &cksum); 3754 3755 cksum = ~cksum; 3756 /* 3757 * RFC 768:If the computed checksum is zero for UDP, it is transmitted 3758 * as all ones 3759 */ 3760 if (cksum == 0) 3761 cksum = 0xffff; 3762 3763 return (uint16_t)cksum; 3764 } 3765 3766 static bool 3767 hns3_validate_tunnel_cksum(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m) 3768 { 3769 uint64_t ol_flags = m->ol_flags; 3770 struct rte_udp_hdr *udp_hdr; 3771 uint16_t dst_port; 3772 3773 if (tx_queue->udp_cksum_mode == HNS3_SPECIAL_PORT_HW_CKSUM_MODE || 3774 ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK || 3775 (ol_flags & RTE_MBUF_F_TX_L4_MASK) != RTE_MBUF_F_TX_UDP_CKSUM) 3776 return true; 3777 /* 3778 * A UDP packet with the same dst_port as VXLAN\VXLAN_GPE\GENEVE will 3779 * be recognized as a tunnel packet in HW. In this case, if UDP CKSUM 3780 * offload is set and the tunnel mask has not been set, the CKSUM will 3781 * be wrong since the header length is wrong and driver should complete 3782 * the CKSUM to avoid CKSUM error. 3783 */ 3784 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, 3785 m->l2_len + m->l3_len); 3786 dst_port = rte_be_to_cpu_16(udp_hdr->dst_port); 3787 switch (dst_port) { 3788 case RTE_VXLAN_DEFAULT_PORT: 3789 case RTE_VXLAN_GPE_DEFAULT_PORT: 3790 case RTE_GENEVE_DEFAULT_PORT: 3791 udp_hdr->dgram_cksum = hns3_udp_cksum_help(m); 3792 m->ol_flags = ol_flags & ~RTE_MBUF_F_TX_L4_MASK; 3793 return false; 3794 default: 3795 return true; 3796 } 3797 } 3798 3799 static int 3800 hns3_prep_pkt_proc(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m) 3801 { 3802 int ret; 3803 3804 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 3805 ret = rte_validate_tx_offload(m); 3806 if (ret != 0) { 3807 rte_errno = -ret; 3808 return ret; 3809 } 3810 3811 ret = hns3_vld_vlan_chk(tx_queue, m); 3812 if (ret != 0) { 3813 rte_errno = EINVAL; 3814 return ret; 3815 } 3816 #endif 3817 if (hns3_pkt_is_tso(m)) { 3818 if (hns3_pkt_need_linearized(m, m->nb_segs, 3819 tx_queue->max_non_tso_bd_num) || 3820 hns3_check_tso_pkt_valid(m)) { 3821 rte_errno = EINVAL; 3822 return -EINVAL; 3823 } 3824 3825 if (tx_queue->tso_mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) { 3826 /* 3827 * (tso mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) means 3828 * hardware support recalculate the TCP pseudo header 3829 * checksum of packets that need TSO, so network driver 3830 * software not need to recalculate it. 3831 */ 3832 return 0; 3833 } 3834 } 3835 3836 ret = rte_net_intel_cksum_prepare(m); 3837 if (ret != 0) { 3838 rte_errno = -ret; 3839 return ret; 3840 } 3841 3842 if (!hns3_validate_tunnel_cksum(tx_queue, m)) 3843 return 0; 3844 3845 return 0; 3846 } 3847 3848 uint16_t 3849 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, 3850 uint16_t nb_pkts) 3851 { 3852 struct rte_mbuf *m; 3853 uint16_t i; 3854 3855 for (i = 0; i < nb_pkts; i++) { 3856 m = tx_pkts[i]; 3857 if (hns3_prep_pkt_proc(tx_queue, m)) 3858 return i; 3859 } 3860 3861 return i; 3862 } 3863 3864 static inline int 3865 hns3_handle_simple_bd(struct hns3_tx_queue *txq, struct hns3_desc *desc, 3866 struct rte_mbuf *m) 3867 { 3868 #define HNS3_TCP_CSUM_OFFSET 16 3869 #define HNS3_UDP_CSUM_OFFSET 6 3870 3871 /* 3872 * In HIP09, NIC HW support Tx simple BD mode that the HW will 3873 * calculate the checksum from the start position of checksum and fill 3874 * the checksum result to the offset position without packet type and 3875 * header length of L3/L4. 3876 * For non-tunneling packet: 3877 * - Tx simple BD support for TCP and UDP checksum. 3878 * For tunneling packet: 3879 * - Tx simple BD support for inner L4 checksum(except sctp checksum). 3880 * - Tx simple BD not support the outer checksum and the inner L3 3881 * checksum. 3882 * - Besides, Tx simple BD is not support for TSO. 3883 */ 3884 if (txq->simple_bd_enable && !(m->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) && 3885 !(m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) && 3886 !(m->ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) && 3887 ((m->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM || 3888 (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_UDP_CKSUM)) { 3889 /* set checksum start and offset, defined in 2 Bytes */ 3890 hns3_set_field(desc->tx.type_cs_vlan_tso_len, 3891 HNS3_TXD_L4_START_M, HNS3_TXD_L4_START_S, 3892 (m->l2_len + m->l3_len) >> HNS3_SIMPLE_BD_UNIT); 3893 hns3_set_field(desc->tx.ol_type_vlan_len_msec, 3894 HNS3_TXD_L4_CKS_OFFSET_M, HNS3_TXD_L4_CKS_OFFSET_S, 3895 (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) == 3896 RTE_MBUF_F_TX_TCP_CKSUM ? 3897 HNS3_TCP_CSUM_OFFSET >> HNS3_SIMPLE_BD_UNIT : 3898 HNS3_UDP_CSUM_OFFSET >> HNS3_SIMPLE_BD_UNIT); 3899 3900 hns3_set_bit(desc->tx.ckst_mss, HNS3_TXD_CKST_B, 1); 3901 3902 return 0; 3903 } 3904 3905 return -ENOTSUP; 3906 } 3907 3908 static int 3909 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id, 3910 struct rte_mbuf *m) 3911 { 3912 struct hns3_desc *tx_ring = txq->tx_ring; 3913 struct hns3_desc *desc = &tx_ring[tx_desc_id]; 3914 3915 /* Enable checksum offloading */ 3916 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) { 3917 if (hns3_handle_simple_bd(txq, desc, m) == 0) 3918 return 0; 3919 /* Fill in tunneling parameters if necessary */ 3920 if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) { 3921 txq->dfx_stats.unsupported_tunnel_pkt_cnt++; 3922 return -EINVAL; 3923 } 3924 3925 hns3_txd_enable_checksum(txq, m, tx_desc_id); 3926 } else { 3927 /* clear the control bit */ 3928 desc->tx.type_cs_vlan_tso_len = 0; 3929 desc->tx.ol_type_vlan_len_msec = 0; 3930 } 3931 3932 return 0; 3933 } 3934 3935 static int 3936 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg, 3937 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq) 3938 { 3939 uint8_t max_non_tso_bd_num; 3940 struct rte_mbuf *new_pkt; 3941 int ret; 3942 3943 if (hns3_pkt_is_tso(*m_seg)) 3944 return 0; 3945 3946 /* 3947 * If packet length is greater than HNS3_MAX_FRAME_LEN 3948 * driver support, the packet will be ignored. 3949 */ 3950 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) { 3951 txq->dfx_stats.over_length_pkt_cnt++; 3952 return -EINVAL; 3953 } 3954 3955 max_non_tso_bd_num = txq->max_non_tso_bd_num; 3956 if (unlikely(nb_buf > max_non_tso_bd_num)) { 3957 txq->dfx_stats.exceed_limit_bd_pkt_cnt++; 3958 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt, 3959 max_non_tso_bd_num); 3960 if (ret) { 3961 txq->dfx_stats.exceed_limit_bd_reassem_fail++; 3962 return ret; 3963 } 3964 *m_seg = new_pkt; 3965 } 3966 3967 return 0; 3968 } 3969 3970 static inline void 3971 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq) 3972 { 3973 struct hns3_entry *tx_entry; 3974 struct hns3_desc *desc; 3975 uint16_t tx_next_clean; 3976 uint16_t i; 3977 3978 while (1) { 3979 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh) 3980 break; 3981 3982 /* 3983 * All mbufs can be released only when the VLD bits of all 3984 * descriptors in a batch are cleared. 3985 */ 3986 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) % 3987 txq->nb_tx_desc; 3988 desc = &txq->tx_ring[tx_next_clean]; 3989 for (i = 0; i < txq->tx_rs_thresh; i++) { 3990 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) & 3991 BIT(HNS3_TXD_VLD_B)) 3992 return; 3993 desc--; 3994 } 3995 3996 tx_entry = &txq->sw_ring[txq->next_to_clean]; 3997 3998 if (txq->mbuf_fast_free_en) { 3999 rte_mempool_put_bulk(tx_entry->mbuf->pool, 4000 (void **)tx_entry, txq->tx_rs_thresh); 4001 for (i = 0; i < txq->tx_rs_thresh; i++) 4002 tx_entry[i].mbuf = NULL; 4003 goto update_field; 4004 } 4005 4006 for (i = 0; i < txq->tx_rs_thresh; i++) 4007 rte_prefetch0((tx_entry + i)->mbuf); 4008 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) { 4009 rte_pktmbuf_free_seg(tx_entry->mbuf); 4010 tx_entry->mbuf = NULL; 4011 } 4012 4013 update_field: 4014 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc; 4015 txq->tx_bd_ready += txq->tx_rs_thresh; 4016 } 4017 } 4018 4019 static inline void 4020 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts) 4021 { 4022 tx_entry->mbuf = pkts[0]; 4023 } 4024 4025 static inline void 4026 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts) 4027 { 4028 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]); 4029 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]); 4030 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]); 4031 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]); 4032 } 4033 4034 static inline void 4035 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) 4036 { 4037 #define PER_LOOP_NUM 4 4038 uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B); 4039 uint64_t dma_addr; 4040 uint32_t i; 4041 4042 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) { 4043 dma_addr = rte_mbuf_data_iova(*pkts); 4044 txdp->addr = rte_cpu_to_le_64(dma_addr); 4045 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); 4046 txdp->tx.paylen_fd_dop_ol4cs = 0; 4047 txdp->tx.type_cs_vlan_tso_len = 0; 4048 txdp->tx.ol_type_vlan_len_msec = 0; 4049 if (unlikely((*pkts)->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)) 4050 bd_flag |= BIT(HNS3_TXD_TSYN_B); 4051 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); 4052 } 4053 } 4054 4055 static inline void 4056 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) 4057 { 4058 uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B); 4059 uint64_t dma_addr; 4060 4061 dma_addr = rte_mbuf_data_iova(*pkts); 4062 txdp->addr = rte_cpu_to_le_64(dma_addr); 4063 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); 4064 txdp->tx.paylen_fd_dop_ol4cs = 0; 4065 txdp->tx.type_cs_vlan_tso_len = 0; 4066 txdp->tx.ol_type_vlan_len_msec = 0; 4067 if (unlikely((*pkts)->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)) 4068 bd_flag |= BIT(HNS3_TXD_TSYN_B); 4069 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); 4070 } 4071 4072 static inline void 4073 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq, 4074 struct rte_mbuf **pkts, 4075 uint16_t nb_pkts) 4076 { 4077 #define PER_LOOP_NUM 4 4078 #define PER_LOOP_MASK (PER_LOOP_NUM - 1) 4079 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use]; 4080 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use]; 4081 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK)); 4082 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK)); 4083 uint32_t i; 4084 4085 for (i = 0; i < mainpart; i += PER_LOOP_NUM) { 4086 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i); 4087 hns3_tx_setup_4bd(txdp + i, pkts + i); 4088 4089 /* Increment bytes counter */ 4090 uint32_t j; 4091 for (j = 0; j < PER_LOOP_NUM; j++) 4092 txq->basic_stats.bytes += pkts[i + j]->pkt_len; 4093 } 4094 if (unlikely(leftover > 0)) { 4095 for (i = 0; i < leftover; i++) { 4096 hns3_tx_backup_1mbuf(tx_entry + mainpart + i, 4097 pkts + mainpart + i); 4098 hns3_tx_setup_1bd(txdp + mainpart + i, 4099 pkts + mainpart + i); 4100 4101 /* Increment bytes counter */ 4102 txq->basic_stats.bytes += pkts[mainpart + i]->pkt_len; 4103 } 4104 } 4105 } 4106 4107 uint16_t 4108 hns3_xmit_pkts_simple(void *tx_queue, 4109 struct rte_mbuf **tx_pkts, 4110 uint16_t nb_pkts) 4111 { 4112 struct hns3_tx_queue *txq = tx_queue; 4113 uint16_t nb_tx = 0; 4114 4115 hns3_tx_free_buffer_simple(txq); 4116 4117 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts); 4118 if (unlikely(nb_pkts == 0)) { 4119 if (txq->tx_bd_ready == 0) 4120 txq->dfx_stats.queue_full_cnt++; 4121 return 0; 4122 } 4123 4124 txq->tx_bd_ready -= nb_pkts; 4125 if (txq->next_to_use + nb_pkts >= txq->nb_tx_desc) { 4126 nb_tx = txq->nb_tx_desc - txq->next_to_use; 4127 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx); 4128 txq->next_to_use = 0; 4129 } 4130 4131 if (nb_pkts > nb_tx) { 4132 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx); 4133 txq->next_to_use += nb_pkts - nb_tx; 4134 } 4135 4136 hns3_write_txq_tail_reg(txq, nb_pkts); 4137 4138 return nb_pkts; 4139 } 4140 4141 uint16_t 4142 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 4143 { 4144 struct hns3_tx_queue *txq = tx_queue; 4145 struct hns3_entry *tx_bak_pkt; 4146 struct hns3_desc *tx_ring; 4147 struct rte_mbuf *tx_pkt; 4148 struct rte_mbuf *m_seg; 4149 struct hns3_desc *desc; 4150 uint32_t nb_hold = 0; 4151 uint16_t tx_next_use; 4152 uint16_t tx_pkt_num; 4153 uint16_t tx_bd_max; 4154 uint16_t nb_buf; 4155 uint16_t nb_tx; 4156 uint16_t i; 4157 4158 hns3_tx_free_useless_buffer(txq); 4159 4160 tx_next_use = txq->next_to_use; 4161 tx_bd_max = txq->nb_tx_desc; 4162 tx_pkt_num = nb_pkts; 4163 tx_ring = txq->tx_ring; 4164 4165 /* send packets */ 4166 tx_bak_pkt = &txq->sw_ring[tx_next_use]; 4167 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) { 4168 tx_pkt = *tx_pkts++; 4169 4170 nb_buf = tx_pkt->nb_segs; 4171 4172 if (nb_buf > txq->tx_bd_ready) { 4173 txq->dfx_stats.queue_full_cnt++; 4174 if (nb_tx == 0) 4175 return 0; 4176 goto end_of_tx; 4177 } 4178 4179 /* 4180 * If packet length is less than minimum packet length supported 4181 * by hardware in Tx direction, driver need to pad it to avoid 4182 * error. 4183 */ 4184 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) < 4185 txq->min_tx_pkt_len)) { 4186 uint16_t add_len; 4187 char *appended; 4188 4189 add_len = txq->min_tx_pkt_len - 4190 rte_pktmbuf_pkt_len(tx_pkt); 4191 appended = rte_pktmbuf_append(tx_pkt, add_len); 4192 if (appended == NULL) { 4193 txq->dfx_stats.pkt_padding_fail_cnt++; 4194 break; 4195 } 4196 4197 memset(appended, 0, add_len); 4198 } 4199 4200 m_seg = tx_pkt; 4201 4202 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq)) 4203 goto end_of_tx; 4204 4205 if (hns3_parse_cksum(txq, tx_next_use, m_seg)) 4206 goto end_of_tx; 4207 4208 i = 0; 4209 desc = &tx_ring[tx_next_use]; 4210 4211 /* 4212 * If the packet is divided into multiple Tx Buffer Descriptors, 4213 * only need to fill vlan, paylen and tso into the first Tx 4214 * Buffer Descriptor. 4215 */ 4216 hns3_fill_first_desc(txq, desc, m_seg); 4217 4218 do { 4219 desc = &tx_ring[tx_next_use]; 4220 /* 4221 * Fill valid bits, DMA address and data length for each 4222 * Tx Buffer Descriptor. 4223 */ 4224 hns3_fill_per_desc(desc, m_seg); 4225 tx_bak_pkt->mbuf = m_seg; 4226 m_seg = m_seg->next; 4227 tx_next_use++; 4228 tx_bak_pkt++; 4229 if (tx_next_use >= tx_bd_max) { 4230 tx_next_use = 0; 4231 tx_bak_pkt = txq->sw_ring; 4232 } 4233 if (m_seg != NULL) 4234 TX_BD_LOG(&txq->hns->hw, DEBUG, desc); 4235 4236 i++; 4237 } while (m_seg != NULL); 4238 4239 /* Add end flag for the last Tx Buffer Descriptor */ 4240 desc->tx.tp_fe_sc_vld_ra_ri |= 4241 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B)); 4242 TX_BD_LOG(&txq->hns->hw, DEBUG, desc); 4243 4244 /* Increment bytes counter */ 4245 txq->basic_stats.bytes += tx_pkt->pkt_len; 4246 nb_hold += i; 4247 txq->next_to_use = tx_next_use; 4248 txq->tx_bd_ready -= i; 4249 } 4250 4251 end_of_tx: 4252 4253 if (likely(nb_tx)) 4254 hns3_write_txq_tail_reg(txq, nb_hold); 4255 4256 return nb_tx; 4257 } 4258 4259 int __rte_weak 4260 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev) 4261 { 4262 return -ENOTSUP; 4263 } 4264 4265 uint16_t __rte_weak 4266 hns3_xmit_pkts_vec(__rte_unused void *tx_queue, 4267 __rte_unused struct rte_mbuf **tx_pkts, 4268 __rte_unused uint16_t nb_pkts) 4269 { 4270 return 0; 4271 } 4272 4273 uint16_t __rte_weak 4274 hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue, 4275 struct rte_mbuf __rte_unused **tx_pkts, 4276 uint16_t __rte_unused nb_pkts) 4277 { 4278 return 0; 4279 } 4280 4281 int 4282 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 4283 struct rte_eth_burst_mode *mode) 4284 { 4285 static const struct { 4286 eth_tx_burst_t pkt_burst; 4287 const char *info; 4288 } burst_infos[] = { 4289 { hns3_xmit_pkts_simple, "Scalar Simple" }, 4290 { hns3_xmit_pkts, "Scalar" }, 4291 { hns3_xmit_pkts_vec, "Vector Neon" }, 4292 { hns3_xmit_pkts_vec_sve, "Vector Sve" }, 4293 { rte_eth_pkt_burst_dummy, "Dummy" }, 4294 }; 4295 4296 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 4297 int ret = -EINVAL; 4298 unsigned int i; 4299 4300 for (i = 0; i < RTE_DIM(burst_infos); i++) { 4301 if (pkt_burst == burst_infos[i].pkt_burst) { 4302 snprintf(mode->info, sizeof(mode->info), "%s", 4303 burst_infos[i].info); 4304 ret = 0; 4305 break; 4306 } 4307 } 4308 4309 return ret; 4310 } 4311 4312 static bool 4313 hns3_tx_check_simple_support(struct rte_eth_dev *dev) 4314 { 4315 uint64_t offloads = dev->data->dev_conf.txmode.offloads; 4316 4317 return (offloads == (offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)); 4318 } 4319 4320 static bool 4321 hns3_get_tx_prep_needed(struct rte_eth_dev *dev) 4322 { 4323 #define HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK (\ 4324 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \ 4325 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \ 4326 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \ 4327 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | \ 4328 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 4329 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \ 4330 RTE_ETH_TX_OFFLOAD_TCP_TSO | \ 4331 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | \ 4332 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | \ 4333 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO) 4334 4335 uint64_t tx_offload = dev->data->dev_conf.txmode.offloads; 4336 4337 if (tx_offload & HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK) 4338 return true; 4339 4340 return false; 4341 } 4342 4343 static eth_tx_prep_t 4344 hns3_get_tx_prepare(struct rte_eth_dev *dev) 4345 { 4346 return hns3_get_tx_prep_needed(dev) ? hns3_prep_pkts : NULL; 4347 } 4348 4349 static eth_tx_burst_t 4350 hns3_get_tx_function(struct rte_eth_dev *dev) 4351 { 4352 struct hns3_adapter *hns = dev->data->dev_private; 4353 bool vec_allowed, sve_allowed, simple_allowed; 4354 bool vec_support; 4355 4356 vec_support = hns3_tx_check_vec_support(dev) == 0; 4357 vec_allowed = vec_support && hns3_get_default_vec_support(); 4358 sve_allowed = vec_support && hns3_get_sve_support(); 4359 simple_allowed = hns3_tx_check_simple_support(dev); 4360 4361 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) 4362 return hns3_xmit_pkts_vec; 4363 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) 4364 return hns3_xmit_pkts_vec_sve; 4365 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) 4366 return hns3_xmit_pkts_simple; 4367 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) 4368 return hns3_xmit_pkts; 4369 4370 if (vec_allowed) 4371 return hns3_xmit_pkts_vec; 4372 if (simple_allowed) 4373 return hns3_xmit_pkts_simple; 4374 4375 return hns3_xmit_pkts; 4376 } 4377 4378 static void 4379 hns3_trace_rxtx_function(struct rte_eth_dev *dev) 4380 { 4381 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4382 struct rte_eth_burst_mode rx_mode; 4383 struct rte_eth_burst_mode tx_mode; 4384 4385 memset(&rx_mode, 0, sizeof(rx_mode)); 4386 memset(&tx_mode, 0, sizeof(tx_mode)); 4387 (void)hns3_rx_burst_mode_get(dev, 0, &rx_mode); 4388 (void)hns3_tx_burst_mode_get(dev, 0, &tx_mode); 4389 4390 hns3_dbg(hw, "using rx_pkt_burst: %s, tx_pkt_burst: %s.", 4391 rx_mode.info, tx_mode.info); 4392 } 4393 4394 static void 4395 hns3_eth_dev_fp_ops_config(const struct rte_eth_dev *dev) 4396 { 4397 struct rte_eth_fp_ops *fpo = rte_eth_fp_ops; 4398 uint16_t port_id = dev->data->port_id; 4399 4400 fpo[port_id].rx_pkt_burst = dev->rx_pkt_burst; 4401 fpo[port_id].tx_pkt_burst = dev->tx_pkt_burst; 4402 fpo[port_id].tx_pkt_prepare = dev->tx_pkt_prepare; 4403 fpo[port_id].rx_descriptor_status = dev->rx_descriptor_status; 4404 fpo[port_id].tx_descriptor_status = dev->tx_descriptor_status; 4405 fpo[port_id].rxq.data = dev->data->rx_queues; 4406 fpo[port_id].txq.data = dev->data->tx_queues; 4407 } 4408 4409 void 4410 hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) 4411 { 4412 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 4413 struct hns3_adapter *hns = eth_dev->data->dev_private; 4414 4415 if (hns->hw.adapter_state == HNS3_NIC_STARTED && 4416 rte_atomic_load_explicit(&hns->hw.reset.resetting, rte_memory_order_relaxed) == 0) { 4417 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); 4418 eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status; 4419 eth_dev->tx_pkt_burst = hw->set_link_down ? 4420 rte_eth_pkt_burst_dummy : 4421 hns3_get_tx_function(eth_dev); 4422 eth_dev->tx_pkt_prepare = hns3_get_tx_prepare(eth_dev); 4423 eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; 4424 } else { 4425 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 4426 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 4427 eth_dev->tx_pkt_prepare = NULL; 4428 } 4429 4430 hns3_trace_rxtx_function(eth_dev); 4431 hns3_eth_dev_fp_ops_config(eth_dev); 4432 } 4433 4434 void 4435 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 4436 struct rte_eth_rxq_info *qinfo) 4437 { 4438 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id]; 4439 4440 qinfo->mp = rxq->mb_pool; 4441 qinfo->nb_desc = rxq->nb_rx_desc; 4442 qinfo->scattered_rx = dev->data->scattered_rx; 4443 /* Report the HW Rx buffer length to user */ 4444 qinfo->rx_buf_size = rxq->rx_buf_len; 4445 4446 /* 4447 * If there are no available Rx buffer descriptors, incoming packets 4448 * are always dropped by hardware based on hns3 network engine. 4449 */ 4450 qinfo->conf.rx_drop_en = 1; 4451 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 4452 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 4453 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 4454 } 4455 4456 void 4457 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 4458 struct rte_eth_txq_info *qinfo) 4459 { 4460 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id]; 4461 4462 qinfo->nb_desc = txq->nb_tx_desc; 4463 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads; 4464 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh; 4465 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 4466 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 4467 } 4468 4469 int 4470 hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) 4471 { 4472 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4473 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id]; 4474 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4475 int ret; 4476 4477 if (!hns3_dev_get_support(hw, INDEP_TXRX)) 4478 return -ENOTSUP; 4479 4480 rte_spinlock_lock(&hw->lock); 4481 4482 if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) { 4483 hns3_err(hw, "fail to start Rx queue during resetting."); 4484 rte_spinlock_unlock(&hw->lock); 4485 return -EIO; 4486 } 4487 4488 ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX); 4489 if (ret) { 4490 hns3_err(hw, "fail to reset Rx queue %u, ret = %d.", 4491 rx_queue_id, ret); 4492 rte_spinlock_unlock(&hw->lock); 4493 return ret; 4494 } 4495 4496 if (rxq->sw_ring[0].mbuf != NULL) 4497 hns3_rx_queue_release_mbufs(rxq); 4498 4499 ret = hns3_init_rxq(hns, rx_queue_id); 4500 if (ret) { 4501 hns3_err(hw, "fail to init Rx queue %u, ret = %d.", 4502 rx_queue_id, ret); 4503 rte_spinlock_unlock(&hw->lock); 4504 return ret; 4505 } 4506 4507 hns3_enable_rxq(rxq, true); 4508 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 4509 rte_spinlock_unlock(&hw->lock); 4510 4511 return ret; 4512 } 4513 4514 static void 4515 hns3_reset_sw_rxq(struct hns3_rx_queue *rxq) 4516 { 4517 rxq->next_to_use = 0; 4518 rxq->rx_rearm_start = 0; 4519 rxq->rx_free_hold = 0; 4520 rxq->rx_rearm_nb = 0; 4521 rxq->pkt_first_seg = NULL; 4522 rxq->pkt_last_seg = NULL; 4523 memset(&rxq->rx_ring[0], 0, rxq->nb_rx_desc * sizeof(struct hns3_desc)); 4524 hns3_rxq_vec_setup(rxq); 4525 } 4526 4527 int 4528 hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) 4529 { 4530 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4531 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id]; 4532 4533 if (!hns3_dev_get_support(hw, INDEP_TXRX)) 4534 return -ENOTSUP; 4535 4536 rte_spinlock_lock(&hw->lock); 4537 4538 if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) { 4539 hns3_err(hw, "fail to stop Rx queue during resetting."); 4540 rte_spinlock_unlock(&hw->lock); 4541 return -EIO; 4542 } 4543 4544 hns3_enable_rxq(rxq, false); 4545 4546 hns3_rx_queue_release_mbufs(rxq); 4547 4548 hns3_reset_sw_rxq(rxq); 4549 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 4550 rte_spinlock_unlock(&hw->lock); 4551 4552 return 0; 4553 } 4554 4555 int 4556 hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) 4557 { 4558 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4559 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id]; 4560 int ret; 4561 4562 if (!hns3_dev_get_support(hw, INDEP_TXRX)) 4563 return -ENOTSUP; 4564 4565 rte_spinlock_lock(&hw->lock); 4566 4567 if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) { 4568 hns3_err(hw, "fail to start Tx queue during resetting."); 4569 rte_spinlock_unlock(&hw->lock); 4570 return -EIO; 4571 } 4572 4573 ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX); 4574 if (ret) { 4575 hns3_err(hw, "fail to reset Tx queue %u, ret = %d.", 4576 tx_queue_id, ret); 4577 rte_spinlock_unlock(&hw->lock); 4578 return ret; 4579 } 4580 4581 hns3_init_txq(txq); 4582 hns3_enable_txq(txq, true); 4583 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 4584 rte_spinlock_unlock(&hw->lock); 4585 4586 return ret; 4587 } 4588 4589 int 4590 hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) 4591 { 4592 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4593 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id]; 4594 4595 if (!hns3_dev_get_support(hw, INDEP_TXRX)) 4596 return -ENOTSUP; 4597 4598 rte_spinlock_lock(&hw->lock); 4599 4600 if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) { 4601 hns3_err(hw, "fail to stop Tx queue during resetting."); 4602 rte_spinlock_unlock(&hw->lock); 4603 return -EIO; 4604 } 4605 4606 hns3_enable_txq(txq, false); 4607 hns3_tx_queue_release_mbufs(txq); 4608 /* 4609 * All the mbufs in sw_ring are released and all the pointers in sw_ring 4610 * are set to NULL. If this queue is still called by upper layer, 4611 * residual SW status of this txq may cause these pointers in sw_ring 4612 * which have been set to NULL to be released again. To avoid it, 4613 * reinit the txq. 4614 */ 4615 hns3_init_txq(txq); 4616 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 4617 rte_spinlock_unlock(&hw->lock); 4618 4619 return 0; 4620 } 4621 4622 static int 4623 hns3_tx_done_cleanup_full(struct hns3_tx_queue *txq, uint32_t free_cnt) 4624 { 4625 uint16_t next_to_clean = txq->next_to_clean; 4626 uint16_t next_to_use = txq->next_to_use; 4627 uint16_t tx_bd_ready = txq->tx_bd_ready; 4628 struct hns3_entry *tx_pkt = &txq->sw_ring[next_to_clean]; 4629 struct hns3_desc *desc = &txq->tx_ring[next_to_clean]; 4630 uint32_t idx; 4631 4632 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc) 4633 free_cnt = txq->nb_tx_desc; 4634 4635 for (idx = 0; idx < free_cnt; idx++) { 4636 if (next_to_clean == next_to_use) 4637 break; 4638 if (desc->tx.tp_fe_sc_vld_ra_ri & 4639 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B))) 4640 break; 4641 if (tx_pkt->mbuf != NULL) { 4642 rte_pktmbuf_free_seg(tx_pkt->mbuf); 4643 tx_pkt->mbuf = NULL; 4644 } 4645 next_to_clean++; 4646 tx_bd_ready++; 4647 tx_pkt++; 4648 desc++; 4649 if (next_to_clean == txq->nb_tx_desc) { 4650 tx_pkt = txq->sw_ring; 4651 desc = txq->tx_ring; 4652 next_to_clean = 0; 4653 } 4654 } 4655 4656 if (idx > 0) { 4657 txq->next_to_clean = next_to_clean; 4658 txq->tx_bd_ready = tx_bd_ready; 4659 } 4660 4661 return (int)idx; 4662 } 4663 4664 int 4665 hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) 4666 { 4667 struct hns3_tx_queue *q = (struct hns3_tx_queue *)txq; 4668 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id]; 4669 4670 if (dev->tx_pkt_burst == hns3_xmit_pkts) 4671 return hns3_tx_done_cleanup_full(q, free_cnt); 4672 else if (dev->tx_pkt_burst == rte_eth_pkt_burst_dummy) 4673 return 0; 4674 else 4675 return -ENOTSUP; 4676 } 4677 4678 int 4679 hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) 4680 { 4681 volatile struct hns3_desc *rxdp; 4682 struct hns3_rx_queue *rxq; 4683 struct rte_eth_dev *dev; 4684 uint32_t bd_base_info; 4685 uint16_t desc_id; 4686 4687 rxq = (struct hns3_rx_queue *)rx_queue; 4688 if (offset >= rxq->nb_rx_desc) 4689 return -EINVAL; 4690 4691 desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc; 4692 rxdp = &rxq->rx_ring[desc_id]; 4693 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); 4694 dev = &rte_eth_devices[rxq->port_id]; 4695 if (dev->rx_pkt_burst == hns3_recv_pkts_simple || 4696 dev->rx_pkt_burst == hns3_recv_scattered_pkts) { 4697 if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold) 4698 return RTE_ETH_RX_DESC_UNAVAIL; 4699 } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec || 4700 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) { 4701 if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb) 4702 return RTE_ETH_RX_DESC_UNAVAIL; 4703 } else { 4704 return RTE_ETH_RX_DESC_UNAVAIL; 4705 } 4706 4707 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 4708 return RTE_ETH_RX_DESC_AVAIL; 4709 else 4710 return RTE_ETH_RX_DESC_DONE; 4711 } 4712 4713 int 4714 hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) 4715 { 4716 volatile struct hns3_desc *txdp; 4717 struct hns3_tx_queue *txq; 4718 struct rte_eth_dev *dev; 4719 uint16_t desc_id; 4720 4721 txq = (struct hns3_tx_queue *)tx_queue; 4722 if (offset >= txq->nb_tx_desc) 4723 return -EINVAL; 4724 4725 dev = &rte_eth_devices[txq->port_id]; 4726 if (dev->tx_pkt_burst != hns3_xmit_pkts_simple && 4727 dev->tx_pkt_burst != hns3_xmit_pkts && 4728 dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve && 4729 dev->tx_pkt_burst != hns3_xmit_pkts_vec) 4730 return RTE_ETH_TX_DESC_UNAVAIL; 4731 4732 desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc; 4733 txdp = &txq->tx_ring[desc_id]; 4734 if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B))) 4735 return RTE_ETH_TX_DESC_FULL; 4736 else 4737 return RTE_ETH_TX_DESC_DONE; 4738 } 4739 4740 uint32_t 4741 hns3_rx_queue_count(void *rx_queue) 4742 { 4743 /* 4744 * Number of BDs that have been processed by the driver 4745 * but have not been notified to the hardware. 4746 */ 4747 uint32_t driver_hold_bd_num; 4748 struct hns3_rx_queue *rxq; 4749 const struct rte_eth_dev *dev; 4750 uint32_t fbd_num; 4751 4752 rxq = rx_queue; 4753 dev = &rte_eth_devices[rxq->port_id]; 4754 4755 fbd_num = hns3_read_dev(rxq, HNS3_RING_RX_FBDNUM_REG); 4756 if (dev->rx_pkt_burst == hns3_recv_pkts_vec || 4757 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) 4758 driver_hold_bd_num = rxq->rx_rearm_nb; 4759 else 4760 driver_hold_bd_num = rxq->rx_free_hold; 4761 4762 if (fbd_num <= driver_hold_bd_num) 4763 return 0; 4764 else 4765 return fbd_num - driver_hold_bd_num; 4766 } 4767 4768 void 4769 hns3_enable_rxd_adv_layout(struct hns3_hw *hw) 4770 { 4771 /* 4772 * If the hardware support rxd advanced layout, then driver enable it 4773 * default. 4774 */ 4775 if (hns3_dev_get_support(hw, RXD_ADV_LAYOUT)) 4776 hns3_write_dev(hw, HNS3_RXD_ADV_LAYOUT_EN_REG, 1); 4777 } 4778 4779 void 4780 hns3_stop_tx_datapath(struct rte_eth_dev *dev) 4781 { 4782 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 4783 dev->tx_pkt_prepare = NULL; 4784 hns3_eth_dev_fp_ops_config(dev); 4785 4786 if (rte_eal_process_type() == RTE_PROC_SECONDARY) 4787 return; 4788 4789 rte_wmb(); 4790 /* Disable tx datapath on secondary process. */ 4791 hns3_mp_req_stop_tx(dev); 4792 /* Prevent crashes when queues are still in use. */ 4793 rte_delay_ms(dev->data->nb_tx_queues); 4794 } 4795 4796 void 4797 hns3_start_tx_datapath(struct rte_eth_dev *dev) 4798 { 4799 dev->tx_pkt_burst = hns3_get_tx_function(dev); 4800 dev->tx_pkt_prepare = hns3_get_tx_prepare(dev); 4801 hns3_eth_dev_fp_ops_config(dev); 4802 4803 if (rte_eal_process_type() == RTE_PROC_SECONDARY) 4804 return; 4805 4806 hns3_mp_req_start_tx(dev); 4807 } 4808 4809 void 4810 hns3_stop_rxtx_datapath(struct rte_eth_dev *dev) 4811 { 4812 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4813 4814 hns3_set_rxtx_function(dev); 4815 4816 if (rte_eal_process_type() == RTE_PROC_SECONDARY) 4817 return; 4818 4819 rte_wmb(); 4820 /* Disable datapath on secondary process. */ 4821 hns3_mp_req_stop_rxtx(dev); 4822 /* Prevent crashes when queues are still in use. */ 4823 rte_delay_ms(hw->cfg_max_queues); 4824 } 4825 4826 void 4827 hns3_start_rxtx_datapath(struct rte_eth_dev *dev) 4828 { 4829 hns3_set_rxtx_function(dev); 4830 4831 if (rte_eal_process_type() == RTE_PROC_SECONDARY) 4832 return; 4833 4834 hns3_mp_req_start_rxtx(dev); 4835 } 4836 4837 static int 4838 hns3_monitor_callback(const uint64_t value, 4839 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused) 4840 { 4841 const uint64_t vld = rte_le_to_cpu_32(BIT(HNS3_RXD_VLD_B)); 4842 return (value & vld) == vld ? -1 : 0; 4843 } 4844 4845 int 4846 hns3_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) 4847 { 4848 struct hns3_rx_queue *rxq = rx_queue; 4849 struct hns3_desc *rxdp = &rxq->rx_ring[rxq->next_to_use]; 4850 4851 pmc->addr = &rxdp->rx.bd_base_info; 4852 pmc->fn = hns3_monitor_callback; 4853 pmc->size = sizeof(uint32_t); 4854 4855 return 0; 4856 } 4857