1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef HNS3_REGS_H 6 #define HNS3_REGS_H 7 8 #include <ethdev_driver.h> 9 #include <rte_dev_info.h> 10 11 /* bar registers for cmdq */ 12 #define HNS3_CMDQ_TX_ADDR_L_REG 0x27000 13 #define HNS3_CMDQ_TX_ADDR_H_REG 0x27004 14 #define HNS3_CMDQ_TX_DEPTH_REG 0x27008 15 #define HNS3_CMDQ_TX_TAIL_REG 0x27010 16 #define HNS3_CMDQ_TX_HEAD_REG 0x27014 17 #define HNS3_CMDQ_RX_ADDR_L_REG 0x27018 18 #define HNS3_CMDQ_RX_ADDR_H_REG 0x2701c 19 #define HNS3_CMDQ_RX_DEPTH_REG 0x27020 20 #define HNS3_CMDQ_RX_TAIL_REG 0x27024 21 #define HNS3_CMDQ_RX_HEAD_REG 0x27028 22 #define HNS3_CMDQ_INTR_STS_REG 0x27104 23 #define HNS3_CMDQ_INTR_EN_REG 0x27108 24 #define HNS3_CMDQ_INTR_GEN_REG 0x2710C 25 26 /* Vector0 interrupt CMDQ event source register(RW) */ 27 #define HNS3_VECTOR0_CMDQ_SRC_REG 0x27100 28 /* Vector0 interrupt CMDQ event status register(RO) */ 29 #define HNS3_VECTOR0_CMDQ_STAT_REG 0x27104 30 31 #define HNS3_VECTOR0_OTHER_INT_STS_REG 0x20800 32 33 #define HNS3_RAS_PF_OTHER_INT_STS_REG 0x20B00 34 #define HNS3_RAS_REG_NFE_MASK 0xFF00 35 36 #define HNS3_MISC_VECTOR_REG_BASE 0x20400 37 #define HNS3_VECTOR0_OTER_EN_REG 0x20600 38 #define HNS3_MISC_RESET_STS_REG 0x20700 39 #define HNS3_GLOBAL_RESET_REG 0x20A00 40 #define HNS3_FUN_RST_ING 0x20C00 41 #define HNS3_GRO_EN_REG 0x28000 42 43 #define HNS3_RPU_DROP_CNT_REG 0x28004 44 #define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008 45 46 /* Vector0 register bits for reset */ 47 #define HNS3_VECTOR0_FUNCRESET_INT_B 0 48 #define HNS3_VECTOR0_GLOBALRESET_INT_B 5 49 #define HNS3_VECTOR0_CORERESET_INT_B 6 50 #define HNS3_VECTOR0_IMPRESET_INT_B 7 51 52 /* CMDQ register bits for RX event(=MBX event) */ 53 #define HNS3_VECTOR0_RX_CMDQ_INT_B 1 54 #define HNS3_VECTOR0_REG_MSIX_MASK 0x1FF00 55 /* RST register bits for RESET event */ 56 #define HNS3_VECTOR0_RST_INT_B 2 57 58 #define HNS3_VF_RST_ING 0x07008 59 #define HNS3_VF_RST_ING_BIT BIT(16) 60 61 /* bar registers for rcb */ 62 #define HNS3_RING_RX_BASEADDR_L_REG 0x00000 63 #define HNS3_RING_RX_BASEADDR_H_REG 0x00004 64 #define HNS3_RING_RX_BD_NUM_REG 0x00008 65 #define HNS3_RING_RX_BD_LEN_REG 0x0000C 66 #define HNS3_RING_RX_MERGE_EN_REG 0x00014 67 #define HNS3_RING_RX_TAIL_REG 0x00018 68 #define HNS3_RING_RX_HEAD_REG 0x0001C 69 #define HNS3_RING_RX_FBDNUM_REG 0x00020 70 #define HNS3_RING_RX_OFFSET_REG 0x00024 71 #define HNS3_RING_RX_FBD_OFFSET_REG 0x00028 72 #define HNS3_RING_RX_PKTNUM_RECORD_REG 0x0002C 73 #define HNS3_RING_RX_STASH_REG 0x00030 74 #define HNS3_RING_RX_BD_ERR_REG 0x00034 75 76 #define HNS3_RING_TX_BASEADDR_L_REG 0x00040 77 #define HNS3_RING_TX_BASEADDR_H_REG 0x00044 78 #define HNS3_RING_TX_BD_NUM_REG 0x00048 79 #define HNS3_RING_TX_PRIORITY_REG 0x0004C 80 #define HNS3_RING_TX_TC_REG 0x00050 81 #define HNS3_RING_TX_MERGE_EN_REG 0x00054 82 #define HNS3_RING_TX_TAIL_REG 0x00058 83 #define HNS3_RING_TX_HEAD_REG 0x0005C 84 #define HNS3_RING_TX_FBDNUM_REG 0x00060 85 #define HNS3_RING_TX_OFFSET_REG 0x00064 86 #define HNS3_RING_TX_EBD_NUM_REG 0x00068 87 #define HNS3_RING_TX_PKTNUM_RECORD_REG 0x0006C 88 #define HNS3_RING_TX_EBD_OFFSET_REG 0x00070 89 #define HNS3_RING_TX_BD_ERR_REG 0x00074 90 91 #define HNS3_RING_EN_REG 0x00090 92 #define HNS3_RING_RX_EN_REG 0x00098 93 #define HNS3_RING_TX_EN_REG 0x000d4 94 95 #define HNS3_RING_EN_B 0 96 97 #define HNS3_TQP_REG_OFFSET 0x80000 98 #define HNS3_TQP_REG_SIZE 0x200 99 100 #define HNS3_TQP_EXT_REG_OFFSET 0x100 101 #define HNS3_MIN_EXTEND_QUEUE_ID 1024 102 103 /* bar registers for tqp interrupt */ 104 #define HNS3_TQP_INTR_REG_BASE 0x20000 105 #define HNS3_TQP_INTR_EXT_REG_BASE 0x30000 106 #define HNS3_TQP_INTR_CTRL_REG 0 107 #define HNS3_TQP_INTR_GL0_REG 0x100 108 #define HNS3_TQP_INTR_GL1_REG 0x200 109 #define HNS3_TQP_INTR_GL2_REG 0x300 110 #define HNS3_TQP_INTR_RL_REG 0x900 111 #define HNS3_TQP_INTR_TX_QL_REG 0xe00 112 #define HNS3_TQP_INTR_RX_QL_REG 0xf00 113 #define HNS3_TQP_INTR_RL_EN_B 6 114 115 #define HNS3_MIN_EXT_TQP_INTR_ID 64 116 #define HNS3_TQP_INTR_LOW_ORDER_OFFSET 0x4 117 #define HNS3_TQP_INTR_HIGH_ORDER_OFFSET 0x1000 118 119 #define HNS3_TQP_INTR_GL_MAX 0x1FE0 120 #define HNS3_TQP_INTR_GL_DEFAULT 20 121 #define HNS3_TQP_INTR_GL_UNIT_1US BIT(31) 122 #define HNS3_TQP_INTR_RL_MAX 0xEC 123 #define HNS3_TQP_INTR_RL_ENABLE_MASK 0x40 124 #define HNS3_TQP_INTR_RL_DEFAULT 0 125 #define HNS3_TQP_INTR_QL_DEFAULT 0 126 127 /* gl_usec convert to hardware count, as writing each 1 represents 2us */ 128 #define HNS3_GL_USEC_TO_REG(gl_usec) ((gl_usec) >> 1) 129 /* rl_usec convert to hardware count, as writing each 1 represents 4us */ 130 #define HNS3_RL_USEC_TO_REG(rl_usec) ((rl_usec) >> 2) 131 132 int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs); 133 #endif /* HNS3_REGS_H */ 134