1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef HNS3_INTR_H 6 #define HNS3_INTR_H 7 8 #include <stdint.h> 9 10 #include "hns3_ethdev.h" 11 12 #define HNS3_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF 13 #define HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF 14 #define HNS3_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF 15 #define HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF 16 #define HNS3_PPP_PF_ERR_INT_EN 0x0003 17 #define HNS3_PPP_PF_ERR_INT_EN_MASK 0x0003 18 #define HNS3_PPP_MPF_ECC_ERR_INT2_EN 0x003F 19 #define HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F 20 #define HNS3_PPP_MPF_ECC_ERR_INT3_EN 0x003F 21 #define HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F 22 23 #define HNS3_MAC_COMMON_ERR_INT_EN 0x107FF 24 #define HNS3_MAC_COMMON_ERR_INT_EN_MASK 0x107FF 25 #define HNS3_MAC_TNL_INT_EN GENMASK(9, 0) 26 #define HNS3_MAC_TNL_INT_EN_MASK GENMASK(9, 0) 27 #define HNS3_MAC_TNL_INT_CLR GENMASK(9, 0) 28 29 #define HNS3_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000 30 #define HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000 31 #define HNS3_IMP_ITCM4_ECC_ERR_INT_EN 0x300 32 #define HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300 33 #define HNS3_IMP_RD_POISON_ERR_INT_EN 0x0100 34 #define HNS3_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100 35 36 #define HNS3_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF 37 #define HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF 38 39 #define HNS3_TQP_ECC_ERR_INT_EN 0x0FFF 40 #define HNS3_TQP_ECC_ERR_INT_EN_MASK 0x0FFF 41 42 #define HNS3_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000 43 #define HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000 44 45 #define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0) 46 #define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0) 47 #define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0) 48 #define HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0) 49 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF 50 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF 51 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN2 0xB 52 #define HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB 53 #define HNS3_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0) 54 #define HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16) 55 #define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0) 56 #define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0) 57 58 #define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0) 59 #define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) 60 #define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0) 61 #define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) 62 #define HNS3_SSU_BIT32_ECC_ERR_INT_EN 0x0101 63 #define HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101 64 #define HNS3_SSU_COMMON_INT_EN GENMASK(9, 0) 65 #define HNS3_SSU_COMMON_INT_EN_MASK GENMASK(9, 0) 66 #define HNS3_SSU_PORT_BASED_ERR_INT_EN 0x0BFF 67 #define HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000 68 #define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0) 69 #define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0) 70 71 #define HNS3_IGU_ERR_INT_ENABLE 0x0000066F 72 #define HNS3_IGU_ERR_INT_DISABLE 0x00000660 73 #define HNS3_IGU_ERR_INT_EN_MASK 0x000F 74 #define HNS3_IGU_TNL_ERR_INT_EN 0x0002AABF 75 #define HNS3_IGU_TNL_ERR_INT_EN_MASK 0x003F 76 77 #define HNS3_NCSI_ERR_INT_EN 0x3 78 79 #define HNS3_TM_SCH_ECC_ERR_INT_EN 0x3 80 #define HNS3_TM_QCN_ERR_INT_TYPE 0x29 81 #define HNS3_TM_QCN_FIFO_INT_EN 0xFFFF00 82 #define HNS3_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF 83 84 #define HNS3_RESET_PROCESS_MS 200 85 86 #define HNS3_DESC_DATA_MAX 8 87 #define HNS3_REG_NUM_MAX 256 88 #define HNS3_DESC_NO_DATA_LEN 8 89 #define HNS3_DESC_DATA_UNIT_SIZE 4 90 91 enum hns3_mod_name_list { 92 MODULE_NONE, 93 MODULE_BIOS_COMMON, 94 MODULE_GE, 95 MODULE_IGU_EGU, 96 MODULE_LGE, 97 MODULE_NCSI, 98 MODULE_PPP, 99 MODULE_QCN, 100 MODULE_RCB_RX, 101 MODULE_RTC, 102 MODULE_SSU, 103 MODULE_TM, 104 MODULE_RCB_TX, 105 MODULE_TXDMA, 106 MODULE_MASTER, 107 MODULE_HIMAC, 108 }; 109 110 enum hns3_err_type_list { 111 NONE_ERROR, 112 FIFO_ERROR, 113 MEMORY_ERROR, 114 POISION_ERROR, 115 MSIX_ECC_ERROR, 116 TQP_INT_ECC_ERROR, 117 PF_ABNORMAL_INT_ERROR, 118 MPF_ABNORMAL_INT_ERROR, 119 COMMON_ERROR, 120 PORT_ERROR, 121 ETS_ERROR, 122 NCSI_ERROR, 123 GLB_ERROR, 124 }; 125 126 struct hns3_hw_mod_name { 127 enum hns3_mod_name_list module_name; 128 const char *msg; 129 }; 130 131 struct hns3_hw_err_type { 132 enum hns3_err_type_list error_type; 133 const char *msg; 134 }; 135 136 struct hns3_sum_err_info { 137 uint8_t reset_type; /* the total reset type */ 138 uint8_t mod_num; /* the modules num encounter error */ 139 uint8_t rsv[2]; 140 }; 141 142 struct hns3_mod_err_info { 143 uint8_t mod_id; /* the error module id */ 144 uint8_t err_num; /* the errors num in module */ 145 uint8_t rsv[2]; 146 }; 147 148 struct hns3_type_reg_err_info { 149 uint8_t type_id; /* the type id of error */ 150 uint8_t reg_num; /* the related registers num of this error */ 151 uint8_t rsv[2]; 152 uint32_t reg[HNS3_REG_NUM_MAX]; /* the registers value */ 153 }; 154 155 struct hns3_hw_blk { 156 const char *name; 157 int (*enable_err_intr)(struct hns3_adapter *hns, bool en); 158 }; 159 160 struct hns3_hw_error { 161 uint32_t int_msk; 162 const char *msg; 163 enum hns3_reset_level reset_level; 164 }; 165 166 struct hns3_hw_error_desc { 167 uint8_t desc_offset; 168 uint8_t data_offset; 169 const char *msg; 170 const struct hns3_hw_error *hw_err; 171 }; 172 173 int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en); 174 void hns3_handle_msix_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels); 175 void hns3_handle_ras_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels); 176 void hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en); 177 void hns3_handle_error(struct hns3_adapter *hns); 178 179 void hns3_intr_unregister(const struct rte_intr_handle *hdl, 180 rte_intr_callback_fn cb_fn, void *cb_arg); 181 void hns3_notify_reset_ready(struct hns3_hw *hw, bool enable); 182 int hns3_reset_init(struct hns3_hw *hw); 183 void hns3_wait_callback(void *param); 184 void hns3_schedule_reset(struct hns3_adapter *hns); 185 void hns3_schedule_delayed_reset(struct hns3_adapter *hns); 186 int hns3_reset_req_hw_reset(struct hns3_adapter *hns); 187 int hns3_reset_process(struct hns3_adapter *hns, 188 enum hns3_reset_level new_level); 189 void hns3_reset_abort(struct hns3_adapter *hns); 190 void hns3_start_report_lse(struct rte_eth_dev *dev); 191 void hns3_stop_report_lse(struct rte_eth_dev *dev); 192 193 #endif /* HNS3_INTR_H */ 194