1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <rte_alarm.h> 10 11 #include "hns3_cmd.h" 12 #include "hns3_mbx.h" 13 #include "hns3_rss.h" 14 #include "hns3_fdir.h" 15 #include "hns3_stats.h" 16 17 /* Vendor ID */ 18 #define PCI_VENDOR_ID_HUAWEI 0x19e5 19 20 /* Device IDs */ 21 #define HNS3_DEV_ID_GE 0xA220 22 #define HNS3_DEV_ID_25GE 0xA221 23 #define HNS3_DEV_ID_25GE_RDMA 0xA222 24 #define HNS3_DEV_ID_50GE_RDMA 0xA224 25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 26 #define HNS3_DEV_ID_100G_VF 0xA22E 27 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 28 29 #define HNS3_UC_MACADDR_NUM 128 30 #define HNS3_VF_UC_MACADDR_NUM 48 31 #define HNS3_MC_MACADDR_NUM 128 32 33 #define HNS3_MAX_BD_SIZE 65535 34 #define HNS3_MAX_TX_BD_PER_PKT 8 35 #define HNS3_MAX_FRAME_LEN 9728 36 #define HNS3_VLAN_TAG_SIZE 4 37 #define HNS3_DEFAULT_RX_BUF_LEN 2048 38 39 #define HNS3_ETH_OVERHEAD \ 40 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 41 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 42 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 43 #define HNS3_DEFAULT_MTU 1500UL 44 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 45 #define HNS3_MIN_PKT_SIZE 60 46 47 #define HNS3_4_TCS 4 48 #define HNS3_8_TCS 8 49 50 #define HNS3_MAX_PF_NUM 8 51 #define HNS3_UMV_TBL_SIZE 3072 52 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 53 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 54 55 #define HNS3_PF_CFG_BLOCK_SIZE 32 56 #define HNS3_PF_CFG_DESC_NUM \ 57 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 58 59 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 60 61 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 62 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 63 64 #define HNS3_QUIT_RESET_CNT 10 65 #define HNS3_QUIT_RESET_DELAY_MS 100 66 67 #define HNS3_POLL_RESPONE_MS 1 68 69 #define HNS3_MAX_USER_PRIO 8 70 #define HNS3_PG_NUM 4 71 enum hns3_fc_mode { 72 HNS3_FC_NONE, 73 HNS3_FC_RX_PAUSE, 74 HNS3_FC_TX_PAUSE, 75 HNS3_FC_FULL, 76 HNS3_FC_DEFAULT 77 }; 78 79 #define HNS3_SCH_MODE_SP 0 80 #define HNS3_SCH_MODE_DWRR 1 81 struct hns3_pg_info { 82 uint8_t pg_id; 83 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 84 uint8_t tc_bit_map; 85 uint32_t bw_limit; 86 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 87 }; 88 89 struct hns3_tc_info { 90 uint8_t tc_id; 91 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 92 uint8_t pgid; 93 uint32_t bw_limit; 94 uint8_t up_to_tc_map; /* user priority maping on the TC */ 95 }; 96 97 struct hns3_dcb_info { 98 uint8_t num_tc; 99 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 100 uint8_t pg_dwrr[HNS3_PG_NUM]; 101 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 102 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 103 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 104 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 105 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 106 }; 107 108 enum hns3_fc_status { 109 HNS3_FC_STATUS_NONE, 110 HNS3_FC_STATUS_MAC_PAUSE, 111 HNS3_FC_STATUS_PFC, 112 }; 113 114 struct hns3_tc_queue_info { 115 uint8_t tqp_offset; /* TQP offset from base TQP */ 116 uint8_t tqp_count; /* Total TQPs */ 117 uint8_t tc; /* TC index */ 118 bool enable; /* If this TC is enable or not */ 119 }; 120 121 struct hns3_cfg { 122 uint8_t vmdq_vport_num; 123 uint8_t tc_num; 124 uint16_t tqp_desc_num; 125 uint16_t rx_buf_len; 126 uint16_t rss_size_max; 127 uint8_t phy_addr; 128 uint8_t media_type; 129 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 130 uint8_t default_speed; 131 uint32_t numa_node_map; 132 uint8_t speed_ability; 133 uint16_t umv_space; 134 }; 135 136 /* mac media type */ 137 enum hns3_media_type { 138 HNS3_MEDIA_TYPE_UNKNOWN, 139 HNS3_MEDIA_TYPE_FIBER, 140 HNS3_MEDIA_TYPE_COPPER, 141 HNS3_MEDIA_TYPE_BACKPLANE, 142 HNS3_MEDIA_TYPE_NONE, 143 }; 144 145 struct hns3_mac { 146 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 147 bool default_addr_setted; /* whether default addr(mac_addr) is setted */ 148 uint8_t media_type; 149 uint8_t phy_addr; 150 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 151 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 152 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 153 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 154 }; 155 156 struct hns3_fake_queue_data { 157 void **rx_queues; /* Array of pointers to fake RX queues. */ 158 void **tx_queues; /* Array of pointers to fake TX queues. */ 159 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 160 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 161 }; 162 163 /* Primary process maintains driver state in main thread. 164 * 165 * +---------------+ 166 * | UNINITIALIZED |<-----------+ 167 * +---------------+ | 168 * |.eth_dev_init |.eth_dev_uninit 169 * V | 170 * +---------------+------------+ 171 * | INITIALIZED | 172 * +---------------+<-----------<---------------+ 173 * |.dev_configure | | 174 * V |failed | 175 * +---------------+------------+ | 176 * | CONFIGURING | | 177 * +---------------+----+ | 178 * |success | | 179 * | | +---------------+ 180 * | | | CLOSING | 181 * | | +---------------+ 182 * | | ^ 183 * V |.dev_configure | 184 * +---------------+----+ |.dev_close 185 * | CONFIGURED |----------------------------+ 186 * +---------------+<-----------+ 187 * |.dev_start | 188 * V | 189 * +---------------+ | 190 * | STARTING |------------^ 191 * +---------------+ failed | 192 * |success | 193 * | +---------------+ 194 * | | STOPPING | 195 * | +---------------+ 196 * | ^ 197 * V |.dev_stop 198 * +---------------+------------+ 199 * | STARTED | 200 * +---------------+ 201 */ 202 enum hns3_adapter_state { 203 HNS3_NIC_UNINITIALIZED = 0, 204 HNS3_NIC_INITIALIZED, 205 HNS3_NIC_CONFIGURING, 206 HNS3_NIC_CONFIGURED, 207 HNS3_NIC_STARTING, 208 HNS3_NIC_STARTED, 209 HNS3_NIC_STOPPING, 210 HNS3_NIC_CLOSING, 211 HNS3_NIC_CLOSED, 212 HNS3_NIC_REMOVED, 213 HNS3_NIC_NSTATES 214 }; 215 216 /* Reset various stages, execute in order */ 217 enum hns3_reset_stage { 218 /* Stop query services, stop transceiver, disable MAC */ 219 RESET_STAGE_DOWN, 220 /* Clear reset completion flags, disable send command */ 221 RESET_STAGE_PREWAIT, 222 /* Inform IMP to start resetting */ 223 RESET_STAGE_REQ_HW_RESET, 224 /* Waiting for hardware reset to complete */ 225 RESET_STAGE_WAIT, 226 /* Reinitialize hardware */ 227 RESET_STAGE_DEV_INIT, 228 /* Restore user settings and enable MAC */ 229 RESET_STAGE_RESTORE, 230 /* Restart query services, start transceiver */ 231 RESET_STAGE_DONE, 232 /* Not in reset state */ 233 RESET_STAGE_NONE, 234 }; 235 236 enum hns3_reset_level { 237 HNS3_NONE_RESET, 238 HNS3_VF_FUNC_RESET, /* A VF function reset */ 239 /* 240 * All VFs under a PF perform function reset. 241 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 242 * of the reset level and the one defined in kernel driver should be 243 * same. 244 */ 245 HNS3_VF_PF_FUNC_RESET = 2, 246 /* 247 * All VFs under a PF perform FLR reset. 248 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 249 * of the reset level and the one defined in kernel driver should be 250 * same. 251 */ 252 HNS3_VF_FULL_RESET = 3, 253 HNS3_FLR_RESET, /* A VF perform FLR reset */ 254 /* All VFs under the rootport perform a global or IMP reset */ 255 HNS3_VF_RESET, 256 HNS3_FUNC_RESET, /* A PF function reset */ 257 /* All PFs under the rootport perform a global reset */ 258 HNS3_GLOBAL_RESET, 259 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 260 HNS3_MAX_RESET 261 }; 262 263 enum hns3_wait_result { 264 HNS3_WAIT_UNKNOWN, 265 HNS3_WAIT_REQUEST, 266 HNS3_WAIT_SUCCESS, 267 HNS3_WAIT_TIMEOUT 268 }; 269 270 #define HNS3_RESET_SYNC_US 100000 271 272 struct hns3_reset_stats { 273 uint64_t request_cnt; /* Total request reset times */ 274 uint64_t global_cnt; /* Total GLOBAL reset times */ 275 uint64_t imp_cnt; /* Total IMP reset times */ 276 uint64_t exec_cnt; /* Total reset executive times */ 277 uint64_t success_cnt; /* Total reset successful times */ 278 uint64_t fail_cnt; /* Total reset failed times */ 279 uint64_t merge_cnt; /* Total merged in high reset times */ 280 }; 281 282 typedef bool (*check_completion_func)(struct hns3_hw *hw); 283 284 struct hns3_wait_data { 285 void *hns; 286 uint64_t end_ms; 287 uint64_t interval; 288 int16_t count; 289 enum hns3_wait_result result; 290 check_completion_func check_completion; 291 }; 292 293 struct hns3_reset_ops { 294 void (*reset_service)(void *arg); 295 int (*stop_service)(struct hns3_adapter *hns); 296 int (*prepare_reset)(struct hns3_adapter *hns); 297 int (*wait_hardware_ready)(struct hns3_adapter *hns); 298 int (*reinit_dev)(struct hns3_adapter *hns); 299 int (*restore_conf)(struct hns3_adapter *hns); 300 int (*start_service)(struct hns3_adapter *hns); 301 }; 302 303 enum hns3_schedule { 304 SCHEDULE_NONE, 305 SCHEDULE_PENDING, 306 SCHEDULE_REQUESTED, 307 SCHEDULE_DEFERRED, 308 }; 309 310 struct hns3_reset_data { 311 enum hns3_reset_stage stage; 312 rte_atomic16_t schedule; 313 /* Reset flag, covering the entire reset process */ 314 rte_atomic16_t resetting; 315 /* Used to disable sending cmds during reset */ 316 rte_atomic16_t disable_cmd; 317 /* The reset level being processed */ 318 enum hns3_reset_level level; 319 /* Reset level set, each bit represents a reset level */ 320 uint64_t pending; 321 /* Request reset level set, from interrupt or mailbox */ 322 uint64_t request; 323 int attempts; /* Reset failure retry */ 324 int retries; /* Timeout failure retry in reset_post */ 325 /* 326 * At the time of global or IMP reset, the command cannot be sent to 327 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 328 * reset process, so the mbuf is required to be released after the reset 329 * is completed.The mbuf_deferred_free is used to mark whether mbuf 330 * needs to be released. 331 */ 332 bool mbuf_deferred_free; 333 struct timeval start_time; 334 struct hns3_reset_stats stats; 335 const struct hns3_reset_ops *ops; 336 struct hns3_wait_data *wait_data; 337 }; 338 339 struct hns3_hw { 340 struct rte_eth_dev_data *data; 341 void *io_base; 342 struct hns3_cmq cmq; 343 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 344 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ 345 pthread_t irq_thread_id; 346 struct hns3_mac mac; 347 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 348 struct hns3_tqp_stats tqp_stats; 349 /* Include Mac stats | Rx stats | Tx stats */ 350 struct hns3_mac_stats mac_stats; 351 uint32_t fw_version; 352 353 uint16_t num_msi; 354 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 355 uint16_t tqps_num; /* num task queue pairs of this function */ 356 uint16_t rss_size_max; /* HW defined max RSS task queue */ 357 uint16_t rx_buf_len; 358 uint16_t num_tx_desc; /* desc num of per tx queue */ 359 uint16_t num_rx_desc; /* desc num of per rx queue */ 360 361 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 362 int mc_addrs_num; /* Multicast mac addresses number */ 363 364 /* The configuration info of RSS */ 365 struct hns3_rss_conf rss_info; 366 367 uint8_t num_tc; /* Total number of enabled TCs */ 368 uint8_t hw_tc_map; 369 enum hns3_fc_mode current_mode; 370 enum hns3_fc_mode requested_mode; 371 struct hns3_dcb_info dcb_info; 372 enum hns3_fc_status current_fc_status; /* current flow control status */ 373 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 374 uint16_t used_rx_queues; 375 uint16_t used_tx_queues; 376 377 /* Config max queue numbers between rx and tx queues from user */ 378 uint16_t cfg_max_queues; 379 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 380 uint16_t alloc_rss_size; /* RX queue number per TC */ 381 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 382 383 uint32_t flag; 384 /* 385 * PMD setup and configuration is not thread safe. Since it is not 386 * performance sensitive, it is better to guarantee thread-safety 387 * and add device level lock. Adapter control operations which 388 * change its state should acquire the lock. 389 */ 390 rte_spinlock_t lock; 391 enum hns3_adapter_state adapter_state; 392 struct hns3_reset_data reset; 393 }; 394 395 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 396 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 397 398 struct hns3_err_msix_intr_stats { 399 uint64_t mac_afifo_tnl_intr_cnt; 400 uint64_t ppu_mpf_abnormal_intr_st2_cnt; 401 uint64_t ssu_port_based_pf_intr_cnt; 402 uint64_t ppp_pf_abnormal_intr_cnt; 403 uint64_t ppu_pf_abnormal_intr_cnt; 404 }; 405 406 /* vlan entry information. */ 407 struct hns3_user_vlan_table { 408 LIST_ENTRY(hns3_user_vlan_table) next; 409 bool hd_tbl_status; 410 uint16_t vlan_id; 411 }; 412 413 struct hns3_port_base_vlan_config { 414 uint16_t state; 415 uint16_t pvid; 416 }; 417 418 /* Vlan tag configuration for RX direction */ 419 struct hns3_rx_vtag_cfg { 420 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */ 421 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */ 422 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */ 423 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ 424 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ 425 }; 426 427 /* Vlan tag configuration for TX direction */ 428 struct hns3_tx_vtag_cfg { 429 bool accept_tag1; /* Whether accept tag1 packet from host */ 430 bool accept_untag1; /* Whether accept untag1 packet from host */ 431 bool accept_tag2; 432 bool accept_untag2; 433 bool insert_tag1_en; /* Whether insert inner vlan tag */ 434 bool insert_tag2_en; /* Whether insert outer vlan tag */ 435 uint16_t default_tag1; /* The default inner vlan tag to insert */ 436 uint16_t default_tag2; /* The default outer vlan tag to insert */ 437 }; 438 439 struct hns3_vtag_cfg { 440 struct hns3_rx_vtag_cfg rx_vcfg; 441 struct hns3_tx_vtag_cfg tx_vcfg; 442 }; 443 444 /* Request types for IPC. */ 445 enum hns3_mp_req_type { 446 HNS3_MP_REQ_START_RXTX = 1, 447 HNS3_MP_REQ_STOP_RXTX, 448 HNS3_MP_REQ_MAX 449 }; 450 451 /* Pameters for IPC. */ 452 struct hns3_mp_param { 453 enum hns3_mp_req_type type; 454 int port_id; 455 int result; 456 }; 457 458 /* Request timeout for IPC. */ 459 #define HNS3_MP_REQ_TIMEOUT_SEC 5 460 461 /* Key string for IPC. */ 462 #define HNS3_MP_NAME "net_hns3_mp" 463 464 struct hns3_pf { 465 struct hns3_adapter *adapter; 466 bool is_main_pf; 467 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 468 469 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 470 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 471 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 472 473 uint16_t mps; /* Max packet size */ 474 475 uint8_t tx_sch_mode; 476 uint8_t tc_max; /* max number of tc driver supported */ 477 uint8_t local_max_tc; /* max number of local tc */ 478 uint8_t pfc_max; 479 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 480 uint16_t pause_time; 481 bool support_fc_autoneg; /* support FC autonegotiate */ 482 483 uint16_t wanted_umv_size; 484 uint16_t max_umv_size; 485 uint16_t used_umv_size; 486 487 /* Statistics information for abnormal interrupt */ 488 struct hns3_err_msix_intr_stats abn_int_stats; 489 490 bool support_sfp_query; 491 492 struct hns3_vtag_cfg vtag_config; 493 struct hns3_port_base_vlan_config port_base_vlan_cfg; 494 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 495 496 struct hns3_fdir_info fdir; /* flow director info */ 497 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 498 }; 499 500 struct hns3_vf { 501 struct hns3_adapter *adapter; 502 }; 503 504 struct hns3_adapter { 505 struct hns3_hw hw; 506 507 /* Specific for PF or VF */ 508 bool is_vf; /* false - PF, true - VF */ 509 union { 510 struct hns3_pf pf; 511 struct hns3_vf vf; 512 }; 513 }; 514 515 #define HNS3_DEV_SUPPORT_DCB_B 0x0 516 517 #define hns3_dev_dcb_supported(hw) \ 518 hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B) 519 520 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 521 (&((struct hns3_adapter *)adapter)->hw) 522 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \ 523 ((struct hns3_adapter *)adapter) 524 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 525 (&((struct hns3_adapter *)adapter)->pf) 526 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \ 527 (&((struct hns3_adapter *)adapter)->vf) 528 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 529 container_of(hw, struct hns3_adapter, hw) 530 531 #define hns3_set_field(origin, mask, shift, val) \ 532 do { \ 533 (origin) &= (~(mask)); \ 534 (origin) |= ((val) << (shift)) & (mask); \ 535 } while (0) 536 #define hns3_get_field(origin, mask, shift) \ 537 (((origin) & (mask)) >> (shift)) 538 #define hns3_set_bit(origin, shift, val) \ 539 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 540 #define hns3_get_bit(origin, shift) \ 541 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 542 543 /* 544 * upper_32_bits - return bits 32-63 of a number 545 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 546 * the "right shift count >= width of type" warning when that quantity is 547 * 32-bits. 548 */ 549 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 550 551 /* lower_32_bits - return bits 0-31 of a number */ 552 #define lower_32_bits(n) ((uint32_t)(n)) 553 554 #define BIT(nr) (1UL << (nr)) 555 556 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 557 #define GENMASK(h, l) \ 558 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 559 560 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 561 #define rounddown(x, y) ((x) - ((x) % (y))) 562 563 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 564 565 #define max_t(type, x, y) ({ \ 566 type __max1 = (x); \ 567 type __max2 = (y); \ 568 __max1 > __max2 ? __max1 : __max2; }) 569 570 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 571 { 572 rte_write32(value, (volatile void *)((char *)base + reg)); 573 } 574 575 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 576 { 577 return rte_read32((volatile void *)((char *)base + reg)); 578 } 579 580 #define hns3_write_dev(a, reg, value) \ 581 hns3_write_reg((a)->io_base, (reg), (value)) 582 583 #define hns3_read_dev(a, reg) \ 584 hns3_read_reg((a)->io_base, (reg)) 585 586 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 587 588 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 589 do { \ 590 act = (actions) + (index); \ 591 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 592 (index)++; \ 593 act = actions + index; \ 594 } \ 595 } while (0) 596 597 #define MSEC_PER_SEC 1000L 598 #define USEC_PER_MSEC 1000L 599 600 static inline uint64_t 601 get_timeofday_ms(void) 602 { 603 struct timeval tv; 604 605 (void)gettimeofday(&tv, NULL); 606 607 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 608 } 609 610 static inline uint64_t 611 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 612 { 613 uint64_t res; 614 615 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 616 return res; 617 } 618 619 static inline void 620 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 621 { 622 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 623 } 624 625 static inline void 626 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 627 { 628 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 629 } 630 631 static inline int64_t 632 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 633 { 634 uint64_t mask = (1UL << nr); 635 636 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 637 } 638 639 int hns3_buffer_alloc(struct hns3_hw *hw); 640 int hns3_config_gro(struct hns3_hw *hw, bool en); 641 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, 642 enum rte_filter_type filter_type, 643 enum rte_filter_op filter_op, void *arg); 644 bool hns3_is_reset_pending(struct hns3_adapter *hns); 645 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 646 void hns3_update_link_status(struct hns3_hw *hw); 647 648 static inline bool 649 is_reset_pending(struct hns3_adapter *hns) 650 { 651 bool ret; 652 if (hns->is_vf) 653 ret = hns3vf_is_reset_pending(hns); 654 else 655 ret = hns3_is_reset_pending(hns); 656 return ret; 657 } 658 659 #endif /* _HNS3_ETHDEV_H_ */ 660