1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef HNS3_ETHDEV_H 6 #define HNS3_ETHDEV_H 7 8 #include <pthread.h> 9 #include <ethdev_driver.h> 10 #include <rte_byteorder.h> 11 #include <rte_io.h> 12 #include <rte_spinlock.h> 13 14 #include "hns3_cmd.h" 15 #include "hns3_mbx.h" 16 #include "hns3_rss.h" 17 #include "hns3_fdir.h" 18 #include "hns3_stats.h" 19 #include "hns3_tm.h" 20 #include "hns3_flow.h" 21 22 /* Vendor ID */ 23 #define PCI_VENDOR_ID_HUAWEI 0x19e5 24 25 /* Device IDs */ 26 #define HNS3_DEV_ID_GE 0xA220 27 #define HNS3_DEV_ID_25GE 0xA221 28 #define HNS3_DEV_ID_25GE_RDMA 0xA222 29 #define HNS3_DEV_ID_50GE_RDMA 0xA224 30 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 31 #define HNS3_DEV_ID_200G_RDMA 0xA228 32 #define HNS3_DEV_ID_100G_VF 0xA22E 33 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 34 35 /* PCI Config offsets */ 36 #define HNS3_PCI_REVISION_ID 0x08 37 #define HNS3_PCI_REVISION_ID_LEN 1 38 39 #define PCI_REVISION_ID_HIP08_B 0x21 40 #define PCI_REVISION_ID_HIP09_A 0x30 41 42 #define HNS3_PF_FUNC_ID 0 43 #define HNS3_1ST_VF_FUNC_ID 1 44 45 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 46 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 47 48 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 49 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 50 51 #define HNS3_UNLIMIT_PROMISC_MODE 0 52 #define HNS3_LIMIT_PROMISC_MODE 1 53 54 #define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0 55 #define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1 56 57 #define HNS3_UC_MACADDR_NUM 128 58 #define HNS3_VF_UC_MACADDR_NUM 48 59 #define HNS3_MC_MACADDR_NUM 128 60 61 #define HNS3_MAX_BD_SIZE 65535 62 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8 63 #define HNS3_MAX_TSO_BD_PER_PKT 63 64 #define HNS3_MAX_FRAME_LEN 9728 65 #define HNS3_DEFAULT_RX_BUF_LEN 2048 66 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) 67 #define HNS3_MAX_TSO_HDR_SIZE 512 68 #define HNS3_MAX_TSO_HDR_BD_NUM 3 69 #define HNS3_MAX_LRO_SIZE 64512 70 71 #define HNS3_ETH_OVERHEAD \ 72 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN * 2) 73 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 74 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 75 #define HNS3_DEFAULT_MTU 1500UL 76 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 77 #define HNS3_HIP08_MIN_TX_PKT_LEN 33 78 79 #define HNS3_BITS_PER_BYTE 8 80 81 #define HNS3_4_TCS 4 82 #define HNS3_8_TCS 8 83 84 #define HNS3_MAX_PF_NUM 8 85 #define HNS3_UMV_TBL_SIZE 3072 86 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 87 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 88 89 #define HNS3_PF_CFG_BLOCK_SIZE 32 90 #define HNS3_PF_CFG_DESC_NUM \ 91 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 92 93 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 94 95 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 96 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 97 98 #define HNS3_QUIT_RESET_CNT 10 99 #define HNS3_QUIT_RESET_DELAY_MS 100 100 101 #define HNS3_POLL_RESPONE_MS 1 102 103 #define HNS3_MAX_USER_PRIO 8 104 #define HNS3_PG_NUM 4 105 enum hns3_fc_mode { 106 HNS3_FC_NONE, 107 HNS3_FC_RX_PAUSE, 108 HNS3_FC_TX_PAUSE, 109 HNS3_FC_FULL, 110 HNS3_FC_DEFAULT 111 }; 112 113 #define HNS3_SCH_MODE_SP 0 114 #define HNS3_SCH_MODE_DWRR 1 115 struct hns3_pg_info { 116 uint8_t pg_id; 117 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 118 uint8_t tc_bit_map; 119 uint32_t bw_limit; 120 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 121 }; 122 123 struct hns3_tc_info { 124 uint8_t tc_id; 125 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 126 uint8_t pgid; 127 uint32_t bw_limit; 128 uint8_t up_to_tc_map; /* user priority mapping on the TC */ 129 }; 130 131 struct hns3_dcb_info { 132 uint8_t num_tc; 133 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 134 uint8_t pg_dwrr[HNS3_PG_NUM]; 135 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 136 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 137 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 138 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 139 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 140 }; 141 142 enum hns3_fc_status { 143 HNS3_FC_STATUS_NONE, 144 HNS3_FC_STATUS_MAC_PAUSE, 145 HNS3_FC_STATUS_PFC, 146 }; 147 148 struct hns3_tc_queue_info { 149 uint16_t tqp_offset; /* TQP offset from base TQP */ 150 uint16_t tqp_count; /* Total TQPs */ 151 uint8_t tc; /* TC index */ 152 bool enable; /* If this TC is enable or not */ 153 }; 154 155 struct hns3_cfg { 156 uint8_t tc_num; 157 uint16_t rss_size_max; 158 uint8_t phy_addr; 159 uint8_t media_type; 160 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 161 uint8_t default_speed; 162 uint32_t numa_node_map; 163 uint8_t speed_ability; 164 uint16_t umv_space; 165 }; 166 167 struct hns3_set_link_speed_cfg { 168 uint32_t speed; 169 uint8_t duplex : 1; 170 uint8_t autoneg : 1; 171 }; 172 173 /* mac media type */ 174 enum hns3_media_type { 175 HNS3_MEDIA_TYPE_UNKNOWN, 176 HNS3_MEDIA_TYPE_FIBER, 177 HNS3_MEDIA_TYPE_COPPER, 178 HNS3_MEDIA_TYPE_BACKPLANE, 179 HNS3_MEDIA_TYPE_NONE, 180 }; 181 182 #define HNS3_DEFAULT_QUERY 0 183 #define HNS3_ACTIVE_QUERY 1 184 185 struct hns3_mac { 186 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 187 uint8_t media_type; 188 uint8_t phy_addr; 189 uint8_t link_duplex : 1; /* RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ 190 uint8_t link_autoneg : 1; /* RTE_ETH_LINK_[AUTONEG/FIXED] */ 191 uint8_t link_status : 1; /* RTE_ETH_LINK_[DOWN/UP] */ 192 uint32_t link_speed; /* RTE_ETH_SPEED_NUM_ */ 193 /* 194 * Some firmware versions support only the SFP speed query. In addition 195 * to the SFP speed query, some firmware supports the query of the speed 196 * capability, auto-negotiation capability, and FEC mode, which can be 197 * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD. 198 * This field is used to record the SFP information query mode. 199 * Value range: 200 * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY 201 * 202 * - HNS3_DEFAULT_QUERY 203 * Speed obtained is from SFP. When the queried speed changes, the MAC 204 * speed needs to be reconfigured. 205 * 206 * - HNS3_ACTIVE_QUERY 207 * Speed obtained is from MAC. At this time, it is unnecessary for 208 * driver to reconfigured the MAC speed. In addition, more information, 209 * such as, the speed capability, auto-negotiation capability and FEC 210 * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD. 211 */ 212 uint8_t query_type; 213 uint32_t supported_speed; /* supported speed for current media type */ 214 uint32_t advertising; /* advertised capability in the local part */ 215 uint32_t lp_advertising; /* advertised capability in the link partner */ 216 uint8_t support_autoneg; 217 /* current supported fec modes. see HNS3_FIBER_FEC_XXX_BIT */ 218 uint32_t fec_capa; 219 }; 220 221 struct hns3_fake_queue_data { 222 void **rx_queues; /* Array of pointers to fake RX queues. */ 223 void **tx_queues; /* Array of pointers to fake TX queues. */ 224 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 225 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 226 }; 227 228 #define HNS3_PORT_BASE_VLAN_DISABLE 0 229 #define HNS3_PORT_BASE_VLAN_ENABLE 1 230 struct hns3_port_base_vlan_config { 231 uint16_t state; 232 uint16_t pvid; 233 }; 234 235 /* Primary process maintains driver state in main thread. 236 * 237 * +---------------+ 238 * | UNINITIALIZED |<-----------+ 239 * +---------------+ | 240 * |.eth_dev_init |.eth_dev_uninit 241 * V | 242 * +---------------+------------+ 243 * | INITIALIZED | 244 * +---------------+<-----------<---------------+ 245 * |.dev_configure | | 246 * V |failed | 247 * +---------------+------------+ | 248 * | CONFIGURING | | 249 * +---------------+----+ | 250 * |success | | 251 * | | +---------------+ 252 * | | | CLOSING | 253 * | | +---------------+ 254 * | | ^ 255 * V |.dev_configure | 256 * +---------------+----+ |.dev_close 257 * | CONFIGURED |----------------------------+ 258 * +---------------+<-----------+ 259 * |.dev_start | 260 * V | 261 * +---------------+ | 262 * | STARTING |------------^ 263 * +---------------+ failed | 264 * |success | 265 * | +---------------+ 266 * | | STOPPING | 267 * | +---------------+ 268 * | ^ 269 * V |.dev_stop 270 * +---------------+------------+ 271 * | STARTED | 272 * +---------------+ 273 */ 274 enum hns3_adapter_state { 275 HNS3_NIC_UNINITIALIZED = 0, 276 HNS3_NIC_INITIALIZED, 277 HNS3_NIC_CONFIGURING, 278 HNS3_NIC_CONFIGURED, 279 HNS3_NIC_STARTING, 280 HNS3_NIC_STARTED, 281 HNS3_NIC_STOPPING, 282 HNS3_NIC_CLOSING, 283 HNS3_NIC_CLOSED, 284 HNS3_NIC_REMOVED, 285 HNS3_NIC_NSTATES 286 }; 287 288 /* Reset various stages, execute in order */ 289 enum hns3_reset_stage { 290 /* Stop query services, stop transceiver, disable MAC */ 291 RESET_STAGE_DOWN, 292 /* Clear reset completion flags, disable send command */ 293 RESET_STAGE_PREWAIT, 294 /* Inform IMP to start resetting */ 295 RESET_STAGE_REQ_HW_RESET, 296 /* Waiting for hardware reset to complete */ 297 RESET_STAGE_WAIT, 298 /* Reinitialize hardware */ 299 RESET_STAGE_DEV_INIT, 300 /* Restore user settings and enable MAC */ 301 RESET_STAGE_RESTORE, 302 /* Restart query services, start transceiver */ 303 RESET_STAGE_DONE, 304 /* Not in reset state */ 305 RESET_STAGE_NONE, 306 }; 307 308 enum hns3_reset_level { 309 HNS3_FLR_RESET, /* A VF perform FLR reset */ 310 HNS3_VF_FUNC_RESET, /* A VF function reset */ 311 312 /* 313 * All VFs under a PF perform function reset. 314 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 315 * of the reset level and the one defined in kernel driver should be 316 * same. 317 */ 318 HNS3_VF_PF_FUNC_RESET = 2, 319 320 /* 321 * All VFs under a PF perform FLR reset. 322 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 323 * of the reset level and the one defined in kernel driver should be 324 * same. 325 * 326 * According to the protocol of PCIe, FLR to a PF resets the PF state as 327 * well as the SR-IOV extended capability including VF Enable which 328 * means that VFs no longer exist. 329 * 330 * In PF FLR, the register state of VF is not reliable, VF's driver 331 * should not access the registers of the VF device. 332 */ 333 HNS3_VF_FULL_RESET, 334 335 /* All VFs under the rootport perform a global or IMP reset */ 336 HNS3_VF_RESET, 337 338 /* 339 * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/ 340 * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and 341 * can not be changed. 342 */ 343 344 HNS3_FUNC_RESET = 5, /* A PF function reset */ 345 346 /* All PFs under the rootport perform a global reset */ 347 HNS3_GLOBAL_RESET, 348 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 349 HNS3_NONE_RESET, 350 HNS3_MAX_RESET 351 }; 352 353 enum hns3_wait_result { 354 HNS3_WAIT_UNKNOWN, 355 HNS3_WAIT_REQUEST, 356 HNS3_WAIT_SUCCESS, 357 HNS3_WAIT_TIMEOUT 358 }; 359 360 #define HNS3_RESET_SYNC_US 100000 361 362 struct hns3_reset_stats { 363 uint64_t request_cnt; /* Total request reset times */ 364 uint64_t global_cnt; /* Total GLOBAL reset times */ 365 uint64_t imp_cnt; /* Total IMP reset times */ 366 uint64_t exec_cnt; /* Total reset executive times */ 367 uint64_t success_cnt; /* Total reset successful times */ 368 uint64_t fail_cnt; /* Total reset failed times */ 369 uint64_t merge_cnt; /* Total merged in high reset times */ 370 }; 371 372 typedef bool (*check_completion_func)(struct hns3_hw *hw); 373 374 struct hns3_wait_data { 375 void *hns; 376 uint64_t end_ms; 377 uint64_t interval; 378 int16_t count; 379 enum hns3_wait_result result; 380 check_completion_func check_completion; 381 }; 382 383 struct hns3_reset_ops { 384 void (*reset_service)(void *arg); 385 int (*stop_service)(struct hns3_adapter *hns); 386 int (*prepare_reset)(struct hns3_adapter *hns); 387 int (*wait_hardware_ready)(struct hns3_adapter *hns); 388 int (*reinit_dev)(struct hns3_adapter *hns); 389 int (*restore_conf)(struct hns3_adapter *hns); 390 int (*start_service)(struct hns3_adapter *hns); 391 }; 392 393 enum hns3_schedule { 394 SCHEDULE_NONE, 395 SCHEDULE_PENDING, 396 SCHEDULE_REQUESTED, 397 SCHEDULE_DEFERRED, 398 }; 399 400 struct hns3_reset_data { 401 enum hns3_reset_stage stage; 402 RTE_ATOMIC(uint16_t) schedule; 403 /* Reset flag, covering the entire reset process */ 404 RTE_ATOMIC(uint16_t) resetting; 405 /* Used to disable sending cmds during reset */ 406 RTE_ATOMIC(uint16_t) disable_cmd; 407 /* The reset level being processed */ 408 enum hns3_reset_level level; 409 /* Reset level set, each bit represents a reset level */ 410 RTE_ATOMIC(uint64_t) pending; 411 /* Request reset level set, from interrupt or mailbox */ 412 RTE_ATOMIC(uint64_t) request; 413 int attempts; /* Reset failure retry */ 414 int retries; /* Timeout failure retry in reset_post */ 415 /* 416 * At the time of global or IMP reset, the command cannot be sent to 417 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 418 * reset process, so the mbuf is required to be released after the reset 419 * is completed.The mbuf_deferred_free is used to mark whether mbuf 420 * needs to be released. 421 */ 422 bool mbuf_deferred_free; 423 struct timeval start_time; 424 struct hns3_reset_stats stats; 425 const struct hns3_reset_ops *ops; 426 struct hns3_wait_data *wait_data; 427 }; 428 429 struct hns3_hw_ops { 430 int (*add_mc_mac_addr)(struct hns3_hw *hw, 431 struct rte_ether_addr *mac_addr); 432 int (*del_mc_mac_addr)(struct hns3_hw *hw, 433 struct rte_ether_addr *mac_addr); 434 int (*add_uc_mac_addr)(struct hns3_hw *hw, 435 struct rte_ether_addr *mac_addr); 436 int (*del_uc_mac_addr)(struct hns3_hw *hw, 437 struct rte_ether_addr *mac_addr); 438 int (*bind_ring_with_vector)(struct hns3_hw *hw, uint16_t vector_id, 439 bool en, enum hns3_ring_type queue_type, 440 uint16_t queue_id); 441 }; 442 443 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 444 #define HNS3_INTR_MAPPING_VEC_ALL 1 445 446 #define HNS3_INTR_COALESCE_GL_UINT_2US 0 447 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 448 449 #define HNS3_INTR_QL_NONE 0 450 451 struct hns3_queue_intr { 452 /* 453 * interrupt mapping mode. 454 * value range: 455 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL 456 * 457 * - HNS3_INTR_MAPPING_VEC_RSV_ONE 458 * For some versions of hardware network engine, because of the 459 * hardware constraint, we need implement clearing the mapping 460 * relationship configurations by binding all queues to the last 461 * interrupt vector and reserving the last interrupt vector. This 462 * method results in a decrease of the maximum queues when upper 463 * applications call the rte_eth_dev_configure API function to 464 * enable Rx interrupt. 465 * 466 * - HNS3_INTR_MAPPING_VEC_ALL 467 * PMD can map/unmmap all interrupt vectors with queues when 468 * Rx interrupt is enabled. 469 */ 470 uint8_t mapping_mode; 471 /* 472 * The unit of GL(gap limiter) configuration for interrupt coalesce of 473 * queue's interrupt. 474 * value range: 475 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US 476 */ 477 uint8_t gl_unit; 478 /* The max QL(quantity limiter) value */ 479 uint16_t int_ql_max; 480 }; 481 482 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 483 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 484 485 #define HNS3_PKTS_DROP_STATS_MODE1 0 486 #define HNS3_PKTS_DROP_STATS_MODE2 1 487 488 #define HNS3_RX_DMA_ADDR_ALIGN_128 128 489 #define HNS3_RX_DMA_ADDR_ALIGN_64 64 490 491 struct hns3_hw { 492 struct rte_eth_dev_data *data; 493 void *io_base; 494 uint8_t revision; /* PCI revision, low byte of class word */ 495 struct hns3_cmq cmq; 496 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 497 struct hns3_mac mac; 498 /* 499 * This flag indicates dev_set_link_down() API is called, and is cleared 500 * by dev_set_link_up() or dev_start(). 501 */ 502 bool set_link_down; 503 RTE_ATOMIC(unsigned int) secondary_cnt; /* Number of secondary processes init'd. */ 504 struct hns3_tqp_stats tqp_stats; 505 /* Include Mac stats | Rx stats | Tx stats */ 506 struct hns3_mac_stats mac_stats; 507 uint32_t mac_stats_reg_num; 508 struct hns3_rx_missed_stats imissed_stats; 509 uint64_t oerror_stats; 510 /* 511 * The lock is used to protect statistics update in stats APIs and 512 * periodic task. 513 */ 514 rte_spinlock_t stats_lock; 515 516 uint32_t fw_version; 517 uint16_t pf_vf_if_version; /* version of communication interface */ 518 519 uint16_t num_msi; 520 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 521 uint16_t tqps_num; /* num task queue pairs of this function */ 522 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ 523 uint16_t rss_size_max; /* HW defined max RSS task queue */ 524 uint16_t rx_buf_len; /* hold min hardware rx buf len */ 525 uint32_t mng_entry_num; /* number of manager table entry */ 526 uint32_t mac_entry_num; /* number of mac-vlan table entry */ 527 528 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 529 int mc_addrs_num; /* Multicast mac addresses number */ 530 531 /* The configuration info of RSS */ 532 struct hns3_rss_conf rss_info; 533 uint16_t rss_ind_tbl_size; 534 uint16_t rss_key_size; 535 536 uint8_t num_tc; /* Total number of enabled TCs */ 537 uint8_t hw_tc_map; 538 enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */ 539 struct hns3_dcb_info dcb_info; 540 enum hns3_fc_status current_fc_status; /* current flow control status */ 541 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 542 uint16_t used_rx_queues; 543 uint16_t used_tx_queues; 544 545 /* Config max queue numbers between rx and tx queues from user */ 546 uint16_t cfg_max_queues; 547 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 548 uint16_t alloc_rss_size; /* RX queue number per TC */ 549 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 550 551 uint32_t capability; 552 uint32_t max_tm_rate; 553 /* 554 * The minimum length of the packet supported by hardware in the Tx 555 * direction. 556 */ 557 uint8_t min_tx_pkt_len; 558 /* 559 * The required alignment of the DMA address of the RX buffer. 560 * See HNS3_RX_DMA_ADDR_ALIGN_XXX for available values. 561 */ 562 uint16_t rx_dma_addr_align; 563 564 struct hns3_queue_intr intr; 565 /* 566 * tso mode. 567 * value range: 568 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 569 * 570 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 571 * In this mode, because of the hardware constraint, network driver 572 * software need erase the L4 len value of the TCP pseudo header 573 * and recalculate the TCP pseudo header checksum of packets that 574 * need TSO. 575 * 576 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 577 * In this mode, hardware support recalculate the TCP pseudo header 578 * checksum of packets that need TSO, so network driver software 579 * not need to recalculate it. 580 */ 581 uint8_t tso_mode; 582 /* 583 * vlan mode. 584 * value range: 585 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHIFT_AND_DISCARD_MODE 586 * 587 * - HNS3_SW_SHIFT_AND_DISCARD_MODE 588 * For some versions of hardware network engine, because of the 589 * hardware limitation, PMD needs to detect the PVID status 590 * to work with hardware to implement PVID-related functions. 591 * For example, driver need discard the stripped PVID tag to ensure 592 * the PVID will not report to mbuf and shift the inserted VLAN tag 593 * to avoid port based VLAN covering it. 594 * 595 * - HNS3_HW_SHIT_AND_DISCARD_MODE 596 * PMD does not need to process PVID-related functions in 597 * I/O process, Hardware will adjust the sequence between port based 598 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by 599 * PVID will be invisible to driver. And in this mode, hns3 is able 600 * to send a multi-layer VLAN packets when hw VLAN insert offload 601 * is enabled. 602 */ 603 uint8_t vlan_mode; 604 /* 605 * promisc mode. 606 * value range: 607 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE 608 * 609 * - HNS3_UNLIMIT_PROMISC_MODE 610 * In this mode, TX unicast promisc will be configured when promisc 611 * is set, driver can receive all the ingress and outgoing traffic. 612 * In the words, all the ingress packets, all the packets sent from 613 * the PF and other VFs on the same physical port. 614 * 615 * - HNS3_LIMIT_PROMISC_MODE 616 * In this mode, TX unicast promisc is shutdown when promisc mode 617 * is set. So, driver will only receive all the ingress traffic. 618 * The packets sent from the PF and other VFs on the same physical 619 * port won't be copied to the function which has set promisc mode. 620 */ 621 uint8_t promisc_mode; 622 623 /* 624 * drop_stats_mode mode. 625 * value range: 626 * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 627 * 628 * - HNS3_PKTS_DROP_STATS_MODE1 629 * This mode for kunpeng920. In this mode, port level imissed stats 630 * is supported. It only includes RPU drop stats. 631 * 632 * - HNS3_PKTS_DROP_STATS_MODE2 633 * This mode for kunpeng930. In this mode, imissed stats and oerrors 634 * stats is supported. Function level imissed stats is supported. It 635 * includes RPU drop stats in VF, and includes both RPU drop stats 636 * and SSU drop stats in PF. Oerror stats is also supported in PF. 637 */ 638 uint8_t drop_stats_mode; 639 640 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 641 /* 642 * udp checksum mode. 643 * value range: 644 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE 645 * 646 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE 647 * In this mode, HW can not do checksum for special UDP port like 648 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel 649 * packets without the RTE_MBUF_F_TX_TUNEL_MASK in the mbuf. So, PMD need 650 * do the checksum for these packets to avoid a checksum error. 651 * 652 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE 653 * In this mode, HW does not have the preceding problems and can 654 * directly calculate the checksum of these UDP packets. 655 */ 656 uint8_t udp_cksum_mode; 657 658 struct hns3_port_base_vlan_config port_base_vlan_cfg; 659 660 pthread_mutex_t flows_lock; /* rte_flow ops lock */ 661 struct hns3_fdir_rule_list flow_fdir_list; /* flow fdir rule list */ 662 struct hns3_rss_filter_list flow_rss_list; /* flow RSS rule list */ 663 struct hns3_flow_mem_list flow_list; 664 665 struct hns3_hw_ops ops; 666 667 /* 668 * PMD setup and configuration is not thread safe. Since it is not 669 * performance sensitive, it is better to guarantee thread-safety 670 * and add device level lock. Adapter control operations which 671 * change its state should acquire the lock. 672 */ 673 rte_spinlock_t lock; 674 enum hns3_adapter_state adapter_state; 675 struct hns3_reset_data reset; 676 }; 677 678 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 679 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 680 681 /* vlan entry information. */ 682 struct hns3_user_vlan_table { 683 LIST_ENTRY(hns3_user_vlan_table) next; 684 bool hd_tbl_status; 685 uint16_t vlan_id; 686 }; 687 688 /* Vlan tag configuration for RX direction */ 689 struct hns3_rx_vtag_cfg { 690 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 691 bool strip_tag1_en; /* Whether strip inner vlan tag */ 692 bool strip_tag2_en; /* Whether strip outer vlan tag */ 693 /* 694 * If strip_tag_en is enabled, this bit decide whether to map the vlan 695 * tag to descriptor. 696 */ 697 bool strip_tag1_discard_en; 698 bool strip_tag2_discard_en; 699 /* 700 * If this bit is enabled, only map inner/outer priority to descriptor 701 * and the vlan tag is always 0. 702 */ 703 bool vlan1_vlan_prionly; 704 bool vlan2_vlan_prionly; 705 }; 706 707 /* Vlan tag configuration for TX direction */ 708 struct hns3_tx_vtag_cfg { 709 bool accept_tag1; /* Whether accept tag1 packet from host */ 710 bool accept_untag1; /* Whether accept untag1 packet from host */ 711 bool accept_tag2; 712 bool accept_untag2; 713 bool insert_tag1_en; /* Whether insert outer vlan tag */ 714 bool insert_tag2_en; /* Whether insert inner vlan tag */ 715 /* 716 * In shift mode, hw will shift the sequence of port based VLAN and 717 * BD VLAN. 718 */ 719 bool tag_shift_mode_en; /* hw shift vlan tag automatically */ 720 uint16_t default_tag1; /* The default outer vlan tag to insert */ 721 uint16_t default_tag2; /* The default inner vlan tag to insert */ 722 }; 723 724 struct hns3_vtag_cfg { 725 struct hns3_rx_vtag_cfg rx_vcfg; 726 struct hns3_tx_vtag_cfg tx_vcfg; 727 }; 728 729 /* Request types for IPC. */ 730 enum hns3_mp_req_type { 731 HNS3_MP_REQ_START_RXTX = 1, 732 HNS3_MP_REQ_STOP_RXTX, 733 HNS3_MP_REQ_START_TX, 734 HNS3_MP_REQ_STOP_TX, 735 HNS3_MP_REQ_MAX 736 }; 737 738 /* Parameters for IPC. */ 739 struct hns3_mp_param { 740 enum hns3_mp_req_type type; 741 int port_id; 742 int result; 743 }; 744 745 /* Request timeout for IPC. */ 746 #define HNS3_MP_REQ_TIMEOUT_SEC 5 747 748 /* Key string for IPC. */ 749 #define HNS3_MP_NAME "net_hns3_mp" 750 751 #define HNS3_L2TBL_NUM 4 752 #define HNS3_L3TBL_NUM 16 753 #define HNS3_L4TBL_NUM 16 754 #define HNS3_OL2TBL_NUM 4 755 #define HNS3_OL3TBL_NUM 16 756 #define HNS3_OL4TBL_NUM 16 757 #define HNS3_PTYPE_NUM 256 758 759 struct hns3_ptype_table { 760 /* 761 * The next fields used to calc packet-type by the 762 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor. 763 */ 764 uint32_t l3table[HNS3_L3TBL_NUM]; 765 uint32_t l4table[HNS3_L4TBL_NUM]; 766 uint32_t inner_l3table[HNS3_L3TBL_NUM]; 767 uint32_t inner_l4table[HNS3_L4TBL_NUM]; 768 uint32_t ol3table[HNS3_OL3TBL_NUM]; 769 uint32_t ol4table[HNS3_OL4TBL_NUM]; 770 771 /* 772 * The next field used to calc packet-type by the PTYPE from the Rx 773 * descriptor, it functions only when firmware report the capability of 774 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it. 775 */ 776 alignas(RTE_CACHE_LINE_SIZE) uint32_t ptype[HNS3_PTYPE_NUM]; 777 }; 778 779 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0 780 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1 781 782 struct hns3_pf { 783 struct hns3_adapter *adapter; 784 bool is_main_pf; 785 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 786 787 /* 788 * tqp_config mode 789 * tqp_config_mode value range: 790 * HNS3_FIXED_MAX_TQP_NUM_MODE, 791 * HNS3_FLEX_MAX_TQP_NUM_MODE 792 * 793 * - HNS3_FIXED_MAX_TQP_NUM_MODE 794 * There is a limitation on the number of pf interrupts available for 795 * on some versions of network engines. In this case, the maximum 796 * queue number of pf can not be greater than the interrupt number, 797 * such as pf of network engine with revision_id 0x21. So the maximum 798 * number of queues must be fixed. 799 * 800 * - HNS3_FLEX_MAX_TQP_NUM_MODE 801 * In this mode, the maximum queue number of pf has not any constraint 802 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 803 * in the config file. Users can modify the macro according to their 804 * own application scenarios, which is more flexible to use. 805 */ 806 uint8_t tqp_config_mode; 807 808 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 809 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 810 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 811 812 uint16_t mps; /* Max packet size */ 813 814 uint8_t tx_sch_mode; 815 uint8_t tc_max; /* max number of tc driver supported */ 816 uint8_t local_max_tc; /* max number of local tc */ 817 uint8_t pfc_max; 818 uint16_t pause_time; 819 bool support_fc_autoneg; /* support FC autonegotiate */ 820 bool support_multi_tc_pause; 821 822 uint16_t wanted_umv_size; 823 uint16_t max_umv_size; 824 uint16_t used_umv_size; 825 826 bool support_sfp_query; 827 uint32_t fec_mode; /* current FEC mode for ethdev */ 828 829 bool ptp_enable; 830 831 /* Stores timestamp of last received packet on dev */ 832 uint64_t rx_timestamp; 833 834 struct hns3_vtag_cfg vtag_config; 835 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 836 837 struct hns3_fdir_info fdir; /* flow director info */ 838 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 839 840 struct hns3_tm_conf tm_conf; 841 }; 842 843 enum { 844 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED, 845 HNS3_PF_PUSH_LSC_CAP_SUPPORTED, 846 HNS3_PF_PUSH_LSC_CAP_UNKNOWN 847 }; 848 849 struct hns3_vf { 850 struct hns3_adapter *adapter; 851 852 /* Whether PF support push link status change to VF */ 853 RTE_ATOMIC(uint16_t) pf_push_lsc_cap; 854 855 /* 856 * If PF support push link status change, VF still need send request to 857 * get link status in some cases (such as reset recover stage), so use 858 * the req_link_info_cnt to control max request count. 859 */ 860 uint16_t req_link_info_cnt; 861 862 RTE_ATOMIC(uint16_t) poll_job_started; /* whether poll job is started */ 863 }; 864 865 struct hns3_adapter { 866 struct hns3_hw hw; 867 868 /* Specific for PF or VF */ 869 bool is_vf; /* false - PF, true - VF */ 870 union { 871 struct hns3_pf pf; 872 struct hns3_vf vf; 873 }; 874 875 uint32_t rx_func_hint; 876 uint32_t tx_func_hint; 877 878 uint64_t dev_caps_mask; 879 uint16_t mbx_time_limit_ms; /* wait time for mbx message */ 880 881 alignas(RTE_CACHE_LINE_SIZE) struct hns3_ptype_table ptype_tbl; 882 }; 883 884 enum hns3_dev_cap { 885 HNS3_DEV_SUPPORT_DCB_B, 886 HNS3_DEV_SUPPORT_COPPER_B, 887 HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B, 888 HNS3_DEV_SUPPORT_PTP_B, 889 HNS3_DEV_SUPPORT_TX_PUSH_B, 890 HNS3_DEV_SUPPORT_INDEP_TXRX_B, 891 HNS3_DEV_SUPPORT_STASH_B, 892 HNS3_DEV_SUPPORT_SIMPLE_BD_B, 893 HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 894 HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 895 HNS3_DEV_SUPPORT_RAS_IMP_B, 896 HNS3_DEV_SUPPORT_TM_B, 897 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 898 HNS3_DEV_SUPPORT_FC_AUTO_B, 899 HNS3_DEV_SUPPORT_GRO_B, 900 }; 901 902 #define hns3_dev_get_support(hw, _name) \ 903 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_##_name##_B) 904 905 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 906 (&((struct hns3_adapter *)(adapter))->hw) 907 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 908 (&((struct hns3_adapter *)(adapter))->pf) 909 #define HNS3_DEV_PRIVATE_TO_VF(adapter) \ 910 (&((struct hns3_adapter *)(adapter))->vf) 911 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 912 container_of(hw, struct hns3_adapter, hw) 913 914 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw) 915 { 916 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 917 return &adapter->pf; 918 } 919 920 static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw) 921 { 922 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 923 return &adapter->vf; 924 } 925 926 #define hns3_set_field(origin, mask, shift, val) \ 927 do { \ 928 (origin) &= (~(mask)); \ 929 (origin) |= ((val) << (shift)) & (mask); \ 930 } while (0) 931 #define hns3_get_field(origin, mask, shift) \ 932 (((origin) & (mask)) >> (shift)) 933 #define hns3_set_bit(origin, shift, val) \ 934 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 935 #define hns3_get_bit(origin, shift) \ 936 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 937 938 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) 939 940 /* 941 * upper_32_bits - return bits 32-63 of a number 942 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 943 * the "right shift count >= width of type" warning when that quantity is 944 * 32-bits. 945 */ 946 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 947 948 /* lower_32_bits - return bits 0-31 of a number */ 949 #define lower_32_bits(n) ((uint32_t)(n)) 950 951 #define BIT(nr) (1UL << (nr)) 952 953 #define BIT_ULL(x) (1ULL << (x)) 954 955 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 956 #define GENMASK(h, l) \ 957 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 958 959 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 960 #define rounddown(x, y) ((x) - ((x) % (y))) 961 962 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 963 964 /* 965 * Because hardware always access register in little-endian mode based on hns3 966 * network engine, so driver should also call rte_cpu_to_le_32 to convert data 967 * in little-endian mode before writing register and call rte_le_to_cpu_32 to 968 * convert data after reading from register. 969 * 970 * Here the driver encapsulates the data conversion operation in the register 971 * read/write operation function as below: 972 * hns3_write_reg 973 * hns3_write_reg_opt 974 * hns3_read_reg 975 * Therefore, when calling these functions, conversion is not required again. 976 */ 977 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 978 { 979 rte_write32(rte_cpu_to_le_32(value), 980 (volatile void *)((char *)base + reg)); 981 } 982 983 /* 984 * The optimized function for writing registers reduces one address addition 985 * calculation, it was used in the '.rx_pkt_burst' and '.tx_pkt_burst' ops 986 * implementation function. 987 */ 988 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) 989 { 990 rte_write32(rte_cpu_to_le_32(value), addr); 991 } 992 993 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 994 { 995 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); 996 return rte_le_to_cpu_32(read_val); 997 } 998 999 #define hns3_write_dev(a, reg, value) \ 1000 hns3_write_reg((a)->io_base, (reg), (value)) 1001 1002 #define hns3_read_dev(a, reg) \ 1003 hns3_read_reg((a)->io_base, (reg)) 1004 1005 static inline uint64_t 1006 hns3_atomic_test_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr) 1007 { 1008 uint64_t res; 1009 1010 res = (rte_atomic_load_explicit(addr, rte_memory_order_relaxed) & (1UL << nr)) != 0; 1011 return res; 1012 } 1013 1014 static inline void 1015 hns3_atomic_set_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr) 1016 { 1017 rte_atomic_fetch_or_explicit(addr, (1UL << nr), rte_memory_order_relaxed); 1018 } 1019 1020 static inline void 1021 hns3_atomic_clear_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr) 1022 { 1023 rte_atomic_fetch_and_explicit(addr, ~(1UL << nr), rte_memory_order_relaxed); 1024 } 1025 1026 static inline uint64_t 1027 hns3_test_and_clear_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr) 1028 { 1029 uint64_t mask = (1UL << nr); 1030 1031 return rte_atomic_fetch_and_explicit(addr, ~mask, rte_memory_order_relaxed) & mask; 1032 } 1033 1034 int 1035 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); 1036 uint32_t hns3_get_speed_capa(struct hns3_hw *hw); 1037 1038 int hns3_buffer_alloc(struct hns3_hw *hw); 1039 bool hns3_is_reset_pending(struct hns3_adapter *hns); 1040 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 1041 void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); 1042 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 1043 uint32_t link_speed, uint8_t link_duplex); 1044 void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); 1045 void hns3_clear_reset_event(struct hns3_hw *hw); 1046 void hns3vf_clear_reset_event(struct hns3_hw *hw); 1047 1048 const char *hns3_get_media_type_name(uint8_t media_type); 1049 1050 static inline bool 1051 is_reset_pending(struct hns3_adapter *hns) 1052 { 1053 bool ret; 1054 if (hns->is_vf) 1055 ret = hns3vf_is_reset_pending(hns); 1056 else 1057 ret = hns3_is_reset_pending(hns); 1058 return ret; 1059 } 1060 1061 static inline void 1062 hns3_clear_reset_status(struct hns3_hw *hw) 1063 { 1064 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1065 1066 if (hns->is_vf) 1067 hns3vf_clear_reset_event(hw); 1068 else 1069 hns3_clear_reset_event(hw); 1070 } 1071 1072 #endif /* HNS3_ETHDEV_H */ 1073