1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <ethdev_driver.h> 10 #include <rte_byteorder.h> 11 #include <rte_io.h> 12 #include <rte_spinlock.h> 13 14 #include "hns3_cmd.h" 15 #include "hns3_mbx.h" 16 #include "hns3_rss.h" 17 #include "hns3_fdir.h" 18 #include "hns3_stats.h" 19 #include "hns3_tm.h" 20 21 /* Vendor ID */ 22 #define PCI_VENDOR_ID_HUAWEI 0x19e5 23 24 /* Device IDs */ 25 #define HNS3_DEV_ID_GE 0xA220 26 #define HNS3_DEV_ID_25GE 0xA221 27 #define HNS3_DEV_ID_25GE_RDMA 0xA222 28 #define HNS3_DEV_ID_50GE_RDMA 0xA224 29 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 30 #define HNS3_DEV_ID_200G_RDMA 0xA228 31 #define HNS3_DEV_ID_100G_VF 0xA22E 32 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 33 34 /* PCI Config offsets */ 35 #define HNS3_PCI_REVISION_ID 0x08 36 #define HNS3_PCI_REVISION_ID_LEN 1 37 38 #define PCI_REVISION_ID_HIP08_B 0x21 39 #define PCI_REVISION_ID_HIP09_A 0x30 40 41 #define HNS3_PF_FUNC_ID 0 42 #define HNS3_1ST_VF_FUNC_ID 1 43 44 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 45 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 46 47 #define HNS3_UNLIMIT_PROMISC_MODE 0 48 #define HNS3_LIMIT_PROMISC_MODE 1 49 50 #define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0 51 #define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1 52 53 #define HNS3_UC_MACADDR_NUM 128 54 #define HNS3_VF_UC_MACADDR_NUM 48 55 #define HNS3_MC_MACADDR_NUM 128 56 57 #define HNS3_MAX_BD_SIZE 65535 58 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8 59 #define HNS3_MAX_TSO_BD_PER_PKT 63 60 #define HNS3_MAX_FRAME_LEN 9728 61 #define HNS3_VLAN_TAG_SIZE 4 62 #define HNS3_DEFAULT_RX_BUF_LEN 2048 63 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) 64 #define HNS3_MAX_TSO_HDR_SIZE 512 65 #define HNS3_MAX_TSO_HDR_BD_NUM 3 66 #define HNS3_MAX_LRO_SIZE 64512 67 68 #define HNS3_ETH_OVERHEAD \ 69 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 70 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 71 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 72 #define HNS3_DEFAULT_MTU 1500UL 73 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 74 #define HNS3_HIP08_MIN_TX_PKT_LEN 33 75 #define HNS3_HIP09_MIN_TX_PKT_LEN 9 76 77 #define HNS3_BITS_PER_BYTE 8 78 79 #define HNS3_4_TCS 4 80 #define HNS3_8_TCS 8 81 82 #define HNS3_MAX_PF_NUM 8 83 #define HNS3_UMV_TBL_SIZE 3072 84 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 85 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 86 87 #define HNS3_PF_CFG_BLOCK_SIZE 32 88 #define HNS3_PF_CFG_DESC_NUM \ 89 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 90 91 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 92 93 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 94 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 95 96 #define HNS3_QUIT_RESET_CNT 10 97 #define HNS3_QUIT_RESET_DELAY_MS 100 98 99 #define HNS3_POLL_RESPONE_MS 1 100 101 #define HNS3_MAX_USER_PRIO 8 102 #define HNS3_PG_NUM 4 103 enum hns3_fc_mode { 104 HNS3_FC_NONE, 105 HNS3_FC_RX_PAUSE, 106 HNS3_FC_TX_PAUSE, 107 HNS3_FC_FULL, 108 HNS3_FC_DEFAULT 109 }; 110 111 #define HNS3_SCH_MODE_SP 0 112 #define HNS3_SCH_MODE_DWRR 1 113 struct hns3_pg_info { 114 uint8_t pg_id; 115 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 116 uint8_t tc_bit_map; 117 uint32_t bw_limit; 118 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 119 }; 120 121 struct hns3_tc_info { 122 uint8_t tc_id; 123 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 124 uint8_t pgid; 125 uint32_t bw_limit; 126 uint8_t up_to_tc_map; /* user priority maping on the TC */ 127 }; 128 129 struct hns3_dcb_info { 130 uint8_t num_tc; 131 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 132 uint8_t pg_dwrr[HNS3_PG_NUM]; 133 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 134 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 135 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 136 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 137 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 138 }; 139 140 enum hns3_fc_status { 141 HNS3_FC_STATUS_NONE, 142 HNS3_FC_STATUS_MAC_PAUSE, 143 HNS3_FC_STATUS_PFC, 144 }; 145 146 struct hns3_tc_queue_info { 147 uint16_t tqp_offset; /* TQP offset from base TQP */ 148 uint16_t tqp_count; /* Total TQPs */ 149 uint8_t tc; /* TC index */ 150 bool enable; /* If this TC is enable or not */ 151 }; 152 153 struct hns3_cfg { 154 uint8_t vmdq_vport_num; 155 uint8_t tc_num; 156 uint16_t tqp_desc_num; 157 uint16_t rx_buf_len; 158 uint16_t rss_size_max; 159 uint8_t phy_addr; 160 uint8_t media_type; 161 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 162 uint8_t default_speed; 163 uint32_t numa_node_map; 164 uint8_t speed_ability; 165 uint16_t umv_space; 166 }; 167 168 struct hns3_set_link_speed_cfg { 169 uint32_t speed; 170 uint8_t duplex : 1; 171 uint8_t autoneg : 1; 172 }; 173 174 /* mac media type */ 175 enum hns3_media_type { 176 HNS3_MEDIA_TYPE_UNKNOWN, 177 HNS3_MEDIA_TYPE_FIBER, 178 HNS3_MEDIA_TYPE_COPPER, 179 HNS3_MEDIA_TYPE_BACKPLANE, 180 HNS3_MEDIA_TYPE_NONE, 181 }; 182 183 #define HNS3_DEFAULT_QUERY 0 184 #define HNS3_ACTIVE_QUERY 1 185 186 struct hns3_mac { 187 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 188 bool default_addr_setted; /* whether default addr(mac_addr) is set */ 189 uint8_t media_type; 190 uint8_t phy_addr; 191 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 192 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 193 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 194 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 195 /* 196 * Some firmware versions support only the SFP speed query. In addition 197 * to the SFP speed query, some firmware supports the query of the speed 198 * capability, auto-negotiation capability, and FEC mode, which can be 199 * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD. 200 * This field is used to record the SFP information query mode. 201 * Value range: 202 * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY 203 * 204 * - HNS3_DEFAULT_QUERY 205 * Speed obtained is from SFP. When the queried speed changes, the MAC 206 * speed needs to be reconfigured. 207 * 208 * - HNS3_ACTIVE_QUERY 209 * Speed obtained is from MAC. At this time, it is unnecessary for 210 * driver to reconfigured the MAC speed. In addition, more information, 211 * such as, the speed capability, auto-negotiation capability and FEC 212 * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD. 213 */ 214 uint8_t query_type; 215 uint32_t supported_speed; /* supported speed for current media type */ 216 uint32_t advertising; /* advertised capability in the local part */ 217 uint32_t lp_advertising; /* advertised capability in the link partner */ 218 uint8_t support_autoneg; 219 }; 220 221 struct hns3_fake_queue_data { 222 void **rx_queues; /* Array of pointers to fake RX queues. */ 223 void **tx_queues; /* Array of pointers to fake TX queues. */ 224 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 225 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 226 }; 227 228 #define HNS3_PORT_BASE_VLAN_DISABLE 0 229 #define HNS3_PORT_BASE_VLAN_ENABLE 1 230 struct hns3_port_base_vlan_config { 231 uint16_t state; 232 uint16_t pvid; 233 }; 234 235 /* Primary process maintains driver state in main thread. 236 * 237 * +---------------+ 238 * | UNINITIALIZED |<-----------+ 239 * +---------------+ | 240 * |.eth_dev_init |.eth_dev_uninit 241 * V | 242 * +---------------+------------+ 243 * | INITIALIZED | 244 * +---------------+<-----------<---------------+ 245 * |.dev_configure | | 246 * V |failed | 247 * +---------------+------------+ | 248 * | CONFIGURING | | 249 * +---------------+----+ | 250 * |success | | 251 * | | +---------------+ 252 * | | | CLOSING | 253 * | | +---------------+ 254 * | | ^ 255 * V |.dev_configure | 256 * +---------------+----+ |.dev_close 257 * | CONFIGURED |----------------------------+ 258 * +---------------+<-----------+ 259 * |.dev_start | 260 * V | 261 * +---------------+ | 262 * | STARTING |------------^ 263 * +---------------+ failed | 264 * |success | 265 * | +---------------+ 266 * | | STOPPING | 267 * | +---------------+ 268 * | ^ 269 * V |.dev_stop 270 * +---------------+------------+ 271 * | STARTED | 272 * +---------------+ 273 */ 274 enum hns3_adapter_state { 275 HNS3_NIC_UNINITIALIZED = 0, 276 HNS3_NIC_INITIALIZED, 277 HNS3_NIC_CONFIGURING, 278 HNS3_NIC_CONFIGURED, 279 HNS3_NIC_STARTING, 280 HNS3_NIC_STARTED, 281 HNS3_NIC_STOPPING, 282 HNS3_NIC_CLOSING, 283 HNS3_NIC_CLOSED, 284 HNS3_NIC_REMOVED, 285 HNS3_NIC_NSTATES 286 }; 287 288 /* Reset various stages, execute in order */ 289 enum hns3_reset_stage { 290 /* Stop query services, stop transceiver, disable MAC */ 291 RESET_STAGE_DOWN, 292 /* Clear reset completion flags, disable send command */ 293 RESET_STAGE_PREWAIT, 294 /* Inform IMP to start resetting */ 295 RESET_STAGE_REQ_HW_RESET, 296 /* Waiting for hardware reset to complete */ 297 RESET_STAGE_WAIT, 298 /* Reinitialize hardware */ 299 RESET_STAGE_DEV_INIT, 300 /* Restore user settings and enable MAC */ 301 RESET_STAGE_RESTORE, 302 /* Restart query services, start transceiver */ 303 RESET_STAGE_DONE, 304 /* Not in reset state */ 305 RESET_STAGE_NONE, 306 }; 307 308 enum hns3_reset_level { 309 HNS3_FLR_RESET, /* A VF perform FLR reset */ 310 HNS3_VF_FUNC_RESET, /* A VF function reset */ 311 312 /* 313 * All VFs under a PF perform function reset. 314 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 315 * of the reset level and the one defined in kernel driver should be 316 * same. 317 */ 318 HNS3_VF_PF_FUNC_RESET = 2, 319 320 /* 321 * All VFs under a PF perform FLR reset. 322 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 323 * of the reset level and the one defined in kernel driver should be 324 * same. 325 * 326 * According to the protocol of PCIe, FLR to a PF resets the PF state as 327 * well as the SR-IOV extended capability including VF Enable which 328 * means that VFs no longer exist. 329 * 330 * In PF FLR, the register state of VF is not reliable, VF's driver 331 * should not access the registers of the VF device. 332 */ 333 HNS3_VF_FULL_RESET, 334 335 /* All VFs under the rootport perform a global or IMP reset */ 336 HNS3_VF_RESET, 337 338 /* 339 * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/ 340 * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and 341 * can not be changed. 342 */ 343 344 HNS3_FUNC_RESET = 5, /* A PF function reset */ 345 346 /* All PFs under the rootport perform a global reset */ 347 HNS3_GLOBAL_RESET, 348 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 349 HNS3_NONE_RESET, 350 HNS3_MAX_RESET 351 }; 352 353 enum hns3_wait_result { 354 HNS3_WAIT_UNKNOWN, 355 HNS3_WAIT_REQUEST, 356 HNS3_WAIT_SUCCESS, 357 HNS3_WAIT_TIMEOUT 358 }; 359 360 #define HNS3_RESET_SYNC_US 100000 361 362 struct hns3_reset_stats { 363 uint64_t request_cnt; /* Total request reset times */ 364 uint64_t global_cnt; /* Total GLOBAL reset times */ 365 uint64_t imp_cnt; /* Total IMP reset times */ 366 uint64_t exec_cnt; /* Total reset executive times */ 367 uint64_t success_cnt; /* Total reset successful times */ 368 uint64_t fail_cnt; /* Total reset failed times */ 369 uint64_t merge_cnt; /* Total merged in high reset times */ 370 }; 371 372 typedef bool (*check_completion_func)(struct hns3_hw *hw); 373 374 struct hns3_wait_data { 375 void *hns; 376 uint64_t end_ms; 377 uint64_t interval; 378 int16_t count; 379 enum hns3_wait_result result; 380 check_completion_func check_completion; 381 }; 382 383 struct hns3_reset_ops { 384 void (*reset_service)(void *arg); 385 int (*stop_service)(struct hns3_adapter *hns); 386 int (*prepare_reset)(struct hns3_adapter *hns); 387 int (*wait_hardware_ready)(struct hns3_adapter *hns); 388 int (*reinit_dev)(struct hns3_adapter *hns); 389 int (*restore_conf)(struct hns3_adapter *hns); 390 int (*start_service)(struct hns3_adapter *hns); 391 }; 392 393 enum hns3_schedule { 394 SCHEDULE_NONE, 395 SCHEDULE_PENDING, 396 SCHEDULE_REQUESTED, 397 SCHEDULE_DEFERRED, 398 }; 399 400 struct hns3_reset_data { 401 enum hns3_reset_stage stage; 402 uint16_t schedule; 403 /* Reset flag, covering the entire reset process */ 404 uint16_t resetting; 405 /* Used to disable sending cmds during reset */ 406 uint16_t disable_cmd; 407 /* The reset level being processed */ 408 enum hns3_reset_level level; 409 /* Reset level set, each bit represents a reset level */ 410 uint64_t pending; 411 /* Request reset level set, from interrupt or mailbox */ 412 uint64_t request; 413 int attempts; /* Reset failure retry */ 414 int retries; /* Timeout failure retry in reset_post */ 415 /* 416 * At the time of global or IMP reset, the command cannot be sent to 417 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 418 * reset process, so the mbuf is required to be released after the reset 419 * is completed.The mbuf_deferred_free is used to mark whether mbuf 420 * needs to be released. 421 */ 422 bool mbuf_deferred_free; 423 struct timeval start_time; 424 struct hns3_reset_stats stats; 425 const struct hns3_reset_ops *ops; 426 struct hns3_wait_data *wait_data; 427 }; 428 429 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 430 #define HNS3_INTR_MAPPING_VEC_ALL 1 431 432 #define HNS3_INTR_COALESCE_GL_UINT_2US 0 433 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 434 435 #define HNS3_INTR_QL_NONE 0 436 437 struct hns3_queue_intr { 438 /* 439 * interrupt mapping mode. 440 * value range: 441 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL 442 * 443 * - HNS3_INTR_MAPPING_VEC_RSV_ONE 444 * For some versions of hardware network engine, because of the 445 * hardware constraint, we need implement clearing the mapping 446 * relationship configurations by binding all queues to the last 447 * interrupt vector and reserving the last interrupt vector. This 448 * method results in a decrease of the maximum queues when upper 449 * applications call the rte_eth_dev_configure API function to 450 * enable Rx interrupt. 451 * 452 * - HNS3_INTR_MAPPING_VEC_ALL 453 * PMD driver can map/unmmap all interrupt vectors with queues When 454 * Rx interrupt in enabled. 455 */ 456 uint8_t mapping_mode; 457 /* 458 * The unit of GL(gap limiter) configuration for interrupt coalesce of 459 * queue's interrupt. 460 * value range: 461 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US 462 */ 463 uint8_t gl_unit; 464 /* The max QL(quantity limiter) value */ 465 uint16_t int_ql_max; 466 }; 467 468 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 469 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 470 471 #define HNS3_PKTS_DROP_STATS_MODE1 0 472 #define HNS3_PKTS_DROP_STATS_MODE2 1 473 474 struct hns3_hw { 475 struct rte_eth_dev_data *data; 476 void *io_base; 477 uint8_t revision; /* PCI revision, low byte of class word */ 478 struct hns3_cmq cmq; 479 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 480 struct hns3_mac mac; 481 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 482 struct hns3_tqp_stats tqp_stats; 483 /* Include Mac stats | Rx stats | Tx stats */ 484 struct hns3_mac_stats mac_stats; 485 struct hns3_rx_missed_stats imissed_stats; 486 uint64_t oerror_stats; 487 uint32_t fw_version; 488 489 uint16_t num_msi; 490 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 491 uint16_t tqps_num; /* num task queue pairs of this function */ 492 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ 493 uint16_t rss_size_max; /* HW defined max RSS task queue */ 494 uint16_t rx_buf_len; /* hold min hardware rx buf len */ 495 uint16_t num_tx_desc; /* desc num of per tx queue */ 496 uint16_t num_rx_desc; /* desc num of per rx queue */ 497 uint32_t mng_entry_num; /* number of manager table entry */ 498 uint32_t mac_entry_num; /* number of mac-vlan table entry */ 499 500 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 501 int mc_addrs_num; /* Multicast mac addresses number */ 502 503 /* The configuration info of RSS */ 504 struct hns3_rss_conf rss_info; 505 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ 506 uint16_t rss_ind_tbl_size; 507 uint16_t rss_key_size; 508 509 uint8_t num_tc; /* Total number of enabled TCs */ 510 uint8_t hw_tc_map; 511 enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */ 512 struct hns3_dcb_info dcb_info; 513 enum hns3_fc_status current_fc_status; /* current flow control status */ 514 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 515 uint16_t used_rx_queues; 516 uint16_t used_tx_queues; 517 518 /* Config max queue numbers between rx and tx queues from user */ 519 uint16_t cfg_max_queues; 520 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 521 uint16_t alloc_rss_size; /* RX queue number per TC */ 522 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 523 524 uint32_t capability; 525 uint32_t max_tm_rate; 526 /* 527 * The minimum length of the packet supported by hardware in the Tx 528 * direction. 529 */ 530 uint32_t min_tx_pkt_len; 531 532 struct hns3_queue_intr intr; 533 /* 534 * tso mode. 535 * value range: 536 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 537 * 538 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 539 * In this mode, because of the hardware constraint, network driver 540 * software need erase the L4 len value of the TCP pseudo header 541 * and recalculate the TCP pseudo header checksum of packets that 542 * need TSO. 543 * 544 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 545 * In this mode, hardware support recalculate the TCP pseudo header 546 * checksum of packets that need TSO, so network driver software 547 * not need to recalculate it. 548 */ 549 uint8_t tso_mode; 550 /* 551 * vlan mode. 552 * value range: 553 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE 554 * 555 * - HNS3_SW_SHIFT_AND_DISCARD_MODE 556 * For some versions of hardware network engine, because of the 557 * hardware limitation, PMD driver needs to detect the PVID status 558 * to work with haredware to implement PVID-related functions. 559 * For example, driver need discard the stripped PVID tag to ensure 560 * the PVID will not report to mbuf and shift the inserted VLAN tag 561 * to avoid port based VLAN covering it. 562 * 563 * - HNS3_HW_SHIT_AND_DISCARD_MODE 564 * PMD driver does not need to process PVID-related functions in 565 * I/O process, Hardware will adjust the sequence between port based 566 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by 567 * PVID will be invisible to driver. And in this mode, hns3 is able 568 * to send a multi-layer VLAN packets when hw VLAN insert offload 569 * is enabled. 570 */ 571 uint8_t vlan_mode; 572 /* 573 * promisc mode. 574 * value range: 575 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE 576 * 577 * - HNS3_UNLIMIT_PROMISC_MODE 578 * In this mode, TX unicast promisc will be configured when promisc 579 * is set, driver can receive all the ingress and outgoing traffic. 580 * In the words, all the ingress packets, all the packets sent from 581 * the PF and other VFs on the same physical port. 582 * 583 * - HNS3_LIMIT_PROMISC_MODE 584 * In this mode, TX unicast promisc is shutdown when promisc mode 585 * is set. So, driver will only receive all the ingress traffic. 586 * The packets sent from the PF and other VFs on the same physical 587 * port won't be copied to the function which has set promisc mode. 588 */ 589 uint8_t promisc_mode; 590 591 /* 592 * drop_stats_mode mode. 593 * value range: 594 * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 595 * 596 * - HNS3_PKTS_DROP_STATS_MODE1 597 * This mode for kunpeng920. In this mode, port level imissed stats 598 * is supported. It only includes RPU drop stats. 599 * 600 * - HNS3_PKTS_DROP_STATS_MODE2 601 * This mode for kunpeng930. In this mode, imissed stats and oerrors 602 * stats is supported. Function level imissed stats is supported. It 603 * includes RPU drop stats in VF, and includes both RPU drop stats 604 * and SSU drop stats in PF. Oerror stats is also supported in PF. 605 */ 606 uint8_t drop_stats_mode; 607 608 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 609 /* 610 * udp checksum mode. 611 * value range: 612 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE 613 * 614 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE 615 * In this mode, HW can not do checksum for special UDP port like 616 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel 617 * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need 618 * do the checksum for these packets to avoid a checksum error. 619 * 620 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE 621 * In this mode, HW does not have the preceding problems and can 622 * directly calculate the checksum of these UDP packets. 623 */ 624 uint8_t udp_cksum_mode; 625 626 struct hns3_port_base_vlan_config port_base_vlan_cfg; 627 /* 628 * PMD setup and configuration is not thread safe. Since it is not 629 * performance sensitive, it is better to guarantee thread-safety 630 * and add device level lock. Adapter control operations which 631 * change its state should acquire the lock. 632 */ 633 rte_spinlock_t lock; 634 enum hns3_adapter_state adapter_state; 635 struct hns3_reset_data reset; 636 }; 637 638 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 639 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 640 641 /* vlan entry information. */ 642 struct hns3_user_vlan_table { 643 LIST_ENTRY(hns3_user_vlan_table) next; 644 bool hd_tbl_status; 645 uint16_t vlan_id; 646 }; 647 648 /* Vlan tag configuration for RX direction */ 649 struct hns3_rx_vtag_cfg { 650 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 651 bool strip_tag1_en; /* Whether strip inner vlan tag */ 652 bool strip_tag2_en; /* Whether strip outer vlan tag */ 653 /* 654 * If strip_tag_en is enabled, this bit decide whether to map the vlan 655 * tag to descriptor. 656 */ 657 bool strip_tag1_discard_en; 658 bool strip_tag2_discard_en; 659 /* 660 * If this bit is enabled, only map inner/outer priority to descriptor 661 * and the vlan tag is always 0. 662 */ 663 bool vlan1_vlan_prionly; 664 bool vlan2_vlan_prionly; 665 }; 666 667 /* Vlan tag configuration for TX direction */ 668 struct hns3_tx_vtag_cfg { 669 bool accept_tag1; /* Whether accept tag1 packet from host */ 670 bool accept_untag1; /* Whether accept untag1 packet from host */ 671 bool accept_tag2; 672 bool accept_untag2; 673 bool insert_tag1_en; /* Whether insert outer vlan tag */ 674 bool insert_tag2_en; /* Whether insert inner vlan tag */ 675 /* 676 * In shift mode, hw will shift the sequence of port based VLAN and 677 * BD VLAN. 678 */ 679 bool tag_shift_mode_en; /* hw shift vlan tag automatically */ 680 uint16_t default_tag1; /* The default outer vlan tag to insert */ 681 uint16_t default_tag2; /* The default inner vlan tag to insert */ 682 }; 683 684 struct hns3_vtag_cfg { 685 struct hns3_rx_vtag_cfg rx_vcfg; 686 struct hns3_tx_vtag_cfg tx_vcfg; 687 }; 688 689 /* Request types for IPC. */ 690 enum hns3_mp_req_type { 691 HNS3_MP_REQ_START_RXTX = 1, 692 HNS3_MP_REQ_STOP_RXTX, 693 HNS3_MP_REQ_MAX 694 }; 695 696 /* Pameters for IPC. */ 697 struct hns3_mp_param { 698 enum hns3_mp_req_type type; 699 int port_id; 700 int result; 701 }; 702 703 /* Request timeout for IPC. */ 704 #define HNS3_MP_REQ_TIMEOUT_SEC 5 705 706 /* Key string for IPC. */ 707 #define HNS3_MP_NAME "net_hns3_mp" 708 709 #define HNS3_L2TBL_NUM 4 710 #define HNS3_L3TBL_NUM 16 711 #define HNS3_L4TBL_NUM 16 712 #define HNS3_OL2TBL_NUM 4 713 #define HNS3_OL3TBL_NUM 16 714 #define HNS3_OL4TBL_NUM 16 715 #define HNS3_PTYPE_NUM 256 716 717 struct hns3_ptype_table { 718 /* 719 * The next fields used to calc packet-type by the 720 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor. 721 */ 722 uint32_t l3table[HNS3_L3TBL_NUM]; 723 uint32_t l4table[HNS3_L4TBL_NUM]; 724 uint32_t inner_l3table[HNS3_L3TBL_NUM]; 725 uint32_t inner_l4table[HNS3_L4TBL_NUM]; 726 uint32_t ol3table[HNS3_OL3TBL_NUM]; 727 uint32_t ol4table[HNS3_OL4TBL_NUM]; 728 729 /* 730 * The next field used to calc packet-type by the PTYPE from the Rx 731 * descriptor, it functions only when firmware report the capability of 732 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it. 733 */ 734 uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned; 735 }; 736 737 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0 738 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1 739 740 struct hns3_pf { 741 struct hns3_adapter *adapter; 742 bool is_main_pf; 743 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 744 745 /* 746 * tqp_config mode 747 * tqp_config_mode value range: 748 * HNS3_FIXED_MAX_TQP_NUM_MODE, 749 * HNS3_FLEX_MAX_TQP_NUM_MODE 750 * 751 * - HNS3_FIXED_MAX_TQP_NUM_MODE 752 * There is a limitation on the number of pf interrupts available for 753 * on some versions of network engines. In this case, the maximum 754 * queue number of pf can not be greater than the interrupt number, 755 * such as pf of network engine with revision_id 0x21. So the maximum 756 * number of queues must be fixed. 757 * 758 * - HNS3_FLEX_MAX_TQP_NUM_MODE 759 * In this mode, the maximum queue number of pf has not any constraint 760 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 761 * in the config file. Users can modify the macro according to their 762 * own application scenarios, which is more flexible to use. 763 */ 764 uint8_t tqp_config_mode; 765 766 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 767 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 768 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 769 770 uint16_t mps; /* Max packet size */ 771 772 uint8_t tx_sch_mode; 773 uint8_t tc_max; /* max number of tc driver supported */ 774 uint8_t local_max_tc; /* max number of local tc */ 775 uint8_t pfc_max; 776 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 777 uint16_t pause_time; 778 bool support_fc_autoneg; /* support FC autonegotiate */ 779 780 uint16_t wanted_umv_size; 781 uint16_t max_umv_size; 782 uint16_t used_umv_size; 783 784 bool support_sfp_query; 785 uint32_t fec_mode; /* current FEC mode for ethdev */ 786 787 bool ptp_enable; 788 789 /* Stores timestamp of last received packet on dev */ 790 uint64_t rx_timestamp; 791 792 struct hns3_vtag_cfg vtag_config; 793 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 794 795 struct hns3_fdir_info fdir; /* flow director info */ 796 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 797 798 struct hns3_tm_conf tm_conf; 799 }; 800 801 enum { 802 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED, 803 HNS3_PF_PUSH_LSC_CAP_SUPPORTED, 804 HNS3_PF_PUSH_LSC_CAP_UNKNOWN 805 }; 806 807 struct hns3_vf { 808 struct hns3_adapter *adapter; 809 810 /* Whether PF support push link status change to VF */ 811 uint16_t pf_push_lsc_cap; 812 813 /* 814 * If PF support push link status change, VF still need send request to 815 * get link status in some cases (such as reset recover stage), so use 816 * the req_link_info_cnt to control max request count. 817 */ 818 uint16_t req_link_info_cnt; 819 820 uint16_t poll_job_started; /* whether poll job is started */ 821 }; 822 823 struct hns3_adapter { 824 struct hns3_hw hw; 825 826 /* Specific for PF or VF */ 827 bool is_vf; /* false - PF, true - VF */ 828 union { 829 struct hns3_pf pf; 830 struct hns3_vf vf; 831 }; 832 833 uint32_t rx_func_hint; 834 uint32_t tx_func_hint; 835 836 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; 837 }; 838 839 enum { 840 HNS3_IO_FUNC_HINT_NONE = 0, 841 HNS3_IO_FUNC_HINT_VEC, 842 HNS3_IO_FUNC_HINT_SVE, 843 HNS3_IO_FUNC_HINT_SIMPLE, 844 HNS3_IO_FUNC_HINT_COMMON 845 }; 846 847 #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" 848 #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" 849 850 #define HNS3_DEV_SUPPORT_DCB_B 0x0 851 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 852 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 853 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 854 #define HNS3_DEV_SUPPORT_PTP_B 0x4 855 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 856 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 857 #define HNS3_DEV_SUPPORT_STASH_B 0x7 858 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 859 #define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA 860 #define HNS3_DEV_SUPPORT_RAS_IMP_B 0xB 861 862 #define hns3_dev_dcb_supported(hw) \ 863 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) 864 865 /* Support copper media type */ 866 #define hns3_dev_copper_supported(hw) \ 867 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) 868 869 /* Support UDP GSO offload */ 870 #define hns3_dev_udp_gso_supported(hw) \ 871 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) 872 873 /* Support the queue region action rule of flow directory */ 874 #define hns3_dev_fd_queue_region_supported(hw) \ 875 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) 876 877 /* Support PTP timestamp offload */ 878 #define hns3_dev_ptp_supported(hw) \ 879 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) 880 881 #define hns3_dev_tx_push_supported(hw) \ 882 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) 883 884 /* Support to Independently enable/disable/reset Tx or Rx queues */ 885 #define hns3_dev_indep_txrx_supported(hw) \ 886 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) 887 888 #define hns3_dev_stash_supported(hw) \ 889 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) 890 891 #define hns3_dev_rxd_adv_layout_supported(hw) \ 892 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) 893 894 #define hns3_dev_outer_udp_cksum_supported(hw) \ 895 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) 896 897 #define hns3_dev_ras_imp_supported(hw) \ 898 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B) 899 900 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 901 (&((struct hns3_adapter *)adapter)->hw) 902 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 903 (&((struct hns3_adapter *)adapter)->pf) 904 #define HNS3_DEV_PRIVATE_TO_VF(adapter) \ 905 (&((struct hns3_adapter *)adapter)->vf) 906 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 907 container_of(hw, struct hns3_adapter, hw) 908 909 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw) 910 { 911 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 912 return &adapter->pf; 913 } 914 915 static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw) 916 { 917 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 918 return &adapter->vf; 919 } 920 921 #define hns3_set_field(origin, mask, shift, val) \ 922 do { \ 923 (origin) &= (~(mask)); \ 924 (origin) |= ((val) << (shift)) & (mask); \ 925 } while (0) 926 #define hns3_get_field(origin, mask, shift) \ 927 (((origin) & (mask)) >> (shift)) 928 #define hns3_set_bit(origin, shift, val) \ 929 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 930 #define hns3_get_bit(origin, shift) \ 931 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 932 933 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) 934 935 /* 936 * upper_32_bits - return bits 32-63 of a number 937 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 938 * the "right shift count >= width of type" warning when that quantity is 939 * 32-bits. 940 */ 941 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 942 943 /* lower_32_bits - return bits 0-31 of a number */ 944 #define lower_32_bits(n) ((uint32_t)(n)) 945 946 #define BIT(nr) (1UL << (nr)) 947 948 #define BIT_ULL(x) (1ULL << (x)) 949 950 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 951 #define GENMASK(h, l) \ 952 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 953 954 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 955 #define rounddown(x, y) ((x) - ((x) % (y))) 956 957 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 958 959 /* 960 * Because hardware always access register in little-endian mode based on hns3 961 * network engine, so driver should also call rte_cpu_to_le_32 to convert data 962 * in little-endian mode before writing register and call rte_le_to_cpu_32 to 963 * convert data after reading from register. 964 * 965 * Here the driver encapsulates the data conversion operation in the register 966 * read/write operation function as below: 967 * hns3_write_reg 968 * hns3_write_reg_opt 969 * hns3_read_reg 970 * Therefore, when calling these functions, conversion is not required again. 971 */ 972 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 973 { 974 rte_write32(rte_cpu_to_le_32(value), 975 (volatile void *)((char *)base + reg)); 976 } 977 978 /* 979 * The optimized function for writing registers used in the '.rx_pkt_burst' and 980 * '.tx_pkt_burst' ops implementation function. 981 */ 982 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) 983 { 984 rte_io_wmb(); 985 rte_write32_relaxed(rte_cpu_to_le_32(value), addr); 986 } 987 988 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 989 { 990 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); 991 return rte_le_to_cpu_32(read_val); 992 } 993 994 #define hns3_write_dev(a, reg, value) \ 995 hns3_write_reg((a)->io_base, (reg), (value)) 996 997 #define hns3_read_dev(a, reg) \ 998 hns3_read_reg((a)->io_base, (reg)) 999 1000 #define ARRAY_SIZE(x) RTE_DIM(x) 1001 1002 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 1003 do { \ 1004 act = (actions) + (index); \ 1005 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 1006 (index)++; \ 1007 act = actions + index; \ 1008 } \ 1009 } while (0) 1010 1011 #define MSEC_PER_SEC 1000L 1012 #define USEC_PER_MSEC 1000L 1013 1014 static inline uint64_t 1015 get_timeofday_ms(void) 1016 { 1017 struct timeval tv; 1018 1019 (void)gettimeofday(&tv, NULL); 1020 1021 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 1022 } 1023 1024 static inline uint64_t 1025 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 1026 { 1027 uint64_t res; 1028 1029 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 1030 return res; 1031 } 1032 1033 static inline void 1034 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 1035 { 1036 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 1037 } 1038 1039 static inline void 1040 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 1041 { 1042 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 1043 } 1044 1045 static inline int64_t 1046 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 1047 { 1048 uint64_t mask = (1UL << nr); 1049 1050 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 1051 } 1052 1053 int hns3_buffer_alloc(struct hns3_hw *hw); 1054 int hns3_dev_flow_ops_get(struct rte_eth_dev *dev, 1055 const struct rte_flow_ops **ops); 1056 bool hns3_is_reset_pending(struct hns3_adapter *hns); 1057 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 1058 void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); 1059 void hns3_ether_format_addr(char *buf, uint16_t size, 1060 const struct rte_ether_addr *ether_addr); 1061 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, 1062 struct rte_eth_dev_info *info); 1063 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 1064 uint32_t link_speed, uint8_t link_duplex); 1065 void hns3_parse_devargs(struct rte_eth_dev *dev); 1066 void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); 1067 int hns3_restore_ptp(struct hns3_adapter *hns); 1068 int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev, 1069 struct rte_eth_conf *conf); 1070 int hns3_ptp_init(struct hns3_hw *hw); 1071 int hns3_timesync_enable(struct rte_eth_dev *dev); 1072 int hns3_timesync_disable(struct rte_eth_dev *dev); 1073 int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1074 struct timespec *timestamp, 1075 uint32_t flags __rte_unused); 1076 int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1077 struct timespec *timestamp); 1078 int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts); 1079 int hns3_timesync_write_time(struct rte_eth_dev *dev, 1080 const struct timespec *ts); 1081 int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 1082 1083 static inline bool 1084 is_reset_pending(struct hns3_adapter *hns) 1085 { 1086 bool ret; 1087 if (hns->is_vf) 1088 ret = hns3vf_is_reset_pending(hns); 1089 else 1090 ret = hns3_is_reset_pending(hns); 1091 return ret; 1092 } 1093 1094 static inline uint64_t 1095 hns3_txvlan_cap_get(struct hns3_hw *hw) 1096 { 1097 if (hw->port_base_vlan_cfg.state) 1098 return DEV_TX_OFFLOAD_VLAN_INSERT; 1099 else 1100 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; 1101 } 1102 1103 #endif /* _HNS3_ETHDEV_H_ */ 1104