1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <errno.h> 6 #include <stdarg.h> 7 #include <stdbool.h> 8 #include <stdio.h> 9 #include <stdint.h> 10 #include <inttypes.h> 11 #include <unistd.h> 12 #include <rte_atomic.h> 13 #include <rte_bus_pci.h> 14 #include <rte_common.h> 15 #include <rte_cycles.h> 16 #include <rte_dev.h> 17 #include <rte_eal.h> 18 #include <rte_ether.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_interrupts.h> 22 #include <rte_io.h> 23 #include <rte_log.h> 24 #include <rte_pci.h> 25 26 #include "hns3_ethdev.h" 27 #include "hns3_logs.h" 28 #include "hns3_rxtx.h" 29 #include "hns3_intr.h" 30 #include "hns3_regs.h" 31 #include "hns3_dcb.h" 32 #include "hns3_mp.h" 33 34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 36 37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 38 #define HNS3_INVLID_PVID 0xFFFF 39 40 #define HNS3_FILTER_TYPE_VF 0 41 #define HNS3_FILTER_TYPE_PORT 1 42 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 43 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 44 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 45 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 46 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 47 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 48 | HNS3_FILTER_FE_ROCE_EGRESS_B) 49 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 50 | HNS3_FILTER_FE_ROCE_INGRESS_B) 51 52 /* Reset related Registers */ 53 #define HNS3_GLOBAL_RESET_BIT 0 54 #define HNS3_CORE_RESET_BIT 1 55 #define HNS3_IMP_RESET_BIT 2 56 #define HNS3_FUN_RST_ING_B 0 57 58 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 59 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U 60 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U 61 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U 62 63 #define HNS3_RESET_WAIT_MS 100 64 #define HNS3_RESET_WAIT_CNT 200 65 66 enum hns3_evt_cause { 67 HNS3_VECTOR0_EVENT_RST, 68 HNS3_VECTOR0_EVENT_MBX, 69 HNS3_VECTOR0_EVENT_ERR, 70 HNS3_VECTOR0_EVENT_OTHER, 71 }; 72 73 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 74 uint64_t *levels); 75 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 76 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 77 int on); 78 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev); 79 80 static int hns3_add_mc_addr(struct hns3_hw *hw, 81 struct rte_ether_addr *mac_addr); 82 static int hns3_remove_mc_addr(struct hns3_hw *hw, 83 struct rte_ether_addr *mac_addr); 84 85 static void 86 hns3_pf_disable_irq0(struct hns3_hw *hw) 87 { 88 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 89 } 90 91 static void 92 hns3_pf_enable_irq0(struct hns3_hw *hw) 93 { 94 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 95 } 96 97 static enum hns3_evt_cause 98 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 99 { 100 struct hns3_hw *hw = &hns->hw; 101 uint32_t vector0_int_stats; 102 uint32_t cmdq_src_val; 103 uint32_t hw_err_src_reg; 104 uint32_t val; 105 enum hns3_evt_cause ret; 106 107 /* fetch the events from their corresponding regs */ 108 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 109 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 110 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 111 112 /* 113 * Assumption: If by any chance reset and mailbox events are reported 114 * together then we will only process reset event and defer the 115 * processing of the mailbox events. Since, we would have not cleared 116 * RX CMDQ event this time we would receive again another interrupt 117 * from H/W just for the mailbox. 118 */ 119 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 120 rte_atomic16_set(&hw->reset.disable_cmd, 1); 121 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 122 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 123 if (clearval) { 124 hw->reset.stats.imp_cnt++; 125 hns3_warn(hw, "IMP reset detected, clear reset status"); 126 } else { 127 hns3_schedule_delayed_reset(hns); 128 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 129 } 130 131 ret = HNS3_VECTOR0_EVENT_RST; 132 goto out; 133 } 134 135 /* Global reset */ 136 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 137 rte_atomic16_set(&hw->reset.disable_cmd, 1); 138 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 139 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 140 if (clearval) { 141 hw->reset.stats.global_cnt++; 142 hns3_warn(hw, "Global reset detected, clear reset status"); 143 } else { 144 hns3_schedule_delayed_reset(hns); 145 hns3_warn(hw, "Global reset detected, don't clear reset status"); 146 } 147 148 ret = HNS3_VECTOR0_EVENT_RST; 149 goto out; 150 } 151 152 /* check for vector0 msix event source */ 153 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || 154 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { 155 val = vector0_int_stats | hw_err_src_reg; 156 ret = HNS3_VECTOR0_EVENT_ERR; 157 goto out; 158 } 159 160 /* check for vector0 mailbox(=CMDQ RX) event source */ 161 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 162 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 163 val = cmdq_src_val; 164 ret = HNS3_VECTOR0_EVENT_MBX; 165 goto out; 166 } 167 168 if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg)) 169 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x", 170 vector0_int_stats, cmdq_src_val, hw_err_src_reg); 171 val = vector0_int_stats; 172 ret = HNS3_VECTOR0_EVENT_OTHER; 173 out: 174 175 if (clearval) 176 *clearval = val; 177 return ret; 178 } 179 180 static void 181 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 182 { 183 if (event_type == HNS3_VECTOR0_EVENT_RST) 184 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 185 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 186 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 187 } 188 189 static void 190 hns3_clear_all_event_cause(struct hns3_hw *hw) 191 { 192 uint32_t vector0_int_stats; 193 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 194 195 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 196 hns3_warn(hw, "Probe during IMP reset interrupt"); 197 198 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 199 hns3_warn(hw, "Probe during Global reset interrupt"); 200 201 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 202 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 203 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 204 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 205 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 206 } 207 208 static void 209 hns3_interrupt_handler(void *param) 210 { 211 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 212 struct hns3_adapter *hns = dev->data->dev_private; 213 struct hns3_hw *hw = &hns->hw; 214 enum hns3_evt_cause event_cause; 215 uint32_t clearval = 0; 216 217 /* Disable interrupt */ 218 hns3_pf_disable_irq0(hw); 219 220 event_cause = hns3_check_event_cause(hns, &clearval); 221 222 /* vector 0 interrupt is shared with reset and mailbox source events. */ 223 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 224 hns3_warn(hw, "Received err interrupt"); 225 hns3_handle_msix_error(hns, &hw->reset.request); 226 hns3_handle_ras_error(hns, &hw->reset.request); 227 hns3_schedule_reset(hns); 228 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { 229 hns3_warn(hw, "Received reset interrupt"); 230 hns3_schedule_reset(hns); 231 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) 232 hns3_dev_handle_mbx_msg(hw); 233 else 234 hns3_err(hw, "Received unknown event"); 235 236 hns3_clear_event_cause(hw, event_cause, clearval); 237 /* Enable interrupt if it is not cause by reset */ 238 hns3_pf_enable_irq0(hw); 239 } 240 241 static int 242 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 243 { 244 #define HNS3_VLAN_ID_OFFSET_STEP 160 245 #define HNS3_VLAN_BYTE_SIZE 8 246 struct hns3_vlan_filter_pf_cfg_cmd *req; 247 struct hns3_hw *hw = &hns->hw; 248 uint8_t vlan_offset_byte_val; 249 struct hns3_cmd_desc desc; 250 uint8_t vlan_offset_byte; 251 uint8_t vlan_offset_base; 252 int ret; 253 254 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 255 256 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 257 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 258 HNS3_VLAN_BYTE_SIZE; 259 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 260 261 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 262 req->vlan_offset = vlan_offset_base; 263 req->vlan_cfg = on ? 0 : 1; 264 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 265 266 ret = hns3_cmd_send(hw, &desc, 1); 267 if (ret) 268 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 269 vlan_id, ret); 270 271 return ret; 272 } 273 274 static void 275 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 276 { 277 struct hns3_user_vlan_table *vlan_entry; 278 struct hns3_pf *pf = &hns->pf; 279 280 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 281 if (vlan_entry->vlan_id == vlan_id) { 282 if (vlan_entry->hd_tbl_status) 283 hns3_set_port_vlan_filter(hns, vlan_id, 0); 284 LIST_REMOVE(vlan_entry, next); 285 rte_free(vlan_entry); 286 break; 287 } 288 } 289 } 290 291 static void 292 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 293 bool writen_to_tbl) 294 { 295 struct hns3_user_vlan_table *vlan_entry; 296 struct hns3_hw *hw = &hns->hw; 297 struct hns3_pf *pf = &hns->pf; 298 299 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 300 if (vlan_entry->vlan_id == vlan_id) 301 return; 302 } 303 304 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 305 if (vlan_entry == NULL) { 306 hns3_err(hw, "Failed to malloc hns3 vlan table"); 307 return; 308 } 309 310 vlan_entry->hd_tbl_status = writen_to_tbl; 311 vlan_entry->vlan_id = vlan_id; 312 313 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 314 } 315 316 static int 317 hns3_restore_vlan_table(struct hns3_adapter *hns) 318 { 319 struct hns3_user_vlan_table *vlan_entry; 320 struct hns3_hw *hw = &hns->hw; 321 struct hns3_pf *pf = &hns->pf; 322 uint16_t vlan_id; 323 int ret = 0; 324 325 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 326 return hns3_vlan_pvid_configure(hns, 327 hw->port_base_vlan_cfg.pvid, 1); 328 329 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 330 if (vlan_entry->hd_tbl_status) { 331 vlan_id = vlan_entry->vlan_id; 332 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 333 if (ret) 334 break; 335 } 336 } 337 338 return ret; 339 } 340 341 static int 342 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 343 { 344 struct hns3_hw *hw = &hns->hw; 345 bool writen_to_tbl = false; 346 int ret = 0; 347 348 /* 349 * When vlan filter is enabled, hardware regards vlan id 0 as the entry 350 * for normal packet, deleting vlan id 0 is not allowed. 351 */ 352 if (on == 0 && vlan_id == 0) 353 return 0; 354 355 /* 356 * When port base vlan enabled, we use port base vlan as the vlan 357 * filter condition. In this case, we don't update vlan filter table 358 * when user add new vlan or remove exist vlan, just update the 359 * vlan list. The vlan id in vlan list will be writen in vlan filter 360 * table until port base vlan disabled 361 */ 362 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 363 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 364 writen_to_tbl = true; 365 } 366 367 if (ret == 0 && vlan_id) { 368 if (on) 369 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 370 else 371 hns3_rm_dev_vlan_table(hns, vlan_id); 372 } 373 return ret; 374 } 375 376 static int 377 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 378 { 379 struct hns3_adapter *hns = dev->data->dev_private; 380 struct hns3_hw *hw = &hns->hw; 381 int ret; 382 383 rte_spinlock_lock(&hw->lock); 384 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 385 rte_spinlock_unlock(&hw->lock); 386 return ret; 387 } 388 389 static int 390 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 391 uint16_t tpid) 392 { 393 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 394 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 395 struct hns3_hw *hw = &hns->hw; 396 struct hns3_cmd_desc desc; 397 int ret; 398 399 if ((vlan_type != ETH_VLAN_TYPE_INNER && 400 vlan_type != ETH_VLAN_TYPE_OUTER)) { 401 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 402 return -EINVAL; 403 } 404 405 if (tpid != RTE_ETHER_TYPE_VLAN) { 406 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 407 return -EINVAL; 408 } 409 410 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 411 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 412 413 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 414 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 415 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 416 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 417 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 418 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 419 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 420 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 421 } 422 423 ret = hns3_cmd_send(hw, &desc, 1); 424 if (ret) { 425 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 426 ret); 427 return ret; 428 } 429 430 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 431 432 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 433 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 434 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 435 436 ret = hns3_cmd_send(hw, &desc, 1); 437 if (ret) 438 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 439 ret); 440 return ret; 441 } 442 443 static int 444 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 445 uint16_t tpid) 446 { 447 struct hns3_adapter *hns = dev->data->dev_private; 448 struct hns3_hw *hw = &hns->hw; 449 int ret; 450 451 rte_spinlock_lock(&hw->lock); 452 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 453 rte_spinlock_unlock(&hw->lock); 454 return ret; 455 } 456 457 static int 458 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 459 struct hns3_rx_vtag_cfg *vcfg) 460 { 461 struct hns3_vport_vtag_rx_cfg_cmd *req; 462 struct hns3_hw *hw = &hns->hw; 463 struct hns3_cmd_desc desc; 464 uint16_t vport_id; 465 uint8_t bitmap; 466 int ret; 467 468 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 469 470 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 471 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 472 vcfg->strip_tag1_en ? 1 : 0); 473 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 474 vcfg->strip_tag2_en ? 1 : 0); 475 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 476 vcfg->vlan1_vlan_prionly ? 1 : 0); 477 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 478 vcfg->vlan2_vlan_prionly ? 1 : 0); 479 480 /* 481 * In current version VF is not supported when PF is driven by DPDK 482 * driver, just need to configure parameters for PF vport. 483 */ 484 vport_id = HNS3_PF_FUNC_ID; 485 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 486 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 487 req->vf_bitmap[req->vf_offset] = bitmap; 488 489 ret = hns3_cmd_send(hw, &desc, 1); 490 if (ret) 491 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 492 return ret; 493 } 494 495 static void 496 hns3_update_rx_offload_cfg(struct hns3_adapter *hns, 497 struct hns3_rx_vtag_cfg *vcfg) 498 { 499 struct hns3_pf *pf = &hns->pf; 500 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg)); 501 } 502 503 static void 504 hns3_update_tx_offload_cfg(struct hns3_adapter *hns, 505 struct hns3_tx_vtag_cfg *vcfg) 506 { 507 struct hns3_pf *pf = &hns->pf; 508 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg)); 509 } 510 511 static int 512 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 513 { 514 struct hns3_rx_vtag_cfg rxvlan_cfg; 515 struct hns3_hw *hw = &hns->hw; 516 int ret; 517 518 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 519 rxvlan_cfg.strip_tag1_en = false; 520 rxvlan_cfg.strip_tag2_en = enable; 521 } else { 522 rxvlan_cfg.strip_tag1_en = enable; 523 rxvlan_cfg.strip_tag2_en = true; 524 } 525 526 rxvlan_cfg.vlan1_vlan_prionly = false; 527 rxvlan_cfg.vlan2_vlan_prionly = false; 528 rxvlan_cfg.rx_vlan_offload_en = enable; 529 530 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 531 if (ret) { 532 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret); 533 return ret; 534 } 535 536 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg); 537 538 return ret; 539 } 540 541 static int 542 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 543 uint8_t fe_type, bool filter_en, uint8_t vf_id) 544 { 545 struct hns3_vlan_filter_ctrl_cmd *req; 546 struct hns3_cmd_desc desc; 547 int ret; 548 549 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 550 551 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 552 req->vlan_type = vlan_type; 553 req->vlan_fe = filter_en ? fe_type : 0; 554 req->vf_id = vf_id; 555 556 ret = hns3_cmd_send(hw, &desc, 1); 557 if (ret) 558 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 559 560 return ret; 561 } 562 563 static int 564 hns3_vlan_filter_init(struct hns3_adapter *hns) 565 { 566 struct hns3_hw *hw = &hns->hw; 567 int ret; 568 569 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 570 HNS3_FILTER_FE_EGRESS, false, 571 HNS3_PF_FUNC_ID); 572 if (ret) { 573 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 574 return ret; 575 } 576 577 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 578 HNS3_FILTER_FE_INGRESS, false, 579 HNS3_PF_FUNC_ID); 580 if (ret) 581 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 582 583 return ret; 584 } 585 586 static int 587 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 588 { 589 struct hns3_hw *hw = &hns->hw; 590 int ret; 591 592 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 593 HNS3_FILTER_FE_INGRESS, enable, 594 HNS3_PF_FUNC_ID); 595 if (ret) 596 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 597 enable ? "enable" : "disable", ret); 598 599 return ret; 600 } 601 602 static int 603 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 604 { 605 struct hns3_adapter *hns = dev->data->dev_private; 606 struct hns3_hw *hw = &hns->hw; 607 struct rte_eth_rxmode *rxmode; 608 unsigned int tmp_mask; 609 bool enable; 610 int ret = 0; 611 612 rte_spinlock_lock(&hw->lock); 613 rxmode = &dev->data->dev_conf.rxmode; 614 tmp_mask = (unsigned int)mask; 615 if (tmp_mask & ETH_VLAN_FILTER_MASK) { 616 /* ignore vlan filter configuration during promiscuous mode */ 617 if (!dev->data->promiscuous) { 618 /* Enable or disable VLAN filter */ 619 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? 620 true : false; 621 622 ret = hns3_enable_vlan_filter(hns, enable); 623 if (ret) { 624 rte_spinlock_unlock(&hw->lock); 625 hns3_err(hw, "failed to %s rx filter, ret = %d", 626 enable ? "enable" : "disable", ret); 627 return ret; 628 } 629 } 630 } 631 632 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 633 /* Enable or disable VLAN stripping */ 634 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? 635 true : false; 636 637 ret = hns3_en_hw_strip_rxvtag(hns, enable); 638 if (ret) { 639 rte_spinlock_unlock(&hw->lock); 640 hns3_err(hw, "failed to %s rx strip, ret = %d", 641 enable ? "enable" : "disable", ret); 642 return ret; 643 } 644 } 645 646 rte_spinlock_unlock(&hw->lock); 647 648 return ret; 649 } 650 651 static int 652 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 653 struct hns3_tx_vtag_cfg *vcfg) 654 { 655 struct hns3_vport_vtag_tx_cfg_cmd *req; 656 struct hns3_cmd_desc desc; 657 struct hns3_hw *hw = &hns->hw; 658 uint16_t vport_id; 659 uint8_t bitmap; 660 int ret; 661 662 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 663 664 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 665 req->def_vlan_tag1 = vcfg->default_tag1; 666 req->def_vlan_tag2 = vcfg->default_tag2; 667 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 668 vcfg->accept_tag1 ? 1 : 0); 669 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 670 vcfg->accept_untag1 ? 1 : 0); 671 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 672 vcfg->accept_tag2 ? 1 : 0); 673 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 674 vcfg->accept_untag2 ? 1 : 0); 675 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 676 vcfg->insert_tag1_en ? 1 : 0); 677 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 678 vcfg->insert_tag2_en ? 1 : 0); 679 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 680 681 /* 682 * In current version VF is not supported when PF is driven by DPDK 683 * driver, just need to configure parameters for PF vport. 684 */ 685 vport_id = HNS3_PF_FUNC_ID; 686 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 687 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 688 req->vf_bitmap[req->vf_offset] = bitmap; 689 690 ret = hns3_cmd_send(hw, &desc, 1); 691 if (ret) 692 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 693 694 return ret; 695 } 696 697 static int 698 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 699 uint16_t pvid) 700 { 701 struct hns3_hw *hw = &hns->hw; 702 struct hns3_tx_vtag_cfg txvlan_cfg; 703 int ret; 704 705 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 706 txvlan_cfg.accept_tag1 = true; 707 txvlan_cfg.insert_tag1_en = false; 708 txvlan_cfg.default_tag1 = 0; 709 } else { 710 txvlan_cfg.accept_tag1 = false; 711 txvlan_cfg.insert_tag1_en = true; 712 txvlan_cfg.default_tag1 = pvid; 713 } 714 715 txvlan_cfg.accept_untag1 = true; 716 txvlan_cfg.accept_tag2 = true; 717 txvlan_cfg.accept_untag2 = true; 718 txvlan_cfg.insert_tag2_en = false; 719 txvlan_cfg.default_tag2 = 0; 720 721 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 722 if (ret) { 723 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 724 ret); 725 return ret; 726 } 727 728 hns3_update_tx_offload_cfg(hns, &txvlan_cfg); 729 return ret; 730 } 731 732 static void 733 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on) 734 { 735 struct hns3_hw *hw = &hns->hw; 736 737 hw->port_base_vlan_cfg.state = on ? 738 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 739 740 hw->port_base_vlan_cfg.pvid = pvid; 741 } 742 743 static void 744 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 745 { 746 struct hns3_user_vlan_table *vlan_entry; 747 struct hns3_pf *pf = &hns->pf; 748 749 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 750 if (vlan_entry->hd_tbl_status) 751 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 752 753 vlan_entry->hd_tbl_status = false; 754 } 755 756 if (is_del_list) { 757 vlan_entry = LIST_FIRST(&pf->vlan_list); 758 while (vlan_entry) { 759 LIST_REMOVE(vlan_entry, next); 760 rte_free(vlan_entry); 761 vlan_entry = LIST_FIRST(&pf->vlan_list); 762 } 763 } 764 } 765 766 static void 767 hns3_add_all_vlan_table(struct hns3_adapter *hns) 768 { 769 struct hns3_user_vlan_table *vlan_entry; 770 struct hns3_pf *pf = &hns->pf; 771 772 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 773 if (!vlan_entry->hd_tbl_status) 774 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 775 776 vlan_entry->hd_tbl_status = true; 777 } 778 } 779 780 static void 781 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 782 { 783 struct hns3_hw *hw = &hns->hw; 784 int ret; 785 786 hns3_rm_all_vlan_table(hns, true); 787 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) { 788 ret = hns3_set_port_vlan_filter(hns, 789 hw->port_base_vlan_cfg.pvid, 0); 790 if (ret) { 791 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 792 ret); 793 return; 794 } 795 } 796 } 797 798 static int 799 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 800 uint16_t port_base_vlan_state, 801 uint16_t new_pvid, uint16_t old_pvid) 802 { 803 struct hns3_hw *hw = &hns->hw; 804 int ret = 0; 805 806 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 807 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) { 808 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 809 if (ret) { 810 hns3_err(hw, 811 "Failed to clear clear old pvid filter, ret =%d", 812 ret); 813 return ret; 814 } 815 } 816 817 hns3_rm_all_vlan_table(hns, false); 818 return hns3_set_port_vlan_filter(hns, new_pvid, 1); 819 } 820 821 if (new_pvid != 0) { 822 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 823 if (ret) { 824 hns3_err(hw, "Failed to set port vlan filter, ret =%d", 825 ret); 826 return ret; 827 } 828 } 829 830 if (new_pvid == hw->port_base_vlan_cfg.pvid) 831 hns3_add_all_vlan_table(hns); 832 833 return ret; 834 } 835 836 static int 837 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 838 { 839 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 840 struct hns3_rx_vtag_cfg rx_vlan_cfg; 841 bool rx_strip_en; 842 int ret; 843 844 rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false; 845 if (on) { 846 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 847 rx_vlan_cfg.strip_tag2_en = true; 848 } else { 849 rx_vlan_cfg.strip_tag1_en = false; 850 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 851 } 852 rx_vlan_cfg.vlan1_vlan_prionly = false; 853 rx_vlan_cfg.vlan2_vlan_prionly = false; 854 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 855 856 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 857 if (ret) 858 return ret; 859 860 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg); 861 return ret; 862 } 863 864 static int 865 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 866 { 867 struct hns3_hw *hw = &hns->hw; 868 uint16_t port_base_vlan_state; 869 uint16_t old_pvid; 870 int ret; 871 872 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 873 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) 874 hns3_warn(hw, "Invalid operation! As current pvid set " 875 "is %u, disable pvid %u is invalid", 876 hw->port_base_vlan_cfg.pvid, pvid); 877 return 0; 878 } 879 880 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 881 HNS3_PORT_BASE_VLAN_DISABLE; 882 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 883 if (ret) { 884 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 885 ret); 886 return ret; 887 } 888 889 ret = hns3_en_pvid_strip(hns, on); 890 if (ret) { 891 hns3_err(hw, "failed to config rx vlan strip for pvid, " 892 "ret = %d", ret); 893 return ret; 894 } 895 896 if (pvid == HNS3_INVLID_PVID) 897 goto out; 898 old_pvid = hw->port_base_vlan_cfg.pvid; 899 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid, 900 old_pvid); 901 if (ret) { 902 hns3_err(hw, "Failed to update vlan filter entries, ret =%d", 903 ret); 904 return ret; 905 } 906 907 out: 908 hns3_store_port_base_vlan_info(hns, pvid, on); 909 return ret; 910 } 911 912 static int 913 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 914 { 915 struct hns3_adapter *hns = dev->data->dev_private; 916 struct hns3_hw *hw = &hns->hw; 917 bool pvid_en_state_change; 918 uint16_t pvid_state; 919 int ret; 920 921 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 922 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 923 RTE_ETHER_MAX_VLAN_ID); 924 return -EINVAL; 925 } 926 927 /* 928 * If PVID configuration state change, should refresh the PVID 929 * configuration state in struct hns3_tx_queue/hns3_rx_queue. 930 */ 931 pvid_state = hw->port_base_vlan_cfg.state; 932 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || 933 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) 934 pvid_en_state_change = false; 935 else 936 pvid_en_state_change = true; 937 938 rte_spinlock_lock(&hw->lock); 939 ret = hns3_vlan_pvid_configure(hns, pvid, on); 940 rte_spinlock_unlock(&hw->lock); 941 if (ret) 942 return ret; 943 944 if (pvid_en_state_change) 945 hns3_update_all_queues_pvid_state(hw); 946 947 return 0; 948 } 949 950 static void 951 init_port_base_vlan_info(struct hns3_hw *hw) 952 { 953 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 954 hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID; 955 } 956 957 static int 958 hns3_default_vlan_config(struct hns3_adapter *hns) 959 { 960 struct hns3_hw *hw = &hns->hw; 961 int ret; 962 963 ret = hns3_set_port_vlan_filter(hns, 0, 1); 964 if (ret) 965 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 966 return ret; 967 } 968 969 static int 970 hns3_init_vlan_config(struct hns3_adapter *hns) 971 { 972 struct hns3_hw *hw = &hns->hw; 973 int ret; 974 975 /* 976 * This function can be called in the initialization and reset process, 977 * when in reset process, it means that hardware had been reseted 978 * successfully and we need to restore the hardware configuration to 979 * ensure that the hardware configuration remains unchanged before and 980 * after reset. 981 */ 982 if (rte_atomic16_read(&hw->reset.resetting) == 0) 983 init_port_base_vlan_info(hw); 984 985 ret = hns3_vlan_filter_init(hns); 986 if (ret) { 987 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 988 return ret; 989 } 990 991 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER, 992 RTE_ETHER_TYPE_VLAN); 993 if (ret) { 994 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 995 return ret; 996 } 997 998 /* 999 * When in the reinit dev stage of the reset process, the following 1000 * vlan-related configurations may differ from those at initialization, 1001 * we will restore configurations to hardware in hns3_restore_vlan_table 1002 * and hns3_restore_vlan_conf later. 1003 */ 1004 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 1005 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0); 1006 if (ret) { 1007 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 1008 return ret; 1009 } 1010 1011 ret = hns3_en_hw_strip_rxvtag(hns, false); 1012 if (ret) { 1013 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 1014 ret); 1015 return ret; 1016 } 1017 } 1018 1019 return hns3_default_vlan_config(hns); 1020 } 1021 1022 static int 1023 hns3_restore_vlan_conf(struct hns3_adapter *hns) 1024 { 1025 struct hns3_pf *pf = &hns->pf; 1026 struct hns3_hw *hw = &hns->hw; 1027 uint64_t offloads; 1028 bool enable; 1029 int ret; 1030 1031 if (!hw->data->promiscuous) { 1032 /* restore vlan filter states */ 1033 offloads = hw->data->dev_conf.rxmode.offloads; 1034 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false; 1035 ret = hns3_enable_vlan_filter(hns, enable); 1036 if (ret) { 1037 hns3_err(hw, "failed to restore vlan rx filter conf, " 1038 "ret = %d", ret); 1039 return ret; 1040 } 1041 } 1042 1043 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1044 if (ret) { 1045 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1046 return ret; 1047 } 1048 1049 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1050 if (ret) 1051 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1052 1053 return ret; 1054 } 1055 1056 static int 1057 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1058 { 1059 struct hns3_adapter *hns = dev->data->dev_private; 1060 struct rte_eth_dev_data *data = dev->data; 1061 struct rte_eth_txmode *txmode; 1062 struct hns3_hw *hw = &hns->hw; 1063 int mask; 1064 int ret; 1065 1066 txmode = &data->dev_conf.txmode; 1067 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1068 hns3_warn(hw, 1069 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1070 "configuration is not supported! Ignore these two " 1071 "parameters: hw_vlan_reject_tagged(%d), " 1072 "hw_vlan_reject_untagged(%d)", 1073 txmode->hw_vlan_reject_tagged, 1074 txmode->hw_vlan_reject_untagged); 1075 1076 /* Apply vlan offload setting */ 1077 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK; 1078 ret = hns3_vlan_offload_set(dev, mask); 1079 if (ret) { 1080 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1081 ret); 1082 return ret; 1083 } 1084 1085 /* 1086 * If pvid config is not set in rte_eth_conf, driver needn't to set 1087 * VLAN pvid related configuration to hardware. 1088 */ 1089 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1090 return 0; 1091 1092 /* Apply pvid setting */ 1093 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1094 txmode->hw_vlan_insert_pvid); 1095 if (ret) 1096 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d", 1097 txmode->pvid, ret); 1098 1099 return ret; 1100 } 1101 1102 static int 1103 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1104 unsigned int tso_mss_max) 1105 { 1106 struct hns3_cfg_tso_status_cmd *req; 1107 struct hns3_cmd_desc desc; 1108 uint16_t tso_mss; 1109 1110 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1111 1112 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1113 1114 tso_mss = 0; 1115 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1116 tso_mss_min); 1117 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1118 1119 tso_mss = 0; 1120 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1121 tso_mss_max); 1122 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1123 1124 return hns3_cmd_send(hw, &desc, 1); 1125 } 1126 1127 static int 1128 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1129 uint16_t *allocated_size, bool is_alloc) 1130 { 1131 struct hns3_umv_spc_alc_cmd *req; 1132 struct hns3_cmd_desc desc; 1133 int ret; 1134 1135 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1136 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1137 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1138 req->space_size = rte_cpu_to_le_32(space_size); 1139 1140 ret = hns3_cmd_send(hw, &desc, 1); 1141 if (ret) { 1142 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1143 is_alloc ? "allocate" : "free", ret); 1144 return ret; 1145 } 1146 1147 if (is_alloc && allocated_size) 1148 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1149 1150 return 0; 1151 } 1152 1153 static int 1154 hns3_init_umv_space(struct hns3_hw *hw) 1155 { 1156 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1157 struct hns3_pf *pf = &hns->pf; 1158 uint16_t allocated_size = 0; 1159 int ret; 1160 1161 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1162 true); 1163 if (ret) 1164 return ret; 1165 1166 if (allocated_size < pf->wanted_umv_size) 1167 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1168 pf->wanted_umv_size, allocated_size); 1169 1170 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1171 pf->wanted_umv_size; 1172 pf->used_umv_size = 0; 1173 return 0; 1174 } 1175 1176 static int 1177 hns3_uninit_umv_space(struct hns3_hw *hw) 1178 { 1179 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1180 struct hns3_pf *pf = &hns->pf; 1181 int ret; 1182 1183 if (pf->max_umv_size == 0) 1184 return 0; 1185 1186 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1187 if (ret) 1188 return ret; 1189 1190 pf->max_umv_size = 0; 1191 1192 return 0; 1193 } 1194 1195 static bool 1196 hns3_is_umv_space_full(struct hns3_hw *hw) 1197 { 1198 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1199 struct hns3_pf *pf = &hns->pf; 1200 bool is_full; 1201 1202 is_full = (pf->used_umv_size >= pf->max_umv_size); 1203 1204 return is_full; 1205 } 1206 1207 static void 1208 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1209 { 1210 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1211 struct hns3_pf *pf = &hns->pf; 1212 1213 if (is_free) { 1214 if (pf->used_umv_size > 0) 1215 pf->used_umv_size--; 1216 } else 1217 pf->used_umv_size++; 1218 } 1219 1220 static void 1221 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1222 const uint8_t *addr, bool is_mc) 1223 { 1224 const unsigned char *mac_addr = addr; 1225 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1226 ((uint32_t)mac_addr[2] << 16) | 1227 ((uint32_t)mac_addr[1] << 8) | 1228 (uint32_t)mac_addr[0]; 1229 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1230 1231 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1232 if (is_mc) { 1233 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1234 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1235 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1236 } 1237 1238 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1239 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1240 } 1241 1242 static int 1243 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1244 uint8_t resp_code, 1245 enum hns3_mac_vlan_tbl_opcode op) 1246 { 1247 if (cmdq_resp) { 1248 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1249 cmdq_resp); 1250 return -EIO; 1251 } 1252 1253 if (op == HNS3_MAC_VLAN_ADD) { 1254 if (resp_code == 0 || resp_code == 1) { 1255 return 0; 1256 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1257 hns3_err(hw, "add mac addr failed for uc_overflow"); 1258 return -ENOSPC; 1259 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1260 hns3_err(hw, "add mac addr failed for mc_overflow"); 1261 return -ENOSPC; 1262 } 1263 1264 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1265 resp_code); 1266 return -EIO; 1267 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1268 if (resp_code == 0) { 1269 return 0; 1270 } else if (resp_code == 1) { 1271 hns3_dbg(hw, "remove mac addr failed for miss"); 1272 return -ENOENT; 1273 } 1274 1275 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1276 resp_code); 1277 return -EIO; 1278 } else if (op == HNS3_MAC_VLAN_LKUP) { 1279 if (resp_code == 0) { 1280 return 0; 1281 } else if (resp_code == 1) { 1282 hns3_dbg(hw, "lookup mac addr failed for miss"); 1283 return -ENOENT; 1284 } 1285 1286 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1287 resp_code); 1288 return -EIO; 1289 } 1290 1291 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1292 op); 1293 1294 return -EINVAL; 1295 } 1296 1297 static int 1298 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1299 struct hns3_mac_vlan_tbl_entry_cmd *req, 1300 struct hns3_cmd_desc *desc, bool is_mc) 1301 { 1302 uint8_t resp_code; 1303 uint16_t retval; 1304 int ret; 1305 1306 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true); 1307 if (is_mc) { 1308 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1309 memcpy(desc[0].data, req, 1310 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1311 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD, 1312 true); 1313 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1314 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD, 1315 true); 1316 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1317 } else { 1318 memcpy(desc[0].data, req, 1319 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1320 ret = hns3_cmd_send(hw, desc, 1); 1321 } 1322 if (ret) { 1323 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1324 ret); 1325 return ret; 1326 } 1327 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1328 retval = rte_le_to_cpu_16(desc[0].retval); 1329 1330 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1331 HNS3_MAC_VLAN_LKUP); 1332 } 1333 1334 static int 1335 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1336 struct hns3_mac_vlan_tbl_entry_cmd *req, 1337 struct hns3_cmd_desc *mc_desc) 1338 { 1339 uint8_t resp_code; 1340 uint16_t retval; 1341 int cfg_status; 1342 int ret; 1343 1344 if (mc_desc == NULL) { 1345 struct hns3_cmd_desc desc; 1346 1347 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false); 1348 memcpy(desc.data, req, 1349 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1350 ret = hns3_cmd_send(hw, &desc, 1); 1351 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1352 retval = rte_le_to_cpu_16(desc.retval); 1353 1354 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1355 HNS3_MAC_VLAN_ADD); 1356 } else { 1357 hns3_cmd_reuse_desc(&mc_desc[0], false); 1358 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1359 hns3_cmd_reuse_desc(&mc_desc[1], false); 1360 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1361 hns3_cmd_reuse_desc(&mc_desc[2], false); 1362 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1363 memcpy(mc_desc[0].data, req, 1364 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1365 mc_desc[0].retval = 0; 1366 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1367 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff; 1368 retval = rte_le_to_cpu_16(mc_desc[0].retval); 1369 1370 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1371 HNS3_MAC_VLAN_ADD); 1372 } 1373 1374 if (ret) { 1375 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1376 return ret; 1377 } 1378 1379 return cfg_status; 1380 } 1381 1382 static int 1383 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1384 struct hns3_mac_vlan_tbl_entry_cmd *req) 1385 { 1386 struct hns3_cmd_desc desc; 1387 uint8_t resp_code; 1388 uint16_t retval; 1389 int ret; 1390 1391 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1392 1393 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1394 1395 ret = hns3_cmd_send(hw, &desc, 1); 1396 if (ret) { 1397 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1398 return ret; 1399 } 1400 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1401 retval = rte_le_to_cpu_16(desc.retval); 1402 1403 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1404 HNS3_MAC_VLAN_REMOVE); 1405 } 1406 1407 static int 1408 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1409 { 1410 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1411 struct hns3_mac_vlan_tbl_entry_cmd req; 1412 struct hns3_pf *pf = &hns->pf; 1413 struct hns3_cmd_desc desc[3]; 1414 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1415 uint16_t egress_port = 0; 1416 uint8_t vf_id; 1417 int ret; 1418 1419 /* check if mac addr is valid */ 1420 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1421 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1422 mac_addr); 1423 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1424 mac_str); 1425 return -EINVAL; 1426 } 1427 1428 memset(&req, 0, sizeof(req)); 1429 1430 /* 1431 * In current version VF is not supported when PF is driven by DPDK 1432 * driver, just need to configure parameters for PF vport. 1433 */ 1434 vf_id = HNS3_PF_FUNC_ID; 1435 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1436 HNS3_MAC_EPORT_VFID_S, vf_id); 1437 1438 req.egress_port = rte_cpu_to_le_16(egress_port); 1439 1440 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1441 1442 /* 1443 * Lookup the mac address in the mac_vlan table, and add 1444 * it if the entry is inexistent. Repeated unicast entry 1445 * is not allowed in the mac vlan table. 1446 */ 1447 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false); 1448 if (ret == -ENOENT) { 1449 if (!hns3_is_umv_space_full(hw)) { 1450 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL); 1451 if (!ret) 1452 hns3_update_umv_space(hw, false); 1453 return ret; 1454 } 1455 1456 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1457 1458 return -ENOSPC; 1459 } 1460 1461 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1462 1463 /* check if we just hit the duplicate */ 1464 if (ret == 0) { 1465 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1466 return 0; 1467 } 1468 1469 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1470 mac_str); 1471 1472 return ret; 1473 } 1474 1475 static int 1476 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1477 { 1478 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1479 struct rte_ether_addr *addr; 1480 int ret; 1481 int i; 1482 1483 for (i = 0; i < hw->mc_addrs_num; i++) { 1484 addr = &hw->mc_addrs[i]; 1485 /* Check if there are duplicate addresses */ 1486 if (rte_is_same_ether_addr(addr, mac_addr)) { 1487 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1488 addr); 1489 hns3_err(hw, "failed to add mc mac addr, same addrs" 1490 "(%s) is added by the set_mc_mac_addr_list " 1491 "API", mac_str); 1492 return -EINVAL; 1493 } 1494 } 1495 1496 ret = hns3_add_mc_addr(hw, mac_addr); 1497 if (ret) { 1498 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1499 mac_addr); 1500 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 1501 mac_str, ret); 1502 } 1503 return ret; 1504 } 1505 1506 static int 1507 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1508 { 1509 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1510 int ret; 1511 1512 ret = hns3_remove_mc_addr(hw, mac_addr); 1513 if (ret) { 1514 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1515 mac_addr); 1516 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d", 1517 mac_str, ret); 1518 } 1519 return ret; 1520 } 1521 1522 static int 1523 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1524 uint32_t idx, __rte_unused uint32_t pool) 1525 { 1526 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1527 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1528 int ret; 1529 1530 rte_spinlock_lock(&hw->lock); 1531 1532 /* 1533 * In hns3 network engine adding UC and MC mac address with different 1534 * commands with firmware. We need to determine whether the input 1535 * address is a UC or a MC address to call different commands. 1536 * By the way, it is recommended calling the API function named 1537 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 1538 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 1539 * may affect the specifications of UC mac addresses. 1540 */ 1541 if (rte_is_multicast_ether_addr(mac_addr)) 1542 ret = hns3_add_mc_addr_common(hw, mac_addr); 1543 else 1544 ret = hns3_add_uc_addr_common(hw, mac_addr); 1545 1546 if (ret) { 1547 rte_spinlock_unlock(&hw->lock); 1548 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1549 mac_addr); 1550 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 1551 ret); 1552 return ret; 1553 } 1554 1555 if (idx == 0) 1556 hw->mac.default_addr_setted = true; 1557 rte_spinlock_unlock(&hw->lock); 1558 1559 return ret; 1560 } 1561 1562 static int 1563 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1564 { 1565 struct hns3_mac_vlan_tbl_entry_cmd req; 1566 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1567 int ret; 1568 1569 /* check if mac addr is valid */ 1570 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1571 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1572 mac_addr); 1573 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1574 mac_str); 1575 return -EINVAL; 1576 } 1577 1578 memset(&req, 0, sizeof(req)); 1579 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1580 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1581 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1582 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1583 return 0; 1584 else if (ret == 0) 1585 hns3_update_umv_space(hw, true); 1586 1587 return ret; 1588 } 1589 1590 static void 1591 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 1592 { 1593 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1594 /* index will be checked by upper level rte interface */ 1595 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 1596 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1597 int ret; 1598 1599 rte_spinlock_lock(&hw->lock); 1600 1601 if (rte_is_multicast_ether_addr(mac_addr)) 1602 ret = hns3_remove_mc_addr_common(hw, mac_addr); 1603 else 1604 ret = hns3_remove_uc_addr_common(hw, mac_addr); 1605 rte_spinlock_unlock(&hw->lock); 1606 if (ret) { 1607 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1608 mac_addr); 1609 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, 1610 ret); 1611 } 1612 } 1613 1614 static int 1615 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1616 struct rte_ether_addr *mac_addr) 1617 { 1618 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1619 struct rte_ether_addr *oaddr; 1620 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1621 bool default_addr_setted; 1622 bool rm_succes = false; 1623 int ret, ret_val; 1624 1625 /* 1626 * It has been guaranteed that input parameter named mac_addr is valid 1627 * address in the rte layer of DPDK framework. 1628 */ 1629 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1630 default_addr_setted = hw->mac.default_addr_setted; 1631 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr)) 1632 return 0; 1633 1634 rte_spinlock_lock(&hw->lock); 1635 if (default_addr_setted) { 1636 ret = hns3_remove_uc_addr_common(hw, oaddr); 1637 if (ret) { 1638 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1639 oaddr); 1640 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1641 mac_str, ret); 1642 rm_succes = false; 1643 } else 1644 rm_succes = true; 1645 } 1646 1647 ret = hns3_add_uc_addr_common(hw, mac_addr); 1648 if (ret) { 1649 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1650 mac_addr); 1651 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1652 goto err_add_uc_addr; 1653 } 1654 1655 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1656 if (ret) { 1657 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1658 goto err_pause_addr_cfg; 1659 } 1660 1661 rte_ether_addr_copy(mac_addr, 1662 (struct rte_ether_addr *)hw->mac.mac_addr); 1663 hw->mac.default_addr_setted = true; 1664 rte_spinlock_unlock(&hw->lock); 1665 1666 return 0; 1667 1668 err_pause_addr_cfg: 1669 ret_val = hns3_remove_uc_addr_common(hw, mac_addr); 1670 if (ret_val) { 1671 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1672 mac_addr); 1673 hns3_warn(hw, 1674 "Failed to roll back to del setted mac addr(%s): %d", 1675 mac_str, ret_val); 1676 } 1677 1678 err_add_uc_addr: 1679 if (rm_succes) { 1680 ret_val = hns3_add_uc_addr_common(hw, oaddr); 1681 if (ret_val) { 1682 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1683 oaddr); 1684 hns3_warn(hw, 1685 "Failed to restore old uc mac addr(%s): %d", 1686 mac_str, ret_val); 1687 hw->mac.default_addr_setted = false; 1688 } 1689 } 1690 rte_spinlock_unlock(&hw->lock); 1691 1692 return ret; 1693 } 1694 1695 static int 1696 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) 1697 { 1698 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1699 struct hns3_hw *hw = &hns->hw; 1700 struct rte_ether_addr *addr; 1701 int err = 0; 1702 int ret; 1703 int i; 1704 1705 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) { 1706 addr = &hw->data->mac_addrs[i]; 1707 if (rte_is_zero_ether_addr(addr)) 1708 continue; 1709 if (rte_is_multicast_ether_addr(addr)) 1710 ret = del ? hns3_remove_mc_addr(hw, addr) : 1711 hns3_add_mc_addr(hw, addr); 1712 else 1713 ret = del ? hns3_remove_uc_addr_common(hw, addr) : 1714 hns3_add_uc_addr_common(hw, addr); 1715 1716 if (ret) { 1717 err = ret; 1718 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1719 addr); 1720 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 1721 "ret = %d.", del ? "remove" : "restore", 1722 mac_str, i, ret); 1723 } 1724 } 1725 return err; 1726 } 1727 1728 static void 1729 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1730 { 1731 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1732 uint8_t word_num; 1733 uint8_t bit_num; 1734 1735 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1736 word_num = vfid / 32; 1737 bit_num = vfid % 32; 1738 if (clr) 1739 desc[1].data[word_num] &= 1740 rte_cpu_to_le_32(~(1UL << bit_num)); 1741 else 1742 desc[1].data[word_num] |= 1743 rte_cpu_to_le_32(1UL << bit_num); 1744 } else { 1745 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1746 bit_num = vfid % 32; 1747 if (clr) 1748 desc[2].data[word_num] &= 1749 rte_cpu_to_le_32(~(1UL << bit_num)); 1750 else 1751 desc[2].data[word_num] |= 1752 rte_cpu_to_le_32(1UL << bit_num); 1753 } 1754 } 1755 1756 static int 1757 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1758 { 1759 struct hns3_mac_vlan_tbl_entry_cmd req; 1760 struct hns3_cmd_desc desc[3]; 1761 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1762 uint8_t vf_id; 1763 int ret; 1764 1765 /* Check if mac addr is valid */ 1766 if (!rte_is_multicast_ether_addr(mac_addr)) { 1767 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1768 mac_addr); 1769 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1770 mac_str); 1771 return -EINVAL; 1772 } 1773 1774 memset(&req, 0, sizeof(req)); 1775 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1776 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1777 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1778 if (ret) { 1779 /* This mac addr do not exist, add new entry for it */ 1780 memset(desc[0].data, 0, sizeof(desc[0].data)); 1781 memset(desc[1].data, 0, sizeof(desc[0].data)); 1782 memset(desc[2].data, 0, sizeof(desc[0].data)); 1783 } 1784 1785 /* 1786 * In current version VF is not supported when PF is driven by DPDK 1787 * driver, just need to configure parameters for PF vport. 1788 */ 1789 vf_id = HNS3_PF_FUNC_ID; 1790 hns3_update_desc_vfid(desc, vf_id, false); 1791 ret = hns3_add_mac_vlan_tbl(hw, &req, desc); 1792 if (ret) { 1793 if (ret == -ENOSPC) 1794 hns3_err(hw, "mc mac vlan table is full"); 1795 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1796 mac_addr); 1797 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1798 } 1799 1800 return ret; 1801 } 1802 1803 static int 1804 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1805 { 1806 struct hns3_mac_vlan_tbl_entry_cmd req; 1807 struct hns3_cmd_desc desc[3]; 1808 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1809 uint8_t vf_id; 1810 int ret; 1811 1812 /* Check if mac addr is valid */ 1813 if (!rte_is_multicast_ether_addr(mac_addr)) { 1814 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1815 mac_addr); 1816 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1817 mac_str); 1818 return -EINVAL; 1819 } 1820 1821 memset(&req, 0, sizeof(req)); 1822 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1823 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1824 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1825 if (ret == 0) { 1826 /* 1827 * This mac addr exist, remove this handle's VFID for it. 1828 * In current version VF is not supported when PF is driven by 1829 * DPDK driver, just need to configure parameters for PF vport. 1830 */ 1831 vf_id = HNS3_PF_FUNC_ID; 1832 hns3_update_desc_vfid(desc, vf_id, true); 1833 1834 /* All the vfid is zero, so need to delete this entry */ 1835 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1836 } else if (ret == -ENOENT) { 1837 /* This mac addr doesn't exist. */ 1838 return 0; 1839 } 1840 1841 if (ret) { 1842 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1843 mac_addr); 1844 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1845 } 1846 1847 return ret; 1848 } 1849 1850 static int 1851 hns3_set_mc_addr_chk_param(struct hns3_hw *hw, 1852 struct rte_ether_addr *mc_addr_set, 1853 uint32_t nb_mc_addr) 1854 { 1855 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1856 struct rte_ether_addr *addr; 1857 uint32_t i; 1858 uint32_t j; 1859 1860 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 1861 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) " 1862 "invalid. valid range: 0~%d", 1863 nb_mc_addr, HNS3_MC_MACADDR_NUM); 1864 return -EINVAL; 1865 } 1866 1867 /* Check if input mac addresses are valid */ 1868 for (i = 0; i < nb_mc_addr; i++) { 1869 addr = &mc_addr_set[i]; 1870 if (!rte_is_multicast_ether_addr(addr)) { 1871 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1872 addr); 1873 hns3_err(hw, 1874 "failed to set mc mac addr, addr(%s) invalid.", 1875 mac_str); 1876 return -EINVAL; 1877 } 1878 1879 /* Check if there are duplicate addresses */ 1880 for (j = i + 1; j < nb_mc_addr; j++) { 1881 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1882 rte_ether_format_addr(mac_str, 1883 RTE_ETHER_ADDR_FMT_SIZE, 1884 addr); 1885 hns3_err(hw, "failed to set mc mac addr, " 1886 "addrs invalid. two same addrs(%s).", 1887 mac_str); 1888 return -EINVAL; 1889 } 1890 } 1891 1892 /* 1893 * Check if there are duplicate addresses between mac_addrs 1894 * and mc_addr_set 1895 */ 1896 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) { 1897 if (rte_is_same_ether_addr(addr, 1898 &hw->data->mac_addrs[j])) { 1899 rte_ether_format_addr(mac_str, 1900 RTE_ETHER_ADDR_FMT_SIZE, 1901 addr); 1902 hns3_err(hw, "failed to set mc mac addr, " 1903 "addrs invalid. addrs(%s) has already " 1904 "configured in mac_addr add API", 1905 mac_str); 1906 return -EINVAL; 1907 } 1908 } 1909 } 1910 1911 return 0; 1912 } 1913 1914 static void 1915 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw, 1916 struct rte_ether_addr *mc_addr_set, 1917 int mc_addr_num, 1918 struct rte_ether_addr *reserved_addr_list, 1919 int *reserved_addr_num, 1920 struct rte_ether_addr *add_addr_list, 1921 int *add_addr_num, 1922 struct rte_ether_addr *rm_addr_list, 1923 int *rm_addr_num) 1924 { 1925 struct rte_ether_addr *addr; 1926 int current_addr_num; 1927 int reserved_num = 0; 1928 int add_num = 0; 1929 int rm_num = 0; 1930 int num; 1931 int i; 1932 int j; 1933 bool same_addr; 1934 1935 /* Calculate the mc mac address list that should be removed */ 1936 current_addr_num = hw->mc_addrs_num; 1937 for (i = 0; i < current_addr_num; i++) { 1938 addr = &hw->mc_addrs[i]; 1939 same_addr = false; 1940 for (j = 0; j < mc_addr_num; j++) { 1941 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1942 same_addr = true; 1943 break; 1944 } 1945 } 1946 1947 if (!same_addr) { 1948 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]); 1949 rm_num++; 1950 } else { 1951 rte_ether_addr_copy(addr, 1952 &reserved_addr_list[reserved_num]); 1953 reserved_num++; 1954 } 1955 } 1956 1957 /* Calculate the mc mac address list that should be added */ 1958 for (i = 0; i < mc_addr_num; i++) { 1959 addr = &mc_addr_set[i]; 1960 same_addr = false; 1961 for (j = 0; j < current_addr_num; j++) { 1962 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) { 1963 same_addr = true; 1964 break; 1965 } 1966 } 1967 1968 if (!same_addr) { 1969 rte_ether_addr_copy(addr, &add_addr_list[add_num]); 1970 add_num++; 1971 } 1972 } 1973 1974 /* Reorder the mc mac address list maintained by driver */ 1975 for (i = 0; i < reserved_num; i++) 1976 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]); 1977 1978 for (i = 0; i < rm_num; i++) { 1979 num = reserved_num + i; 1980 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]); 1981 } 1982 1983 *reserved_addr_num = reserved_num; 1984 *add_addr_num = add_num; 1985 *rm_addr_num = rm_num; 1986 } 1987 1988 static int 1989 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, 1990 struct rte_ether_addr *mc_addr_set, 1991 uint32_t nb_mc_addr) 1992 { 1993 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1994 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM]; 1995 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM]; 1996 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM]; 1997 struct rte_ether_addr *addr; 1998 int reserved_addr_num; 1999 int add_addr_num; 2000 int rm_addr_num; 2001 int mc_addr_num; 2002 int num; 2003 int ret; 2004 int i; 2005 2006 /* Check if input parameters are valid */ 2007 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 2008 if (ret) 2009 return ret; 2010 2011 rte_spinlock_lock(&hw->lock); 2012 2013 /* 2014 * Calculate the mc mac address lists those should be removed and be 2015 * added, Reorder the mc mac address list maintained by driver. 2016 */ 2017 mc_addr_num = (int)nb_mc_addr; 2018 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num, 2019 reserved_addr_list, &reserved_addr_num, 2020 add_addr_list, &add_addr_num, 2021 rm_addr_list, &rm_addr_num); 2022 2023 /* Remove mc mac addresses */ 2024 for (i = 0; i < rm_addr_num; i++) { 2025 num = rm_addr_num - i - 1; 2026 addr = &rm_addr_list[num]; 2027 ret = hns3_remove_mc_addr(hw, addr); 2028 if (ret) { 2029 rte_spinlock_unlock(&hw->lock); 2030 return ret; 2031 } 2032 hw->mc_addrs_num--; 2033 } 2034 2035 /* Add mc mac addresses */ 2036 for (i = 0; i < add_addr_num; i++) { 2037 addr = &add_addr_list[i]; 2038 ret = hns3_add_mc_addr(hw, addr); 2039 if (ret) { 2040 rte_spinlock_unlock(&hw->lock); 2041 return ret; 2042 } 2043 2044 num = reserved_addr_num + i; 2045 rte_ether_addr_copy(addr, &hw->mc_addrs[num]); 2046 hw->mc_addrs_num++; 2047 } 2048 rte_spinlock_unlock(&hw->lock); 2049 2050 return 0; 2051 } 2052 2053 static int 2054 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 2055 { 2056 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2057 struct hns3_hw *hw = &hns->hw; 2058 struct rte_ether_addr *addr; 2059 int err = 0; 2060 int ret; 2061 int i; 2062 2063 for (i = 0; i < hw->mc_addrs_num; i++) { 2064 addr = &hw->mc_addrs[i]; 2065 if (!rte_is_multicast_ether_addr(addr)) 2066 continue; 2067 if (del) 2068 ret = hns3_remove_mc_addr(hw, addr); 2069 else 2070 ret = hns3_add_mc_addr(hw, addr); 2071 if (ret) { 2072 err = ret; 2073 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2074 addr); 2075 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d", 2076 del ? "Remove" : "Restore", mac_str, ret); 2077 } 2078 } 2079 return err; 2080 } 2081 2082 static int 2083 hns3_check_mq_mode(struct rte_eth_dev *dev) 2084 { 2085 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 2086 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 2087 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2088 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2089 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 2090 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 2091 uint8_t num_tc; 2092 int max_tc = 0; 2093 int i; 2094 2095 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 2096 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 2097 2098 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2099 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. " 2100 "rx_mq_mode = %d", rx_mq_mode); 2101 return -EINVAL; 2102 } 2103 2104 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB || 2105 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2106 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB " 2107 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d", 2108 rx_mq_mode, tx_mq_mode); 2109 return -EINVAL; 2110 } 2111 2112 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) { 2113 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 2114 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 2115 dcb_rx_conf->nb_tcs, pf->tc_max); 2116 return -EINVAL; 2117 } 2118 2119 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 2120 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 2121 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, " 2122 "nb_tcs(%d) != %d or %d in rx direction.", 2123 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 2124 return -EINVAL; 2125 } 2126 2127 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 2128 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 2129 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 2130 return -EINVAL; 2131 } 2132 2133 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 2134 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 2135 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, " 2136 "is not equal to one in tx direction.", 2137 i, dcb_rx_conf->dcb_tc[i]); 2138 return -EINVAL; 2139 } 2140 if (dcb_rx_conf->dcb_tc[i] > max_tc) 2141 max_tc = dcb_rx_conf->dcb_tc[i]; 2142 } 2143 2144 num_tc = max_tc + 1; 2145 if (num_tc > dcb_rx_conf->nb_tcs) { 2146 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 2147 num_tc, dcb_rx_conf->nb_tcs); 2148 return -EINVAL; 2149 } 2150 } 2151 2152 return 0; 2153 } 2154 2155 static int 2156 hns3_check_dcb_cfg(struct rte_eth_dev *dev) 2157 { 2158 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2159 2160 if (!hns3_dev_dcb_supported(hw)) { 2161 hns3_err(hw, "this port does not support dcb configurations."); 2162 return -EOPNOTSUPP; 2163 } 2164 2165 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 2166 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 2167 return -EOPNOTSUPP; 2168 } 2169 2170 /* Check multiple queue mode */ 2171 return hns3_check_mq_mode(dev); 2172 } 2173 2174 static int 2175 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap, 2176 enum hns3_ring_type queue_type, uint16_t queue_id) 2177 { 2178 struct hns3_cmd_desc desc; 2179 struct hns3_ctrl_vector_chain_cmd *req = 2180 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 2181 enum hns3_cmd_status status; 2182 enum hns3_opcode_type op; 2183 uint16_t tqp_type_and_id = 0; 2184 const char *op_str; 2185 uint16_t type; 2186 uint16_t gl; 2187 2188 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 2189 hns3_cmd_setup_basic_desc(&desc, op, false); 2190 req->int_vector_id = vector_id; 2191 2192 if (queue_type == HNS3_RING_TYPE_RX) 2193 gl = HNS3_RING_GL_RX; 2194 else 2195 gl = HNS3_RING_GL_TX; 2196 2197 type = queue_type; 2198 2199 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 2200 type); 2201 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 2202 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 2203 gl); 2204 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 2205 req->int_cause_num = 1; 2206 op_str = mmap ? "Map" : "Unmap"; 2207 status = hns3_cmd_send(hw, &desc, 1); 2208 if (status) { 2209 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.", 2210 op_str, queue_id, req->int_vector_id, status); 2211 return status; 2212 } 2213 2214 return 0; 2215 } 2216 2217 static int 2218 hns3_init_ring_with_vector(struct hns3_hw *hw) 2219 { 2220 uint16_t vec; 2221 int ret; 2222 int i; 2223 2224 /* 2225 * In hns3 network engine, vector 0 is always the misc interrupt of this 2226 * function, vector 1~N can be used respectively for the queues of the 2227 * function. Tx and Rx queues with the same number share the interrupt 2228 * vector. In the initialization clearing the all hardware mapping 2229 * relationship configurations between queues and interrupt vectors is 2230 * needed, so some error caused by the residual configurations, such as 2231 * the unexpected Tx interrupt, can be avoid. 2232 */ 2233 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 2234 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 2235 vec = vec - 1; /* the last interrupt is reserved */ 2236 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 2237 for (i = 0; i < hw->intr_tqps_num; i++) { 2238 /* 2239 * Set gap limiter/rate limiter/quanity limiter algorithm 2240 * configuration for interrupt coalesce of queue's interrupt. 2241 */ 2242 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 2243 HNS3_TQP_INTR_GL_DEFAULT); 2244 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 2245 HNS3_TQP_INTR_GL_DEFAULT); 2246 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 2247 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 2248 2249 ret = hns3_bind_ring_with_vector(hw, vec, false, 2250 HNS3_RING_TYPE_TX, i); 2251 if (ret) { 2252 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with " 2253 "vector: %d, ret=%d", i, vec, ret); 2254 return ret; 2255 } 2256 2257 ret = hns3_bind_ring_with_vector(hw, vec, false, 2258 HNS3_RING_TYPE_RX, i); 2259 if (ret) { 2260 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with " 2261 "vector: %d, ret=%d", i, vec, ret); 2262 return ret; 2263 } 2264 } 2265 2266 return 0; 2267 } 2268 2269 static int 2270 hns3_dev_configure(struct rte_eth_dev *dev) 2271 { 2272 struct hns3_adapter *hns = dev->data->dev_private; 2273 struct rte_eth_conf *conf = &dev->data->dev_conf; 2274 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 2275 struct hns3_hw *hw = &hns->hw; 2276 struct hns3_rss_conf *rss_cfg = &hw->rss_info; 2277 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2278 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2279 struct rte_eth_rss_conf rss_conf; 2280 uint16_t mtu; 2281 bool gro_en; 2282 int ret; 2283 2284 /* 2285 * Hardware does not support individually enable/disable/reset the Tx or 2286 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx 2287 * and Rx queues at the same time. When the numbers of Tx queues 2288 * allocated by upper applications are not equal to the numbers of Rx 2289 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers 2290 * of Tx/Rx queues. otherwise, network engine can not work as usual. But 2291 * these fake queues are imperceptible, and can not be used by upper 2292 * applications. 2293 */ 2294 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2295 if (ret) { 2296 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret); 2297 return ret; 2298 } 2299 2300 hw->adapter_state = HNS3_NIC_CONFIGURING; 2301 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 2302 hns3_err(hw, "setting link speed/duplex not supported"); 2303 ret = -EINVAL; 2304 goto cfg_err; 2305 } 2306 2307 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { 2308 ret = hns3_check_dcb_cfg(dev); 2309 if (ret) 2310 goto cfg_err; 2311 } 2312 2313 /* When RSS is not configured, redirect the packet queue 0 */ 2314 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 2315 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2316 rss_conf = conf->rx_adv_conf.rss_conf; 2317 if (rss_conf.rss_key == NULL) { 2318 rss_conf.rss_key = rss_cfg->key; 2319 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE; 2320 } 2321 2322 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2323 if (ret) 2324 goto cfg_err; 2325 } 2326 2327 /* 2328 * If jumbo frames are enabled, MTU needs to be refreshed 2329 * according to the maximum RX packet length. 2330 */ 2331 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 2332 /* 2333 * Security of max_rx_pkt_len is guaranteed in dpdk frame. 2334 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it 2335 * can safely assign to "uint16_t" type variable. 2336 */ 2337 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len); 2338 ret = hns3_dev_mtu_set(dev, mtu); 2339 if (ret) 2340 goto cfg_err; 2341 dev->data->mtu = mtu; 2342 } 2343 2344 ret = hns3_dev_configure_vlan(dev); 2345 if (ret) 2346 goto cfg_err; 2347 2348 /* config hardware GRO */ 2349 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 2350 ret = hns3_config_gro(hw, gro_en); 2351 if (ret) 2352 goto cfg_err; 2353 2354 hw->adapter_state = HNS3_NIC_CONFIGURED; 2355 2356 return 0; 2357 2358 cfg_err: 2359 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2360 hw->adapter_state = HNS3_NIC_INITIALIZED; 2361 2362 return ret; 2363 } 2364 2365 static int 2366 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2367 { 2368 struct hns3_config_max_frm_size_cmd *req; 2369 struct hns3_cmd_desc desc; 2370 2371 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2372 2373 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2374 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2375 req->min_frm_size = RTE_ETHER_MIN_LEN; 2376 2377 return hns3_cmd_send(hw, &desc, 1); 2378 } 2379 2380 static int 2381 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2382 { 2383 int ret; 2384 2385 ret = hns3_set_mac_mtu(hw, mps); 2386 if (ret) { 2387 hns3_err(hw, "Failed to set mtu, ret = %d", ret); 2388 return ret; 2389 } 2390 2391 ret = hns3_buffer_alloc(hw); 2392 if (ret) 2393 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret); 2394 2395 return ret; 2396 } 2397 2398 static int 2399 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2400 { 2401 struct hns3_adapter *hns = dev->data->dev_private; 2402 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2403 struct hns3_hw *hw = &hns->hw; 2404 bool is_jumbo_frame; 2405 int ret; 2406 2407 if (dev->data->dev_started) { 2408 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2409 "before configuration", dev->data->port_id); 2410 return -EBUSY; 2411 } 2412 2413 rte_spinlock_lock(&hw->lock); 2414 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false; 2415 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2416 2417 /* 2418 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2419 * assign to "uint16_t" type variable. 2420 */ 2421 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2422 if (ret) { 2423 rte_spinlock_unlock(&hw->lock); 2424 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2425 dev->data->port_id, mtu, ret); 2426 return ret; 2427 } 2428 hns->pf.mps = (uint16_t)frame_size; 2429 if (is_jumbo_frame) 2430 dev->data->dev_conf.rxmode.offloads |= 2431 DEV_RX_OFFLOAD_JUMBO_FRAME; 2432 else 2433 dev->data->dev_conf.rxmode.offloads &= 2434 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2435 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2436 rte_spinlock_unlock(&hw->lock); 2437 2438 return 0; 2439 } 2440 2441 static int 2442 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 2443 { 2444 struct hns3_adapter *hns = eth_dev->data->dev_private; 2445 struct hns3_hw *hw = &hns->hw; 2446 uint16_t queue_num = hw->tqps_num; 2447 2448 /* 2449 * In interrupt mode, 'max_rx_queues' is set based on the number of 2450 * MSI-X interrupt resources of the hardware. 2451 */ 2452 if (hw->data->dev_conf.intr_conf.rxq == 1) 2453 queue_num = hw->intr_tqps_num; 2454 2455 info->max_rx_queues = queue_num; 2456 info->max_tx_queues = hw->tqps_num; 2457 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 2458 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 2459 info->max_mac_addrs = HNS3_UC_MACADDR_NUM; 2460 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 2461 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 2462 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 2463 DEV_RX_OFFLOAD_TCP_CKSUM | 2464 DEV_RX_OFFLOAD_UDP_CKSUM | 2465 DEV_RX_OFFLOAD_SCTP_CKSUM | 2466 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2467 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 2468 DEV_RX_OFFLOAD_KEEP_CRC | 2469 DEV_RX_OFFLOAD_SCATTER | 2470 DEV_RX_OFFLOAD_VLAN_STRIP | 2471 DEV_RX_OFFLOAD_VLAN_FILTER | 2472 DEV_RX_OFFLOAD_JUMBO_FRAME | 2473 DEV_RX_OFFLOAD_RSS_HASH | 2474 DEV_RX_OFFLOAD_TCP_LRO); 2475 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 2476 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2477 DEV_TX_OFFLOAD_IPV4_CKSUM | 2478 DEV_TX_OFFLOAD_TCP_CKSUM | 2479 DEV_TX_OFFLOAD_UDP_CKSUM | 2480 DEV_TX_OFFLOAD_SCTP_CKSUM | 2481 DEV_TX_OFFLOAD_MULTI_SEGS | 2482 DEV_TX_OFFLOAD_TCP_TSO | 2483 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 2484 DEV_TX_OFFLOAD_GRE_TNL_TSO | 2485 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 2486 info->tx_queue_offload_capa | 2487 hns3_txvlan_cap_get(hw)); 2488 2489 info->rx_desc_lim = (struct rte_eth_desc_lim) { 2490 .nb_max = HNS3_MAX_RING_DESC, 2491 .nb_min = HNS3_MIN_RING_DESC, 2492 .nb_align = HNS3_ALIGN_RING_DESC, 2493 }; 2494 2495 info->tx_desc_lim = (struct rte_eth_desc_lim) { 2496 .nb_max = HNS3_MAX_RING_DESC, 2497 .nb_min = HNS3_MIN_RING_DESC, 2498 .nb_align = HNS3_ALIGN_RING_DESC, 2499 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 2500 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT, 2501 }; 2502 2503 info->default_rxconf = (struct rte_eth_rxconf) { 2504 /* 2505 * If there are no available Rx buffer descriptors, incoming 2506 * packets are always dropped by hardware based on hns3 network 2507 * engine. 2508 */ 2509 .rx_drop_en = 1, 2510 }; 2511 2512 info->vmdq_queue_num = 0; 2513 2514 info->reta_size = HNS3_RSS_IND_TBL_SIZE; 2515 info->hash_key_size = HNS3_RSS_KEY_SIZE; 2516 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 2517 2518 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2519 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2520 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2521 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2522 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2523 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2524 2525 return 0; 2526 } 2527 2528 static int 2529 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2530 size_t fw_size) 2531 { 2532 struct hns3_adapter *hns = eth_dev->data->dev_private; 2533 struct hns3_hw *hw = &hns->hw; 2534 uint32_t version = hw->fw_version; 2535 int ret; 2536 2537 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2538 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2539 HNS3_FW_VERSION_BYTE3_S), 2540 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2541 HNS3_FW_VERSION_BYTE2_S), 2542 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2543 HNS3_FW_VERSION_BYTE1_S), 2544 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2545 HNS3_FW_VERSION_BYTE0_S)); 2546 ret += 1; /* add the size of '\0' */ 2547 if (fw_size < (uint32_t)ret) 2548 return ret; 2549 else 2550 return 0; 2551 } 2552 2553 static int 2554 hns3_dev_link_update(struct rte_eth_dev *eth_dev, 2555 __rte_unused int wait_to_complete) 2556 { 2557 struct hns3_adapter *hns = eth_dev->data->dev_private; 2558 struct hns3_hw *hw = &hns->hw; 2559 struct hns3_mac *mac = &hw->mac; 2560 struct rte_eth_link new_link; 2561 2562 if (!hns3_is_reset_pending(hns)) { 2563 hns3_update_speed_duplex(eth_dev); 2564 hns3_update_link_status(hw); 2565 } 2566 2567 memset(&new_link, 0, sizeof(new_link)); 2568 switch (mac->link_speed) { 2569 case ETH_SPEED_NUM_10M: 2570 case ETH_SPEED_NUM_100M: 2571 case ETH_SPEED_NUM_1G: 2572 case ETH_SPEED_NUM_10G: 2573 case ETH_SPEED_NUM_25G: 2574 case ETH_SPEED_NUM_40G: 2575 case ETH_SPEED_NUM_50G: 2576 case ETH_SPEED_NUM_100G: 2577 case ETH_SPEED_NUM_200G: 2578 new_link.link_speed = mac->link_speed; 2579 break; 2580 default: 2581 new_link.link_speed = ETH_SPEED_NUM_100M; 2582 break; 2583 } 2584 2585 new_link.link_duplex = mac->link_duplex; 2586 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2587 new_link.link_autoneg = 2588 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2589 2590 return rte_eth_linkstatus_set(eth_dev, &new_link); 2591 } 2592 2593 static int 2594 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2595 { 2596 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2597 struct hns3_pf *pf = &hns->pf; 2598 2599 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2600 return -EINVAL; 2601 2602 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2603 2604 return 0; 2605 } 2606 2607 static int 2608 hns3_query_function_status(struct hns3_hw *hw) 2609 { 2610 #define HNS3_QUERY_MAX_CNT 10 2611 #define HNS3_QUERY_SLEEP_MSCOEND 1 2612 struct hns3_func_status_cmd *req; 2613 struct hns3_cmd_desc desc; 2614 int timeout = 0; 2615 int ret; 2616 2617 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2618 req = (struct hns3_func_status_cmd *)desc.data; 2619 2620 do { 2621 ret = hns3_cmd_send(hw, &desc, 1); 2622 if (ret) { 2623 PMD_INIT_LOG(ERR, "query function status failed %d", 2624 ret); 2625 return ret; 2626 } 2627 2628 /* Check pf reset is done */ 2629 if (req->pf_state) 2630 break; 2631 2632 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2633 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2634 2635 return hns3_parse_func_status(hw, req); 2636 } 2637 2638 static int 2639 hns3_query_pf_resource(struct hns3_hw *hw) 2640 { 2641 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2642 struct hns3_pf *pf = &hns->pf; 2643 struct hns3_pf_res_cmd *req; 2644 struct hns3_cmd_desc desc; 2645 int ret; 2646 2647 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 2648 ret = hns3_cmd_send(hw, &desc, 1); 2649 if (ret) { 2650 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 2651 return ret; 2652 } 2653 2654 req = (struct hns3_pf_res_cmd *)desc.data; 2655 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num); 2656 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 2657 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC); 2658 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 2659 2660 if (req->tx_buf_size) 2661 pf->tx_buf_size = 2662 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 2663 else 2664 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 2665 2666 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 2667 2668 if (req->dv_buf_size) 2669 pf->dv_buf_size = 2670 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 2671 else 2672 pf->dv_buf_size = HNS3_DEFAULT_DV; 2673 2674 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 2675 2676 hw->num_msi = 2677 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number), 2678 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 2679 2680 return 0; 2681 } 2682 2683 static void 2684 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 2685 { 2686 struct hns3_cfg_param_cmd *req; 2687 uint64_t mac_addr_tmp_high; 2688 uint64_t mac_addr_tmp; 2689 uint32_t i; 2690 2691 req = (struct hns3_cfg_param_cmd *)desc[0].data; 2692 2693 /* get the configuration */ 2694 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2695 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S); 2696 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2697 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 2698 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2699 HNS3_CFG_TQP_DESC_N_M, 2700 HNS3_CFG_TQP_DESC_N_S); 2701 2702 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2703 HNS3_CFG_PHY_ADDR_M, 2704 HNS3_CFG_PHY_ADDR_S); 2705 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2706 HNS3_CFG_MEDIA_TP_M, 2707 HNS3_CFG_MEDIA_TP_S); 2708 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2709 HNS3_CFG_RX_BUF_LEN_M, 2710 HNS3_CFG_RX_BUF_LEN_S); 2711 /* get mac address */ 2712 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 2713 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2714 HNS3_CFG_MAC_ADDR_H_M, 2715 HNS3_CFG_MAC_ADDR_H_S); 2716 2717 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 2718 2719 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2720 HNS3_CFG_DEFAULT_SPEED_M, 2721 HNS3_CFG_DEFAULT_SPEED_S); 2722 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2723 HNS3_CFG_RSS_SIZE_M, 2724 HNS3_CFG_RSS_SIZE_S); 2725 2726 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2727 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 2728 2729 req = (struct hns3_cfg_param_cmd *)desc[1].data; 2730 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 2731 2732 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2733 HNS3_CFG_SPEED_ABILITY_M, 2734 HNS3_CFG_SPEED_ABILITY_S); 2735 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2736 HNS3_CFG_UMV_TBL_SPACE_M, 2737 HNS3_CFG_UMV_TBL_SPACE_S); 2738 if (!cfg->umv_space) 2739 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 2740 } 2741 2742 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 2743 * @hw: pointer to struct hns3_hw 2744 * @hcfg: the config structure to be getted 2745 */ 2746 static int 2747 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 2748 { 2749 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 2750 struct hns3_cfg_param_cmd *req; 2751 uint32_t offset; 2752 uint32_t i; 2753 int ret; 2754 2755 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 2756 offset = 0; 2757 req = (struct hns3_cfg_param_cmd *)desc[i].data; 2758 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 2759 true); 2760 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 2761 i * HNS3_CFG_RD_LEN_BYTES); 2762 /* Len should be divided by 4 when send to hardware */ 2763 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 2764 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 2765 req->offset = rte_cpu_to_le_32(offset); 2766 } 2767 2768 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 2769 if (ret) { 2770 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 2771 return ret; 2772 } 2773 2774 hns3_parse_cfg(hcfg, desc); 2775 2776 return 0; 2777 } 2778 2779 static int 2780 hns3_parse_speed(int speed_cmd, uint32_t *speed) 2781 { 2782 switch (speed_cmd) { 2783 case HNS3_CFG_SPEED_10M: 2784 *speed = ETH_SPEED_NUM_10M; 2785 break; 2786 case HNS3_CFG_SPEED_100M: 2787 *speed = ETH_SPEED_NUM_100M; 2788 break; 2789 case HNS3_CFG_SPEED_1G: 2790 *speed = ETH_SPEED_NUM_1G; 2791 break; 2792 case HNS3_CFG_SPEED_10G: 2793 *speed = ETH_SPEED_NUM_10G; 2794 break; 2795 case HNS3_CFG_SPEED_25G: 2796 *speed = ETH_SPEED_NUM_25G; 2797 break; 2798 case HNS3_CFG_SPEED_40G: 2799 *speed = ETH_SPEED_NUM_40G; 2800 break; 2801 case HNS3_CFG_SPEED_50G: 2802 *speed = ETH_SPEED_NUM_50G; 2803 break; 2804 case HNS3_CFG_SPEED_100G: 2805 *speed = ETH_SPEED_NUM_100G; 2806 break; 2807 case HNS3_CFG_SPEED_200G: 2808 *speed = ETH_SPEED_NUM_200G; 2809 break; 2810 default: 2811 return -EINVAL; 2812 } 2813 2814 return 0; 2815 } 2816 2817 static void 2818 hns3_set_default_dev_specifications(struct hns3_hw *hw) 2819 { 2820 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 2821 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 2822 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 2823 hw->max_tm_rate = HNS3_ETHER_MAX_RATE; 2824 } 2825 2826 static void 2827 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 2828 { 2829 struct hns3_dev_specs_0_cmd *req0; 2830 2831 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 2832 2833 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 2834 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 2835 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 2836 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); 2837 } 2838 2839 static int 2840 hns3_query_dev_specifications(struct hns3_hw *hw) 2841 { 2842 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 2843 int ret; 2844 int i; 2845 2846 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2847 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 2848 true); 2849 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 2850 } 2851 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 2852 2853 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 2854 if (ret) 2855 return ret; 2856 2857 hns3_parse_dev_specifications(hw, desc); 2858 2859 return 0; 2860 } 2861 2862 static int 2863 hns3_get_capability(struct hns3_hw *hw) 2864 { 2865 struct rte_pci_device *pci_dev; 2866 struct rte_eth_dev *eth_dev; 2867 uint16_t device_id; 2868 uint8_t revision; 2869 int ret; 2870 2871 eth_dev = &rte_eth_devices[hw->data->port_id]; 2872 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2873 device_id = pci_dev->id.device_id; 2874 2875 if (device_id == HNS3_DEV_ID_25GE_RDMA || 2876 device_id == HNS3_DEV_ID_50GE_RDMA || 2877 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || 2878 device_id == HNS3_DEV_ID_200G_RDMA) 2879 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); 2880 2881 /* Get PCI revision id */ 2882 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 2883 HNS3_PCI_REVISION_ID); 2884 if (ret != HNS3_PCI_REVISION_ID_LEN) { 2885 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 2886 ret); 2887 return -EIO; 2888 } 2889 hw->revision = revision; 2890 2891 if (revision < PCI_REVISION_ID_HIP09_A) { 2892 hns3_set_default_dev_specifications(hw); 2893 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 2894 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL; 2895 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 2896 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 2897 return 0; 2898 } 2899 2900 ret = hns3_query_dev_specifications(hw); 2901 if (ret) { 2902 PMD_INIT_LOG(ERR, 2903 "failed to query dev specifications, ret = %d", 2904 ret); 2905 return ret; 2906 } 2907 2908 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 2909 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL; 2910 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 2911 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 2912 2913 return 0; 2914 } 2915 2916 static int 2917 hns3_get_board_configuration(struct hns3_hw *hw) 2918 { 2919 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2920 struct hns3_pf *pf = &hns->pf; 2921 struct hns3_cfg cfg; 2922 int ret; 2923 2924 ret = hns3_get_board_cfg(hw, &cfg); 2925 if (ret) { 2926 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 2927 return ret; 2928 } 2929 2930 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER && 2931 !hns3_dev_copper_supported(hw)) { 2932 PMD_INIT_LOG(ERR, "media type is copper, not supported."); 2933 return -EOPNOTSUPP; 2934 } 2935 2936 hw->mac.media_type = cfg.media_type; 2937 hw->rss_size_max = cfg.rss_size_max; 2938 hw->rss_dis_flag = false; 2939 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 2940 hw->mac.phy_addr = cfg.phy_addr; 2941 hw->mac.default_addr_setted = false; 2942 hw->num_tx_desc = cfg.tqp_desc_num; 2943 hw->num_rx_desc = cfg.tqp_desc_num; 2944 hw->dcb_info.num_pg = 1; 2945 hw->dcb_info.hw_pfc_map = 0; 2946 2947 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 2948 if (ret) { 2949 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d", 2950 cfg.default_speed, ret); 2951 return ret; 2952 } 2953 2954 pf->tc_max = cfg.tc_num; 2955 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 2956 PMD_INIT_LOG(WARNING, 2957 "Get TC num(%u) from flash, set TC num to 1", 2958 pf->tc_max); 2959 pf->tc_max = 1; 2960 } 2961 2962 /* Dev does not support DCB */ 2963 if (!hns3_dev_dcb_supported(hw)) { 2964 pf->tc_max = 1; 2965 pf->pfc_max = 0; 2966 } else 2967 pf->pfc_max = pf->tc_max; 2968 2969 hw->dcb_info.num_tc = 1; 2970 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 2971 hw->tqps_num / hw->dcb_info.num_tc); 2972 hns3_set_bit(hw->hw_tc_map, 0, 1); 2973 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 2974 2975 pf->wanted_umv_size = cfg.umv_space; 2976 2977 return ret; 2978 } 2979 2980 static int 2981 hns3_get_configuration(struct hns3_hw *hw) 2982 { 2983 int ret; 2984 2985 ret = hns3_query_function_status(hw); 2986 if (ret) { 2987 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 2988 return ret; 2989 } 2990 2991 /* Get device capability */ 2992 ret = hns3_get_capability(hw); 2993 if (ret) { 2994 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 2995 return ret; 2996 } 2997 2998 /* Get pf resource */ 2999 ret = hns3_query_pf_resource(hw); 3000 if (ret) { 3001 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 3002 return ret; 3003 } 3004 3005 ret = hns3_get_board_configuration(hw); 3006 if (ret) 3007 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret); 3008 3009 return ret; 3010 } 3011 3012 static int 3013 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 3014 uint16_t tqp_vid, bool is_pf) 3015 { 3016 struct hns3_tqp_map_cmd *req; 3017 struct hns3_cmd_desc desc; 3018 int ret; 3019 3020 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 3021 3022 req = (struct hns3_tqp_map_cmd *)desc.data; 3023 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 3024 req->tqp_vf = func_id; 3025 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 3026 if (!is_pf) 3027 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 3028 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 3029 3030 ret = hns3_cmd_send(hw, &desc, 1); 3031 if (ret) 3032 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 3033 3034 return ret; 3035 } 3036 3037 static int 3038 hns3_map_tqp(struct hns3_hw *hw) 3039 { 3040 uint16_t tqps_num = hw->total_tqps_num; 3041 uint16_t func_id; 3042 uint16_t tqp_id; 3043 bool is_pf; 3044 int num; 3045 int ret; 3046 int i; 3047 3048 /* 3049 * In current version VF is not supported when PF is driven by DPDK 3050 * driver, so we allocate tqps to PF as much as possible. 3051 */ 3052 tqp_id = 0; 3053 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC); 3054 for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) { 3055 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false; 3056 for (i = 0; 3057 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) { 3058 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i, 3059 is_pf); 3060 if (ret) 3061 return ret; 3062 } 3063 } 3064 3065 return 0; 3066 } 3067 3068 static int 3069 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 3070 { 3071 struct hns3_config_mac_speed_dup_cmd *req; 3072 struct hns3_cmd_desc desc; 3073 int ret; 3074 3075 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 3076 3077 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 3078 3079 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 3080 3081 switch (speed) { 3082 case ETH_SPEED_NUM_10M: 3083 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3084 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 3085 break; 3086 case ETH_SPEED_NUM_100M: 3087 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3088 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 3089 break; 3090 case ETH_SPEED_NUM_1G: 3091 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3092 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 3093 break; 3094 case ETH_SPEED_NUM_10G: 3095 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3096 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 3097 break; 3098 case ETH_SPEED_NUM_25G: 3099 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3100 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 3101 break; 3102 case ETH_SPEED_NUM_40G: 3103 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3104 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 3105 break; 3106 case ETH_SPEED_NUM_50G: 3107 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3108 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 3109 break; 3110 case ETH_SPEED_NUM_100G: 3111 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3112 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 3113 break; 3114 case ETH_SPEED_NUM_200G: 3115 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3116 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G); 3117 break; 3118 default: 3119 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 3120 return -EINVAL; 3121 } 3122 3123 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 3124 3125 ret = hns3_cmd_send(hw, &desc, 1); 3126 if (ret) 3127 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 3128 3129 return ret; 3130 } 3131 3132 static int 3133 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3134 { 3135 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3136 struct hns3_pf *pf = &hns->pf; 3137 struct hns3_priv_buf *priv; 3138 uint32_t i, total_size; 3139 3140 total_size = pf->pkt_buf_size; 3141 3142 /* alloc tx buffer for all enabled tc */ 3143 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3144 priv = &buf_alloc->priv_buf[i]; 3145 3146 if (hw->hw_tc_map & BIT(i)) { 3147 if (total_size < pf->tx_buf_size) 3148 return -ENOMEM; 3149 3150 priv->tx_buf_size = pf->tx_buf_size; 3151 } else 3152 priv->tx_buf_size = 0; 3153 3154 total_size -= priv->tx_buf_size; 3155 } 3156 3157 return 0; 3158 } 3159 3160 static int 3161 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3162 { 3163 /* TX buffer size is unit by 128 byte */ 3164 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3165 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3166 struct hns3_tx_buff_alloc_cmd *req; 3167 struct hns3_cmd_desc desc; 3168 uint32_t buf_size; 3169 uint32_t i; 3170 int ret; 3171 3172 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3173 3174 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3175 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3176 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3177 3178 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3179 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3180 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3181 } 3182 3183 ret = hns3_cmd_send(hw, &desc, 1); 3184 if (ret) 3185 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3186 3187 return ret; 3188 } 3189 3190 static int 3191 hns3_get_tc_num(struct hns3_hw *hw) 3192 { 3193 int cnt = 0; 3194 uint8_t i; 3195 3196 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3197 if (hw->hw_tc_map & BIT(i)) 3198 cnt++; 3199 return cnt; 3200 } 3201 3202 static uint32_t 3203 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3204 { 3205 struct hns3_priv_buf *priv; 3206 uint32_t rx_priv = 0; 3207 int i; 3208 3209 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3210 priv = &buf_alloc->priv_buf[i]; 3211 if (priv->enable) 3212 rx_priv += priv->buf_size; 3213 } 3214 return rx_priv; 3215 } 3216 3217 static uint32_t 3218 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3219 { 3220 uint32_t total_tx_size = 0; 3221 uint32_t i; 3222 3223 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3224 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3225 3226 return total_tx_size; 3227 } 3228 3229 /* Get the number of pfc enabled TCs, which have private buffer */ 3230 static int 3231 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3232 { 3233 struct hns3_priv_buf *priv; 3234 int cnt = 0; 3235 uint8_t i; 3236 3237 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3238 priv = &buf_alloc->priv_buf[i]; 3239 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3240 cnt++; 3241 } 3242 3243 return cnt; 3244 } 3245 3246 /* Get the number of pfc disabled TCs, which have private buffer */ 3247 static int 3248 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3249 struct hns3_pkt_buf_alloc *buf_alloc) 3250 { 3251 struct hns3_priv_buf *priv; 3252 int cnt = 0; 3253 uint8_t i; 3254 3255 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3256 priv = &buf_alloc->priv_buf[i]; 3257 if (hw->hw_tc_map & BIT(i) && 3258 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3259 cnt++; 3260 } 3261 3262 return cnt; 3263 } 3264 3265 static bool 3266 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3267 uint32_t rx_all) 3268 { 3269 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3270 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3271 struct hns3_pf *pf = &hns->pf; 3272 uint32_t shared_buf, aligned_mps; 3273 uint32_t rx_priv; 3274 uint8_t tc_num; 3275 uint8_t i; 3276 3277 tc_num = hns3_get_tc_num(hw); 3278 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3279 3280 if (hns3_dev_dcb_supported(hw)) 3281 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3282 pf->dv_buf_size; 3283 else 3284 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3285 + pf->dv_buf_size; 3286 3287 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3288 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), 3289 HNS3_BUF_SIZE_UNIT); 3290 3291 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3292 if (rx_all < rx_priv + shared_std) 3293 return false; 3294 3295 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3296 buf_alloc->s_buf.buf_size = shared_buf; 3297 if (hns3_dev_dcb_supported(hw)) { 3298 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3299 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3300 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3301 HNS3_BUF_SIZE_UNIT); 3302 } else { 3303 buf_alloc->s_buf.self.high = 3304 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3305 buf_alloc->s_buf.self.low = aligned_mps; 3306 } 3307 3308 if (hns3_dev_dcb_supported(hw)) { 3309 hi_thrd = shared_buf - pf->dv_buf_size; 3310 3311 if (tc_num <= NEED_RESERVE_TC_NUM) 3312 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 3313 / BUF_MAX_PERCENT; 3314 3315 if (tc_num) 3316 hi_thrd = hi_thrd / tc_num; 3317 3318 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); 3319 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3320 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3321 } else { 3322 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3323 lo_thrd = aligned_mps; 3324 } 3325 3326 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3327 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3328 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3329 } 3330 3331 return true; 3332 } 3333 3334 static bool 3335 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3336 struct hns3_pkt_buf_alloc *buf_alloc) 3337 { 3338 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3339 struct hns3_pf *pf = &hns->pf; 3340 struct hns3_priv_buf *priv; 3341 uint32_t aligned_mps; 3342 uint32_t rx_all; 3343 uint8_t i; 3344 3345 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3346 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3347 3348 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3349 priv = &buf_alloc->priv_buf[i]; 3350 3351 priv->enable = 0; 3352 priv->wl.low = 0; 3353 priv->wl.high = 0; 3354 priv->buf_size = 0; 3355 3356 if (!(hw->hw_tc_map & BIT(i))) 3357 continue; 3358 3359 priv->enable = 1; 3360 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3361 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3362 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3363 HNS3_BUF_SIZE_UNIT); 3364 } else { 3365 priv->wl.low = 0; 3366 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3367 aligned_mps; 3368 } 3369 3370 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3371 } 3372 3373 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3374 } 3375 3376 static bool 3377 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3378 struct hns3_pkt_buf_alloc *buf_alloc) 3379 { 3380 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3381 struct hns3_pf *pf = &hns->pf; 3382 struct hns3_priv_buf *priv; 3383 int no_pfc_priv_num; 3384 uint32_t rx_all; 3385 uint8_t mask; 3386 int i; 3387 3388 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3389 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3390 3391 /* let the last to be cleared first */ 3392 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3393 priv = &buf_alloc->priv_buf[i]; 3394 mask = BIT((uint8_t)i); 3395 3396 if (hw->hw_tc_map & mask && 3397 !(hw->dcb_info.hw_pfc_map & mask)) { 3398 /* Clear the no pfc TC private buffer */ 3399 priv->wl.low = 0; 3400 priv->wl.high = 0; 3401 priv->buf_size = 0; 3402 priv->enable = 0; 3403 no_pfc_priv_num--; 3404 } 3405 3406 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3407 no_pfc_priv_num == 0) 3408 break; 3409 } 3410 3411 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3412 } 3413 3414 static bool 3415 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3416 struct hns3_pkt_buf_alloc *buf_alloc) 3417 { 3418 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3419 struct hns3_pf *pf = &hns->pf; 3420 struct hns3_priv_buf *priv; 3421 uint32_t rx_all; 3422 int pfc_priv_num; 3423 uint8_t mask; 3424 int i; 3425 3426 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3427 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3428 3429 /* let the last to be cleared first */ 3430 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3431 priv = &buf_alloc->priv_buf[i]; 3432 mask = BIT((uint8_t)i); 3433 3434 if (hw->hw_tc_map & mask && 3435 hw->dcb_info.hw_pfc_map & mask) { 3436 /* Reduce the number of pfc TC with private buffer */ 3437 priv->wl.low = 0; 3438 priv->enable = 0; 3439 priv->wl.high = 0; 3440 priv->buf_size = 0; 3441 pfc_priv_num--; 3442 } 3443 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3444 pfc_priv_num == 0) 3445 break; 3446 } 3447 3448 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3449 } 3450 3451 static bool 3452 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3453 struct hns3_pkt_buf_alloc *buf_alloc) 3454 { 3455 #define COMPENSATE_BUFFER 0x3C00 3456 #define COMPENSATE_HALF_MPS_NUM 5 3457 #define PRIV_WL_GAP 0x1800 3458 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3459 struct hns3_pf *pf = &hns->pf; 3460 uint32_t tc_num = hns3_get_tc_num(hw); 3461 uint32_t half_mps = pf->mps >> 1; 3462 struct hns3_priv_buf *priv; 3463 uint32_t min_rx_priv; 3464 uint32_t rx_priv; 3465 uint8_t i; 3466 3467 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3468 if (tc_num) 3469 rx_priv = rx_priv / tc_num; 3470 3471 if (tc_num <= NEED_RESERVE_TC_NUM) 3472 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3473 3474 /* 3475 * Minimum value of private buffer in rx direction (min_rx_priv) is 3476 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3477 * buffer if rx_priv is greater than min_rx_priv. 3478 */ 3479 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3480 COMPENSATE_HALF_MPS_NUM * half_mps; 3481 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3482 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3483 3484 if (rx_priv < min_rx_priv) 3485 return false; 3486 3487 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3488 priv = &buf_alloc->priv_buf[i]; 3489 3490 priv->enable = 0; 3491 priv->wl.low = 0; 3492 priv->wl.high = 0; 3493 priv->buf_size = 0; 3494 3495 if (!(hw->hw_tc_map & BIT(i))) 3496 continue; 3497 3498 priv->enable = 1; 3499 priv->buf_size = rx_priv; 3500 priv->wl.high = rx_priv - pf->dv_buf_size; 3501 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3502 } 3503 3504 buf_alloc->s_buf.buf_size = 0; 3505 3506 return true; 3507 } 3508 3509 /* 3510 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3511 * @hw: pointer to struct hns3_hw 3512 * @buf_alloc: pointer to buffer calculation data 3513 * @return: 0: calculate sucessful, negative: fail 3514 */ 3515 static int 3516 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3517 { 3518 /* When DCB is not supported, rx private buffer is not allocated. */ 3519 if (!hns3_dev_dcb_supported(hw)) { 3520 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3521 struct hns3_pf *pf = &hns->pf; 3522 uint32_t rx_all = pf->pkt_buf_size; 3523 3524 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3525 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3526 return -ENOMEM; 3527 3528 return 0; 3529 } 3530 3531 /* 3532 * Try to allocate privated packet buffer for all TCs without share 3533 * buffer. 3534 */ 3535 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3536 return 0; 3537 3538 /* 3539 * Try to allocate privated packet buffer for all TCs with share 3540 * buffer. 3541 */ 3542 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3543 return 0; 3544 3545 /* 3546 * For different application scenes, the enabled port number, TC number 3547 * and no_drop TC number are different. In order to obtain the better 3548 * performance, software could allocate the buffer size and configure 3549 * the waterline by tring to decrease the private buffer size according 3550 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc 3551 * enabled tc. 3552 */ 3553 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 3554 return 0; 3555 3556 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 3557 return 0; 3558 3559 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 3560 return 0; 3561 3562 return -ENOMEM; 3563 } 3564 3565 static int 3566 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3567 { 3568 struct hns3_rx_priv_buff_cmd *req; 3569 struct hns3_cmd_desc desc; 3570 uint32_t buf_size; 3571 int ret; 3572 int i; 3573 3574 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 3575 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 3576 3577 /* Alloc private buffer TCs */ 3578 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3579 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 3580 3581 req->buf_num[i] = 3582 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 3583 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 3584 } 3585 3586 buf_size = buf_alloc->s_buf.buf_size; 3587 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 3588 (1 << HNS3_TC0_PRI_BUF_EN_B)); 3589 3590 ret = hns3_cmd_send(hw, &desc, 1); 3591 if (ret) 3592 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 3593 3594 return ret; 3595 } 3596 3597 static int 3598 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3599 { 3600 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 3601 struct hns3_rx_priv_wl_buf *req; 3602 struct hns3_priv_buf *priv; 3603 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 3604 int i, j; 3605 int ret; 3606 3607 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 3608 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 3609 false); 3610 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 3611 3612 /* The first descriptor set the NEXT bit to 1 */ 3613 if (i == 0) 3614 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3615 else 3616 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3617 3618 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3619 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 3620 3621 priv = &buf_alloc->priv_buf[idx]; 3622 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 3623 HNS3_BUF_UNIT_S); 3624 req->tc_wl[j].high |= 3625 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3626 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 3627 HNS3_BUF_UNIT_S); 3628 req->tc_wl[j].low |= 3629 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3630 } 3631 } 3632 3633 /* Send 2 descriptor at one time */ 3634 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 3635 if (ret) 3636 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 3637 ret); 3638 return ret; 3639 } 3640 3641 static int 3642 hns3_common_thrd_config(struct hns3_hw *hw, 3643 struct hns3_pkt_buf_alloc *buf_alloc) 3644 { 3645 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 3646 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 3647 struct hns3_rx_com_thrd *req; 3648 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 3649 struct hns3_tc_thrd *tc; 3650 int tc_idx; 3651 int i, j; 3652 int ret; 3653 3654 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 3655 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 3656 false); 3657 req = (struct hns3_rx_com_thrd *)&desc[i].data; 3658 3659 /* The first descriptor set the NEXT bit to 1 */ 3660 if (i == 0) 3661 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3662 else 3663 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3664 3665 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3666 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 3667 tc = &s_buf->tc_thrd[tc_idx]; 3668 3669 req->com_thrd[j].high = 3670 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 3671 req->com_thrd[j].high |= 3672 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3673 req->com_thrd[j].low = 3674 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 3675 req->com_thrd[j].low |= 3676 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3677 } 3678 } 3679 3680 /* Send 2 descriptors at one time */ 3681 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 3682 if (ret) 3683 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 3684 3685 return ret; 3686 } 3687 3688 static int 3689 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3690 { 3691 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 3692 struct hns3_rx_com_wl *req; 3693 struct hns3_cmd_desc desc; 3694 int ret; 3695 3696 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 3697 3698 req = (struct hns3_rx_com_wl *)desc.data; 3699 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 3700 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3701 3702 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 3703 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3704 3705 ret = hns3_cmd_send(hw, &desc, 1); 3706 if (ret) 3707 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 3708 3709 return ret; 3710 } 3711 3712 int 3713 hns3_buffer_alloc(struct hns3_hw *hw) 3714 { 3715 struct hns3_pkt_buf_alloc pkt_buf; 3716 int ret; 3717 3718 memset(&pkt_buf, 0, sizeof(pkt_buf)); 3719 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 3720 if (ret) { 3721 PMD_INIT_LOG(ERR, 3722 "could not calc tx buffer size for all TCs %d", 3723 ret); 3724 return ret; 3725 } 3726 3727 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 3728 if (ret) { 3729 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 3730 return ret; 3731 } 3732 3733 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 3734 if (ret) { 3735 PMD_INIT_LOG(ERR, 3736 "could not calc rx priv buffer size for all TCs %d", 3737 ret); 3738 return ret; 3739 } 3740 3741 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 3742 if (ret) { 3743 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 3744 return ret; 3745 } 3746 3747 if (hns3_dev_dcb_supported(hw)) { 3748 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 3749 if (ret) { 3750 PMD_INIT_LOG(ERR, 3751 "could not configure rx private waterline %d", 3752 ret); 3753 return ret; 3754 } 3755 3756 ret = hns3_common_thrd_config(hw, &pkt_buf); 3757 if (ret) { 3758 PMD_INIT_LOG(ERR, 3759 "could not configure common threshold %d", 3760 ret); 3761 return ret; 3762 } 3763 } 3764 3765 ret = hns3_common_wl_config(hw, &pkt_buf); 3766 if (ret) 3767 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 3768 ret); 3769 3770 return ret; 3771 } 3772 3773 static int 3774 hns3_mac_init(struct hns3_hw *hw) 3775 { 3776 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3777 struct hns3_mac *mac = &hw->mac; 3778 struct hns3_pf *pf = &hns->pf; 3779 int ret; 3780 3781 pf->support_sfp_query = true; 3782 mac->link_duplex = ETH_LINK_FULL_DUPLEX; 3783 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 3784 if (ret) { 3785 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 3786 return ret; 3787 } 3788 3789 mac->link_status = ETH_LINK_DOWN; 3790 3791 return hns3_config_mtu(hw, pf->mps); 3792 } 3793 3794 static int 3795 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 3796 { 3797 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 3798 #define HNS3_ETHERTYPE_ALREADY_ADD 1 3799 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 3800 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 3801 int return_status; 3802 3803 if (cmdq_resp) { 3804 PMD_INIT_LOG(ERR, 3805 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 3806 cmdq_resp); 3807 return -EIO; 3808 } 3809 3810 switch (resp_code) { 3811 case HNS3_ETHERTYPE_SUCCESS_ADD: 3812 case HNS3_ETHERTYPE_ALREADY_ADD: 3813 return_status = 0; 3814 break; 3815 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 3816 PMD_INIT_LOG(ERR, 3817 "add mac ethertype failed for manager table overflow."); 3818 return_status = -EIO; 3819 break; 3820 case HNS3_ETHERTYPE_KEY_CONFLICT: 3821 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 3822 return_status = -EIO; 3823 break; 3824 default: 3825 PMD_INIT_LOG(ERR, 3826 "add mac ethertype failed for undefined, code=%d.", 3827 resp_code); 3828 return_status = -EIO; 3829 break; 3830 } 3831 3832 return return_status; 3833 } 3834 3835 static int 3836 hns3_add_mgr_tbl(struct hns3_hw *hw, 3837 const struct hns3_mac_mgr_tbl_entry_cmd *req) 3838 { 3839 struct hns3_cmd_desc desc; 3840 uint8_t resp_code; 3841 uint16_t retval; 3842 int ret; 3843 3844 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 3845 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 3846 3847 ret = hns3_cmd_send(hw, &desc, 1); 3848 if (ret) { 3849 PMD_INIT_LOG(ERR, 3850 "add mac ethertype failed for cmd_send, ret =%d.", 3851 ret); 3852 return ret; 3853 } 3854 3855 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 3856 retval = rte_le_to_cpu_16(desc.retval); 3857 3858 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 3859 } 3860 3861 static void 3862 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 3863 int *table_item_num) 3864 { 3865 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 3866 3867 /* 3868 * In current version, we add one item in management table as below: 3869 * 0x0180C200000E -- LLDP MC address 3870 */ 3871 tbl = mgr_table; 3872 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 3873 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 3874 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 3875 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 3876 tbl->i_port_bitmap = 0x1; 3877 *table_item_num = 1; 3878 } 3879 3880 static int 3881 hns3_init_mgr_tbl(struct hns3_hw *hw) 3882 { 3883 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 3884 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 3885 int table_item_num; 3886 int ret; 3887 int i; 3888 3889 memset(mgr_table, 0, sizeof(mgr_table)); 3890 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 3891 for (i = 0; i < table_item_num; i++) { 3892 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 3893 if (ret) { 3894 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 3895 ret); 3896 return ret; 3897 } 3898 } 3899 3900 return 0; 3901 } 3902 3903 static void 3904 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 3905 bool en_mc, bool en_bc, int vport_id) 3906 { 3907 if (!param) 3908 return; 3909 3910 memset(param, 0, sizeof(struct hns3_promisc_param)); 3911 if (en_uc) 3912 param->enable = HNS3_PROMISC_EN_UC; 3913 if (en_mc) 3914 param->enable |= HNS3_PROMISC_EN_MC; 3915 if (en_bc) 3916 param->enable |= HNS3_PROMISC_EN_BC; 3917 param->vf_id = vport_id; 3918 } 3919 3920 static int 3921 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 3922 { 3923 struct hns3_promisc_cfg_cmd *req; 3924 struct hns3_cmd_desc desc; 3925 int ret; 3926 3927 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 3928 3929 req = (struct hns3_promisc_cfg_cmd *)desc.data; 3930 req->vf_id = param->vf_id; 3931 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 3932 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 3933 3934 ret = hns3_cmd_send(hw, &desc, 1); 3935 if (ret) 3936 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 3937 3938 return ret; 3939 } 3940 3941 static int 3942 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 3943 { 3944 struct hns3_promisc_param param; 3945 bool en_bc_pmc = true; 3946 uint8_t vf_id; 3947 3948 /* 3949 * In current version VF is not supported when PF is driven by DPDK 3950 * driver, just need to configure parameters for PF vport. 3951 */ 3952 vf_id = HNS3_PF_FUNC_ID; 3953 3954 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 3955 return hns3_cmd_set_promisc_mode(hw, ¶m); 3956 } 3957 3958 static int 3959 hns3_promisc_init(struct hns3_hw *hw) 3960 { 3961 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3962 struct hns3_pf *pf = &hns->pf; 3963 struct hns3_promisc_param param; 3964 uint16_t func_id; 3965 int ret; 3966 3967 ret = hns3_set_promisc_mode(hw, false, false); 3968 if (ret) { 3969 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 3970 return ret; 3971 } 3972 3973 /* 3974 * In current version VFs are not supported when PF is driven by DPDK 3975 * driver. After PF has been taken over by DPDK, the original VF will 3976 * be invalid. So, there is a possibility of entry residues. It should 3977 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 3978 * during init. 3979 */ 3980 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 3981 hns3_promisc_param_init(¶m, false, false, false, func_id); 3982 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 3983 if (ret) { 3984 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode," 3985 " ret = %d", func_id, ret); 3986 return ret; 3987 } 3988 } 3989 3990 return 0; 3991 } 3992 3993 static void 3994 hns3_promisc_uninit(struct hns3_hw *hw) 3995 { 3996 struct hns3_promisc_param param; 3997 uint16_t func_id; 3998 int ret; 3999 4000 func_id = HNS3_PF_FUNC_ID; 4001 4002 /* 4003 * In current version VFs are not supported when PF is driven by 4004 * DPDK driver, and VFs' promisc mode status has been cleared during 4005 * init and their status will not change. So just clear PF's promisc 4006 * mode status during uninit. 4007 */ 4008 hns3_promisc_param_init(¶m, false, false, false, func_id); 4009 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4010 if (ret) 4011 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 4012 " uninit, ret = %d", ret); 4013 } 4014 4015 static int 4016 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 4017 { 4018 bool allmulti = dev->data->all_multicast ? true : false; 4019 struct hns3_adapter *hns = dev->data->dev_private; 4020 struct hns3_hw *hw = &hns->hw; 4021 uint64_t offloads; 4022 int err; 4023 int ret; 4024 4025 rte_spinlock_lock(&hw->lock); 4026 ret = hns3_set_promisc_mode(hw, true, true); 4027 if (ret) { 4028 rte_spinlock_unlock(&hw->lock); 4029 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 4030 ret); 4031 return ret; 4032 } 4033 4034 /* 4035 * When promiscuous mode was enabled, disable the vlan filter to let 4036 * all packets coming in in the receiving direction. 4037 */ 4038 offloads = dev->data->dev_conf.rxmode.offloads; 4039 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4040 ret = hns3_enable_vlan_filter(hns, false); 4041 if (ret) { 4042 hns3_err(hw, "failed to enable promiscuous mode due to " 4043 "failure to disable vlan filter, ret = %d", 4044 ret); 4045 err = hns3_set_promisc_mode(hw, false, allmulti); 4046 if (err) 4047 hns3_err(hw, "failed to restore promiscuous " 4048 "status after disable vlan filter " 4049 "failed during enabling promiscuous " 4050 "mode, ret = %d", ret); 4051 } 4052 } 4053 4054 rte_spinlock_unlock(&hw->lock); 4055 4056 return ret; 4057 } 4058 4059 static int 4060 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 4061 { 4062 bool allmulti = dev->data->all_multicast ? true : false; 4063 struct hns3_adapter *hns = dev->data->dev_private; 4064 struct hns3_hw *hw = &hns->hw; 4065 uint64_t offloads; 4066 int err; 4067 int ret; 4068 4069 /* If now in all_multicast mode, must remain in all_multicast mode. */ 4070 rte_spinlock_lock(&hw->lock); 4071 ret = hns3_set_promisc_mode(hw, false, allmulti); 4072 if (ret) { 4073 rte_spinlock_unlock(&hw->lock); 4074 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 4075 ret); 4076 return ret; 4077 } 4078 /* when promiscuous mode was disabled, restore the vlan filter status */ 4079 offloads = dev->data->dev_conf.rxmode.offloads; 4080 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4081 ret = hns3_enable_vlan_filter(hns, true); 4082 if (ret) { 4083 hns3_err(hw, "failed to disable promiscuous mode due to" 4084 " failure to restore vlan filter, ret = %d", 4085 ret); 4086 err = hns3_set_promisc_mode(hw, true, true); 4087 if (err) 4088 hns3_err(hw, "failed to restore promiscuous " 4089 "status after enabling vlan filter " 4090 "failed during disabling promiscuous " 4091 "mode, ret = %d", ret); 4092 } 4093 } 4094 rte_spinlock_unlock(&hw->lock); 4095 4096 return ret; 4097 } 4098 4099 static int 4100 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 4101 { 4102 struct hns3_adapter *hns = dev->data->dev_private; 4103 struct hns3_hw *hw = &hns->hw; 4104 int ret; 4105 4106 if (dev->data->promiscuous) 4107 return 0; 4108 4109 rte_spinlock_lock(&hw->lock); 4110 ret = hns3_set_promisc_mode(hw, false, true); 4111 rte_spinlock_unlock(&hw->lock); 4112 if (ret) 4113 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 4114 ret); 4115 4116 return ret; 4117 } 4118 4119 static int 4120 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 4121 { 4122 struct hns3_adapter *hns = dev->data->dev_private; 4123 struct hns3_hw *hw = &hns->hw; 4124 int ret; 4125 4126 /* If now in promiscuous mode, must remain in all_multicast mode. */ 4127 if (dev->data->promiscuous) 4128 return 0; 4129 4130 rte_spinlock_lock(&hw->lock); 4131 ret = hns3_set_promisc_mode(hw, false, false); 4132 rte_spinlock_unlock(&hw->lock); 4133 if (ret) 4134 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4135 ret); 4136 4137 return ret; 4138 } 4139 4140 static int 4141 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4142 { 4143 struct hns3_hw *hw = &hns->hw; 4144 bool allmulti = hw->data->all_multicast ? true : false; 4145 int ret; 4146 4147 if (hw->data->promiscuous) { 4148 ret = hns3_set_promisc_mode(hw, true, true); 4149 if (ret) 4150 hns3_err(hw, "failed to restore promiscuous mode, " 4151 "ret = %d", ret); 4152 return ret; 4153 } 4154 4155 ret = hns3_set_promisc_mode(hw, false, allmulti); 4156 if (ret) 4157 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4158 ret); 4159 return ret; 4160 } 4161 4162 static int 4163 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed) 4164 { 4165 struct hns3_sfp_speed_cmd *resp; 4166 struct hns3_cmd_desc desc; 4167 int ret; 4168 4169 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true); 4170 resp = (struct hns3_sfp_speed_cmd *)desc.data; 4171 ret = hns3_cmd_send(hw, &desc, 1); 4172 if (ret == -EOPNOTSUPP) { 4173 hns3_err(hw, "IMP do not support get SFP speed %d", ret); 4174 return ret; 4175 } else if (ret) { 4176 hns3_err(hw, "get sfp speed failed %d", ret); 4177 return ret; 4178 } 4179 4180 *speed = resp->sfp_speed; 4181 4182 return 0; 4183 } 4184 4185 static uint8_t 4186 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4187 { 4188 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M)) 4189 duplex = ETH_LINK_FULL_DUPLEX; 4190 4191 return duplex; 4192 } 4193 4194 static int 4195 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4196 { 4197 struct hns3_mac *mac = &hw->mac; 4198 int ret; 4199 4200 duplex = hns3_check_speed_dup(duplex, speed); 4201 if (mac->link_speed == speed && mac->link_duplex == duplex) 4202 return 0; 4203 4204 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4205 if (ret) 4206 return ret; 4207 4208 mac->link_speed = speed; 4209 mac->link_duplex = duplex; 4210 4211 return 0; 4212 } 4213 4214 static int 4215 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev) 4216 { 4217 struct hns3_adapter *hns = eth_dev->data->dev_private; 4218 struct hns3_hw *hw = &hns->hw; 4219 struct hns3_pf *pf = &hns->pf; 4220 uint32_t speed; 4221 int ret; 4222 4223 /* If IMP do not support get SFP/qSFP speed, return directly */ 4224 if (!pf->support_sfp_query) 4225 return 0; 4226 4227 ret = hns3_get_sfp_speed(hw, &speed); 4228 if (ret == -EOPNOTSUPP) { 4229 pf->support_sfp_query = false; 4230 return ret; 4231 } else if (ret) 4232 return ret; 4233 4234 if (speed == ETH_SPEED_NUM_NONE) 4235 return 0; /* do nothing if no SFP */ 4236 4237 /* Config full duplex for SFP */ 4238 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX); 4239 } 4240 4241 static int 4242 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4243 { 4244 struct hns3_config_mac_mode_cmd *req; 4245 struct hns3_cmd_desc desc; 4246 uint32_t loop_en = 0; 4247 uint8_t val = 0; 4248 int ret; 4249 4250 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4251 4252 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4253 if (enable) 4254 val = 1; 4255 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4256 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4257 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4258 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4259 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4260 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4261 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4262 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4263 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4264 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4265 4266 /* 4267 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC 4268 * when receiving frames. Otherwise, CRC will be stripped. 4269 */ 4270 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 4271 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0); 4272 else 4273 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4274 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4275 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4276 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4277 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4278 4279 ret = hns3_cmd_send(hw, &desc, 1); 4280 if (ret) 4281 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4282 4283 return ret; 4284 } 4285 4286 static int 4287 hns3_get_mac_link_status(struct hns3_hw *hw) 4288 { 4289 struct hns3_link_status_cmd *req; 4290 struct hns3_cmd_desc desc; 4291 int link_status; 4292 int ret; 4293 4294 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4295 ret = hns3_cmd_send(hw, &desc, 1); 4296 if (ret) { 4297 hns3_err(hw, "get link status cmd failed %d", ret); 4298 return ETH_LINK_DOWN; 4299 } 4300 4301 req = (struct hns3_link_status_cmd *)desc.data; 4302 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4303 4304 return !!link_status; 4305 } 4306 4307 void 4308 hns3_update_link_status(struct hns3_hw *hw) 4309 { 4310 int state; 4311 4312 state = hns3_get_mac_link_status(hw); 4313 if (state != hw->mac.link_status) { 4314 hw->mac.link_status = state; 4315 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4316 } 4317 } 4318 4319 static void 4320 hns3_service_handler(void *param) 4321 { 4322 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 4323 struct hns3_adapter *hns = eth_dev->data->dev_private; 4324 struct hns3_hw *hw = &hns->hw; 4325 4326 if (!hns3_is_reset_pending(hns)) { 4327 hns3_update_speed_duplex(eth_dev); 4328 hns3_update_link_status(hw); 4329 } else 4330 hns3_warn(hw, "Cancel the query when reset is pending"); 4331 4332 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4333 } 4334 4335 static int 4336 hns3_init_hardware(struct hns3_adapter *hns) 4337 { 4338 struct hns3_hw *hw = &hns->hw; 4339 int ret; 4340 4341 ret = hns3_map_tqp(hw); 4342 if (ret) { 4343 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 4344 return ret; 4345 } 4346 4347 ret = hns3_init_umv_space(hw); 4348 if (ret) { 4349 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 4350 return ret; 4351 } 4352 4353 ret = hns3_mac_init(hw); 4354 if (ret) { 4355 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 4356 goto err_mac_init; 4357 } 4358 4359 ret = hns3_init_mgr_tbl(hw); 4360 if (ret) { 4361 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 4362 goto err_mac_init; 4363 } 4364 4365 ret = hns3_promisc_init(hw); 4366 if (ret) { 4367 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 4368 ret); 4369 goto err_mac_init; 4370 } 4371 4372 ret = hns3_init_vlan_config(hns); 4373 if (ret) { 4374 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 4375 goto err_mac_init; 4376 } 4377 4378 ret = hns3_dcb_init(hw); 4379 if (ret) { 4380 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 4381 goto err_mac_init; 4382 } 4383 4384 ret = hns3_init_fd_config(hns); 4385 if (ret) { 4386 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 4387 goto err_mac_init; 4388 } 4389 4390 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 4391 if (ret) { 4392 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 4393 goto err_mac_init; 4394 } 4395 4396 ret = hns3_config_gro(hw, false); 4397 if (ret) { 4398 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 4399 goto err_mac_init; 4400 } 4401 4402 /* 4403 * In the initialization clearing the all hardware mapping relationship 4404 * configurations between queues and interrupt vectors is needed, so 4405 * some error caused by the residual configurations, such as the 4406 * unexpected interrupt, can be avoid. 4407 */ 4408 ret = hns3_init_ring_with_vector(hw); 4409 if (ret) { 4410 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 4411 goto err_mac_init; 4412 } 4413 4414 return 0; 4415 4416 err_mac_init: 4417 hns3_uninit_umv_space(hw); 4418 return ret; 4419 } 4420 4421 static int 4422 hns3_clear_hw(struct hns3_hw *hw) 4423 { 4424 struct hns3_cmd_desc desc; 4425 int ret; 4426 4427 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); 4428 4429 ret = hns3_cmd_send(hw, &desc, 1); 4430 if (ret && ret != -EOPNOTSUPP) 4431 return ret; 4432 4433 return 0; 4434 } 4435 4436 static void 4437 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) 4438 { 4439 uint32_t val; 4440 4441 /* 4442 * The new firmware support report more hardware error types by 4443 * msix mode. These errors are defined as RAS errors in hardware 4444 * and belong to a different type from the MSI-x errors processed 4445 * by the network driver. 4446 * 4447 * Network driver should open the new error report on initialition 4448 */ 4449 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 4450 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); 4451 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); 4452 } 4453 4454 static int 4455 hns3_init_pf(struct rte_eth_dev *eth_dev) 4456 { 4457 struct rte_device *dev = eth_dev->device; 4458 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4459 struct hns3_adapter *hns = eth_dev->data->dev_private; 4460 struct hns3_hw *hw = &hns->hw; 4461 int ret; 4462 4463 PMD_INIT_FUNC_TRACE(); 4464 4465 /* Get hardware io base address from pcie BAR2 IO space */ 4466 hw->io_base = pci_dev->mem_resource[2].addr; 4467 4468 /* Firmware command queue initialize */ 4469 ret = hns3_cmd_init_queue(hw); 4470 if (ret) { 4471 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 4472 goto err_cmd_init_queue; 4473 } 4474 4475 hns3_clear_all_event_cause(hw); 4476 4477 /* Firmware command initialize */ 4478 ret = hns3_cmd_init(hw); 4479 if (ret) { 4480 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 4481 goto err_cmd_init; 4482 } 4483 4484 /* 4485 * To ensure that the hardware environment is clean during 4486 * initialization, the driver actively clear the hardware environment 4487 * during initialization, including PF and corresponding VFs' vlan, mac, 4488 * flow table configurations, etc. 4489 */ 4490 ret = hns3_clear_hw(hw); 4491 if (ret) { 4492 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); 4493 goto err_cmd_init; 4494 } 4495 4496 hns3_config_all_msix_error(hw, true); 4497 4498 ret = rte_intr_callback_register(&pci_dev->intr_handle, 4499 hns3_interrupt_handler, 4500 eth_dev); 4501 if (ret) { 4502 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 4503 goto err_intr_callback_register; 4504 } 4505 4506 /* Enable interrupt */ 4507 rte_intr_enable(&pci_dev->intr_handle); 4508 hns3_pf_enable_irq0(hw); 4509 4510 /* Get configuration */ 4511 ret = hns3_get_configuration(hw); 4512 if (ret) { 4513 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 4514 goto err_get_config; 4515 } 4516 4517 ret = hns3_init_hardware(hns); 4518 if (ret) { 4519 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 4520 goto err_get_config; 4521 } 4522 4523 /* Initialize flow director filter list & hash */ 4524 ret = hns3_fdir_filter_init(hns); 4525 if (ret) { 4526 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 4527 goto err_hw_init; 4528 } 4529 4530 hns3_set_default_rss_args(hw); 4531 4532 ret = hns3_enable_hw_error_intr(hns, true); 4533 if (ret) { 4534 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 4535 ret); 4536 goto err_fdir; 4537 } 4538 4539 return 0; 4540 4541 err_fdir: 4542 hns3_fdir_filter_uninit(hns); 4543 err_hw_init: 4544 hns3_uninit_umv_space(hw); 4545 4546 err_get_config: 4547 hns3_pf_disable_irq0(hw); 4548 rte_intr_disable(&pci_dev->intr_handle); 4549 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 4550 eth_dev); 4551 err_intr_callback_register: 4552 err_cmd_init: 4553 hns3_cmd_uninit(hw); 4554 hns3_cmd_destroy_queue(hw); 4555 err_cmd_init_queue: 4556 hw->io_base = NULL; 4557 4558 return ret; 4559 } 4560 4561 static void 4562 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 4563 { 4564 struct hns3_adapter *hns = eth_dev->data->dev_private; 4565 struct rte_device *dev = eth_dev->device; 4566 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4567 struct hns3_hw *hw = &hns->hw; 4568 4569 PMD_INIT_FUNC_TRACE(); 4570 4571 hns3_enable_hw_error_intr(hns, false); 4572 hns3_rss_uninit(hns); 4573 (void)hns3_config_gro(hw, false); 4574 hns3_promisc_uninit(hw); 4575 hns3_fdir_filter_uninit(hns); 4576 hns3_uninit_umv_space(hw); 4577 hns3_pf_disable_irq0(hw); 4578 rte_intr_disable(&pci_dev->intr_handle); 4579 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 4580 eth_dev); 4581 hns3_config_all_msix_error(hw, false); 4582 hns3_cmd_uninit(hw); 4583 hns3_cmd_destroy_queue(hw); 4584 hw->io_base = NULL; 4585 } 4586 4587 static int 4588 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 4589 { 4590 struct hns3_hw *hw = &hns->hw; 4591 int ret; 4592 4593 ret = hns3_dcb_cfg_update(hns); 4594 if (ret) 4595 return ret; 4596 4597 /* Enable queues */ 4598 ret = hns3_start_queues(hns, reset_queue); 4599 if (ret) { 4600 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret); 4601 return ret; 4602 } 4603 4604 /* Enable MAC */ 4605 ret = hns3_cfg_mac_mode(hw, true); 4606 if (ret) { 4607 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret); 4608 goto err_config_mac_mode; 4609 } 4610 return 0; 4611 4612 err_config_mac_mode: 4613 hns3_stop_queues(hns, true); 4614 return ret; 4615 } 4616 4617 static int 4618 hns3_map_rx_interrupt(struct rte_eth_dev *dev) 4619 { 4620 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4621 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4622 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4623 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 4624 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 4625 uint32_t intr_vector; 4626 uint16_t q_id; 4627 int ret; 4628 4629 if (dev->data->dev_conf.intr_conf.rxq == 0) 4630 return 0; 4631 4632 /* disable uio/vfio intr/eventfd mapping */ 4633 rte_intr_disable(intr_handle); 4634 4635 /* check and configure queue intr-vector mapping */ 4636 if (rte_intr_cap_multiple(intr_handle) || 4637 !RTE_ETH_DEV_SRIOV(dev).active) { 4638 intr_vector = hw->used_rx_queues; 4639 /* creates event fd for each intr vector when MSIX is used */ 4640 if (rte_intr_efd_enable(intr_handle, intr_vector)) 4641 return -EINVAL; 4642 } 4643 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 4644 intr_handle->intr_vec = 4645 rte_zmalloc("intr_vec", 4646 hw->used_rx_queues * sizeof(int), 0); 4647 if (intr_handle->intr_vec == NULL) { 4648 hns3_err(hw, "Failed to allocate %d rx_queues" 4649 " intr_vec", hw->used_rx_queues); 4650 ret = -ENOMEM; 4651 goto alloc_intr_vec_error; 4652 } 4653 } 4654 4655 if (rte_intr_allow_others(intr_handle)) { 4656 vec = RTE_INTR_VEC_RXTX_OFFSET; 4657 base = RTE_INTR_VEC_RXTX_OFFSET; 4658 } 4659 if (rte_intr_dp_is_en(intr_handle)) { 4660 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4661 ret = hns3_bind_ring_with_vector(hw, vec, true, 4662 HNS3_RING_TYPE_RX, 4663 q_id); 4664 if (ret) 4665 goto bind_vector_error; 4666 intr_handle->intr_vec[q_id] = vec; 4667 if (vec < base + intr_handle->nb_efd - 1) 4668 vec++; 4669 } 4670 } 4671 rte_intr_enable(intr_handle); 4672 return 0; 4673 4674 bind_vector_error: 4675 rte_intr_efd_disable(intr_handle); 4676 if (intr_handle->intr_vec) { 4677 free(intr_handle->intr_vec); 4678 intr_handle->intr_vec = NULL; 4679 } 4680 return ret; 4681 alloc_intr_vec_error: 4682 rte_intr_efd_disable(intr_handle); 4683 return ret; 4684 } 4685 4686 static int 4687 hns3_restore_rx_interrupt(struct hns3_hw *hw) 4688 { 4689 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4690 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4691 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4692 uint16_t q_id; 4693 int ret; 4694 4695 if (dev->data->dev_conf.intr_conf.rxq == 0) 4696 return 0; 4697 4698 if (rte_intr_dp_is_en(intr_handle)) { 4699 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4700 ret = hns3_bind_ring_with_vector(hw, 4701 intr_handle->intr_vec[q_id], true, 4702 HNS3_RING_TYPE_RX, q_id); 4703 if (ret) 4704 return ret; 4705 } 4706 } 4707 4708 return 0; 4709 } 4710 4711 static void 4712 hns3_restore_filter(struct rte_eth_dev *dev) 4713 { 4714 hns3_restore_rss_filter(dev); 4715 } 4716 4717 static int 4718 hns3_dev_start(struct rte_eth_dev *dev) 4719 { 4720 struct hns3_adapter *hns = dev->data->dev_private; 4721 struct hns3_hw *hw = &hns->hw; 4722 int ret; 4723 4724 PMD_INIT_FUNC_TRACE(); 4725 if (rte_atomic16_read(&hw->reset.resetting)) 4726 return -EBUSY; 4727 4728 rte_spinlock_lock(&hw->lock); 4729 hw->adapter_state = HNS3_NIC_STARTING; 4730 4731 ret = hns3_do_start(hns, true); 4732 if (ret) { 4733 hw->adapter_state = HNS3_NIC_CONFIGURED; 4734 rte_spinlock_unlock(&hw->lock); 4735 return ret; 4736 } 4737 ret = hns3_map_rx_interrupt(dev); 4738 if (ret) { 4739 hw->adapter_state = HNS3_NIC_CONFIGURED; 4740 rte_spinlock_unlock(&hw->lock); 4741 return ret; 4742 } 4743 4744 hw->adapter_state = HNS3_NIC_STARTED; 4745 rte_spinlock_unlock(&hw->lock); 4746 4747 hns3_set_rxtx_function(dev); 4748 hns3_mp_req_start_rxtx(dev); 4749 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 4750 4751 hns3_restore_filter(dev); 4752 4753 /* Enable interrupt of all rx queues before enabling queues */ 4754 hns3_dev_all_rx_queue_intr_enable(hw, true); 4755 /* 4756 * When finished the initialization, enable queues to receive/transmit 4757 * packets. 4758 */ 4759 hns3_enable_all_queues(hw, true); 4760 4761 hns3_info(hw, "hns3 dev start successful!"); 4762 return 0; 4763 } 4764 4765 static int 4766 hns3_do_stop(struct hns3_adapter *hns) 4767 { 4768 struct hns3_hw *hw = &hns->hw; 4769 bool reset_queue; 4770 int ret; 4771 4772 ret = hns3_cfg_mac_mode(hw, false); 4773 if (ret) 4774 return ret; 4775 hw->mac.link_status = ETH_LINK_DOWN; 4776 4777 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) { 4778 hns3_configure_all_mac_addr(hns, true); 4779 reset_queue = true; 4780 } else 4781 reset_queue = false; 4782 hw->mac.default_addr_setted = false; 4783 return hns3_stop_queues(hns, reset_queue); 4784 } 4785 4786 static void 4787 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) 4788 { 4789 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4790 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4791 struct hns3_adapter *hns = dev->data->dev_private; 4792 struct hns3_hw *hw = &hns->hw; 4793 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 4794 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 4795 uint16_t q_id; 4796 4797 if (dev->data->dev_conf.intr_conf.rxq == 0) 4798 return; 4799 4800 /* unmap the ring with vector */ 4801 if (rte_intr_allow_others(intr_handle)) { 4802 vec = RTE_INTR_VEC_RXTX_OFFSET; 4803 base = RTE_INTR_VEC_RXTX_OFFSET; 4804 } 4805 if (rte_intr_dp_is_en(intr_handle)) { 4806 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4807 (void)hns3_bind_ring_with_vector(hw, vec, false, 4808 HNS3_RING_TYPE_RX, 4809 q_id); 4810 if (vec < base + intr_handle->nb_efd - 1) 4811 vec++; 4812 } 4813 } 4814 /* Clean datapath event and queue/vec mapping */ 4815 rte_intr_efd_disable(intr_handle); 4816 if (intr_handle->intr_vec) { 4817 rte_free(intr_handle->intr_vec); 4818 intr_handle->intr_vec = NULL; 4819 } 4820 } 4821 4822 static void 4823 hns3_dev_stop(struct rte_eth_dev *dev) 4824 { 4825 struct hns3_adapter *hns = dev->data->dev_private; 4826 struct hns3_hw *hw = &hns->hw; 4827 4828 PMD_INIT_FUNC_TRACE(); 4829 4830 hw->adapter_state = HNS3_NIC_STOPPING; 4831 hns3_set_rxtx_function(dev); 4832 rte_wmb(); 4833 /* Disable datapath on secondary process. */ 4834 hns3_mp_req_stop_rxtx(dev); 4835 /* Prevent crashes when queues are still in use. */ 4836 rte_delay_ms(hw->tqps_num); 4837 4838 rte_spinlock_lock(&hw->lock); 4839 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 4840 hns3_do_stop(hns); 4841 hns3_unmap_rx_interrupt(dev); 4842 hns3_dev_release_mbufs(hns); 4843 hw->adapter_state = HNS3_NIC_CONFIGURED; 4844 } 4845 rte_eal_alarm_cancel(hns3_service_handler, dev); 4846 rte_spinlock_unlock(&hw->lock); 4847 } 4848 4849 static void 4850 hns3_dev_close(struct rte_eth_dev *eth_dev) 4851 { 4852 struct hns3_adapter *hns = eth_dev->data->dev_private; 4853 struct hns3_hw *hw = &hns->hw; 4854 4855 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 4856 rte_free(eth_dev->process_private); 4857 eth_dev->process_private = NULL; 4858 return; 4859 } 4860 4861 if (hw->adapter_state == HNS3_NIC_STARTED) 4862 hns3_dev_stop(eth_dev); 4863 4864 hw->adapter_state = HNS3_NIC_CLOSING; 4865 hns3_reset_abort(hns); 4866 hw->adapter_state = HNS3_NIC_CLOSED; 4867 4868 hns3_configure_all_mc_mac_addr(hns, true); 4869 hns3_remove_all_vlan_table(hns); 4870 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 4871 hns3_uninit_pf(eth_dev); 4872 hns3_free_all_queues(eth_dev); 4873 rte_free(hw->reset.wait_data); 4874 rte_free(eth_dev->process_private); 4875 eth_dev->process_private = NULL; 4876 hns3_mp_uninit_primary(); 4877 hns3_warn(hw, "Close port %d finished", hw->data->port_id); 4878 } 4879 4880 static int 4881 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4882 { 4883 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4884 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4885 4886 fc_conf->pause_time = pf->pause_time; 4887 4888 /* return fc current mode */ 4889 switch (hw->current_mode) { 4890 case HNS3_FC_FULL: 4891 fc_conf->mode = RTE_FC_FULL; 4892 break; 4893 case HNS3_FC_TX_PAUSE: 4894 fc_conf->mode = RTE_FC_TX_PAUSE; 4895 break; 4896 case HNS3_FC_RX_PAUSE: 4897 fc_conf->mode = RTE_FC_RX_PAUSE; 4898 break; 4899 case HNS3_FC_NONE: 4900 default: 4901 fc_conf->mode = RTE_FC_NONE; 4902 break; 4903 } 4904 4905 return 0; 4906 } 4907 4908 static void 4909 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode) 4910 { 4911 switch (mode) { 4912 case RTE_FC_NONE: 4913 hw->requested_mode = HNS3_FC_NONE; 4914 break; 4915 case RTE_FC_RX_PAUSE: 4916 hw->requested_mode = HNS3_FC_RX_PAUSE; 4917 break; 4918 case RTE_FC_TX_PAUSE: 4919 hw->requested_mode = HNS3_FC_TX_PAUSE; 4920 break; 4921 case RTE_FC_FULL: 4922 hw->requested_mode = HNS3_FC_FULL; 4923 break; 4924 default: 4925 hw->requested_mode = HNS3_FC_NONE; 4926 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is " 4927 "configured to RTE_FC_NONE", mode); 4928 break; 4929 } 4930 } 4931 4932 static int 4933 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4934 { 4935 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4936 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4937 int ret; 4938 4939 if (fc_conf->high_water || fc_conf->low_water || 4940 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 4941 hns3_err(hw, "Unsupported flow control settings specified, " 4942 "high_water(%u), low_water(%u), send_xon(%u) and " 4943 "mac_ctrl_frame_fwd(%u) must be set to '0'", 4944 fc_conf->high_water, fc_conf->low_water, 4945 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 4946 return -EINVAL; 4947 } 4948 if (fc_conf->autoneg) { 4949 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 4950 return -EINVAL; 4951 } 4952 if (!fc_conf->pause_time) { 4953 hns3_err(hw, "Invalid pause time %d setting.", 4954 fc_conf->pause_time); 4955 return -EINVAL; 4956 } 4957 4958 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 4959 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 4960 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 4961 "current_fc_status = %d", hw->current_fc_status); 4962 return -EOPNOTSUPP; 4963 } 4964 4965 hns3_get_fc_mode(hw, fc_conf->mode); 4966 if (hw->requested_mode == hw->current_mode && 4967 pf->pause_time == fc_conf->pause_time) 4968 return 0; 4969 4970 rte_spinlock_lock(&hw->lock); 4971 ret = hns3_fc_enable(dev, fc_conf); 4972 rte_spinlock_unlock(&hw->lock); 4973 4974 return ret; 4975 } 4976 4977 static int 4978 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 4979 struct rte_eth_pfc_conf *pfc_conf) 4980 { 4981 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4982 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4983 uint8_t priority; 4984 int ret; 4985 4986 if (!hns3_dev_dcb_supported(hw)) { 4987 hns3_err(hw, "This port does not support dcb configurations."); 4988 return -EOPNOTSUPP; 4989 } 4990 4991 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 4992 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 4993 hns3_err(hw, "Unsupported flow control settings specified, " 4994 "high_water(%u), low_water(%u), send_xon(%u) and " 4995 "mac_ctrl_frame_fwd(%u) must be set to '0'", 4996 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 4997 pfc_conf->fc.send_xon, 4998 pfc_conf->fc.mac_ctrl_frame_fwd); 4999 return -EINVAL; 5000 } 5001 if (pfc_conf->fc.autoneg) { 5002 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 5003 return -EINVAL; 5004 } 5005 if (pfc_conf->fc.pause_time == 0) { 5006 hns3_err(hw, "Invalid pause time %d setting.", 5007 pfc_conf->fc.pause_time); 5008 return -EINVAL; 5009 } 5010 5011 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 5012 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 5013 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 5014 "current_fc_status = %d", hw->current_fc_status); 5015 return -EOPNOTSUPP; 5016 } 5017 5018 priority = pfc_conf->priority; 5019 hns3_get_fc_mode(hw, pfc_conf->fc.mode); 5020 if (hw->dcb_info.pfc_en & BIT(priority) && 5021 hw->requested_mode == hw->current_mode && 5022 pfc_conf->fc.pause_time == pf->pause_time) 5023 return 0; 5024 5025 rte_spinlock_lock(&hw->lock); 5026 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 5027 rte_spinlock_unlock(&hw->lock); 5028 5029 return ret; 5030 } 5031 5032 static int 5033 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 5034 { 5035 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5036 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5037 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 5038 int i; 5039 5040 rte_spinlock_lock(&hw->lock); 5041 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) 5042 dcb_info->nb_tcs = pf->local_max_tc; 5043 else 5044 dcb_info->nb_tcs = 1; 5045 5046 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 5047 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 5048 for (i = 0; i < dcb_info->nb_tcs; i++) 5049 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 5050 5051 for (i = 0; i < hw->num_tc; i++) { 5052 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 5053 dcb_info->tc_queue.tc_txq[0][i].base = 5054 hw->tc_queue[i].tqp_offset; 5055 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 5056 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 5057 hw->tc_queue[i].tqp_count; 5058 } 5059 rte_spinlock_unlock(&hw->lock); 5060 5061 return 0; 5062 } 5063 5064 static int 5065 hns3_reinit_dev(struct hns3_adapter *hns) 5066 { 5067 struct hns3_hw *hw = &hns->hw; 5068 int ret; 5069 5070 ret = hns3_cmd_init(hw); 5071 if (ret) { 5072 hns3_err(hw, "Failed to init cmd: %d", ret); 5073 return ret; 5074 } 5075 5076 ret = hns3_reset_all_queues(hns); 5077 if (ret) { 5078 hns3_err(hw, "Failed to reset all queues: %d", ret); 5079 return ret; 5080 } 5081 5082 ret = hns3_init_hardware(hns); 5083 if (ret) { 5084 hns3_err(hw, "Failed to init hardware: %d", ret); 5085 return ret; 5086 } 5087 5088 ret = hns3_enable_hw_error_intr(hns, true); 5089 if (ret) { 5090 hns3_err(hw, "fail to enable hw error interrupts: %d", 5091 ret); 5092 return ret; 5093 } 5094 hns3_info(hw, "Reset done, driver initialization finished."); 5095 5096 return 0; 5097 } 5098 5099 static bool 5100 is_pf_reset_done(struct hns3_hw *hw) 5101 { 5102 uint32_t val, reg, reg_bit; 5103 5104 switch (hw->reset.level) { 5105 case HNS3_IMP_RESET: 5106 reg = HNS3_GLOBAL_RESET_REG; 5107 reg_bit = HNS3_IMP_RESET_BIT; 5108 break; 5109 case HNS3_GLOBAL_RESET: 5110 reg = HNS3_GLOBAL_RESET_REG; 5111 reg_bit = HNS3_GLOBAL_RESET_BIT; 5112 break; 5113 case HNS3_FUNC_RESET: 5114 reg = HNS3_FUN_RST_ING; 5115 reg_bit = HNS3_FUN_RST_ING_B; 5116 break; 5117 case HNS3_FLR_RESET: 5118 default: 5119 hns3_err(hw, "Wait for unsupported reset level: %d", 5120 hw->reset.level); 5121 return true; 5122 } 5123 val = hns3_read_dev(hw, reg); 5124 if (hns3_get_bit(val, reg_bit)) 5125 return false; 5126 else 5127 return true; 5128 } 5129 5130 bool 5131 hns3_is_reset_pending(struct hns3_adapter *hns) 5132 { 5133 struct hns3_hw *hw = &hns->hw; 5134 enum hns3_reset_level reset; 5135 5136 hns3_check_event_cause(hns, NULL); 5137 reset = hns3_get_reset_level(hns, &hw->reset.pending); 5138 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 5139 hns3_warn(hw, "High level reset %d is pending", reset); 5140 return true; 5141 } 5142 reset = hns3_get_reset_level(hns, &hw->reset.request); 5143 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 5144 hns3_warn(hw, "High level reset %d is request", reset); 5145 return true; 5146 } 5147 return false; 5148 } 5149 5150 static int 5151 hns3_wait_hardware_ready(struct hns3_adapter *hns) 5152 { 5153 struct hns3_hw *hw = &hns->hw; 5154 struct hns3_wait_data *wait_data = hw->reset.wait_data; 5155 struct timeval tv; 5156 5157 if (wait_data->result == HNS3_WAIT_SUCCESS) 5158 return 0; 5159 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 5160 gettimeofday(&tv, NULL); 5161 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 5162 tv.tv_sec, tv.tv_usec); 5163 return -ETIME; 5164 } else if (wait_data->result == HNS3_WAIT_REQUEST) 5165 return -EAGAIN; 5166 5167 wait_data->hns = hns; 5168 wait_data->check_completion = is_pf_reset_done; 5169 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 5170 HNS3_RESET_WAIT_MS + get_timeofday_ms(); 5171 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 5172 wait_data->count = HNS3_RESET_WAIT_CNT; 5173 wait_data->result = HNS3_WAIT_REQUEST; 5174 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 5175 return -EAGAIN; 5176 } 5177 5178 static int 5179 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 5180 { 5181 struct hns3_cmd_desc desc; 5182 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 5183 5184 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 5185 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 5186 req->fun_reset_vfid = func_id; 5187 5188 return hns3_cmd_send(hw, &desc, 1); 5189 } 5190 5191 static int 5192 hns3_imp_reset_cmd(struct hns3_hw *hw) 5193 { 5194 struct hns3_cmd_desc desc; 5195 5196 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 5197 desc.data[0] = 0xeedd; 5198 5199 return hns3_cmd_send(hw, &desc, 1); 5200 } 5201 5202 static void 5203 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 5204 { 5205 struct hns3_hw *hw = &hns->hw; 5206 struct timeval tv; 5207 uint32_t val; 5208 5209 gettimeofday(&tv, NULL); 5210 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 5211 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 5212 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 5213 tv.tv_sec, tv.tv_usec); 5214 return; 5215 } 5216 5217 switch (reset_level) { 5218 case HNS3_IMP_RESET: 5219 hns3_imp_reset_cmd(hw); 5220 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 5221 tv.tv_sec, tv.tv_usec); 5222 break; 5223 case HNS3_GLOBAL_RESET: 5224 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 5225 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 5226 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 5227 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 5228 tv.tv_sec, tv.tv_usec); 5229 break; 5230 case HNS3_FUNC_RESET: 5231 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 5232 tv.tv_sec, tv.tv_usec); 5233 /* schedule again to check later */ 5234 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 5235 hns3_schedule_reset(hns); 5236 break; 5237 default: 5238 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 5239 return; 5240 } 5241 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 5242 } 5243 5244 static enum hns3_reset_level 5245 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 5246 { 5247 struct hns3_hw *hw = &hns->hw; 5248 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 5249 5250 /* Return the highest priority reset level amongst all */ 5251 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 5252 reset_level = HNS3_IMP_RESET; 5253 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 5254 reset_level = HNS3_GLOBAL_RESET; 5255 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 5256 reset_level = HNS3_FUNC_RESET; 5257 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 5258 reset_level = HNS3_FLR_RESET; 5259 5260 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 5261 return HNS3_NONE_RESET; 5262 5263 return reset_level; 5264 } 5265 5266 static void 5267 hns3_record_imp_error(struct hns3_adapter *hns) 5268 { 5269 struct hns3_hw *hw = &hns->hw; 5270 uint32_t reg_val; 5271 5272 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5273 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { 5274 hns3_warn(hw, "Detected IMP RD poison!"); 5275 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); 5276 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); 5277 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5278 } 5279 5280 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { 5281 hns3_warn(hw, "Detected IMP CMDQ error!"); 5282 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); 5283 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); 5284 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5285 } 5286 } 5287 5288 static int 5289 hns3_prepare_reset(struct hns3_adapter *hns) 5290 { 5291 struct hns3_hw *hw = &hns->hw; 5292 uint32_t reg_val; 5293 int ret; 5294 5295 switch (hw->reset.level) { 5296 case HNS3_FUNC_RESET: 5297 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 5298 if (ret) 5299 return ret; 5300 5301 /* 5302 * After performaning pf reset, it is not necessary to do the 5303 * mailbox handling or send any command to firmware, because 5304 * any mailbox handling or command to firmware is only valid 5305 * after hns3_cmd_init is called. 5306 */ 5307 rte_atomic16_set(&hw->reset.disable_cmd, 1); 5308 hw->reset.stats.request_cnt++; 5309 break; 5310 case HNS3_IMP_RESET: 5311 hns3_record_imp_error(hns); 5312 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5313 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 5314 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 5315 break; 5316 default: 5317 break; 5318 } 5319 return 0; 5320 } 5321 5322 static int 5323 hns3_set_rst_done(struct hns3_hw *hw) 5324 { 5325 struct hns3_pf_rst_done_cmd *req; 5326 struct hns3_cmd_desc desc; 5327 5328 req = (struct hns3_pf_rst_done_cmd *)desc.data; 5329 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 5330 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 5331 return hns3_cmd_send(hw, &desc, 1); 5332 } 5333 5334 static int 5335 hns3_stop_service(struct hns3_adapter *hns) 5336 { 5337 struct hns3_hw *hw = &hns->hw; 5338 struct rte_eth_dev *eth_dev; 5339 5340 eth_dev = &rte_eth_devices[hw->data->port_id]; 5341 if (hw->adapter_state == HNS3_NIC_STARTED) 5342 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 5343 hw->mac.link_status = ETH_LINK_DOWN; 5344 5345 hns3_set_rxtx_function(eth_dev); 5346 rte_wmb(); 5347 /* Disable datapath on secondary process. */ 5348 hns3_mp_req_stop_rxtx(eth_dev); 5349 rte_delay_ms(hw->tqps_num); 5350 5351 rte_spinlock_lock(&hw->lock); 5352 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 5353 hw->adapter_state == HNS3_NIC_STOPPING) { 5354 hns3_do_stop(hns); 5355 hw->reset.mbuf_deferred_free = true; 5356 } else 5357 hw->reset.mbuf_deferred_free = false; 5358 5359 /* 5360 * It is cumbersome for hardware to pick-and-choose entries for deletion 5361 * from table space. Hence, for function reset software intervention is 5362 * required to delete the entries 5363 */ 5364 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) 5365 hns3_configure_all_mc_mac_addr(hns, true); 5366 rte_spinlock_unlock(&hw->lock); 5367 5368 return 0; 5369 } 5370 5371 static int 5372 hns3_start_service(struct hns3_adapter *hns) 5373 { 5374 struct hns3_hw *hw = &hns->hw; 5375 struct rte_eth_dev *eth_dev; 5376 5377 if (hw->reset.level == HNS3_IMP_RESET || 5378 hw->reset.level == HNS3_GLOBAL_RESET) 5379 hns3_set_rst_done(hw); 5380 eth_dev = &rte_eth_devices[hw->data->port_id]; 5381 hns3_set_rxtx_function(eth_dev); 5382 hns3_mp_req_start_rxtx(eth_dev); 5383 if (hw->adapter_state == HNS3_NIC_STARTED) { 5384 hns3_service_handler(eth_dev); 5385 5386 /* Enable interrupt of all rx queues before enabling queues */ 5387 hns3_dev_all_rx_queue_intr_enable(hw, true); 5388 /* 5389 * When finished the initialization, enable queues to receive 5390 * and transmit packets. 5391 */ 5392 hns3_enable_all_queues(hw, true); 5393 } 5394 5395 return 0; 5396 } 5397 5398 static int 5399 hns3_restore_conf(struct hns3_adapter *hns) 5400 { 5401 struct hns3_hw *hw = &hns->hw; 5402 int ret; 5403 5404 ret = hns3_configure_all_mac_addr(hns, false); 5405 if (ret) 5406 return ret; 5407 5408 ret = hns3_configure_all_mc_mac_addr(hns, false); 5409 if (ret) 5410 goto err_mc_mac; 5411 5412 ret = hns3_dev_promisc_restore(hns); 5413 if (ret) 5414 goto err_promisc; 5415 5416 ret = hns3_restore_vlan_table(hns); 5417 if (ret) 5418 goto err_promisc; 5419 5420 ret = hns3_restore_vlan_conf(hns); 5421 if (ret) 5422 goto err_promisc; 5423 5424 ret = hns3_restore_all_fdir_filter(hns); 5425 if (ret) 5426 goto err_promisc; 5427 5428 ret = hns3_restore_rx_interrupt(hw); 5429 if (ret) 5430 goto err_promisc; 5431 5432 ret = hns3_restore_gro_conf(hw); 5433 if (ret) 5434 goto err_promisc; 5435 5436 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 5437 ret = hns3_do_start(hns, false); 5438 if (ret) 5439 goto err_promisc; 5440 hns3_info(hw, "hns3 dev restart successful!"); 5441 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 5442 hw->adapter_state = HNS3_NIC_CONFIGURED; 5443 return 0; 5444 5445 err_promisc: 5446 hns3_configure_all_mc_mac_addr(hns, true); 5447 err_mc_mac: 5448 hns3_configure_all_mac_addr(hns, true); 5449 return ret; 5450 } 5451 5452 static void 5453 hns3_reset_service(void *param) 5454 { 5455 struct hns3_adapter *hns = (struct hns3_adapter *)param; 5456 struct hns3_hw *hw = &hns->hw; 5457 enum hns3_reset_level reset_level; 5458 struct timeval tv_delta; 5459 struct timeval tv_start; 5460 struct timeval tv; 5461 uint64_t msec; 5462 int ret; 5463 5464 /* 5465 * The interrupt is not triggered within the delay time. 5466 * The interrupt may have been lost. It is necessary to handle 5467 * the interrupt to recover from the error. 5468 */ 5469 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) { 5470 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); 5471 hns3_err(hw, "Handling interrupts in delayed tasks"); 5472 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 5473 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5474 if (reset_level == HNS3_NONE_RESET) { 5475 hns3_err(hw, "No reset level is set, try IMP reset"); 5476 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 5477 } 5478 } 5479 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE); 5480 5481 /* 5482 * Check if there is any ongoing reset in the hardware. This status can 5483 * be checked from reset_pending. If there is then, we need to wait for 5484 * hardware to complete reset. 5485 * a. If we are able to figure out in reasonable time that hardware 5486 * has fully resetted then, we can proceed with driver, client 5487 * reset. 5488 * b. else, we can come back later to check this status so re-sched 5489 * now. 5490 */ 5491 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5492 if (reset_level != HNS3_NONE_RESET) { 5493 gettimeofday(&tv_start, NULL); 5494 ret = hns3_reset_process(hns, reset_level); 5495 gettimeofday(&tv, NULL); 5496 timersub(&tv, &tv_start, &tv_delta); 5497 msec = tv_delta.tv_sec * MSEC_PER_SEC + 5498 tv_delta.tv_usec / USEC_PER_MSEC; 5499 if (msec > HNS3_RESET_PROCESS_MS) 5500 hns3_err(hw, "%d handle long time delta %" PRIx64 5501 " ms time=%ld.%.6ld", 5502 hw->reset.level, msec, 5503 tv.tv_sec, tv.tv_usec); 5504 if (ret == -EAGAIN) 5505 return; 5506 } 5507 5508 /* Check if we got any *new* reset requests to be honored */ 5509 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 5510 if (reset_level != HNS3_NONE_RESET) 5511 hns3_msix_process(hns, reset_level); 5512 } 5513 5514 static const struct eth_dev_ops hns3_eth_dev_ops = { 5515 .dev_start = hns3_dev_start, 5516 .dev_stop = hns3_dev_stop, 5517 .dev_close = hns3_dev_close, 5518 .promiscuous_enable = hns3_dev_promiscuous_enable, 5519 .promiscuous_disable = hns3_dev_promiscuous_disable, 5520 .allmulticast_enable = hns3_dev_allmulticast_enable, 5521 .allmulticast_disable = hns3_dev_allmulticast_disable, 5522 .mtu_set = hns3_dev_mtu_set, 5523 .stats_get = hns3_stats_get, 5524 .stats_reset = hns3_stats_reset, 5525 .xstats_get = hns3_dev_xstats_get, 5526 .xstats_get_names = hns3_dev_xstats_get_names, 5527 .xstats_reset = hns3_dev_xstats_reset, 5528 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 5529 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 5530 .dev_infos_get = hns3_dev_infos_get, 5531 .fw_version_get = hns3_fw_version_get, 5532 .rx_queue_setup = hns3_rx_queue_setup, 5533 .tx_queue_setup = hns3_tx_queue_setup, 5534 .rx_queue_release = hns3_dev_rx_queue_release, 5535 .tx_queue_release = hns3_dev_tx_queue_release, 5536 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 5537 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 5538 .rxq_info_get = hns3_rxq_info_get, 5539 .txq_info_get = hns3_txq_info_get, 5540 .dev_configure = hns3_dev_configure, 5541 .flow_ctrl_get = hns3_flow_ctrl_get, 5542 .flow_ctrl_set = hns3_flow_ctrl_set, 5543 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 5544 .mac_addr_add = hns3_add_mac_addr, 5545 .mac_addr_remove = hns3_remove_mac_addr, 5546 .mac_addr_set = hns3_set_default_mac_addr, 5547 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 5548 .link_update = hns3_dev_link_update, 5549 .rss_hash_update = hns3_dev_rss_hash_update, 5550 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 5551 .reta_update = hns3_dev_rss_reta_update, 5552 .reta_query = hns3_dev_rss_reta_query, 5553 .filter_ctrl = hns3_dev_filter_ctrl, 5554 .vlan_filter_set = hns3_vlan_filter_set, 5555 .vlan_tpid_set = hns3_vlan_tpid_set, 5556 .vlan_offload_set = hns3_vlan_offload_set, 5557 .vlan_pvid_set = hns3_vlan_pvid_set, 5558 .get_reg = hns3_get_regs, 5559 .get_dcb_info = hns3_get_dcb_info, 5560 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 5561 }; 5562 5563 static const struct hns3_reset_ops hns3_reset_ops = { 5564 .reset_service = hns3_reset_service, 5565 .stop_service = hns3_stop_service, 5566 .prepare_reset = hns3_prepare_reset, 5567 .wait_hardware_ready = hns3_wait_hardware_ready, 5568 .reinit_dev = hns3_reinit_dev, 5569 .restore_conf = hns3_restore_conf, 5570 .start_service = hns3_start_service, 5571 }; 5572 5573 static int 5574 hns3_dev_init(struct rte_eth_dev *eth_dev) 5575 { 5576 struct hns3_adapter *hns = eth_dev->data->dev_private; 5577 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 5578 struct rte_ether_addr *eth_addr; 5579 struct hns3_hw *hw = &hns->hw; 5580 int ret; 5581 5582 PMD_INIT_FUNC_TRACE(); 5583 5584 eth_dev->process_private = (struct hns3_process_private *) 5585 rte_zmalloc_socket("hns3_filter_list", 5586 sizeof(struct hns3_process_private), 5587 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 5588 if (eth_dev->process_private == NULL) { 5589 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 5590 return -ENOMEM; 5591 } 5592 /* initialize flow filter lists */ 5593 hns3_filterlist_init(eth_dev); 5594 5595 hns3_set_rxtx_function(eth_dev); 5596 eth_dev->dev_ops = &hns3_eth_dev_ops; 5597 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 5598 ret = hns3_mp_init_secondary(); 5599 if (ret) { 5600 PMD_INIT_LOG(ERR, "Failed to init for secondary " 5601 "process, ret = %d", ret); 5602 goto err_mp_init_secondary; 5603 } 5604 5605 hw->secondary_cnt++; 5606 return 0; 5607 } 5608 5609 ret = hns3_mp_init_primary(); 5610 if (ret) { 5611 PMD_INIT_LOG(ERR, 5612 "Failed to init for primary process, ret = %d", 5613 ret); 5614 goto err_mp_init_primary; 5615 } 5616 5617 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 5618 hns->is_vf = false; 5619 hw->data = eth_dev->data; 5620 5621 /* 5622 * Set default max packet size according to the mtu 5623 * default vale in DPDK frame. 5624 */ 5625 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 5626 5627 ret = hns3_reset_init(hw); 5628 if (ret) 5629 goto err_init_reset; 5630 hw->reset.ops = &hns3_reset_ops; 5631 5632 ret = hns3_init_pf(eth_dev); 5633 if (ret) { 5634 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 5635 goto err_init_pf; 5636 } 5637 5638 /* Allocate memory for storing MAC addresses */ 5639 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac", 5640 sizeof(struct rte_ether_addr) * 5641 HNS3_UC_MACADDR_NUM, 0); 5642 if (eth_dev->data->mac_addrs == NULL) { 5643 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 5644 "to store MAC addresses", 5645 sizeof(struct rte_ether_addr) * 5646 HNS3_UC_MACADDR_NUM); 5647 ret = -ENOMEM; 5648 goto err_rte_zmalloc; 5649 } 5650 5651 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 5652 if (!rte_is_valid_assigned_ether_addr(eth_addr)) { 5653 rte_eth_random_addr(hw->mac.mac_addr); 5654 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 5655 (struct rte_ether_addr *)hw->mac.mac_addr); 5656 hns3_warn(hw, "default mac_addr from firmware is an invalid " 5657 "unicast address, using random MAC address %s", 5658 mac_str); 5659 } 5660 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 5661 ð_dev->data->mac_addrs[0]); 5662 5663 hw->adapter_state = HNS3_NIC_INITIALIZED; 5664 /* 5665 * Pass the information to the rte_eth_dev_close() that it should also 5666 * release the private port resources. 5667 */ 5668 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 5669 5670 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) { 5671 hns3_err(hw, "Reschedule reset service after dev_init"); 5672 hns3_schedule_reset(hns); 5673 } else { 5674 /* IMP will wait ready flag before reset */ 5675 hns3_notify_reset_ready(hw, false); 5676 } 5677 5678 hns3_info(hw, "hns3 dev initialization successful!"); 5679 return 0; 5680 5681 err_rte_zmalloc: 5682 hns3_uninit_pf(eth_dev); 5683 5684 err_init_pf: 5685 rte_free(hw->reset.wait_data); 5686 5687 err_init_reset: 5688 hns3_mp_uninit_primary(); 5689 5690 err_mp_init_primary: 5691 err_mp_init_secondary: 5692 eth_dev->dev_ops = NULL; 5693 eth_dev->rx_pkt_burst = NULL; 5694 eth_dev->tx_pkt_burst = NULL; 5695 eth_dev->tx_pkt_prepare = NULL; 5696 rte_free(eth_dev->process_private); 5697 eth_dev->process_private = NULL; 5698 return ret; 5699 } 5700 5701 static int 5702 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 5703 { 5704 struct hns3_adapter *hns = eth_dev->data->dev_private; 5705 struct hns3_hw *hw = &hns->hw; 5706 5707 PMD_INIT_FUNC_TRACE(); 5708 5709 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5710 return -EPERM; 5711 5712 eth_dev->dev_ops = NULL; 5713 eth_dev->rx_pkt_burst = NULL; 5714 eth_dev->tx_pkt_burst = NULL; 5715 eth_dev->tx_pkt_prepare = NULL; 5716 if (hw->adapter_state < HNS3_NIC_CLOSING) 5717 hns3_dev_close(eth_dev); 5718 5719 hw->adapter_state = HNS3_NIC_REMOVED; 5720 return 0; 5721 } 5722 5723 static int 5724 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5725 struct rte_pci_device *pci_dev) 5726 { 5727 return rte_eth_dev_pci_generic_probe(pci_dev, 5728 sizeof(struct hns3_adapter), 5729 hns3_dev_init); 5730 } 5731 5732 static int 5733 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 5734 { 5735 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 5736 } 5737 5738 static const struct rte_pci_id pci_id_hns3_map[] = { 5739 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 5740 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 5741 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 5742 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 5743 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 5744 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, 5745 { .vendor_id = 0, /* sentinel */ }, 5746 }; 5747 5748 static struct rte_pci_driver rte_hns3_pmd = { 5749 .id_table = pci_id_hns3_map, 5750 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 5751 .probe = eth_hns3_pci_probe, 5752 .remove = eth_hns3_pci_remove, 5753 }; 5754 5755 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 5756 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 5757 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 5758 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE); 5759 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE); 5760