1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <rte_alarm.h> 6 #include <rte_bus_pci.h> 7 #include <ethdev_pci.h> 8 #include <rte_pci.h> 9 #include <rte_kvargs.h> 10 11 #include "hns3_ethdev.h" 12 #include "hns3_logs.h" 13 #include "hns3_rxtx.h" 14 #include "hns3_intr.h" 15 #include "hns3_regs.h" 16 #include "hns3_dcb.h" 17 #include "hns3_mp.h" 18 19 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 20 #define HNS3_SERVICE_QUICK_INTERVAL 10 21 #define HNS3_INVALID_PVID 0xFFFF 22 23 #define HNS3_FILTER_TYPE_VF 0 24 #define HNS3_FILTER_TYPE_PORT 1 25 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 26 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 27 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 28 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 29 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 30 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 31 | HNS3_FILTER_FE_ROCE_EGRESS_B) 32 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 33 | HNS3_FILTER_FE_ROCE_INGRESS_B) 34 35 /* Reset related Registers */ 36 #define HNS3_GLOBAL_RESET_BIT 0 37 #define HNS3_CORE_RESET_BIT 1 38 #define HNS3_IMP_RESET_BIT 2 39 #define HNS3_FUN_RST_ING_B 0 40 41 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U 43 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U 44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U 45 46 #define HNS3_RESET_WAIT_MS 100 47 #define HNS3_RESET_WAIT_CNT 200 48 49 /* FEC mode order defined in HNS3 hardware */ 50 #define HNS3_HW_FEC_MODE_NOFEC 0 51 #define HNS3_HW_FEC_MODE_BASER 1 52 #define HNS3_HW_FEC_MODE_RS 2 53 54 enum hns3_evt_cause { 55 HNS3_VECTOR0_EVENT_RST, 56 HNS3_VECTOR0_EVENT_MBX, 57 HNS3_VECTOR0_EVENT_ERR, 58 HNS3_VECTOR0_EVENT_PTP, 59 HNS3_VECTOR0_EVENT_OTHER, 60 }; 61 62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = { 63 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 66 67 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 71 72 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 75 76 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 80 81 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 84 85 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) } 88 }; 89 90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 91 uint64_t *levels); 92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 94 int on); 95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev); 96 static bool hns3_update_link_status(struct hns3_hw *hw); 97 98 static int hns3_add_mc_addr(struct hns3_hw *hw, 99 struct rte_ether_addr *mac_addr); 100 static int hns3_remove_mc_addr(struct hns3_hw *hw, 101 struct rte_ether_addr *mac_addr); 102 static int hns3_restore_fec(struct hns3_hw *hw); 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw); 104 static int hns3_do_stop(struct hns3_adapter *hns); 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds); 106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable); 107 108 void hns3_ether_format_addr(char *buf, uint16_t size, 109 const struct rte_ether_addr *ether_addr) 110 { 111 snprintf(buf, size, "%02X:**:**:**:%02X:%02X", 112 ether_addr->addr_bytes[0], 113 ether_addr->addr_bytes[4], 114 ether_addr->addr_bytes[5]); 115 } 116 117 static void 118 hns3_pf_disable_irq0(struct hns3_hw *hw) 119 { 120 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 121 } 122 123 static void 124 hns3_pf_enable_irq0(struct hns3_hw *hw) 125 { 126 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 127 } 128 129 static enum hns3_evt_cause 130 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay, 131 uint32_t *vec_val) 132 { 133 struct hns3_hw *hw = &hns->hw; 134 135 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 136 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 137 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 138 if (!is_delay) { 139 hw->reset.stats.imp_cnt++; 140 hns3_warn(hw, "IMP reset detected, clear reset status"); 141 } else { 142 hns3_schedule_delayed_reset(hns); 143 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 144 } 145 146 return HNS3_VECTOR0_EVENT_RST; 147 } 148 149 static enum hns3_evt_cause 150 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay, 151 uint32_t *vec_val) 152 { 153 struct hns3_hw *hw = &hns->hw; 154 155 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 156 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 157 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 158 if (!is_delay) { 159 hw->reset.stats.global_cnt++; 160 hns3_warn(hw, "Global reset detected, clear reset status"); 161 } else { 162 hns3_schedule_delayed_reset(hns); 163 hns3_warn(hw, 164 "Global reset detected, don't clear reset status"); 165 } 166 167 return HNS3_VECTOR0_EVENT_RST; 168 } 169 170 static enum hns3_evt_cause 171 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 172 { 173 struct hns3_hw *hw = &hns->hw; 174 uint32_t vector0_int_stats; 175 uint32_t cmdq_src_val; 176 uint32_t hw_err_src_reg; 177 uint32_t val; 178 enum hns3_evt_cause ret; 179 bool is_delay; 180 181 /* fetch the events from their corresponding regs */ 182 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 183 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 184 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 185 186 is_delay = clearval == NULL ? true : false; 187 /* 188 * Assumption: If by any chance reset and mailbox events are reported 189 * together then we will only process reset event and defer the 190 * processing of the mailbox events. Since, we would have not cleared 191 * RX CMDQ event this time we would receive again another interrupt 192 * from H/W just for the mailbox. 193 */ 194 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 195 ret = hns3_proc_imp_reset_event(hns, is_delay, &val); 196 goto out; 197 } 198 199 /* Global reset */ 200 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 201 ret = hns3_proc_global_reset_event(hns, is_delay, &val); 202 goto out; 203 } 204 205 /* Check for vector0 1588 event source */ 206 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) { 207 val = BIT(HNS3_VECTOR0_1588_INT_B); 208 ret = HNS3_VECTOR0_EVENT_PTP; 209 goto out; 210 } 211 212 /* check for vector0 msix event source */ 213 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || 214 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { 215 val = vector0_int_stats | hw_err_src_reg; 216 ret = HNS3_VECTOR0_EVENT_ERR; 217 goto out; 218 } 219 220 /* check for vector0 mailbox(=CMDQ RX) event source */ 221 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 222 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 223 val = cmdq_src_val; 224 ret = HNS3_VECTOR0_EVENT_MBX; 225 goto out; 226 } 227 228 val = vector0_int_stats; 229 ret = HNS3_VECTOR0_EVENT_OTHER; 230 out: 231 232 if (clearval) 233 *clearval = val; 234 return ret; 235 } 236 237 static bool 238 hns3_is_1588_event_type(uint32_t event_type) 239 { 240 return (event_type == HNS3_VECTOR0_EVENT_PTP); 241 } 242 243 static void 244 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 245 { 246 if (event_type == HNS3_VECTOR0_EVENT_RST || 247 hns3_is_1588_event_type(event_type)) 248 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 249 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 250 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 251 } 252 253 static void 254 hns3_clear_all_event_cause(struct hns3_hw *hw) 255 { 256 uint32_t vector0_int_stats; 257 258 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 259 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 260 hns3_warn(hw, "Probe during IMP reset interrupt"); 261 262 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 263 hns3_warn(hw, "Probe during Global reset interrupt"); 264 265 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 266 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 267 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 268 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 269 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 270 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP, 271 BIT(HNS3_VECTOR0_1588_INT_B)); 272 } 273 274 static void 275 hns3_handle_mac_tnl(struct hns3_hw *hw) 276 { 277 struct hns3_cmd_desc desc; 278 uint32_t status; 279 int ret; 280 281 /* query and clear mac tnl interrupt */ 282 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true); 283 ret = hns3_cmd_send(hw, &desc, 1); 284 if (ret) { 285 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret); 286 return; 287 } 288 289 status = rte_le_to_cpu_32(desc.data[0]); 290 if (status) { 291 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status); 292 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT, 293 false); 294 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR); 295 ret = hns3_cmd_send(hw, &desc, 1); 296 if (ret) 297 hns3_err(hw, "failed to clear mac tnl int, ret = %d.", 298 ret); 299 } 300 } 301 302 static void 303 hns3_interrupt_handler(void *param) 304 { 305 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 306 struct hns3_adapter *hns = dev->data->dev_private; 307 struct hns3_hw *hw = &hns->hw; 308 enum hns3_evt_cause event_cause; 309 uint32_t clearval = 0; 310 uint32_t vector0_int; 311 uint32_t ras_int; 312 uint32_t cmdq_int; 313 314 /* Disable interrupt */ 315 hns3_pf_disable_irq0(hw); 316 317 event_cause = hns3_check_event_cause(hns, &clearval); 318 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 319 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 320 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 321 hns3_clear_event_cause(hw, event_cause, clearval); 322 /* vector 0 interrupt is shared with reset and mailbox source events. */ 323 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 324 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x " 325 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 326 vector0_int, ras_int, cmdq_int); 327 hns3_handle_mac_tnl(hw); 328 hns3_handle_error(hns); 329 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { 330 hns3_warn(hw, "received reset interrupt"); 331 hns3_schedule_reset(hns); 332 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) { 333 hns3_dev_handle_mbx_msg(hw); 334 } else { 335 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x " 336 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 337 vector0_int, ras_int, cmdq_int); 338 } 339 340 /* Enable interrupt if it is not cause by reset */ 341 hns3_pf_enable_irq0(hw); 342 } 343 344 static int 345 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 346 { 347 #define HNS3_VLAN_ID_OFFSET_STEP 160 348 #define HNS3_VLAN_BYTE_SIZE 8 349 struct hns3_vlan_filter_pf_cfg_cmd *req; 350 struct hns3_hw *hw = &hns->hw; 351 uint8_t vlan_offset_byte_val; 352 struct hns3_cmd_desc desc; 353 uint8_t vlan_offset_byte; 354 uint8_t vlan_offset_base; 355 int ret; 356 357 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 358 359 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 360 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 361 HNS3_VLAN_BYTE_SIZE; 362 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 363 364 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 365 req->vlan_offset = vlan_offset_base; 366 req->vlan_cfg = on ? 0 : 1; 367 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 368 369 ret = hns3_cmd_send(hw, &desc, 1); 370 if (ret) 371 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 372 vlan_id, ret); 373 374 return ret; 375 } 376 377 static void 378 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 379 { 380 struct hns3_user_vlan_table *vlan_entry; 381 struct hns3_pf *pf = &hns->pf; 382 383 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 384 if (vlan_entry->vlan_id == vlan_id) { 385 if (vlan_entry->hd_tbl_status) 386 hns3_set_port_vlan_filter(hns, vlan_id, 0); 387 LIST_REMOVE(vlan_entry, next); 388 rte_free(vlan_entry); 389 break; 390 } 391 } 392 } 393 394 static void 395 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 396 bool writen_to_tbl) 397 { 398 struct hns3_user_vlan_table *vlan_entry; 399 struct hns3_hw *hw = &hns->hw; 400 struct hns3_pf *pf = &hns->pf; 401 402 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 403 if (vlan_entry->vlan_id == vlan_id) 404 return; 405 } 406 407 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 408 if (vlan_entry == NULL) { 409 hns3_err(hw, "Failed to malloc hns3 vlan table"); 410 return; 411 } 412 413 vlan_entry->hd_tbl_status = writen_to_tbl; 414 vlan_entry->vlan_id = vlan_id; 415 416 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 417 } 418 419 static int 420 hns3_restore_vlan_table(struct hns3_adapter *hns) 421 { 422 struct hns3_user_vlan_table *vlan_entry; 423 struct hns3_hw *hw = &hns->hw; 424 struct hns3_pf *pf = &hns->pf; 425 uint16_t vlan_id; 426 int ret = 0; 427 428 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 429 return hns3_vlan_pvid_configure(hns, 430 hw->port_base_vlan_cfg.pvid, 1); 431 432 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 433 if (vlan_entry->hd_tbl_status) { 434 vlan_id = vlan_entry->vlan_id; 435 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 436 if (ret) 437 break; 438 } 439 } 440 441 return ret; 442 } 443 444 static int 445 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 446 { 447 struct hns3_hw *hw = &hns->hw; 448 bool writen_to_tbl = false; 449 int ret = 0; 450 451 /* 452 * When vlan filter is enabled, hardware regards packets without vlan 453 * as packets with vlan 0. So, to receive packets without vlan, vlan id 454 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter. 455 */ 456 if (on == 0 && vlan_id == 0) 457 return 0; 458 459 /* 460 * When port base vlan enabled, we use port base vlan as the vlan 461 * filter condition. In this case, we don't update vlan filter table 462 * when user add new vlan or remove exist vlan, just update the 463 * vlan list. The vlan id in vlan list will be written in vlan filter 464 * table until port base vlan disabled 465 */ 466 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 467 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 468 writen_to_tbl = true; 469 } 470 471 if (ret == 0) { 472 if (on) 473 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 474 else 475 hns3_rm_dev_vlan_table(hns, vlan_id); 476 } 477 return ret; 478 } 479 480 static int 481 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 482 { 483 struct hns3_adapter *hns = dev->data->dev_private; 484 struct hns3_hw *hw = &hns->hw; 485 int ret; 486 487 rte_spinlock_lock(&hw->lock); 488 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 489 rte_spinlock_unlock(&hw->lock); 490 return ret; 491 } 492 493 static int 494 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 495 uint16_t tpid) 496 { 497 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 498 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 499 struct hns3_hw *hw = &hns->hw; 500 struct hns3_cmd_desc desc; 501 int ret; 502 503 if ((vlan_type != ETH_VLAN_TYPE_INNER && 504 vlan_type != ETH_VLAN_TYPE_OUTER)) { 505 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 506 return -EINVAL; 507 } 508 509 if (tpid != RTE_ETHER_TYPE_VLAN) { 510 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 511 return -EINVAL; 512 } 513 514 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 515 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 516 517 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 518 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 519 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 520 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 521 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 522 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 523 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 524 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 525 } 526 527 ret = hns3_cmd_send(hw, &desc, 1); 528 if (ret) { 529 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 530 ret); 531 return ret; 532 } 533 534 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 535 536 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 537 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 538 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 539 540 ret = hns3_cmd_send(hw, &desc, 1); 541 if (ret) 542 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 543 ret); 544 return ret; 545 } 546 547 static int 548 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 549 uint16_t tpid) 550 { 551 struct hns3_adapter *hns = dev->data->dev_private; 552 struct hns3_hw *hw = &hns->hw; 553 int ret; 554 555 rte_spinlock_lock(&hw->lock); 556 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 557 rte_spinlock_unlock(&hw->lock); 558 return ret; 559 } 560 561 static int 562 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 563 struct hns3_rx_vtag_cfg *vcfg) 564 { 565 struct hns3_vport_vtag_rx_cfg_cmd *req; 566 struct hns3_hw *hw = &hns->hw; 567 struct hns3_cmd_desc desc; 568 uint16_t vport_id; 569 uint8_t bitmap; 570 int ret; 571 572 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 573 574 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 575 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 576 vcfg->strip_tag1_en ? 1 : 0); 577 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 578 vcfg->strip_tag2_en ? 1 : 0); 579 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 580 vcfg->vlan1_vlan_prionly ? 1 : 0); 581 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 582 vcfg->vlan2_vlan_prionly ? 1 : 0); 583 584 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 585 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B, 586 vcfg->strip_tag1_discard_en ? 1 : 0); 587 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B, 588 vcfg->strip_tag2_discard_en ? 1 : 0); 589 /* 590 * In current version VF is not supported when PF is driven by DPDK 591 * driver, just need to configure parameters for PF vport. 592 */ 593 vport_id = HNS3_PF_FUNC_ID; 594 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 595 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 596 req->vf_bitmap[req->vf_offset] = bitmap; 597 598 ret = hns3_cmd_send(hw, &desc, 1); 599 if (ret) 600 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 601 return ret; 602 } 603 604 static void 605 hns3_update_rx_offload_cfg(struct hns3_adapter *hns, 606 struct hns3_rx_vtag_cfg *vcfg) 607 { 608 struct hns3_pf *pf = &hns->pf; 609 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg)); 610 } 611 612 static void 613 hns3_update_tx_offload_cfg(struct hns3_adapter *hns, 614 struct hns3_tx_vtag_cfg *vcfg) 615 { 616 struct hns3_pf *pf = &hns->pf; 617 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg)); 618 } 619 620 static int 621 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 622 { 623 struct hns3_rx_vtag_cfg rxvlan_cfg; 624 struct hns3_hw *hw = &hns->hw; 625 int ret; 626 627 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 628 rxvlan_cfg.strip_tag1_en = false; 629 rxvlan_cfg.strip_tag2_en = enable; 630 rxvlan_cfg.strip_tag2_discard_en = false; 631 } else { 632 rxvlan_cfg.strip_tag1_en = enable; 633 rxvlan_cfg.strip_tag2_en = true; 634 rxvlan_cfg.strip_tag2_discard_en = true; 635 } 636 637 rxvlan_cfg.strip_tag1_discard_en = false; 638 rxvlan_cfg.vlan1_vlan_prionly = false; 639 rxvlan_cfg.vlan2_vlan_prionly = false; 640 rxvlan_cfg.rx_vlan_offload_en = enable; 641 642 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 643 if (ret) { 644 hns3_err(hw, "%s strip rx vtag failed, ret = %d.", 645 enable ? "enable" : "disable", ret); 646 return ret; 647 } 648 649 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg); 650 651 return ret; 652 } 653 654 static int 655 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 656 uint8_t fe_type, bool filter_en, uint8_t vf_id) 657 { 658 struct hns3_vlan_filter_ctrl_cmd *req; 659 struct hns3_cmd_desc desc; 660 int ret; 661 662 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 663 664 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 665 req->vlan_type = vlan_type; 666 req->vlan_fe = filter_en ? fe_type : 0; 667 req->vf_id = vf_id; 668 669 ret = hns3_cmd_send(hw, &desc, 1); 670 if (ret) 671 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 672 673 return ret; 674 } 675 676 static int 677 hns3_vlan_filter_init(struct hns3_adapter *hns) 678 { 679 struct hns3_hw *hw = &hns->hw; 680 int ret; 681 682 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 683 HNS3_FILTER_FE_EGRESS, false, 684 HNS3_PF_FUNC_ID); 685 if (ret) { 686 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 687 return ret; 688 } 689 690 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 691 HNS3_FILTER_FE_INGRESS, false, 692 HNS3_PF_FUNC_ID); 693 if (ret) 694 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 695 696 return ret; 697 } 698 699 static int 700 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 701 { 702 struct hns3_hw *hw = &hns->hw; 703 int ret; 704 705 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 706 HNS3_FILTER_FE_INGRESS, enable, 707 HNS3_PF_FUNC_ID); 708 if (ret) 709 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 710 enable ? "enable" : "disable", ret); 711 712 return ret; 713 } 714 715 static int 716 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 717 { 718 struct hns3_adapter *hns = dev->data->dev_private; 719 struct hns3_hw *hw = &hns->hw; 720 struct rte_eth_rxmode *rxmode; 721 unsigned int tmp_mask; 722 bool enable; 723 int ret = 0; 724 725 rte_spinlock_lock(&hw->lock); 726 rxmode = &dev->data->dev_conf.rxmode; 727 tmp_mask = (unsigned int)mask; 728 if (tmp_mask & ETH_VLAN_FILTER_MASK) { 729 /* ignore vlan filter configuration during promiscuous mode */ 730 if (!dev->data->promiscuous) { 731 /* Enable or disable VLAN filter */ 732 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? 733 true : false; 734 735 ret = hns3_enable_vlan_filter(hns, enable); 736 if (ret) { 737 rte_spinlock_unlock(&hw->lock); 738 hns3_err(hw, "failed to %s rx filter, ret = %d", 739 enable ? "enable" : "disable", ret); 740 return ret; 741 } 742 } 743 } 744 745 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 746 /* Enable or disable VLAN stripping */ 747 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? 748 true : false; 749 750 ret = hns3_en_hw_strip_rxvtag(hns, enable); 751 if (ret) { 752 rte_spinlock_unlock(&hw->lock); 753 hns3_err(hw, "failed to %s rx strip, ret = %d", 754 enable ? "enable" : "disable", ret); 755 return ret; 756 } 757 } 758 759 rte_spinlock_unlock(&hw->lock); 760 761 return ret; 762 } 763 764 static int 765 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 766 struct hns3_tx_vtag_cfg *vcfg) 767 { 768 struct hns3_vport_vtag_tx_cfg_cmd *req; 769 struct hns3_cmd_desc desc; 770 struct hns3_hw *hw = &hns->hw; 771 uint16_t vport_id; 772 uint8_t bitmap; 773 int ret; 774 775 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 776 777 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 778 req->def_vlan_tag1 = vcfg->default_tag1; 779 req->def_vlan_tag2 = vcfg->default_tag2; 780 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 781 vcfg->accept_tag1 ? 1 : 0); 782 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 783 vcfg->accept_untag1 ? 1 : 0); 784 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 785 vcfg->accept_tag2 ? 1 : 0); 786 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 787 vcfg->accept_untag2 ? 1 : 0); 788 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 789 vcfg->insert_tag1_en ? 1 : 0); 790 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 791 vcfg->insert_tag2_en ? 1 : 0); 792 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 793 794 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 795 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B, 796 vcfg->tag_shift_mode_en ? 1 : 0); 797 798 /* 799 * In current version VF is not supported when PF is driven by DPDK 800 * driver, just need to configure parameters for PF vport. 801 */ 802 vport_id = HNS3_PF_FUNC_ID; 803 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 804 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 805 req->vf_bitmap[req->vf_offset] = bitmap; 806 807 ret = hns3_cmd_send(hw, &desc, 1); 808 if (ret) 809 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 810 811 return ret; 812 } 813 814 static int 815 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 816 uint16_t pvid) 817 { 818 struct hns3_hw *hw = &hns->hw; 819 struct hns3_tx_vtag_cfg txvlan_cfg; 820 int ret; 821 822 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 823 txvlan_cfg.accept_tag1 = true; 824 txvlan_cfg.insert_tag1_en = false; 825 txvlan_cfg.default_tag1 = 0; 826 } else { 827 txvlan_cfg.accept_tag1 = 828 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE; 829 txvlan_cfg.insert_tag1_en = true; 830 txvlan_cfg.default_tag1 = pvid; 831 } 832 833 txvlan_cfg.accept_untag1 = true; 834 txvlan_cfg.accept_tag2 = true; 835 txvlan_cfg.accept_untag2 = true; 836 txvlan_cfg.insert_tag2_en = false; 837 txvlan_cfg.default_tag2 = 0; 838 txvlan_cfg.tag_shift_mode_en = true; 839 840 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 841 if (ret) { 842 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 843 ret); 844 return ret; 845 } 846 847 hns3_update_tx_offload_cfg(hns, &txvlan_cfg); 848 return ret; 849 } 850 851 852 static void 853 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 854 { 855 struct hns3_user_vlan_table *vlan_entry; 856 struct hns3_pf *pf = &hns->pf; 857 858 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 859 if (vlan_entry->hd_tbl_status) { 860 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 861 vlan_entry->hd_tbl_status = false; 862 } 863 } 864 865 if (is_del_list) { 866 vlan_entry = LIST_FIRST(&pf->vlan_list); 867 while (vlan_entry) { 868 LIST_REMOVE(vlan_entry, next); 869 rte_free(vlan_entry); 870 vlan_entry = LIST_FIRST(&pf->vlan_list); 871 } 872 } 873 } 874 875 static void 876 hns3_add_all_vlan_table(struct hns3_adapter *hns) 877 { 878 struct hns3_user_vlan_table *vlan_entry; 879 struct hns3_pf *pf = &hns->pf; 880 881 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 882 if (!vlan_entry->hd_tbl_status) { 883 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 884 vlan_entry->hd_tbl_status = true; 885 } 886 } 887 } 888 889 static void 890 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 891 { 892 struct hns3_hw *hw = &hns->hw; 893 int ret; 894 895 hns3_rm_all_vlan_table(hns, true); 896 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) { 897 ret = hns3_set_port_vlan_filter(hns, 898 hw->port_base_vlan_cfg.pvid, 0); 899 if (ret) { 900 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 901 ret); 902 return; 903 } 904 } 905 } 906 907 static int 908 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 909 uint16_t port_base_vlan_state, uint16_t new_pvid) 910 { 911 struct hns3_hw *hw = &hns->hw; 912 uint16_t old_pvid; 913 int ret; 914 915 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 916 old_pvid = hw->port_base_vlan_cfg.pvid; 917 if (old_pvid != HNS3_INVALID_PVID) { 918 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 919 if (ret) { 920 hns3_err(hw, "failed to remove old pvid %u, " 921 "ret = %d", old_pvid, ret); 922 return ret; 923 } 924 } 925 926 hns3_rm_all_vlan_table(hns, false); 927 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1); 928 if (ret) { 929 hns3_err(hw, "failed to add new pvid %u, ret = %d", 930 new_pvid, ret); 931 return ret; 932 } 933 } else { 934 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 935 if (ret) { 936 hns3_err(hw, "failed to remove pvid %u, ret = %d", 937 new_pvid, ret); 938 return ret; 939 } 940 941 hns3_add_all_vlan_table(hns); 942 } 943 return 0; 944 } 945 946 static int 947 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 948 { 949 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 950 struct hns3_rx_vtag_cfg rx_vlan_cfg; 951 bool rx_strip_en; 952 int ret; 953 954 rx_strip_en = old_cfg->rx_vlan_offload_en; 955 if (on) { 956 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 957 rx_vlan_cfg.strip_tag2_en = true; 958 rx_vlan_cfg.strip_tag2_discard_en = true; 959 } else { 960 rx_vlan_cfg.strip_tag1_en = false; 961 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 962 rx_vlan_cfg.strip_tag2_discard_en = false; 963 } 964 rx_vlan_cfg.strip_tag1_discard_en = false; 965 rx_vlan_cfg.vlan1_vlan_prionly = false; 966 rx_vlan_cfg.vlan2_vlan_prionly = false; 967 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 968 969 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 970 if (ret) 971 return ret; 972 973 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg); 974 return ret; 975 } 976 977 static int 978 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 979 { 980 struct hns3_hw *hw = &hns->hw; 981 uint16_t port_base_vlan_state; 982 int ret, err; 983 984 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 985 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) 986 hns3_warn(hw, "Invalid operation! As current pvid set " 987 "is %u, disable pvid %u is invalid", 988 hw->port_base_vlan_cfg.pvid, pvid); 989 return 0; 990 } 991 992 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 993 HNS3_PORT_BASE_VLAN_DISABLE; 994 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 995 if (ret) { 996 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 997 ret); 998 return ret; 999 } 1000 1001 ret = hns3_en_pvid_strip(hns, on); 1002 if (ret) { 1003 hns3_err(hw, "failed to config rx vlan strip for pvid, " 1004 "ret = %d", ret); 1005 goto pvid_vlan_strip_fail; 1006 } 1007 1008 if (pvid == HNS3_INVALID_PVID) 1009 goto out; 1010 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid); 1011 if (ret) { 1012 hns3_err(hw, "failed to update vlan filter entries, ret = %d", 1013 ret); 1014 goto vlan_filter_set_fail; 1015 } 1016 1017 out: 1018 hw->port_base_vlan_cfg.state = port_base_vlan_state; 1019 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID; 1020 return ret; 1021 1022 vlan_filter_set_fail: 1023 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state == 1024 HNS3_PORT_BASE_VLAN_ENABLE); 1025 if (err) 1026 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err); 1027 1028 pvid_vlan_strip_fail: 1029 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state, 1030 hw->port_base_vlan_cfg.pvid); 1031 if (err) 1032 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err); 1033 1034 return ret; 1035 } 1036 1037 static int 1038 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 1039 { 1040 struct hns3_adapter *hns = dev->data->dev_private; 1041 struct hns3_hw *hw = &hns->hw; 1042 bool pvid_en_state_change; 1043 uint16_t pvid_state; 1044 int ret; 1045 1046 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 1047 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 1048 RTE_ETHER_MAX_VLAN_ID); 1049 return -EINVAL; 1050 } 1051 1052 /* 1053 * If PVID configuration state change, should refresh the PVID 1054 * configuration state in struct hns3_tx_queue/hns3_rx_queue. 1055 */ 1056 pvid_state = hw->port_base_vlan_cfg.state; 1057 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || 1058 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) 1059 pvid_en_state_change = false; 1060 else 1061 pvid_en_state_change = true; 1062 1063 rte_spinlock_lock(&hw->lock); 1064 ret = hns3_vlan_pvid_configure(hns, pvid, on); 1065 rte_spinlock_unlock(&hw->lock); 1066 if (ret) 1067 return ret; 1068 /* 1069 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx 1070 * need be processed by PMD driver. 1071 */ 1072 if (pvid_en_state_change && 1073 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 1074 hns3_update_all_queues_pvid_proc_en(hw); 1075 1076 return 0; 1077 } 1078 1079 static int 1080 hns3_default_vlan_config(struct hns3_adapter *hns) 1081 { 1082 struct hns3_hw *hw = &hns->hw; 1083 int ret; 1084 1085 /* 1086 * When vlan filter is enabled, hardware regards packets without vlan 1087 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan 1088 * table, packets without vlan won't be received. So, add vlan 0 as 1089 * the default vlan. 1090 */ 1091 ret = hns3_vlan_filter_configure(hns, 0, 1); 1092 if (ret) 1093 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 1094 return ret; 1095 } 1096 1097 static int 1098 hns3_init_vlan_config(struct hns3_adapter *hns) 1099 { 1100 struct hns3_hw *hw = &hns->hw; 1101 int ret; 1102 1103 /* 1104 * This function can be called in the initialization and reset process, 1105 * when in reset process, it means that hardware had been reseted 1106 * successfully and we need to restore the hardware configuration to 1107 * ensure that the hardware configuration remains unchanged before and 1108 * after reset. 1109 */ 1110 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1111 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 1112 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID; 1113 } 1114 1115 ret = hns3_vlan_filter_init(hns); 1116 if (ret) { 1117 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 1118 return ret; 1119 } 1120 1121 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER, 1122 RTE_ETHER_TYPE_VLAN); 1123 if (ret) { 1124 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 1125 return ret; 1126 } 1127 1128 /* 1129 * When in the reinit dev stage of the reset process, the following 1130 * vlan-related configurations may differ from those at initialization, 1131 * we will restore configurations to hardware in hns3_restore_vlan_table 1132 * and hns3_restore_vlan_conf later. 1133 */ 1134 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1135 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0); 1136 if (ret) { 1137 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 1138 return ret; 1139 } 1140 1141 ret = hns3_en_hw_strip_rxvtag(hns, false); 1142 if (ret) { 1143 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 1144 ret); 1145 return ret; 1146 } 1147 } 1148 1149 return hns3_default_vlan_config(hns); 1150 } 1151 1152 static int 1153 hns3_restore_vlan_conf(struct hns3_adapter *hns) 1154 { 1155 struct hns3_pf *pf = &hns->pf; 1156 struct hns3_hw *hw = &hns->hw; 1157 uint64_t offloads; 1158 bool enable; 1159 int ret; 1160 1161 if (!hw->data->promiscuous) { 1162 /* restore vlan filter states */ 1163 offloads = hw->data->dev_conf.rxmode.offloads; 1164 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false; 1165 ret = hns3_enable_vlan_filter(hns, enable); 1166 if (ret) { 1167 hns3_err(hw, "failed to restore vlan rx filter conf, " 1168 "ret = %d", ret); 1169 return ret; 1170 } 1171 } 1172 1173 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1174 if (ret) { 1175 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1176 return ret; 1177 } 1178 1179 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1180 if (ret) 1181 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1182 1183 return ret; 1184 } 1185 1186 static int 1187 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1188 { 1189 struct hns3_adapter *hns = dev->data->dev_private; 1190 struct rte_eth_dev_data *data = dev->data; 1191 struct rte_eth_txmode *txmode; 1192 struct hns3_hw *hw = &hns->hw; 1193 int mask; 1194 int ret; 1195 1196 txmode = &data->dev_conf.txmode; 1197 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1198 hns3_warn(hw, 1199 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1200 "configuration is not supported! Ignore these two " 1201 "parameters: hw_vlan_reject_tagged(%u), " 1202 "hw_vlan_reject_untagged(%u)", 1203 txmode->hw_vlan_reject_tagged, 1204 txmode->hw_vlan_reject_untagged); 1205 1206 /* Apply vlan offload setting */ 1207 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK; 1208 ret = hns3_vlan_offload_set(dev, mask); 1209 if (ret) { 1210 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1211 ret); 1212 return ret; 1213 } 1214 1215 /* 1216 * If pvid config is not set in rte_eth_conf, driver needn't to set 1217 * VLAN pvid related configuration to hardware. 1218 */ 1219 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1220 return 0; 1221 1222 /* Apply pvid setting */ 1223 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1224 txmode->hw_vlan_insert_pvid); 1225 if (ret) 1226 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d", 1227 txmode->pvid, ret); 1228 1229 return ret; 1230 } 1231 1232 static int 1233 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1234 unsigned int tso_mss_max) 1235 { 1236 struct hns3_cfg_tso_status_cmd *req; 1237 struct hns3_cmd_desc desc; 1238 uint16_t tso_mss; 1239 1240 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1241 1242 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1243 1244 tso_mss = 0; 1245 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1246 tso_mss_min); 1247 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1248 1249 tso_mss = 0; 1250 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1251 tso_mss_max); 1252 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1253 1254 return hns3_cmd_send(hw, &desc, 1); 1255 } 1256 1257 static int 1258 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1259 uint16_t *allocated_size, bool is_alloc) 1260 { 1261 struct hns3_umv_spc_alc_cmd *req; 1262 struct hns3_cmd_desc desc; 1263 int ret; 1264 1265 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1266 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1267 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1268 req->space_size = rte_cpu_to_le_32(space_size); 1269 1270 ret = hns3_cmd_send(hw, &desc, 1); 1271 if (ret) { 1272 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1273 is_alloc ? "allocate" : "free", ret); 1274 return ret; 1275 } 1276 1277 if (is_alloc && allocated_size) 1278 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1279 1280 return 0; 1281 } 1282 1283 static int 1284 hns3_init_umv_space(struct hns3_hw *hw) 1285 { 1286 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1287 struct hns3_pf *pf = &hns->pf; 1288 uint16_t allocated_size = 0; 1289 int ret; 1290 1291 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1292 true); 1293 if (ret) 1294 return ret; 1295 1296 if (allocated_size < pf->wanted_umv_size) 1297 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1298 pf->wanted_umv_size, allocated_size); 1299 1300 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1301 pf->wanted_umv_size; 1302 pf->used_umv_size = 0; 1303 return 0; 1304 } 1305 1306 static int 1307 hns3_uninit_umv_space(struct hns3_hw *hw) 1308 { 1309 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1310 struct hns3_pf *pf = &hns->pf; 1311 int ret; 1312 1313 if (pf->max_umv_size == 0) 1314 return 0; 1315 1316 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1317 if (ret) 1318 return ret; 1319 1320 pf->max_umv_size = 0; 1321 1322 return 0; 1323 } 1324 1325 static bool 1326 hns3_is_umv_space_full(struct hns3_hw *hw) 1327 { 1328 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1329 struct hns3_pf *pf = &hns->pf; 1330 bool is_full; 1331 1332 is_full = (pf->used_umv_size >= pf->max_umv_size); 1333 1334 return is_full; 1335 } 1336 1337 static void 1338 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1339 { 1340 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1341 struct hns3_pf *pf = &hns->pf; 1342 1343 if (is_free) { 1344 if (pf->used_umv_size > 0) 1345 pf->used_umv_size--; 1346 } else 1347 pf->used_umv_size++; 1348 } 1349 1350 static void 1351 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1352 const uint8_t *addr, bool is_mc) 1353 { 1354 const unsigned char *mac_addr = addr; 1355 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1356 ((uint32_t)mac_addr[2] << 16) | 1357 ((uint32_t)mac_addr[1] << 8) | 1358 (uint32_t)mac_addr[0]; 1359 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1360 1361 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1362 if (is_mc) { 1363 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1364 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1365 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1366 } 1367 1368 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1369 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1370 } 1371 1372 static int 1373 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1374 uint8_t resp_code, 1375 enum hns3_mac_vlan_tbl_opcode op) 1376 { 1377 if (cmdq_resp) { 1378 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1379 cmdq_resp); 1380 return -EIO; 1381 } 1382 1383 if (op == HNS3_MAC_VLAN_ADD) { 1384 if (resp_code == 0 || resp_code == 1) { 1385 return 0; 1386 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1387 hns3_err(hw, "add mac addr failed for uc_overflow"); 1388 return -ENOSPC; 1389 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1390 hns3_err(hw, "add mac addr failed for mc_overflow"); 1391 return -ENOSPC; 1392 } 1393 1394 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1395 resp_code); 1396 return -EIO; 1397 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1398 if (resp_code == 0) { 1399 return 0; 1400 } else if (resp_code == 1) { 1401 hns3_dbg(hw, "remove mac addr failed for miss"); 1402 return -ENOENT; 1403 } 1404 1405 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1406 resp_code); 1407 return -EIO; 1408 } else if (op == HNS3_MAC_VLAN_LKUP) { 1409 if (resp_code == 0) { 1410 return 0; 1411 } else if (resp_code == 1) { 1412 hns3_dbg(hw, "lookup mac addr failed for miss"); 1413 return -ENOENT; 1414 } 1415 1416 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1417 resp_code); 1418 return -EIO; 1419 } 1420 1421 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1422 op); 1423 1424 return -EINVAL; 1425 } 1426 1427 static int 1428 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1429 struct hns3_mac_vlan_tbl_entry_cmd *req, 1430 struct hns3_cmd_desc *desc, uint8_t desc_num) 1431 { 1432 uint8_t resp_code; 1433 uint16_t retval; 1434 int ret; 1435 int i; 1436 1437 if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) { 1438 for (i = 0; i < desc_num - 1; i++) { 1439 hns3_cmd_setup_basic_desc(&desc[i], 1440 HNS3_OPC_MAC_VLAN_ADD, true); 1441 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1442 if (i == 0) 1443 memcpy(desc[i].data, req, 1444 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1445 } 1446 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD, 1447 true); 1448 } else { 1449 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, 1450 true); 1451 memcpy(desc[0].data, req, 1452 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1453 } 1454 ret = hns3_cmd_send(hw, desc, desc_num); 1455 if (ret) { 1456 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1457 ret); 1458 return ret; 1459 } 1460 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1461 retval = rte_le_to_cpu_16(desc[0].retval); 1462 1463 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1464 HNS3_MAC_VLAN_LKUP); 1465 } 1466 1467 static int 1468 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1469 struct hns3_mac_vlan_tbl_entry_cmd *req, 1470 struct hns3_cmd_desc *desc, uint8_t desc_num) 1471 { 1472 uint8_t resp_code; 1473 uint16_t retval; 1474 int cfg_status; 1475 int ret; 1476 int i; 1477 1478 if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) { 1479 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false); 1480 memcpy(desc->data, req, 1481 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1482 ret = hns3_cmd_send(hw, desc, desc_num); 1483 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff; 1484 retval = rte_le_to_cpu_16(desc->retval); 1485 1486 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1487 HNS3_MAC_VLAN_ADD); 1488 } else { 1489 for (i = 0; i < desc_num; i++) { 1490 hns3_cmd_reuse_desc(&desc[i], false); 1491 if (i == desc_num - 1) 1492 desc[i].flag &= 1493 rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1494 else 1495 desc[i].flag |= 1496 rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1497 } 1498 memcpy(desc[0].data, req, 1499 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1500 desc[0].retval = 0; 1501 ret = hns3_cmd_send(hw, desc, desc_num); 1502 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1503 retval = rte_le_to_cpu_16(desc[0].retval); 1504 1505 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1506 HNS3_MAC_VLAN_ADD); 1507 } 1508 1509 if (ret) { 1510 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1511 return ret; 1512 } 1513 1514 return cfg_status; 1515 } 1516 1517 static int 1518 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1519 struct hns3_mac_vlan_tbl_entry_cmd *req) 1520 { 1521 struct hns3_cmd_desc desc; 1522 uint8_t resp_code; 1523 uint16_t retval; 1524 int ret; 1525 1526 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1527 1528 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1529 1530 ret = hns3_cmd_send(hw, &desc, 1); 1531 if (ret) { 1532 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1533 return ret; 1534 } 1535 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1536 retval = rte_le_to_cpu_16(desc.retval); 1537 1538 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1539 HNS3_MAC_VLAN_REMOVE); 1540 } 1541 1542 static int 1543 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1544 { 1545 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1546 struct hns3_mac_vlan_tbl_entry_cmd req; 1547 struct hns3_pf *pf = &hns->pf; 1548 struct hns3_cmd_desc desc; 1549 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1550 uint16_t egress_port = 0; 1551 uint8_t vf_id; 1552 int ret; 1553 1554 /* check if mac addr is valid */ 1555 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1556 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1557 mac_addr); 1558 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1559 mac_str); 1560 return -EINVAL; 1561 } 1562 1563 memset(&req, 0, sizeof(req)); 1564 1565 /* 1566 * In current version VF is not supported when PF is driven by DPDK 1567 * driver, just need to configure parameters for PF vport. 1568 */ 1569 vf_id = HNS3_PF_FUNC_ID; 1570 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1571 HNS3_MAC_EPORT_VFID_S, vf_id); 1572 1573 req.egress_port = rte_cpu_to_le_16(egress_port); 1574 1575 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1576 1577 /* 1578 * Lookup the mac address in the mac_vlan table, and add 1579 * it if the entry is inexistent. Repeated unicast entry 1580 * is not allowed in the mac vlan table. 1581 */ 1582 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, 1583 HNS3_UC_MAC_VLAN_OPS_DESC_NUM); 1584 if (ret == -ENOENT) { 1585 if (!hns3_is_umv_space_full(hw)) { 1586 ret = hns3_add_mac_vlan_tbl(hw, &req, &desc, 1587 HNS3_UC_MAC_VLAN_OPS_DESC_NUM); 1588 if (!ret) 1589 hns3_update_umv_space(hw, false); 1590 return ret; 1591 } 1592 1593 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1594 1595 return -ENOSPC; 1596 } 1597 1598 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1599 1600 /* check if we just hit the duplicate */ 1601 if (ret == 0) { 1602 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1603 return 0; 1604 } 1605 1606 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1607 mac_str); 1608 1609 return ret; 1610 } 1611 1612 static int 1613 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1614 { 1615 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1616 struct rte_ether_addr *addr; 1617 int ret; 1618 int i; 1619 1620 for (i = 0; i < hw->mc_addrs_num; i++) { 1621 addr = &hw->mc_addrs[i]; 1622 /* Check if there are duplicate addresses */ 1623 if (rte_is_same_ether_addr(addr, mac_addr)) { 1624 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1625 addr); 1626 hns3_err(hw, "failed to add mc mac addr, same addrs" 1627 "(%s) is added by the set_mc_mac_addr_list " 1628 "API", mac_str); 1629 return -EINVAL; 1630 } 1631 } 1632 1633 ret = hns3_add_mc_addr(hw, mac_addr); 1634 if (ret) { 1635 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1636 mac_addr); 1637 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 1638 mac_str, ret); 1639 } 1640 return ret; 1641 } 1642 1643 static int 1644 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1645 { 1646 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1647 int ret; 1648 1649 ret = hns3_remove_mc_addr(hw, mac_addr); 1650 if (ret) { 1651 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1652 mac_addr); 1653 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d", 1654 mac_str, ret); 1655 } 1656 return ret; 1657 } 1658 1659 static int 1660 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1661 __rte_unused uint32_t idx, __rte_unused uint32_t pool) 1662 { 1663 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1664 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1665 int ret; 1666 1667 rte_spinlock_lock(&hw->lock); 1668 1669 /* 1670 * In hns3 network engine adding UC and MC mac address with different 1671 * commands with firmware. We need to determine whether the input 1672 * address is a UC or a MC address to call different commands. 1673 * By the way, it is recommended calling the API function named 1674 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 1675 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 1676 * may affect the specifications of UC mac addresses. 1677 */ 1678 if (rte_is_multicast_ether_addr(mac_addr)) 1679 ret = hns3_add_mc_addr_common(hw, mac_addr); 1680 else 1681 ret = hns3_add_uc_addr_common(hw, mac_addr); 1682 1683 if (ret) { 1684 rte_spinlock_unlock(&hw->lock); 1685 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1686 mac_addr); 1687 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 1688 ret); 1689 return ret; 1690 } 1691 1692 rte_spinlock_unlock(&hw->lock); 1693 1694 return ret; 1695 } 1696 1697 static int 1698 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1699 { 1700 struct hns3_mac_vlan_tbl_entry_cmd req; 1701 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1702 int ret; 1703 1704 /* check if mac addr is valid */ 1705 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1706 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1707 mac_addr); 1708 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1709 mac_str); 1710 return -EINVAL; 1711 } 1712 1713 memset(&req, 0, sizeof(req)); 1714 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1715 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1716 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1717 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1718 return 0; 1719 else if (ret == 0) 1720 hns3_update_umv_space(hw, true); 1721 1722 return ret; 1723 } 1724 1725 static void 1726 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 1727 { 1728 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1729 /* index will be checked by upper level rte interface */ 1730 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 1731 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1732 int ret; 1733 1734 rte_spinlock_lock(&hw->lock); 1735 1736 if (rte_is_multicast_ether_addr(mac_addr)) 1737 ret = hns3_remove_mc_addr_common(hw, mac_addr); 1738 else 1739 ret = hns3_remove_uc_addr_common(hw, mac_addr); 1740 rte_spinlock_unlock(&hw->lock); 1741 if (ret) { 1742 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1743 mac_addr); 1744 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, 1745 ret); 1746 } 1747 } 1748 1749 static int 1750 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1751 struct rte_ether_addr *mac_addr) 1752 { 1753 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1754 struct rte_ether_addr *oaddr; 1755 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1756 int ret, ret_val; 1757 1758 rte_spinlock_lock(&hw->lock); 1759 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1760 ret = hns3_remove_uc_addr_common(hw, oaddr); 1761 if (ret) { 1762 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1763 oaddr); 1764 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1765 mac_str, ret); 1766 1767 rte_spinlock_unlock(&hw->lock); 1768 return ret; 1769 } 1770 1771 ret = hns3_add_uc_addr_common(hw, mac_addr); 1772 if (ret) { 1773 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1774 mac_addr); 1775 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1776 goto err_add_uc_addr; 1777 } 1778 1779 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1780 if (ret) { 1781 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1782 goto err_pause_addr_cfg; 1783 } 1784 1785 rte_ether_addr_copy(mac_addr, 1786 (struct rte_ether_addr *)hw->mac.mac_addr); 1787 rte_spinlock_unlock(&hw->lock); 1788 1789 return 0; 1790 1791 err_pause_addr_cfg: 1792 ret_val = hns3_remove_uc_addr_common(hw, mac_addr); 1793 if (ret_val) { 1794 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1795 mac_addr); 1796 hns3_warn(hw, 1797 "Failed to roll back to del setted mac addr(%s): %d", 1798 mac_str, ret_val); 1799 } 1800 1801 err_add_uc_addr: 1802 ret_val = hns3_add_uc_addr_common(hw, oaddr); 1803 if (ret_val) { 1804 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr); 1805 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d", 1806 mac_str, ret_val); 1807 } 1808 rte_spinlock_unlock(&hw->lock); 1809 1810 return ret; 1811 } 1812 1813 static int 1814 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) 1815 { 1816 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1817 struct hns3_hw *hw = &hns->hw; 1818 struct rte_ether_addr *addr; 1819 int err = 0; 1820 int ret; 1821 int i; 1822 1823 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) { 1824 addr = &hw->data->mac_addrs[i]; 1825 if (rte_is_zero_ether_addr(addr)) 1826 continue; 1827 if (rte_is_multicast_ether_addr(addr)) 1828 ret = del ? hns3_remove_mc_addr(hw, addr) : 1829 hns3_add_mc_addr(hw, addr); 1830 else 1831 ret = del ? hns3_remove_uc_addr_common(hw, addr) : 1832 hns3_add_uc_addr_common(hw, addr); 1833 1834 if (ret) { 1835 err = ret; 1836 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1837 addr); 1838 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 1839 "ret = %d.", del ? "remove" : "restore", 1840 mac_str, i, ret); 1841 } 1842 } 1843 return err; 1844 } 1845 1846 static void 1847 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1848 { 1849 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1850 uint8_t word_num; 1851 uint8_t bit_num; 1852 1853 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1854 word_num = vfid / 32; 1855 bit_num = vfid % 32; 1856 if (clr) 1857 desc[1].data[word_num] &= 1858 rte_cpu_to_le_32(~(1UL << bit_num)); 1859 else 1860 desc[1].data[word_num] |= 1861 rte_cpu_to_le_32(1UL << bit_num); 1862 } else { 1863 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1864 bit_num = vfid % 32; 1865 if (clr) 1866 desc[2].data[word_num] &= 1867 rte_cpu_to_le_32(~(1UL << bit_num)); 1868 else 1869 desc[2].data[word_num] |= 1870 rte_cpu_to_le_32(1UL << bit_num); 1871 } 1872 } 1873 1874 static int 1875 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1876 { 1877 struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM]; 1878 struct hns3_mac_vlan_tbl_entry_cmd req; 1879 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1880 uint8_t vf_id; 1881 int ret; 1882 1883 /* Check if mac addr is valid */ 1884 if (!rte_is_multicast_ether_addr(mac_addr)) { 1885 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1886 mac_addr); 1887 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1888 mac_str); 1889 return -EINVAL; 1890 } 1891 1892 memset(&req, 0, sizeof(req)); 1893 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1894 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1895 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, 1896 HNS3_MC_MAC_VLAN_OPS_DESC_NUM); 1897 if (ret) { 1898 /* This mac addr do not exist, add new entry for it */ 1899 memset(desc[0].data, 0, sizeof(desc[0].data)); 1900 memset(desc[1].data, 0, sizeof(desc[0].data)); 1901 memset(desc[2].data, 0, sizeof(desc[0].data)); 1902 } 1903 1904 /* 1905 * In current version VF is not supported when PF is driven by DPDK 1906 * driver, just need to configure parameters for PF vport. 1907 */ 1908 vf_id = HNS3_PF_FUNC_ID; 1909 hns3_update_desc_vfid(desc, vf_id, false); 1910 ret = hns3_add_mac_vlan_tbl(hw, &req, desc, 1911 HNS3_MC_MAC_VLAN_OPS_DESC_NUM); 1912 if (ret) { 1913 if (ret == -ENOSPC) 1914 hns3_err(hw, "mc mac vlan table is full"); 1915 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1916 mac_addr); 1917 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1918 } 1919 1920 return ret; 1921 } 1922 1923 static int 1924 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1925 { 1926 struct hns3_mac_vlan_tbl_entry_cmd req; 1927 struct hns3_cmd_desc desc[3]; 1928 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1929 uint8_t vf_id; 1930 int ret; 1931 1932 /* Check if mac addr is valid */ 1933 if (!rte_is_multicast_ether_addr(mac_addr)) { 1934 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1935 mac_addr); 1936 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1937 mac_str); 1938 return -EINVAL; 1939 } 1940 1941 memset(&req, 0, sizeof(req)); 1942 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1943 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1944 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, 1945 HNS3_MC_MAC_VLAN_OPS_DESC_NUM); 1946 if (ret == 0) { 1947 /* 1948 * This mac addr exist, remove this handle's VFID for it. 1949 * In current version VF is not supported when PF is driven by 1950 * DPDK driver, just need to configure parameters for PF vport. 1951 */ 1952 vf_id = HNS3_PF_FUNC_ID; 1953 hns3_update_desc_vfid(desc, vf_id, true); 1954 1955 /* All the vfid is zero, so need to delete this entry */ 1956 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1957 } else if (ret == -ENOENT) { 1958 /* This mac addr doesn't exist. */ 1959 return 0; 1960 } 1961 1962 if (ret) { 1963 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1964 mac_addr); 1965 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1966 } 1967 1968 return ret; 1969 } 1970 1971 static int 1972 hns3_set_mc_addr_chk_param(struct hns3_hw *hw, 1973 struct rte_ether_addr *mc_addr_set, 1974 uint32_t nb_mc_addr) 1975 { 1976 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1977 struct rte_ether_addr *addr; 1978 uint32_t i; 1979 uint32_t j; 1980 1981 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 1982 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " 1983 "invalid. valid range: 0~%d", 1984 nb_mc_addr, HNS3_MC_MACADDR_NUM); 1985 return -EINVAL; 1986 } 1987 1988 /* Check if input mac addresses are valid */ 1989 for (i = 0; i < nb_mc_addr; i++) { 1990 addr = &mc_addr_set[i]; 1991 if (!rte_is_multicast_ether_addr(addr)) { 1992 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1993 addr); 1994 hns3_err(hw, 1995 "failed to set mc mac addr, addr(%s) invalid.", 1996 mac_str); 1997 return -EINVAL; 1998 } 1999 2000 /* Check if there are duplicate addresses */ 2001 for (j = i + 1; j < nb_mc_addr; j++) { 2002 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 2003 hns3_ether_format_addr(mac_str, 2004 RTE_ETHER_ADDR_FMT_SIZE, 2005 addr); 2006 hns3_err(hw, "failed to set mc mac addr, " 2007 "addrs invalid. two same addrs(%s).", 2008 mac_str); 2009 return -EINVAL; 2010 } 2011 } 2012 2013 /* 2014 * Check if there are duplicate addresses between mac_addrs 2015 * and mc_addr_set 2016 */ 2017 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) { 2018 if (rte_is_same_ether_addr(addr, 2019 &hw->data->mac_addrs[j])) { 2020 hns3_ether_format_addr(mac_str, 2021 RTE_ETHER_ADDR_FMT_SIZE, 2022 addr); 2023 hns3_err(hw, "failed to set mc mac addr, " 2024 "addrs invalid. addrs(%s) has already " 2025 "configured in mac_addr add API", 2026 mac_str); 2027 return -EINVAL; 2028 } 2029 } 2030 } 2031 2032 return 0; 2033 } 2034 2035 static void 2036 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw, 2037 struct rte_ether_addr *mc_addr_set, 2038 int mc_addr_num, 2039 struct rte_ether_addr *reserved_addr_list, 2040 int *reserved_addr_num, 2041 struct rte_ether_addr *add_addr_list, 2042 int *add_addr_num, 2043 struct rte_ether_addr *rm_addr_list, 2044 int *rm_addr_num) 2045 { 2046 struct rte_ether_addr *addr; 2047 int current_addr_num; 2048 int reserved_num = 0; 2049 int add_num = 0; 2050 int rm_num = 0; 2051 int num; 2052 int i; 2053 int j; 2054 bool same_addr; 2055 2056 /* Calculate the mc mac address list that should be removed */ 2057 current_addr_num = hw->mc_addrs_num; 2058 for (i = 0; i < current_addr_num; i++) { 2059 addr = &hw->mc_addrs[i]; 2060 same_addr = false; 2061 for (j = 0; j < mc_addr_num; j++) { 2062 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 2063 same_addr = true; 2064 break; 2065 } 2066 } 2067 2068 if (!same_addr) { 2069 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]); 2070 rm_num++; 2071 } else { 2072 rte_ether_addr_copy(addr, 2073 &reserved_addr_list[reserved_num]); 2074 reserved_num++; 2075 } 2076 } 2077 2078 /* Calculate the mc mac address list that should be added */ 2079 for (i = 0; i < mc_addr_num; i++) { 2080 addr = &mc_addr_set[i]; 2081 same_addr = false; 2082 for (j = 0; j < current_addr_num; j++) { 2083 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) { 2084 same_addr = true; 2085 break; 2086 } 2087 } 2088 2089 if (!same_addr) { 2090 rte_ether_addr_copy(addr, &add_addr_list[add_num]); 2091 add_num++; 2092 } 2093 } 2094 2095 /* Reorder the mc mac address list maintained by driver */ 2096 for (i = 0; i < reserved_num; i++) 2097 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]); 2098 2099 for (i = 0; i < rm_num; i++) { 2100 num = reserved_num + i; 2101 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]); 2102 } 2103 2104 *reserved_addr_num = reserved_num; 2105 *add_addr_num = add_num; 2106 *rm_addr_num = rm_num; 2107 } 2108 2109 static int 2110 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, 2111 struct rte_ether_addr *mc_addr_set, 2112 uint32_t nb_mc_addr) 2113 { 2114 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2115 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM]; 2116 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM]; 2117 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM]; 2118 struct rte_ether_addr *addr; 2119 int reserved_addr_num; 2120 int add_addr_num; 2121 int rm_addr_num; 2122 int mc_addr_num; 2123 int num; 2124 int ret; 2125 int i; 2126 2127 /* Check if input parameters are valid */ 2128 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 2129 if (ret) 2130 return ret; 2131 2132 rte_spinlock_lock(&hw->lock); 2133 2134 /* 2135 * Calculate the mc mac address lists those should be removed and be 2136 * added, Reorder the mc mac address list maintained by driver. 2137 */ 2138 mc_addr_num = (int)nb_mc_addr; 2139 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num, 2140 reserved_addr_list, &reserved_addr_num, 2141 add_addr_list, &add_addr_num, 2142 rm_addr_list, &rm_addr_num); 2143 2144 /* Remove mc mac addresses */ 2145 for (i = 0; i < rm_addr_num; i++) { 2146 num = rm_addr_num - i - 1; 2147 addr = &rm_addr_list[num]; 2148 ret = hns3_remove_mc_addr(hw, addr); 2149 if (ret) { 2150 rte_spinlock_unlock(&hw->lock); 2151 return ret; 2152 } 2153 hw->mc_addrs_num--; 2154 } 2155 2156 /* Add mc mac addresses */ 2157 for (i = 0; i < add_addr_num; i++) { 2158 addr = &add_addr_list[i]; 2159 ret = hns3_add_mc_addr(hw, addr); 2160 if (ret) { 2161 rte_spinlock_unlock(&hw->lock); 2162 return ret; 2163 } 2164 2165 num = reserved_addr_num + i; 2166 rte_ether_addr_copy(addr, &hw->mc_addrs[num]); 2167 hw->mc_addrs_num++; 2168 } 2169 rte_spinlock_unlock(&hw->lock); 2170 2171 return 0; 2172 } 2173 2174 static int 2175 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 2176 { 2177 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2178 struct hns3_hw *hw = &hns->hw; 2179 struct rte_ether_addr *addr; 2180 int err = 0; 2181 int ret; 2182 int i; 2183 2184 for (i = 0; i < hw->mc_addrs_num; i++) { 2185 addr = &hw->mc_addrs[i]; 2186 if (!rte_is_multicast_ether_addr(addr)) 2187 continue; 2188 if (del) 2189 ret = hns3_remove_mc_addr(hw, addr); 2190 else 2191 ret = hns3_add_mc_addr(hw, addr); 2192 if (ret) { 2193 err = ret; 2194 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2195 addr); 2196 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d", 2197 del ? "Remove" : "Restore", mac_str, ret); 2198 } 2199 } 2200 return err; 2201 } 2202 2203 static int 2204 hns3_check_mq_mode(struct rte_eth_dev *dev) 2205 { 2206 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 2207 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 2208 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2209 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2210 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 2211 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 2212 uint8_t num_tc; 2213 int max_tc = 0; 2214 int i; 2215 2216 if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) || 2217 (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB || 2218 tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) { 2219 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.", 2220 rx_mq_mode, tx_mq_mode); 2221 return -EOPNOTSUPP; 2222 } 2223 2224 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 2225 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 2226 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) { 2227 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 2228 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 2229 dcb_rx_conf->nb_tcs, pf->tc_max); 2230 return -EINVAL; 2231 } 2232 2233 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 2234 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 2235 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, " 2236 "nb_tcs(%d) != %d or %d in rx direction.", 2237 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 2238 return -EINVAL; 2239 } 2240 2241 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 2242 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 2243 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 2244 return -EINVAL; 2245 } 2246 2247 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 2248 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 2249 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, " 2250 "is not equal to one in tx direction.", 2251 i, dcb_rx_conf->dcb_tc[i]); 2252 return -EINVAL; 2253 } 2254 if (dcb_rx_conf->dcb_tc[i] > max_tc) 2255 max_tc = dcb_rx_conf->dcb_tc[i]; 2256 } 2257 2258 num_tc = max_tc + 1; 2259 if (num_tc > dcb_rx_conf->nb_tcs) { 2260 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 2261 num_tc, dcb_rx_conf->nb_tcs); 2262 return -EINVAL; 2263 } 2264 } 2265 2266 return 0; 2267 } 2268 2269 static int 2270 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en, 2271 enum hns3_ring_type queue_type, uint16_t queue_id) 2272 { 2273 struct hns3_cmd_desc desc; 2274 struct hns3_ctrl_vector_chain_cmd *req = 2275 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 2276 enum hns3_opcode_type op; 2277 uint16_t tqp_type_and_id = 0; 2278 uint16_t type; 2279 uint16_t gl; 2280 int ret; 2281 2282 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 2283 hns3_cmd_setup_basic_desc(&desc, op, false); 2284 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M, 2285 HNS3_TQP_INT_ID_L_S); 2286 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M, 2287 HNS3_TQP_INT_ID_H_S); 2288 2289 if (queue_type == HNS3_RING_TYPE_RX) 2290 gl = HNS3_RING_GL_RX; 2291 else 2292 gl = HNS3_RING_GL_TX; 2293 2294 type = queue_type; 2295 2296 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 2297 type); 2298 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 2299 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 2300 gl); 2301 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 2302 req->int_cause_num = 1; 2303 ret = hns3_cmd_send(hw, &desc, 1); 2304 if (ret) { 2305 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.", 2306 en ? "Map" : "Unmap", queue_id, vector_id, ret); 2307 return ret; 2308 } 2309 2310 return 0; 2311 } 2312 2313 static int 2314 hns3_init_ring_with_vector(struct hns3_hw *hw) 2315 { 2316 uint16_t vec; 2317 int ret; 2318 int i; 2319 2320 /* 2321 * In hns3 network engine, vector 0 is always the misc interrupt of this 2322 * function, vector 1~N can be used respectively for the queues of the 2323 * function. Tx and Rx queues with the same number share the interrupt 2324 * vector. In the initialization clearing the all hardware mapping 2325 * relationship configurations between queues and interrupt vectors is 2326 * needed, so some error caused by the residual configurations, such as 2327 * the unexpected Tx interrupt, can be avoid. 2328 */ 2329 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 2330 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 2331 vec = vec - 1; /* the last interrupt is reserved */ 2332 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 2333 for (i = 0; i < hw->intr_tqps_num; i++) { 2334 /* 2335 * Set gap limiter/rate limiter/quanity limiter algorithm 2336 * configuration for interrupt coalesce of queue's interrupt. 2337 */ 2338 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 2339 HNS3_TQP_INTR_GL_DEFAULT); 2340 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 2341 HNS3_TQP_INTR_GL_DEFAULT); 2342 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 2343 /* 2344 * QL(quantity limiter) is not used currently, just set 0 to 2345 * close it. 2346 */ 2347 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 2348 2349 ret = hns3_bind_ring_with_vector(hw, vec, false, 2350 HNS3_RING_TYPE_TX, i); 2351 if (ret) { 2352 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with " 2353 "vector: %u, ret=%d", i, vec, ret); 2354 return ret; 2355 } 2356 2357 ret = hns3_bind_ring_with_vector(hw, vec, false, 2358 HNS3_RING_TYPE_RX, i); 2359 if (ret) { 2360 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with " 2361 "vector: %u, ret=%d", i, vec, ret); 2362 return ret; 2363 } 2364 } 2365 2366 return 0; 2367 } 2368 2369 static int 2370 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf) 2371 { 2372 struct hns3_adapter *hns = dev->data->dev_private; 2373 struct hns3_hw *hw = &hns->hw; 2374 uint32_t max_rx_pkt_len; 2375 uint16_t mtu; 2376 int ret; 2377 2378 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)) 2379 return 0; 2380 2381 /* 2382 * If jumbo frames are enabled, MTU needs to be refreshed 2383 * according to the maximum RX packet length. 2384 */ 2385 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len; 2386 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN || 2387 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) { 2388 hns3_err(hw, "maximum Rx packet length must be greater than %u " 2389 "and no more than %u when jumbo frame enabled.", 2390 (uint16_t)HNS3_DEFAULT_FRAME_LEN, 2391 (uint16_t)HNS3_MAX_FRAME_LEN); 2392 return -EINVAL; 2393 } 2394 2395 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len); 2396 ret = hns3_dev_mtu_set(dev, mtu); 2397 if (ret) 2398 return ret; 2399 dev->data->mtu = mtu; 2400 2401 return 0; 2402 } 2403 2404 static int 2405 hns3_setup_dcb(struct rte_eth_dev *dev) 2406 { 2407 struct hns3_adapter *hns = dev->data->dev_private; 2408 struct hns3_hw *hw = &hns->hw; 2409 int ret; 2410 2411 if (!hns3_dev_get_support(hw, DCB)) { 2412 hns3_err(hw, "this port does not support dcb configurations."); 2413 return -EOPNOTSUPP; 2414 } 2415 2416 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 2417 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 2418 return -EOPNOTSUPP; 2419 } 2420 2421 ret = hns3_dcb_configure(hns); 2422 if (ret) 2423 hns3_err(hw, "failed to config dcb: %d", ret); 2424 2425 return ret; 2426 } 2427 2428 static int 2429 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds) 2430 { 2431 int ret; 2432 2433 /* 2434 * Some hardware doesn't support auto-negotiation, but users may not 2435 * configure link_speeds (default 0), which means auto-negotiation. 2436 * In this case, it should return success. 2437 */ 2438 if (link_speeds == ETH_LINK_SPEED_AUTONEG && 2439 hw->mac.support_autoneg == 0) 2440 return 0; 2441 2442 if (link_speeds != ETH_LINK_SPEED_AUTONEG) { 2443 ret = hns3_check_port_speed(hw, link_speeds); 2444 if (ret) 2445 return ret; 2446 } 2447 2448 return 0; 2449 } 2450 2451 static int 2452 hns3_check_dev_conf(struct rte_eth_dev *dev) 2453 { 2454 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2455 struct rte_eth_conf *conf = &dev->data->dev_conf; 2456 int ret; 2457 2458 ret = hns3_check_mq_mode(dev); 2459 if (ret) 2460 return ret; 2461 2462 return hns3_check_link_speed(hw, conf->link_speeds); 2463 } 2464 2465 static int 2466 hns3_dev_configure(struct rte_eth_dev *dev) 2467 { 2468 struct hns3_adapter *hns = dev->data->dev_private; 2469 struct rte_eth_conf *conf = &dev->data->dev_conf; 2470 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 2471 struct hns3_hw *hw = &hns->hw; 2472 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2473 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2474 struct rte_eth_rss_conf rss_conf; 2475 bool gro_en; 2476 int ret; 2477 2478 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 2479 2480 /* 2481 * Some versions of hardware network engine does not support 2482 * individually enable/disable/reset the Tx or Rx queue. These devices 2483 * must enable/disable/reset Tx and Rx queues at the same time. When the 2484 * numbers of Tx queues allocated by upper applications are not equal to 2485 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 2486 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 2487 * work as usual. But these fake queues are imperceptible, and can not 2488 * be used by upper applications. 2489 */ 2490 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2491 if (ret) { 2492 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret); 2493 hw->cfg_max_queues = 0; 2494 return ret; 2495 } 2496 2497 hw->adapter_state = HNS3_NIC_CONFIGURING; 2498 ret = hns3_check_dev_conf(dev); 2499 if (ret) 2500 goto cfg_err; 2501 2502 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { 2503 ret = hns3_setup_dcb(dev); 2504 if (ret) 2505 goto cfg_err; 2506 } 2507 2508 /* When RSS is not configured, redirect the packet queue 0 */ 2509 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 2510 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2511 rss_conf = conf->rx_adv_conf.rss_conf; 2512 hw->rss_dis_flag = false; 2513 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2514 if (ret) 2515 goto cfg_err; 2516 } 2517 2518 ret = hns3_refresh_mtu(dev, conf); 2519 if (ret) 2520 goto cfg_err; 2521 2522 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf); 2523 if (ret) 2524 goto cfg_err; 2525 2526 ret = hns3_dev_configure_vlan(dev); 2527 if (ret) 2528 goto cfg_err; 2529 2530 /* config hardware GRO */ 2531 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 2532 ret = hns3_config_gro(hw, gro_en); 2533 if (ret) 2534 goto cfg_err; 2535 2536 hns3_init_rx_ptype_tble(dev); 2537 hw->adapter_state = HNS3_NIC_CONFIGURED; 2538 2539 return 0; 2540 2541 cfg_err: 2542 hw->cfg_max_queues = 0; 2543 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2544 hw->adapter_state = HNS3_NIC_INITIALIZED; 2545 2546 return ret; 2547 } 2548 2549 static int 2550 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2551 { 2552 struct hns3_config_max_frm_size_cmd *req; 2553 struct hns3_cmd_desc desc; 2554 2555 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2556 2557 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2558 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2559 req->min_frm_size = RTE_ETHER_MIN_LEN; 2560 2561 return hns3_cmd_send(hw, &desc, 1); 2562 } 2563 2564 static int 2565 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2566 { 2567 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2568 uint16_t original_mps = hns->pf.mps; 2569 int err; 2570 int ret; 2571 2572 ret = hns3_set_mac_mtu(hw, mps); 2573 if (ret) { 2574 hns3_err(hw, "failed to set mtu, ret = %d", ret); 2575 return ret; 2576 } 2577 2578 hns->pf.mps = mps; 2579 ret = hns3_buffer_alloc(hw); 2580 if (ret) { 2581 hns3_err(hw, "failed to allocate buffer, ret = %d", ret); 2582 goto rollback; 2583 } 2584 2585 return 0; 2586 2587 rollback: 2588 err = hns3_set_mac_mtu(hw, original_mps); 2589 if (err) { 2590 hns3_err(hw, "fail to rollback MTU, err = %d", err); 2591 return ret; 2592 } 2593 hns->pf.mps = original_mps; 2594 2595 return ret; 2596 } 2597 2598 static int 2599 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2600 { 2601 struct hns3_adapter *hns = dev->data->dev_private; 2602 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2603 struct hns3_hw *hw = &hns->hw; 2604 bool is_jumbo_frame; 2605 int ret; 2606 2607 if (dev->data->dev_started) { 2608 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2609 "before configuration", dev->data->port_id); 2610 return -EBUSY; 2611 } 2612 2613 rte_spinlock_lock(&hw->lock); 2614 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false; 2615 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2616 2617 /* 2618 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2619 * assign to "uint16_t" type variable. 2620 */ 2621 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2622 if (ret) { 2623 rte_spinlock_unlock(&hw->lock); 2624 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2625 dev->data->port_id, mtu, ret); 2626 return ret; 2627 } 2628 2629 if (is_jumbo_frame) 2630 dev->data->dev_conf.rxmode.offloads |= 2631 DEV_RX_OFFLOAD_JUMBO_FRAME; 2632 else 2633 dev->data->dev_conf.rxmode.offloads &= 2634 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2635 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2636 rte_spinlock_unlock(&hw->lock); 2637 2638 return 0; 2639 } 2640 2641 static uint32_t 2642 hns3_get_copper_port_speed_capa(uint32_t supported_speed) 2643 { 2644 uint32_t speed_capa = 0; 2645 2646 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT) 2647 speed_capa |= ETH_LINK_SPEED_10M_HD; 2648 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT) 2649 speed_capa |= ETH_LINK_SPEED_10M; 2650 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT) 2651 speed_capa |= ETH_LINK_SPEED_100M_HD; 2652 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT) 2653 speed_capa |= ETH_LINK_SPEED_100M; 2654 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT) 2655 speed_capa |= ETH_LINK_SPEED_1G; 2656 2657 return speed_capa; 2658 } 2659 2660 static uint32_t 2661 hns3_get_firber_port_speed_capa(uint32_t supported_speed) 2662 { 2663 uint32_t speed_capa = 0; 2664 2665 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT) 2666 speed_capa |= ETH_LINK_SPEED_1G; 2667 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT) 2668 speed_capa |= ETH_LINK_SPEED_10G; 2669 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT) 2670 speed_capa |= ETH_LINK_SPEED_25G; 2671 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT) 2672 speed_capa |= ETH_LINK_SPEED_40G; 2673 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT) 2674 speed_capa |= ETH_LINK_SPEED_50G; 2675 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT) 2676 speed_capa |= ETH_LINK_SPEED_100G; 2677 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT) 2678 speed_capa |= ETH_LINK_SPEED_200G; 2679 2680 return speed_capa; 2681 } 2682 2683 static uint32_t 2684 hns3_get_speed_capa(struct hns3_hw *hw) 2685 { 2686 struct hns3_mac *mac = &hw->mac; 2687 uint32_t speed_capa; 2688 2689 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 2690 speed_capa = 2691 hns3_get_copper_port_speed_capa(mac->supported_speed); 2692 else 2693 speed_capa = 2694 hns3_get_firber_port_speed_capa(mac->supported_speed); 2695 2696 if (mac->support_autoneg == 0) 2697 speed_capa |= ETH_LINK_SPEED_FIXED; 2698 2699 return speed_capa; 2700 } 2701 2702 int 2703 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 2704 { 2705 struct hns3_adapter *hns = eth_dev->data->dev_private; 2706 struct hns3_hw *hw = &hns->hw; 2707 uint16_t queue_num = hw->tqps_num; 2708 2709 /* 2710 * In interrupt mode, 'max_rx_queues' is set based on the number of 2711 * MSI-X interrupt resources of the hardware. 2712 */ 2713 if (hw->data->dev_conf.intr_conf.rxq == 1) 2714 queue_num = hw->intr_tqps_num; 2715 2716 info->max_rx_queues = queue_num; 2717 info->max_tx_queues = hw->tqps_num; 2718 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 2719 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 2720 info->max_mac_addrs = HNS3_UC_MACADDR_NUM; 2721 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 2722 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 2723 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 2724 DEV_RX_OFFLOAD_TCP_CKSUM | 2725 DEV_RX_OFFLOAD_UDP_CKSUM | 2726 DEV_RX_OFFLOAD_SCTP_CKSUM | 2727 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2728 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 2729 DEV_RX_OFFLOAD_KEEP_CRC | 2730 DEV_RX_OFFLOAD_SCATTER | 2731 DEV_RX_OFFLOAD_VLAN_STRIP | 2732 DEV_RX_OFFLOAD_VLAN_FILTER | 2733 DEV_RX_OFFLOAD_JUMBO_FRAME | 2734 DEV_RX_OFFLOAD_RSS_HASH | 2735 DEV_RX_OFFLOAD_TCP_LRO); 2736 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2737 DEV_TX_OFFLOAD_IPV4_CKSUM | 2738 DEV_TX_OFFLOAD_TCP_CKSUM | 2739 DEV_TX_OFFLOAD_UDP_CKSUM | 2740 DEV_TX_OFFLOAD_SCTP_CKSUM | 2741 DEV_TX_OFFLOAD_MULTI_SEGS | 2742 DEV_TX_OFFLOAD_TCP_TSO | 2743 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 2744 DEV_TX_OFFLOAD_GRE_TNL_TSO | 2745 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 2746 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 2747 hns3_txvlan_cap_get(hw)); 2748 2749 if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM)) 2750 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 2751 2752 if (hns3_dev_get_support(hw, INDEP_TXRX)) 2753 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 2754 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 2755 2756 if (hns3_dev_get_support(hw, PTP)) 2757 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 2758 2759 info->rx_desc_lim = (struct rte_eth_desc_lim) { 2760 .nb_max = HNS3_MAX_RING_DESC, 2761 .nb_min = HNS3_MIN_RING_DESC, 2762 .nb_align = HNS3_ALIGN_RING_DESC, 2763 }; 2764 2765 info->tx_desc_lim = (struct rte_eth_desc_lim) { 2766 .nb_max = HNS3_MAX_RING_DESC, 2767 .nb_min = HNS3_MIN_RING_DESC, 2768 .nb_align = HNS3_ALIGN_RING_DESC, 2769 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 2770 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 2771 }; 2772 2773 info->speed_capa = hns3_get_speed_capa(hw); 2774 info->default_rxconf = (struct rte_eth_rxconf) { 2775 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 2776 /* 2777 * If there are no available Rx buffer descriptors, incoming 2778 * packets are always dropped by hardware based on hns3 network 2779 * engine. 2780 */ 2781 .rx_drop_en = 1, 2782 .offloads = 0, 2783 }; 2784 info->default_txconf = (struct rte_eth_txconf) { 2785 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 2786 .offloads = 0, 2787 }; 2788 2789 info->reta_size = hw->rss_ind_tbl_size; 2790 info->hash_key_size = HNS3_RSS_KEY_SIZE; 2791 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 2792 2793 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2794 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2795 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2796 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2797 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2798 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2799 2800 return 0; 2801 } 2802 2803 static int 2804 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2805 size_t fw_size) 2806 { 2807 struct hns3_adapter *hns = eth_dev->data->dev_private; 2808 struct hns3_hw *hw = &hns->hw; 2809 uint32_t version = hw->fw_version; 2810 int ret; 2811 2812 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2813 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2814 HNS3_FW_VERSION_BYTE3_S), 2815 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2816 HNS3_FW_VERSION_BYTE2_S), 2817 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2818 HNS3_FW_VERSION_BYTE1_S), 2819 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2820 HNS3_FW_VERSION_BYTE0_S)); 2821 if (ret < 0) 2822 return -EINVAL; 2823 2824 ret += 1; /* add the size of '\0' */ 2825 if (fw_size < (size_t)ret) 2826 return ret; 2827 else 2828 return 0; 2829 } 2830 2831 static int 2832 hns3_update_port_link_info(struct rte_eth_dev *eth_dev) 2833 { 2834 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2835 int ret; 2836 2837 (void)hns3_update_link_status(hw); 2838 2839 ret = hns3_update_link_info(eth_dev); 2840 if (ret) 2841 hw->mac.link_status = ETH_LINK_DOWN; 2842 2843 return ret; 2844 } 2845 2846 static void 2847 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev, 2848 struct rte_eth_link *new_link) 2849 { 2850 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2851 struct hns3_mac *mac = &hw->mac; 2852 2853 switch (mac->link_speed) { 2854 case ETH_SPEED_NUM_10M: 2855 case ETH_SPEED_NUM_100M: 2856 case ETH_SPEED_NUM_1G: 2857 case ETH_SPEED_NUM_10G: 2858 case ETH_SPEED_NUM_25G: 2859 case ETH_SPEED_NUM_40G: 2860 case ETH_SPEED_NUM_50G: 2861 case ETH_SPEED_NUM_100G: 2862 case ETH_SPEED_NUM_200G: 2863 if (mac->link_status) 2864 new_link->link_speed = mac->link_speed; 2865 break; 2866 default: 2867 if (mac->link_status) 2868 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN; 2869 break; 2870 } 2871 2872 if (!mac->link_status) 2873 new_link->link_speed = ETH_SPEED_NUM_NONE; 2874 2875 new_link->link_duplex = mac->link_duplex; 2876 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2877 new_link->link_autoneg = mac->link_autoneg; 2878 } 2879 2880 static int 2881 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) 2882 { 2883 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */ 2884 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */ 2885 2886 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2887 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES; 2888 struct hns3_mac *mac = &hw->mac; 2889 struct rte_eth_link new_link; 2890 int ret; 2891 2892 /* When port is stopped, report link down. */ 2893 if (eth_dev->data->dev_started == 0) { 2894 new_link.link_autoneg = mac->link_autoneg; 2895 new_link.link_duplex = mac->link_duplex; 2896 new_link.link_speed = ETH_SPEED_NUM_NONE; 2897 new_link.link_status = ETH_LINK_DOWN; 2898 goto out; 2899 } 2900 2901 do { 2902 ret = hns3_update_port_link_info(eth_dev); 2903 if (ret) { 2904 hns3_err(hw, "failed to get port link info, ret = %d.", 2905 ret); 2906 break; 2907 } 2908 2909 if (!wait_to_complete || mac->link_status == ETH_LINK_UP) 2910 break; 2911 2912 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL); 2913 } while (retry_cnt--); 2914 2915 memset(&new_link, 0, sizeof(new_link)); 2916 hns3_setup_linkstatus(eth_dev, &new_link); 2917 2918 out: 2919 return rte_eth_linkstatus_set(eth_dev, &new_link); 2920 } 2921 2922 static int 2923 hns3_dev_set_link_up(struct rte_eth_dev *dev) 2924 { 2925 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2926 int ret; 2927 2928 /* 2929 * The "tx_pkt_burst" will be restored. But the secondary process does 2930 * not support the mechanism for notifying the primary process. 2931 */ 2932 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2933 hns3_err(hw, "secondary process does not support to set link up."); 2934 return -ENOTSUP; 2935 } 2936 2937 /* 2938 * If device isn't started Rx/Tx function is still disabled, setting 2939 * link up is not allowed. But it is probably better to return success 2940 * to reduce the impact on the upper layer. 2941 */ 2942 if (hw->adapter_state != HNS3_NIC_STARTED) { 2943 hns3_info(hw, "device isn't started, can't set link up."); 2944 return 0; 2945 } 2946 2947 if (!hw->set_link_down) 2948 return 0; 2949 2950 rte_spinlock_lock(&hw->lock); 2951 ret = hns3_cfg_mac_mode(hw, true); 2952 if (ret) { 2953 rte_spinlock_unlock(&hw->lock); 2954 hns3_err(hw, "failed to set link up, ret = %d", ret); 2955 return ret; 2956 } 2957 2958 hw->set_link_down = false; 2959 hns3_start_tx_datapath(dev); 2960 rte_spinlock_unlock(&hw->lock); 2961 2962 return 0; 2963 } 2964 2965 static int 2966 hns3_dev_set_link_down(struct rte_eth_dev *dev) 2967 { 2968 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2969 int ret; 2970 2971 /* 2972 * The "tx_pkt_burst" will be set to dummy function. But the secondary 2973 * process does not support the mechanism for notifying the primary 2974 * process. 2975 */ 2976 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2977 hns3_err(hw, "secondary process does not support to set link down."); 2978 return -ENOTSUP; 2979 } 2980 2981 /* 2982 * If device isn't started or the API has been called, link status is 2983 * down, return success. 2984 */ 2985 if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down) 2986 return 0; 2987 2988 rte_spinlock_lock(&hw->lock); 2989 hns3_stop_tx_datapath(dev); 2990 ret = hns3_cfg_mac_mode(hw, false); 2991 if (ret) { 2992 hns3_start_tx_datapath(dev); 2993 rte_spinlock_unlock(&hw->lock); 2994 hns3_err(hw, "failed to set link down, ret = %d", ret); 2995 return ret; 2996 } 2997 2998 hw->set_link_down = true; 2999 rte_spinlock_unlock(&hw->lock); 3000 3001 return 0; 3002 } 3003 3004 static int 3005 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 3006 { 3007 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3008 struct hns3_pf *pf = &hns->pf; 3009 3010 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 3011 return -EINVAL; 3012 3013 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 3014 3015 return 0; 3016 } 3017 3018 static int 3019 hns3_query_function_status(struct hns3_hw *hw) 3020 { 3021 #define HNS3_QUERY_MAX_CNT 10 3022 #define HNS3_QUERY_SLEEP_MSCOEND 1 3023 struct hns3_func_status_cmd *req; 3024 struct hns3_cmd_desc desc; 3025 int timeout = 0; 3026 int ret; 3027 3028 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 3029 req = (struct hns3_func_status_cmd *)desc.data; 3030 3031 do { 3032 ret = hns3_cmd_send(hw, &desc, 1); 3033 if (ret) { 3034 PMD_INIT_LOG(ERR, "query function status failed %d", 3035 ret); 3036 return ret; 3037 } 3038 3039 /* Check pf reset is done */ 3040 if (req->pf_state) 3041 break; 3042 3043 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 3044 } while (timeout++ < HNS3_QUERY_MAX_CNT); 3045 3046 return hns3_parse_func_status(hw, req); 3047 } 3048 3049 static int 3050 hns3_get_pf_max_tqp_num(struct hns3_hw *hw) 3051 { 3052 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3053 struct hns3_pf *pf = &hns->pf; 3054 3055 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) { 3056 /* 3057 * The total_tqps_num obtained from firmware is maximum tqp 3058 * numbers of this port, which should be used for PF and VFs. 3059 * There is no need for pf to have so many tqp numbers in 3060 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 3061 * coming from config file, is assigned to maximum queue number 3062 * for the PF of this port by user. So users can modify the 3063 * maximum queue number of PF according to their own application 3064 * scenarios, which is more flexible to use. In addition, many 3065 * memories can be saved due to allocating queue statistics 3066 * room according to the actual number of queues required. The 3067 * maximum queue number of PF for network engine with 3068 * revision_id greater than 0x30 is assigned by config file. 3069 */ 3070 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) { 3071 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) " 3072 "must be greater than 0.", 3073 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF); 3074 return -EINVAL; 3075 } 3076 3077 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 3078 hw->total_tqps_num); 3079 } else { 3080 /* 3081 * Due to the limitation on the number of PF interrupts 3082 * available, the maximum queue number assigned to PF on 3083 * the network engine with revision_id 0x21 is 64. 3084 */ 3085 hw->tqps_num = RTE_MIN(hw->total_tqps_num, 3086 HNS3_MAX_TQP_NUM_HIP08_PF); 3087 } 3088 3089 return 0; 3090 } 3091 3092 static int 3093 hns3_query_pf_resource(struct hns3_hw *hw) 3094 { 3095 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3096 struct hns3_pf *pf = &hns->pf; 3097 struct hns3_pf_res_cmd *req; 3098 struct hns3_cmd_desc desc; 3099 int ret; 3100 3101 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 3102 ret = hns3_cmd_send(hw, &desc, 1); 3103 if (ret) { 3104 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 3105 return ret; 3106 } 3107 3108 req = (struct hns3_pf_res_cmd *)desc.data; 3109 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) + 3110 rte_le_to_cpu_16(req->ext_tqp_num); 3111 ret = hns3_get_pf_max_tqp_num(hw); 3112 if (ret) 3113 return ret; 3114 3115 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 3116 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 3117 3118 if (req->tx_buf_size) 3119 pf->tx_buf_size = 3120 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 3121 else 3122 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 3123 3124 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 3125 3126 if (req->dv_buf_size) 3127 pf->dv_buf_size = 3128 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 3129 else 3130 pf->dv_buf_size = HNS3_DEFAULT_DV; 3131 3132 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 3133 3134 hw->num_msi = 3135 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number), 3136 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 3137 3138 return 0; 3139 } 3140 3141 static void 3142 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 3143 { 3144 struct hns3_cfg_param_cmd *req; 3145 uint64_t mac_addr_tmp_high; 3146 uint8_t ext_rss_size_max; 3147 uint64_t mac_addr_tmp; 3148 uint32_t i; 3149 3150 req = (struct hns3_cfg_param_cmd *)desc[0].data; 3151 3152 /* get the configuration */ 3153 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 3154 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 3155 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 3156 HNS3_CFG_TQP_DESC_N_M, 3157 HNS3_CFG_TQP_DESC_N_S); 3158 3159 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3160 HNS3_CFG_PHY_ADDR_M, 3161 HNS3_CFG_PHY_ADDR_S); 3162 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3163 HNS3_CFG_MEDIA_TP_M, 3164 HNS3_CFG_MEDIA_TP_S); 3165 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3166 HNS3_CFG_RX_BUF_LEN_M, 3167 HNS3_CFG_RX_BUF_LEN_S); 3168 /* get mac address */ 3169 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 3170 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3171 HNS3_CFG_MAC_ADDR_H_M, 3172 HNS3_CFG_MAC_ADDR_H_S); 3173 3174 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 3175 3176 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3177 HNS3_CFG_DEFAULT_SPEED_M, 3178 HNS3_CFG_DEFAULT_SPEED_S); 3179 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3180 HNS3_CFG_RSS_SIZE_M, 3181 HNS3_CFG_RSS_SIZE_S); 3182 3183 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 3184 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 3185 3186 req = (struct hns3_cfg_param_cmd *)desc[1].data; 3187 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 3188 3189 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3190 HNS3_CFG_SPEED_ABILITY_M, 3191 HNS3_CFG_SPEED_ABILITY_S); 3192 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3193 HNS3_CFG_UMV_TBL_SPACE_M, 3194 HNS3_CFG_UMV_TBL_SPACE_S); 3195 if (!cfg->umv_space) 3196 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 3197 3198 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]), 3199 HNS3_CFG_EXT_RSS_SIZE_M, 3200 HNS3_CFG_EXT_RSS_SIZE_S); 3201 /* 3202 * Field ext_rss_size_max obtained from firmware will be more flexible 3203 * for future changes and expansions, which is an exponent of 2, instead 3204 * of reading out directly. If this field is not zero, hns3 PF PMD 3205 * driver uses it as rss_size_max under one TC. Device, whose revision 3206 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the 3207 * maximum number of queues supported under a TC through this field. 3208 */ 3209 if (ext_rss_size_max) 3210 cfg->rss_size_max = 1U << ext_rss_size_max; 3211 } 3212 3213 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 3214 * @hw: pointer to struct hns3_hw 3215 * @hcfg: the config structure to be getted 3216 */ 3217 static int 3218 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 3219 { 3220 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 3221 struct hns3_cfg_param_cmd *req; 3222 uint32_t offset; 3223 uint32_t i; 3224 int ret; 3225 3226 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 3227 offset = 0; 3228 req = (struct hns3_cfg_param_cmd *)desc[i].data; 3229 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 3230 true); 3231 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 3232 i * HNS3_CFG_RD_LEN_BYTES); 3233 /* Len should be divided by 4 when send to hardware */ 3234 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 3235 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 3236 req->offset = rte_cpu_to_le_32(offset); 3237 } 3238 3239 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 3240 if (ret) { 3241 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 3242 return ret; 3243 } 3244 3245 hns3_parse_cfg(hcfg, desc); 3246 3247 return 0; 3248 } 3249 3250 static int 3251 hns3_parse_speed(int speed_cmd, uint32_t *speed) 3252 { 3253 switch (speed_cmd) { 3254 case HNS3_CFG_SPEED_10M: 3255 *speed = ETH_SPEED_NUM_10M; 3256 break; 3257 case HNS3_CFG_SPEED_100M: 3258 *speed = ETH_SPEED_NUM_100M; 3259 break; 3260 case HNS3_CFG_SPEED_1G: 3261 *speed = ETH_SPEED_NUM_1G; 3262 break; 3263 case HNS3_CFG_SPEED_10G: 3264 *speed = ETH_SPEED_NUM_10G; 3265 break; 3266 case HNS3_CFG_SPEED_25G: 3267 *speed = ETH_SPEED_NUM_25G; 3268 break; 3269 case HNS3_CFG_SPEED_40G: 3270 *speed = ETH_SPEED_NUM_40G; 3271 break; 3272 case HNS3_CFG_SPEED_50G: 3273 *speed = ETH_SPEED_NUM_50G; 3274 break; 3275 case HNS3_CFG_SPEED_100G: 3276 *speed = ETH_SPEED_NUM_100G; 3277 break; 3278 case HNS3_CFG_SPEED_200G: 3279 *speed = ETH_SPEED_NUM_200G; 3280 break; 3281 default: 3282 return -EINVAL; 3283 } 3284 3285 return 0; 3286 } 3287 3288 static void 3289 hns3_set_default_dev_specifications(struct hns3_hw *hw) 3290 { 3291 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 3292 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 3293 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 3294 hw->max_tm_rate = HNS3_ETHER_MAX_RATE; 3295 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 3296 } 3297 3298 static void 3299 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 3300 { 3301 struct hns3_dev_specs_0_cmd *req0; 3302 3303 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 3304 3305 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 3306 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 3307 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 3308 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); 3309 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 3310 } 3311 3312 static int 3313 hns3_check_dev_specifications(struct hns3_hw *hw) 3314 { 3315 if (hw->rss_ind_tbl_size == 0 || 3316 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 3317 hns3_err(hw, "the size of hash lookup table configured (%u)" 3318 " exceeds the maximum(%u)", hw->rss_ind_tbl_size, 3319 HNS3_RSS_IND_TBL_SIZE_MAX); 3320 return -EINVAL; 3321 } 3322 3323 return 0; 3324 } 3325 3326 static int 3327 hns3_query_dev_specifications(struct hns3_hw *hw) 3328 { 3329 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 3330 int ret; 3331 int i; 3332 3333 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3334 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 3335 true); 3336 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3337 } 3338 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 3339 3340 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 3341 if (ret) 3342 return ret; 3343 3344 hns3_parse_dev_specifications(hw, desc); 3345 3346 return hns3_check_dev_specifications(hw); 3347 } 3348 3349 static int 3350 hns3_get_capability(struct hns3_hw *hw) 3351 { 3352 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3353 struct rte_pci_device *pci_dev; 3354 struct hns3_pf *pf = &hns->pf; 3355 struct rte_eth_dev *eth_dev; 3356 uint16_t device_id; 3357 uint8_t revision; 3358 int ret; 3359 3360 eth_dev = &rte_eth_devices[hw->data->port_id]; 3361 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3362 device_id = pci_dev->id.device_id; 3363 3364 if (device_id == HNS3_DEV_ID_25GE_RDMA || 3365 device_id == HNS3_DEV_ID_50GE_RDMA || 3366 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || 3367 device_id == HNS3_DEV_ID_200G_RDMA) 3368 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); 3369 3370 /* Get PCI revision id */ 3371 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 3372 HNS3_PCI_REVISION_ID); 3373 if (ret != HNS3_PCI_REVISION_ID_LEN) { 3374 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 3375 ret); 3376 return -EIO; 3377 } 3378 hw->revision = revision; 3379 3380 if (revision < PCI_REVISION_ID_HIP09_A) { 3381 hns3_set_default_dev_specifications(hw); 3382 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 3383 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 3384 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 3385 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; 3386 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; 3387 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 3388 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; 3389 hw->rss_info.ipv6_sctp_offload_supported = false; 3390 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE; 3391 pf->support_multi_tc_pause = false; 3392 return 0; 3393 } 3394 3395 ret = hns3_query_dev_specifications(hw); 3396 if (ret) { 3397 PMD_INIT_LOG(ERR, 3398 "failed to query dev specifications, ret = %d", 3399 ret); 3400 return ret; 3401 } 3402 3403 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 3404 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 3405 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 3406 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; 3407 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; 3408 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 3409 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; 3410 hw->rss_info.ipv6_sctp_offload_supported = true; 3411 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE; 3412 pf->support_multi_tc_pause = true; 3413 3414 return 0; 3415 } 3416 3417 static int 3418 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type) 3419 { 3420 int ret; 3421 3422 switch (media_type) { 3423 case HNS3_MEDIA_TYPE_COPPER: 3424 if (!hns3_dev_get_support(hw, COPPER)) { 3425 PMD_INIT_LOG(ERR, 3426 "Media type is copper, not supported."); 3427 ret = -EOPNOTSUPP; 3428 } else { 3429 ret = 0; 3430 } 3431 break; 3432 case HNS3_MEDIA_TYPE_FIBER: 3433 ret = 0; 3434 break; 3435 case HNS3_MEDIA_TYPE_BACKPLANE: 3436 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported."); 3437 ret = -EOPNOTSUPP; 3438 break; 3439 default: 3440 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type); 3441 ret = -EINVAL; 3442 break; 3443 } 3444 3445 return ret; 3446 } 3447 3448 static int 3449 hns3_get_board_configuration(struct hns3_hw *hw) 3450 { 3451 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3452 struct hns3_pf *pf = &hns->pf; 3453 struct hns3_cfg cfg; 3454 int ret; 3455 3456 ret = hns3_get_board_cfg(hw, &cfg); 3457 if (ret) { 3458 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 3459 return ret; 3460 } 3461 3462 ret = hns3_check_media_type(hw, cfg.media_type); 3463 if (ret) 3464 return ret; 3465 3466 hw->mac.media_type = cfg.media_type; 3467 hw->rss_size_max = cfg.rss_size_max; 3468 hw->rss_dis_flag = false; 3469 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 3470 hw->mac.phy_addr = cfg.phy_addr; 3471 hw->num_tx_desc = cfg.tqp_desc_num; 3472 hw->num_rx_desc = cfg.tqp_desc_num; 3473 hw->dcb_info.num_pg = 1; 3474 hw->dcb_info.hw_pfc_map = 0; 3475 3476 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 3477 if (ret) { 3478 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d", 3479 cfg.default_speed, ret); 3480 return ret; 3481 } 3482 3483 pf->tc_max = cfg.tc_num; 3484 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 3485 PMD_INIT_LOG(WARNING, 3486 "Get TC num(%u) from flash, set TC num to 1", 3487 pf->tc_max); 3488 pf->tc_max = 1; 3489 } 3490 3491 /* Dev does not support DCB */ 3492 if (!hns3_dev_get_support(hw, DCB)) { 3493 pf->tc_max = 1; 3494 pf->pfc_max = 0; 3495 } else 3496 pf->pfc_max = pf->tc_max; 3497 3498 hw->dcb_info.num_tc = 1; 3499 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 3500 hw->tqps_num / hw->dcb_info.num_tc); 3501 hns3_set_bit(hw->hw_tc_map, 0, 1); 3502 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 3503 3504 pf->wanted_umv_size = cfg.umv_space; 3505 3506 return ret; 3507 } 3508 3509 static int 3510 hns3_get_configuration(struct hns3_hw *hw) 3511 { 3512 int ret; 3513 3514 ret = hns3_query_function_status(hw); 3515 if (ret) { 3516 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 3517 return ret; 3518 } 3519 3520 /* Get device capability */ 3521 ret = hns3_get_capability(hw); 3522 if (ret) { 3523 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 3524 return ret; 3525 } 3526 3527 /* Get pf resource */ 3528 ret = hns3_query_pf_resource(hw); 3529 if (ret) { 3530 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 3531 return ret; 3532 } 3533 3534 ret = hns3_get_board_configuration(hw); 3535 if (ret) { 3536 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret); 3537 return ret; 3538 } 3539 3540 ret = hns3_query_dev_fec_info(hw); 3541 if (ret) 3542 PMD_INIT_LOG(ERR, 3543 "failed to query FEC information, ret = %d", ret); 3544 3545 return ret; 3546 } 3547 3548 static int 3549 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 3550 uint16_t tqp_vid, bool is_pf) 3551 { 3552 struct hns3_tqp_map_cmd *req; 3553 struct hns3_cmd_desc desc; 3554 int ret; 3555 3556 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 3557 3558 req = (struct hns3_tqp_map_cmd *)desc.data; 3559 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 3560 req->tqp_vf = func_id; 3561 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 3562 if (!is_pf) 3563 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 3564 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 3565 3566 ret = hns3_cmd_send(hw, &desc, 1); 3567 if (ret) 3568 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 3569 3570 return ret; 3571 } 3572 3573 static int 3574 hns3_map_tqp(struct hns3_hw *hw) 3575 { 3576 int ret; 3577 int i; 3578 3579 /* 3580 * In current version, VF is not supported when PF is driven by DPDK 3581 * driver, so we assign total tqps_num tqps allocated to this port 3582 * to PF. 3583 */ 3584 for (i = 0; i < hw->total_tqps_num; i++) { 3585 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true); 3586 if (ret) 3587 return ret; 3588 } 3589 3590 return 0; 3591 } 3592 3593 static int 3594 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 3595 { 3596 struct hns3_config_mac_speed_dup_cmd *req; 3597 struct hns3_cmd_desc desc; 3598 int ret; 3599 3600 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 3601 3602 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 3603 3604 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 3605 3606 switch (speed) { 3607 case ETH_SPEED_NUM_10M: 3608 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3609 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 3610 break; 3611 case ETH_SPEED_NUM_100M: 3612 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3613 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 3614 break; 3615 case ETH_SPEED_NUM_1G: 3616 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3617 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 3618 break; 3619 case ETH_SPEED_NUM_10G: 3620 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3621 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 3622 break; 3623 case ETH_SPEED_NUM_25G: 3624 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3625 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 3626 break; 3627 case ETH_SPEED_NUM_40G: 3628 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3629 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 3630 break; 3631 case ETH_SPEED_NUM_50G: 3632 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3633 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 3634 break; 3635 case ETH_SPEED_NUM_100G: 3636 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3637 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 3638 break; 3639 case ETH_SPEED_NUM_200G: 3640 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3641 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G); 3642 break; 3643 default: 3644 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 3645 return -EINVAL; 3646 } 3647 3648 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 3649 3650 ret = hns3_cmd_send(hw, &desc, 1); 3651 if (ret) 3652 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 3653 3654 return ret; 3655 } 3656 3657 static int 3658 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3659 { 3660 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3661 struct hns3_pf *pf = &hns->pf; 3662 struct hns3_priv_buf *priv; 3663 uint32_t i, total_size; 3664 3665 total_size = pf->pkt_buf_size; 3666 3667 /* alloc tx buffer for all enabled tc */ 3668 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3669 priv = &buf_alloc->priv_buf[i]; 3670 3671 if (hw->hw_tc_map & BIT(i)) { 3672 if (total_size < pf->tx_buf_size) 3673 return -ENOMEM; 3674 3675 priv->tx_buf_size = pf->tx_buf_size; 3676 } else 3677 priv->tx_buf_size = 0; 3678 3679 total_size -= priv->tx_buf_size; 3680 } 3681 3682 return 0; 3683 } 3684 3685 static int 3686 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3687 { 3688 /* TX buffer size is unit by 128 byte */ 3689 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3690 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3691 struct hns3_tx_buff_alloc_cmd *req; 3692 struct hns3_cmd_desc desc; 3693 uint32_t buf_size; 3694 uint32_t i; 3695 int ret; 3696 3697 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3698 3699 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3700 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3701 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3702 3703 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3704 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3705 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3706 } 3707 3708 ret = hns3_cmd_send(hw, &desc, 1); 3709 if (ret) 3710 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3711 3712 return ret; 3713 } 3714 3715 static int 3716 hns3_get_tc_num(struct hns3_hw *hw) 3717 { 3718 int cnt = 0; 3719 uint8_t i; 3720 3721 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3722 if (hw->hw_tc_map & BIT(i)) 3723 cnt++; 3724 return cnt; 3725 } 3726 3727 static uint32_t 3728 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3729 { 3730 struct hns3_priv_buf *priv; 3731 uint32_t rx_priv = 0; 3732 int i; 3733 3734 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3735 priv = &buf_alloc->priv_buf[i]; 3736 if (priv->enable) 3737 rx_priv += priv->buf_size; 3738 } 3739 return rx_priv; 3740 } 3741 3742 static uint32_t 3743 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3744 { 3745 uint32_t total_tx_size = 0; 3746 uint32_t i; 3747 3748 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3749 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3750 3751 return total_tx_size; 3752 } 3753 3754 /* Get the number of pfc enabled TCs, which have private buffer */ 3755 static int 3756 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3757 { 3758 struct hns3_priv_buf *priv; 3759 int cnt = 0; 3760 uint8_t i; 3761 3762 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3763 priv = &buf_alloc->priv_buf[i]; 3764 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3765 cnt++; 3766 } 3767 3768 return cnt; 3769 } 3770 3771 /* Get the number of pfc disabled TCs, which have private buffer */ 3772 static int 3773 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3774 struct hns3_pkt_buf_alloc *buf_alloc) 3775 { 3776 struct hns3_priv_buf *priv; 3777 int cnt = 0; 3778 uint8_t i; 3779 3780 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3781 priv = &buf_alloc->priv_buf[i]; 3782 if (hw->hw_tc_map & BIT(i) && 3783 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3784 cnt++; 3785 } 3786 3787 return cnt; 3788 } 3789 3790 static bool 3791 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3792 uint32_t rx_all) 3793 { 3794 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3795 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3796 struct hns3_pf *pf = &hns->pf; 3797 uint32_t shared_buf, aligned_mps; 3798 uint32_t rx_priv; 3799 uint8_t tc_num; 3800 uint8_t i; 3801 3802 tc_num = hns3_get_tc_num(hw); 3803 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3804 3805 if (hns3_dev_get_support(hw, DCB)) 3806 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3807 pf->dv_buf_size; 3808 else 3809 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3810 + pf->dv_buf_size; 3811 3812 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3813 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), 3814 HNS3_BUF_SIZE_UNIT); 3815 3816 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3817 if (rx_all < rx_priv + shared_std) 3818 return false; 3819 3820 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3821 buf_alloc->s_buf.buf_size = shared_buf; 3822 if (hns3_dev_get_support(hw, DCB)) { 3823 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3824 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3825 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3826 HNS3_BUF_SIZE_UNIT); 3827 } else { 3828 buf_alloc->s_buf.self.high = 3829 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3830 buf_alloc->s_buf.self.low = aligned_mps; 3831 } 3832 3833 if (hns3_dev_get_support(hw, DCB)) { 3834 hi_thrd = shared_buf - pf->dv_buf_size; 3835 3836 if (tc_num <= NEED_RESERVE_TC_NUM) 3837 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT / 3838 BUF_MAX_PERCENT; 3839 3840 if (tc_num) 3841 hi_thrd = hi_thrd / tc_num; 3842 3843 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); 3844 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3845 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3846 } else { 3847 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3848 lo_thrd = aligned_mps; 3849 } 3850 3851 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3852 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3853 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3854 } 3855 3856 return true; 3857 } 3858 3859 static bool 3860 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3861 struct hns3_pkt_buf_alloc *buf_alloc) 3862 { 3863 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3864 struct hns3_pf *pf = &hns->pf; 3865 struct hns3_priv_buf *priv; 3866 uint32_t aligned_mps; 3867 uint32_t rx_all; 3868 uint8_t i; 3869 3870 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3871 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3872 3873 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3874 priv = &buf_alloc->priv_buf[i]; 3875 3876 priv->enable = 0; 3877 priv->wl.low = 0; 3878 priv->wl.high = 0; 3879 priv->buf_size = 0; 3880 3881 if (!(hw->hw_tc_map & BIT(i))) 3882 continue; 3883 3884 priv->enable = 1; 3885 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3886 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3887 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3888 HNS3_BUF_SIZE_UNIT); 3889 } else { 3890 priv->wl.low = 0; 3891 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3892 aligned_mps; 3893 } 3894 3895 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3896 } 3897 3898 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3899 } 3900 3901 static bool 3902 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3903 struct hns3_pkt_buf_alloc *buf_alloc) 3904 { 3905 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3906 struct hns3_pf *pf = &hns->pf; 3907 struct hns3_priv_buf *priv; 3908 int no_pfc_priv_num; 3909 uint32_t rx_all; 3910 uint8_t mask; 3911 int i; 3912 3913 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3914 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3915 3916 /* let the last to be cleared first */ 3917 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3918 priv = &buf_alloc->priv_buf[i]; 3919 mask = BIT((uint8_t)i); 3920 if (hw->hw_tc_map & mask && 3921 !(hw->dcb_info.hw_pfc_map & mask)) { 3922 /* Clear the no pfc TC private buffer */ 3923 priv->wl.low = 0; 3924 priv->wl.high = 0; 3925 priv->buf_size = 0; 3926 priv->enable = 0; 3927 no_pfc_priv_num--; 3928 } 3929 3930 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3931 no_pfc_priv_num == 0) 3932 break; 3933 } 3934 3935 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3936 } 3937 3938 static bool 3939 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3940 struct hns3_pkt_buf_alloc *buf_alloc) 3941 { 3942 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3943 struct hns3_pf *pf = &hns->pf; 3944 struct hns3_priv_buf *priv; 3945 uint32_t rx_all; 3946 int pfc_priv_num; 3947 uint8_t mask; 3948 int i; 3949 3950 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3951 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3952 3953 /* let the last to be cleared first */ 3954 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3955 priv = &buf_alloc->priv_buf[i]; 3956 mask = BIT((uint8_t)i); 3957 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) { 3958 /* Reduce the number of pfc TC with private buffer */ 3959 priv->wl.low = 0; 3960 priv->enable = 0; 3961 priv->wl.high = 0; 3962 priv->buf_size = 0; 3963 pfc_priv_num--; 3964 } 3965 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3966 pfc_priv_num == 0) 3967 break; 3968 } 3969 3970 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3971 } 3972 3973 static bool 3974 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3975 struct hns3_pkt_buf_alloc *buf_alloc) 3976 { 3977 #define COMPENSATE_BUFFER 0x3C00 3978 #define COMPENSATE_HALF_MPS_NUM 5 3979 #define PRIV_WL_GAP 0x1800 3980 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3981 struct hns3_pf *pf = &hns->pf; 3982 uint32_t tc_num = hns3_get_tc_num(hw); 3983 uint32_t half_mps = pf->mps >> 1; 3984 struct hns3_priv_buf *priv; 3985 uint32_t min_rx_priv; 3986 uint32_t rx_priv; 3987 uint8_t i; 3988 3989 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3990 if (tc_num) 3991 rx_priv = rx_priv / tc_num; 3992 3993 if (tc_num <= NEED_RESERVE_TC_NUM) 3994 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3995 3996 /* 3997 * Minimum value of private buffer in rx direction (min_rx_priv) is 3998 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3999 * buffer if rx_priv is greater than min_rx_priv. 4000 */ 4001 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 4002 COMPENSATE_HALF_MPS_NUM * half_mps; 4003 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 4004 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 4005 if (rx_priv < min_rx_priv) 4006 return false; 4007 4008 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 4009 priv = &buf_alloc->priv_buf[i]; 4010 priv->enable = 0; 4011 priv->wl.low = 0; 4012 priv->wl.high = 0; 4013 priv->buf_size = 0; 4014 4015 if (!(hw->hw_tc_map & BIT(i))) 4016 continue; 4017 4018 priv->enable = 1; 4019 priv->buf_size = rx_priv; 4020 priv->wl.high = rx_priv - pf->dv_buf_size; 4021 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 4022 } 4023 4024 buf_alloc->s_buf.buf_size = 0; 4025 4026 return true; 4027 } 4028 4029 /* 4030 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 4031 * @hw: pointer to struct hns3_hw 4032 * @buf_alloc: pointer to buffer calculation data 4033 * @return: 0: calculate sucessful, negative: fail 4034 */ 4035 static int 4036 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4037 { 4038 /* When DCB is not supported, rx private buffer is not allocated. */ 4039 if (!hns3_dev_get_support(hw, DCB)) { 4040 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4041 struct hns3_pf *pf = &hns->pf; 4042 uint32_t rx_all = pf->pkt_buf_size; 4043 4044 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 4045 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 4046 return -ENOMEM; 4047 4048 return 0; 4049 } 4050 4051 /* 4052 * Try to allocate privated packet buffer for all TCs without share 4053 * buffer. 4054 */ 4055 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 4056 return 0; 4057 4058 /* 4059 * Try to allocate privated packet buffer for all TCs with share 4060 * buffer. 4061 */ 4062 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 4063 return 0; 4064 4065 /* 4066 * For different application scenes, the enabled port number, TC number 4067 * and no_drop TC number are different. In order to obtain the better 4068 * performance, software could allocate the buffer size and configure 4069 * the waterline by trying to decrease the private buffer size according 4070 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc 4071 * enabled tc. 4072 */ 4073 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 4074 return 0; 4075 4076 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 4077 return 0; 4078 4079 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 4080 return 0; 4081 4082 return -ENOMEM; 4083 } 4084 4085 static int 4086 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4087 { 4088 struct hns3_rx_priv_buff_cmd *req; 4089 struct hns3_cmd_desc desc; 4090 uint32_t buf_size; 4091 int ret; 4092 int i; 4093 4094 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 4095 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 4096 4097 /* Alloc private buffer TCs */ 4098 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 4099 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 4100 4101 req->buf_num[i] = 4102 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 4103 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 4104 } 4105 4106 buf_size = buf_alloc->s_buf.buf_size; 4107 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 4108 (1 << HNS3_TC0_PRI_BUF_EN_B)); 4109 4110 ret = hns3_cmd_send(hw, &desc, 1); 4111 if (ret) 4112 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 4113 4114 return ret; 4115 } 4116 4117 static int 4118 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4119 { 4120 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 4121 struct hns3_rx_priv_wl_buf *req; 4122 struct hns3_priv_buf *priv; 4123 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 4124 int i, j; 4125 int ret; 4126 4127 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 4128 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 4129 false); 4130 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 4131 4132 /* The first descriptor set the NEXT bit to 1 */ 4133 if (i == 0) 4134 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4135 else 4136 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4137 4138 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 4139 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 4140 4141 priv = &buf_alloc->priv_buf[idx]; 4142 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 4143 HNS3_BUF_UNIT_S); 4144 req->tc_wl[j].high |= 4145 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4146 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 4147 HNS3_BUF_UNIT_S); 4148 req->tc_wl[j].low |= 4149 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4150 } 4151 } 4152 4153 /* Send 2 descriptor at one time */ 4154 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 4155 if (ret) 4156 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 4157 ret); 4158 return ret; 4159 } 4160 4161 static int 4162 hns3_common_thrd_config(struct hns3_hw *hw, 4163 struct hns3_pkt_buf_alloc *buf_alloc) 4164 { 4165 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 4166 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 4167 struct hns3_rx_com_thrd *req; 4168 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 4169 struct hns3_tc_thrd *tc; 4170 int tc_idx; 4171 int i, j; 4172 int ret; 4173 4174 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 4175 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 4176 false); 4177 req = (struct hns3_rx_com_thrd *)&desc[i].data; 4178 4179 /* The first descriptor set the NEXT bit to 1 */ 4180 if (i == 0) 4181 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4182 else 4183 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4184 4185 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 4186 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 4187 tc = &s_buf->tc_thrd[tc_idx]; 4188 4189 req->com_thrd[j].high = 4190 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 4191 req->com_thrd[j].high |= 4192 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4193 req->com_thrd[j].low = 4194 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 4195 req->com_thrd[j].low |= 4196 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4197 } 4198 } 4199 4200 /* Send 2 descriptors at one time */ 4201 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 4202 if (ret) 4203 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 4204 4205 return ret; 4206 } 4207 4208 static int 4209 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4210 { 4211 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 4212 struct hns3_rx_com_wl *req; 4213 struct hns3_cmd_desc desc; 4214 int ret; 4215 4216 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 4217 4218 req = (struct hns3_rx_com_wl *)desc.data; 4219 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 4220 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4221 4222 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 4223 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4224 4225 ret = hns3_cmd_send(hw, &desc, 1); 4226 if (ret) 4227 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 4228 4229 return ret; 4230 } 4231 4232 int 4233 hns3_buffer_alloc(struct hns3_hw *hw) 4234 { 4235 struct hns3_pkt_buf_alloc pkt_buf; 4236 int ret; 4237 4238 memset(&pkt_buf, 0, sizeof(pkt_buf)); 4239 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 4240 if (ret) { 4241 PMD_INIT_LOG(ERR, 4242 "could not calc tx buffer size for all TCs %d", 4243 ret); 4244 return ret; 4245 } 4246 4247 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 4248 if (ret) { 4249 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 4250 return ret; 4251 } 4252 4253 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 4254 if (ret) { 4255 PMD_INIT_LOG(ERR, 4256 "could not calc rx priv buffer size for all TCs %d", 4257 ret); 4258 return ret; 4259 } 4260 4261 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 4262 if (ret) { 4263 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 4264 return ret; 4265 } 4266 4267 if (hns3_dev_get_support(hw, DCB)) { 4268 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 4269 if (ret) { 4270 PMD_INIT_LOG(ERR, 4271 "could not configure rx private waterline %d", 4272 ret); 4273 return ret; 4274 } 4275 4276 ret = hns3_common_thrd_config(hw, &pkt_buf); 4277 if (ret) { 4278 PMD_INIT_LOG(ERR, 4279 "could not configure common threshold %d", 4280 ret); 4281 return ret; 4282 } 4283 } 4284 4285 ret = hns3_common_wl_config(hw, &pkt_buf); 4286 if (ret) 4287 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 4288 ret); 4289 4290 return ret; 4291 } 4292 4293 static int 4294 hns3_mac_init(struct hns3_hw *hw) 4295 { 4296 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4297 struct hns3_mac *mac = &hw->mac; 4298 struct hns3_pf *pf = &hns->pf; 4299 int ret; 4300 4301 pf->support_sfp_query = true; 4302 mac->link_duplex = ETH_LINK_FULL_DUPLEX; 4303 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 4304 if (ret) { 4305 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 4306 return ret; 4307 } 4308 4309 mac->link_status = ETH_LINK_DOWN; 4310 4311 return hns3_config_mtu(hw, pf->mps); 4312 } 4313 4314 static int 4315 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 4316 { 4317 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 4318 #define HNS3_ETHERTYPE_ALREADY_ADD 1 4319 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 4320 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 4321 int return_status; 4322 4323 if (cmdq_resp) { 4324 PMD_INIT_LOG(ERR, 4325 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 4326 cmdq_resp); 4327 return -EIO; 4328 } 4329 4330 switch (resp_code) { 4331 case HNS3_ETHERTYPE_SUCCESS_ADD: 4332 case HNS3_ETHERTYPE_ALREADY_ADD: 4333 return_status = 0; 4334 break; 4335 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 4336 PMD_INIT_LOG(ERR, 4337 "add mac ethertype failed for manager table overflow."); 4338 return_status = -EIO; 4339 break; 4340 case HNS3_ETHERTYPE_KEY_CONFLICT: 4341 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 4342 return_status = -EIO; 4343 break; 4344 default: 4345 PMD_INIT_LOG(ERR, 4346 "add mac ethertype failed for undefined, code=%u.", 4347 resp_code); 4348 return_status = -EIO; 4349 break; 4350 } 4351 4352 return return_status; 4353 } 4354 4355 static int 4356 hns3_add_mgr_tbl(struct hns3_hw *hw, 4357 const struct hns3_mac_mgr_tbl_entry_cmd *req) 4358 { 4359 struct hns3_cmd_desc desc; 4360 uint8_t resp_code; 4361 uint16_t retval; 4362 int ret; 4363 4364 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 4365 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 4366 4367 ret = hns3_cmd_send(hw, &desc, 1); 4368 if (ret) { 4369 PMD_INIT_LOG(ERR, 4370 "add mac ethertype failed for cmd_send, ret =%d.", 4371 ret); 4372 return ret; 4373 } 4374 4375 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 4376 retval = rte_le_to_cpu_16(desc.retval); 4377 4378 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 4379 } 4380 4381 static void 4382 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 4383 int *table_item_num) 4384 { 4385 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 4386 4387 /* 4388 * In current version, we add one item in management table as below: 4389 * 0x0180C200000E -- LLDP MC address 4390 */ 4391 tbl = mgr_table; 4392 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 4393 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 4394 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 4395 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 4396 tbl->i_port_bitmap = 0x1; 4397 *table_item_num = 1; 4398 } 4399 4400 static int 4401 hns3_init_mgr_tbl(struct hns3_hw *hw) 4402 { 4403 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 4404 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 4405 int table_item_num; 4406 int ret; 4407 int i; 4408 4409 memset(mgr_table, 0, sizeof(mgr_table)); 4410 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 4411 for (i = 0; i < table_item_num; i++) { 4412 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 4413 if (ret) { 4414 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 4415 ret); 4416 return ret; 4417 } 4418 } 4419 4420 return 0; 4421 } 4422 4423 static void 4424 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 4425 bool en_mc, bool en_bc, int vport_id) 4426 { 4427 if (!param) 4428 return; 4429 4430 memset(param, 0, sizeof(struct hns3_promisc_param)); 4431 if (en_uc) 4432 param->enable = HNS3_PROMISC_EN_UC; 4433 if (en_mc) 4434 param->enable |= HNS3_PROMISC_EN_MC; 4435 if (en_bc) 4436 param->enable |= HNS3_PROMISC_EN_BC; 4437 param->vf_id = vport_id; 4438 } 4439 4440 static int 4441 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 4442 { 4443 struct hns3_promisc_cfg_cmd *req; 4444 struct hns3_cmd_desc desc; 4445 int ret; 4446 4447 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 4448 4449 req = (struct hns3_promisc_cfg_cmd *)desc.data; 4450 req->vf_id = param->vf_id; 4451 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 4452 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 4453 4454 ret = hns3_cmd_send(hw, &desc, 1); 4455 if (ret) 4456 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 4457 4458 return ret; 4459 } 4460 4461 static int 4462 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 4463 { 4464 struct hns3_promisc_param param; 4465 bool en_bc_pmc = true; 4466 uint8_t vf_id; 4467 4468 /* 4469 * In current version VF is not supported when PF is driven by DPDK 4470 * driver, just need to configure parameters for PF vport. 4471 */ 4472 vf_id = HNS3_PF_FUNC_ID; 4473 4474 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 4475 return hns3_cmd_set_promisc_mode(hw, ¶m); 4476 } 4477 4478 static int 4479 hns3_promisc_init(struct hns3_hw *hw) 4480 { 4481 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4482 struct hns3_pf *pf = &hns->pf; 4483 struct hns3_promisc_param param; 4484 uint16_t func_id; 4485 int ret; 4486 4487 ret = hns3_set_promisc_mode(hw, false, false); 4488 if (ret) { 4489 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 4490 return ret; 4491 } 4492 4493 /* 4494 * In current version VFs are not supported when PF is driven by DPDK 4495 * driver. After PF has been taken over by DPDK, the original VF will 4496 * be invalid. So, there is a possibility of entry residues. It should 4497 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 4498 * during init. 4499 */ 4500 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 4501 hns3_promisc_param_init(¶m, false, false, false, func_id); 4502 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4503 if (ret) { 4504 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode," 4505 " ret = %d", func_id, ret); 4506 return ret; 4507 } 4508 } 4509 4510 return 0; 4511 } 4512 4513 static void 4514 hns3_promisc_uninit(struct hns3_hw *hw) 4515 { 4516 struct hns3_promisc_param param; 4517 uint16_t func_id; 4518 int ret; 4519 4520 func_id = HNS3_PF_FUNC_ID; 4521 4522 /* 4523 * In current version VFs are not supported when PF is driven by 4524 * DPDK driver, and VFs' promisc mode status has been cleared during 4525 * init and their status will not change. So just clear PF's promisc 4526 * mode status during uninit. 4527 */ 4528 hns3_promisc_param_init(¶m, false, false, false, func_id); 4529 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4530 if (ret) 4531 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 4532 " uninit, ret = %d", ret); 4533 } 4534 4535 static int 4536 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 4537 { 4538 bool allmulti = dev->data->all_multicast ? true : false; 4539 struct hns3_adapter *hns = dev->data->dev_private; 4540 struct hns3_hw *hw = &hns->hw; 4541 uint64_t offloads; 4542 int err; 4543 int ret; 4544 4545 rte_spinlock_lock(&hw->lock); 4546 ret = hns3_set_promisc_mode(hw, true, true); 4547 if (ret) { 4548 rte_spinlock_unlock(&hw->lock); 4549 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 4550 ret); 4551 return ret; 4552 } 4553 4554 /* 4555 * When promiscuous mode was enabled, disable the vlan filter to let 4556 * all packets coming in in the receiving direction. 4557 */ 4558 offloads = dev->data->dev_conf.rxmode.offloads; 4559 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4560 ret = hns3_enable_vlan_filter(hns, false); 4561 if (ret) { 4562 hns3_err(hw, "failed to enable promiscuous mode due to " 4563 "failure to disable vlan filter, ret = %d", 4564 ret); 4565 err = hns3_set_promisc_mode(hw, false, allmulti); 4566 if (err) 4567 hns3_err(hw, "failed to restore promiscuous " 4568 "status after disable vlan filter " 4569 "failed during enabling promiscuous " 4570 "mode, ret = %d", ret); 4571 } 4572 } 4573 4574 rte_spinlock_unlock(&hw->lock); 4575 4576 return ret; 4577 } 4578 4579 static int 4580 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 4581 { 4582 bool allmulti = dev->data->all_multicast ? true : false; 4583 struct hns3_adapter *hns = dev->data->dev_private; 4584 struct hns3_hw *hw = &hns->hw; 4585 uint64_t offloads; 4586 int err; 4587 int ret; 4588 4589 /* If now in all_multicast mode, must remain in all_multicast mode. */ 4590 rte_spinlock_lock(&hw->lock); 4591 ret = hns3_set_promisc_mode(hw, false, allmulti); 4592 if (ret) { 4593 rte_spinlock_unlock(&hw->lock); 4594 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 4595 ret); 4596 return ret; 4597 } 4598 /* when promiscuous mode was disabled, restore the vlan filter status */ 4599 offloads = dev->data->dev_conf.rxmode.offloads; 4600 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4601 ret = hns3_enable_vlan_filter(hns, true); 4602 if (ret) { 4603 hns3_err(hw, "failed to disable promiscuous mode due to" 4604 " failure to restore vlan filter, ret = %d", 4605 ret); 4606 err = hns3_set_promisc_mode(hw, true, true); 4607 if (err) 4608 hns3_err(hw, "failed to restore promiscuous " 4609 "status after enabling vlan filter " 4610 "failed during disabling promiscuous " 4611 "mode, ret = %d", ret); 4612 } 4613 } 4614 rte_spinlock_unlock(&hw->lock); 4615 4616 return ret; 4617 } 4618 4619 static int 4620 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 4621 { 4622 struct hns3_adapter *hns = dev->data->dev_private; 4623 struct hns3_hw *hw = &hns->hw; 4624 int ret; 4625 4626 if (dev->data->promiscuous) 4627 return 0; 4628 4629 rte_spinlock_lock(&hw->lock); 4630 ret = hns3_set_promisc_mode(hw, false, true); 4631 rte_spinlock_unlock(&hw->lock); 4632 if (ret) 4633 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 4634 ret); 4635 4636 return ret; 4637 } 4638 4639 static int 4640 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 4641 { 4642 struct hns3_adapter *hns = dev->data->dev_private; 4643 struct hns3_hw *hw = &hns->hw; 4644 int ret; 4645 4646 /* If now in promiscuous mode, must remain in all_multicast mode. */ 4647 if (dev->data->promiscuous) 4648 return 0; 4649 4650 rte_spinlock_lock(&hw->lock); 4651 ret = hns3_set_promisc_mode(hw, false, false); 4652 rte_spinlock_unlock(&hw->lock); 4653 if (ret) 4654 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4655 ret); 4656 4657 return ret; 4658 } 4659 4660 static int 4661 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4662 { 4663 struct hns3_hw *hw = &hns->hw; 4664 bool allmulti = hw->data->all_multicast ? true : false; 4665 int ret; 4666 4667 if (hw->data->promiscuous) { 4668 ret = hns3_set_promisc_mode(hw, true, true); 4669 if (ret) 4670 hns3_err(hw, "failed to restore promiscuous mode, " 4671 "ret = %d", ret); 4672 return ret; 4673 } 4674 4675 ret = hns3_set_promisc_mode(hw, false, allmulti); 4676 if (ret) 4677 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4678 ret); 4679 return ret; 4680 } 4681 4682 static int 4683 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) 4684 { 4685 struct hns3_sfp_info_cmd *resp; 4686 struct hns3_cmd_desc desc; 4687 int ret; 4688 4689 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 4690 resp = (struct hns3_sfp_info_cmd *)desc.data; 4691 resp->query_type = HNS3_ACTIVE_QUERY; 4692 4693 ret = hns3_cmd_send(hw, &desc, 1); 4694 if (ret == -EOPNOTSUPP) { 4695 hns3_warn(hw, "firmware does not support get SFP info," 4696 " ret = %d.", ret); 4697 return ret; 4698 } else if (ret) { 4699 hns3_err(hw, "get sfp info failed, ret = %d.", ret); 4700 return ret; 4701 } 4702 4703 /* 4704 * In some case, the speed of MAC obtained from firmware may be 0, it 4705 * shouldn't be set to mac->speed. 4706 */ 4707 if (!rte_le_to_cpu_32(resp->sfp_speed)) 4708 return 0; 4709 4710 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed); 4711 /* 4712 * if resp->supported_speed is 0, it means it's an old version 4713 * firmware, do not update these params. 4714 */ 4715 if (resp->supported_speed) { 4716 mac_info->query_type = HNS3_ACTIVE_QUERY; 4717 mac_info->supported_speed = 4718 rte_le_to_cpu_32(resp->supported_speed); 4719 mac_info->support_autoneg = resp->autoneg_ability; 4720 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED 4721 : ETH_LINK_AUTONEG; 4722 } else { 4723 mac_info->query_type = HNS3_DEFAULT_QUERY; 4724 } 4725 4726 return 0; 4727 } 4728 4729 static uint8_t 4730 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4731 { 4732 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M)) 4733 duplex = ETH_LINK_FULL_DUPLEX; 4734 4735 return duplex; 4736 } 4737 4738 static int 4739 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4740 { 4741 struct hns3_mac *mac = &hw->mac; 4742 int ret; 4743 4744 duplex = hns3_check_speed_dup(duplex, speed); 4745 if (mac->link_speed == speed && mac->link_duplex == duplex) 4746 return 0; 4747 4748 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4749 if (ret) 4750 return ret; 4751 4752 ret = hns3_port_shaper_update(hw, speed); 4753 if (ret) 4754 return ret; 4755 4756 mac->link_speed = speed; 4757 mac->link_duplex = duplex; 4758 4759 return 0; 4760 } 4761 4762 static int 4763 hns3_update_fiber_link_info(struct hns3_hw *hw) 4764 { 4765 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 4766 struct hns3_mac *mac = &hw->mac; 4767 struct hns3_mac mac_info; 4768 int ret; 4769 4770 /* If firmware do not support get SFP/qSFP speed, return directly */ 4771 if (!pf->support_sfp_query) 4772 return 0; 4773 4774 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4775 ret = hns3_get_sfp_info(hw, &mac_info); 4776 if (ret == -EOPNOTSUPP) { 4777 pf->support_sfp_query = false; 4778 return ret; 4779 } else if (ret) 4780 return ret; 4781 4782 /* Do nothing if no SFP */ 4783 if (mac_info.link_speed == ETH_SPEED_NUM_NONE) 4784 return 0; 4785 4786 /* 4787 * If query_type is HNS3_ACTIVE_QUERY, it is no need 4788 * to reconfigure the speed of MAC. Otherwise, it indicates 4789 * that the current firmware only supports to obtain the 4790 * speed of the SFP, and the speed of MAC needs to reconfigure. 4791 */ 4792 mac->query_type = mac_info.query_type; 4793 if (mac->query_type == HNS3_ACTIVE_QUERY) { 4794 if (mac_info.link_speed != mac->link_speed) { 4795 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4796 if (ret) 4797 return ret; 4798 } 4799 4800 mac->link_speed = mac_info.link_speed; 4801 mac->supported_speed = mac_info.supported_speed; 4802 mac->support_autoneg = mac_info.support_autoneg; 4803 mac->link_autoneg = mac_info.link_autoneg; 4804 4805 return 0; 4806 } 4807 4808 /* Config full duplex for SFP */ 4809 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, 4810 ETH_LINK_FULL_DUPLEX); 4811 } 4812 4813 static void 4814 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac) 4815 { 4816 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f 4817 4818 struct hns3_phy_params_bd0_cmd *req; 4819 uint32_t supported; 4820 4821 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 4822 mac->link_speed = rte_le_to_cpu_32(req->speed); 4823 mac->link_duplex = hns3_get_bit(req->duplex, 4824 HNS3_PHY_DUPLEX_CFG_B); 4825 mac->link_autoneg = hns3_get_bit(req->autoneg, 4826 HNS3_PHY_AUTONEG_CFG_B); 4827 mac->advertising = rte_le_to_cpu_32(req->advertising); 4828 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising); 4829 supported = rte_le_to_cpu_32(req->supported); 4830 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK; 4831 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT); 4832 } 4833 4834 static int 4835 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac) 4836 { 4837 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 4838 uint16_t i; 4839 int ret; 4840 4841 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 4842 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 4843 true); 4844 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4845 } 4846 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true); 4847 4848 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 4849 if (ret) { 4850 hns3_err(hw, "get phy parameters failed, ret = %d.", ret); 4851 return ret; 4852 } 4853 4854 hns3_parse_copper_phy_params(desc, mac); 4855 4856 return 0; 4857 } 4858 4859 static int 4860 hns3_update_copper_link_info(struct hns3_hw *hw) 4861 { 4862 struct hns3_mac *mac = &hw->mac; 4863 struct hns3_mac mac_info; 4864 int ret; 4865 4866 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4867 ret = hns3_get_copper_phy_params(hw, &mac_info); 4868 if (ret) 4869 return ret; 4870 4871 if (mac_info.link_speed != mac->link_speed) { 4872 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4873 if (ret) 4874 return ret; 4875 } 4876 4877 mac->link_speed = mac_info.link_speed; 4878 mac->link_duplex = mac_info.link_duplex; 4879 mac->link_autoneg = mac_info.link_autoneg; 4880 mac->supported_speed = mac_info.supported_speed; 4881 mac->advertising = mac_info.advertising; 4882 mac->lp_advertising = mac_info.lp_advertising; 4883 mac->support_autoneg = mac_info.support_autoneg; 4884 4885 return 0; 4886 } 4887 4888 static int 4889 hns3_update_link_info(struct rte_eth_dev *eth_dev) 4890 { 4891 struct hns3_adapter *hns = eth_dev->data->dev_private; 4892 struct hns3_hw *hw = &hns->hw; 4893 int ret = 0; 4894 4895 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) 4896 ret = hns3_update_copper_link_info(hw); 4897 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) 4898 ret = hns3_update_fiber_link_info(hw); 4899 4900 return ret; 4901 } 4902 4903 static int 4904 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4905 { 4906 struct hns3_config_mac_mode_cmd *req; 4907 struct hns3_cmd_desc desc; 4908 uint32_t loop_en = 0; 4909 uint8_t val = 0; 4910 int ret; 4911 4912 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4913 4914 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4915 if (enable) 4916 val = 1; 4917 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4918 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4919 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4920 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4921 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4922 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4923 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4924 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4925 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4926 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4927 4928 /* 4929 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC 4930 * when receiving frames. Otherwise, CRC will be stripped. 4931 */ 4932 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 4933 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0); 4934 else 4935 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4936 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4937 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4938 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4939 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4940 4941 ret = hns3_cmd_send(hw, &desc, 1); 4942 if (ret) 4943 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4944 4945 return ret; 4946 } 4947 4948 static int 4949 hns3_get_mac_link_status(struct hns3_hw *hw) 4950 { 4951 struct hns3_link_status_cmd *req; 4952 struct hns3_cmd_desc desc; 4953 int link_status; 4954 int ret; 4955 4956 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4957 ret = hns3_cmd_send(hw, &desc, 1); 4958 if (ret) { 4959 hns3_err(hw, "get link status cmd failed %d", ret); 4960 return ETH_LINK_DOWN; 4961 } 4962 4963 req = (struct hns3_link_status_cmd *)desc.data; 4964 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4965 4966 return !!link_status; 4967 } 4968 4969 static bool 4970 hns3_update_link_status(struct hns3_hw *hw) 4971 { 4972 int state; 4973 4974 state = hns3_get_mac_link_status(hw); 4975 if (state != hw->mac.link_status) { 4976 hw->mac.link_status = state; 4977 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4978 return true; 4979 } 4980 4981 return false; 4982 } 4983 4984 void 4985 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query) 4986 { 4987 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4988 struct rte_eth_link new_link; 4989 int ret; 4990 4991 if (query) 4992 hns3_update_port_link_info(dev); 4993 4994 memset(&new_link, 0, sizeof(new_link)); 4995 hns3_setup_linkstatus(dev, &new_link); 4996 4997 ret = rte_eth_linkstatus_set(dev, &new_link); 4998 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0) 4999 hns3_start_report_lse(dev); 5000 } 5001 5002 static void 5003 hns3_service_handler(void *param) 5004 { 5005 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 5006 struct hns3_adapter *hns = eth_dev->data->dev_private; 5007 struct hns3_hw *hw = &hns->hw; 5008 5009 if (!hns3_is_reset_pending(hns)) 5010 hns3_update_linkstatus_and_event(hw, true); 5011 else 5012 hns3_warn(hw, "Cancel the query when reset is pending"); 5013 5014 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 5015 } 5016 5017 static int 5018 hns3_init_hardware(struct hns3_adapter *hns) 5019 { 5020 struct hns3_hw *hw = &hns->hw; 5021 int ret; 5022 5023 ret = hns3_map_tqp(hw); 5024 if (ret) { 5025 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 5026 return ret; 5027 } 5028 5029 ret = hns3_init_umv_space(hw); 5030 if (ret) { 5031 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 5032 return ret; 5033 } 5034 5035 ret = hns3_mac_init(hw); 5036 if (ret) { 5037 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 5038 goto err_mac_init; 5039 } 5040 5041 ret = hns3_init_mgr_tbl(hw); 5042 if (ret) { 5043 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 5044 goto err_mac_init; 5045 } 5046 5047 ret = hns3_promisc_init(hw); 5048 if (ret) { 5049 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 5050 ret); 5051 goto err_mac_init; 5052 } 5053 5054 ret = hns3_init_vlan_config(hns); 5055 if (ret) { 5056 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 5057 goto err_mac_init; 5058 } 5059 5060 ret = hns3_dcb_init(hw); 5061 if (ret) { 5062 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 5063 goto err_mac_init; 5064 } 5065 5066 ret = hns3_init_fd_config(hns); 5067 if (ret) { 5068 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 5069 goto err_mac_init; 5070 } 5071 5072 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 5073 if (ret) { 5074 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 5075 goto err_mac_init; 5076 } 5077 5078 ret = hns3_config_gro(hw, false); 5079 if (ret) { 5080 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 5081 goto err_mac_init; 5082 } 5083 5084 /* 5085 * In the initialization clearing the all hardware mapping relationship 5086 * configurations between queues and interrupt vectors is needed, so 5087 * some error caused by the residual configurations, such as the 5088 * unexpected interrupt, can be avoid. 5089 */ 5090 ret = hns3_init_ring_with_vector(hw); 5091 if (ret) { 5092 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 5093 goto err_mac_init; 5094 } 5095 5096 return 0; 5097 5098 err_mac_init: 5099 hns3_uninit_umv_space(hw); 5100 return ret; 5101 } 5102 5103 static int 5104 hns3_clear_hw(struct hns3_hw *hw) 5105 { 5106 struct hns3_cmd_desc desc; 5107 int ret; 5108 5109 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); 5110 5111 ret = hns3_cmd_send(hw, &desc, 1); 5112 if (ret && ret != -EOPNOTSUPP) 5113 return ret; 5114 5115 return 0; 5116 } 5117 5118 static void 5119 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) 5120 { 5121 uint32_t val; 5122 5123 /* 5124 * The new firmware support report more hardware error types by 5125 * msix mode. These errors are defined as RAS errors in hardware 5126 * and belong to a different type from the MSI-x errors processed 5127 * by the network driver. 5128 * 5129 * Network driver should open the new error report on initialization. 5130 */ 5131 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5132 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); 5133 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); 5134 } 5135 5136 static uint32_t 5137 hns3_set_firber_default_support_speed(struct hns3_hw *hw) 5138 { 5139 struct hns3_mac *mac = &hw->mac; 5140 5141 switch (mac->link_speed) { 5142 case ETH_SPEED_NUM_1G: 5143 return HNS3_FIBER_LINK_SPEED_1G_BIT; 5144 case ETH_SPEED_NUM_10G: 5145 return HNS3_FIBER_LINK_SPEED_10G_BIT; 5146 case ETH_SPEED_NUM_25G: 5147 return HNS3_FIBER_LINK_SPEED_25G_BIT; 5148 case ETH_SPEED_NUM_40G: 5149 return HNS3_FIBER_LINK_SPEED_40G_BIT; 5150 case ETH_SPEED_NUM_50G: 5151 return HNS3_FIBER_LINK_SPEED_50G_BIT; 5152 case ETH_SPEED_NUM_100G: 5153 return HNS3_FIBER_LINK_SPEED_100G_BIT; 5154 case ETH_SPEED_NUM_200G: 5155 return HNS3_FIBER_LINK_SPEED_200G_BIT; 5156 default: 5157 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed); 5158 return 0; 5159 } 5160 } 5161 5162 /* 5163 * Validity of supported_speed for firber and copper media type can be 5164 * guaranteed by the following policy: 5165 * Copper: 5166 * Although the initialization of the phy in the firmware may not be 5167 * completed, the firmware can guarantees that the supported_speed is 5168 * an valid value. 5169 * Firber: 5170 * If the version of firmware supports the acitive query way of the 5171 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained 5172 * through it. If unsupported, use the SFP's speed as the value of the 5173 * supported_speed. 5174 */ 5175 static int 5176 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev) 5177 { 5178 struct hns3_adapter *hns = eth_dev->data->dev_private; 5179 struct hns3_hw *hw = &hns->hw; 5180 struct hns3_mac *mac = &hw->mac; 5181 int ret; 5182 5183 ret = hns3_update_link_info(eth_dev); 5184 if (ret) 5185 return ret; 5186 5187 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) { 5188 /* 5189 * Some firmware does not support the report of supported_speed, 5190 * and only report the effective speed of SFP. In this case, it 5191 * is necessary to use the SFP's speed as the supported_speed. 5192 */ 5193 if (mac->supported_speed == 0) 5194 mac->supported_speed = 5195 hns3_set_firber_default_support_speed(hw); 5196 } 5197 5198 return 0; 5199 } 5200 5201 static void 5202 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns) 5203 { 5204 struct hns3_mac *mac = &hns->hw.mac; 5205 5206 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) { 5207 hns->pf.support_fc_autoneg = true; 5208 return; 5209 } 5210 5211 /* 5212 * Flow control auto-negotiation requires the cooperation of the driver 5213 * and firmware. Currently, the optical port does not support flow 5214 * control auto-negotiation. 5215 */ 5216 hns->pf.support_fc_autoneg = false; 5217 } 5218 5219 static int 5220 hns3_init_pf(struct rte_eth_dev *eth_dev) 5221 { 5222 struct rte_device *dev = eth_dev->device; 5223 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 5224 struct hns3_adapter *hns = eth_dev->data->dev_private; 5225 struct hns3_hw *hw = &hns->hw; 5226 int ret; 5227 5228 PMD_INIT_FUNC_TRACE(); 5229 5230 /* Get hardware io base address from pcie BAR2 IO space */ 5231 hw->io_base = pci_dev->mem_resource[2].addr; 5232 5233 /* Firmware command queue initialize */ 5234 ret = hns3_cmd_init_queue(hw); 5235 if (ret) { 5236 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 5237 goto err_cmd_init_queue; 5238 } 5239 5240 hns3_clear_all_event_cause(hw); 5241 5242 /* Firmware command initialize */ 5243 ret = hns3_cmd_init(hw); 5244 if (ret) { 5245 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 5246 goto err_cmd_init; 5247 } 5248 5249 hns3_tx_push_init(eth_dev); 5250 5251 /* 5252 * To ensure that the hardware environment is clean during 5253 * initialization, the driver actively clear the hardware environment 5254 * during initialization, including PF and corresponding VFs' vlan, mac, 5255 * flow table configurations, etc. 5256 */ 5257 ret = hns3_clear_hw(hw); 5258 if (ret) { 5259 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); 5260 goto err_cmd_init; 5261 } 5262 5263 /* Hardware statistics of imissed registers cleared. */ 5264 ret = hns3_update_imissed_stats(hw, true); 5265 if (ret) { 5266 hns3_err(hw, "clear imissed stats failed, ret = %d", ret); 5267 goto err_cmd_init; 5268 } 5269 5270 hns3_config_all_msix_error(hw, true); 5271 5272 ret = rte_intr_callback_register(&pci_dev->intr_handle, 5273 hns3_interrupt_handler, 5274 eth_dev); 5275 if (ret) { 5276 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 5277 goto err_intr_callback_register; 5278 } 5279 5280 ret = hns3_ptp_init(hw); 5281 if (ret) 5282 goto err_get_config; 5283 5284 /* Enable interrupt */ 5285 rte_intr_enable(&pci_dev->intr_handle); 5286 hns3_pf_enable_irq0(hw); 5287 5288 /* Get configuration */ 5289 ret = hns3_get_configuration(hw); 5290 if (ret) { 5291 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 5292 goto err_get_config; 5293 } 5294 5295 ret = hns3_tqp_stats_init(hw); 5296 if (ret) 5297 goto err_get_config; 5298 5299 ret = hns3_init_hardware(hns); 5300 if (ret) { 5301 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 5302 goto err_init_hw; 5303 } 5304 5305 /* Initialize flow director filter list & hash */ 5306 ret = hns3_fdir_filter_init(hns); 5307 if (ret) { 5308 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 5309 goto err_fdir; 5310 } 5311 5312 hns3_rss_set_default_args(hw); 5313 5314 ret = hns3_enable_hw_error_intr(hns, true); 5315 if (ret) { 5316 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 5317 ret); 5318 goto err_enable_intr; 5319 } 5320 5321 ret = hns3_get_port_supported_speed(eth_dev); 5322 if (ret) { 5323 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported " 5324 "by device, ret = %d.", ret); 5325 goto err_supported_speed; 5326 } 5327 5328 hns3_get_fc_autoneg_capability(hns); 5329 5330 hns3_tm_conf_init(eth_dev); 5331 5332 return 0; 5333 5334 err_supported_speed: 5335 (void)hns3_enable_hw_error_intr(hns, false); 5336 err_enable_intr: 5337 hns3_fdir_filter_uninit(hns); 5338 err_fdir: 5339 hns3_uninit_umv_space(hw); 5340 err_init_hw: 5341 hns3_tqp_stats_uninit(hw); 5342 err_get_config: 5343 hns3_pf_disable_irq0(hw); 5344 rte_intr_disable(&pci_dev->intr_handle); 5345 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 5346 eth_dev); 5347 err_intr_callback_register: 5348 err_cmd_init: 5349 hns3_cmd_uninit(hw); 5350 hns3_cmd_destroy_queue(hw); 5351 err_cmd_init_queue: 5352 hw->io_base = NULL; 5353 5354 return ret; 5355 } 5356 5357 static void 5358 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 5359 { 5360 struct hns3_adapter *hns = eth_dev->data->dev_private; 5361 struct rte_device *dev = eth_dev->device; 5362 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 5363 struct hns3_hw *hw = &hns->hw; 5364 5365 PMD_INIT_FUNC_TRACE(); 5366 5367 hns3_tm_conf_uninit(eth_dev); 5368 hns3_enable_hw_error_intr(hns, false); 5369 hns3_rss_uninit(hns); 5370 (void)hns3_config_gro(hw, false); 5371 hns3_promisc_uninit(hw); 5372 hns3_flow_uninit(eth_dev); 5373 hns3_fdir_filter_uninit(hns); 5374 hns3_uninit_umv_space(hw); 5375 hns3_tqp_stats_uninit(hw); 5376 hns3_config_mac_tnl_int(hw, false); 5377 hns3_pf_disable_irq0(hw); 5378 rte_intr_disable(&pci_dev->intr_handle); 5379 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 5380 eth_dev); 5381 hns3_config_all_msix_error(hw, false); 5382 hns3_cmd_uninit(hw); 5383 hns3_cmd_destroy_queue(hw); 5384 hw->io_base = NULL; 5385 } 5386 5387 static uint32_t 5388 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds) 5389 { 5390 uint32_t speed_bit; 5391 5392 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) { 5393 case ETH_LINK_SPEED_10M: 5394 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT; 5395 break; 5396 case ETH_LINK_SPEED_10M_HD: 5397 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT; 5398 break; 5399 case ETH_LINK_SPEED_100M: 5400 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT; 5401 break; 5402 case ETH_LINK_SPEED_100M_HD: 5403 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT; 5404 break; 5405 case ETH_LINK_SPEED_1G: 5406 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT; 5407 break; 5408 default: 5409 speed_bit = 0; 5410 break; 5411 } 5412 5413 return speed_bit; 5414 } 5415 5416 static uint32_t 5417 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds) 5418 { 5419 uint32_t speed_bit; 5420 5421 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) { 5422 case ETH_LINK_SPEED_1G: 5423 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT; 5424 break; 5425 case ETH_LINK_SPEED_10G: 5426 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT; 5427 break; 5428 case ETH_LINK_SPEED_25G: 5429 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT; 5430 break; 5431 case ETH_LINK_SPEED_40G: 5432 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT; 5433 break; 5434 case ETH_LINK_SPEED_50G: 5435 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT; 5436 break; 5437 case ETH_LINK_SPEED_100G: 5438 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT; 5439 break; 5440 case ETH_LINK_SPEED_200G: 5441 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT; 5442 break; 5443 default: 5444 speed_bit = 0; 5445 break; 5446 } 5447 5448 return speed_bit; 5449 } 5450 5451 static int 5452 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds) 5453 { 5454 struct hns3_mac *mac = &hw->mac; 5455 uint32_t supported_speed = mac->supported_speed; 5456 uint32_t speed_bit = 0; 5457 5458 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 5459 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds); 5460 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) 5461 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds); 5462 5463 if (!(speed_bit & supported_speed)) { 5464 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.", 5465 link_speeds); 5466 return -EINVAL; 5467 } 5468 5469 return 0; 5470 } 5471 5472 static inline uint32_t 5473 hns3_get_link_speed(uint32_t link_speeds) 5474 { 5475 uint32_t speed = ETH_SPEED_NUM_NONE; 5476 5477 if (link_speeds & ETH_LINK_SPEED_10M || 5478 link_speeds & ETH_LINK_SPEED_10M_HD) 5479 speed = ETH_SPEED_NUM_10M; 5480 if (link_speeds & ETH_LINK_SPEED_100M || 5481 link_speeds & ETH_LINK_SPEED_100M_HD) 5482 speed = ETH_SPEED_NUM_100M; 5483 if (link_speeds & ETH_LINK_SPEED_1G) 5484 speed = ETH_SPEED_NUM_1G; 5485 if (link_speeds & ETH_LINK_SPEED_10G) 5486 speed = ETH_SPEED_NUM_10G; 5487 if (link_speeds & ETH_LINK_SPEED_25G) 5488 speed = ETH_SPEED_NUM_25G; 5489 if (link_speeds & ETH_LINK_SPEED_40G) 5490 speed = ETH_SPEED_NUM_40G; 5491 if (link_speeds & ETH_LINK_SPEED_50G) 5492 speed = ETH_SPEED_NUM_50G; 5493 if (link_speeds & ETH_LINK_SPEED_100G) 5494 speed = ETH_SPEED_NUM_100G; 5495 if (link_speeds & ETH_LINK_SPEED_200G) 5496 speed = ETH_SPEED_NUM_200G; 5497 5498 return speed; 5499 } 5500 5501 static uint8_t 5502 hns3_get_link_duplex(uint32_t link_speeds) 5503 { 5504 if ((link_speeds & ETH_LINK_SPEED_10M_HD) || 5505 (link_speeds & ETH_LINK_SPEED_100M_HD)) 5506 return ETH_LINK_HALF_DUPLEX; 5507 else 5508 return ETH_LINK_FULL_DUPLEX; 5509 } 5510 5511 static int 5512 hns3_set_copper_port_link_speed(struct hns3_hw *hw, 5513 struct hns3_set_link_speed_cfg *cfg) 5514 { 5515 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 5516 struct hns3_phy_params_bd0_cmd *req; 5517 uint16_t i; 5518 5519 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 5520 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 5521 false); 5522 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 5523 } 5524 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false); 5525 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 5526 req->autoneg = cfg->autoneg; 5527 5528 /* 5529 * The full speed capability is used to negotiate when 5530 * auto-negotiation is enabled. 5531 */ 5532 if (cfg->autoneg) { 5533 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT | 5534 HNS3_PHY_LINK_SPEED_10M_HD_BIT | 5535 HNS3_PHY_LINK_SPEED_100M_BIT | 5536 HNS3_PHY_LINK_SPEED_100M_HD_BIT | 5537 HNS3_PHY_LINK_SPEED_1000M_BIT; 5538 } else { 5539 req->speed = cfg->speed; 5540 req->duplex = cfg->duplex; 5541 } 5542 5543 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 5544 } 5545 5546 static int 5547 hns3_set_autoneg(struct hns3_hw *hw, bool enable) 5548 { 5549 struct hns3_config_auto_neg_cmd *req; 5550 struct hns3_cmd_desc desc; 5551 uint32_t flag = 0; 5552 int ret; 5553 5554 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false); 5555 5556 req = (struct hns3_config_auto_neg_cmd *)desc.data; 5557 if (enable) 5558 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1); 5559 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag); 5560 5561 ret = hns3_cmd_send(hw, &desc, 1); 5562 if (ret) 5563 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret); 5564 5565 return ret; 5566 } 5567 5568 static int 5569 hns3_set_fiber_port_link_speed(struct hns3_hw *hw, 5570 struct hns3_set_link_speed_cfg *cfg) 5571 { 5572 int ret; 5573 5574 if (hw->mac.support_autoneg) { 5575 ret = hns3_set_autoneg(hw, cfg->autoneg); 5576 if (ret) { 5577 hns3_err(hw, "failed to configure auto-negotiation."); 5578 return ret; 5579 } 5580 5581 /* 5582 * To enable auto-negotiation, we only need to open the switch 5583 * of auto-negotiation, then firmware sets all speed 5584 * capabilities. 5585 */ 5586 if (cfg->autoneg) 5587 return 0; 5588 } 5589 5590 /* 5591 * Some hardware doesn't support auto-negotiation, but users may not 5592 * configure link_speeds (default 0), which means auto-negotiation. 5593 * In this case, a warning message need to be printed, instead of 5594 * an error. 5595 */ 5596 if (cfg->autoneg) { 5597 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!"); 5598 return 0; 5599 } 5600 5601 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex); 5602 } 5603 5604 static int 5605 hns3_set_port_link_speed(struct hns3_hw *hw, 5606 struct hns3_set_link_speed_cfg *cfg) 5607 { 5608 int ret; 5609 5610 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) { 5611 #if defined(RTE_HNS3_ONLY_1630_FPGA) 5612 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 5613 if (pf->is_tmp_phy) 5614 return 0; 5615 #endif 5616 5617 ret = hns3_set_copper_port_link_speed(hw, cfg); 5618 if (ret) { 5619 hns3_err(hw, "failed to set copper port link speed," 5620 "ret = %d.", ret); 5621 return ret; 5622 } 5623 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) { 5624 ret = hns3_set_fiber_port_link_speed(hw, cfg); 5625 if (ret) { 5626 hns3_err(hw, "failed to set fiber port link speed," 5627 "ret = %d.", ret); 5628 return ret; 5629 } 5630 } 5631 5632 return 0; 5633 } 5634 5635 static int 5636 hns3_apply_link_speed(struct hns3_hw *hw) 5637 { 5638 struct rte_eth_conf *conf = &hw->data->dev_conf; 5639 struct hns3_set_link_speed_cfg cfg; 5640 5641 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg)); 5642 cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ? 5643 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 5644 if (cfg.autoneg != ETH_LINK_AUTONEG) { 5645 cfg.speed = hns3_get_link_speed(conf->link_speeds); 5646 cfg.duplex = hns3_get_link_duplex(conf->link_speeds); 5647 } 5648 5649 return hns3_set_port_link_speed(hw, &cfg); 5650 } 5651 5652 static int 5653 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 5654 { 5655 struct hns3_hw *hw = &hns->hw; 5656 bool link_en; 5657 int ret; 5658 5659 ret = hns3_update_queue_map_configure(hns); 5660 if (ret) { 5661 hns3_err(hw, "failed to update queue mapping configuration, ret = %d", 5662 ret); 5663 return ret; 5664 } 5665 5666 /* Note: hns3_tm_conf_update must be called after configuring DCB. */ 5667 ret = hns3_tm_conf_update(hw); 5668 if (ret) { 5669 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret); 5670 return ret; 5671 } 5672 5673 hns3_enable_rxd_adv_layout(hw); 5674 5675 ret = hns3_init_queues(hns, reset_queue); 5676 if (ret) { 5677 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret); 5678 return ret; 5679 } 5680 5681 link_en = hw->set_link_down ? false : true; 5682 ret = hns3_cfg_mac_mode(hw, link_en); 5683 if (ret) { 5684 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret); 5685 goto err_config_mac_mode; 5686 } 5687 5688 ret = hns3_apply_link_speed(hw); 5689 if (ret) 5690 goto err_set_link_speed; 5691 5692 return 0; 5693 5694 err_set_link_speed: 5695 (void)hns3_cfg_mac_mode(hw, false); 5696 5697 err_config_mac_mode: 5698 hns3_dev_release_mbufs(hns); 5699 /* 5700 * Here is exception handling, hns3_reset_all_tqps will have the 5701 * corresponding error message if it is handled incorrectly, so it is 5702 * not necessary to check hns3_reset_all_tqps return value, here keep 5703 * ret as the error code causing the exception. 5704 */ 5705 (void)hns3_reset_all_tqps(hns); 5706 return ret; 5707 } 5708 5709 static int 5710 hns3_map_rx_interrupt(struct rte_eth_dev *dev) 5711 { 5712 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5713 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5714 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5715 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET; 5716 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET; 5717 uint32_t intr_vector; 5718 uint16_t q_id; 5719 int ret; 5720 5721 /* 5722 * hns3 needs a separate interrupt to be used as event interrupt which 5723 * could not be shared with task queue pair, so KERNEL drivers need 5724 * support multiple interrupt vectors. 5725 */ 5726 if (dev->data->dev_conf.intr_conf.rxq == 0 || 5727 !rte_intr_cap_multiple(intr_handle)) 5728 return 0; 5729 5730 rte_intr_disable(intr_handle); 5731 intr_vector = hw->used_rx_queues; 5732 /* creates event fd for each intr vector when MSIX is used */ 5733 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5734 return -EINVAL; 5735 5736 if (intr_handle->intr_vec == NULL) { 5737 intr_handle->intr_vec = 5738 rte_zmalloc("intr_vec", 5739 hw->used_rx_queues * sizeof(int), 0); 5740 if (intr_handle->intr_vec == NULL) { 5741 hns3_err(hw, "failed to allocate %u rx_queues intr_vec", 5742 hw->used_rx_queues); 5743 ret = -ENOMEM; 5744 goto alloc_intr_vec_error; 5745 } 5746 } 5747 5748 if (rte_intr_allow_others(intr_handle)) { 5749 vec = RTE_INTR_VEC_RXTX_OFFSET; 5750 base = RTE_INTR_VEC_RXTX_OFFSET; 5751 } 5752 5753 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5754 ret = hns3_bind_ring_with_vector(hw, vec, true, 5755 HNS3_RING_TYPE_RX, q_id); 5756 if (ret) 5757 goto bind_vector_error; 5758 intr_handle->intr_vec[q_id] = vec; 5759 /* 5760 * If there are not enough efds (e.g. not enough interrupt), 5761 * remaining queues will be bond to the last interrupt. 5762 */ 5763 if (vec < base + intr_handle->nb_efd - 1) 5764 vec++; 5765 } 5766 rte_intr_enable(intr_handle); 5767 return 0; 5768 5769 bind_vector_error: 5770 rte_free(intr_handle->intr_vec); 5771 intr_handle->intr_vec = NULL; 5772 alloc_intr_vec_error: 5773 rte_intr_efd_disable(intr_handle); 5774 return ret; 5775 } 5776 5777 static int 5778 hns3_restore_rx_interrupt(struct hns3_hw *hw) 5779 { 5780 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 5781 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5782 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5783 uint16_t q_id; 5784 int ret; 5785 5786 if (dev->data->dev_conf.intr_conf.rxq == 0) 5787 return 0; 5788 5789 if (rte_intr_dp_is_en(intr_handle)) { 5790 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5791 ret = hns3_bind_ring_with_vector(hw, 5792 intr_handle->intr_vec[q_id], true, 5793 HNS3_RING_TYPE_RX, q_id); 5794 if (ret) 5795 return ret; 5796 } 5797 } 5798 5799 return 0; 5800 } 5801 5802 static void 5803 hns3_restore_filter(struct rte_eth_dev *dev) 5804 { 5805 hns3_restore_rss_filter(dev); 5806 } 5807 5808 static int 5809 hns3_dev_start(struct rte_eth_dev *dev) 5810 { 5811 struct hns3_adapter *hns = dev->data->dev_private; 5812 struct hns3_hw *hw = &hns->hw; 5813 bool old_state = hw->set_link_down; 5814 int ret; 5815 5816 PMD_INIT_FUNC_TRACE(); 5817 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 5818 return -EBUSY; 5819 5820 rte_spinlock_lock(&hw->lock); 5821 hw->adapter_state = HNS3_NIC_STARTING; 5822 5823 /* 5824 * If the dev_set_link_down() API has been called, the "set_link_down" 5825 * flag can be cleared by dev_start() API. In addition, the flag should 5826 * also be cleared before calling hns3_do_start() so that MAC can be 5827 * enabled in dev_start stage. 5828 */ 5829 hw->set_link_down = false; 5830 ret = hns3_do_start(hns, true); 5831 if (ret) 5832 goto do_start_fail; 5833 5834 ret = hns3_map_rx_interrupt(dev); 5835 if (ret) 5836 goto map_rx_inter_err; 5837 5838 /* 5839 * There are three register used to control the status of a TQP 5840 * (contains a pair of Tx queue and Rx queue) in the new version network 5841 * engine. One is used to control the enabling of Tx queue, the other is 5842 * used to control the enabling of Rx queue, and the last is the master 5843 * switch used to control the enabling of the tqp. The Tx register and 5844 * TQP register must be enabled at the same time to enable a Tx queue. 5845 * The same applies to the Rx queue. For the older network engine, this 5846 * function only refresh the enabled flag, and it is used to update the 5847 * status of queue in the dpdk framework. 5848 */ 5849 ret = hns3_start_all_txqs(dev); 5850 if (ret) 5851 goto map_rx_inter_err; 5852 5853 ret = hns3_start_all_rxqs(dev); 5854 if (ret) 5855 goto start_all_rxqs_fail; 5856 5857 hw->adapter_state = HNS3_NIC_STARTED; 5858 rte_spinlock_unlock(&hw->lock); 5859 5860 hns3_rx_scattered_calc(dev); 5861 hns3_set_rxtx_function(dev); 5862 hns3_mp_req_start_rxtx(dev); 5863 5864 hns3_restore_filter(dev); 5865 5866 /* Enable interrupt of all rx queues before enabling queues */ 5867 hns3_dev_all_rx_queue_intr_enable(hw, true); 5868 5869 /* 5870 * After finished the initialization, enable tqps to receive/transmit 5871 * packets and refresh all queue status. 5872 */ 5873 hns3_start_tqps(hw); 5874 5875 hns3_tm_dev_start_proc(hw); 5876 5877 if (dev->data->dev_conf.intr_conf.lsc != 0) 5878 hns3_dev_link_update(dev, 0); 5879 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 5880 5881 hns3_info(hw, "hns3 dev start successful!"); 5882 5883 return 0; 5884 5885 start_all_rxqs_fail: 5886 hns3_stop_all_txqs(dev); 5887 map_rx_inter_err: 5888 (void)hns3_do_stop(hns); 5889 do_start_fail: 5890 hw->set_link_down = old_state; 5891 hw->adapter_state = HNS3_NIC_CONFIGURED; 5892 rte_spinlock_unlock(&hw->lock); 5893 5894 return ret; 5895 } 5896 5897 static int 5898 hns3_do_stop(struct hns3_adapter *hns) 5899 { 5900 struct hns3_hw *hw = &hns->hw; 5901 int ret; 5902 5903 /* 5904 * The "hns3_do_stop" function will also be called by .stop_service to 5905 * prepare reset. At the time of global or IMP reset, the command cannot 5906 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 5907 * accessed during the reset process. So the mbuf can not be released 5908 * during reset and is required to be released after the reset is 5909 * completed. 5910 */ 5911 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 5912 hns3_dev_release_mbufs(hns); 5913 5914 ret = hns3_cfg_mac_mode(hw, false); 5915 if (ret) 5916 return ret; 5917 hw->mac.link_status = ETH_LINK_DOWN; 5918 5919 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 5920 hns3_configure_all_mac_addr(hns, true); 5921 ret = hns3_reset_all_tqps(hns); 5922 if (ret) { 5923 hns3_err(hw, "failed to reset all queues ret = %d.", 5924 ret); 5925 return ret; 5926 } 5927 } 5928 5929 return 0; 5930 } 5931 5932 static void 5933 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) 5934 { 5935 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5936 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5937 struct hns3_adapter *hns = dev->data->dev_private; 5938 struct hns3_hw *hw = &hns->hw; 5939 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 5940 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 5941 uint16_t q_id; 5942 5943 if (dev->data->dev_conf.intr_conf.rxq == 0) 5944 return; 5945 5946 /* unmap the ring with vector */ 5947 if (rte_intr_allow_others(intr_handle)) { 5948 vec = RTE_INTR_VEC_RXTX_OFFSET; 5949 base = RTE_INTR_VEC_RXTX_OFFSET; 5950 } 5951 if (rte_intr_dp_is_en(intr_handle)) { 5952 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5953 (void)hns3_bind_ring_with_vector(hw, vec, false, 5954 HNS3_RING_TYPE_RX, 5955 q_id); 5956 if (vec < base + intr_handle->nb_efd - 1) 5957 vec++; 5958 } 5959 } 5960 /* Clean datapath event and queue/vec mapping */ 5961 rte_intr_efd_disable(intr_handle); 5962 if (intr_handle->intr_vec) { 5963 rte_free(intr_handle->intr_vec); 5964 intr_handle->intr_vec = NULL; 5965 } 5966 } 5967 5968 static int 5969 hns3_dev_stop(struct rte_eth_dev *dev) 5970 { 5971 struct hns3_adapter *hns = dev->data->dev_private; 5972 struct hns3_hw *hw = &hns->hw; 5973 5974 PMD_INIT_FUNC_TRACE(); 5975 dev->data->dev_started = 0; 5976 5977 hw->adapter_state = HNS3_NIC_STOPPING; 5978 hns3_set_rxtx_function(dev); 5979 rte_wmb(); 5980 /* Disable datapath on secondary process. */ 5981 hns3_mp_req_stop_rxtx(dev); 5982 /* Prevent crashes when queues are still in use. */ 5983 rte_delay_ms(hw->cfg_max_queues); 5984 5985 rte_spinlock_lock(&hw->lock); 5986 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 5987 hns3_tm_dev_stop_proc(hw); 5988 hns3_config_mac_tnl_int(hw, false); 5989 hns3_stop_tqps(hw); 5990 hns3_do_stop(hns); 5991 hns3_unmap_rx_interrupt(dev); 5992 hw->adapter_state = HNS3_NIC_CONFIGURED; 5993 } 5994 hns3_rx_scattered_reset(dev); 5995 rte_eal_alarm_cancel(hns3_service_handler, dev); 5996 hns3_stop_report_lse(dev); 5997 rte_spinlock_unlock(&hw->lock); 5998 5999 return 0; 6000 } 6001 6002 static int 6003 hns3_dev_close(struct rte_eth_dev *eth_dev) 6004 { 6005 struct hns3_adapter *hns = eth_dev->data->dev_private; 6006 struct hns3_hw *hw = &hns->hw; 6007 int ret = 0; 6008 6009 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6010 return 0; 6011 6012 if (hw->adapter_state == HNS3_NIC_STARTED) 6013 ret = hns3_dev_stop(eth_dev); 6014 6015 hw->adapter_state = HNS3_NIC_CLOSING; 6016 hns3_reset_abort(hns); 6017 hw->adapter_state = HNS3_NIC_CLOSED; 6018 6019 hns3_configure_all_mc_mac_addr(hns, true); 6020 hns3_remove_all_vlan_table(hns); 6021 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 6022 hns3_uninit_pf(eth_dev); 6023 hns3_free_all_queues(eth_dev); 6024 rte_free(hw->reset.wait_data); 6025 hns3_mp_uninit_primary(); 6026 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 6027 6028 return ret; 6029 } 6030 6031 static void 6032 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause, 6033 bool *tx_pause) 6034 { 6035 struct hns3_mac *mac = &hw->mac; 6036 uint32_t advertising = mac->advertising; 6037 uint32_t lp_advertising = mac->lp_advertising; 6038 *rx_pause = false; 6039 *tx_pause = false; 6040 6041 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) { 6042 *rx_pause = true; 6043 *tx_pause = true; 6044 } else if (advertising & lp_advertising & 6045 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) { 6046 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 6047 *rx_pause = true; 6048 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 6049 *tx_pause = true; 6050 } 6051 } 6052 6053 static enum hns3_fc_mode 6054 hns3_get_autoneg_fc_mode(struct hns3_hw *hw) 6055 { 6056 enum hns3_fc_mode current_mode; 6057 bool rx_pause = false; 6058 bool tx_pause = false; 6059 6060 switch (hw->mac.media_type) { 6061 case HNS3_MEDIA_TYPE_COPPER: 6062 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause); 6063 break; 6064 6065 /* 6066 * Flow control auto-negotiation is not supported for fiber and 6067 * backpalne media type. 6068 */ 6069 case HNS3_MEDIA_TYPE_FIBER: 6070 case HNS3_MEDIA_TYPE_BACKPLANE: 6071 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled."); 6072 current_mode = hw->requested_fc_mode; 6073 goto out; 6074 default: 6075 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).", 6076 hw->mac.media_type); 6077 current_mode = HNS3_FC_NONE; 6078 goto out; 6079 } 6080 6081 if (rx_pause && tx_pause) 6082 current_mode = HNS3_FC_FULL; 6083 else if (rx_pause) 6084 current_mode = HNS3_FC_RX_PAUSE; 6085 else if (tx_pause) 6086 current_mode = HNS3_FC_TX_PAUSE; 6087 else 6088 current_mode = HNS3_FC_NONE; 6089 6090 out: 6091 return current_mode; 6092 } 6093 6094 static enum hns3_fc_mode 6095 hns3_get_current_fc_mode(struct rte_eth_dev *dev) 6096 { 6097 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6098 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6099 struct hns3_mac *mac = &hw->mac; 6100 6101 /* 6102 * When the flow control mode is obtained, the device may not complete 6103 * auto-negotiation. It is necessary to wait for link establishment. 6104 */ 6105 (void)hns3_dev_link_update(dev, 1); 6106 6107 /* 6108 * If the link auto-negotiation of the nic is disabled, or the flow 6109 * control auto-negotiation is not supported, the forced flow control 6110 * mode is used. 6111 */ 6112 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg) 6113 return hw->requested_fc_mode; 6114 6115 return hns3_get_autoneg_fc_mode(hw); 6116 } 6117 6118 static int 6119 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 6120 { 6121 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6122 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6123 enum hns3_fc_mode current_mode; 6124 6125 current_mode = hns3_get_current_fc_mode(dev); 6126 switch (current_mode) { 6127 case HNS3_FC_FULL: 6128 fc_conf->mode = RTE_FC_FULL; 6129 break; 6130 case HNS3_FC_TX_PAUSE: 6131 fc_conf->mode = RTE_FC_TX_PAUSE; 6132 break; 6133 case HNS3_FC_RX_PAUSE: 6134 fc_conf->mode = RTE_FC_RX_PAUSE; 6135 break; 6136 case HNS3_FC_NONE: 6137 default: 6138 fc_conf->mode = RTE_FC_NONE; 6139 break; 6140 } 6141 6142 fc_conf->pause_time = pf->pause_time; 6143 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0; 6144 6145 return 0; 6146 } 6147 6148 static int 6149 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg) 6150 { 6151 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 6152 6153 if (!pf->support_fc_autoneg) { 6154 if (autoneg != 0) { 6155 hns3_err(hw, "unsupported fc auto-negotiation setting."); 6156 return -EOPNOTSUPP; 6157 } 6158 6159 /* 6160 * Flow control auto-negotiation of the NIC is not supported, 6161 * but other auto-negotiation features may be supported. 6162 */ 6163 if (autoneg != hw->mac.link_autoneg) { 6164 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!"); 6165 return -EOPNOTSUPP; 6166 } 6167 6168 return 0; 6169 } 6170 6171 /* 6172 * If flow control auto-negotiation of the NIC is supported, all 6173 * auto-negotiation features are supported. 6174 */ 6175 if (autoneg != hw->mac.link_autoneg) { 6176 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!"); 6177 return -EOPNOTSUPP; 6178 } 6179 6180 return 0; 6181 } 6182 6183 static int 6184 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 6185 { 6186 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6187 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6188 int ret; 6189 6190 if (fc_conf->high_water || fc_conf->low_water || 6191 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 6192 hns3_err(hw, "Unsupported flow control settings specified, " 6193 "high_water(%u), low_water(%u), send_xon(%u) and " 6194 "mac_ctrl_frame_fwd(%u) must be set to '0'", 6195 fc_conf->high_water, fc_conf->low_water, 6196 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 6197 return -EINVAL; 6198 } 6199 6200 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg); 6201 if (ret) 6202 return ret; 6203 6204 if (!fc_conf->pause_time) { 6205 hns3_err(hw, "Invalid pause time %u setting.", 6206 fc_conf->pause_time); 6207 return -EINVAL; 6208 } 6209 6210 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 6211 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 6212 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 6213 "current_fc_status = %d", hw->current_fc_status); 6214 return -EOPNOTSUPP; 6215 } 6216 6217 if (hw->num_tc > 1 && !pf->support_multi_tc_pause) { 6218 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported."); 6219 return -EOPNOTSUPP; 6220 } 6221 6222 rte_spinlock_lock(&hw->lock); 6223 ret = hns3_fc_enable(dev, fc_conf); 6224 rte_spinlock_unlock(&hw->lock); 6225 6226 return ret; 6227 } 6228 6229 static int 6230 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 6231 struct rte_eth_pfc_conf *pfc_conf) 6232 { 6233 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6234 int ret; 6235 6236 if (!hns3_dev_get_support(hw, DCB)) { 6237 hns3_err(hw, "This port does not support dcb configurations."); 6238 return -EOPNOTSUPP; 6239 } 6240 6241 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 6242 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 6243 hns3_err(hw, "Unsupported flow control settings specified, " 6244 "high_water(%u), low_water(%u), send_xon(%u) and " 6245 "mac_ctrl_frame_fwd(%u) must be set to '0'", 6246 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 6247 pfc_conf->fc.send_xon, 6248 pfc_conf->fc.mac_ctrl_frame_fwd); 6249 return -EINVAL; 6250 } 6251 if (pfc_conf->fc.autoneg) { 6252 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 6253 return -EINVAL; 6254 } 6255 if (pfc_conf->fc.pause_time == 0) { 6256 hns3_err(hw, "Invalid pause time %u setting.", 6257 pfc_conf->fc.pause_time); 6258 return -EINVAL; 6259 } 6260 6261 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 6262 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 6263 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 6264 "current_fc_status = %d", hw->current_fc_status); 6265 return -EOPNOTSUPP; 6266 } 6267 6268 rte_spinlock_lock(&hw->lock); 6269 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 6270 rte_spinlock_unlock(&hw->lock); 6271 6272 return ret; 6273 } 6274 6275 static int 6276 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 6277 { 6278 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6279 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6280 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 6281 int i; 6282 6283 rte_spinlock_lock(&hw->lock); 6284 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) 6285 dcb_info->nb_tcs = pf->local_max_tc; 6286 else 6287 dcb_info->nb_tcs = 1; 6288 6289 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 6290 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 6291 for (i = 0; i < dcb_info->nb_tcs; i++) 6292 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 6293 6294 for (i = 0; i < hw->num_tc; i++) { 6295 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 6296 dcb_info->tc_queue.tc_txq[0][i].base = 6297 hw->tc_queue[i].tqp_offset; 6298 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 6299 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 6300 hw->tc_queue[i].tqp_count; 6301 } 6302 rte_spinlock_unlock(&hw->lock); 6303 6304 return 0; 6305 } 6306 6307 static int 6308 hns3_reinit_dev(struct hns3_adapter *hns) 6309 { 6310 struct hns3_hw *hw = &hns->hw; 6311 int ret; 6312 6313 ret = hns3_cmd_init(hw); 6314 if (ret) { 6315 hns3_err(hw, "Failed to init cmd: %d", ret); 6316 return ret; 6317 } 6318 6319 ret = hns3_reset_all_tqps(hns); 6320 if (ret) { 6321 hns3_err(hw, "Failed to reset all queues: %d", ret); 6322 return ret; 6323 } 6324 6325 ret = hns3_init_hardware(hns); 6326 if (ret) { 6327 hns3_err(hw, "Failed to init hardware: %d", ret); 6328 return ret; 6329 } 6330 6331 ret = hns3_enable_hw_error_intr(hns, true); 6332 if (ret) { 6333 hns3_err(hw, "fail to enable hw error interrupts: %d", 6334 ret); 6335 return ret; 6336 } 6337 hns3_info(hw, "Reset done, driver initialization finished."); 6338 6339 return 0; 6340 } 6341 6342 static bool 6343 is_pf_reset_done(struct hns3_hw *hw) 6344 { 6345 uint32_t val, reg, reg_bit; 6346 6347 switch (hw->reset.level) { 6348 case HNS3_IMP_RESET: 6349 reg = HNS3_GLOBAL_RESET_REG; 6350 reg_bit = HNS3_IMP_RESET_BIT; 6351 break; 6352 case HNS3_GLOBAL_RESET: 6353 reg = HNS3_GLOBAL_RESET_REG; 6354 reg_bit = HNS3_GLOBAL_RESET_BIT; 6355 break; 6356 case HNS3_FUNC_RESET: 6357 reg = HNS3_FUN_RST_ING; 6358 reg_bit = HNS3_FUN_RST_ING_B; 6359 break; 6360 case HNS3_FLR_RESET: 6361 default: 6362 hns3_err(hw, "Wait for unsupported reset level: %d", 6363 hw->reset.level); 6364 return true; 6365 } 6366 val = hns3_read_dev(hw, reg); 6367 if (hns3_get_bit(val, reg_bit)) 6368 return false; 6369 else 6370 return true; 6371 } 6372 6373 bool 6374 hns3_is_reset_pending(struct hns3_adapter *hns) 6375 { 6376 struct hns3_hw *hw = &hns->hw; 6377 enum hns3_reset_level reset; 6378 6379 hns3_check_event_cause(hns, NULL); 6380 reset = hns3_get_reset_level(hns, &hw->reset.pending); 6381 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 6382 hw->reset.level < reset) { 6383 hns3_warn(hw, "High level reset %d is pending", reset); 6384 return true; 6385 } 6386 reset = hns3_get_reset_level(hns, &hw->reset.request); 6387 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 6388 hw->reset.level < reset) { 6389 hns3_warn(hw, "High level reset %d is request", reset); 6390 return true; 6391 } 6392 return false; 6393 } 6394 6395 static int 6396 hns3_wait_hardware_ready(struct hns3_adapter *hns) 6397 { 6398 struct hns3_hw *hw = &hns->hw; 6399 struct hns3_wait_data *wait_data = hw->reset.wait_data; 6400 struct timeval tv; 6401 6402 if (wait_data->result == HNS3_WAIT_SUCCESS) 6403 return 0; 6404 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 6405 hns3_clock_gettime(&tv); 6406 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 6407 tv.tv_sec, tv.tv_usec); 6408 return -ETIME; 6409 } else if (wait_data->result == HNS3_WAIT_REQUEST) 6410 return -EAGAIN; 6411 6412 wait_data->hns = hns; 6413 wait_data->check_completion = is_pf_reset_done; 6414 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 6415 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms(); 6416 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 6417 wait_data->count = HNS3_RESET_WAIT_CNT; 6418 wait_data->result = HNS3_WAIT_REQUEST; 6419 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 6420 return -EAGAIN; 6421 } 6422 6423 static int 6424 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 6425 { 6426 struct hns3_cmd_desc desc; 6427 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 6428 6429 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 6430 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 6431 req->fun_reset_vfid = func_id; 6432 6433 return hns3_cmd_send(hw, &desc, 1); 6434 } 6435 6436 static int 6437 hns3_imp_reset_cmd(struct hns3_hw *hw) 6438 { 6439 struct hns3_cmd_desc desc; 6440 6441 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 6442 desc.data[0] = 0xeedd; 6443 6444 return hns3_cmd_send(hw, &desc, 1); 6445 } 6446 6447 static void 6448 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 6449 { 6450 struct hns3_hw *hw = &hns->hw; 6451 struct timeval tv; 6452 uint32_t val; 6453 6454 hns3_clock_gettime(&tv); 6455 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 6456 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 6457 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 6458 tv.tv_sec, tv.tv_usec); 6459 return; 6460 } 6461 6462 switch (reset_level) { 6463 case HNS3_IMP_RESET: 6464 hns3_imp_reset_cmd(hw); 6465 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 6466 tv.tv_sec, tv.tv_usec); 6467 break; 6468 case HNS3_GLOBAL_RESET: 6469 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 6470 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 6471 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 6472 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 6473 tv.tv_sec, tv.tv_usec); 6474 break; 6475 case HNS3_FUNC_RESET: 6476 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 6477 tv.tv_sec, tv.tv_usec); 6478 /* schedule again to check later */ 6479 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 6480 hns3_schedule_reset(hns); 6481 break; 6482 default: 6483 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 6484 return; 6485 } 6486 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 6487 } 6488 6489 static enum hns3_reset_level 6490 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 6491 { 6492 struct hns3_hw *hw = &hns->hw; 6493 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 6494 6495 /* Return the highest priority reset level amongst all */ 6496 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 6497 reset_level = HNS3_IMP_RESET; 6498 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 6499 reset_level = HNS3_GLOBAL_RESET; 6500 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 6501 reset_level = HNS3_FUNC_RESET; 6502 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 6503 reset_level = HNS3_FLR_RESET; 6504 6505 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 6506 return HNS3_NONE_RESET; 6507 6508 return reset_level; 6509 } 6510 6511 static void 6512 hns3_record_imp_error(struct hns3_adapter *hns) 6513 { 6514 struct hns3_hw *hw = &hns->hw; 6515 uint32_t reg_val; 6516 6517 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 6518 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { 6519 hns3_warn(hw, "Detected IMP RD poison!"); 6520 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); 6521 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 6522 } 6523 6524 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { 6525 hns3_warn(hw, "Detected IMP CMDQ error!"); 6526 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); 6527 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 6528 } 6529 } 6530 6531 static int 6532 hns3_prepare_reset(struct hns3_adapter *hns) 6533 { 6534 struct hns3_hw *hw = &hns->hw; 6535 uint32_t reg_val; 6536 int ret; 6537 6538 switch (hw->reset.level) { 6539 case HNS3_FUNC_RESET: 6540 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 6541 if (ret) 6542 return ret; 6543 6544 /* 6545 * After performaning pf reset, it is not necessary to do the 6546 * mailbox handling or send any command to firmware, because 6547 * any mailbox handling or command to firmware is only valid 6548 * after hns3_cmd_init is called. 6549 */ 6550 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 6551 hw->reset.stats.request_cnt++; 6552 break; 6553 case HNS3_IMP_RESET: 6554 hns3_record_imp_error(hns); 6555 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 6556 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 6557 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 6558 break; 6559 default: 6560 break; 6561 } 6562 return 0; 6563 } 6564 6565 static int 6566 hns3_set_rst_done(struct hns3_hw *hw) 6567 { 6568 struct hns3_pf_rst_done_cmd *req; 6569 struct hns3_cmd_desc desc; 6570 6571 req = (struct hns3_pf_rst_done_cmd *)desc.data; 6572 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 6573 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 6574 return hns3_cmd_send(hw, &desc, 1); 6575 } 6576 6577 static int 6578 hns3_stop_service(struct hns3_adapter *hns) 6579 { 6580 struct hns3_hw *hw = &hns->hw; 6581 struct rte_eth_dev *eth_dev; 6582 6583 eth_dev = &rte_eth_devices[hw->data->port_id]; 6584 hw->mac.link_status = ETH_LINK_DOWN; 6585 if (hw->adapter_state == HNS3_NIC_STARTED) { 6586 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 6587 hns3_update_linkstatus_and_event(hw, false); 6588 } 6589 6590 hns3_set_rxtx_function(eth_dev); 6591 rte_wmb(); 6592 /* Disable datapath on secondary process. */ 6593 hns3_mp_req_stop_rxtx(eth_dev); 6594 rte_delay_ms(hw->cfg_max_queues); 6595 6596 rte_spinlock_lock(&hw->lock); 6597 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 6598 hw->adapter_state == HNS3_NIC_STOPPING) { 6599 hns3_enable_all_queues(hw, false); 6600 hns3_do_stop(hns); 6601 hw->reset.mbuf_deferred_free = true; 6602 } else 6603 hw->reset.mbuf_deferred_free = false; 6604 6605 /* 6606 * It is cumbersome for hardware to pick-and-choose entries for deletion 6607 * from table space. Hence, for function reset software intervention is 6608 * required to delete the entries 6609 */ 6610 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 6611 hns3_configure_all_mc_mac_addr(hns, true); 6612 rte_spinlock_unlock(&hw->lock); 6613 6614 return 0; 6615 } 6616 6617 static int 6618 hns3_start_service(struct hns3_adapter *hns) 6619 { 6620 struct hns3_hw *hw = &hns->hw; 6621 struct rte_eth_dev *eth_dev; 6622 6623 if (hw->reset.level == HNS3_IMP_RESET || 6624 hw->reset.level == HNS3_GLOBAL_RESET) 6625 hns3_set_rst_done(hw); 6626 eth_dev = &rte_eth_devices[hw->data->port_id]; 6627 hns3_set_rxtx_function(eth_dev); 6628 hns3_mp_req_start_rxtx(eth_dev); 6629 if (hw->adapter_state == HNS3_NIC_STARTED) { 6630 /* 6631 * This API parent function already hold the hns3_hw.lock, the 6632 * hns3_service_handler may report lse, in bonding application 6633 * it will call driver's ops which may acquire the hns3_hw.lock 6634 * again, thus lead to deadlock. 6635 * We defer calls hns3_service_handler to avoid the deadlock. 6636 */ 6637 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL, 6638 hns3_service_handler, eth_dev); 6639 6640 /* Enable interrupt of all rx queues before enabling queues */ 6641 hns3_dev_all_rx_queue_intr_enable(hw, true); 6642 /* 6643 * Enable state of each rxq and txq will be recovered after 6644 * reset, so we need to restore them before enable all tqps; 6645 */ 6646 hns3_restore_tqp_enable_state(hw); 6647 /* 6648 * When finished the initialization, enable queues to receive 6649 * and transmit packets. 6650 */ 6651 hns3_enable_all_queues(hw, true); 6652 } 6653 6654 return 0; 6655 } 6656 6657 static int 6658 hns3_restore_conf(struct hns3_adapter *hns) 6659 { 6660 struct hns3_hw *hw = &hns->hw; 6661 int ret; 6662 6663 ret = hns3_configure_all_mac_addr(hns, false); 6664 if (ret) 6665 return ret; 6666 6667 ret = hns3_configure_all_mc_mac_addr(hns, false); 6668 if (ret) 6669 goto err_mc_mac; 6670 6671 ret = hns3_dev_promisc_restore(hns); 6672 if (ret) 6673 goto err_promisc; 6674 6675 ret = hns3_restore_vlan_table(hns); 6676 if (ret) 6677 goto err_promisc; 6678 6679 ret = hns3_restore_vlan_conf(hns); 6680 if (ret) 6681 goto err_promisc; 6682 6683 ret = hns3_restore_all_fdir_filter(hns); 6684 if (ret) 6685 goto err_promisc; 6686 6687 ret = hns3_restore_ptp(hns); 6688 if (ret) 6689 goto err_promisc; 6690 6691 ret = hns3_restore_rx_interrupt(hw); 6692 if (ret) 6693 goto err_promisc; 6694 6695 ret = hns3_restore_gro_conf(hw); 6696 if (ret) 6697 goto err_promisc; 6698 6699 ret = hns3_restore_fec(hw); 6700 if (ret) 6701 goto err_promisc; 6702 6703 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 6704 ret = hns3_do_start(hns, false); 6705 if (ret) 6706 goto err_promisc; 6707 hns3_info(hw, "hns3 dev restart successful!"); 6708 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 6709 hw->adapter_state = HNS3_NIC_CONFIGURED; 6710 return 0; 6711 6712 err_promisc: 6713 hns3_configure_all_mc_mac_addr(hns, true); 6714 err_mc_mac: 6715 hns3_configure_all_mac_addr(hns, true); 6716 return ret; 6717 } 6718 6719 static void 6720 hns3_reset_service(void *param) 6721 { 6722 struct hns3_adapter *hns = (struct hns3_adapter *)param; 6723 struct hns3_hw *hw = &hns->hw; 6724 enum hns3_reset_level reset_level; 6725 struct timeval tv_delta; 6726 struct timeval tv_start; 6727 struct timeval tv; 6728 uint64_t msec; 6729 int ret; 6730 6731 /* 6732 * The interrupt is not triggered within the delay time. 6733 * The interrupt may have been lost. It is necessary to handle 6734 * the interrupt to recover from the error. 6735 */ 6736 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 6737 SCHEDULE_DEFERRED) { 6738 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 6739 __ATOMIC_RELAXED); 6740 hns3_err(hw, "Handling interrupts in delayed tasks"); 6741 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 6742 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 6743 if (reset_level == HNS3_NONE_RESET) { 6744 hns3_err(hw, "No reset level is set, try IMP reset"); 6745 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 6746 } 6747 } 6748 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 6749 6750 /* 6751 * Check if there is any ongoing reset in the hardware. This status can 6752 * be checked from reset_pending. If there is then, we need to wait for 6753 * hardware to complete reset. 6754 * a. If we are able to figure out in reasonable time that hardware 6755 * has fully resetted then, we can proceed with driver, client 6756 * reset. 6757 * b. else, we can come back later to check this status so re-sched 6758 * now. 6759 */ 6760 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 6761 if (reset_level != HNS3_NONE_RESET) { 6762 hns3_clock_gettime(&tv_start); 6763 ret = hns3_reset_process(hns, reset_level); 6764 hns3_clock_gettime(&tv); 6765 timersub(&tv, &tv_start, &tv_delta); 6766 msec = hns3_clock_calctime_ms(&tv_delta); 6767 if (msec > HNS3_RESET_PROCESS_MS) 6768 hns3_err(hw, "%d handle long time delta %" PRIu64 6769 " ms time=%ld.%.6ld", 6770 hw->reset.level, msec, 6771 tv.tv_sec, tv.tv_usec); 6772 if (ret == -EAGAIN) 6773 return; 6774 } 6775 6776 /* Check if we got any *new* reset requests to be honored */ 6777 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 6778 if (reset_level != HNS3_NONE_RESET) 6779 hns3_msix_process(hns, reset_level); 6780 } 6781 6782 static unsigned int 6783 hns3_get_speed_capa_num(uint16_t device_id) 6784 { 6785 unsigned int num; 6786 6787 switch (device_id) { 6788 case HNS3_DEV_ID_25GE: 6789 case HNS3_DEV_ID_25GE_RDMA: 6790 num = 2; 6791 break; 6792 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6793 case HNS3_DEV_ID_200G_RDMA: 6794 num = 1; 6795 break; 6796 default: 6797 num = 0; 6798 break; 6799 } 6800 6801 return num; 6802 } 6803 6804 static int 6805 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, 6806 uint16_t device_id) 6807 { 6808 switch (device_id) { 6809 case HNS3_DEV_ID_25GE: 6810 /* fallthrough */ 6811 case HNS3_DEV_ID_25GE_RDMA: 6812 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed; 6813 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa; 6814 6815 /* In HNS3 device, the 25G NIC is compatible with 10G rate */ 6816 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed; 6817 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa; 6818 break; 6819 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6820 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed; 6821 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa; 6822 break; 6823 case HNS3_DEV_ID_200G_RDMA: 6824 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed; 6825 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa; 6826 break; 6827 default: 6828 return -ENOTSUP; 6829 } 6830 6831 return 0; 6832 } 6833 6834 static int 6835 hns3_fec_get_capability(struct rte_eth_dev *dev, 6836 struct rte_eth_fec_capa *speed_fec_capa, 6837 unsigned int num) 6838 { 6839 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6840 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6841 uint16_t device_id = pci_dev->id.device_id; 6842 unsigned int capa_num; 6843 int ret; 6844 6845 capa_num = hns3_get_speed_capa_num(device_id); 6846 if (capa_num == 0) { 6847 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD", 6848 device_id); 6849 return -ENOTSUP; 6850 } 6851 6852 if (speed_fec_capa == NULL || num < capa_num) 6853 return capa_num; 6854 6855 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id); 6856 if (ret) 6857 return -ENOTSUP; 6858 6859 return capa_num; 6860 } 6861 6862 static int 6863 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state) 6864 { 6865 struct hns3_config_fec_cmd *req; 6866 struct hns3_cmd_desc desc; 6867 int ret; 6868 6869 /* 6870 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported 6871 * in device of link speed 6872 * below 10 Gbps. 6873 */ 6874 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) { 6875 *state = 0; 6876 return 0; 6877 } 6878 6879 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true); 6880 req = (struct hns3_config_fec_cmd *)desc.data; 6881 ret = hns3_cmd_send(hw, &desc, 1); 6882 if (ret) { 6883 hns3_err(hw, "get current fec auto state failed, ret = %d", 6884 ret); 6885 return ret; 6886 } 6887 6888 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B); 6889 return 0; 6890 } 6891 6892 static int 6893 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa) 6894 { 6895 struct hns3_sfp_info_cmd *resp; 6896 uint32_t tmp_fec_capa; 6897 uint8_t auto_state; 6898 struct hns3_cmd_desc desc; 6899 int ret; 6900 6901 /* 6902 * If link is down and AUTO is enabled, AUTO is returned, otherwise, 6903 * configured FEC mode is returned. 6904 * If link is up, current FEC mode is returned. 6905 */ 6906 if (hw->mac.link_status == ETH_LINK_DOWN) { 6907 ret = get_current_fec_auto_state(hw, &auto_state); 6908 if (ret) 6909 return ret; 6910 6911 if (auto_state == 0x1) { 6912 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 6913 return 0; 6914 } 6915 } 6916 6917 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 6918 resp = (struct hns3_sfp_info_cmd *)desc.data; 6919 resp->query_type = HNS3_ACTIVE_QUERY; 6920 6921 ret = hns3_cmd_send(hw, &desc, 1); 6922 if (ret == -EOPNOTSUPP) { 6923 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret); 6924 return ret; 6925 } else if (ret) { 6926 hns3_err(hw, "get FEC failed, ret = %d", ret); 6927 return ret; 6928 } 6929 6930 /* 6931 * FEC mode order defined in hns3 hardware is inconsistend with 6932 * that defined in the ethdev library. So the sequence needs 6933 * to be converted. 6934 */ 6935 switch (resp->active_fec) { 6936 case HNS3_HW_FEC_MODE_NOFEC: 6937 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6938 break; 6939 case HNS3_HW_FEC_MODE_BASER: 6940 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 6941 break; 6942 case HNS3_HW_FEC_MODE_RS: 6943 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 6944 break; 6945 default: 6946 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6947 break; 6948 } 6949 6950 *fec_capa = tmp_fec_capa; 6951 return 0; 6952 } 6953 6954 static int 6955 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 6956 { 6957 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6958 6959 return hns3_fec_get_internal(hw, fec_capa); 6960 } 6961 6962 static int 6963 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode) 6964 { 6965 struct hns3_config_fec_cmd *req; 6966 struct hns3_cmd_desc desc; 6967 int ret; 6968 6969 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false); 6970 6971 req = (struct hns3_config_fec_cmd *)desc.data; 6972 switch (mode) { 6973 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC): 6974 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6975 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF); 6976 break; 6977 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER): 6978 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6979 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER); 6980 break; 6981 case RTE_ETH_FEC_MODE_CAPA_MASK(RS): 6982 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6983 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS); 6984 break; 6985 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO): 6986 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1); 6987 break; 6988 default: 6989 return 0; 6990 } 6991 ret = hns3_cmd_send(hw, &desc, 1); 6992 if (ret) 6993 hns3_err(hw, "set fec mode failed, ret = %d", ret); 6994 6995 return ret; 6996 } 6997 6998 static uint32_t 6999 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa) 7000 { 7001 struct hns3_mac *mac = &hw->mac; 7002 uint32_t cur_capa; 7003 7004 switch (mac->link_speed) { 7005 case ETH_SPEED_NUM_10G: 7006 cur_capa = fec_capa[1].capa; 7007 break; 7008 case ETH_SPEED_NUM_25G: 7009 case ETH_SPEED_NUM_100G: 7010 case ETH_SPEED_NUM_200G: 7011 cur_capa = fec_capa[0].capa; 7012 break; 7013 default: 7014 cur_capa = 0; 7015 break; 7016 } 7017 7018 return cur_capa; 7019 } 7020 7021 static bool 7022 is_fec_mode_one_bit_set(uint32_t mode) 7023 { 7024 int cnt = 0; 7025 uint8_t i; 7026 7027 for (i = 0; i < sizeof(mode); i++) 7028 if (mode >> i & 0x1) 7029 cnt++; 7030 7031 return cnt == 1 ? true : false; 7032 } 7033 7034 static int 7035 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode) 7036 { 7037 #define FEC_CAPA_NUM 2 7038 struct hns3_adapter *hns = dev->data->dev_private; 7039 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 7040 struct hns3_pf *pf = &hns->pf; 7041 7042 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM]; 7043 uint32_t cur_capa; 7044 uint32_t num = FEC_CAPA_NUM; 7045 int ret; 7046 7047 ret = hns3_fec_get_capability(dev, fec_capa, num); 7048 if (ret < 0) 7049 return ret; 7050 7051 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */ 7052 if (!is_fec_mode_one_bit_set(mode)) { 7053 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, " 7054 "FEC mode should be only one bit set", mode); 7055 return -EINVAL; 7056 } 7057 7058 /* 7059 * Check whether the configured mode is within the FEC capability. 7060 * If not, the configured mode will not be supported. 7061 */ 7062 cur_capa = get_current_speed_fec_cap(hw, fec_capa); 7063 if (!(cur_capa & mode)) { 7064 hns3_err(hw, "unsupported FEC mode = 0x%x", mode); 7065 return -EINVAL; 7066 } 7067 7068 rte_spinlock_lock(&hw->lock); 7069 ret = hns3_set_fec_hw(hw, mode); 7070 if (ret) { 7071 rte_spinlock_unlock(&hw->lock); 7072 return ret; 7073 } 7074 7075 pf->fec_mode = mode; 7076 rte_spinlock_unlock(&hw->lock); 7077 7078 return 0; 7079 } 7080 7081 static int 7082 hns3_restore_fec(struct hns3_hw *hw) 7083 { 7084 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 7085 struct hns3_pf *pf = &hns->pf; 7086 uint32_t mode = pf->fec_mode; 7087 int ret; 7088 7089 ret = hns3_set_fec_hw(hw, mode); 7090 if (ret) 7091 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d", 7092 mode, ret); 7093 7094 return ret; 7095 } 7096 7097 static int 7098 hns3_query_dev_fec_info(struct hns3_hw *hw) 7099 { 7100 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 7101 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns); 7102 int ret; 7103 7104 ret = hns3_fec_get_internal(hw, &pf->fec_mode); 7105 if (ret) 7106 hns3_err(hw, "query device FEC info failed, ret = %d", ret); 7107 7108 return ret; 7109 } 7110 7111 static bool 7112 hns3_optical_module_existed(struct hns3_hw *hw) 7113 { 7114 struct hns3_cmd_desc desc; 7115 bool existed; 7116 int ret; 7117 7118 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true); 7119 ret = hns3_cmd_send(hw, &desc, 1); 7120 if (ret) { 7121 hns3_err(hw, 7122 "fail to get optical module exist state, ret = %d.\n", 7123 ret); 7124 return false; 7125 } 7126 existed = !!desc.data[0]; 7127 7128 return existed; 7129 } 7130 7131 static int 7132 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset, 7133 uint32_t len, uint8_t *data) 7134 { 7135 #define HNS3_SFP_INFO_CMD_NUM 6 7136 #define HNS3_SFP_INFO_MAX_LEN \ 7137 (HNS3_SFP_INFO_BD0_LEN + \ 7138 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN) 7139 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM]; 7140 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0; 7141 uint16_t read_len; 7142 uint16_t copy_len; 7143 int ret; 7144 int i; 7145 7146 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) { 7147 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM, 7148 true); 7149 if (i < HNS3_SFP_INFO_CMD_NUM - 1) 7150 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 7151 } 7152 7153 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data; 7154 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset); 7155 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN); 7156 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len); 7157 7158 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM); 7159 if (ret) { 7160 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n", 7161 ret); 7162 return ret; 7163 } 7164 7165 /* The data format in BD0 is different with the others. */ 7166 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN); 7167 memcpy(data, sfp_info_bd0->data, copy_len); 7168 read_len = copy_len; 7169 7170 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) { 7171 if (read_len >= len) 7172 break; 7173 7174 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN); 7175 memcpy(data + read_len, desc[i].data, copy_len); 7176 read_len += copy_len; 7177 } 7178 7179 return (int)read_len; 7180 } 7181 7182 static int 7183 hns3_get_module_eeprom(struct rte_eth_dev *dev, 7184 struct rte_dev_eeprom_info *info) 7185 { 7186 struct hns3_adapter *hns = dev->data->dev_private; 7187 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 7188 uint32_t offset = info->offset; 7189 uint32_t len = info->length; 7190 uint8_t *data = info->data; 7191 uint32_t read_len = 0; 7192 7193 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER) 7194 return -ENOTSUP; 7195 7196 if (!hns3_optical_module_existed(hw)) { 7197 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n"); 7198 return -EIO; 7199 } 7200 7201 while (read_len < len) { 7202 int ret; 7203 ret = hns3_get_module_eeprom_data(hw, offset + read_len, 7204 len - read_len, 7205 data + read_len); 7206 if (ret < 0) 7207 return -EIO; 7208 read_len += ret; 7209 } 7210 7211 return 0; 7212 } 7213 7214 static int 7215 hns3_get_module_info(struct rte_eth_dev *dev, 7216 struct rte_eth_dev_module_info *modinfo) 7217 { 7218 #define HNS3_SFF8024_ID_SFP 0x03 7219 #define HNS3_SFF8024_ID_QSFP_8438 0x0c 7220 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d 7221 #define HNS3_SFF8024_ID_QSFP28_8636 0x11 7222 #define HNS3_SFF_8636_V1_3 0x03 7223 struct hns3_adapter *hns = dev->data->dev_private; 7224 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 7225 struct rte_dev_eeprom_info info; 7226 struct hns3_sfp_type sfp_type; 7227 int ret; 7228 7229 memset(&sfp_type, 0, sizeof(sfp_type)); 7230 memset(&info, 0, sizeof(info)); 7231 info.data = (uint8_t *)&sfp_type; 7232 info.length = sizeof(sfp_type); 7233 ret = hns3_get_module_eeprom(dev, &info); 7234 if (ret) 7235 return ret; 7236 7237 switch (sfp_type.type) { 7238 case HNS3_SFF8024_ID_SFP: 7239 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7240 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7241 break; 7242 case HNS3_SFF8024_ID_QSFP_8438: 7243 modinfo->type = RTE_ETH_MODULE_SFF_8436; 7244 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 7245 break; 7246 case HNS3_SFF8024_ID_QSFP_8436_8636: 7247 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) { 7248 modinfo->type = RTE_ETH_MODULE_SFF_8436; 7249 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 7250 } else { 7251 modinfo->type = RTE_ETH_MODULE_SFF_8636; 7252 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 7253 } 7254 break; 7255 case HNS3_SFF8024_ID_QSFP28_8636: 7256 modinfo->type = RTE_ETH_MODULE_SFF_8636; 7257 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 7258 break; 7259 default: 7260 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n", 7261 sfp_type.type, sfp_type.ext_type); 7262 return -EINVAL; 7263 } 7264 7265 return 0; 7266 } 7267 7268 void 7269 hns3_clock_gettime(struct timeval *tv) 7270 { 7271 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */ 7272 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW 7273 #else 7274 #define CLOCK_TYPE CLOCK_MONOTONIC 7275 #endif 7276 #define NSEC_TO_USEC_DIV 1000 7277 7278 struct timespec spec; 7279 (void)clock_gettime(CLOCK_TYPE, &spec); 7280 7281 tv->tv_sec = spec.tv_sec; 7282 tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV; 7283 } 7284 7285 uint64_t 7286 hns3_clock_calctime_ms(struct timeval *tv) 7287 { 7288 return (uint64_t)tv->tv_sec * MSEC_PER_SEC + 7289 tv->tv_usec / USEC_PER_MSEC; 7290 } 7291 7292 uint64_t 7293 hns3_clock_gettime_ms(void) 7294 { 7295 struct timeval tv; 7296 7297 hns3_clock_gettime(&tv); 7298 return hns3_clock_calctime_ms(&tv); 7299 } 7300 7301 static int 7302 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) 7303 { 7304 uint32_t hint = HNS3_IO_FUNC_HINT_NONE; 7305 7306 RTE_SET_USED(key); 7307 7308 if (strcmp(value, "vec") == 0) 7309 hint = HNS3_IO_FUNC_HINT_VEC; 7310 else if (strcmp(value, "sve") == 0) 7311 hint = HNS3_IO_FUNC_HINT_SVE; 7312 else if (strcmp(value, "simple") == 0) 7313 hint = HNS3_IO_FUNC_HINT_SIMPLE; 7314 else if (strcmp(value, "common") == 0) 7315 hint = HNS3_IO_FUNC_HINT_COMMON; 7316 7317 /* If the hint is valid then update output parameters */ 7318 if (hint != HNS3_IO_FUNC_HINT_NONE) 7319 *(uint32_t *)extra_args = hint; 7320 7321 return 0; 7322 } 7323 7324 static const char * 7325 hns3_get_io_hint_func_name(uint32_t hint) 7326 { 7327 switch (hint) { 7328 case HNS3_IO_FUNC_HINT_VEC: 7329 return "vec"; 7330 case HNS3_IO_FUNC_HINT_SVE: 7331 return "sve"; 7332 case HNS3_IO_FUNC_HINT_SIMPLE: 7333 return "simple"; 7334 case HNS3_IO_FUNC_HINT_COMMON: 7335 return "common"; 7336 default: 7337 return "none"; 7338 } 7339 } 7340 7341 static int 7342 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args) 7343 { 7344 uint64_t val; 7345 7346 RTE_SET_USED(key); 7347 7348 val = strtoull(value, NULL, 16); 7349 *(uint64_t *)extra_args = val; 7350 7351 return 0; 7352 } 7353 7354 void 7355 hns3_parse_devargs(struct rte_eth_dev *dev) 7356 { 7357 struct hns3_adapter *hns = dev->data->dev_private; 7358 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; 7359 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; 7360 struct hns3_hw *hw = &hns->hw; 7361 uint64_t dev_caps_mask = 0; 7362 struct rte_kvargs *kvlist; 7363 7364 if (dev->device->devargs == NULL) 7365 return; 7366 7367 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); 7368 if (!kvlist) 7369 return; 7370 7371 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, 7372 &hns3_parse_io_hint_func, &rx_func_hint); 7373 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, 7374 &hns3_parse_io_hint_func, &tx_func_hint); 7375 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK, 7376 &hns3_parse_dev_caps_mask, &dev_caps_mask); 7377 rte_kvargs_free(kvlist); 7378 7379 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) 7380 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, 7381 hns3_get_io_hint_func_name(rx_func_hint)); 7382 hns->rx_func_hint = rx_func_hint; 7383 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) 7384 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, 7385 hns3_get_io_hint_func_name(tx_func_hint)); 7386 hns->tx_func_hint = tx_func_hint; 7387 7388 if (dev_caps_mask != 0) 7389 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".", 7390 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask); 7391 hns->dev_caps_mask = dev_caps_mask; 7392 } 7393 7394 static const struct eth_dev_ops hns3_eth_dev_ops = { 7395 .dev_configure = hns3_dev_configure, 7396 .dev_start = hns3_dev_start, 7397 .dev_stop = hns3_dev_stop, 7398 .dev_close = hns3_dev_close, 7399 .promiscuous_enable = hns3_dev_promiscuous_enable, 7400 .promiscuous_disable = hns3_dev_promiscuous_disable, 7401 .allmulticast_enable = hns3_dev_allmulticast_enable, 7402 .allmulticast_disable = hns3_dev_allmulticast_disable, 7403 .mtu_set = hns3_dev_mtu_set, 7404 .stats_get = hns3_stats_get, 7405 .stats_reset = hns3_stats_reset, 7406 .xstats_get = hns3_dev_xstats_get, 7407 .xstats_get_names = hns3_dev_xstats_get_names, 7408 .xstats_reset = hns3_dev_xstats_reset, 7409 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 7410 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 7411 .dev_infos_get = hns3_dev_infos_get, 7412 .fw_version_get = hns3_fw_version_get, 7413 .rx_queue_setup = hns3_rx_queue_setup, 7414 .tx_queue_setup = hns3_tx_queue_setup, 7415 .rx_queue_release = hns3_dev_rx_queue_release, 7416 .tx_queue_release = hns3_dev_tx_queue_release, 7417 .rx_queue_start = hns3_dev_rx_queue_start, 7418 .rx_queue_stop = hns3_dev_rx_queue_stop, 7419 .tx_queue_start = hns3_dev_tx_queue_start, 7420 .tx_queue_stop = hns3_dev_tx_queue_stop, 7421 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 7422 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 7423 .rxq_info_get = hns3_rxq_info_get, 7424 .txq_info_get = hns3_txq_info_get, 7425 .rx_burst_mode_get = hns3_rx_burst_mode_get, 7426 .tx_burst_mode_get = hns3_tx_burst_mode_get, 7427 .flow_ctrl_get = hns3_flow_ctrl_get, 7428 .flow_ctrl_set = hns3_flow_ctrl_set, 7429 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 7430 .mac_addr_add = hns3_add_mac_addr, 7431 .mac_addr_remove = hns3_remove_mac_addr, 7432 .mac_addr_set = hns3_set_default_mac_addr, 7433 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 7434 .link_update = hns3_dev_link_update, 7435 .dev_set_link_up = hns3_dev_set_link_up, 7436 .dev_set_link_down = hns3_dev_set_link_down, 7437 .rss_hash_update = hns3_dev_rss_hash_update, 7438 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 7439 .reta_update = hns3_dev_rss_reta_update, 7440 .reta_query = hns3_dev_rss_reta_query, 7441 .flow_ops_get = hns3_dev_flow_ops_get, 7442 .vlan_filter_set = hns3_vlan_filter_set, 7443 .vlan_tpid_set = hns3_vlan_tpid_set, 7444 .vlan_offload_set = hns3_vlan_offload_set, 7445 .vlan_pvid_set = hns3_vlan_pvid_set, 7446 .get_reg = hns3_get_regs, 7447 .get_module_info = hns3_get_module_info, 7448 .get_module_eeprom = hns3_get_module_eeprom, 7449 .get_dcb_info = hns3_get_dcb_info, 7450 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 7451 .fec_get_capability = hns3_fec_get_capability, 7452 .fec_get = hns3_fec_get, 7453 .fec_set = hns3_fec_set, 7454 .tm_ops_get = hns3_tm_ops_get, 7455 .tx_done_cleanup = hns3_tx_done_cleanup, 7456 .timesync_enable = hns3_timesync_enable, 7457 .timesync_disable = hns3_timesync_disable, 7458 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp, 7459 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp, 7460 .timesync_adjust_time = hns3_timesync_adjust_time, 7461 .timesync_read_time = hns3_timesync_read_time, 7462 .timesync_write_time = hns3_timesync_write_time, 7463 }; 7464 7465 static const struct hns3_reset_ops hns3_reset_ops = { 7466 .reset_service = hns3_reset_service, 7467 .stop_service = hns3_stop_service, 7468 .prepare_reset = hns3_prepare_reset, 7469 .wait_hardware_ready = hns3_wait_hardware_ready, 7470 .reinit_dev = hns3_reinit_dev, 7471 .restore_conf = hns3_restore_conf, 7472 .start_service = hns3_start_service, 7473 }; 7474 7475 static int 7476 hns3_dev_init(struct rte_eth_dev *eth_dev) 7477 { 7478 struct hns3_adapter *hns = eth_dev->data->dev_private; 7479 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 7480 struct rte_ether_addr *eth_addr; 7481 struct hns3_hw *hw = &hns->hw; 7482 int ret; 7483 7484 PMD_INIT_FUNC_TRACE(); 7485 7486 hns3_flow_init(eth_dev); 7487 7488 hns3_set_rxtx_function(eth_dev); 7489 eth_dev->dev_ops = &hns3_eth_dev_ops; 7490 eth_dev->rx_queue_count = hns3_rx_queue_count; 7491 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 7492 ret = hns3_mp_init_secondary(); 7493 if (ret) { 7494 PMD_INIT_LOG(ERR, "Failed to init for secondary " 7495 "process, ret = %d", ret); 7496 goto err_mp_init_secondary; 7497 } 7498 hw->secondary_cnt++; 7499 hns3_tx_push_init(eth_dev); 7500 return 0; 7501 } 7502 7503 ret = hns3_mp_init_primary(); 7504 if (ret) { 7505 PMD_INIT_LOG(ERR, 7506 "Failed to init for primary process, ret = %d", 7507 ret); 7508 goto err_mp_init_primary; 7509 } 7510 7511 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 7512 hns->is_vf = false; 7513 hw->data = eth_dev->data; 7514 hns3_parse_devargs(eth_dev); 7515 7516 /* 7517 * Set default max packet size according to the mtu 7518 * default vale in DPDK frame. 7519 */ 7520 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 7521 7522 ret = hns3_reset_init(hw); 7523 if (ret) 7524 goto err_init_reset; 7525 hw->reset.ops = &hns3_reset_ops; 7526 7527 ret = hns3_init_pf(eth_dev); 7528 if (ret) { 7529 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 7530 goto err_init_pf; 7531 } 7532 7533 /* Allocate memory for storing MAC addresses */ 7534 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac", 7535 sizeof(struct rte_ether_addr) * 7536 HNS3_UC_MACADDR_NUM, 0); 7537 if (eth_dev->data->mac_addrs == NULL) { 7538 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 7539 "to store MAC addresses", 7540 sizeof(struct rte_ether_addr) * 7541 HNS3_UC_MACADDR_NUM); 7542 ret = -ENOMEM; 7543 goto err_rte_zmalloc; 7544 } 7545 7546 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 7547 if (!rte_is_valid_assigned_ether_addr(eth_addr)) { 7548 rte_eth_random_addr(hw->mac.mac_addr); 7549 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 7550 (struct rte_ether_addr *)hw->mac.mac_addr); 7551 hns3_warn(hw, "default mac_addr from firmware is an invalid " 7552 "unicast address, using random MAC address %s", 7553 mac_str); 7554 } 7555 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 7556 ð_dev->data->mac_addrs[0]); 7557 7558 hw->adapter_state = HNS3_NIC_INITIALIZED; 7559 7560 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 7561 SCHEDULE_PENDING) { 7562 hns3_err(hw, "Reschedule reset service after dev_init"); 7563 hns3_schedule_reset(hns); 7564 } else { 7565 /* IMP will wait ready flag before reset */ 7566 hns3_notify_reset_ready(hw, false); 7567 } 7568 7569 hns3_info(hw, "hns3 dev initialization successful!"); 7570 return 0; 7571 7572 err_rte_zmalloc: 7573 hns3_uninit_pf(eth_dev); 7574 7575 err_init_pf: 7576 rte_free(hw->reset.wait_data); 7577 7578 err_init_reset: 7579 hns3_mp_uninit_primary(); 7580 7581 err_mp_init_primary: 7582 err_mp_init_secondary: 7583 eth_dev->dev_ops = NULL; 7584 eth_dev->rx_pkt_burst = NULL; 7585 eth_dev->rx_descriptor_status = NULL; 7586 eth_dev->tx_pkt_burst = NULL; 7587 eth_dev->tx_pkt_prepare = NULL; 7588 eth_dev->tx_descriptor_status = NULL; 7589 return ret; 7590 } 7591 7592 static int 7593 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 7594 { 7595 struct hns3_adapter *hns = eth_dev->data->dev_private; 7596 struct hns3_hw *hw = &hns->hw; 7597 7598 PMD_INIT_FUNC_TRACE(); 7599 7600 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 7601 return 0; 7602 7603 if (hw->adapter_state < HNS3_NIC_CLOSING) 7604 hns3_dev_close(eth_dev); 7605 7606 hw->adapter_state = HNS3_NIC_REMOVED; 7607 return 0; 7608 } 7609 7610 static int 7611 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 7612 struct rte_pci_device *pci_dev) 7613 { 7614 return rte_eth_dev_pci_generic_probe(pci_dev, 7615 sizeof(struct hns3_adapter), 7616 hns3_dev_init); 7617 } 7618 7619 static int 7620 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 7621 { 7622 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 7623 } 7624 7625 static const struct rte_pci_id pci_id_hns3_map[] = { 7626 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 7627 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 7628 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 7629 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 7630 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 7631 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, 7632 { .vendor_id = 0, }, /* sentinel */ 7633 }; 7634 7635 static struct rte_pci_driver rte_hns3_pmd = { 7636 .id_table = pci_id_hns3_map, 7637 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 7638 .probe = eth_hns3_pci_probe, 7639 .remove = eth_hns3_pci_remove, 7640 }; 7641 7642 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 7643 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 7644 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 7645 RTE_PMD_REGISTER_PARAM_STRING(net_hns3, 7646 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " 7647 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common " 7648 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "); 7649 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE); 7650 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE); 7651