1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <rte_alarm.h> 6 #include <bus_pci_driver.h> 7 #include <ethdev_pci.h> 8 9 #include "hns3_common.h" 10 #include "hns3_dump.h" 11 #include "hns3_logs.h" 12 #include "hns3_rxtx.h" 13 #include "hns3_intr.h" 14 #include "hns3_regs.h" 15 #include "hns3_dcb.h" 16 #include "hns3_mp.h" 17 #include "hns3_flow.h" 18 #include "hns3_ethdev.h" 19 20 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 21 #define HNS3_SERVICE_QUICK_INTERVAL 10 22 #define HNS3_INVALID_PVID 0xFFFF 23 24 #define HNS3_FILTER_TYPE_VF 0 25 #define HNS3_FILTER_TYPE_PORT 1 26 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 27 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 28 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 29 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 30 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 31 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 32 | HNS3_FILTER_FE_ROCE_EGRESS_B) 33 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 34 | HNS3_FILTER_FE_ROCE_INGRESS_B) 35 36 /* Reset related Registers */ 37 #define HNS3_GLOBAL_RESET_BIT 0 38 #define HNS3_CORE_RESET_BIT 1 39 #define HNS3_IMP_RESET_BIT 2 40 #define HNS3_FUN_RST_ING_B 0 41 42 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 43 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U 44 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U 45 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U 46 47 #define HNS3_RESET_WAIT_MS 100 48 #define HNS3_RESET_WAIT_CNT 200 49 50 /* FEC mode order defined in HNS3 hardware */ 51 #define HNS3_HW_FEC_MODE_NOFEC 0 52 #define HNS3_HW_FEC_MODE_BASER 1 53 #define HNS3_HW_FEC_MODE_RS 2 54 55 enum hns3_evt_cause { 56 HNS3_VECTOR0_EVENT_RST, 57 HNS3_VECTOR0_EVENT_MBX, 58 HNS3_VECTOR0_EVENT_ERR, 59 HNS3_VECTOR0_EVENT_PTP, 60 HNS3_VECTOR0_EVENT_OTHER, 61 }; 62 63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = { 64 { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 65 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 66 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 67 68 { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 69 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 70 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 71 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 72 73 { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 74 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 75 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 76 77 { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 78 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 79 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 80 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 81 82 { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 83 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 84 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 85 86 { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 87 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 88 RTE_ETH_FEC_MODE_CAPA_MASK(RS) } 89 }; 90 91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 92 uint64_t *levels); 93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 95 int on); 96 static int hns3_update_link_info(struct rte_eth_dev *eth_dev); 97 static bool hns3_update_link_status(struct hns3_hw *hw); 98 99 static int hns3_add_mc_mac_addr(struct hns3_hw *hw, 100 struct rte_ether_addr *mac_addr); 101 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw, 102 struct rte_ether_addr *mac_addr); 103 static int hns3_restore_fec(struct hns3_hw *hw); 104 static int hns3_query_dev_fec_info(struct hns3_hw *hw); 105 static int hns3_do_stop(struct hns3_adapter *hns); 106 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds); 107 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable); 108 109 110 static void 111 hns3_pf_disable_irq0(struct hns3_hw *hw) 112 { 113 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 114 } 115 116 static void 117 hns3_pf_enable_irq0(struct hns3_hw *hw) 118 { 119 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 120 } 121 122 static enum hns3_evt_cause 123 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay, 124 uint32_t *vec_val) 125 { 126 struct hns3_hw *hw = &hns->hw; 127 128 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 129 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 130 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 131 if (!is_delay) { 132 hw->reset.stats.imp_cnt++; 133 hns3_warn(hw, "IMP reset detected, clear reset status"); 134 } else { 135 hns3_schedule_delayed_reset(hns); 136 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 137 } 138 139 return HNS3_VECTOR0_EVENT_RST; 140 } 141 142 static enum hns3_evt_cause 143 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay, 144 uint32_t *vec_val) 145 { 146 struct hns3_hw *hw = &hns->hw; 147 148 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 149 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 150 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 151 if (!is_delay) { 152 hw->reset.stats.global_cnt++; 153 hns3_warn(hw, "Global reset detected, clear reset status"); 154 } else { 155 hns3_schedule_delayed_reset(hns); 156 hns3_warn(hw, 157 "Global reset detected, don't clear reset status"); 158 } 159 160 return HNS3_VECTOR0_EVENT_RST; 161 } 162 163 static enum hns3_evt_cause 164 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 165 { 166 struct hns3_hw *hw = &hns->hw; 167 uint32_t vector0_int_stats; 168 uint32_t cmdq_src_val; 169 uint32_t hw_err_src_reg; 170 uint32_t val; 171 enum hns3_evt_cause ret; 172 bool is_delay; 173 174 /* fetch the events from their corresponding regs */ 175 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 176 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 177 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 178 179 is_delay = clearval == NULL ? true : false; 180 /* 181 * Assumption: If by any chance reset and mailbox events are reported 182 * together then we will only process reset event and defer the 183 * processing of the mailbox events. Since, we would have not cleared 184 * RX CMDQ event this time we would receive again another interrupt 185 * from H/W just for the mailbox. 186 */ 187 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 188 ret = hns3_proc_imp_reset_event(hns, is_delay, &val); 189 goto out; 190 } 191 192 /* Global reset */ 193 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 194 ret = hns3_proc_global_reset_event(hns, is_delay, &val); 195 goto out; 196 } 197 198 /* Check for vector0 1588 event source */ 199 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) { 200 val = BIT(HNS3_VECTOR0_1588_INT_B); 201 ret = HNS3_VECTOR0_EVENT_PTP; 202 goto out; 203 } 204 205 /* check for vector0 msix event source */ 206 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || 207 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { 208 val = vector0_int_stats | hw_err_src_reg; 209 ret = HNS3_VECTOR0_EVENT_ERR; 210 goto out; 211 } 212 213 /* check for vector0 mailbox(=CMDQ RX) event source */ 214 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 215 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 216 val = cmdq_src_val; 217 ret = HNS3_VECTOR0_EVENT_MBX; 218 goto out; 219 } 220 221 val = vector0_int_stats; 222 ret = HNS3_VECTOR0_EVENT_OTHER; 223 out: 224 225 if (clearval) 226 *clearval = val; 227 return ret; 228 } 229 230 static void 231 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 232 { 233 if (event_type == HNS3_VECTOR0_EVENT_RST || 234 event_type == HNS3_VECTOR0_EVENT_PTP) 235 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 236 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 237 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 238 } 239 240 static void 241 hns3_clear_all_event_cause(struct hns3_hw *hw) 242 { 243 uint32_t vector0_int_stats; 244 245 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 246 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 247 hns3_warn(hw, "Probe during IMP reset interrupt"); 248 249 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 250 hns3_warn(hw, "Probe during Global reset interrupt"); 251 252 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 253 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 254 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 255 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 256 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 257 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP, 258 BIT(HNS3_VECTOR0_1588_INT_B)); 259 } 260 261 static void 262 hns3_handle_mac_tnl(struct hns3_hw *hw) 263 { 264 struct hns3_cmd_desc desc; 265 uint32_t status; 266 int ret; 267 268 /* query and clear mac tnl interrupt */ 269 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true); 270 ret = hns3_cmd_send(hw, &desc, 1); 271 if (ret) { 272 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret); 273 return; 274 } 275 276 status = rte_le_to_cpu_32(desc.data[0]); 277 if (status) { 278 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status); 279 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT, 280 false); 281 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR); 282 ret = hns3_cmd_send(hw, &desc, 1); 283 if (ret) 284 hns3_err(hw, "failed to clear mac tnl int, ret = %d.", 285 ret); 286 } 287 } 288 289 static void 290 hns3_interrupt_handler(void *param) 291 { 292 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 293 struct hns3_adapter *hns = dev->data->dev_private; 294 struct hns3_hw *hw = &hns->hw; 295 enum hns3_evt_cause event_cause; 296 uint32_t clearval = 0; 297 uint32_t vector0_int; 298 uint32_t ras_int; 299 uint32_t cmdq_int; 300 301 /* Disable interrupt */ 302 hns3_pf_disable_irq0(hw); 303 304 event_cause = hns3_check_event_cause(hns, &clearval); 305 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 306 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 307 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 308 hns3_clear_event_cause(hw, event_cause, clearval); 309 /* vector 0 interrupt is shared with reset and mailbox source events. */ 310 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 311 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x " 312 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 313 vector0_int, ras_int, cmdq_int); 314 hns3_handle_mac_tnl(hw); 315 hns3_handle_error(hns); 316 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { 317 hns3_warn(hw, "received reset interrupt"); 318 hns3_schedule_reset(hns); 319 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) { 320 hns3_dev_handle_mbx_msg(hw); 321 } else if (event_cause != HNS3_VECTOR0_EVENT_PTP) { 322 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x " 323 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 324 vector0_int, ras_int, cmdq_int); 325 } 326 327 /* Enable interrupt if it is not cause by reset */ 328 hns3_pf_enable_irq0(hw); 329 } 330 331 static int 332 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 333 { 334 #define HNS3_VLAN_ID_OFFSET_STEP 160 335 #define HNS3_VLAN_BYTE_SIZE 8 336 struct hns3_vlan_filter_pf_cfg_cmd *req; 337 struct hns3_hw *hw = &hns->hw; 338 uint8_t vlan_offset_byte_val; 339 struct hns3_cmd_desc desc; 340 uint8_t vlan_offset_byte; 341 uint8_t vlan_offset_base; 342 int ret; 343 344 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 345 346 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 347 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 348 HNS3_VLAN_BYTE_SIZE; 349 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 350 351 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 352 req->vlan_offset = vlan_offset_base; 353 req->vlan_cfg = on ? 0 : 1; 354 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 355 356 ret = hns3_cmd_send(hw, &desc, 1); 357 if (ret) 358 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 359 vlan_id, ret); 360 361 return ret; 362 } 363 364 static void 365 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 366 { 367 struct hns3_user_vlan_table *vlan_entry; 368 struct hns3_pf *pf = &hns->pf; 369 370 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 371 if (vlan_entry->vlan_id == vlan_id) { 372 if (vlan_entry->hd_tbl_status) 373 hns3_set_port_vlan_filter(hns, vlan_id, 0); 374 LIST_REMOVE(vlan_entry, next); 375 rte_free(vlan_entry); 376 break; 377 } 378 } 379 } 380 381 static void 382 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 383 bool writen_to_tbl) 384 { 385 struct hns3_user_vlan_table *vlan_entry; 386 struct hns3_hw *hw = &hns->hw; 387 struct hns3_pf *pf = &hns->pf; 388 389 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 390 if (vlan_entry->vlan_id == vlan_id) 391 return; 392 } 393 394 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 395 if (vlan_entry == NULL) { 396 hns3_err(hw, "Failed to malloc hns3 vlan table"); 397 return; 398 } 399 400 vlan_entry->hd_tbl_status = writen_to_tbl; 401 vlan_entry->vlan_id = vlan_id; 402 403 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 404 } 405 406 static int 407 hns3_restore_vlan_table(struct hns3_adapter *hns) 408 { 409 struct hns3_user_vlan_table *vlan_entry; 410 struct hns3_hw *hw = &hns->hw; 411 struct hns3_pf *pf = &hns->pf; 412 uint16_t vlan_id; 413 int ret = 0; 414 415 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 416 return hns3_vlan_pvid_configure(hns, 417 hw->port_base_vlan_cfg.pvid, 1); 418 419 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 420 if (vlan_entry->hd_tbl_status) { 421 vlan_id = vlan_entry->vlan_id; 422 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 423 if (ret) 424 break; 425 } 426 } 427 428 return ret; 429 } 430 431 static int 432 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 433 { 434 struct hns3_hw *hw = &hns->hw; 435 bool writen_to_tbl = false; 436 int ret = 0; 437 438 /* 439 * When vlan filter is enabled, hardware regards packets without vlan 440 * as packets with vlan 0. So, to receive packets without vlan, vlan id 441 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter. 442 */ 443 if (on == 0 && vlan_id == 0) 444 return 0; 445 446 /* 447 * When port base vlan enabled, we use port base vlan as the vlan 448 * filter condition. In this case, we don't update vlan filter table 449 * when user add new vlan or remove exist vlan, just update the 450 * vlan list. The vlan id in vlan list will be written in vlan filter 451 * table until port base vlan disabled 452 */ 453 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 454 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 455 writen_to_tbl = true; 456 } 457 458 if (ret == 0) { 459 if (on) 460 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 461 else 462 hns3_rm_dev_vlan_table(hns, vlan_id); 463 } 464 return ret; 465 } 466 467 static int 468 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 469 { 470 struct hns3_adapter *hns = dev->data->dev_private; 471 struct hns3_hw *hw = &hns->hw; 472 int ret; 473 474 rte_spinlock_lock(&hw->lock); 475 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 476 rte_spinlock_unlock(&hw->lock); 477 return ret; 478 } 479 480 static int 481 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 482 uint16_t tpid) 483 { 484 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 485 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 486 struct hns3_hw *hw = &hns->hw; 487 struct hns3_cmd_desc desc; 488 int ret; 489 490 if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER && 491 vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) { 492 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 493 return -EINVAL; 494 } 495 496 if (tpid != RTE_ETHER_TYPE_VLAN) { 497 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 498 return -EINVAL; 499 } 500 501 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 502 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 503 504 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) { 505 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 506 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 507 } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) { 508 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 509 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 510 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 511 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 512 } 513 514 ret = hns3_cmd_send(hw, &desc, 1); 515 if (ret) { 516 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 517 ret); 518 return ret; 519 } 520 521 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 522 523 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 524 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 525 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 526 527 ret = hns3_cmd_send(hw, &desc, 1); 528 if (ret) 529 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 530 ret); 531 return ret; 532 } 533 534 static int 535 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 536 uint16_t tpid) 537 { 538 struct hns3_adapter *hns = dev->data->dev_private; 539 struct hns3_hw *hw = &hns->hw; 540 int ret; 541 542 rte_spinlock_lock(&hw->lock); 543 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 544 rte_spinlock_unlock(&hw->lock); 545 return ret; 546 } 547 548 static int 549 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 550 struct hns3_rx_vtag_cfg *vcfg) 551 { 552 struct hns3_vport_vtag_rx_cfg_cmd *req; 553 struct hns3_hw *hw = &hns->hw; 554 struct hns3_cmd_desc desc; 555 uint16_t vport_id; 556 uint8_t bitmap; 557 int ret; 558 559 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 560 561 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 562 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 563 vcfg->strip_tag1_en ? 1 : 0); 564 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 565 vcfg->strip_tag2_en ? 1 : 0); 566 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 567 vcfg->vlan1_vlan_prionly ? 1 : 0); 568 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 569 vcfg->vlan2_vlan_prionly ? 1 : 0); 570 571 /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */ 572 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B, 573 vcfg->strip_tag1_discard_en ? 1 : 0); 574 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B, 575 vcfg->strip_tag2_discard_en ? 1 : 0); 576 /* 577 * In current version VF is not supported when PF is driven by DPDK 578 * driver, just need to configure parameters for PF vport. 579 */ 580 vport_id = HNS3_PF_FUNC_ID; 581 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 582 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 583 req->vf_bitmap[req->vf_offset] = bitmap; 584 585 ret = hns3_cmd_send(hw, &desc, 1); 586 if (ret) 587 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 588 return ret; 589 } 590 591 static int 592 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 593 { 594 struct hns3_rx_vtag_cfg rxvlan_cfg; 595 struct hns3_hw *hw = &hns->hw; 596 int ret; 597 598 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 599 rxvlan_cfg.strip_tag1_en = false; 600 rxvlan_cfg.strip_tag2_en = enable; 601 rxvlan_cfg.strip_tag2_discard_en = false; 602 } else { 603 rxvlan_cfg.strip_tag1_en = enable; 604 rxvlan_cfg.strip_tag2_en = true; 605 rxvlan_cfg.strip_tag2_discard_en = true; 606 } 607 608 rxvlan_cfg.strip_tag1_discard_en = false; 609 rxvlan_cfg.vlan1_vlan_prionly = false; 610 rxvlan_cfg.vlan2_vlan_prionly = false; 611 rxvlan_cfg.rx_vlan_offload_en = enable; 612 613 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 614 if (ret) { 615 hns3_err(hw, "%s strip rx vtag failed, ret = %d.", 616 enable ? "enable" : "disable", ret); 617 return ret; 618 } 619 620 memcpy(&hns->pf.vtag_config.rx_vcfg, &rxvlan_cfg, 621 sizeof(struct hns3_rx_vtag_cfg)); 622 623 return ret; 624 } 625 626 static int 627 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 628 uint8_t fe_type, bool filter_en, uint8_t vf_id) 629 { 630 struct hns3_vlan_filter_ctrl_cmd *req; 631 struct hns3_cmd_desc desc; 632 int ret; 633 634 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 635 636 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 637 req->vlan_type = vlan_type; 638 req->vlan_fe = filter_en ? fe_type : 0; 639 req->vf_id = vf_id; 640 641 ret = hns3_cmd_send(hw, &desc, 1); 642 if (ret) 643 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 644 645 return ret; 646 } 647 648 static int 649 hns3_vlan_filter_init(struct hns3_adapter *hns) 650 { 651 struct hns3_hw *hw = &hns->hw; 652 int ret; 653 654 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 655 HNS3_FILTER_FE_EGRESS, false, 656 HNS3_PF_FUNC_ID); 657 if (ret) { 658 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 659 return ret; 660 } 661 662 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 663 HNS3_FILTER_FE_INGRESS, false, 664 HNS3_PF_FUNC_ID); 665 if (ret) 666 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 667 668 return ret; 669 } 670 671 static int 672 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 673 { 674 struct hns3_hw *hw = &hns->hw; 675 int ret; 676 677 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 678 HNS3_FILTER_FE_INGRESS, enable, 679 HNS3_PF_FUNC_ID); 680 if (ret) 681 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 682 enable ? "enable" : "disable", ret); 683 684 return ret; 685 } 686 687 static int 688 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 689 { 690 struct hns3_adapter *hns = dev->data->dev_private; 691 struct hns3_hw *hw = &hns->hw; 692 struct rte_eth_rxmode *rxmode; 693 unsigned int tmp_mask; 694 bool enable; 695 int ret = 0; 696 697 rte_spinlock_lock(&hw->lock); 698 rxmode = &dev->data->dev_conf.rxmode; 699 tmp_mask = (unsigned int)mask; 700 if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) { 701 /* ignore vlan filter configuration during promiscuous mode */ 702 if (!dev->data->promiscuous) { 703 /* Enable or disable VLAN filter */ 704 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? 705 true : false; 706 707 ret = hns3_enable_vlan_filter(hns, enable); 708 if (ret) { 709 rte_spinlock_unlock(&hw->lock); 710 hns3_err(hw, "failed to %s rx filter, ret = %d", 711 enable ? "enable" : "disable", ret); 712 return ret; 713 } 714 } 715 } 716 717 if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) { 718 /* Enable or disable VLAN stripping */ 719 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? 720 true : false; 721 722 ret = hns3_en_hw_strip_rxvtag(hns, enable); 723 if (ret) { 724 rte_spinlock_unlock(&hw->lock); 725 hns3_err(hw, "failed to %s rx strip, ret = %d", 726 enable ? "enable" : "disable", ret); 727 return ret; 728 } 729 } 730 731 rte_spinlock_unlock(&hw->lock); 732 733 return ret; 734 } 735 736 static int 737 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 738 struct hns3_tx_vtag_cfg *vcfg) 739 { 740 struct hns3_vport_vtag_tx_cfg_cmd *req; 741 struct hns3_cmd_desc desc; 742 struct hns3_hw *hw = &hns->hw; 743 uint16_t vport_id; 744 uint8_t bitmap; 745 int ret; 746 747 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 748 749 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 750 req->def_vlan_tag1 = vcfg->default_tag1; 751 req->def_vlan_tag2 = vcfg->default_tag2; 752 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 753 vcfg->accept_tag1 ? 1 : 0); 754 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 755 vcfg->accept_untag1 ? 1 : 0); 756 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 757 vcfg->accept_tag2 ? 1 : 0); 758 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 759 vcfg->accept_untag2 ? 1 : 0); 760 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 761 vcfg->insert_tag1_en ? 1 : 0); 762 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 763 vcfg->insert_tag2_en ? 1 : 0); 764 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 765 766 /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */ 767 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B, 768 vcfg->tag_shift_mode_en ? 1 : 0); 769 770 /* 771 * In current version VF is not supported when PF is driven by DPDK 772 * driver, just need to configure parameters for PF vport. 773 */ 774 vport_id = HNS3_PF_FUNC_ID; 775 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 776 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 777 req->vf_bitmap[req->vf_offset] = bitmap; 778 779 ret = hns3_cmd_send(hw, &desc, 1); 780 if (ret) 781 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 782 783 return ret; 784 } 785 786 static int 787 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 788 uint16_t pvid) 789 { 790 struct hns3_hw *hw = &hns->hw; 791 struct hns3_tx_vtag_cfg txvlan_cfg; 792 int ret; 793 794 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 795 txvlan_cfg.accept_tag1 = true; 796 txvlan_cfg.insert_tag1_en = false; 797 txvlan_cfg.default_tag1 = 0; 798 } else { 799 txvlan_cfg.accept_tag1 = 800 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE; 801 txvlan_cfg.insert_tag1_en = true; 802 txvlan_cfg.default_tag1 = pvid; 803 } 804 805 txvlan_cfg.accept_untag1 = true; 806 txvlan_cfg.accept_tag2 = true; 807 txvlan_cfg.accept_untag2 = true; 808 txvlan_cfg.insert_tag2_en = false; 809 txvlan_cfg.default_tag2 = 0; 810 txvlan_cfg.tag_shift_mode_en = true; 811 812 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 813 if (ret) { 814 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 815 ret); 816 return ret; 817 } 818 819 memcpy(&hns->pf.vtag_config.tx_vcfg, &txvlan_cfg, 820 sizeof(struct hns3_tx_vtag_cfg)); 821 822 return ret; 823 } 824 825 826 static void 827 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 828 { 829 struct hns3_user_vlan_table *vlan_entry; 830 struct hns3_pf *pf = &hns->pf; 831 832 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 833 if (vlan_entry->hd_tbl_status) { 834 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 835 vlan_entry->hd_tbl_status = false; 836 } 837 } 838 839 if (is_del_list) { 840 vlan_entry = LIST_FIRST(&pf->vlan_list); 841 while (vlan_entry) { 842 LIST_REMOVE(vlan_entry, next); 843 rte_free(vlan_entry); 844 vlan_entry = LIST_FIRST(&pf->vlan_list); 845 } 846 } 847 } 848 849 static void 850 hns3_add_all_vlan_table(struct hns3_adapter *hns) 851 { 852 struct hns3_user_vlan_table *vlan_entry; 853 struct hns3_pf *pf = &hns->pf; 854 855 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 856 if (!vlan_entry->hd_tbl_status) { 857 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 858 vlan_entry->hd_tbl_status = true; 859 } 860 } 861 } 862 863 static void 864 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 865 { 866 struct hns3_hw *hw = &hns->hw; 867 int ret; 868 869 hns3_rm_all_vlan_table(hns, true); 870 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) { 871 ret = hns3_set_port_vlan_filter(hns, 872 hw->port_base_vlan_cfg.pvid, 0); 873 if (ret) { 874 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 875 ret); 876 return; 877 } 878 } 879 } 880 881 static int 882 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 883 uint16_t port_base_vlan_state, uint16_t new_pvid) 884 { 885 struct hns3_hw *hw = &hns->hw; 886 uint16_t old_pvid; 887 int ret; 888 889 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 890 old_pvid = hw->port_base_vlan_cfg.pvid; 891 if (old_pvid != HNS3_INVALID_PVID) { 892 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 893 if (ret) { 894 hns3_err(hw, "failed to remove old pvid %u, " 895 "ret = %d", old_pvid, ret); 896 return ret; 897 } 898 } 899 900 hns3_rm_all_vlan_table(hns, false); 901 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1); 902 if (ret) { 903 hns3_err(hw, "failed to add new pvid %u, ret = %d", 904 new_pvid, ret); 905 return ret; 906 } 907 } else { 908 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 909 if (ret) { 910 hns3_err(hw, "failed to remove pvid %u, ret = %d", 911 new_pvid, ret); 912 return ret; 913 } 914 915 hns3_add_all_vlan_table(hns); 916 } 917 return 0; 918 } 919 920 static int 921 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 922 { 923 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 924 struct hns3_rx_vtag_cfg rx_vlan_cfg; 925 bool rx_strip_en; 926 int ret; 927 928 rx_strip_en = old_cfg->rx_vlan_offload_en; 929 if (on) { 930 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 931 rx_vlan_cfg.strip_tag2_en = true; 932 rx_vlan_cfg.strip_tag2_discard_en = true; 933 } else { 934 rx_vlan_cfg.strip_tag1_en = false; 935 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 936 rx_vlan_cfg.strip_tag2_discard_en = false; 937 } 938 rx_vlan_cfg.strip_tag1_discard_en = false; 939 rx_vlan_cfg.vlan1_vlan_prionly = false; 940 rx_vlan_cfg.vlan2_vlan_prionly = false; 941 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 942 943 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 944 if (ret) 945 return ret; 946 947 memcpy(&hns->pf.vtag_config.rx_vcfg, &rx_vlan_cfg, 948 sizeof(struct hns3_rx_vtag_cfg)); 949 950 return ret; 951 } 952 953 static int 954 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 955 { 956 struct hns3_hw *hw = &hns->hw; 957 uint16_t port_base_vlan_state; 958 int ret, err; 959 960 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 961 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) 962 hns3_warn(hw, "Invalid operation! As current pvid set " 963 "is %u, disable pvid %u is invalid", 964 hw->port_base_vlan_cfg.pvid, pvid); 965 return 0; 966 } 967 968 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 969 HNS3_PORT_BASE_VLAN_DISABLE; 970 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 971 if (ret) { 972 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 973 ret); 974 return ret; 975 } 976 977 ret = hns3_en_pvid_strip(hns, on); 978 if (ret) { 979 hns3_err(hw, "failed to config rx vlan strip for pvid, " 980 "ret = %d", ret); 981 goto pvid_vlan_strip_fail; 982 } 983 984 if (pvid == HNS3_INVALID_PVID) 985 goto out; 986 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid); 987 if (ret) { 988 hns3_err(hw, "failed to update vlan filter entries, ret = %d", 989 ret); 990 goto vlan_filter_set_fail; 991 } 992 993 out: 994 hw->port_base_vlan_cfg.state = port_base_vlan_state; 995 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID; 996 return ret; 997 998 vlan_filter_set_fail: 999 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state == 1000 HNS3_PORT_BASE_VLAN_ENABLE); 1001 if (err) 1002 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err); 1003 1004 pvid_vlan_strip_fail: 1005 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state, 1006 hw->port_base_vlan_cfg.pvid); 1007 if (err) 1008 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err); 1009 1010 return ret; 1011 } 1012 1013 static int 1014 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 1015 { 1016 struct hns3_adapter *hns = dev->data->dev_private; 1017 struct hns3_hw *hw = &hns->hw; 1018 bool pvid_en_state_change; 1019 uint16_t pvid_state; 1020 int ret; 1021 1022 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 1023 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 1024 RTE_ETHER_MAX_VLAN_ID); 1025 return -EINVAL; 1026 } 1027 1028 /* 1029 * If PVID configuration state change, should refresh the PVID 1030 * configuration state in struct hns3_tx_queue/hns3_rx_queue. 1031 */ 1032 pvid_state = hw->port_base_vlan_cfg.state; 1033 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || 1034 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) 1035 pvid_en_state_change = false; 1036 else 1037 pvid_en_state_change = true; 1038 1039 rte_spinlock_lock(&hw->lock); 1040 ret = hns3_vlan_pvid_configure(hns, pvid, on); 1041 rte_spinlock_unlock(&hw->lock); 1042 if (ret) 1043 return ret; 1044 /* 1045 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx 1046 * need be processed by PMD. 1047 */ 1048 if (pvid_en_state_change && 1049 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 1050 hns3_update_all_queues_pvid_proc_en(hw); 1051 1052 return 0; 1053 } 1054 1055 static int 1056 hns3_default_vlan_config(struct hns3_adapter *hns) 1057 { 1058 struct hns3_hw *hw = &hns->hw; 1059 int ret; 1060 1061 /* 1062 * When vlan filter is enabled, hardware regards packets without vlan 1063 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan 1064 * table, packets without vlan won't be received. So, add vlan 0 as 1065 * the default vlan. 1066 */ 1067 ret = hns3_vlan_filter_configure(hns, 0, 1); 1068 if (ret) 1069 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 1070 return ret; 1071 } 1072 1073 static int 1074 hns3_init_vlan_config(struct hns3_adapter *hns) 1075 { 1076 struct hns3_hw *hw = &hns->hw; 1077 int ret; 1078 1079 /* 1080 * This function can be called in the initialization and reset process, 1081 * when in reset process, it means that hardware had been reseted 1082 * successfully and we need to restore the hardware configuration to 1083 * ensure that the hardware configuration remains unchanged before and 1084 * after reset. 1085 */ 1086 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1087 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 1088 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID; 1089 } 1090 1091 ret = hns3_vlan_filter_init(hns); 1092 if (ret) { 1093 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 1094 return ret; 1095 } 1096 1097 ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER, 1098 RTE_ETHER_TYPE_VLAN); 1099 if (ret) { 1100 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 1101 return ret; 1102 } 1103 1104 /* 1105 * When in the reinit dev stage of the reset process, the following 1106 * vlan-related configurations may differ from those at initialization, 1107 * we will restore configurations to hardware in hns3_restore_vlan_table 1108 * and hns3_restore_vlan_conf later. 1109 */ 1110 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1111 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0); 1112 if (ret) { 1113 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 1114 return ret; 1115 } 1116 1117 ret = hns3_en_hw_strip_rxvtag(hns, false); 1118 if (ret) { 1119 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 1120 ret); 1121 return ret; 1122 } 1123 } 1124 1125 return hns3_default_vlan_config(hns); 1126 } 1127 1128 static int 1129 hns3_restore_vlan_conf(struct hns3_adapter *hns) 1130 { 1131 struct hns3_pf *pf = &hns->pf; 1132 struct hns3_hw *hw = &hns->hw; 1133 uint64_t offloads; 1134 bool enable; 1135 int ret; 1136 1137 if (!hw->data->promiscuous) { 1138 /* restore vlan filter states */ 1139 offloads = hw->data->dev_conf.rxmode.offloads; 1140 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false; 1141 ret = hns3_enable_vlan_filter(hns, enable); 1142 if (ret) { 1143 hns3_err(hw, "failed to restore vlan rx filter conf, " 1144 "ret = %d", ret); 1145 return ret; 1146 } 1147 } 1148 1149 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1150 if (ret) { 1151 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1152 return ret; 1153 } 1154 1155 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1156 if (ret) 1157 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1158 1159 return ret; 1160 } 1161 1162 static int 1163 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1164 { 1165 struct hns3_adapter *hns = dev->data->dev_private; 1166 struct rte_eth_dev_data *data = dev->data; 1167 struct rte_eth_txmode *txmode; 1168 struct hns3_hw *hw = &hns->hw; 1169 int mask; 1170 int ret; 1171 1172 txmode = &data->dev_conf.txmode; 1173 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1174 hns3_warn(hw, 1175 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1176 "configuration is not supported! Ignore these two " 1177 "parameters: hw_vlan_reject_tagged(%u), " 1178 "hw_vlan_reject_untagged(%u)", 1179 txmode->hw_vlan_reject_tagged, 1180 txmode->hw_vlan_reject_untagged); 1181 1182 /* Apply vlan offload setting */ 1183 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK; 1184 ret = hns3_vlan_offload_set(dev, mask); 1185 if (ret) { 1186 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1187 ret); 1188 return ret; 1189 } 1190 1191 /* 1192 * If pvid config is not set in rte_eth_conf, driver needn't to set 1193 * VLAN pvid related configuration to hardware. 1194 */ 1195 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1196 return 0; 1197 1198 /* Apply pvid setting */ 1199 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1200 txmode->hw_vlan_insert_pvid); 1201 if (ret) 1202 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d", 1203 txmode->pvid, ret); 1204 1205 return ret; 1206 } 1207 1208 static int 1209 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1210 unsigned int tso_mss_max) 1211 { 1212 struct hns3_cfg_tso_status_cmd *req; 1213 struct hns3_cmd_desc desc; 1214 uint16_t tso_mss; 1215 1216 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1217 1218 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1219 1220 tso_mss = 0; 1221 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1222 tso_mss_min); 1223 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1224 1225 tso_mss = 0; 1226 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1227 tso_mss_max); 1228 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1229 1230 return hns3_cmd_send(hw, &desc, 1); 1231 } 1232 1233 static int 1234 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1235 uint16_t *allocated_size, bool is_alloc) 1236 { 1237 struct hns3_umv_spc_alc_cmd *req; 1238 struct hns3_cmd_desc desc; 1239 int ret; 1240 1241 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1242 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1243 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1244 req->space_size = rte_cpu_to_le_32(space_size); 1245 1246 ret = hns3_cmd_send(hw, &desc, 1); 1247 if (ret) { 1248 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1249 is_alloc ? "allocate" : "free", ret); 1250 return ret; 1251 } 1252 1253 if (is_alloc && allocated_size) 1254 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1255 1256 return 0; 1257 } 1258 1259 static int 1260 hns3_init_umv_space(struct hns3_hw *hw) 1261 { 1262 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1263 struct hns3_pf *pf = &hns->pf; 1264 uint16_t allocated_size = 0; 1265 int ret; 1266 1267 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1268 true); 1269 if (ret) 1270 return ret; 1271 1272 if (allocated_size < pf->wanted_umv_size) 1273 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1274 pf->wanted_umv_size, allocated_size); 1275 1276 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1277 pf->wanted_umv_size; 1278 pf->used_umv_size = 0; 1279 return 0; 1280 } 1281 1282 static int 1283 hns3_uninit_umv_space(struct hns3_hw *hw) 1284 { 1285 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1286 struct hns3_pf *pf = &hns->pf; 1287 int ret; 1288 1289 if (pf->max_umv_size == 0) 1290 return 0; 1291 1292 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1293 if (ret) 1294 return ret; 1295 1296 pf->max_umv_size = 0; 1297 1298 return 0; 1299 } 1300 1301 static bool 1302 hns3_is_umv_space_full(struct hns3_hw *hw) 1303 { 1304 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1305 struct hns3_pf *pf = &hns->pf; 1306 bool is_full; 1307 1308 is_full = (pf->used_umv_size >= pf->max_umv_size); 1309 1310 return is_full; 1311 } 1312 1313 static void 1314 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1315 { 1316 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1317 struct hns3_pf *pf = &hns->pf; 1318 1319 if (is_free) { 1320 if (pf->used_umv_size > 0) 1321 pf->used_umv_size--; 1322 } else 1323 pf->used_umv_size++; 1324 } 1325 1326 static void 1327 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1328 const uint8_t *addr, bool is_mc) 1329 { 1330 const unsigned char *mac_addr = addr; 1331 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1332 ((uint32_t)mac_addr[2] << 16) | 1333 ((uint32_t)mac_addr[1] << 8) | 1334 (uint32_t)mac_addr[0]; 1335 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1336 1337 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1338 if (is_mc) { 1339 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1340 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1341 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1342 } 1343 1344 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1345 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1346 } 1347 1348 static int 1349 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1350 uint8_t resp_code, 1351 enum hns3_mac_vlan_tbl_opcode op) 1352 { 1353 if (cmdq_resp) { 1354 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1355 cmdq_resp); 1356 return -EIO; 1357 } 1358 1359 if (op == HNS3_MAC_VLAN_ADD) { 1360 if (resp_code == 0 || resp_code == 1) { 1361 return 0; 1362 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1363 hns3_err(hw, "add mac addr failed for uc_overflow"); 1364 return -ENOSPC; 1365 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1366 hns3_err(hw, "add mac addr failed for mc_overflow"); 1367 return -ENOSPC; 1368 } 1369 1370 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1371 resp_code); 1372 return -EIO; 1373 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1374 if (resp_code == 0) { 1375 return 0; 1376 } else if (resp_code == 1) { 1377 hns3_dbg(hw, "remove mac addr failed for miss"); 1378 return -ENOENT; 1379 } 1380 1381 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1382 resp_code); 1383 return -EIO; 1384 } else if (op == HNS3_MAC_VLAN_LKUP) { 1385 if (resp_code == 0) { 1386 return 0; 1387 } else if (resp_code == 1) { 1388 hns3_dbg(hw, "lookup mac addr failed for miss"); 1389 return -ENOENT; 1390 } 1391 1392 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1393 resp_code); 1394 return -EIO; 1395 } 1396 1397 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1398 op); 1399 1400 return -EINVAL; 1401 } 1402 1403 static int 1404 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1405 struct hns3_mac_vlan_tbl_entry_cmd *req, 1406 struct hns3_cmd_desc *desc, uint8_t desc_num) 1407 { 1408 uint8_t resp_code; 1409 uint16_t retval; 1410 int ret; 1411 int i; 1412 1413 if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) { 1414 for (i = 0; i < desc_num - 1; i++) { 1415 hns3_cmd_setup_basic_desc(&desc[i], 1416 HNS3_OPC_MAC_VLAN_ADD, true); 1417 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1418 if (i == 0) 1419 memcpy(desc[i].data, req, 1420 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1421 } 1422 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD, 1423 true); 1424 } else { 1425 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, 1426 true); 1427 memcpy(desc[0].data, req, 1428 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1429 } 1430 ret = hns3_cmd_send(hw, desc, desc_num); 1431 if (ret) { 1432 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1433 ret); 1434 return ret; 1435 } 1436 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1437 retval = rte_le_to_cpu_16(desc[0].retval); 1438 1439 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1440 HNS3_MAC_VLAN_LKUP); 1441 } 1442 1443 static int 1444 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1445 struct hns3_mac_vlan_tbl_entry_cmd *req, 1446 struct hns3_cmd_desc *desc, uint8_t desc_num) 1447 { 1448 uint8_t resp_code; 1449 uint16_t retval; 1450 int cfg_status; 1451 int ret; 1452 int i; 1453 1454 if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) { 1455 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false); 1456 memcpy(desc->data, req, 1457 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1458 ret = hns3_cmd_send(hw, desc, desc_num); 1459 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff; 1460 retval = rte_le_to_cpu_16(desc->retval); 1461 1462 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1463 HNS3_MAC_VLAN_ADD); 1464 } else { 1465 for (i = 0; i < desc_num; i++) { 1466 hns3_cmd_reuse_desc(&desc[i], false); 1467 if (i == desc_num - 1) 1468 desc[i].flag &= 1469 rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1470 else 1471 desc[i].flag |= 1472 rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1473 } 1474 memcpy(desc[0].data, req, 1475 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1476 desc[0].retval = 0; 1477 ret = hns3_cmd_send(hw, desc, desc_num); 1478 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1479 retval = rte_le_to_cpu_16(desc[0].retval); 1480 1481 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1482 HNS3_MAC_VLAN_ADD); 1483 } 1484 1485 if (ret) { 1486 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1487 return ret; 1488 } 1489 1490 return cfg_status; 1491 } 1492 1493 static int 1494 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1495 struct hns3_mac_vlan_tbl_entry_cmd *req) 1496 { 1497 struct hns3_cmd_desc desc; 1498 uint8_t resp_code; 1499 uint16_t retval; 1500 int ret; 1501 1502 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1503 1504 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1505 1506 ret = hns3_cmd_send(hw, &desc, 1); 1507 if (ret) { 1508 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1509 return ret; 1510 } 1511 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1512 retval = rte_le_to_cpu_16(desc.retval); 1513 1514 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1515 HNS3_MAC_VLAN_REMOVE); 1516 } 1517 1518 static int 1519 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1520 { 1521 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1522 struct hns3_mac_vlan_tbl_entry_cmd req; 1523 struct hns3_pf *pf = &hns->pf; 1524 struct hns3_cmd_desc desc; 1525 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1526 uint16_t egress_port = 0; 1527 uint8_t vf_id; 1528 int ret; 1529 1530 /* check if mac addr is valid */ 1531 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1532 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1533 mac_addr); 1534 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1535 mac_str); 1536 return -EINVAL; 1537 } 1538 1539 memset(&req, 0, sizeof(req)); 1540 1541 /* 1542 * In current version VF is not supported when PF is driven by DPDK 1543 * driver, just need to configure parameters for PF vport. 1544 */ 1545 vf_id = HNS3_PF_FUNC_ID; 1546 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1547 HNS3_MAC_EPORT_VFID_S, vf_id); 1548 1549 req.egress_port = rte_cpu_to_le_16(egress_port); 1550 1551 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1552 1553 /* 1554 * Lookup the mac address in the mac_vlan table, and add 1555 * it if the entry is inexistent. Repeated unicast entry 1556 * is not allowed in the mac vlan table. 1557 */ 1558 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, 1559 HNS3_UC_MAC_VLAN_OPS_DESC_NUM); 1560 if (ret == -ENOENT) { 1561 if (!hns3_is_umv_space_full(hw)) { 1562 ret = hns3_add_mac_vlan_tbl(hw, &req, &desc, 1563 HNS3_UC_MAC_VLAN_OPS_DESC_NUM); 1564 if (!ret) 1565 hns3_update_umv_space(hw, false); 1566 return ret; 1567 } 1568 1569 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1570 1571 return -ENOSPC; 1572 } 1573 1574 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1575 1576 /* check if we just hit the duplicate */ 1577 if (ret == 0) { 1578 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1579 return 0; 1580 } 1581 1582 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1583 mac_str); 1584 1585 return ret; 1586 } 1587 1588 static int 1589 hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1590 { 1591 struct hns3_mac_vlan_tbl_entry_cmd req; 1592 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1593 int ret; 1594 1595 /* check if mac addr is valid */ 1596 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1597 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1598 mac_addr); 1599 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1600 mac_str); 1601 return -EINVAL; 1602 } 1603 1604 memset(&req, 0, sizeof(req)); 1605 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1606 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1607 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1608 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1609 return 0; 1610 else if (ret == 0) 1611 hns3_update_umv_space(hw, true); 1612 1613 return ret; 1614 } 1615 1616 static int 1617 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1618 struct rte_ether_addr *mac_addr) 1619 { 1620 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1621 struct rte_ether_addr *oaddr; 1622 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1623 int ret, ret_val; 1624 1625 rte_spinlock_lock(&hw->lock); 1626 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1627 ret = hw->ops.del_uc_mac_addr(hw, oaddr); 1628 if (ret) { 1629 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1630 oaddr); 1631 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1632 mac_str, ret); 1633 1634 rte_spinlock_unlock(&hw->lock); 1635 return ret; 1636 } 1637 1638 ret = hw->ops.add_uc_mac_addr(hw, mac_addr); 1639 if (ret) { 1640 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1641 mac_addr); 1642 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1643 goto err_add_uc_addr; 1644 } 1645 1646 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1647 if (ret) { 1648 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1649 goto err_pause_addr_cfg; 1650 } 1651 1652 rte_ether_addr_copy(mac_addr, 1653 (struct rte_ether_addr *)hw->mac.mac_addr); 1654 rte_spinlock_unlock(&hw->lock); 1655 1656 return 0; 1657 1658 err_pause_addr_cfg: 1659 ret_val = hw->ops.del_uc_mac_addr(hw, mac_addr); 1660 if (ret_val) { 1661 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1662 mac_addr); 1663 hns3_warn(hw, 1664 "Failed to roll back to del set mac addr(%s): %d", 1665 mac_str, ret_val); 1666 } 1667 1668 err_add_uc_addr: 1669 ret_val = hw->ops.add_uc_mac_addr(hw, oaddr); 1670 if (ret_val) { 1671 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr); 1672 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d", 1673 mac_str, ret_val); 1674 } 1675 rte_spinlock_unlock(&hw->lock); 1676 1677 return ret; 1678 } 1679 1680 static void 1681 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1682 { 1683 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1684 uint8_t word_num; 1685 uint8_t bit_num; 1686 1687 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1688 word_num = vfid / 32; 1689 bit_num = vfid % 32; 1690 if (clr) 1691 desc[1].data[word_num] &= 1692 rte_cpu_to_le_32(~(1UL << bit_num)); 1693 else 1694 desc[1].data[word_num] |= 1695 rte_cpu_to_le_32(1UL << bit_num); 1696 } else { 1697 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1698 bit_num = vfid % 32; 1699 if (clr) 1700 desc[2].data[word_num] &= 1701 rte_cpu_to_le_32(~(1UL << bit_num)); 1702 else 1703 desc[2].data[word_num] |= 1704 rte_cpu_to_le_32(1UL << bit_num); 1705 } 1706 } 1707 1708 static int 1709 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1710 { 1711 struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM]; 1712 struct hns3_mac_vlan_tbl_entry_cmd req; 1713 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1714 uint8_t vf_id; 1715 int ret; 1716 int idx; 1717 1718 /* Check if mac addr is valid */ 1719 if (!rte_is_multicast_ether_addr(mac_addr)) { 1720 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1721 mac_addr); 1722 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1723 mac_str); 1724 return -EINVAL; 1725 } 1726 1727 memset(&req, 0, sizeof(req)); 1728 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1729 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1730 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, 1731 HNS3_MC_MAC_VLAN_OPS_DESC_NUM); 1732 if (ret) { 1733 /* This mac addr do not exist, add new entry for it */ 1734 for (idx = 0; idx < HNS3_MC_MAC_VLAN_OPS_DESC_NUM; idx++) 1735 memset(desc[idx].data, 0, sizeof(desc[idx].data)); 1736 } 1737 1738 /* 1739 * In current version VF is not supported when PF is driven by DPDK 1740 * driver, just need to configure parameters for PF vport. 1741 */ 1742 vf_id = HNS3_PF_FUNC_ID; 1743 hns3_update_desc_vfid(desc, vf_id, false); 1744 ret = hns3_add_mac_vlan_tbl(hw, &req, desc, 1745 HNS3_MC_MAC_VLAN_OPS_DESC_NUM); 1746 if (ret) { 1747 if (ret == -ENOSPC) 1748 hns3_err(hw, "mc mac vlan table is full"); 1749 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1750 mac_addr); 1751 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1752 } 1753 1754 return ret; 1755 } 1756 1757 static int 1758 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1759 { 1760 struct hns3_mac_vlan_tbl_entry_cmd req; 1761 struct hns3_cmd_desc desc[3]; 1762 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1763 uint8_t vf_id; 1764 int ret; 1765 1766 /* Check if mac addr is valid */ 1767 if (!rte_is_multicast_ether_addr(mac_addr)) { 1768 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1769 mac_addr); 1770 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1771 mac_str); 1772 return -EINVAL; 1773 } 1774 1775 memset(&req, 0, sizeof(req)); 1776 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1777 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1778 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, 1779 HNS3_MC_MAC_VLAN_OPS_DESC_NUM); 1780 if (ret == 0) { 1781 /* 1782 * This mac addr exist, remove this handle's VFID for it. 1783 * In current version VF is not supported when PF is driven by 1784 * DPDK driver, just need to configure parameters for PF vport. 1785 */ 1786 vf_id = HNS3_PF_FUNC_ID; 1787 hns3_update_desc_vfid(desc, vf_id, true); 1788 1789 /* All the vfid is zero, so need to delete this entry */ 1790 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1791 } else if (ret == -ENOENT) { 1792 /* This mac addr doesn't exist. */ 1793 return 0; 1794 } 1795 1796 if (ret) { 1797 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1798 mac_addr); 1799 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1800 } 1801 1802 return ret; 1803 } 1804 1805 static int 1806 hns3_check_mq_mode(struct rte_eth_dev *dev) 1807 { 1808 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 1809 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 1810 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1811 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1812 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 1813 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 1814 uint8_t num_tc; 1815 int max_tc = 0; 1816 int i; 1817 1818 if (((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) || 1819 (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB || 1820 tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) { 1821 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.", 1822 rx_mq_mode, tx_mq_mode); 1823 return -EOPNOTSUPP; 1824 } 1825 1826 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 1827 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 1828 if ((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) { 1829 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 1830 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 1831 dcb_rx_conf->nb_tcs, pf->tc_max); 1832 return -EINVAL; 1833 } 1834 1835 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 1836 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 1837 hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, " 1838 "nb_tcs(%d) != %d or %d in rx direction.", 1839 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 1840 return -EINVAL; 1841 } 1842 1843 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 1844 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 1845 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 1846 return -EINVAL; 1847 } 1848 1849 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 1850 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 1851 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, " 1852 "is not equal to one in tx direction.", 1853 i, dcb_rx_conf->dcb_tc[i]); 1854 return -EINVAL; 1855 } 1856 if (dcb_rx_conf->dcb_tc[i] > max_tc) 1857 max_tc = dcb_rx_conf->dcb_tc[i]; 1858 } 1859 1860 num_tc = max_tc + 1; 1861 if (num_tc > dcb_rx_conf->nb_tcs) { 1862 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 1863 num_tc, dcb_rx_conf->nb_tcs); 1864 return -EINVAL; 1865 } 1866 } 1867 1868 return 0; 1869 } 1870 1871 static int 1872 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en, 1873 enum hns3_ring_type queue_type, uint16_t queue_id) 1874 { 1875 struct hns3_cmd_desc desc; 1876 struct hns3_ctrl_vector_chain_cmd *req = 1877 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 1878 enum hns3_opcode_type op; 1879 uint16_t tqp_type_and_id = 0; 1880 uint16_t type; 1881 uint16_t gl; 1882 int ret; 1883 1884 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 1885 hns3_cmd_setup_basic_desc(&desc, op, false); 1886 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M, 1887 HNS3_TQP_INT_ID_L_S); 1888 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M, 1889 HNS3_TQP_INT_ID_H_S); 1890 1891 if (queue_type == HNS3_RING_TYPE_RX) 1892 gl = HNS3_RING_GL_RX; 1893 else 1894 gl = HNS3_RING_GL_TX; 1895 1896 type = queue_type; 1897 1898 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 1899 type); 1900 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 1901 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 1902 gl); 1903 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 1904 req->int_cause_num = 1; 1905 ret = hns3_cmd_send(hw, &desc, 1); 1906 if (ret) { 1907 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.", 1908 en ? "Map" : "Unmap", queue_id, vector_id, ret); 1909 return ret; 1910 } 1911 1912 return 0; 1913 } 1914 1915 static int 1916 hns3_setup_dcb(struct rte_eth_dev *dev) 1917 { 1918 struct hns3_adapter *hns = dev->data->dev_private; 1919 struct hns3_hw *hw = &hns->hw; 1920 int ret; 1921 1922 if (!hns3_dev_get_support(hw, DCB)) { 1923 hns3_err(hw, "this port does not support dcb configurations."); 1924 return -EOPNOTSUPP; 1925 } 1926 1927 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 1928 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 1929 return -EOPNOTSUPP; 1930 } 1931 1932 ret = hns3_dcb_configure(hns); 1933 if (ret) 1934 hns3_err(hw, "failed to config dcb: %d", ret); 1935 1936 return ret; 1937 } 1938 1939 static int 1940 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds) 1941 { 1942 int ret; 1943 1944 /* 1945 * Some hardware doesn't support auto-negotiation, but users may not 1946 * configure link_speeds (default 0), which means auto-negotiation. 1947 * In this case, it should return success. 1948 */ 1949 if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG && 1950 hw->mac.support_autoneg == 0) 1951 return 0; 1952 1953 if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) { 1954 ret = hns3_check_port_speed(hw, link_speeds); 1955 if (ret) 1956 return ret; 1957 } 1958 1959 return 0; 1960 } 1961 1962 static int 1963 hns3_check_dev_conf(struct rte_eth_dev *dev) 1964 { 1965 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1966 struct rte_eth_conf *conf = &dev->data->dev_conf; 1967 int ret; 1968 1969 ret = hns3_check_mq_mode(dev); 1970 if (ret) 1971 return ret; 1972 1973 return hns3_check_link_speed(hw, conf->link_speeds); 1974 } 1975 1976 static int 1977 hns3_dev_configure(struct rte_eth_dev *dev) 1978 { 1979 struct hns3_adapter *hns = dev->data->dev_private; 1980 struct rte_eth_conf *conf = &dev->data->dev_conf; 1981 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 1982 struct hns3_hw *hw = &hns->hw; 1983 uint16_t nb_rx_q = dev->data->nb_rx_queues; 1984 uint16_t nb_tx_q = dev->data->nb_tx_queues; 1985 struct rte_eth_rss_conf rss_conf; 1986 bool gro_en; 1987 int ret; 1988 1989 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 1990 1991 /* 1992 * Some versions of hardware network engine does not support 1993 * individually enable/disable/reset the Tx or Rx queue. These devices 1994 * must enable/disable/reset Tx and Rx queues at the same time. When the 1995 * numbers of Tx queues allocated by upper applications are not equal to 1996 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 1997 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 1998 * work as usual. But these fake queues are imperceptible, and can not 1999 * be used by upper applications. 2000 */ 2001 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2002 if (ret) { 2003 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret); 2004 hw->cfg_max_queues = 0; 2005 return ret; 2006 } 2007 2008 hw->adapter_state = HNS3_NIC_CONFIGURING; 2009 ret = hns3_check_dev_conf(dev); 2010 if (ret) 2011 goto cfg_err; 2012 2013 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) { 2014 ret = hns3_setup_dcb(dev); 2015 if (ret) 2016 goto cfg_err; 2017 } 2018 2019 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) { 2020 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 2021 rss_conf = conf->rx_adv_conf.rss_conf; 2022 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2023 if (ret) 2024 goto cfg_err; 2025 } 2026 2027 ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu); 2028 if (ret != 0) 2029 goto cfg_err; 2030 2031 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf); 2032 if (ret) 2033 goto cfg_err; 2034 2035 ret = hns3_dev_configure_vlan(dev); 2036 if (ret) 2037 goto cfg_err; 2038 2039 /* config hardware GRO */ 2040 gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false; 2041 ret = hns3_config_gro(hw, gro_en); 2042 if (ret) 2043 goto cfg_err; 2044 2045 hns3_init_rx_ptype_tble(dev); 2046 hw->adapter_state = HNS3_NIC_CONFIGURED; 2047 2048 return 0; 2049 2050 cfg_err: 2051 hw->cfg_max_queues = 0; 2052 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2053 hw->adapter_state = HNS3_NIC_INITIALIZED; 2054 2055 return ret; 2056 } 2057 2058 static int 2059 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2060 { 2061 struct hns3_config_max_frm_size_cmd *req; 2062 struct hns3_cmd_desc desc; 2063 2064 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2065 2066 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2067 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2068 req->min_frm_size = RTE_ETHER_MIN_LEN; 2069 2070 return hns3_cmd_send(hw, &desc, 1); 2071 } 2072 2073 static int 2074 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2075 { 2076 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2077 int err; 2078 int ret; 2079 2080 ret = hns3_set_mac_mtu(hw, mps); 2081 if (ret) { 2082 hns3_err(hw, "failed to set mtu, ret = %d", ret); 2083 return ret; 2084 } 2085 2086 ret = hns3_buffer_alloc(hw); 2087 if (ret) { 2088 hns3_err(hw, "failed to allocate buffer, ret = %d", ret); 2089 goto rollback; 2090 } 2091 2092 hns->pf.mps = mps; 2093 2094 return 0; 2095 2096 rollback: 2097 err = hns3_set_mac_mtu(hw, hns->pf.mps); 2098 if (err) 2099 hns3_err(hw, "fail to rollback MTU, err = %d", err); 2100 2101 return ret; 2102 } 2103 2104 static int 2105 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2106 { 2107 struct hns3_adapter *hns = dev->data->dev_private; 2108 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2109 struct hns3_hw *hw = &hns->hw; 2110 int ret; 2111 2112 if (dev->data->dev_started) { 2113 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2114 "before configuration", dev->data->port_id); 2115 return -EBUSY; 2116 } 2117 2118 rte_spinlock_lock(&hw->lock); 2119 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2120 2121 /* 2122 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2123 * assign to "uint16_t" type variable. 2124 */ 2125 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2126 if (ret) { 2127 rte_spinlock_unlock(&hw->lock); 2128 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2129 dev->data->port_id, mtu, ret); 2130 return ret; 2131 } 2132 2133 rte_spinlock_unlock(&hw->lock); 2134 2135 return 0; 2136 } 2137 2138 static uint32_t 2139 hns3_get_copper_port_speed_capa(uint32_t supported_speed) 2140 { 2141 uint32_t speed_capa = 0; 2142 2143 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT) 2144 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD; 2145 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT) 2146 speed_capa |= RTE_ETH_LINK_SPEED_10M; 2147 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT) 2148 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD; 2149 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT) 2150 speed_capa |= RTE_ETH_LINK_SPEED_100M; 2151 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT) 2152 speed_capa |= RTE_ETH_LINK_SPEED_1G; 2153 2154 return speed_capa; 2155 } 2156 2157 static uint32_t 2158 hns3_get_firber_port_speed_capa(uint32_t supported_speed) 2159 { 2160 uint32_t speed_capa = 0; 2161 2162 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT) 2163 speed_capa |= RTE_ETH_LINK_SPEED_1G; 2164 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT) 2165 speed_capa |= RTE_ETH_LINK_SPEED_10G; 2166 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT) 2167 speed_capa |= RTE_ETH_LINK_SPEED_25G; 2168 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT) 2169 speed_capa |= RTE_ETH_LINK_SPEED_40G; 2170 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT) 2171 speed_capa |= RTE_ETH_LINK_SPEED_50G; 2172 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT) 2173 speed_capa |= RTE_ETH_LINK_SPEED_100G; 2174 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT) 2175 speed_capa |= RTE_ETH_LINK_SPEED_200G; 2176 2177 return speed_capa; 2178 } 2179 2180 uint32_t 2181 hns3_get_speed_capa(struct hns3_hw *hw) 2182 { 2183 struct hns3_mac *mac = &hw->mac; 2184 uint32_t speed_capa; 2185 2186 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 2187 speed_capa = 2188 hns3_get_copper_port_speed_capa(mac->supported_speed); 2189 else 2190 speed_capa = 2191 hns3_get_firber_port_speed_capa(mac->supported_speed); 2192 2193 if (mac->support_autoneg == 0) 2194 speed_capa |= RTE_ETH_LINK_SPEED_FIXED; 2195 2196 return speed_capa; 2197 } 2198 2199 static int 2200 hns3_update_port_link_info(struct rte_eth_dev *eth_dev) 2201 { 2202 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2203 int ret; 2204 2205 (void)hns3_update_link_status(hw); 2206 2207 ret = hns3_update_link_info(eth_dev); 2208 if (ret) 2209 hw->mac.link_status = RTE_ETH_LINK_DOWN; 2210 2211 return ret; 2212 } 2213 2214 static void 2215 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev, 2216 struct rte_eth_link *new_link) 2217 { 2218 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2219 struct hns3_mac *mac = &hw->mac; 2220 2221 switch (mac->link_speed) { 2222 case RTE_ETH_SPEED_NUM_10M: 2223 case RTE_ETH_SPEED_NUM_100M: 2224 case RTE_ETH_SPEED_NUM_1G: 2225 case RTE_ETH_SPEED_NUM_10G: 2226 case RTE_ETH_SPEED_NUM_25G: 2227 case RTE_ETH_SPEED_NUM_40G: 2228 case RTE_ETH_SPEED_NUM_50G: 2229 case RTE_ETH_SPEED_NUM_100G: 2230 case RTE_ETH_SPEED_NUM_200G: 2231 if (mac->link_status) 2232 new_link->link_speed = mac->link_speed; 2233 break; 2234 default: 2235 if (mac->link_status) 2236 new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN; 2237 break; 2238 } 2239 2240 if (!mac->link_status) 2241 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE; 2242 2243 new_link->link_duplex = mac->link_duplex; 2244 new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; 2245 new_link->link_autoneg = mac->link_autoneg; 2246 } 2247 2248 static int 2249 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) 2250 { 2251 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */ 2252 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */ 2253 2254 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2255 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES; 2256 struct hns3_mac *mac = &hw->mac; 2257 struct rte_eth_link new_link; 2258 int ret; 2259 2260 /* When port is stopped, report link down. */ 2261 if (eth_dev->data->dev_started == 0) { 2262 new_link.link_autoneg = mac->link_autoneg; 2263 new_link.link_duplex = mac->link_duplex; 2264 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE; 2265 new_link.link_status = RTE_ETH_LINK_DOWN; 2266 goto out; 2267 } 2268 2269 do { 2270 ret = hns3_update_port_link_info(eth_dev); 2271 if (ret) { 2272 hns3_err(hw, "failed to get port link info, ret = %d.", 2273 ret); 2274 break; 2275 } 2276 2277 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP) 2278 break; 2279 2280 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL); 2281 } while (retry_cnt--); 2282 2283 memset(&new_link, 0, sizeof(new_link)); 2284 hns3_setup_linkstatus(eth_dev, &new_link); 2285 2286 out: 2287 return rte_eth_linkstatus_set(eth_dev, &new_link); 2288 } 2289 2290 static int 2291 hns3_dev_set_link_up(struct rte_eth_dev *dev) 2292 { 2293 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2294 int ret; 2295 2296 /* 2297 * The "tx_pkt_burst" will be restored. But the secondary process does 2298 * not support the mechanism for notifying the primary process. 2299 */ 2300 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2301 hns3_err(hw, "secondary process does not support to set link up."); 2302 return -ENOTSUP; 2303 } 2304 2305 /* 2306 * If device isn't started Rx/Tx function is still disabled, setting 2307 * link up is not allowed. But it is probably better to return success 2308 * to reduce the impact on the upper layer. 2309 */ 2310 if (hw->adapter_state != HNS3_NIC_STARTED) { 2311 hns3_info(hw, "device isn't started, can't set link up."); 2312 return 0; 2313 } 2314 2315 if (!hw->set_link_down) 2316 return 0; 2317 2318 rte_spinlock_lock(&hw->lock); 2319 ret = hns3_cfg_mac_mode(hw, true); 2320 if (ret) { 2321 rte_spinlock_unlock(&hw->lock); 2322 hns3_err(hw, "failed to set link up, ret = %d", ret); 2323 return ret; 2324 } 2325 2326 hw->set_link_down = false; 2327 hns3_start_tx_datapath(dev); 2328 rte_spinlock_unlock(&hw->lock); 2329 2330 return 0; 2331 } 2332 2333 static int 2334 hns3_dev_set_link_down(struct rte_eth_dev *dev) 2335 { 2336 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2337 int ret; 2338 2339 /* 2340 * The "tx_pkt_burst" will be set to dummy function. But the secondary 2341 * process does not support the mechanism for notifying the primary 2342 * process. 2343 */ 2344 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2345 hns3_err(hw, "secondary process does not support to set link down."); 2346 return -ENOTSUP; 2347 } 2348 2349 /* 2350 * If device isn't started or the API has been called, link status is 2351 * down, return success. 2352 */ 2353 if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down) 2354 return 0; 2355 2356 rte_spinlock_lock(&hw->lock); 2357 hns3_stop_tx_datapath(dev); 2358 ret = hns3_cfg_mac_mode(hw, false); 2359 if (ret) { 2360 hns3_start_tx_datapath(dev); 2361 rte_spinlock_unlock(&hw->lock); 2362 hns3_err(hw, "failed to set link down, ret = %d", ret); 2363 return ret; 2364 } 2365 2366 hw->set_link_down = true; 2367 rte_spinlock_unlock(&hw->lock); 2368 2369 return 0; 2370 } 2371 2372 static int 2373 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2374 { 2375 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2376 struct hns3_pf *pf = &hns->pf; 2377 2378 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2379 return -EINVAL; 2380 2381 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2382 2383 return 0; 2384 } 2385 2386 static int 2387 hns3_query_function_status(struct hns3_hw *hw) 2388 { 2389 #define HNS3_QUERY_MAX_CNT 10 2390 #define HNS3_QUERY_SLEEP_MSCOEND 1 2391 struct hns3_func_status_cmd *req; 2392 struct hns3_cmd_desc desc; 2393 int timeout = 0; 2394 int ret; 2395 2396 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2397 req = (struct hns3_func_status_cmd *)desc.data; 2398 2399 do { 2400 ret = hns3_cmd_send(hw, &desc, 1); 2401 if (ret) { 2402 PMD_INIT_LOG(ERR, "query function status failed %d", 2403 ret); 2404 return ret; 2405 } 2406 2407 /* Check pf reset is done */ 2408 if (req->pf_state) 2409 break; 2410 2411 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2412 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2413 2414 return hns3_parse_func_status(hw, req); 2415 } 2416 2417 static int 2418 hns3_get_pf_max_tqp_num(struct hns3_hw *hw) 2419 { 2420 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2421 struct hns3_pf *pf = &hns->pf; 2422 2423 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) { 2424 /* 2425 * The total_tqps_num obtained from firmware is maximum tqp 2426 * numbers of this port, which should be used for PF and VFs. 2427 * There is no need for pf to have so many tqp numbers in 2428 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 2429 * coming from config file, is assigned to maximum queue number 2430 * for the PF of this port by user. So users can modify the 2431 * maximum queue number of PF according to their own application 2432 * scenarios, which is more flexible to use. In addition, many 2433 * memories can be saved due to allocating queue statistics 2434 * room according to the actual number of queues required. The 2435 * maximum queue number of PF for network engine with 2436 * revision_id greater than 0x30 is assigned by config file. 2437 */ 2438 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) { 2439 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) " 2440 "must be greater than 0.", 2441 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF); 2442 return -EINVAL; 2443 } 2444 2445 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 2446 hw->total_tqps_num); 2447 } else { 2448 /* 2449 * Due to the limitation on the number of PF interrupts 2450 * available, the maximum queue number assigned to PF on 2451 * the network engine with revision_id 0x21 is 64. 2452 */ 2453 hw->tqps_num = RTE_MIN(hw->total_tqps_num, 2454 HNS3_MAX_TQP_NUM_HIP08_PF); 2455 } 2456 2457 return 0; 2458 } 2459 2460 static int 2461 hns3_query_pf_resource(struct hns3_hw *hw) 2462 { 2463 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2464 struct hns3_pf *pf = &hns->pf; 2465 struct hns3_pf_res_cmd *req; 2466 struct hns3_cmd_desc desc; 2467 int ret; 2468 2469 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 2470 ret = hns3_cmd_send(hw, &desc, 1); 2471 if (ret) { 2472 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 2473 return ret; 2474 } 2475 2476 req = (struct hns3_pf_res_cmd *)desc.data; 2477 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) + 2478 rte_le_to_cpu_16(req->ext_tqp_num); 2479 ret = hns3_get_pf_max_tqp_num(hw); 2480 if (ret) 2481 return ret; 2482 2483 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 2484 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 2485 2486 if (req->tx_buf_size) 2487 pf->tx_buf_size = 2488 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 2489 else 2490 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 2491 2492 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 2493 2494 if (req->dv_buf_size) 2495 pf->dv_buf_size = 2496 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 2497 else 2498 pf->dv_buf_size = HNS3_DEFAULT_DV; 2499 2500 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 2501 2502 hw->num_msi = 2503 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number), 2504 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 2505 2506 return 0; 2507 } 2508 2509 static void 2510 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 2511 { 2512 struct hns3_cfg_param_cmd *req; 2513 uint64_t mac_addr_tmp_high; 2514 uint8_t ext_rss_size_max; 2515 uint64_t mac_addr_tmp; 2516 uint32_t i; 2517 2518 req = (struct hns3_cfg_param_cmd *)desc[0].data; 2519 2520 /* get the configuration */ 2521 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2522 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 2523 2524 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2525 HNS3_CFG_PHY_ADDR_M, 2526 HNS3_CFG_PHY_ADDR_S); 2527 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2528 HNS3_CFG_MEDIA_TP_M, 2529 HNS3_CFG_MEDIA_TP_S); 2530 /* get mac address */ 2531 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 2532 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2533 HNS3_CFG_MAC_ADDR_H_M, 2534 HNS3_CFG_MAC_ADDR_H_S); 2535 2536 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 2537 2538 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2539 HNS3_CFG_DEFAULT_SPEED_M, 2540 HNS3_CFG_DEFAULT_SPEED_S); 2541 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2542 HNS3_CFG_RSS_SIZE_M, 2543 HNS3_CFG_RSS_SIZE_S); 2544 2545 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2546 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 2547 2548 req = (struct hns3_cfg_param_cmd *)desc[1].data; 2549 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 2550 2551 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2552 HNS3_CFG_SPEED_ABILITY_M, 2553 HNS3_CFG_SPEED_ABILITY_S); 2554 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2555 HNS3_CFG_UMV_TBL_SPACE_M, 2556 HNS3_CFG_UMV_TBL_SPACE_S); 2557 if (!cfg->umv_space) 2558 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 2559 2560 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]), 2561 HNS3_CFG_EXT_RSS_SIZE_M, 2562 HNS3_CFG_EXT_RSS_SIZE_S); 2563 /* 2564 * Field ext_rss_size_max obtained from firmware will be more flexible 2565 * for future changes and expansions, which is an exponent of 2, instead 2566 * of reading out directly. If this field is not zero, hns3 PF PMD 2567 * uses it as rss_size_max under one TC. Device, whose revision 2568 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the 2569 * maximum number of queues supported under a TC through this field. 2570 */ 2571 if (ext_rss_size_max) 2572 cfg->rss_size_max = 1U << ext_rss_size_max; 2573 } 2574 2575 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 2576 * @hw: pointer to struct hns3_hw 2577 * @hcfg: the config structure to be getted 2578 */ 2579 static int 2580 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 2581 { 2582 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 2583 struct hns3_cfg_param_cmd *req; 2584 uint32_t offset; 2585 uint32_t i; 2586 int ret; 2587 2588 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 2589 offset = 0; 2590 req = (struct hns3_cfg_param_cmd *)desc[i].data; 2591 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 2592 true); 2593 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 2594 i * HNS3_CFG_RD_LEN_BYTES); 2595 /* Len should be divided by 4 when send to hardware */ 2596 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 2597 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 2598 req->offset = rte_cpu_to_le_32(offset); 2599 } 2600 2601 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 2602 if (ret) { 2603 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 2604 return ret; 2605 } 2606 2607 hns3_parse_cfg(hcfg, desc); 2608 2609 return 0; 2610 } 2611 2612 static int 2613 hns3_parse_speed(int speed_cmd, uint32_t *speed) 2614 { 2615 switch (speed_cmd) { 2616 case HNS3_CFG_SPEED_10M: 2617 *speed = RTE_ETH_SPEED_NUM_10M; 2618 break; 2619 case HNS3_CFG_SPEED_100M: 2620 *speed = RTE_ETH_SPEED_NUM_100M; 2621 break; 2622 case HNS3_CFG_SPEED_1G: 2623 *speed = RTE_ETH_SPEED_NUM_1G; 2624 break; 2625 case HNS3_CFG_SPEED_10G: 2626 *speed = RTE_ETH_SPEED_NUM_10G; 2627 break; 2628 case HNS3_CFG_SPEED_25G: 2629 *speed = RTE_ETH_SPEED_NUM_25G; 2630 break; 2631 case HNS3_CFG_SPEED_40G: 2632 *speed = RTE_ETH_SPEED_NUM_40G; 2633 break; 2634 case HNS3_CFG_SPEED_50G: 2635 *speed = RTE_ETH_SPEED_NUM_50G; 2636 break; 2637 case HNS3_CFG_SPEED_100G: 2638 *speed = RTE_ETH_SPEED_NUM_100G; 2639 break; 2640 case HNS3_CFG_SPEED_200G: 2641 *speed = RTE_ETH_SPEED_NUM_200G; 2642 break; 2643 default: 2644 return -EINVAL; 2645 } 2646 2647 return 0; 2648 } 2649 2650 static void 2651 hns3_set_default_dev_specifications(struct hns3_hw *hw) 2652 { 2653 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 2654 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 2655 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 2656 hw->max_tm_rate = HNS3_ETHER_MAX_RATE; 2657 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 2658 } 2659 2660 static void 2661 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 2662 { 2663 struct hns3_dev_specs_0_cmd *req0; 2664 struct hns3_dev_specs_1_cmd *req1; 2665 2666 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 2667 req1 = (struct hns3_dev_specs_1_cmd *)desc[1].data; 2668 2669 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 2670 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 2671 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 2672 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); 2673 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 2674 hw->min_tx_pkt_len = req1->min_tx_pkt_len; 2675 } 2676 2677 static int 2678 hns3_check_dev_specifications(struct hns3_hw *hw) 2679 { 2680 if (hw->rss_ind_tbl_size == 0 || 2681 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 2682 hns3_err(hw, "the size of hash lookup table configured (%u) exceeds the maximum(%u)", 2683 hw->rss_ind_tbl_size, HNS3_RSS_IND_TBL_SIZE_MAX); 2684 return -EINVAL; 2685 } 2686 2687 return 0; 2688 } 2689 2690 static int 2691 hns3_query_dev_specifications(struct hns3_hw *hw) 2692 { 2693 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 2694 int ret; 2695 int i; 2696 2697 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2698 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 2699 true); 2700 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 2701 } 2702 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 2703 2704 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 2705 if (ret) 2706 return ret; 2707 2708 hns3_parse_dev_specifications(hw, desc); 2709 2710 return hns3_check_dev_specifications(hw); 2711 } 2712 2713 static int 2714 hns3_get_capability(struct hns3_hw *hw) 2715 { 2716 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2717 struct rte_pci_device *pci_dev; 2718 struct hns3_pf *pf = &hns->pf; 2719 struct rte_eth_dev *eth_dev; 2720 uint16_t device_id; 2721 int ret; 2722 2723 eth_dev = &rte_eth_devices[hw->data->port_id]; 2724 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2725 device_id = pci_dev->id.device_id; 2726 2727 if (device_id == HNS3_DEV_ID_25GE_RDMA || 2728 device_id == HNS3_DEV_ID_50GE_RDMA || 2729 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || 2730 device_id == HNS3_DEV_ID_200G_RDMA) 2731 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); 2732 2733 ret = hns3_get_pci_revision_id(hw, &hw->revision); 2734 if (ret) 2735 return ret; 2736 2737 ret = hns3_query_mac_stats_reg_num(hw); 2738 if (ret) 2739 return ret; 2740 2741 if (hw->revision < PCI_REVISION_ID_HIP09_A) { 2742 hns3_set_default_dev_specifications(hw); 2743 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 2744 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 2745 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 2746 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; 2747 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; 2748 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 2749 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; 2750 hw->rss_info.ipv6_sctp_offload_supported = false; 2751 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE; 2752 pf->support_multi_tc_pause = false; 2753 return 0; 2754 } 2755 2756 ret = hns3_query_dev_specifications(hw); 2757 if (ret) { 2758 PMD_INIT_LOG(ERR, 2759 "failed to query dev specifications, ret = %d", 2760 ret); 2761 return ret; 2762 } 2763 2764 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 2765 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 2766 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 2767 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; 2768 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; 2769 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; 2770 hw->rss_info.ipv6_sctp_offload_supported = true; 2771 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE; 2772 pf->support_multi_tc_pause = true; 2773 2774 return 0; 2775 } 2776 2777 static int 2778 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type) 2779 { 2780 int ret; 2781 2782 switch (media_type) { 2783 case HNS3_MEDIA_TYPE_COPPER: 2784 if (!hns3_dev_get_support(hw, COPPER)) { 2785 PMD_INIT_LOG(ERR, 2786 "Media type is copper, not supported."); 2787 ret = -EOPNOTSUPP; 2788 } else { 2789 ret = 0; 2790 } 2791 break; 2792 case HNS3_MEDIA_TYPE_FIBER: 2793 case HNS3_MEDIA_TYPE_BACKPLANE: 2794 ret = 0; 2795 break; 2796 default: 2797 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type); 2798 ret = -EINVAL; 2799 break; 2800 } 2801 2802 return ret; 2803 } 2804 2805 static int 2806 hns3_get_board_configuration(struct hns3_hw *hw) 2807 { 2808 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2809 struct hns3_pf *pf = &hns->pf; 2810 struct hns3_cfg cfg; 2811 int ret; 2812 2813 memset(&cfg, 0, sizeof(cfg)); 2814 ret = hns3_get_board_cfg(hw, &cfg); 2815 if (ret) { 2816 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 2817 return ret; 2818 } 2819 2820 ret = hns3_check_media_type(hw, cfg.media_type); 2821 if (ret) 2822 return ret; 2823 2824 hw->mac.media_type = cfg.media_type; 2825 hw->rss_size_max = cfg.rss_size_max; 2826 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 2827 hw->mac.phy_addr = cfg.phy_addr; 2828 hw->dcb_info.num_pg = 1; 2829 hw->dcb_info.hw_pfc_map = 0; 2830 2831 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 2832 if (ret) { 2833 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d", 2834 cfg.default_speed, ret); 2835 return ret; 2836 } 2837 2838 pf->tc_max = cfg.tc_num; 2839 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 2840 PMD_INIT_LOG(WARNING, 2841 "Get TC num(%u) from flash, set TC num to 1", 2842 pf->tc_max); 2843 pf->tc_max = 1; 2844 } 2845 2846 /* Dev does not support DCB */ 2847 if (!hns3_dev_get_support(hw, DCB)) { 2848 pf->tc_max = 1; 2849 pf->pfc_max = 0; 2850 } else 2851 pf->pfc_max = pf->tc_max; 2852 2853 hw->dcb_info.num_tc = 1; 2854 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 2855 hw->tqps_num / hw->dcb_info.num_tc); 2856 hns3_set_bit(hw->hw_tc_map, 0, 1); 2857 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 2858 2859 pf->wanted_umv_size = cfg.umv_space; 2860 2861 return ret; 2862 } 2863 2864 static int 2865 hns3_get_configuration(struct hns3_hw *hw) 2866 { 2867 int ret; 2868 2869 ret = hns3_query_function_status(hw); 2870 if (ret) { 2871 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 2872 return ret; 2873 } 2874 2875 /* Get device capability */ 2876 ret = hns3_get_capability(hw); 2877 if (ret) { 2878 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 2879 return ret; 2880 } 2881 2882 /* Get pf resource */ 2883 ret = hns3_query_pf_resource(hw); 2884 if (ret) { 2885 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 2886 return ret; 2887 } 2888 2889 ret = hns3_get_board_configuration(hw); 2890 if (ret) { 2891 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret); 2892 return ret; 2893 } 2894 2895 ret = hns3_query_dev_fec_info(hw); 2896 if (ret) 2897 PMD_INIT_LOG(ERR, 2898 "failed to query FEC information, ret = %d", ret); 2899 2900 return ret; 2901 } 2902 2903 static int 2904 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 2905 uint16_t tqp_vid, bool is_pf) 2906 { 2907 struct hns3_tqp_map_cmd *req; 2908 struct hns3_cmd_desc desc; 2909 int ret; 2910 2911 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 2912 2913 req = (struct hns3_tqp_map_cmd *)desc.data; 2914 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 2915 req->tqp_vf = func_id; 2916 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 2917 if (!is_pf) 2918 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 2919 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 2920 2921 ret = hns3_cmd_send(hw, &desc, 1); 2922 if (ret) 2923 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 2924 2925 return ret; 2926 } 2927 2928 static int 2929 hns3_map_tqp(struct hns3_hw *hw) 2930 { 2931 uint16_t i; 2932 int ret; 2933 2934 /* 2935 * In current version, VF is not supported when PF is driven by DPDK 2936 * driver, so we assign total tqps_num tqps allocated to this port 2937 * to PF. 2938 */ 2939 for (i = 0; i < hw->total_tqps_num; i++) { 2940 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true); 2941 if (ret) 2942 return ret; 2943 } 2944 2945 return 0; 2946 } 2947 2948 static int 2949 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 2950 { 2951 struct hns3_config_mac_speed_dup_cmd *req; 2952 struct hns3_cmd_desc desc; 2953 int ret; 2954 2955 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 2956 2957 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 2958 2959 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 2960 2961 switch (speed) { 2962 case RTE_ETH_SPEED_NUM_10M: 2963 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2964 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 2965 break; 2966 case RTE_ETH_SPEED_NUM_100M: 2967 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2968 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 2969 break; 2970 case RTE_ETH_SPEED_NUM_1G: 2971 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2972 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 2973 break; 2974 case RTE_ETH_SPEED_NUM_10G: 2975 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2976 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 2977 break; 2978 case RTE_ETH_SPEED_NUM_25G: 2979 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2980 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 2981 break; 2982 case RTE_ETH_SPEED_NUM_40G: 2983 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2984 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 2985 break; 2986 case RTE_ETH_SPEED_NUM_50G: 2987 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2988 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 2989 break; 2990 case RTE_ETH_SPEED_NUM_100G: 2991 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2992 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 2993 break; 2994 case RTE_ETH_SPEED_NUM_200G: 2995 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2996 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G); 2997 break; 2998 default: 2999 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 3000 return -EINVAL; 3001 } 3002 3003 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 3004 3005 ret = hns3_cmd_send(hw, &desc, 1); 3006 if (ret) 3007 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 3008 3009 return ret; 3010 } 3011 3012 static int 3013 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3014 { 3015 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3016 struct hns3_pf *pf = &hns->pf; 3017 struct hns3_priv_buf *priv; 3018 uint32_t i, total_size; 3019 3020 total_size = pf->pkt_buf_size; 3021 3022 /* alloc tx buffer for all enabled tc */ 3023 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3024 priv = &buf_alloc->priv_buf[i]; 3025 3026 if (hw->hw_tc_map & BIT(i)) { 3027 if (total_size < pf->tx_buf_size) 3028 return -ENOMEM; 3029 3030 priv->tx_buf_size = pf->tx_buf_size; 3031 } else 3032 priv->tx_buf_size = 0; 3033 3034 total_size -= priv->tx_buf_size; 3035 } 3036 3037 return 0; 3038 } 3039 3040 static int 3041 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3042 { 3043 /* TX buffer size is unit by 128 byte */ 3044 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3045 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3046 struct hns3_tx_buff_alloc_cmd *req; 3047 struct hns3_cmd_desc desc; 3048 uint32_t buf_size; 3049 uint32_t i; 3050 int ret; 3051 3052 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3053 3054 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3055 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3056 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3057 3058 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3059 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3060 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3061 } 3062 3063 ret = hns3_cmd_send(hw, &desc, 1); 3064 if (ret) 3065 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3066 3067 return ret; 3068 } 3069 3070 static int 3071 hns3_get_tc_num(struct hns3_hw *hw) 3072 { 3073 int cnt = 0; 3074 uint8_t i; 3075 3076 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3077 if (hw->hw_tc_map & BIT(i)) 3078 cnt++; 3079 return cnt; 3080 } 3081 3082 static uint32_t 3083 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3084 { 3085 struct hns3_priv_buf *priv; 3086 uint32_t rx_priv = 0; 3087 int i; 3088 3089 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3090 priv = &buf_alloc->priv_buf[i]; 3091 if (priv->enable) 3092 rx_priv += priv->buf_size; 3093 } 3094 return rx_priv; 3095 } 3096 3097 static uint32_t 3098 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3099 { 3100 uint32_t total_tx_size = 0; 3101 uint32_t i; 3102 3103 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3104 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3105 3106 return total_tx_size; 3107 } 3108 3109 /* Get the number of pfc enabled TCs, which have private buffer */ 3110 static int 3111 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3112 { 3113 struct hns3_priv_buf *priv; 3114 int cnt = 0; 3115 uint8_t i; 3116 3117 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3118 priv = &buf_alloc->priv_buf[i]; 3119 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3120 cnt++; 3121 } 3122 3123 return cnt; 3124 } 3125 3126 /* Get the number of pfc disabled TCs, which have private buffer */ 3127 static int 3128 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3129 struct hns3_pkt_buf_alloc *buf_alloc) 3130 { 3131 struct hns3_priv_buf *priv; 3132 int cnt = 0; 3133 uint8_t i; 3134 3135 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3136 priv = &buf_alloc->priv_buf[i]; 3137 if (hw->hw_tc_map & BIT(i) && 3138 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3139 cnt++; 3140 } 3141 3142 return cnt; 3143 } 3144 3145 static bool 3146 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3147 uint32_t rx_all) 3148 { 3149 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3150 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3151 struct hns3_pf *pf = &hns->pf; 3152 uint32_t shared_buf, aligned_mps; 3153 uint32_t rx_priv; 3154 uint8_t tc_num; 3155 uint8_t i; 3156 3157 tc_num = hns3_get_tc_num(hw); 3158 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3159 3160 if (hns3_dev_get_support(hw, DCB)) 3161 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3162 pf->dv_buf_size; 3163 else 3164 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3165 + pf->dv_buf_size; 3166 3167 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3168 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), 3169 HNS3_BUF_SIZE_UNIT); 3170 3171 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3172 if (rx_all < rx_priv + shared_std) 3173 return false; 3174 3175 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3176 buf_alloc->s_buf.buf_size = shared_buf; 3177 if (hns3_dev_get_support(hw, DCB)) { 3178 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3179 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3180 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3181 HNS3_BUF_SIZE_UNIT); 3182 } else { 3183 buf_alloc->s_buf.self.high = 3184 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3185 buf_alloc->s_buf.self.low = aligned_mps; 3186 } 3187 3188 if (hns3_dev_get_support(hw, DCB)) { 3189 hi_thrd = shared_buf - pf->dv_buf_size; 3190 3191 if (tc_num <= NEED_RESERVE_TC_NUM) 3192 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT / 3193 BUF_MAX_PERCENT; 3194 3195 if (tc_num) 3196 hi_thrd = hi_thrd / tc_num; 3197 3198 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); 3199 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3200 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3201 } else { 3202 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3203 lo_thrd = aligned_mps; 3204 } 3205 3206 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3207 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3208 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3209 } 3210 3211 return true; 3212 } 3213 3214 static bool 3215 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3216 struct hns3_pkt_buf_alloc *buf_alloc) 3217 { 3218 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3219 struct hns3_pf *pf = &hns->pf; 3220 struct hns3_priv_buf *priv; 3221 uint32_t aligned_mps; 3222 uint32_t rx_all; 3223 uint8_t i; 3224 3225 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3226 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3227 3228 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3229 priv = &buf_alloc->priv_buf[i]; 3230 3231 priv->enable = 0; 3232 priv->wl.low = 0; 3233 priv->wl.high = 0; 3234 priv->buf_size = 0; 3235 3236 if (!(hw->hw_tc_map & BIT(i))) 3237 continue; 3238 3239 priv->enable = 1; 3240 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3241 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3242 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3243 HNS3_BUF_SIZE_UNIT); 3244 } else { 3245 priv->wl.low = 0; 3246 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3247 aligned_mps; 3248 } 3249 3250 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3251 } 3252 3253 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3254 } 3255 3256 static bool 3257 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3258 struct hns3_pkt_buf_alloc *buf_alloc) 3259 { 3260 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3261 struct hns3_pf *pf = &hns->pf; 3262 struct hns3_priv_buf *priv; 3263 int no_pfc_priv_num; 3264 uint32_t rx_all; 3265 uint8_t mask; 3266 int i; 3267 3268 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3269 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3270 3271 /* let the last to be cleared first */ 3272 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3273 priv = &buf_alloc->priv_buf[i]; 3274 mask = BIT((uint8_t)i); 3275 if (hw->hw_tc_map & mask && 3276 !(hw->dcb_info.hw_pfc_map & mask)) { 3277 /* Clear the no pfc TC private buffer */ 3278 priv->wl.low = 0; 3279 priv->wl.high = 0; 3280 priv->buf_size = 0; 3281 priv->enable = 0; 3282 no_pfc_priv_num--; 3283 } 3284 3285 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3286 no_pfc_priv_num == 0) 3287 break; 3288 } 3289 3290 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3291 } 3292 3293 static bool 3294 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3295 struct hns3_pkt_buf_alloc *buf_alloc) 3296 { 3297 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3298 struct hns3_pf *pf = &hns->pf; 3299 struct hns3_priv_buf *priv; 3300 uint32_t rx_all; 3301 int pfc_priv_num; 3302 uint8_t mask; 3303 int i; 3304 3305 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3306 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3307 3308 /* let the last to be cleared first */ 3309 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3310 priv = &buf_alloc->priv_buf[i]; 3311 mask = BIT((uint8_t)i); 3312 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) { 3313 /* Reduce the number of pfc TC with private buffer */ 3314 priv->wl.low = 0; 3315 priv->enable = 0; 3316 priv->wl.high = 0; 3317 priv->buf_size = 0; 3318 pfc_priv_num--; 3319 } 3320 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3321 pfc_priv_num == 0) 3322 break; 3323 } 3324 3325 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3326 } 3327 3328 static bool 3329 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3330 struct hns3_pkt_buf_alloc *buf_alloc) 3331 { 3332 #define COMPENSATE_BUFFER 0x3C00 3333 #define COMPENSATE_HALF_MPS_NUM 5 3334 #define PRIV_WL_GAP 0x1800 3335 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3336 struct hns3_pf *pf = &hns->pf; 3337 uint32_t tc_num = hns3_get_tc_num(hw); 3338 uint32_t half_mps = pf->mps >> 1; 3339 struct hns3_priv_buf *priv; 3340 uint32_t min_rx_priv; 3341 uint32_t rx_priv; 3342 uint8_t i; 3343 3344 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3345 if (tc_num) 3346 rx_priv = rx_priv / tc_num; 3347 3348 if (tc_num <= NEED_RESERVE_TC_NUM) 3349 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3350 3351 /* 3352 * Minimum value of private buffer in rx direction (min_rx_priv) is 3353 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3354 * buffer if rx_priv is greater than min_rx_priv. 3355 */ 3356 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3357 COMPENSATE_HALF_MPS_NUM * half_mps; 3358 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3359 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3360 if (rx_priv < min_rx_priv) 3361 return false; 3362 3363 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3364 priv = &buf_alloc->priv_buf[i]; 3365 priv->enable = 0; 3366 priv->wl.low = 0; 3367 priv->wl.high = 0; 3368 priv->buf_size = 0; 3369 3370 if (!(hw->hw_tc_map & BIT(i))) 3371 continue; 3372 3373 priv->enable = 1; 3374 priv->buf_size = rx_priv; 3375 priv->wl.high = rx_priv - pf->dv_buf_size; 3376 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3377 } 3378 3379 buf_alloc->s_buf.buf_size = 0; 3380 3381 return true; 3382 } 3383 3384 /* 3385 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3386 * @hw: pointer to struct hns3_hw 3387 * @buf_alloc: pointer to buffer calculation data 3388 * @return: 0: calculate successful, negative: fail 3389 */ 3390 static int 3391 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3392 { 3393 /* When DCB is not supported, rx private buffer is not allocated. */ 3394 if (!hns3_dev_get_support(hw, DCB)) { 3395 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3396 struct hns3_pf *pf = &hns->pf; 3397 uint32_t rx_all = pf->pkt_buf_size; 3398 3399 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3400 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3401 return -ENOMEM; 3402 3403 return 0; 3404 } 3405 3406 /* 3407 * Try to allocate privated packet buffer for all TCs without share 3408 * buffer. 3409 */ 3410 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3411 return 0; 3412 3413 /* 3414 * Try to allocate privated packet buffer for all TCs with share 3415 * buffer. 3416 */ 3417 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3418 return 0; 3419 3420 /* 3421 * For different application scenes, the enabled port number, TC number 3422 * and no_drop TC number are different. In order to obtain the better 3423 * performance, software could allocate the buffer size and configure 3424 * the waterline by trying to decrease the private buffer size according 3425 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc 3426 * enabled tc. 3427 */ 3428 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 3429 return 0; 3430 3431 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 3432 return 0; 3433 3434 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 3435 return 0; 3436 3437 return -ENOMEM; 3438 } 3439 3440 static int 3441 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3442 { 3443 struct hns3_rx_priv_buff_cmd *req; 3444 struct hns3_cmd_desc desc; 3445 uint32_t buf_size; 3446 int ret; 3447 int i; 3448 3449 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 3450 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 3451 3452 /* Alloc private buffer TCs */ 3453 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3454 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 3455 3456 req->buf_num[i] = 3457 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 3458 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 3459 } 3460 3461 buf_size = buf_alloc->s_buf.buf_size; 3462 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 3463 (1 << HNS3_TC0_PRI_BUF_EN_B)); 3464 3465 ret = hns3_cmd_send(hw, &desc, 1); 3466 if (ret) 3467 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 3468 3469 return ret; 3470 } 3471 3472 static int 3473 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3474 { 3475 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 3476 struct hns3_rx_priv_wl_buf *req; 3477 struct hns3_priv_buf *priv; 3478 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 3479 int i, j; 3480 int ret; 3481 3482 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 3483 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 3484 false); 3485 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 3486 3487 /* The first descriptor set the NEXT bit to 1 */ 3488 if (i == 0) 3489 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3490 else 3491 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3492 3493 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3494 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 3495 3496 priv = &buf_alloc->priv_buf[idx]; 3497 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 3498 HNS3_BUF_UNIT_S); 3499 req->tc_wl[j].high |= 3500 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3501 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 3502 HNS3_BUF_UNIT_S); 3503 req->tc_wl[j].low |= 3504 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3505 } 3506 } 3507 3508 /* Send 2 descriptor at one time */ 3509 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 3510 if (ret) 3511 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 3512 ret); 3513 return ret; 3514 } 3515 3516 static int 3517 hns3_common_thrd_config(struct hns3_hw *hw, 3518 struct hns3_pkt_buf_alloc *buf_alloc) 3519 { 3520 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 3521 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 3522 struct hns3_rx_com_thrd *req; 3523 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 3524 struct hns3_tc_thrd *tc; 3525 int tc_idx; 3526 int i, j; 3527 int ret; 3528 3529 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 3530 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 3531 false); 3532 req = (struct hns3_rx_com_thrd *)&desc[i].data; 3533 3534 /* The first descriptor set the NEXT bit to 1 */ 3535 if (i == 0) 3536 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3537 else 3538 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3539 3540 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3541 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 3542 tc = &s_buf->tc_thrd[tc_idx]; 3543 3544 req->com_thrd[j].high = 3545 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 3546 req->com_thrd[j].high |= 3547 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3548 req->com_thrd[j].low = 3549 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 3550 req->com_thrd[j].low |= 3551 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3552 } 3553 } 3554 3555 /* Send 2 descriptors at one time */ 3556 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 3557 if (ret) 3558 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 3559 3560 return ret; 3561 } 3562 3563 static int 3564 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3565 { 3566 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 3567 struct hns3_rx_com_wl *req; 3568 struct hns3_cmd_desc desc; 3569 int ret; 3570 3571 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 3572 3573 req = (struct hns3_rx_com_wl *)desc.data; 3574 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 3575 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3576 3577 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 3578 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3579 3580 ret = hns3_cmd_send(hw, &desc, 1); 3581 if (ret) 3582 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 3583 3584 return ret; 3585 } 3586 3587 int 3588 hns3_buffer_alloc(struct hns3_hw *hw) 3589 { 3590 struct hns3_pkt_buf_alloc pkt_buf; 3591 int ret; 3592 3593 memset(&pkt_buf, 0, sizeof(pkt_buf)); 3594 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 3595 if (ret) { 3596 PMD_INIT_LOG(ERR, 3597 "could not calc tx buffer size for all TCs %d", 3598 ret); 3599 return ret; 3600 } 3601 3602 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 3603 if (ret) { 3604 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 3605 return ret; 3606 } 3607 3608 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 3609 if (ret) { 3610 PMD_INIT_LOG(ERR, 3611 "could not calc rx priv buffer size for all TCs %d", 3612 ret); 3613 return ret; 3614 } 3615 3616 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 3617 if (ret) { 3618 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 3619 return ret; 3620 } 3621 3622 if (hns3_dev_get_support(hw, DCB)) { 3623 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 3624 if (ret) { 3625 PMD_INIT_LOG(ERR, 3626 "could not configure rx private waterline %d", 3627 ret); 3628 return ret; 3629 } 3630 3631 ret = hns3_common_thrd_config(hw, &pkt_buf); 3632 if (ret) { 3633 PMD_INIT_LOG(ERR, 3634 "could not configure common threshold %d", 3635 ret); 3636 return ret; 3637 } 3638 } 3639 3640 ret = hns3_common_wl_config(hw, &pkt_buf); 3641 if (ret) 3642 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 3643 ret); 3644 3645 return ret; 3646 } 3647 3648 static int 3649 hns3_mac_init(struct hns3_hw *hw) 3650 { 3651 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3652 struct hns3_mac *mac = &hw->mac; 3653 struct hns3_pf *pf = &hns->pf; 3654 int ret; 3655 3656 pf->support_sfp_query = true; 3657 mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 3658 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 3659 if (ret) { 3660 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 3661 return ret; 3662 } 3663 3664 mac->link_status = RTE_ETH_LINK_DOWN; 3665 3666 return hns3_config_mtu(hw, pf->mps); 3667 } 3668 3669 static int 3670 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 3671 { 3672 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 3673 #define HNS3_ETHERTYPE_ALREADY_ADD 1 3674 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 3675 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 3676 int return_status; 3677 3678 if (cmdq_resp) { 3679 PMD_INIT_LOG(ERR, 3680 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 3681 cmdq_resp); 3682 return -EIO; 3683 } 3684 3685 switch (resp_code) { 3686 case HNS3_ETHERTYPE_SUCCESS_ADD: 3687 case HNS3_ETHERTYPE_ALREADY_ADD: 3688 return_status = 0; 3689 break; 3690 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 3691 PMD_INIT_LOG(ERR, 3692 "add mac ethertype failed for manager table overflow."); 3693 return_status = -EIO; 3694 break; 3695 case HNS3_ETHERTYPE_KEY_CONFLICT: 3696 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 3697 return_status = -EIO; 3698 break; 3699 default: 3700 PMD_INIT_LOG(ERR, 3701 "add mac ethertype failed for undefined, code=%u.", 3702 resp_code); 3703 return_status = -EIO; 3704 break; 3705 } 3706 3707 return return_status; 3708 } 3709 3710 static int 3711 hns3_add_mgr_tbl(struct hns3_hw *hw, 3712 const struct hns3_mac_mgr_tbl_entry_cmd *req) 3713 { 3714 struct hns3_cmd_desc desc; 3715 uint8_t resp_code; 3716 uint16_t retval; 3717 int ret; 3718 3719 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 3720 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 3721 3722 ret = hns3_cmd_send(hw, &desc, 1); 3723 if (ret) { 3724 PMD_INIT_LOG(ERR, 3725 "add mac ethertype failed for cmd_send, ret =%d.", 3726 ret); 3727 return ret; 3728 } 3729 3730 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 3731 retval = rte_le_to_cpu_16(desc.retval); 3732 3733 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 3734 } 3735 3736 static void 3737 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 3738 int *table_item_num) 3739 { 3740 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 3741 3742 /* 3743 * In current version, we add one item in management table as below: 3744 * 0x0180C200000E -- LLDP MC address 3745 */ 3746 tbl = mgr_table; 3747 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 3748 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 3749 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 3750 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 3751 tbl->i_port_bitmap = 0x1; 3752 *table_item_num = 1; 3753 } 3754 3755 static int 3756 hns3_init_mgr_tbl(struct hns3_hw *hw) 3757 { 3758 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 3759 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 3760 int table_item_num; 3761 int ret; 3762 int i; 3763 3764 memset(mgr_table, 0, sizeof(mgr_table)); 3765 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 3766 for (i = 0; i < table_item_num; i++) { 3767 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 3768 if (ret) { 3769 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 3770 ret); 3771 return ret; 3772 } 3773 } 3774 3775 return 0; 3776 } 3777 3778 static void 3779 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 3780 bool en_mc, bool en_bc, int vport_id) 3781 { 3782 if (!param) 3783 return; 3784 3785 memset(param, 0, sizeof(struct hns3_promisc_param)); 3786 if (en_uc) 3787 param->enable = HNS3_PROMISC_EN_UC; 3788 if (en_mc) 3789 param->enable |= HNS3_PROMISC_EN_MC; 3790 if (en_bc) 3791 param->enable |= HNS3_PROMISC_EN_BC; 3792 param->vf_id = vport_id; 3793 } 3794 3795 static int 3796 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 3797 { 3798 struct hns3_promisc_cfg_cmd *req; 3799 struct hns3_cmd_desc desc; 3800 int ret; 3801 3802 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 3803 3804 req = (struct hns3_promisc_cfg_cmd *)desc.data; 3805 req->vf_id = param->vf_id; 3806 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 3807 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 3808 3809 ret = hns3_cmd_send(hw, &desc, 1); 3810 if (ret) 3811 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 3812 3813 return ret; 3814 } 3815 3816 static int 3817 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 3818 { 3819 struct hns3_promisc_param param; 3820 bool en_bc_pmc = true; 3821 uint8_t vf_id; 3822 3823 /* 3824 * In current version VF is not supported when PF is driven by DPDK 3825 * driver, just need to configure parameters for PF vport. 3826 */ 3827 vf_id = HNS3_PF_FUNC_ID; 3828 3829 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 3830 return hns3_cmd_set_promisc_mode(hw, ¶m); 3831 } 3832 3833 static int 3834 hns3_promisc_init(struct hns3_hw *hw) 3835 { 3836 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3837 struct hns3_pf *pf = &hns->pf; 3838 struct hns3_promisc_param param; 3839 uint16_t func_id; 3840 int ret; 3841 3842 ret = hns3_set_promisc_mode(hw, false, false); 3843 if (ret) { 3844 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 3845 return ret; 3846 } 3847 3848 /* 3849 * In current version VFs are not supported when PF is driven by DPDK 3850 * driver. After PF has been taken over by DPDK, the original VF will 3851 * be invalid. So, there is a possibility of entry residues. It should 3852 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 3853 * during init. 3854 */ 3855 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 3856 hns3_promisc_param_init(¶m, false, false, false, func_id); 3857 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 3858 if (ret) { 3859 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode," 3860 " ret = %d", func_id, ret); 3861 return ret; 3862 } 3863 } 3864 3865 return 0; 3866 } 3867 3868 static void 3869 hns3_promisc_uninit(struct hns3_hw *hw) 3870 { 3871 struct hns3_promisc_param param; 3872 uint16_t func_id; 3873 int ret; 3874 3875 func_id = HNS3_PF_FUNC_ID; 3876 3877 /* 3878 * In current version VFs are not supported when PF is driven by 3879 * DPDK driver, and VFs' promisc mode status has been cleared during 3880 * init and their status will not change. So just clear PF's promisc 3881 * mode status during uninit. 3882 */ 3883 hns3_promisc_param_init(¶m, false, false, false, func_id); 3884 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 3885 if (ret) 3886 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 3887 " uninit, ret = %d", ret); 3888 } 3889 3890 static int 3891 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 3892 { 3893 bool allmulti = dev->data->all_multicast ? true : false; 3894 struct hns3_adapter *hns = dev->data->dev_private; 3895 struct hns3_hw *hw = &hns->hw; 3896 uint64_t offloads; 3897 int err; 3898 int ret; 3899 3900 rte_spinlock_lock(&hw->lock); 3901 ret = hns3_set_promisc_mode(hw, true, true); 3902 if (ret) { 3903 rte_spinlock_unlock(&hw->lock); 3904 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 3905 ret); 3906 return ret; 3907 } 3908 3909 /* 3910 * When promiscuous mode was enabled, disable the vlan filter to let 3911 * all packets coming in in the receiving direction. 3912 */ 3913 offloads = dev->data->dev_conf.rxmode.offloads; 3914 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 3915 ret = hns3_enable_vlan_filter(hns, false); 3916 if (ret) { 3917 hns3_err(hw, "failed to enable promiscuous mode due to " 3918 "failure to disable vlan filter, ret = %d", 3919 ret); 3920 err = hns3_set_promisc_mode(hw, false, allmulti); 3921 if (err) 3922 hns3_err(hw, "failed to restore promiscuous " 3923 "status after disable vlan filter " 3924 "failed during enabling promiscuous " 3925 "mode, ret = %d", ret); 3926 } 3927 } 3928 3929 rte_spinlock_unlock(&hw->lock); 3930 3931 return ret; 3932 } 3933 3934 static int 3935 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 3936 { 3937 bool allmulti = dev->data->all_multicast ? true : false; 3938 struct hns3_adapter *hns = dev->data->dev_private; 3939 struct hns3_hw *hw = &hns->hw; 3940 uint64_t offloads; 3941 int err; 3942 int ret; 3943 3944 /* If now in all_multicast mode, must remain in all_multicast mode. */ 3945 rte_spinlock_lock(&hw->lock); 3946 ret = hns3_set_promisc_mode(hw, false, allmulti); 3947 if (ret) { 3948 rte_spinlock_unlock(&hw->lock); 3949 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 3950 ret); 3951 return ret; 3952 } 3953 /* when promiscuous mode was disabled, restore the vlan filter status */ 3954 offloads = dev->data->dev_conf.rxmode.offloads; 3955 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 3956 ret = hns3_enable_vlan_filter(hns, true); 3957 if (ret) { 3958 hns3_err(hw, "failed to disable promiscuous mode due to" 3959 " failure to restore vlan filter, ret = %d", 3960 ret); 3961 err = hns3_set_promisc_mode(hw, true, true); 3962 if (err) 3963 hns3_err(hw, "failed to restore promiscuous " 3964 "status after enabling vlan filter " 3965 "failed during disabling promiscuous " 3966 "mode, ret = %d", ret); 3967 } 3968 } 3969 rte_spinlock_unlock(&hw->lock); 3970 3971 return ret; 3972 } 3973 3974 static int 3975 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 3976 { 3977 struct hns3_adapter *hns = dev->data->dev_private; 3978 struct hns3_hw *hw = &hns->hw; 3979 int ret; 3980 3981 if (dev->data->promiscuous) 3982 return 0; 3983 3984 rte_spinlock_lock(&hw->lock); 3985 ret = hns3_set_promisc_mode(hw, false, true); 3986 rte_spinlock_unlock(&hw->lock); 3987 if (ret) 3988 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 3989 ret); 3990 3991 return ret; 3992 } 3993 3994 static int 3995 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 3996 { 3997 struct hns3_adapter *hns = dev->data->dev_private; 3998 struct hns3_hw *hw = &hns->hw; 3999 int ret; 4000 4001 /* If now in promiscuous mode, must remain in all_multicast mode. */ 4002 if (dev->data->promiscuous) 4003 return 0; 4004 4005 rte_spinlock_lock(&hw->lock); 4006 ret = hns3_set_promisc_mode(hw, false, false); 4007 rte_spinlock_unlock(&hw->lock); 4008 if (ret) 4009 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4010 ret); 4011 4012 return ret; 4013 } 4014 4015 static int 4016 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4017 { 4018 struct hns3_hw *hw = &hns->hw; 4019 bool allmulti = hw->data->all_multicast ? true : false; 4020 int ret; 4021 4022 if (hw->data->promiscuous) { 4023 ret = hns3_set_promisc_mode(hw, true, true); 4024 if (ret) 4025 hns3_err(hw, "failed to restore promiscuous mode, " 4026 "ret = %d", ret); 4027 return ret; 4028 } 4029 4030 ret = hns3_set_promisc_mode(hw, false, allmulti); 4031 if (ret) 4032 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4033 ret); 4034 return ret; 4035 } 4036 4037 static int 4038 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) 4039 { 4040 struct hns3_sfp_info_cmd *resp; 4041 struct hns3_cmd_desc desc; 4042 int ret; 4043 4044 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 4045 resp = (struct hns3_sfp_info_cmd *)desc.data; 4046 resp->query_type = HNS3_ACTIVE_QUERY; 4047 4048 ret = hns3_cmd_send(hw, &desc, 1); 4049 if (ret == -EOPNOTSUPP) { 4050 hns3_warn(hw, "firmware does not support get SFP info," 4051 " ret = %d.", ret); 4052 return ret; 4053 } else if (ret) { 4054 hns3_err(hw, "get sfp info failed, ret = %d.", ret); 4055 return ret; 4056 } 4057 4058 /* 4059 * In some case, the speed of MAC obtained from firmware may be 0, it 4060 * shouldn't be set to mac->speed. 4061 */ 4062 if (!rte_le_to_cpu_32(resp->sfp_speed)) 4063 return 0; 4064 4065 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed); 4066 /* 4067 * if resp->supported_speed is 0, it means it's an old version 4068 * firmware, do not update these params. 4069 */ 4070 if (resp->supported_speed) { 4071 mac_info->query_type = HNS3_ACTIVE_QUERY; 4072 mac_info->supported_speed = 4073 rte_le_to_cpu_32(resp->supported_speed); 4074 mac_info->support_autoneg = resp->autoneg_ability; 4075 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED 4076 : RTE_ETH_LINK_AUTONEG; 4077 } else { 4078 mac_info->query_type = HNS3_DEFAULT_QUERY; 4079 } 4080 4081 return 0; 4082 } 4083 4084 static uint8_t 4085 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4086 { 4087 if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M)) 4088 duplex = RTE_ETH_LINK_FULL_DUPLEX; 4089 4090 return duplex; 4091 } 4092 4093 static int 4094 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4095 { 4096 struct hns3_mac *mac = &hw->mac; 4097 int ret; 4098 4099 duplex = hns3_check_speed_dup(duplex, speed); 4100 if (mac->link_speed == speed && mac->link_duplex == duplex) 4101 return 0; 4102 4103 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4104 if (ret) 4105 return ret; 4106 4107 ret = hns3_port_shaper_update(hw, speed); 4108 if (ret) 4109 return ret; 4110 4111 mac->link_speed = speed; 4112 mac->link_duplex = duplex; 4113 4114 return 0; 4115 } 4116 4117 static int 4118 hns3_update_fiber_link_info(struct hns3_hw *hw) 4119 { 4120 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 4121 struct hns3_mac *mac = &hw->mac; 4122 struct hns3_mac mac_info; 4123 int ret; 4124 4125 /* If firmware do not support get SFP/qSFP speed, return directly */ 4126 if (!pf->support_sfp_query) 4127 return 0; 4128 4129 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4130 ret = hns3_get_sfp_info(hw, &mac_info); 4131 if (ret == -EOPNOTSUPP) { 4132 pf->support_sfp_query = false; 4133 return ret; 4134 } else if (ret) 4135 return ret; 4136 4137 /* Do nothing if no SFP */ 4138 if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE) 4139 return 0; 4140 4141 /* 4142 * If query_type is HNS3_ACTIVE_QUERY, it is no need 4143 * to reconfigure the speed of MAC. Otherwise, it indicates 4144 * that the current firmware only supports to obtain the 4145 * speed of the SFP, and the speed of MAC needs to reconfigure. 4146 */ 4147 mac->query_type = mac_info.query_type; 4148 if (mac->query_type == HNS3_ACTIVE_QUERY) { 4149 if (mac_info.link_speed != mac->link_speed) { 4150 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4151 if (ret) 4152 return ret; 4153 } 4154 4155 mac->link_speed = mac_info.link_speed; 4156 mac->supported_speed = mac_info.supported_speed; 4157 mac->support_autoneg = mac_info.support_autoneg; 4158 mac->link_autoneg = mac_info.link_autoneg; 4159 4160 return 0; 4161 } 4162 4163 /* Config full duplex for SFP */ 4164 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, 4165 RTE_ETH_LINK_FULL_DUPLEX); 4166 } 4167 4168 static void 4169 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac) 4170 { 4171 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f 4172 4173 struct hns3_phy_params_bd0_cmd *req; 4174 uint32_t supported; 4175 4176 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 4177 mac->link_speed = rte_le_to_cpu_32(req->speed); 4178 mac->link_duplex = hns3_get_bit(req->duplex, 4179 HNS3_PHY_DUPLEX_CFG_B); 4180 mac->link_autoneg = hns3_get_bit(req->autoneg, 4181 HNS3_PHY_AUTONEG_CFG_B); 4182 mac->advertising = rte_le_to_cpu_32(req->advertising); 4183 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising); 4184 supported = rte_le_to_cpu_32(req->supported); 4185 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK; 4186 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT); 4187 } 4188 4189 static int 4190 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac) 4191 { 4192 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 4193 uint16_t i; 4194 int ret; 4195 4196 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 4197 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 4198 true); 4199 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4200 } 4201 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true); 4202 4203 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 4204 if (ret) { 4205 hns3_err(hw, "get phy parameters failed, ret = %d.", ret); 4206 return ret; 4207 } 4208 4209 hns3_parse_copper_phy_params(desc, mac); 4210 4211 return 0; 4212 } 4213 4214 static int 4215 hns3_update_copper_link_info(struct hns3_hw *hw) 4216 { 4217 struct hns3_mac *mac = &hw->mac; 4218 struct hns3_mac mac_info; 4219 int ret; 4220 4221 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4222 ret = hns3_get_copper_phy_params(hw, &mac_info); 4223 if (ret) 4224 return ret; 4225 4226 if (mac_info.link_speed != mac->link_speed) { 4227 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4228 if (ret) 4229 return ret; 4230 } 4231 4232 mac->link_speed = mac_info.link_speed; 4233 mac->link_duplex = mac_info.link_duplex; 4234 mac->link_autoneg = mac_info.link_autoneg; 4235 mac->supported_speed = mac_info.supported_speed; 4236 mac->advertising = mac_info.advertising; 4237 mac->lp_advertising = mac_info.lp_advertising; 4238 mac->support_autoneg = mac_info.support_autoneg; 4239 4240 return 0; 4241 } 4242 4243 static int 4244 hns3_update_link_info(struct rte_eth_dev *eth_dev) 4245 { 4246 struct hns3_adapter *hns = eth_dev->data->dev_private; 4247 struct hns3_hw *hw = &hns->hw; 4248 4249 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) 4250 return hns3_update_copper_link_info(hw); 4251 4252 return hns3_update_fiber_link_info(hw); 4253 } 4254 4255 static int 4256 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4257 { 4258 struct hns3_config_mac_mode_cmd *req; 4259 struct hns3_cmd_desc desc; 4260 uint32_t loop_en = 0; 4261 uint8_t val = 0; 4262 int ret; 4263 4264 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4265 4266 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4267 if (enable) 4268 val = 1; 4269 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4270 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4271 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4272 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4273 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4274 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4275 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4276 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4277 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4278 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4279 4280 /* 4281 * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC 4282 * when receiving frames. Otherwise, CRC will be stripped. 4283 */ 4284 if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) 4285 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0); 4286 else 4287 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4288 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4289 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4290 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4291 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4292 4293 ret = hns3_cmd_send(hw, &desc, 1); 4294 if (ret) 4295 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4296 4297 return ret; 4298 } 4299 4300 static int 4301 hns3_get_mac_link_status(struct hns3_hw *hw) 4302 { 4303 struct hns3_link_status_cmd *req; 4304 struct hns3_cmd_desc desc; 4305 int link_status; 4306 int ret; 4307 4308 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4309 ret = hns3_cmd_send(hw, &desc, 1); 4310 if (ret) { 4311 hns3_err(hw, "get link status cmd failed %d", ret); 4312 return RTE_ETH_LINK_DOWN; 4313 } 4314 4315 req = (struct hns3_link_status_cmd *)desc.data; 4316 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4317 4318 return !!link_status; 4319 } 4320 4321 static bool 4322 hns3_update_link_status(struct hns3_hw *hw) 4323 { 4324 int state; 4325 4326 state = hns3_get_mac_link_status(hw); 4327 if (state != hw->mac.link_status) { 4328 hw->mac.link_status = state; 4329 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4330 return true; 4331 } 4332 4333 return false; 4334 } 4335 4336 void 4337 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query) 4338 { 4339 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4340 struct rte_eth_link new_link; 4341 int ret; 4342 4343 if (query) 4344 hns3_update_port_link_info(dev); 4345 4346 memset(&new_link, 0, sizeof(new_link)); 4347 hns3_setup_linkstatus(dev, &new_link); 4348 4349 ret = rte_eth_linkstatus_set(dev, &new_link); 4350 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0) 4351 hns3_start_report_lse(dev); 4352 } 4353 4354 static void 4355 hns3_service_handler(void *param) 4356 { 4357 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 4358 struct hns3_adapter *hns = eth_dev->data->dev_private; 4359 struct hns3_hw *hw = &hns->hw; 4360 4361 if (!hns3_is_reset_pending(hns)) { 4362 hns3_update_linkstatus_and_event(hw, true); 4363 hns3_update_hw_stats(hw); 4364 } else { 4365 hns3_warn(hw, "Cancel the query when reset is pending"); 4366 } 4367 4368 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4369 } 4370 4371 static int 4372 hns3_init_hardware(struct hns3_adapter *hns) 4373 { 4374 struct hns3_hw *hw = &hns->hw; 4375 int ret; 4376 4377 /* 4378 * All queue-related HW operations must be performed after the TCAM 4379 * table is configured. 4380 */ 4381 ret = hns3_map_tqp(hw); 4382 if (ret) { 4383 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 4384 return ret; 4385 } 4386 4387 ret = hns3_init_umv_space(hw); 4388 if (ret) { 4389 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 4390 return ret; 4391 } 4392 4393 ret = hns3_mac_init(hw); 4394 if (ret) { 4395 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 4396 goto err_mac_init; 4397 } 4398 4399 ret = hns3_init_mgr_tbl(hw); 4400 if (ret) { 4401 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 4402 goto err_mac_init; 4403 } 4404 4405 ret = hns3_promisc_init(hw); 4406 if (ret) { 4407 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 4408 ret); 4409 goto err_mac_init; 4410 } 4411 4412 ret = hns3_init_vlan_config(hns); 4413 if (ret) { 4414 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 4415 goto err_mac_init; 4416 } 4417 4418 ret = hns3_dcb_init(hw); 4419 if (ret) { 4420 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 4421 goto err_mac_init; 4422 } 4423 4424 ret = hns3_init_fd_config(hns); 4425 if (ret) { 4426 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 4427 goto err_mac_init; 4428 } 4429 4430 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 4431 if (ret) { 4432 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 4433 goto err_mac_init; 4434 } 4435 4436 ret = hns3_config_gro(hw, false); 4437 if (ret) { 4438 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 4439 goto err_mac_init; 4440 } 4441 4442 /* 4443 * In the initialization clearing the all hardware mapping relationship 4444 * configurations between queues and interrupt vectors is needed, so 4445 * some error caused by the residual configurations, such as the 4446 * unexpected interrupt, can be avoid. 4447 */ 4448 ret = hns3_init_ring_with_vector(hw); 4449 if (ret) { 4450 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 4451 goto err_mac_init; 4452 } 4453 4454 return 0; 4455 4456 err_mac_init: 4457 hns3_uninit_umv_space(hw); 4458 return ret; 4459 } 4460 4461 static int 4462 hns3_clear_hw(struct hns3_hw *hw) 4463 { 4464 struct hns3_cmd_desc desc; 4465 int ret; 4466 4467 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); 4468 4469 ret = hns3_cmd_send(hw, &desc, 1); 4470 if (ret && ret != -EOPNOTSUPP) 4471 return ret; 4472 4473 return 0; 4474 } 4475 4476 static void 4477 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) 4478 { 4479 uint32_t val; 4480 4481 /* 4482 * The new firmware support report more hardware error types by 4483 * msix mode. These errors are defined as RAS errors in hardware 4484 * and belong to a different type from the MSI-x errors processed 4485 * by the network driver. 4486 * 4487 * Network driver should open the new error report on initialization. 4488 */ 4489 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 4490 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); 4491 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); 4492 } 4493 4494 static uint32_t 4495 hns3_set_firber_default_support_speed(struct hns3_hw *hw) 4496 { 4497 struct hns3_mac *mac = &hw->mac; 4498 4499 switch (mac->link_speed) { 4500 case RTE_ETH_SPEED_NUM_1G: 4501 return HNS3_FIBER_LINK_SPEED_1G_BIT; 4502 case RTE_ETH_SPEED_NUM_10G: 4503 return HNS3_FIBER_LINK_SPEED_10G_BIT; 4504 case RTE_ETH_SPEED_NUM_25G: 4505 return HNS3_FIBER_LINK_SPEED_25G_BIT; 4506 case RTE_ETH_SPEED_NUM_40G: 4507 return HNS3_FIBER_LINK_SPEED_40G_BIT; 4508 case RTE_ETH_SPEED_NUM_50G: 4509 return HNS3_FIBER_LINK_SPEED_50G_BIT; 4510 case RTE_ETH_SPEED_NUM_100G: 4511 return HNS3_FIBER_LINK_SPEED_100G_BIT; 4512 case RTE_ETH_SPEED_NUM_200G: 4513 return HNS3_FIBER_LINK_SPEED_200G_BIT; 4514 default: 4515 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed); 4516 return 0; 4517 } 4518 } 4519 4520 /* 4521 * Validity of supported_speed for fiber and copper media type can be 4522 * guaranteed by the following policy: 4523 * Copper: 4524 * Although the initialization of the phy in the firmware may not be 4525 * completed, the firmware can guarantees that the supported_speed is 4526 * an valid value. 4527 * Firber: 4528 * If the version of firmware supports the active query way of the 4529 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained 4530 * through it. If unsupported, use the SFP's speed as the value of the 4531 * supported_speed. 4532 */ 4533 static int 4534 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev) 4535 { 4536 struct hns3_adapter *hns = eth_dev->data->dev_private; 4537 struct hns3_hw *hw = &hns->hw; 4538 struct hns3_mac *mac = &hw->mac; 4539 int ret; 4540 4541 ret = hns3_update_link_info(eth_dev); 4542 if (ret) 4543 return ret; 4544 4545 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER || 4546 mac->media_type == HNS3_MEDIA_TYPE_BACKPLANE) { 4547 /* 4548 * Some firmware does not support the report of supported_speed, 4549 * and only report the effective speed of SFP/backplane. In this 4550 * case, it is necessary to use the SFP/backplane's speed as the 4551 * supported_speed. 4552 */ 4553 if (mac->supported_speed == 0) 4554 mac->supported_speed = 4555 hns3_set_firber_default_support_speed(hw); 4556 } 4557 4558 return 0; 4559 } 4560 4561 static void 4562 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns) 4563 { 4564 struct hns3_mac *mac = &hns->hw.mac; 4565 4566 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) { 4567 hns->pf.support_fc_autoneg = true; 4568 return; 4569 } 4570 4571 /* 4572 * Flow control auto-negotiation requires the cooperation of the driver 4573 * and firmware. Currently, the optical port does not support flow 4574 * control auto-negotiation. 4575 */ 4576 hns->pf.support_fc_autoneg = false; 4577 } 4578 4579 static int 4580 hns3_init_pf(struct rte_eth_dev *eth_dev) 4581 { 4582 struct rte_device *dev = eth_dev->device; 4583 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4584 struct hns3_adapter *hns = eth_dev->data->dev_private; 4585 struct hns3_hw *hw = &hns->hw; 4586 int ret; 4587 4588 PMD_INIT_FUNC_TRACE(); 4589 4590 /* Get hardware io base address from pcie BAR2 IO space */ 4591 hw->io_base = pci_dev->mem_resource[2].addr; 4592 4593 /* Firmware command queue initialize */ 4594 ret = hns3_cmd_init_queue(hw); 4595 if (ret) { 4596 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 4597 goto err_cmd_init_queue; 4598 } 4599 4600 hns3_clear_all_event_cause(hw); 4601 4602 /* Firmware command initialize */ 4603 ret = hns3_cmd_init(hw); 4604 if (ret) { 4605 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 4606 goto err_cmd_init; 4607 } 4608 4609 hns3_tx_push_init(eth_dev); 4610 4611 /* 4612 * To ensure that the hardware environment is clean during 4613 * initialization, the driver actively clear the hardware environment 4614 * during initialization, including PF and corresponding VFs' vlan, mac, 4615 * flow table configurations, etc. 4616 */ 4617 ret = hns3_clear_hw(hw); 4618 if (ret) { 4619 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); 4620 goto err_cmd_init; 4621 } 4622 4623 hns3_config_all_msix_error(hw, true); 4624 4625 ret = rte_intr_callback_register(pci_dev->intr_handle, 4626 hns3_interrupt_handler, 4627 eth_dev); 4628 if (ret) { 4629 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 4630 goto err_intr_callback_register; 4631 } 4632 4633 ret = hns3_ptp_init(hw); 4634 if (ret) 4635 goto err_get_config; 4636 4637 /* Enable interrupt */ 4638 rte_intr_enable(pci_dev->intr_handle); 4639 hns3_pf_enable_irq0(hw); 4640 4641 /* Get configuration */ 4642 ret = hns3_get_configuration(hw); 4643 if (ret) { 4644 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 4645 goto err_get_config; 4646 } 4647 4648 ret = hns3_stats_init(hw); 4649 if (ret) 4650 goto err_get_config; 4651 4652 ret = hns3_init_hardware(hns); 4653 if (ret) { 4654 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 4655 goto err_init_hw; 4656 } 4657 4658 /* Initialize flow director filter list & hash */ 4659 ret = hns3_fdir_filter_init(hns); 4660 if (ret) { 4661 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 4662 goto err_fdir; 4663 } 4664 4665 hns3_rss_set_default_args(hw); 4666 4667 ret = hns3_enable_hw_error_intr(hns, true); 4668 if (ret) { 4669 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 4670 ret); 4671 goto err_enable_intr; 4672 } 4673 4674 ret = hns3_get_port_supported_speed(eth_dev); 4675 if (ret) { 4676 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported " 4677 "by device, ret = %d.", ret); 4678 goto err_supported_speed; 4679 } 4680 4681 hns3_get_fc_autoneg_capability(hns); 4682 4683 hns3_tm_conf_init(eth_dev); 4684 4685 return 0; 4686 4687 err_supported_speed: 4688 (void)hns3_enable_hw_error_intr(hns, false); 4689 err_enable_intr: 4690 hns3_fdir_filter_uninit(hns); 4691 err_fdir: 4692 hns3_uninit_umv_space(hw); 4693 err_init_hw: 4694 hns3_stats_uninit(hw); 4695 err_get_config: 4696 hns3_pf_disable_irq0(hw); 4697 rte_intr_disable(pci_dev->intr_handle); 4698 hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler, 4699 eth_dev); 4700 err_intr_callback_register: 4701 err_cmd_init: 4702 hns3_cmd_uninit(hw); 4703 hns3_cmd_destroy_queue(hw); 4704 err_cmd_init_queue: 4705 hw->io_base = NULL; 4706 4707 return ret; 4708 } 4709 4710 static void 4711 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 4712 { 4713 struct hns3_adapter *hns = eth_dev->data->dev_private; 4714 struct rte_device *dev = eth_dev->device; 4715 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4716 struct hns3_hw *hw = &hns->hw; 4717 4718 PMD_INIT_FUNC_TRACE(); 4719 4720 hns3_tm_conf_uninit(eth_dev); 4721 hns3_enable_hw_error_intr(hns, false); 4722 hns3_rss_uninit(hns); 4723 (void)hns3_config_gro(hw, false); 4724 hns3_promisc_uninit(hw); 4725 hns3_flow_uninit(eth_dev); 4726 hns3_fdir_filter_uninit(hns); 4727 hns3_uninit_umv_space(hw); 4728 hns3_stats_uninit(hw); 4729 hns3_config_mac_tnl_int(hw, false); 4730 hns3_pf_disable_irq0(hw); 4731 rte_intr_disable(pci_dev->intr_handle); 4732 hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler, 4733 eth_dev); 4734 hns3_config_all_msix_error(hw, false); 4735 hns3_cmd_uninit(hw); 4736 hns3_cmd_destroy_queue(hw); 4737 hw->io_base = NULL; 4738 } 4739 4740 static uint32_t 4741 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds) 4742 { 4743 uint32_t speed_bit; 4744 4745 switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) { 4746 case RTE_ETH_LINK_SPEED_10M: 4747 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT; 4748 break; 4749 case RTE_ETH_LINK_SPEED_10M_HD: 4750 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT; 4751 break; 4752 case RTE_ETH_LINK_SPEED_100M: 4753 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT; 4754 break; 4755 case RTE_ETH_LINK_SPEED_100M_HD: 4756 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT; 4757 break; 4758 case RTE_ETH_LINK_SPEED_1G: 4759 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT; 4760 break; 4761 default: 4762 speed_bit = 0; 4763 break; 4764 } 4765 4766 return speed_bit; 4767 } 4768 4769 static uint32_t 4770 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds) 4771 { 4772 uint32_t speed_bit; 4773 4774 switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) { 4775 case RTE_ETH_LINK_SPEED_1G: 4776 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT; 4777 break; 4778 case RTE_ETH_LINK_SPEED_10G: 4779 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT; 4780 break; 4781 case RTE_ETH_LINK_SPEED_25G: 4782 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT; 4783 break; 4784 case RTE_ETH_LINK_SPEED_40G: 4785 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT; 4786 break; 4787 case RTE_ETH_LINK_SPEED_50G: 4788 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT; 4789 break; 4790 case RTE_ETH_LINK_SPEED_100G: 4791 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT; 4792 break; 4793 case RTE_ETH_LINK_SPEED_200G: 4794 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT; 4795 break; 4796 default: 4797 speed_bit = 0; 4798 break; 4799 } 4800 4801 return speed_bit; 4802 } 4803 4804 static int 4805 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds) 4806 { 4807 struct hns3_mac *mac = &hw->mac; 4808 uint32_t supported_speed = mac->supported_speed; 4809 uint32_t speed_bit = 0; 4810 4811 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 4812 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds); 4813 else 4814 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds); 4815 4816 if (!(speed_bit & supported_speed)) { 4817 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.", 4818 link_speeds); 4819 return -EINVAL; 4820 } 4821 4822 return 0; 4823 } 4824 4825 static uint32_t 4826 hns3_get_link_speed(uint32_t link_speeds) 4827 { 4828 uint32_t speed = RTE_ETH_SPEED_NUM_NONE; 4829 4830 if (link_speeds & RTE_ETH_LINK_SPEED_10M || 4831 link_speeds & RTE_ETH_LINK_SPEED_10M_HD) 4832 speed = RTE_ETH_SPEED_NUM_10M; 4833 if (link_speeds & RTE_ETH_LINK_SPEED_100M || 4834 link_speeds & RTE_ETH_LINK_SPEED_100M_HD) 4835 speed = RTE_ETH_SPEED_NUM_100M; 4836 if (link_speeds & RTE_ETH_LINK_SPEED_1G) 4837 speed = RTE_ETH_SPEED_NUM_1G; 4838 if (link_speeds & RTE_ETH_LINK_SPEED_10G) 4839 speed = RTE_ETH_SPEED_NUM_10G; 4840 if (link_speeds & RTE_ETH_LINK_SPEED_25G) 4841 speed = RTE_ETH_SPEED_NUM_25G; 4842 if (link_speeds & RTE_ETH_LINK_SPEED_40G) 4843 speed = RTE_ETH_SPEED_NUM_40G; 4844 if (link_speeds & RTE_ETH_LINK_SPEED_50G) 4845 speed = RTE_ETH_SPEED_NUM_50G; 4846 if (link_speeds & RTE_ETH_LINK_SPEED_100G) 4847 speed = RTE_ETH_SPEED_NUM_100G; 4848 if (link_speeds & RTE_ETH_LINK_SPEED_200G) 4849 speed = RTE_ETH_SPEED_NUM_200G; 4850 4851 return speed; 4852 } 4853 4854 static uint8_t 4855 hns3_get_link_duplex(uint32_t link_speeds) 4856 { 4857 if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || 4858 (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) 4859 return RTE_ETH_LINK_HALF_DUPLEX; 4860 else 4861 return RTE_ETH_LINK_FULL_DUPLEX; 4862 } 4863 4864 static int 4865 hns3_set_copper_port_link_speed(struct hns3_hw *hw, 4866 struct hns3_set_link_speed_cfg *cfg) 4867 { 4868 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 4869 struct hns3_phy_params_bd0_cmd *req; 4870 uint16_t i; 4871 4872 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 4873 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 4874 false); 4875 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4876 } 4877 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false); 4878 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 4879 req->autoneg = cfg->autoneg; 4880 4881 /* 4882 * The full speed capability is used to negotiate when 4883 * auto-negotiation is enabled. 4884 */ 4885 if (cfg->autoneg) { 4886 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT | 4887 HNS3_PHY_LINK_SPEED_10M_HD_BIT | 4888 HNS3_PHY_LINK_SPEED_100M_BIT | 4889 HNS3_PHY_LINK_SPEED_100M_HD_BIT | 4890 HNS3_PHY_LINK_SPEED_1000M_BIT; 4891 } else { 4892 req->speed = cfg->speed; 4893 req->duplex = cfg->duplex; 4894 } 4895 4896 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 4897 } 4898 4899 static int 4900 hns3_set_autoneg(struct hns3_hw *hw, bool enable) 4901 { 4902 struct hns3_config_auto_neg_cmd *req; 4903 struct hns3_cmd_desc desc; 4904 uint32_t flag = 0; 4905 int ret; 4906 4907 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false); 4908 4909 req = (struct hns3_config_auto_neg_cmd *)desc.data; 4910 if (enable) 4911 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1); 4912 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag); 4913 4914 ret = hns3_cmd_send(hw, &desc, 1); 4915 if (ret) 4916 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret); 4917 4918 return ret; 4919 } 4920 4921 static int 4922 hns3_set_fiber_port_link_speed(struct hns3_hw *hw, 4923 struct hns3_set_link_speed_cfg *cfg) 4924 { 4925 int ret; 4926 4927 if (hw->mac.support_autoneg) { 4928 ret = hns3_set_autoneg(hw, cfg->autoneg); 4929 if (ret) { 4930 hns3_err(hw, "failed to configure auto-negotiation."); 4931 return ret; 4932 } 4933 4934 /* 4935 * To enable auto-negotiation, we only need to open the switch 4936 * of auto-negotiation, then firmware sets all speed 4937 * capabilities. 4938 */ 4939 if (cfg->autoneg) 4940 return 0; 4941 } 4942 4943 /* 4944 * Some hardware doesn't support auto-negotiation, but users may not 4945 * configure link_speeds (default 0), which means auto-negotiation. 4946 * In this case, a warning message need to be printed, instead of 4947 * an error. 4948 */ 4949 if (cfg->autoneg) { 4950 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!"); 4951 return 0; 4952 } 4953 4954 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex); 4955 } 4956 4957 static const char * 4958 hns3_get_media_type_name(uint8_t media_type) 4959 { 4960 if (media_type == HNS3_MEDIA_TYPE_FIBER) 4961 return "fiber"; 4962 else if (media_type == HNS3_MEDIA_TYPE_COPPER) 4963 return "copper"; 4964 else if (media_type == HNS3_MEDIA_TYPE_BACKPLANE) 4965 return "backplane"; 4966 else 4967 return "unknown"; 4968 } 4969 4970 static int 4971 hns3_set_port_link_speed(struct hns3_hw *hw, 4972 struct hns3_set_link_speed_cfg *cfg) 4973 { 4974 int ret; 4975 4976 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) 4977 ret = hns3_set_copper_port_link_speed(hw, cfg); 4978 else 4979 ret = hns3_set_fiber_port_link_speed(hw, cfg); 4980 4981 if (ret) { 4982 hns3_err(hw, "failed to set %s port link speed, ret = %d.", 4983 hns3_get_media_type_name(hw->mac.media_type), 4984 ret); 4985 return ret; 4986 } 4987 4988 return 0; 4989 } 4990 4991 static int 4992 hns3_apply_link_speed(struct hns3_hw *hw) 4993 { 4994 struct rte_eth_conf *conf = &hw->data->dev_conf; 4995 struct hns3_set_link_speed_cfg cfg; 4996 4997 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg)); 4998 cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ? 4999 RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED; 5000 if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) { 5001 cfg.speed = hns3_get_link_speed(conf->link_speeds); 5002 cfg.duplex = hns3_get_link_duplex(conf->link_speeds); 5003 } 5004 5005 return hns3_set_port_link_speed(hw, &cfg); 5006 } 5007 5008 static int 5009 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 5010 { 5011 struct hns3_hw *hw = &hns->hw; 5012 bool link_en; 5013 int ret; 5014 5015 ret = hns3_update_queue_map_configure(hns); 5016 if (ret) { 5017 hns3_err(hw, "failed to update queue mapping configuration, ret = %d", 5018 ret); 5019 return ret; 5020 } 5021 5022 /* Note: hns3_tm_conf_update must be called after configuring DCB. */ 5023 ret = hns3_tm_conf_update(hw); 5024 if (ret) { 5025 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret); 5026 return ret; 5027 } 5028 5029 hns3_enable_rxd_adv_layout(hw); 5030 5031 ret = hns3_init_queues(hns, reset_queue); 5032 if (ret) { 5033 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret); 5034 return ret; 5035 } 5036 5037 link_en = hw->set_link_down ? false : true; 5038 ret = hns3_cfg_mac_mode(hw, link_en); 5039 if (ret) { 5040 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret); 5041 goto err_config_mac_mode; 5042 } 5043 5044 ret = hns3_apply_link_speed(hw); 5045 if (ret) 5046 goto err_set_link_speed; 5047 5048 return hns3_restore_filter(hns); 5049 5050 err_set_link_speed: 5051 (void)hns3_cfg_mac_mode(hw, false); 5052 5053 err_config_mac_mode: 5054 hns3_dev_release_mbufs(hns); 5055 /* 5056 * Here is exception handling, hns3_reset_all_tqps will have the 5057 * corresponding error message if it is handled incorrectly, so it is 5058 * not necessary to check hns3_reset_all_tqps return value, here keep 5059 * ret as the error code causing the exception. 5060 */ 5061 (void)hns3_reset_all_tqps(hns); 5062 return ret; 5063 } 5064 5065 static int 5066 hns3_dev_start(struct rte_eth_dev *dev) 5067 { 5068 struct hns3_adapter *hns = dev->data->dev_private; 5069 struct hns3_hw *hw = &hns->hw; 5070 bool old_state = hw->set_link_down; 5071 int ret; 5072 5073 PMD_INIT_FUNC_TRACE(); 5074 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 5075 return -EBUSY; 5076 5077 rte_spinlock_lock(&hw->lock); 5078 hw->adapter_state = HNS3_NIC_STARTING; 5079 5080 /* 5081 * If the dev_set_link_down() API has been called, the "set_link_down" 5082 * flag can be cleared by dev_start() API. In addition, the flag should 5083 * also be cleared before calling hns3_do_start() so that MAC can be 5084 * enabled in dev_start stage. 5085 */ 5086 hw->set_link_down = false; 5087 ret = hns3_do_start(hns, true); 5088 if (ret) 5089 goto do_start_fail; 5090 5091 ret = hns3_map_rx_interrupt(dev); 5092 if (ret) 5093 goto map_rx_inter_err; 5094 5095 /* 5096 * There are three register used to control the status of a TQP 5097 * (contains a pair of Tx queue and Rx queue) in the new version network 5098 * engine. One is used to control the enabling of Tx queue, the other is 5099 * used to control the enabling of Rx queue, and the last is the master 5100 * switch used to control the enabling of the tqp. The Tx register and 5101 * TQP register must be enabled at the same time to enable a Tx queue. 5102 * The same applies to the Rx queue. For the older network engine, this 5103 * function only refresh the enabled flag, and it is used to update the 5104 * status of queue in the dpdk framework. 5105 */ 5106 ret = hns3_start_all_txqs(dev); 5107 if (ret) 5108 goto map_rx_inter_err; 5109 5110 ret = hns3_start_all_rxqs(dev); 5111 if (ret) 5112 goto start_all_rxqs_fail; 5113 5114 hw->adapter_state = HNS3_NIC_STARTED; 5115 rte_spinlock_unlock(&hw->lock); 5116 5117 hns3_rx_scattered_calc(dev); 5118 hns3_set_rxtx_function(dev); 5119 hns3_mp_req_start_rxtx(dev); 5120 5121 /* Enable interrupt of all rx queues before enabling queues */ 5122 hns3_dev_all_rx_queue_intr_enable(hw, true); 5123 5124 /* 5125 * After finished the initialization, enable tqps to receive/transmit 5126 * packets and refresh all queue status. 5127 */ 5128 hns3_start_tqps(hw); 5129 5130 hns3_tm_dev_start_proc(hw); 5131 5132 if (dev->data->dev_conf.intr_conf.lsc != 0) 5133 hns3_dev_link_update(dev, 0); 5134 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 5135 5136 hns3_info(hw, "hns3 dev start successful!"); 5137 5138 return 0; 5139 5140 start_all_rxqs_fail: 5141 hns3_stop_all_txqs(dev); 5142 map_rx_inter_err: 5143 (void)hns3_do_stop(hns); 5144 do_start_fail: 5145 hw->set_link_down = old_state; 5146 hw->adapter_state = HNS3_NIC_CONFIGURED; 5147 rte_spinlock_unlock(&hw->lock); 5148 5149 return ret; 5150 } 5151 5152 static int 5153 hns3_do_stop(struct hns3_adapter *hns) 5154 { 5155 struct hns3_hw *hw = &hns->hw; 5156 int ret; 5157 5158 /* 5159 * The "hns3_do_stop" function will also be called by .stop_service to 5160 * prepare reset. At the time of global or IMP reset, the command cannot 5161 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 5162 * accessed during the reset process. So the mbuf can not be released 5163 * during reset and is required to be released after the reset is 5164 * completed. 5165 */ 5166 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 5167 hns3_dev_release_mbufs(hns); 5168 5169 ret = hns3_cfg_mac_mode(hw, false); 5170 if (ret) 5171 return ret; 5172 hw->mac.link_status = RTE_ETH_LINK_DOWN; 5173 5174 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 5175 hns3_configure_all_mac_addr(hns, true); 5176 ret = hns3_reset_all_tqps(hns); 5177 if (ret) { 5178 hns3_err(hw, "failed to reset all queues ret = %d.", 5179 ret); 5180 return ret; 5181 } 5182 } 5183 5184 return 0; 5185 } 5186 5187 static int 5188 hns3_dev_stop(struct rte_eth_dev *dev) 5189 { 5190 struct hns3_adapter *hns = dev->data->dev_private; 5191 struct hns3_hw *hw = &hns->hw; 5192 5193 PMD_INIT_FUNC_TRACE(); 5194 dev->data->dev_started = 0; 5195 5196 hw->adapter_state = HNS3_NIC_STOPPING; 5197 hns3_set_rxtx_function(dev); 5198 rte_wmb(); 5199 /* Disable datapath on secondary process. */ 5200 hns3_mp_req_stop_rxtx(dev); 5201 /* Prevent crashes when queues are still in use. */ 5202 rte_delay_ms(hw->cfg_max_queues); 5203 5204 rte_spinlock_lock(&hw->lock); 5205 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 5206 hns3_tm_dev_stop_proc(hw); 5207 hns3_config_mac_tnl_int(hw, false); 5208 hns3_stop_tqps(hw); 5209 hns3_do_stop(hns); 5210 hns3_unmap_rx_interrupt(dev); 5211 hw->adapter_state = HNS3_NIC_CONFIGURED; 5212 } 5213 hns3_rx_scattered_reset(dev); 5214 rte_eal_alarm_cancel(hns3_service_handler, dev); 5215 hns3_stop_report_lse(dev); 5216 rte_spinlock_unlock(&hw->lock); 5217 5218 return 0; 5219 } 5220 5221 static int 5222 hns3_dev_close(struct rte_eth_dev *eth_dev) 5223 { 5224 struct hns3_adapter *hns = eth_dev->data->dev_private; 5225 struct hns3_hw *hw = &hns->hw; 5226 int ret = 0; 5227 5228 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 5229 hns3_mp_uninit(eth_dev); 5230 return 0; 5231 } 5232 5233 if (hw->adapter_state == HNS3_NIC_STARTED) 5234 ret = hns3_dev_stop(eth_dev); 5235 5236 hw->adapter_state = HNS3_NIC_CLOSING; 5237 hns3_reset_abort(hns); 5238 hw->adapter_state = HNS3_NIC_CLOSED; 5239 5240 hns3_configure_all_mc_mac_addr(hns, true); 5241 hns3_remove_all_vlan_table(hns); 5242 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 5243 hns3_uninit_pf(eth_dev); 5244 hns3_free_all_queues(eth_dev); 5245 rte_free(hw->reset.wait_data); 5246 hns3_mp_uninit(eth_dev); 5247 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 5248 5249 return ret; 5250 } 5251 5252 static void 5253 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause, 5254 bool *tx_pause) 5255 { 5256 struct hns3_mac *mac = &hw->mac; 5257 uint32_t advertising = mac->advertising; 5258 uint32_t lp_advertising = mac->lp_advertising; 5259 *rx_pause = false; 5260 *tx_pause = false; 5261 5262 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) { 5263 *rx_pause = true; 5264 *tx_pause = true; 5265 } else if (advertising & lp_advertising & 5266 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) { 5267 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5268 *rx_pause = true; 5269 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5270 *tx_pause = true; 5271 } 5272 } 5273 5274 static enum hns3_fc_mode 5275 hns3_get_autoneg_fc_mode(struct hns3_hw *hw) 5276 { 5277 enum hns3_fc_mode current_mode; 5278 bool rx_pause = false; 5279 bool tx_pause = false; 5280 5281 switch (hw->mac.media_type) { 5282 case HNS3_MEDIA_TYPE_COPPER: 5283 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause); 5284 break; 5285 5286 /* 5287 * Flow control auto-negotiation is not supported for fiber and 5288 * backplane media type. 5289 */ 5290 case HNS3_MEDIA_TYPE_FIBER: 5291 case HNS3_MEDIA_TYPE_BACKPLANE: 5292 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled."); 5293 current_mode = hw->requested_fc_mode; 5294 goto out; 5295 default: 5296 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).", 5297 hw->mac.media_type); 5298 current_mode = HNS3_FC_NONE; 5299 goto out; 5300 } 5301 5302 if (rx_pause && tx_pause) 5303 current_mode = HNS3_FC_FULL; 5304 else if (rx_pause) 5305 current_mode = HNS3_FC_RX_PAUSE; 5306 else if (tx_pause) 5307 current_mode = HNS3_FC_TX_PAUSE; 5308 else 5309 current_mode = HNS3_FC_NONE; 5310 5311 out: 5312 return current_mode; 5313 } 5314 5315 static enum hns3_fc_mode 5316 hns3_get_current_fc_mode(struct rte_eth_dev *dev) 5317 { 5318 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5319 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5320 struct hns3_mac *mac = &hw->mac; 5321 5322 /* 5323 * When the flow control mode is obtained, the device may not complete 5324 * auto-negotiation. It is necessary to wait for link establishment. 5325 */ 5326 (void)hns3_dev_link_update(dev, 1); 5327 5328 /* 5329 * If the link auto-negotiation of the nic is disabled, or the flow 5330 * control auto-negotiation is not supported, the forced flow control 5331 * mode is used. 5332 */ 5333 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg) 5334 return hw->requested_fc_mode; 5335 5336 return hns3_get_autoneg_fc_mode(hw); 5337 } 5338 5339 int 5340 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 5341 { 5342 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5343 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5344 enum hns3_fc_mode current_mode; 5345 5346 current_mode = hns3_get_current_fc_mode(dev); 5347 switch (current_mode) { 5348 case HNS3_FC_FULL: 5349 fc_conf->mode = RTE_ETH_FC_FULL; 5350 break; 5351 case HNS3_FC_TX_PAUSE: 5352 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 5353 break; 5354 case HNS3_FC_RX_PAUSE: 5355 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 5356 break; 5357 case HNS3_FC_NONE: 5358 default: 5359 fc_conf->mode = RTE_ETH_FC_NONE; 5360 break; 5361 } 5362 5363 fc_conf->pause_time = pf->pause_time; 5364 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0; 5365 5366 return 0; 5367 } 5368 5369 static int 5370 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg) 5371 { 5372 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 5373 5374 if (!pf->support_fc_autoneg) { 5375 if (autoneg != 0) { 5376 hns3_err(hw, "unsupported fc auto-negotiation setting."); 5377 return -EOPNOTSUPP; 5378 } 5379 5380 /* 5381 * Flow control auto-negotiation of the NIC is not supported, 5382 * but other auto-negotiation features may be supported. 5383 */ 5384 if (autoneg != hw->mac.link_autoneg) { 5385 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!"); 5386 return -EOPNOTSUPP; 5387 } 5388 5389 return 0; 5390 } 5391 5392 /* 5393 * If flow control auto-negotiation of the NIC is supported, all 5394 * auto-negotiation features are supported. 5395 */ 5396 if (autoneg != hw->mac.link_autoneg) { 5397 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!"); 5398 return -EOPNOTSUPP; 5399 } 5400 5401 return 0; 5402 } 5403 5404 static int 5405 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 5406 { 5407 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5408 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5409 int ret; 5410 5411 if (fc_conf->high_water || fc_conf->low_water || 5412 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 5413 hns3_err(hw, "Unsupported flow control settings specified, " 5414 "high_water(%u), low_water(%u), send_xon(%u) and " 5415 "mac_ctrl_frame_fwd(%u) must be set to '0'", 5416 fc_conf->high_water, fc_conf->low_water, 5417 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 5418 return -EINVAL; 5419 } 5420 5421 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg); 5422 if (ret) 5423 return ret; 5424 5425 if (!fc_conf->pause_time) { 5426 hns3_err(hw, "Invalid pause time %u setting.", 5427 fc_conf->pause_time); 5428 return -EINVAL; 5429 } 5430 5431 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 5432 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 5433 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 5434 "current_fc_status = %d", hw->current_fc_status); 5435 return -EOPNOTSUPP; 5436 } 5437 5438 if (hw->num_tc > 1 && !pf->support_multi_tc_pause) { 5439 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported."); 5440 return -EOPNOTSUPP; 5441 } 5442 5443 rte_spinlock_lock(&hw->lock); 5444 ret = hns3_fc_enable(dev, fc_conf); 5445 rte_spinlock_unlock(&hw->lock); 5446 5447 return ret; 5448 } 5449 5450 static int 5451 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 5452 struct rte_eth_pfc_conf *pfc_conf) 5453 { 5454 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5455 int ret; 5456 5457 if (!hns3_dev_get_support(hw, DCB)) { 5458 hns3_err(hw, "This port does not support dcb configurations."); 5459 return -EOPNOTSUPP; 5460 } 5461 5462 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 5463 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 5464 hns3_err(hw, "Unsupported flow control settings specified, " 5465 "high_water(%u), low_water(%u), send_xon(%u) and " 5466 "mac_ctrl_frame_fwd(%u) must be set to '0'", 5467 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 5468 pfc_conf->fc.send_xon, 5469 pfc_conf->fc.mac_ctrl_frame_fwd); 5470 return -EINVAL; 5471 } 5472 if (pfc_conf->fc.autoneg) { 5473 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 5474 return -EINVAL; 5475 } 5476 if (pfc_conf->fc.pause_time == 0) { 5477 hns3_err(hw, "Invalid pause time %u setting.", 5478 pfc_conf->fc.pause_time); 5479 return -EINVAL; 5480 } 5481 5482 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 5483 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 5484 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 5485 "current_fc_status = %d", hw->current_fc_status); 5486 return -EOPNOTSUPP; 5487 } 5488 5489 rte_spinlock_lock(&hw->lock); 5490 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 5491 rte_spinlock_unlock(&hw->lock); 5492 5493 return ret; 5494 } 5495 5496 static int 5497 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 5498 { 5499 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5500 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5501 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 5502 int i; 5503 5504 rte_spinlock_lock(&hw->lock); 5505 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) 5506 dcb_info->nb_tcs = pf->local_max_tc; 5507 else 5508 dcb_info->nb_tcs = 1; 5509 5510 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 5511 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 5512 for (i = 0; i < dcb_info->nb_tcs; i++) 5513 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 5514 5515 for (i = 0; i < hw->num_tc; i++) { 5516 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 5517 dcb_info->tc_queue.tc_txq[0][i].base = 5518 hw->tc_queue[i].tqp_offset; 5519 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 5520 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 5521 hw->tc_queue[i].tqp_count; 5522 } 5523 rte_spinlock_unlock(&hw->lock); 5524 5525 return 0; 5526 } 5527 5528 static int 5529 hns3_reinit_dev(struct hns3_adapter *hns) 5530 { 5531 struct hns3_hw *hw = &hns->hw; 5532 int ret; 5533 5534 ret = hns3_cmd_init(hw); 5535 if (ret) { 5536 hns3_err(hw, "Failed to init cmd: %d", ret); 5537 return ret; 5538 } 5539 5540 ret = hns3_init_hardware(hns); 5541 if (ret) { 5542 hns3_err(hw, "Failed to init hardware: %d", ret); 5543 return ret; 5544 } 5545 5546 ret = hns3_reset_all_tqps(hns); 5547 if (ret) { 5548 hns3_err(hw, "Failed to reset all queues: %d", ret); 5549 return ret; 5550 } 5551 5552 ret = hns3_enable_hw_error_intr(hns, true); 5553 if (ret) { 5554 hns3_err(hw, "fail to enable hw error interrupts: %d", 5555 ret); 5556 return ret; 5557 } 5558 hns3_info(hw, "Reset done, driver initialization finished."); 5559 5560 return 0; 5561 } 5562 5563 static bool 5564 is_pf_reset_done(struct hns3_hw *hw) 5565 { 5566 uint32_t val, reg, reg_bit; 5567 5568 switch (hw->reset.level) { 5569 case HNS3_IMP_RESET: 5570 reg = HNS3_GLOBAL_RESET_REG; 5571 reg_bit = HNS3_IMP_RESET_BIT; 5572 break; 5573 case HNS3_GLOBAL_RESET: 5574 reg = HNS3_GLOBAL_RESET_REG; 5575 reg_bit = HNS3_GLOBAL_RESET_BIT; 5576 break; 5577 case HNS3_FUNC_RESET: 5578 reg = HNS3_FUN_RST_ING; 5579 reg_bit = HNS3_FUN_RST_ING_B; 5580 break; 5581 case HNS3_FLR_RESET: 5582 default: 5583 hns3_err(hw, "Wait for unsupported reset level: %d", 5584 hw->reset.level); 5585 return true; 5586 } 5587 val = hns3_read_dev(hw, reg); 5588 if (hns3_get_bit(val, reg_bit)) 5589 return false; 5590 else 5591 return true; 5592 } 5593 5594 bool 5595 hns3_is_reset_pending(struct hns3_adapter *hns) 5596 { 5597 struct hns3_hw *hw = &hns->hw; 5598 enum hns3_reset_level reset; 5599 5600 /* 5601 * Check the registers to confirm whether there is reset pending. 5602 * Note: This check may lead to schedule reset task, but only primary 5603 * process can process the reset event. Therefore, limit the 5604 * checking under only primary process. 5605 */ 5606 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 5607 hns3_check_event_cause(hns, NULL); 5608 5609 reset = hns3_get_reset_level(hns, &hw->reset.pending); 5610 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 5611 hw->reset.level < reset) { 5612 hns3_warn(hw, "High level reset %d is pending", reset); 5613 return true; 5614 } 5615 reset = hns3_get_reset_level(hns, &hw->reset.request); 5616 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 5617 hw->reset.level < reset) { 5618 hns3_warn(hw, "High level reset %d is request", reset); 5619 return true; 5620 } 5621 return false; 5622 } 5623 5624 static int 5625 hns3_wait_hardware_ready(struct hns3_adapter *hns) 5626 { 5627 struct hns3_hw *hw = &hns->hw; 5628 struct hns3_wait_data *wait_data = hw->reset.wait_data; 5629 struct timeval tv; 5630 5631 if (wait_data->result == HNS3_WAIT_SUCCESS) 5632 return 0; 5633 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 5634 hns3_clock_gettime(&tv); 5635 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 5636 tv.tv_sec, tv.tv_usec); 5637 return -ETIME; 5638 } else if (wait_data->result == HNS3_WAIT_REQUEST) 5639 return -EAGAIN; 5640 5641 wait_data->hns = hns; 5642 wait_data->check_completion = is_pf_reset_done; 5643 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 5644 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms(); 5645 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 5646 wait_data->count = HNS3_RESET_WAIT_CNT; 5647 wait_data->result = HNS3_WAIT_REQUEST; 5648 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 5649 return -EAGAIN; 5650 } 5651 5652 static int 5653 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 5654 { 5655 struct hns3_cmd_desc desc; 5656 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 5657 5658 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 5659 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 5660 req->fun_reset_vfid = func_id; 5661 5662 return hns3_cmd_send(hw, &desc, 1); 5663 } 5664 5665 static int 5666 hns3_imp_reset_cmd(struct hns3_hw *hw) 5667 { 5668 struct hns3_cmd_desc desc; 5669 5670 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 5671 desc.data[0] = 0xeedd; 5672 5673 return hns3_cmd_send(hw, &desc, 1); 5674 } 5675 5676 static void 5677 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 5678 { 5679 struct hns3_hw *hw = &hns->hw; 5680 struct timeval tv; 5681 uint32_t val; 5682 5683 hns3_clock_gettime(&tv); 5684 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 5685 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 5686 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 5687 tv.tv_sec, tv.tv_usec); 5688 return; 5689 } 5690 5691 switch (reset_level) { 5692 case HNS3_IMP_RESET: 5693 hns3_imp_reset_cmd(hw); 5694 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 5695 tv.tv_sec, tv.tv_usec); 5696 break; 5697 case HNS3_GLOBAL_RESET: 5698 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 5699 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 5700 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 5701 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 5702 tv.tv_sec, tv.tv_usec); 5703 break; 5704 case HNS3_FUNC_RESET: 5705 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 5706 tv.tv_sec, tv.tv_usec); 5707 /* schedule again to check later */ 5708 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 5709 hns3_schedule_reset(hns); 5710 break; 5711 default: 5712 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 5713 return; 5714 } 5715 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 5716 } 5717 5718 static enum hns3_reset_level 5719 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 5720 { 5721 struct hns3_hw *hw = &hns->hw; 5722 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 5723 5724 /* Return the highest priority reset level amongst all */ 5725 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 5726 reset_level = HNS3_IMP_RESET; 5727 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 5728 reset_level = HNS3_GLOBAL_RESET; 5729 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 5730 reset_level = HNS3_FUNC_RESET; 5731 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 5732 reset_level = HNS3_FLR_RESET; 5733 5734 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 5735 return HNS3_NONE_RESET; 5736 5737 return reset_level; 5738 } 5739 5740 static void 5741 hns3_record_imp_error(struct hns3_adapter *hns) 5742 { 5743 struct hns3_hw *hw = &hns->hw; 5744 uint32_t reg_val; 5745 5746 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5747 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { 5748 hns3_warn(hw, "Detected IMP RD poison!"); 5749 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); 5750 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5751 } 5752 5753 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { 5754 hns3_warn(hw, "Detected IMP CMDQ error!"); 5755 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); 5756 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5757 } 5758 } 5759 5760 static int 5761 hns3_prepare_reset(struct hns3_adapter *hns) 5762 { 5763 struct hns3_hw *hw = &hns->hw; 5764 uint32_t reg_val; 5765 int ret; 5766 5767 switch (hw->reset.level) { 5768 case HNS3_FUNC_RESET: 5769 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 5770 if (ret) 5771 return ret; 5772 5773 /* 5774 * After performaning pf reset, it is not necessary to do the 5775 * mailbox handling or send any command to firmware, because 5776 * any mailbox handling or command to firmware is only valid 5777 * after hns3_cmd_init is called. 5778 */ 5779 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 5780 hw->reset.stats.request_cnt++; 5781 break; 5782 case HNS3_IMP_RESET: 5783 hns3_record_imp_error(hns); 5784 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5785 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 5786 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 5787 break; 5788 default: 5789 break; 5790 } 5791 return 0; 5792 } 5793 5794 static int 5795 hns3_set_rst_done(struct hns3_hw *hw) 5796 { 5797 struct hns3_pf_rst_done_cmd *req; 5798 struct hns3_cmd_desc desc; 5799 5800 req = (struct hns3_pf_rst_done_cmd *)desc.data; 5801 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 5802 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 5803 return hns3_cmd_send(hw, &desc, 1); 5804 } 5805 5806 static int 5807 hns3_stop_service(struct hns3_adapter *hns) 5808 { 5809 struct hns3_hw *hw = &hns->hw; 5810 struct rte_eth_dev *eth_dev; 5811 5812 eth_dev = &rte_eth_devices[hw->data->port_id]; 5813 hw->mac.link_status = RTE_ETH_LINK_DOWN; 5814 if (hw->adapter_state == HNS3_NIC_STARTED) { 5815 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 5816 hns3_update_linkstatus_and_event(hw, false); 5817 } 5818 5819 hns3_set_rxtx_function(eth_dev); 5820 rte_wmb(); 5821 /* Disable datapath on secondary process. */ 5822 hns3_mp_req_stop_rxtx(eth_dev); 5823 rte_delay_ms(hw->cfg_max_queues); 5824 5825 rte_spinlock_lock(&hw->lock); 5826 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 5827 hw->adapter_state == HNS3_NIC_STOPPING) { 5828 hns3_enable_all_queues(hw, false); 5829 hns3_do_stop(hns); 5830 hw->reset.mbuf_deferred_free = true; 5831 } else 5832 hw->reset.mbuf_deferred_free = false; 5833 5834 /* 5835 * It is cumbersome for hardware to pick-and-choose entries for deletion 5836 * from table space. Hence, for function reset software intervention is 5837 * required to delete the entries 5838 */ 5839 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 5840 hns3_configure_all_mc_mac_addr(hns, true); 5841 rte_spinlock_unlock(&hw->lock); 5842 5843 return 0; 5844 } 5845 5846 static int 5847 hns3_start_service(struct hns3_adapter *hns) 5848 { 5849 struct hns3_hw *hw = &hns->hw; 5850 struct rte_eth_dev *eth_dev; 5851 5852 if (hw->reset.level == HNS3_IMP_RESET || 5853 hw->reset.level == HNS3_GLOBAL_RESET) 5854 hns3_set_rst_done(hw); 5855 eth_dev = &rte_eth_devices[hw->data->port_id]; 5856 hns3_set_rxtx_function(eth_dev); 5857 hns3_mp_req_start_rxtx(eth_dev); 5858 if (hw->adapter_state == HNS3_NIC_STARTED) { 5859 /* 5860 * This API parent function already hold the hns3_hw.lock, the 5861 * hns3_service_handler may report lse, in bonding application 5862 * it will call driver's ops which may acquire the hns3_hw.lock 5863 * again, thus lead to deadlock. 5864 * We defer calls hns3_service_handler to avoid the deadlock. 5865 */ 5866 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL, 5867 hns3_service_handler, eth_dev); 5868 5869 /* Enable interrupt of all rx queues before enabling queues */ 5870 hns3_dev_all_rx_queue_intr_enable(hw, true); 5871 /* 5872 * Enable state of each rxq and txq will be recovered after 5873 * reset, so we need to restore them before enable all tqps; 5874 */ 5875 hns3_restore_tqp_enable_state(hw); 5876 /* 5877 * When finished the initialization, enable queues to receive 5878 * and transmit packets. 5879 */ 5880 hns3_enable_all_queues(hw, true); 5881 } 5882 5883 return 0; 5884 } 5885 5886 static int 5887 hns3_restore_conf(struct hns3_adapter *hns) 5888 { 5889 struct hns3_hw *hw = &hns->hw; 5890 int ret; 5891 5892 ret = hns3_configure_all_mac_addr(hns, false); 5893 if (ret) 5894 return ret; 5895 5896 ret = hns3_configure_all_mc_mac_addr(hns, false); 5897 if (ret) 5898 goto err_mc_mac; 5899 5900 ret = hns3_dev_promisc_restore(hns); 5901 if (ret) 5902 goto err_promisc; 5903 5904 ret = hns3_restore_vlan_table(hns); 5905 if (ret) 5906 goto err_promisc; 5907 5908 ret = hns3_restore_vlan_conf(hns); 5909 if (ret) 5910 goto err_promisc; 5911 5912 ret = hns3_restore_ptp(hns); 5913 if (ret) 5914 goto err_promisc; 5915 5916 ret = hns3_restore_rx_interrupt(hw); 5917 if (ret) 5918 goto err_promisc; 5919 5920 ret = hns3_restore_gro_conf(hw); 5921 if (ret) 5922 goto err_promisc; 5923 5924 ret = hns3_restore_fec(hw); 5925 if (ret) 5926 goto err_promisc; 5927 5928 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 5929 ret = hns3_do_start(hns, false); 5930 if (ret) 5931 goto err_promisc; 5932 hns3_info(hw, "hns3 dev restart successful!"); 5933 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 5934 hw->adapter_state = HNS3_NIC_CONFIGURED; 5935 return 0; 5936 5937 err_promisc: 5938 hns3_configure_all_mc_mac_addr(hns, true); 5939 err_mc_mac: 5940 hns3_configure_all_mac_addr(hns, true); 5941 return ret; 5942 } 5943 5944 static void 5945 hns3_reset_service(void *param) 5946 { 5947 struct hns3_adapter *hns = (struct hns3_adapter *)param; 5948 struct hns3_hw *hw = &hns->hw; 5949 enum hns3_reset_level reset_level; 5950 struct timeval tv_delta; 5951 struct timeval tv_start; 5952 struct timeval tv; 5953 uint64_t msec; 5954 int ret; 5955 5956 /* 5957 * The interrupt is not triggered within the delay time. 5958 * The interrupt may have been lost. It is necessary to handle 5959 * the interrupt to recover from the error. 5960 */ 5961 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 5962 SCHEDULE_DEFERRED) { 5963 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 5964 __ATOMIC_RELAXED); 5965 hns3_err(hw, "Handling interrupts in delayed tasks"); 5966 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 5967 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5968 if (reset_level == HNS3_NONE_RESET) { 5969 hns3_err(hw, "No reset level is set, try IMP reset"); 5970 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 5971 } 5972 } 5973 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 5974 5975 /* 5976 * Check if there is any ongoing reset in the hardware. This status can 5977 * be checked from reset_pending. If there is then, we need to wait for 5978 * hardware to complete reset. 5979 * a. If we are able to figure out in reasonable time that hardware 5980 * has fully resetted then, we can proceed with driver, client 5981 * reset. 5982 * b. else, we can come back later to check this status so re-sched 5983 * now. 5984 */ 5985 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5986 if (reset_level != HNS3_NONE_RESET) { 5987 hns3_clock_gettime(&tv_start); 5988 ret = hns3_reset_process(hns, reset_level); 5989 hns3_clock_gettime(&tv); 5990 timersub(&tv, &tv_start, &tv_delta); 5991 msec = hns3_clock_calctime_ms(&tv_delta); 5992 if (msec > HNS3_RESET_PROCESS_MS) 5993 hns3_err(hw, "%d handle long time delta %" PRIu64 " ms time=%ld.%.6ld", 5994 hw->reset.level, msec, 5995 tv.tv_sec, tv.tv_usec); 5996 if (ret == -EAGAIN) 5997 return; 5998 } 5999 6000 /* Check if we got any *new* reset requests to be honored */ 6001 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 6002 if (reset_level != HNS3_NONE_RESET) 6003 hns3_msix_process(hns, reset_level); 6004 } 6005 6006 static unsigned int 6007 hns3_get_speed_capa_num(uint16_t device_id) 6008 { 6009 unsigned int num; 6010 6011 switch (device_id) { 6012 case HNS3_DEV_ID_25GE: 6013 case HNS3_DEV_ID_25GE_RDMA: 6014 num = 2; 6015 break; 6016 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6017 case HNS3_DEV_ID_200G_RDMA: 6018 num = 1; 6019 break; 6020 default: 6021 num = 0; 6022 break; 6023 } 6024 6025 return num; 6026 } 6027 6028 static int 6029 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, 6030 uint16_t device_id) 6031 { 6032 switch (device_id) { 6033 case HNS3_DEV_ID_25GE: 6034 /* fallthrough */ 6035 case HNS3_DEV_ID_25GE_RDMA: 6036 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed; 6037 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa; 6038 6039 /* In HNS3 device, the 25G NIC is compatible with 10G rate */ 6040 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed; 6041 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa; 6042 break; 6043 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6044 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed; 6045 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa; 6046 break; 6047 case HNS3_DEV_ID_200G_RDMA: 6048 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed; 6049 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa; 6050 break; 6051 default: 6052 return -ENOTSUP; 6053 } 6054 6055 return 0; 6056 } 6057 6058 static int 6059 hns3_fec_get_capability(struct rte_eth_dev *dev, 6060 struct rte_eth_fec_capa *speed_fec_capa, 6061 unsigned int num) 6062 { 6063 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6064 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6065 uint16_t device_id = pci_dev->id.device_id; 6066 unsigned int capa_num; 6067 int ret; 6068 6069 capa_num = hns3_get_speed_capa_num(device_id); 6070 if (capa_num == 0) { 6071 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD", 6072 device_id); 6073 return -ENOTSUP; 6074 } 6075 6076 if (speed_fec_capa == NULL || num < capa_num) 6077 return capa_num; 6078 6079 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id); 6080 if (ret) 6081 return -ENOTSUP; 6082 6083 return capa_num; 6084 } 6085 6086 static int 6087 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state) 6088 { 6089 struct hns3_config_fec_cmd *req; 6090 struct hns3_cmd_desc desc; 6091 int ret; 6092 6093 /* 6094 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported 6095 * in device of link speed 6096 * below 10 Gbps. 6097 */ 6098 if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) { 6099 *state = 0; 6100 return 0; 6101 } 6102 6103 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true); 6104 req = (struct hns3_config_fec_cmd *)desc.data; 6105 ret = hns3_cmd_send(hw, &desc, 1); 6106 if (ret) { 6107 hns3_err(hw, "get current fec auto state failed, ret = %d", 6108 ret); 6109 return ret; 6110 } 6111 6112 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B); 6113 return 0; 6114 } 6115 6116 static int 6117 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa) 6118 { 6119 struct hns3_sfp_info_cmd *resp; 6120 uint32_t tmp_fec_capa; 6121 uint8_t auto_state; 6122 struct hns3_cmd_desc desc; 6123 int ret; 6124 6125 /* 6126 * If link is down and AUTO is enabled, AUTO is returned, otherwise, 6127 * configured FEC mode is returned. 6128 * If link is up, current FEC mode is returned. 6129 */ 6130 if (hw->mac.link_status == RTE_ETH_LINK_DOWN) { 6131 ret = get_current_fec_auto_state(hw, &auto_state); 6132 if (ret) 6133 return ret; 6134 6135 if (auto_state == 0x1) { 6136 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 6137 return 0; 6138 } 6139 } 6140 6141 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 6142 resp = (struct hns3_sfp_info_cmd *)desc.data; 6143 resp->query_type = HNS3_ACTIVE_QUERY; 6144 6145 ret = hns3_cmd_send(hw, &desc, 1); 6146 if (ret == -EOPNOTSUPP) { 6147 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret); 6148 return ret; 6149 } else if (ret) { 6150 hns3_err(hw, "get FEC failed, ret = %d", ret); 6151 return ret; 6152 } 6153 6154 /* 6155 * FEC mode order defined in hns3 hardware is inconsistent with 6156 * that defined in the ethdev library. So the sequence needs 6157 * to be converted. 6158 */ 6159 switch (resp->active_fec) { 6160 case HNS3_HW_FEC_MODE_NOFEC: 6161 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6162 break; 6163 case HNS3_HW_FEC_MODE_BASER: 6164 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 6165 break; 6166 case HNS3_HW_FEC_MODE_RS: 6167 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 6168 break; 6169 default: 6170 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6171 break; 6172 } 6173 6174 *fec_capa = tmp_fec_capa; 6175 return 0; 6176 } 6177 6178 static int 6179 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 6180 { 6181 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6182 6183 return hns3_fec_get_internal(hw, fec_capa); 6184 } 6185 6186 static int 6187 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode) 6188 { 6189 struct hns3_config_fec_cmd *req; 6190 struct hns3_cmd_desc desc; 6191 int ret; 6192 6193 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false); 6194 6195 req = (struct hns3_config_fec_cmd *)desc.data; 6196 switch (mode) { 6197 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC): 6198 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6199 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF); 6200 break; 6201 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER): 6202 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6203 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER); 6204 break; 6205 case RTE_ETH_FEC_MODE_CAPA_MASK(RS): 6206 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6207 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS); 6208 break; 6209 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO): 6210 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1); 6211 break; 6212 default: 6213 return 0; 6214 } 6215 ret = hns3_cmd_send(hw, &desc, 1); 6216 if (ret) 6217 hns3_err(hw, "set fec mode failed, ret = %d", ret); 6218 6219 return ret; 6220 } 6221 6222 static uint32_t 6223 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa) 6224 { 6225 struct hns3_mac *mac = &hw->mac; 6226 uint32_t cur_capa; 6227 6228 switch (mac->link_speed) { 6229 case RTE_ETH_SPEED_NUM_10G: 6230 cur_capa = fec_capa[1].capa; 6231 break; 6232 case RTE_ETH_SPEED_NUM_25G: 6233 case RTE_ETH_SPEED_NUM_100G: 6234 case RTE_ETH_SPEED_NUM_200G: 6235 cur_capa = fec_capa[0].capa; 6236 break; 6237 default: 6238 cur_capa = 0; 6239 break; 6240 } 6241 6242 return cur_capa; 6243 } 6244 6245 static bool 6246 is_fec_mode_one_bit_set(uint32_t mode) 6247 { 6248 int cnt = 0; 6249 uint8_t i; 6250 6251 for (i = 0; i < sizeof(mode); i++) 6252 if (mode >> i & 0x1) 6253 cnt++; 6254 6255 return cnt == 1 ? true : false; 6256 } 6257 6258 static int 6259 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode) 6260 { 6261 #define FEC_CAPA_NUM 2 6262 struct hns3_adapter *hns = dev->data->dev_private; 6263 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6264 struct hns3_pf *pf = &hns->pf; 6265 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM]; 6266 uint32_t cur_capa; 6267 uint32_t num = FEC_CAPA_NUM; 6268 int ret; 6269 6270 ret = hns3_fec_get_capability(dev, fec_capa, num); 6271 if (ret < 0) 6272 return ret; 6273 6274 /* HNS3 PMD only support one bit set mode, e.g. 0x1, 0x4 */ 6275 if (!is_fec_mode_one_bit_set(mode)) { 6276 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, " 6277 "FEC mode should be only one bit set", mode); 6278 return -EINVAL; 6279 } 6280 6281 /* 6282 * Check whether the configured mode is within the FEC capability. 6283 * If not, the configured mode will not be supported. 6284 */ 6285 cur_capa = get_current_speed_fec_cap(hw, fec_capa); 6286 if (!(cur_capa & mode)) { 6287 hns3_err(hw, "unsupported FEC mode = 0x%x", mode); 6288 return -EINVAL; 6289 } 6290 6291 rte_spinlock_lock(&hw->lock); 6292 ret = hns3_set_fec_hw(hw, mode); 6293 if (ret) { 6294 rte_spinlock_unlock(&hw->lock); 6295 return ret; 6296 } 6297 6298 pf->fec_mode = mode; 6299 rte_spinlock_unlock(&hw->lock); 6300 6301 return 0; 6302 } 6303 6304 static int 6305 hns3_restore_fec(struct hns3_hw *hw) 6306 { 6307 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 6308 struct hns3_pf *pf = &hns->pf; 6309 uint32_t mode = pf->fec_mode; 6310 int ret; 6311 6312 ret = hns3_set_fec_hw(hw, mode); 6313 if (ret) 6314 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d", 6315 mode, ret); 6316 6317 return ret; 6318 } 6319 6320 static int 6321 hns3_query_dev_fec_info(struct hns3_hw *hw) 6322 { 6323 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 6324 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns); 6325 int ret; 6326 6327 ret = hns3_fec_get_internal(hw, &pf->fec_mode); 6328 if (ret) 6329 hns3_err(hw, "query device FEC info failed, ret = %d", ret); 6330 6331 return ret; 6332 } 6333 6334 static bool 6335 hns3_optical_module_existed(struct hns3_hw *hw) 6336 { 6337 struct hns3_cmd_desc desc; 6338 bool existed; 6339 int ret; 6340 6341 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true); 6342 ret = hns3_cmd_send(hw, &desc, 1); 6343 if (ret) { 6344 hns3_err(hw, 6345 "fail to get optical module exist state, ret = %d.\n", 6346 ret); 6347 return false; 6348 } 6349 existed = !!desc.data[0]; 6350 6351 return existed; 6352 } 6353 6354 static int 6355 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset, 6356 uint32_t len, uint8_t *data) 6357 { 6358 #define HNS3_SFP_INFO_CMD_NUM 6 6359 #define HNS3_SFP_INFO_MAX_LEN \ 6360 (HNS3_SFP_INFO_BD0_LEN + \ 6361 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN) 6362 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM]; 6363 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0; 6364 uint16_t read_len; 6365 uint16_t copy_len; 6366 int ret; 6367 int i; 6368 6369 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) { 6370 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM, 6371 true); 6372 if (i < HNS3_SFP_INFO_CMD_NUM - 1) 6373 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 6374 } 6375 6376 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data; 6377 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset); 6378 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN); 6379 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len); 6380 6381 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM); 6382 if (ret) { 6383 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n", 6384 ret); 6385 return ret; 6386 } 6387 6388 /* The data format in BD0 is different with the others. */ 6389 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN); 6390 memcpy(data, sfp_info_bd0->data, copy_len); 6391 read_len = copy_len; 6392 6393 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) { 6394 if (read_len >= len) 6395 break; 6396 6397 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN); 6398 memcpy(data + read_len, desc[i].data, copy_len); 6399 read_len += copy_len; 6400 } 6401 6402 return (int)read_len; 6403 } 6404 6405 static int 6406 hns3_get_module_eeprom(struct rte_eth_dev *dev, 6407 struct rte_dev_eeprom_info *info) 6408 { 6409 struct hns3_adapter *hns = dev->data->dev_private; 6410 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6411 uint32_t offset = info->offset; 6412 uint32_t len = info->length; 6413 uint8_t *data = info->data; 6414 uint32_t read_len = 0; 6415 6416 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER) 6417 return -ENOTSUP; 6418 6419 if (!hns3_optical_module_existed(hw)) { 6420 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n"); 6421 return -EIO; 6422 } 6423 6424 while (read_len < len) { 6425 int ret; 6426 ret = hns3_get_module_eeprom_data(hw, offset + read_len, 6427 len - read_len, 6428 data + read_len); 6429 if (ret < 0) 6430 return -EIO; 6431 read_len += ret; 6432 } 6433 6434 return 0; 6435 } 6436 6437 static int 6438 hns3_get_module_info(struct rte_eth_dev *dev, 6439 struct rte_eth_dev_module_info *modinfo) 6440 { 6441 #define HNS3_SFF8024_ID_SFP 0x03 6442 #define HNS3_SFF8024_ID_QSFP_8438 0x0c 6443 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d 6444 #define HNS3_SFF8024_ID_QSFP28_8636 0x11 6445 #define HNS3_SFF_8636_V1_3 0x03 6446 struct hns3_adapter *hns = dev->data->dev_private; 6447 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6448 struct rte_dev_eeprom_info info; 6449 struct hns3_sfp_type sfp_type; 6450 int ret; 6451 6452 memset(&sfp_type, 0, sizeof(sfp_type)); 6453 memset(&info, 0, sizeof(info)); 6454 info.data = (uint8_t *)&sfp_type; 6455 info.length = sizeof(sfp_type); 6456 ret = hns3_get_module_eeprom(dev, &info); 6457 if (ret) 6458 return ret; 6459 6460 switch (sfp_type.type) { 6461 case HNS3_SFF8024_ID_SFP: 6462 modinfo->type = RTE_ETH_MODULE_SFF_8472; 6463 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 6464 break; 6465 case HNS3_SFF8024_ID_QSFP_8438: 6466 modinfo->type = RTE_ETH_MODULE_SFF_8436; 6467 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 6468 break; 6469 case HNS3_SFF8024_ID_QSFP_8436_8636: 6470 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) { 6471 modinfo->type = RTE_ETH_MODULE_SFF_8436; 6472 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 6473 } else { 6474 modinfo->type = RTE_ETH_MODULE_SFF_8636; 6475 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 6476 } 6477 break; 6478 case HNS3_SFF8024_ID_QSFP28_8636: 6479 modinfo->type = RTE_ETH_MODULE_SFF_8636; 6480 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 6481 break; 6482 default: 6483 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n", 6484 sfp_type.type, sfp_type.ext_type); 6485 return -EINVAL; 6486 } 6487 6488 return 0; 6489 } 6490 6491 static const struct eth_dev_ops hns3_eth_dev_ops = { 6492 .dev_configure = hns3_dev_configure, 6493 .dev_start = hns3_dev_start, 6494 .dev_stop = hns3_dev_stop, 6495 .dev_close = hns3_dev_close, 6496 .promiscuous_enable = hns3_dev_promiscuous_enable, 6497 .promiscuous_disable = hns3_dev_promiscuous_disable, 6498 .allmulticast_enable = hns3_dev_allmulticast_enable, 6499 .allmulticast_disable = hns3_dev_allmulticast_disable, 6500 .mtu_set = hns3_dev_mtu_set, 6501 .stats_get = hns3_stats_get, 6502 .stats_reset = hns3_stats_reset, 6503 .xstats_get = hns3_dev_xstats_get, 6504 .xstats_get_names = hns3_dev_xstats_get_names, 6505 .xstats_reset = hns3_dev_xstats_reset, 6506 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 6507 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 6508 .dev_infos_get = hns3_dev_infos_get, 6509 .fw_version_get = hns3_fw_version_get, 6510 .rx_queue_setup = hns3_rx_queue_setup, 6511 .tx_queue_setup = hns3_tx_queue_setup, 6512 .rx_queue_release = hns3_dev_rx_queue_release, 6513 .tx_queue_release = hns3_dev_tx_queue_release, 6514 .rx_queue_start = hns3_dev_rx_queue_start, 6515 .rx_queue_stop = hns3_dev_rx_queue_stop, 6516 .tx_queue_start = hns3_dev_tx_queue_start, 6517 .tx_queue_stop = hns3_dev_tx_queue_stop, 6518 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 6519 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 6520 .rxq_info_get = hns3_rxq_info_get, 6521 .txq_info_get = hns3_txq_info_get, 6522 .rx_burst_mode_get = hns3_rx_burst_mode_get, 6523 .tx_burst_mode_get = hns3_tx_burst_mode_get, 6524 .flow_ctrl_get = hns3_flow_ctrl_get, 6525 .flow_ctrl_set = hns3_flow_ctrl_set, 6526 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 6527 .mac_addr_add = hns3_add_mac_addr, 6528 .mac_addr_remove = hns3_remove_mac_addr, 6529 .mac_addr_set = hns3_set_default_mac_addr, 6530 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 6531 .link_update = hns3_dev_link_update, 6532 .dev_set_link_up = hns3_dev_set_link_up, 6533 .dev_set_link_down = hns3_dev_set_link_down, 6534 .rss_hash_update = hns3_dev_rss_hash_update, 6535 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 6536 .reta_update = hns3_dev_rss_reta_update, 6537 .reta_query = hns3_dev_rss_reta_query, 6538 .flow_ops_get = hns3_dev_flow_ops_get, 6539 .vlan_filter_set = hns3_vlan_filter_set, 6540 .vlan_tpid_set = hns3_vlan_tpid_set, 6541 .vlan_offload_set = hns3_vlan_offload_set, 6542 .vlan_pvid_set = hns3_vlan_pvid_set, 6543 .get_reg = hns3_get_regs, 6544 .get_module_info = hns3_get_module_info, 6545 .get_module_eeprom = hns3_get_module_eeprom, 6546 .get_dcb_info = hns3_get_dcb_info, 6547 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 6548 .fec_get_capability = hns3_fec_get_capability, 6549 .fec_get = hns3_fec_get, 6550 .fec_set = hns3_fec_set, 6551 .tm_ops_get = hns3_tm_ops_get, 6552 .tx_done_cleanup = hns3_tx_done_cleanup, 6553 .timesync_enable = hns3_timesync_enable, 6554 .timesync_disable = hns3_timesync_disable, 6555 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp, 6556 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp, 6557 .timesync_adjust_time = hns3_timesync_adjust_time, 6558 .timesync_read_time = hns3_timesync_read_time, 6559 .timesync_write_time = hns3_timesync_write_time, 6560 .eth_dev_priv_dump = hns3_eth_dev_priv_dump, 6561 .eth_rx_descriptor_dump = hns3_rx_descriptor_dump, 6562 .eth_tx_descriptor_dump = hns3_tx_descriptor_dump, 6563 }; 6564 6565 static const struct hns3_reset_ops hns3_reset_ops = { 6566 .reset_service = hns3_reset_service, 6567 .stop_service = hns3_stop_service, 6568 .prepare_reset = hns3_prepare_reset, 6569 .wait_hardware_ready = hns3_wait_hardware_ready, 6570 .reinit_dev = hns3_reinit_dev, 6571 .restore_conf = hns3_restore_conf, 6572 .start_service = hns3_start_service, 6573 }; 6574 6575 static void 6576 hns3_init_hw_ops(struct hns3_hw *hw) 6577 { 6578 hw->ops.add_mc_mac_addr = hns3_add_mc_mac_addr; 6579 hw->ops.del_mc_mac_addr = hns3_remove_mc_mac_addr; 6580 hw->ops.add_uc_mac_addr = hns3_add_uc_mac_addr; 6581 hw->ops.del_uc_mac_addr = hns3_remove_uc_mac_addr; 6582 hw->ops.bind_ring_with_vector = hns3_bind_ring_with_vector; 6583 } 6584 6585 static int 6586 hns3_dev_init(struct rte_eth_dev *eth_dev) 6587 { 6588 struct hns3_adapter *hns = eth_dev->data->dev_private; 6589 struct hns3_hw *hw = &hns->hw; 6590 int ret; 6591 6592 PMD_INIT_FUNC_TRACE(); 6593 6594 hns3_flow_init(eth_dev); 6595 6596 hns3_set_rxtx_function(eth_dev); 6597 eth_dev->dev_ops = &hns3_eth_dev_ops; 6598 eth_dev->rx_queue_count = hns3_rx_queue_count; 6599 ret = hns3_mp_init(eth_dev); 6600 if (ret) 6601 goto err_mp_init; 6602 6603 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 6604 hns3_tx_push_init(eth_dev); 6605 return 0; 6606 } 6607 6608 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 6609 hns->is_vf = false; 6610 hw->data = eth_dev->data; 6611 hns3_parse_devargs(eth_dev); 6612 6613 /* 6614 * Set default max packet size according to the mtu 6615 * default vale in DPDK frame. 6616 */ 6617 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 6618 6619 ret = hns3_reset_init(hw); 6620 if (ret) 6621 goto err_init_reset; 6622 hw->reset.ops = &hns3_reset_ops; 6623 6624 hns3_init_hw_ops(hw); 6625 ret = hns3_init_pf(eth_dev); 6626 if (ret) { 6627 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 6628 goto err_init_pf; 6629 } 6630 6631 ret = hns3_init_mac_addrs(eth_dev); 6632 if (ret != 0) 6633 goto err_init_mac_addrs; 6634 6635 hw->adapter_state = HNS3_NIC_INITIALIZED; 6636 6637 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 6638 SCHEDULE_PENDING) { 6639 hns3_err(hw, "Reschedule reset service after dev_init"); 6640 hns3_schedule_reset(hns); 6641 } else { 6642 /* IMP will wait ready flag before reset */ 6643 hns3_notify_reset_ready(hw, false); 6644 } 6645 6646 hns3_info(hw, "hns3 dev initialization successful!"); 6647 return 0; 6648 6649 err_init_mac_addrs: 6650 hns3_uninit_pf(eth_dev); 6651 6652 err_init_pf: 6653 rte_free(hw->reset.wait_data); 6654 6655 err_init_reset: 6656 hns3_mp_uninit(eth_dev); 6657 6658 err_mp_init: 6659 eth_dev->dev_ops = NULL; 6660 eth_dev->rx_pkt_burst = NULL; 6661 eth_dev->rx_descriptor_status = NULL; 6662 eth_dev->tx_pkt_burst = NULL; 6663 eth_dev->tx_pkt_prepare = NULL; 6664 eth_dev->tx_descriptor_status = NULL; 6665 return ret; 6666 } 6667 6668 static int 6669 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 6670 { 6671 struct hns3_adapter *hns = eth_dev->data->dev_private; 6672 struct hns3_hw *hw = &hns->hw; 6673 6674 PMD_INIT_FUNC_TRACE(); 6675 6676 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 6677 hns3_mp_uninit(eth_dev); 6678 return 0; 6679 } 6680 6681 if (hw->adapter_state < HNS3_NIC_CLOSING) 6682 hns3_dev_close(eth_dev); 6683 6684 hw->adapter_state = HNS3_NIC_REMOVED; 6685 return 0; 6686 } 6687 6688 static int 6689 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6690 struct rte_pci_device *pci_dev) 6691 { 6692 return rte_eth_dev_pci_generic_probe(pci_dev, 6693 sizeof(struct hns3_adapter), 6694 hns3_dev_init); 6695 } 6696 6697 static int 6698 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 6699 { 6700 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 6701 } 6702 6703 static const struct rte_pci_id pci_id_hns3_map[] = { 6704 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 6705 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 6706 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 6707 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 6708 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 6709 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, 6710 { .vendor_id = 0, }, /* sentinel */ 6711 }; 6712 6713 static struct rte_pci_driver rte_hns3_pmd = { 6714 .id_table = pci_id_hns3_map, 6715 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 6716 .probe = eth_hns3_pci_probe, 6717 .remove = eth_hns3_pci_remove, 6718 }; 6719 6720 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 6721 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 6722 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 6723 RTE_PMD_REGISTER_PARAM_STRING(net_hns3, 6724 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " 6725 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common " 6726 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> " 6727 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> "); 6728 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE); 6729 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE); 6730