1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2022 HiSilicon Limited 3 */ 4 5 #include <rte_malloc.h> 6 7 #include "hns3_common.h" 8 #include "hns3_logs.h" 9 #include "hns3_regs.h" 10 #include "hns3_rxtx.h" 11 #include "hns3_dump.h" 12 13 #define HNS3_BD_DW_NUM 8 14 #define HNS3_BD_ADDRESS_LAST_DW 2 15 16 static const char * 17 hns3_get_adapter_state_name(enum hns3_adapter_state state) 18 { 19 const struct { 20 enum hns3_adapter_state state; 21 const char *name; 22 } adapter_state_name[] = { 23 {HNS3_NIC_UNINITIALIZED, "UNINITIALIZED"}, 24 {HNS3_NIC_INITIALIZED, "INITIALIZED"}, 25 {HNS3_NIC_CONFIGURING, "CONFIGURING"}, 26 {HNS3_NIC_CONFIGURED, "CONFIGURED"}, 27 {HNS3_NIC_STARTING, "STARTING"}, 28 {HNS3_NIC_STARTED, "STARTED"}, 29 {HNS3_NIC_STOPPING, "STOPPING"}, 30 {HNS3_NIC_CLOSING, "CLOSING"}, 31 {HNS3_NIC_CLOSED, "CLOSED"}, 32 {HNS3_NIC_REMOVED, "REMOVED"}, 33 {HNS3_NIC_NSTATES, "NSTATES"}, 34 }; 35 uint32_t i; 36 37 for (i = 0; i < RTE_DIM(adapter_state_name); i++) 38 if (state == adapter_state_name[i].state) 39 return adapter_state_name[i].name; 40 41 return "Unknown"; 42 } 43 44 static const char * 45 hns3_get_io_func_hint_name(uint32_t hint) 46 { 47 switch (hint) { 48 case HNS3_IO_FUNC_HINT_NONE: 49 return "none"; 50 case HNS3_IO_FUNC_HINT_VEC: 51 return "vec"; 52 case HNS3_IO_FUNC_HINT_SVE: 53 return "sve"; 54 case HNS3_IO_FUNC_HINT_SIMPLE: 55 return "simple"; 56 case HNS3_IO_FUNC_HINT_COMMON: 57 return "common"; 58 default: 59 return "unknown"; 60 } 61 } 62 63 static void 64 hns3_get_dev_mac_info(FILE *file, struct hns3_adapter *hns) 65 { 66 struct hns3_hw *hw = &hns->hw; 67 struct hns3_pf *pf = &hns->pf; 68 69 fprintf(file, " - MAC Info:\n"); 70 fprintf(file, 71 "\t -- media_type=%s\n" 72 "\t -- query_type=%u\n" 73 "\t -- supported_speed=0x%x\n" 74 "\t -- advertising=0x%x\n" 75 "\t -- lp_advertising=0x%x\n" 76 "\t -- support_autoneg=%s\n" 77 "\t -- support_fc_autoneg=%s\n", 78 hns3_get_media_type_name(hw->mac.media_type), 79 hw->mac.query_type, 80 hw->mac.supported_speed, 81 hw->mac.advertising, 82 hw->mac.lp_advertising, 83 hw->mac.support_autoneg != 0 ? "Yes" : "No", 84 pf->support_fc_autoneg ? "Yes" : "No"); 85 } 86 87 static void 88 hns3_get_dev_feature_capability(FILE *file, struct hns3_hw *hw) 89 { 90 const struct { 91 enum hns3_dev_cap cap; 92 const char *name; 93 } caps_name[] = { 94 {HNS3_DEV_SUPPORT_DCB_B, "DCB"}, 95 {HNS3_DEV_SUPPORT_COPPER_B, "COPPER"}, 96 {HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B, "FD QUEUE REGION"}, 97 {HNS3_DEV_SUPPORT_PTP_B, "PTP"}, 98 {HNS3_DEV_SUPPORT_TX_PUSH_B, "TX PUSH"}, 99 {HNS3_DEV_SUPPORT_INDEP_TXRX_B, "INDEP TXRX"}, 100 {HNS3_DEV_SUPPORT_STASH_B, "STASH"}, 101 {HNS3_DEV_SUPPORT_SIMPLE_BD_B, "SIMPLE BD"}, 102 {HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, "RXD Advanced Layout"}, 103 {HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, "OUTER UDP CKSUM"}, 104 {HNS3_DEV_SUPPORT_RAS_IMP_B, "RAS IMP"}, 105 {HNS3_DEV_SUPPORT_TM_B, "TM"}, 106 {HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, "VF VLAN FILTER MOD"}, 107 {HNS3_DEV_SUPPORT_FC_AUTO_B, "FC AUTO"}, 108 {HNS3_DEV_SUPPORT_GRO_B, "GRO"} 109 }; 110 uint32_t i; 111 112 fprintf(file, " - Dev Capability:\n"); 113 for (i = 0; i < RTE_DIM(caps_name); i++) 114 fprintf(file, "\t -- support %s: %s\n", caps_name[i].name, 115 hns3_get_bit(hw->capability, caps_name[i].cap) ? "Yes" : 116 "No"); 117 } 118 119 static const char * 120 hns3_get_fdir_tuple_name(uint32_t index) 121 { 122 const char * const tuple_name[] = { 123 "outer_dst_mac", 124 "outer_src_mac", 125 "outer_vlan_1st_tag", 126 "outer_vlan_2nd_tag", 127 "outer_eth_type", 128 "outer_l2_rsv", 129 "outer_ip_tos", 130 "outer_ip_proto", 131 "outer_src_ip", 132 "outer_dst_ip", 133 "outer_l3_rsv", 134 "outer_src_port", 135 "outer_dst_port", 136 "outer_l4_rsv", 137 "outer_tun_vni", 138 "outer_tun_flow_id", 139 "inner_dst_mac", 140 "inner_src_mac", 141 "inner_vlan_tag1", 142 "inner_vlan_tag2", 143 "inner_eth_type", 144 "inner_l2_rsv", 145 "inner_ip_tos", 146 "inner_ip_proto", 147 "inner_src_ip", 148 "inner_dst_ip", 149 "inner_l3_rsv", 150 "inner_src_port", 151 "inner_dst_port", 152 "inner_sctp_tag", 153 }; 154 if (index < RTE_DIM(tuple_name)) 155 return tuple_name[index]; 156 else 157 return "unknown"; 158 } 159 160 static void 161 hns3_get_fdir_basic_info(FILE *file, struct hns3_pf *pf) 162 { 163 #define HNS3_PERLINE_TUPLE_NAME_LEN 4 164 struct hns3_fd_cfg *fdcfg = &pf->fdir.fd_cfg; 165 uint32_t i, count = 0; 166 167 fprintf(file, " - Fdir Info:\n"); 168 fprintf(file, 169 "\t -- mode=%u max_key_len=%u rule_num:%u cnt_num:%u\n" 170 "\t -- key_sel=%u tuple_active=0x%x meta_data_active=0x%x\n" 171 "\t -- ipv6_word_en: in_s=%u in_d=%u out_s=%u out_d=%u\n" 172 "\t -- index_cfg: %s\n" 173 "\t -- tuple_config: %s\n" 174 "\t -- active_tuples:\n", 175 fdcfg->fd_mode, fdcfg->max_key_length, 176 fdcfg->rule_num[HNS3_FD_STAGE_1], 177 fdcfg->cnt_num[HNS3_FD_STAGE_1], 178 fdcfg->key_cfg[HNS3_FD_STAGE_1].key_sel, 179 fdcfg->key_cfg[HNS3_FD_STAGE_1].tuple_active, 180 fdcfg->key_cfg[HNS3_FD_STAGE_1].meta_data_active, 181 fdcfg->key_cfg[HNS3_FD_STAGE_1].inner_sipv6_word_en, 182 fdcfg->key_cfg[HNS3_FD_STAGE_1].inner_dipv6_word_en, 183 fdcfg->key_cfg[HNS3_FD_STAGE_1].outer_sipv6_word_en, 184 fdcfg->key_cfg[HNS3_FD_STAGE_1].outer_dipv6_word_en, 185 hns3_fdir_index_config_name(pf->fdir.index_cfg), 186 hns3_tuple_config_name(pf->fdir.tuple_cfg)); 187 188 for (i = 0; i < MAX_TUPLE; i++) { 189 if (!(fdcfg->key_cfg[HNS3_FD_STAGE_1].tuple_active & BIT(i))) 190 continue; 191 if (count % HNS3_PERLINE_TUPLE_NAME_LEN == 0) 192 fprintf(file, "\t "); 193 fprintf(file, " %s", hns3_get_fdir_tuple_name(i)); 194 count++; 195 if (count % HNS3_PERLINE_TUPLE_NAME_LEN == 0) 196 fprintf(file, "\n"); 197 } 198 if (count % HNS3_PERLINE_TUPLE_NAME_LEN) 199 fprintf(file, "\n"); 200 } 201 202 static void 203 hns3_get_device_basic_info(FILE *file, struct rte_eth_dev *dev) 204 { 205 struct hns3_adapter *hns = dev->data->dev_private; 206 struct hns3_hw *hw = &hns->hw; 207 208 fprintf(file, 209 " - Device Base Info:\n" 210 "\t -- name: %s\n" 211 "\t -- adapter_state=%s\n" 212 "\t -- nb_rx_queues=%u nb_tx_queues=%u\n" 213 "\t -- total_tqps_num=%u tqps_num=%u intr_tqps_num=%u\n" 214 "\t -- rss_size_max=%u alloc_rss_size=%u tx_qnum_per_tc=%u\n" 215 "\t -- min_tx_pkt_len=%u intr_mapping_mode=%u vlan_mode=%u\n" 216 "\t -- tso_mode=%u max_non_tso_bd_num=%u\n" 217 "\t -- max_tm_rate=%u Mbps\n" 218 "\t -- set link down: %s\n" 219 "\t -- rx_func_hint=%s tx_func_hint=%s\n" 220 "\t -- dev_flags: lsc=%d\n" 221 "\t -- intr_conf: lsc=%u rxq=%u\n", 222 dev->data->name, 223 hns3_get_adapter_state_name(hw->adapter_state), 224 dev->data->nb_rx_queues, dev->data->nb_tx_queues, 225 hw->total_tqps_num, hw->tqps_num, hw->intr_tqps_num, 226 hw->rss_size_max, hw->alloc_rss_size, hw->tx_qnum_per_tc, 227 hw->min_tx_pkt_len, hw->intr.mapping_mode, hw->vlan_mode, 228 hw->tso_mode, hw->max_non_tso_bd_num, 229 hw->max_tm_rate, 230 hw->set_link_down ? "Yes" : "No", 231 hns3_get_io_func_hint_name(hns->rx_func_hint), 232 hns3_get_io_func_hint_name(hns->tx_func_hint), 233 !!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC), 234 dev->data->dev_conf.intr_conf.lsc, 235 dev->data->dev_conf.intr_conf.rxq); 236 } 237 238 static struct hns3_rx_queue * 239 hns3_get_rx_queue(struct rte_eth_dev *dev) 240 { 241 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 242 struct hns3_rx_queue *rxq; 243 uint32_t queue_id; 244 void **rx_queues; 245 246 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) { 247 rx_queues = dev->data->rx_queues; 248 if (rx_queues == NULL || rx_queues[queue_id] == NULL) { 249 hns3_err(hw, "detect rx_queues is NULL!"); 250 return NULL; 251 } 252 253 rxq = (struct hns3_rx_queue *)rx_queues[queue_id]; 254 if (rxq->rx_deferred_start) 255 continue; 256 257 return rx_queues[queue_id]; 258 } 259 260 return NULL; 261 } 262 263 static struct hns3_tx_queue * 264 hns3_get_tx_queue(struct rte_eth_dev *dev) 265 { 266 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 267 struct hns3_tx_queue *txq; 268 uint32_t queue_id; 269 void **tx_queues; 270 271 for (queue_id = 0; queue_id < dev->data->nb_tx_queues; queue_id++) { 272 tx_queues = dev->data->tx_queues; 273 if (tx_queues == NULL || tx_queues[queue_id] == NULL) { 274 hns3_err(hw, "detect tx_queues is NULL!"); 275 return NULL; 276 } 277 278 txq = (struct hns3_tx_queue *)tx_queues[queue_id]; 279 if (txq->tx_deferred_start) 280 continue; 281 282 return tx_queues[queue_id]; 283 } 284 285 return NULL; 286 } 287 288 static void 289 hns3_get_rxtx_fake_queue_info(FILE *file, struct rte_eth_dev *dev) 290 { 291 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 292 struct hns3_rx_queue *rxq; 293 struct hns3_tx_queue *txq; 294 uint32_t queue_id = 0; 295 void **rx_queues; 296 void **tx_queues; 297 298 if (hns3_dev_get_support(hw, INDEP_TXRX)) 299 return; 300 301 if (dev->data->nb_rx_queues < dev->data->nb_tx_queues) { 302 rx_queues = hw->fkq_data.rx_queues; 303 if (rx_queues == NULL || rx_queues[queue_id] == NULL) { 304 hns3_err(hw, "detect rx_queues is NULL!"); 305 return; 306 } 307 rxq = (struct hns3_rx_queue *)rx_queues[queue_id]; 308 309 fprintf(file, 310 "\t -- first fake_queue info:\n" 311 "\t Rx: port=%u nb_desc=%u free_thresh=%u\n", 312 rxq->port_id, rxq->nb_rx_desc, rxq->rx_free_thresh); 313 } else if (dev->data->nb_rx_queues > dev->data->nb_tx_queues) { 314 tx_queues = hw->fkq_data.tx_queues; 315 queue_id = 0; 316 317 if (tx_queues == NULL || tx_queues[queue_id] == NULL) { 318 hns3_err(hw, "detect tx_queues is NULL!"); 319 return; 320 } 321 txq = (struct hns3_tx_queue *)tx_queues[queue_id]; 322 323 fprintf(file, 324 "\t -- first fake_queue info:\n" 325 "\t Tx: port=%u nb_desc=%u\n", 326 txq->port_id, txq->nb_tx_desc); 327 } 328 } 329 330 static void 331 hns3_get_queue_enable_state(struct hns3_hw *hw, uint32_t *queue_state, 332 uint32_t nb_queues, bool is_rxq) 333 { 334 #define HNS3_QUEUE_NUM_PER_STATS (sizeof(*queue_state) * HNS3_UINT8_BIT) 335 uint32_t queue_en_reg; 336 uint32_t reg_offset; 337 uint32_t state; 338 uint32_t i; 339 340 queue_en_reg = is_rxq ? HNS3_RING_RX_EN_REG : HNS3_RING_TX_EN_REG; 341 for (i = 0; i < nb_queues; i++) { 342 reg_offset = hns3_get_tqp_reg_offset(i); 343 state = hns3_read_dev(hw, reg_offset + HNS3_RING_EN_REG); 344 if (hns3_dev_get_support(hw, INDEP_TXRX)) 345 state = state && hns3_read_dev(hw, reg_offset + 346 queue_en_reg); 347 hns3_set_bit(queue_state[i / HNS3_QUEUE_NUM_PER_STATS], 348 i % HNS3_QUEUE_NUM_PER_STATS, state); 349 } 350 } 351 352 static void 353 hns3_print_queue_state_perline(FILE *file, const uint32_t *queue_state, 354 uint32_t nb_queues, uint32_t line_num) 355 { 356 #define HNS3_NUM_QUEUE_PER_LINE (sizeof(uint32_t) * HNS3_UINT8_BIT) 357 uint32_t id = line_num * HNS3_NUM_QUEUE_PER_LINE; 358 uint32_t i; 359 360 for (i = 0; i < HNS3_NUM_QUEUE_PER_LINE; i++) { 361 fprintf(file, "%1lx", hns3_get_bit(queue_state[line_num], i)); 362 363 if (id % HNS3_UINT8_BIT == HNS3_UINT8_BIT - 1) { 364 fprintf(file, "%s", 365 i == HNS3_NUM_QUEUE_PER_LINE - 1 ? "\n" : ":"); 366 } 367 id++; 368 if (id >= nb_queues) { 369 fprintf(file, "\n"); 370 break; 371 } 372 } 373 } 374 375 static void 376 hns3_display_queue_enable_state(FILE *file, const uint32_t *queue_state, 377 uint32_t nb_queues, bool is_rxq) 378 { 379 #define HNS3_NUM_QUEUE_PER_LINE (sizeof(uint32_t) * HNS3_UINT8_BIT) 380 uint32_t i; 381 382 fprintf(file, "\t %s queue id | enable state bitMap\n", 383 is_rxq ? "Rx" : "Tx"); 384 385 for (i = 0; i < (nb_queues - 1) / HNS3_NUM_QUEUE_PER_LINE + 1; i++) { 386 uint32_t line_end = (i + 1) * HNS3_NUM_QUEUE_PER_LINE - 1; 387 uint32_t line_start = i * HNS3_NUM_QUEUE_PER_LINE; 388 fprintf(file, "\t %04u - %04u | ", line_start, 389 nb_queues - 1 > line_end ? line_end : nb_queues - 1); 390 391 hns3_print_queue_state_perline(file, queue_state, nb_queues, i); 392 } 393 } 394 395 static void 396 hns3_get_rxtx_queue_enable_state(FILE *file, struct rte_eth_dev *dev) 397 { 398 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 399 uint32_t *rx_queue_state; 400 uint32_t *tx_queue_state; 401 uint32_t nb_rx_queues; 402 uint32_t nb_tx_queues; 403 uint32_t bitmap_size; 404 405 nb_rx_queues = dev->data->nb_rx_queues; 406 nb_tx_queues = dev->data->nb_tx_queues; 407 if (nb_rx_queues == 0) { 408 fprintf(file, "\t -- Rx queue number is 0\n"); 409 return; 410 } 411 if (nb_tx_queues == 0) { 412 fprintf(file, "\t -- Tx queue number is 0\n"); 413 return; 414 } 415 416 bitmap_size = (hw->tqps_num * sizeof(uint32_t) + HNS3_UINT32_BIT) / 417 HNS3_UINT32_BIT; 418 rx_queue_state = (uint32_t *)rte_zmalloc(NULL, bitmap_size, 0); 419 if (rx_queue_state == NULL) { 420 hns3_err(hw, "Failed to allocate memory for rx queue state!"); 421 return; 422 } 423 424 tx_queue_state = (uint32_t *)rte_zmalloc(NULL, bitmap_size, 0); 425 if (tx_queue_state == NULL) { 426 hns3_err(hw, "Failed to allocate memory for tx queue state!"); 427 rte_free(rx_queue_state); 428 return; 429 } 430 431 fprintf(file, "\t -- enable state:\n"); 432 hns3_get_queue_enable_state(hw, rx_queue_state, nb_rx_queues, true); 433 hns3_display_queue_enable_state(file, rx_queue_state, nb_rx_queues, 434 true); 435 436 hns3_get_queue_enable_state(hw, tx_queue_state, nb_tx_queues, false); 437 hns3_display_queue_enable_state(file, tx_queue_state, nb_tx_queues, 438 false); 439 rte_free(rx_queue_state); 440 rte_free(tx_queue_state); 441 } 442 443 static void 444 hns3_get_rxtx_queue_head_tail_pointer(FILE *file, struct rte_eth_dev *dev) 445 { 446 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 447 uint32_t reg_offset, queue_id; 448 void **rx_queues, **tx_queues; 449 struct hns3_rx_queue *rxq; 450 struct hns3_tx_queue *txq; 451 uint16_t sw_hold; 452 453 rx_queues = dev->data->rx_queues; 454 if (rx_queues == NULL) 455 return; 456 tx_queues = dev->data->tx_queues; 457 if (tx_queues == NULL) 458 return; 459 460 fprintf(file, "\t -- Rx queue head and tail info:\n"); 461 fprintf(file, "\t qid sw_head sw_hold hw_head hw_tail\n"); 462 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) { 463 if (rx_queues[queue_id] == NULL) 464 continue; 465 rxq = (struct hns3_rx_queue *)rx_queues[queue_id]; 466 if (rxq->rx_deferred_start) 467 continue; 468 469 if (dev->rx_pkt_burst == hns3_recv_pkts_vec || 470 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) 471 sw_hold = rxq->rx_rearm_nb; 472 else 473 sw_hold = rxq->rx_free_hold; 474 475 reg_offset = hns3_get_tqp_reg_offset(queue_id); 476 fprintf(file, "\t %-5u%-9u%-9u%-9u%u\n", queue_id, 477 rxq->next_to_use, sw_hold, 478 hns3_read_dev(hw, HNS3_RING_RX_HEAD_REG + reg_offset), 479 hns3_read_dev(hw, HNS3_RING_RX_TAIL_REG + reg_offset)); 480 } 481 482 fprintf(file, "\t -- Tx queue head and tail info:\n"); 483 fprintf(file, "\t qid sw_head sw_tail hw_head hw_tail\n"); 484 for (queue_id = 0; queue_id < dev->data->nb_tx_queues; queue_id++) { 485 if (tx_queues[queue_id] == NULL) 486 continue; 487 txq = (struct hns3_tx_queue *)tx_queues[queue_id]; 488 if (txq->tx_deferred_start) 489 continue; 490 491 reg_offset = hns3_get_tqp_reg_offset(queue_id); 492 fprintf(file, "\t %-5u%-9u%-9u%-9u%u\n", queue_id, 493 txq->next_to_clean, txq->next_to_use, 494 hns3_read_dev(hw, HNS3_RING_TX_HEAD_REG + reg_offset), 495 hns3_read_dev(hw, HNS3_RING_TX_TAIL_REG + reg_offset)); 496 } 497 } 498 499 static void 500 hns3_get_rxtx_queue_info(FILE *file, struct rte_eth_dev *dev) 501 { 502 struct hns3_rx_queue *rxq; 503 struct hns3_tx_queue *txq; 504 505 rxq = hns3_get_rx_queue(dev); 506 if (rxq == NULL) 507 return; 508 txq = hns3_get_tx_queue(dev); 509 if (txq == NULL) 510 return; 511 fprintf(file, " - Rx/Tx Queue Info:\n"); 512 fprintf(file, 513 "\t -- first queue rxtx info:\n" 514 "\t Rx: port=%u nb_desc=%u free_thresh=%u\n" 515 "\t Tx: port=%u nb_desc=%u\n" 516 "\t -- tx push: %s\n", 517 rxq->port_id, rxq->nb_rx_desc, rxq->rx_free_thresh, 518 txq->port_id, txq->nb_tx_desc, 519 txq->tx_push_enable ? "enabled" : "disabled"); 520 521 hns3_get_rxtx_fake_queue_info(file, dev); 522 hns3_get_rxtx_queue_enable_state(file, dev); 523 hns3_get_rxtx_queue_head_tail_pointer(file, dev); 524 } 525 526 static int 527 hns3_get_vlan_filter_cfg(FILE *file, struct hns3_hw *hw) 528 { 529 #define HNS3_FILTER_TYPE_VF 0 530 #define HNS3_FILTER_TYPE_PORT 1 531 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 532 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 533 struct hns3_vlan_filter_ctrl_cmd *req; 534 struct hns3_cmd_desc desc; 535 uint8_t i; 536 int ret; 537 538 static const uint32_t vlan_filter_type[] = { 539 HNS3_FILTER_TYPE_PORT, 540 HNS3_FILTER_TYPE_VF 541 }; 542 543 for (i = 0; i < RTE_DIM(vlan_filter_type); i++) { 544 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, 545 true); 546 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 547 req->vlan_type = vlan_filter_type[i]; 548 req->vf_id = HNS3_PF_FUNC_ID; 549 ret = hns3_cmd_send(hw, &desc, 1); 550 if (ret != 0) { 551 hns3_err(hw, 552 "NIC IMP exec ret=%d desc_num=%d optcode=0x%x!", 553 ret, 1, rte_le_to_cpu_16(desc.opcode)); 554 return ret; 555 } 556 fprintf(file, 557 "\t -- %s VLAN filter configuration\n" 558 "\t nic_ingress :%s\n" 559 "\t nic_egress :%s\n", 560 req->vlan_type == HNS3_FILTER_TYPE_PORT ? 561 "Port" : "VF", 562 req->vlan_fe & HNS3_FILTER_FE_NIC_INGRESS_B ? 563 "Enable" : "Disable", 564 req->vlan_fe & HNS3_FILTER_FE_NIC_EGRESS_B ? 565 "Enable" : "Disable"); 566 } 567 568 return 0; 569 } 570 571 static int 572 hns3_get_vlan_rx_offload_cfg(FILE *file, struct hns3_hw *hw) 573 { 574 struct hns3_vport_vtag_rx_cfg_cmd *req; 575 struct hns3_cmd_desc desc; 576 uint16_t vport_id; 577 uint8_t bitmap; 578 int ret; 579 580 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, true); 581 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 582 vport_id = HNS3_PF_FUNC_ID; 583 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 584 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 585 req->vf_bitmap[req->vf_offset] = bitmap; 586 587 /* 588 * current version VF is not supported when PF is driven by DPDK driver, 589 * just need to configure rx parameters for PF vport. 590 */ 591 ret = hns3_cmd_send(hw, &desc, 1); 592 if (ret != 0) { 593 hns3_err(hw, 594 "NIC firmware exec ret=%d optcode=0x%x!", ret, 595 rte_le_to_cpu_16(desc.opcode)); 596 return ret; 597 } 598 599 fprintf(file, 600 "\t -- RX VLAN configuration\n" 601 "\t vlan1_strip_en :%s\n" 602 "\t vlan2_strip_en :%s\n" 603 "\t vlan1_vlan_prionly :%s\n" 604 "\t vlan2_vlan_prionly :%s\n" 605 "\t vlan1_strip_discard :%s\n" 606 "\t vlan2_strip_discard :%s\n", 607 hns3_get_bit(req->vport_vlan_cfg, 608 HNS3_REM_TAG1_EN_B) ? "Enable" : "Disable", 609 hns3_get_bit(req->vport_vlan_cfg, 610 HNS3_REM_TAG2_EN_B) ? "Enable" : "Disable", 611 hns3_get_bit(req->vport_vlan_cfg, 612 HNS3_SHOW_TAG1_EN_B) ? "Enable" : "Disable", 613 hns3_get_bit(req->vport_vlan_cfg, 614 HNS3_SHOW_TAG2_EN_B) ? "Enable" : "Disable", 615 hns3_get_bit(req->vport_vlan_cfg, 616 HNS3_DISCARD_TAG1_EN_B) ? "Enable" : "Disable", 617 hns3_get_bit(req->vport_vlan_cfg, 618 HNS3_DISCARD_TAG2_EN_B) ? "Enable" : "Disable"); 619 620 return 0; 621 } 622 623 static void 624 hns3_parse_tx_vlan_cfg(FILE *file, struct hns3_vport_vtag_tx_cfg_cmd *req) 625 { 626 #define VLAN_VID_MASK 0x0fff 627 #define VLAN_PRIO_SHIFT 13 628 629 fprintf(file, 630 "\t -- TX VLAN configuration\n" 631 "\t accept_tag1 :%s\n" 632 "\t accept_untag1 :%s\n" 633 "\t insert_tag1_en :%s\n" 634 "\t default_vlan_tag1 = %d, qos = %d\n" 635 "\t accept_tag2 :%s\n" 636 "\t accept_untag2 :%s\n" 637 "\t insert_tag2_en :%s\n" 638 "\t default_vlan_tag2 = %d, qos = %d\n" 639 "\t vlan_shift_mode :%s\n", 640 hns3_get_bit(req->vport_vlan_cfg, 641 HNS3_ACCEPT_TAG1_B) ? "Enable" : "Disable", 642 hns3_get_bit(req->vport_vlan_cfg, 643 HNS3_ACCEPT_UNTAG1_B) ? "Enable" : "Disable", 644 hns3_get_bit(req->vport_vlan_cfg, 645 HNS3_PORT_INS_TAG1_EN_B) ? "Enable" : "Disable", 646 req->def_vlan_tag1 & VLAN_VID_MASK, 647 req->def_vlan_tag1 >> VLAN_PRIO_SHIFT, 648 hns3_get_bit(req->vport_vlan_cfg, 649 HNS3_ACCEPT_TAG2_B) ? "Enable" : "Disable", 650 hns3_get_bit(req->vport_vlan_cfg, 651 HNS3_ACCEPT_UNTAG2_B) ? "Enable" : "Disable", 652 hns3_get_bit(req->vport_vlan_cfg, 653 HNS3_PORT_INS_TAG2_EN_B) ? "Enable" : "Disable", 654 req->def_vlan_tag2 & VLAN_VID_MASK, 655 req->def_vlan_tag2 >> VLAN_PRIO_SHIFT, 656 hns3_get_bit(req->vport_vlan_cfg, 657 HNS3_TAG_SHIFT_MODE_EN_B) ? "Enable" : 658 "Disable"); 659 } 660 661 static int 662 hns3_get_vlan_tx_offload_cfg(FILE *file, struct hns3_hw *hw) 663 { 664 struct hns3_vport_vtag_tx_cfg_cmd *req; 665 struct hns3_cmd_desc desc; 666 uint16_t vport_id; 667 uint8_t bitmap; 668 int ret; 669 670 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, true); 671 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 672 vport_id = HNS3_PF_FUNC_ID; 673 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 674 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 675 req->vf_bitmap[req->vf_offset] = bitmap; 676 /* 677 * current version VF is not supported when PF is driven by DPDK driver, 678 * just need to configure tx parameters for PF vport. 679 */ 680 ret = hns3_cmd_send(hw, &desc, 1); 681 if (ret != 0) { 682 hns3_err(hw, 683 "NIC firmware exec ret=%d desc_num=%d optcode=0x%x!", 684 ret, 1, rte_le_to_cpu_16(desc.opcode)); 685 return ret; 686 } 687 688 hns3_parse_tx_vlan_cfg(file, req); 689 690 return 0; 691 } 692 693 static void 694 hns3_get_port_pvid_info(FILE *file, struct hns3_hw *hw) 695 { 696 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 697 if (hns->is_vf) 698 return; 699 700 fprintf(file, " - pvid status: %s\n", 701 hw->port_base_vlan_cfg.state ? "On" : "Off"); 702 } 703 704 static void 705 hns3_get_vlan_config_info(FILE *file, struct hns3_hw *hw) 706 { 707 int ret; 708 709 fprintf(file, " - VLAN Config Info:\n"); 710 ret = hns3_get_vlan_filter_cfg(file, hw); 711 if (ret < 0) 712 return; 713 714 ret = hns3_get_vlan_rx_offload_cfg(file, hw); 715 if (ret < 0) 716 return; 717 718 ret = hns3_get_vlan_tx_offload_cfg(file, hw); 719 if (ret < 0) 720 return; 721 } 722 723 static void 724 hns3_get_tm_conf_shaper_info(FILE *file, struct hns3_tm_conf *conf) 725 { 726 struct hns3_shaper_profile_list *shaper_profile_list = 727 &conf->shaper_profile_list; 728 struct hns3_tm_shaper_profile *shaper_profile; 729 730 if (conf->nb_shaper_profile == 0) 731 return; 732 733 fprintf(file, "\t -- shaper_profile:\n"); 734 TAILQ_FOREACH(shaper_profile, shaper_profile_list, node) { 735 fprintf(file, 736 "\t id=%u reference_count=%u peak_rate=%" PRIu64 "Bps\n", 737 shaper_profile->shaper_profile_id, 738 shaper_profile->reference_count, 739 shaper_profile->profile.peak.rate); 740 } 741 } 742 743 static void 744 hns3_get_tm_conf_port_node_info(FILE *file, struct hns3_tm_conf *conf) 745 { 746 if (conf->root == NULL) 747 return; 748 749 fprintf(file, 750 "\t -- port_node:\n" 751 "\t node_id=%u reference_count=%u shaper_profile_id=%d\n", 752 conf->root->id, conf->root->reference_count, 753 conf->root->shaper_profile ? 754 (int)conf->root->shaper_profile->shaper_profile_id : -1); 755 } 756 757 static void 758 hns3_get_tm_conf_tc_node_info(FILE *file, struct hns3_tm_conf *conf) 759 { 760 struct hns3_tm_node_list *tc_list = &conf->tc_list; 761 struct hns3_tm_node *tc_node[HNS3_MAX_TC_NUM]; 762 struct hns3_tm_node *tm_node; 763 uint32_t tidx; 764 765 if (conf->nb_tc_node == 0) 766 return; 767 768 fprintf(file, "\t -- tc_node:\n"); 769 memset(tc_node, 0, sizeof(tc_node)); 770 TAILQ_FOREACH(tm_node, tc_list, node) { 771 tidx = hns3_tm_calc_node_tc_no(conf, tm_node->id); 772 if (tidx < HNS3_MAX_TC_NUM) 773 tc_node[tidx] = tm_node; 774 } 775 776 for (tidx = 0; tidx < HNS3_MAX_TC_NUM; tidx++) { 777 tm_node = tc_node[tidx]; 778 if (tm_node == NULL) 779 continue; 780 fprintf(file, 781 "\t id=%u TC%u reference_count=%u parent_id=%d " 782 "shaper_profile_id=%d\n", 783 tm_node->id, hns3_tm_calc_node_tc_no(conf, tm_node->id), 784 tm_node->reference_count, 785 tm_node->parent ? (int)tm_node->parent->id : -1, 786 tm_node->shaper_profile ? 787 (int)tm_node->shaper_profile->shaper_profile_id : -1); 788 } 789 } 790 791 static void 792 hns3_get_tm_conf_queue_format_info(FILE *file, struct hns3_tm_node **queue_node, 793 uint32_t *queue_node_tc, 794 uint32_t nb_tx_queues) 795 { 796 #define HNS3_PERLINE_QUEUES 32 797 #define HNS3_PERLINE_STRIDE 8 798 uint32_t i, j, line_num, start_queue_id, end_queue_id; 799 800 line_num = (nb_tx_queues + HNS3_PERLINE_QUEUES - 1) / 801 HNS3_PERLINE_QUEUES; 802 for (i = 0; i < line_num; i++) { 803 start_queue_id = i * HNS3_PERLINE_QUEUES; 804 end_queue_id = (i + 1) * HNS3_PERLINE_QUEUES - 1; 805 if (end_queue_id > nb_tx_queues - 1) 806 end_queue_id = nb_tx_queues - 1; 807 fprintf(file, "\t %04u - %04u | ", start_queue_id, 808 end_queue_id); 809 for (j = start_queue_id; j < nb_tx_queues; j++) { 810 if (j >= end_queue_id + 1) 811 break; 812 if (j > start_queue_id && j % HNS3_PERLINE_STRIDE == 0) 813 fprintf(file, ":"); 814 fprintf(file, "%u", 815 queue_node[j] ? queue_node_tc[j] : 816 HNS3_MAX_TC_NUM); 817 } 818 fprintf(file, "\n"); 819 } 820 } 821 822 static void 823 hns3_get_tm_conf_queue_node_info(FILE *file, struct hns3_tm_conf *conf, 824 uint32_t nb_tx_queues) 825 { 826 struct hns3_tm_node_list *queue_list = &conf->queue_list; 827 uint32_t nb_queue_node = conf->nb_leaf_nodes_max + 1; 828 struct hns3_tm_node *queue_node[nb_queue_node]; 829 uint32_t queue_node_tc[nb_queue_node]; 830 struct hns3_tm_node *tm_node; 831 832 if (conf->nb_queue_node == 0) 833 return; 834 835 fprintf(file, 836 "\t -- queue_node:\n" 837 "\t tx queue id | mapped tc (8 mean node not exist)\n"); 838 839 memset(queue_node, 0, sizeof(queue_node)); 840 memset(queue_node_tc, 0, sizeof(queue_node_tc)); 841 nb_tx_queues = RTE_MIN(nb_tx_queues, nb_queue_node); 842 TAILQ_FOREACH(tm_node, queue_list, node) { 843 if (tm_node->id >= nb_queue_node) 844 continue; 845 queue_node[tm_node->id] = tm_node; 846 queue_node_tc[tm_node->id] = tm_node->parent ? 847 hns3_tm_calc_node_tc_no(conf, tm_node->parent->id) : 0; 848 nb_tx_queues = RTE_MAX(nb_tx_queues, tm_node->id + 1); 849 } 850 851 hns3_get_tm_conf_queue_format_info(file, queue_node, queue_node_tc, 852 nb_tx_queues); 853 } 854 855 static void 856 hns3_get_tm_conf_info(FILE *file, struct rte_eth_dev *dev) 857 { 858 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 859 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 860 struct hns3_tm_conf *conf = &pf->tm_conf; 861 862 if (!hns3_dev_get_support(hw, TM)) 863 return; 864 865 fprintf(file, " - TM config info:\n"); 866 fprintf(file, 867 "\t -- nb_leaf_nodes_max=%u nb_nodes_max=%u\n" 868 "\t -- nb_shaper_profile=%u nb_tc_node=%u nb_queue_node=%u\n" 869 "\t -- committed=%u\n", 870 conf->nb_leaf_nodes_max, conf->nb_nodes_max, 871 conf->nb_shaper_profile, conf->nb_tc_node, conf->nb_queue_node, 872 conf->committed); 873 874 hns3_get_tm_conf_shaper_info(file, conf); 875 hns3_get_tm_conf_port_node_info(file, conf); 876 hns3_get_tm_conf_tc_node_info(file, conf); 877 hns3_get_tm_conf_queue_node_info(file, conf, dev->data->nb_tx_queues); 878 } 879 880 static void 881 hns3_fc_mode_to_rxtx_pause(enum hns3_fc_mode fc_mode, bool *rx_pause, 882 bool *tx_pause) 883 { 884 switch (fc_mode) { 885 case HNS3_FC_NONE: 886 *tx_pause = false; 887 *rx_pause = false; 888 break; 889 case HNS3_FC_RX_PAUSE: 890 *rx_pause = true; 891 *tx_pause = false; 892 break; 893 case HNS3_FC_TX_PAUSE: 894 *rx_pause = false; 895 *tx_pause = true; 896 break; 897 case HNS3_FC_FULL: 898 *rx_pause = true; 899 *tx_pause = true; 900 break; 901 default: 902 *rx_pause = false; 903 *tx_pause = false; 904 break; 905 } 906 } 907 908 static bool 909 hns3_is_link_fc_mode(struct hns3_adapter *hns) 910 { 911 struct hns3_hw *hw = &hns->hw; 912 struct hns3_pf *pf = &hns->pf; 913 914 if (hw->current_fc_status == HNS3_FC_STATUS_PFC) 915 return false; 916 917 if (hw->num_tc > 1 && !pf->support_multi_tc_pause) 918 return false; 919 920 return true; 921 } 922 923 static void 924 hns3_get_link_fc_info(FILE *file, struct rte_eth_dev *dev) 925 { 926 struct hns3_adapter *hns = dev->data->dev_private; 927 struct hns3_hw *hw = &hns->hw; 928 struct rte_eth_fc_conf cur_fc_conf; 929 bool rx_pause1; 930 bool tx_pause1; 931 bool rx_pause2; 932 bool tx_pause2; 933 int ret; 934 935 if (!hns3_is_link_fc_mode(hns)) 936 return; 937 938 ret = hns3_flow_ctrl_get(dev, &cur_fc_conf); 939 if (ret) { 940 fprintf(file, "get device flow control info fail!\n"); 941 return; 942 } 943 944 hns3_fc_mode_to_rxtx_pause(hw->requested_fc_mode, 945 &rx_pause1, &tx_pause1); 946 hns3_fc_mode_to_rxtx_pause((enum hns3_fc_mode)cur_fc_conf.mode, 947 &rx_pause2, &tx_pause2); 948 949 fprintf(file, 950 "\t -- link_fc_info:\n" 951 "\t Requested fc:\n" 952 "\t Rx: %s\n" 953 "\t Tx: %s\n" 954 "\t Current fc:\n" 955 "\t Rx: %s\n" 956 "\t Tx: %s\n" 957 "\t Autonegotiate: %s\n" 958 "\t Pause time: 0x%x\n", 959 rx_pause1 ? "On" : "Off", tx_pause1 ? "On" : "Off", 960 rx_pause2 ? "On" : "Off", tx_pause2 ? "On" : "Off", 961 cur_fc_conf.autoneg == RTE_ETH_LINK_AUTONEG ? "On" : "Off", 962 cur_fc_conf.pause_time); 963 } 964 965 static void 966 hns3_get_flow_ctrl_info(FILE *file, struct rte_eth_dev *dev) 967 { 968 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 969 970 fprintf(file, " - Flow Ctrl Info:\n"); 971 fprintf(file, 972 "\t -- fc_common_info:\n" 973 "\t current_fc_status=%u\n" 974 "\t requested_fc_mode=%u\n", 975 hw->current_fc_status, 976 hw->requested_fc_mode); 977 978 hns3_get_link_fc_info(file, dev); 979 } 980 981 int 982 hns3_eth_dev_priv_dump(struct rte_eth_dev *dev, FILE *file) 983 { 984 struct hns3_adapter *hns = dev->data->dev_private; 985 struct hns3_hw *hw = &hns->hw; 986 987 rte_spinlock_lock(&hw->lock); 988 989 hns3_get_device_basic_info(file, dev); 990 hns3_get_dev_feature_capability(file, hw); 991 hns3_get_rxtx_queue_info(file, dev); 992 hns3_get_port_pvid_info(file, hw); 993 994 /* 995 * VF only supports dumping basic info, feature capability and queue 996 * info. 997 */ 998 if (hns->is_vf) { 999 rte_spinlock_unlock(&hw->lock); 1000 return 0; 1001 } 1002 1003 hns3_get_dev_mac_info(file, hns); 1004 hns3_get_vlan_config_info(file, hw); 1005 hns3_get_fdir_basic_info(file, &hns->pf); 1006 hns3_get_tm_conf_info(file, dev); 1007 hns3_get_flow_ctrl_info(file, dev); 1008 1009 rte_spinlock_unlock(&hw->lock); 1010 1011 return 0; 1012 } 1013 1014 int 1015 hns3_rx_descriptor_dump(const struct rte_eth_dev *dev, uint16_t queue_id, 1016 uint16_t offset, uint16_t num, FILE *file) 1017 { 1018 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1019 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id]; 1020 uint32_t *bd_data; 1021 uint16_t count = 0; 1022 uint16_t desc_id; 1023 int i; 1024 1025 if (offset >= rxq->nb_rx_desc) 1026 return -EINVAL; 1027 1028 if (num > rxq->nb_rx_desc) { 1029 hns3_err(hw, "Invalid BD num=%u", num); 1030 return -EINVAL; 1031 } 1032 1033 while (count < num) { 1034 desc_id = (rxq->next_to_use + offset + count) % rxq->nb_rx_desc; 1035 bd_data = (uint32_t *)(&rxq->rx_ring[desc_id]); 1036 fprintf(file, "Rx queue id:%u BD id:%u\n", queue_id, desc_id); 1037 for (i = 0; i < HNS3_BD_DW_NUM; i++) { 1038 /* 1039 * For the sake of security, first 8 bytes of BD which 1040 * stands for physical address of packet should not be 1041 * shown. 1042 */ 1043 if (i < HNS3_BD_ADDRESS_LAST_DW) { 1044 fprintf(file, "RX BD WORD[%d]:0x%08x\n", i, 0); 1045 continue; 1046 } 1047 fprintf(file, "RX BD WORD[%d]:0x%08x\n", i, 1048 *(bd_data + i)); 1049 } 1050 count++; 1051 } 1052 1053 return 0; 1054 } 1055 1056 int 1057 hns3_tx_descriptor_dump(const struct rte_eth_dev *dev, uint16_t queue_id, 1058 uint16_t offset, uint16_t num, FILE *file) 1059 { 1060 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1061 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id]; 1062 uint32_t *bd_data; 1063 uint16_t count = 0; 1064 uint16_t desc_id; 1065 int i; 1066 1067 if (offset >= txq->nb_tx_desc) 1068 return -EINVAL; 1069 1070 if (num > txq->nb_tx_desc) { 1071 hns3_err(hw, "Invalid BD num=%u", num); 1072 return -EINVAL; 1073 } 1074 1075 while (count < num) { 1076 desc_id = (txq->next_to_use + offset + count) % txq->nb_tx_desc; 1077 bd_data = (uint32_t *)(&txq->tx_ring[desc_id]); 1078 fprintf(file, "Tx queue id:%u BD id:%u\n", queue_id, desc_id); 1079 for (i = 0; i < HNS3_BD_DW_NUM; i++) { 1080 /* 1081 * For the sake of security, first 8 bytes of BD which 1082 * stands for physical address of packet should not be 1083 * shown. 1084 */ 1085 if (i < HNS3_BD_ADDRESS_LAST_DW) { 1086 fprintf(file, "TX BD WORD[%d]:0x%08x\n", i, 0); 1087 continue; 1088 } 1089 1090 fprintf(file, "Tx BD WORD[%d]:0x%08x\n", i, 1091 *(bd_data + i)); 1092 } 1093 count++; 1094 } 1095 1096 return 0; 1097 } 1098