1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
3 */
4
5 #ifndef _HINIC_PMD_HWIF_H_
6 #define _HINIC_PMD_HWIF_H_
7
8 #define HINIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT 30000
9
10 #define HINIC_HWIF_NUM_AEQS(hwif) ((hwif)->attr.num_aeqs)
11 #define HINIC_HWIF_NUM_CEQS(hwif) ((hwif)->attr.num_ceqs)
12 #define HINIC_HWIF_NUM_IRQS(hwif) ((hwif)->attr.num_irqs)
13 #define HINIC_HWIF_GLOBAL_IDX(hwif) ((hwif)->attr.func_global_idx)
14 #define HINIC_HWIF_GLOBAL_VF_OFFSET(hwif) ((hwif)->attr.global_vf_id_of_pf)
15 #define HINIC_HWIF_PPF_IDX(hwif) ((hwif)->attr.ppf_idx)
16 #define HINIC_PCI_INTF_IDX(hwif) ((hwif)->attr.pci_intf_idx)
17
18 #define HINIC_FUNC_TYPE(dev) ((dev)->hwif->attr.func_type)
19 #define HINIC_IS_PF(dev) (HINIC_FUNC_TYPE(dev) == TYPE_PF)
20 #define HINIC_IS_VF(dev) (HINIC_FUNC_TYPE(dev) == TYPE_VF)
21 #define HINIC_IS_PPF(dev) (HINIC_FUNC_TYPE(dev) == TYPE_PPF)
22
23 enum func_type {
24 TYPE_PF,
25 TYPE_VF,
26 TYPE_PPF,
27 };
28
29 enum hinic_msix_state {
30 HINIC_MSIX_ENABLE,
31 HINIC_MSIX_DISABLE,
32 };
33
34 /* Defines the IRQ information structure */
35 struct irq_info {
36 u16 msix_entry_idx; /* IRQ corresponding index number */
37 u32 irq_id; /* the IRQ number from OS */
38 };
39
40 struct hinic_free_db_area {
41 u32 db_idx[HINIC_DB_MAX_AREAS];
42
43 u32 num_free;
44
45 u32 alloc_pos;
46 u32 return_pos;
47 /* spinlock for idx */
48 spinlock_t idx_lock;
49 };
50
51 struct hinic_func_attr {
52 u16 func_global_idx;
53 u8 port_to_port_idx;
54 u8 pci_intf_idx;
55 u8 vf_in_pf;
56 enum func_type func_type;
57
58 u8 mpf_idx;
59
60 u8 ppf_idx;
61
62 u16 num_irqs; /* max: 2 ^ 15 */
63 u8 num_aeqs; /* max: 2 ^ 3 */
64 u8 num_ceqs; /* max: 2 ^ 7 */
65
66 u8 num_dma_attr; /* max: 2 ^ 6 */
67
68 u16 global_vf_id_of_pf;
69 };
70
71 struct hinic_hwif {
72 u8 __iomem *cfg_regs_base;
73 u8 __iomem *intr_regs_base;
74 u64 db_base_phy;
75 u8 __iomem *db_base;
76 u64 db_max_areas;
77 struct hinic_free_db_area free_db_area;
78 struct hinic_func_attr attr;
79 };
80
hinic_hwif_read_reg(struct hinic_hwif * hwif,u32 reg)81 static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)
82 {
83 return be32_to_cpu(readl(hwif->cfg_regs_base + reg));
84 }
85
86 static inline void
hinic_hwif_write_reg(struct hinic_hwif * hwif,u32 reg,u32 val)87 hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg, u32 val)
88 {
89 writel(cpu_to_be32(val), hwif->cfg_regs_base + reg);
90 }
91
92 u16 hinic_global_func_id(void *hwdev); /* func_attr.glb_func_idx */
93
94 enum func_type hinic_func_type(void *hwdev);
95
96 void hinic_set_pf_status(struct hinic_hwif *hwif, enum hinic_pf_status status);
97
98 enum hinic_pf_status hinic_get_pf_status(struct hinic_hwif *hwif);
99
100 void hinic_enable_doorbell(struct hinic_hwif *hwif);
101
102 void hinic_disable_doorbell(struct hinic_hwif *hwif);
103
104 int hinic_alloc_db_addr(void *hwdev, void __iomem **db_base);
105
106 void hinic_free_db_addr(void *hwdev, void __iomem *db_base);
107
108 int wait_until_doorbell_flush_states(struct hinic_hwif *hwif,
109 enum hinic_doorbell_ctrl states);
110
111 void hinic_set_msix_state(void *hwdev, u16 msix_idx,
112 enum hinic_msix_state flag);
113
114 void hinic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx,
115 u8 clear_resend_en);
116
117 u8 hinic_ppf_idx(void *hwdev);
118
119 int hinic_hwif_res_init(struct hinic_hwdev *hwdev);
120
121 void hinic_hwif_res_free(struct hinic_hwdev *hwdev);
122
123 u8 hinic_dma_attr_entry_num(void *hwdev);
124
125 #endif /* _HINIC_PMD_HWIF_H_ */
126