1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Huawei Technologies Co., Ltd 3 */ 4 5 #ifndef _HINIC_PORT_CMD_H_ 6 #define _HINIC_PORT_CMD_H_ 7 8 enum hinic_eq_type { 9 HINIC_AEQ, 10 HINIC_CEQ 11 }; 12 13 enum hinic_resp_aeq_num { 14 HINIC_AEQ0 = 0, 15 HINIC_AEQ1 = 1, 16 HINIC_AEQ2 = 2, 17 HINIC_AEQ3 = 3, 18 }; 19 20 enum hinic_mod_type { 21 HINIC_MOD_COMM = 0, /* HW communication module */ 22 HINIC_MOD_L2NIC = 1, /* L2NIC module */ 23 HINIC_MOD_CFGM = 7, /* Configuration module */ 24 HINIC_MOD_HILINK = 14, 25 HINIC_MOD_MAX = 15 26 }; 27 28 /* cmd of mgmt CPU message for NIC module */ 29 enum hinic_port_cmd { 30 HINIC_PORT_CMD_MGMT_RESET = 0x0, 31 32 HINIC_PORT_CMD_CHANGE_MTU = 0x2, 33 34 HINIC_PORT_CMD_ADD_VLAN = 0x3, 35 HINIC_PORT_CMD_DEL_VLAN, 36 37 HINIC_PORT_CMD_SET_ETS = 0x7, 38 HINIC_PORT_CMD_GET_ETS, 39 40 HINIC_PORT_CMD_SET_MAC = 0x9, 41 HINIC_PORT_CMD_GET_MAC, 42 HINIC_PORT_CMD_DEL_MAC, 43 44 HINIC_PORT_CMD_SET_RX_MODE = 0xc, 45 HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE = 0xd, 46 47 HINIC_PORT_CMD_GET_PAUSE_INFO = 0x14, 48 HINIC_PORT_CMD_SET_PAUSE_INFO, 49 50 HINIC_PORT_CMD_GET_LINK_STATE = 0x18, 51 HINIC_PORT_CMD_SET_LRO = 0x19, 52 HINIC_PORT_CMD_SET_RX_CSUM = 0x1a, 53 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 0x1b, 54 55 HINIC_PORT_CMD_GET_PORT_STATISTICS = 0x1c, 56 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS, 57 HINIC_PORT_CMD_GET_VPORT_STAT, 58 HINIC_PORT_CMD_CLEAN_VPORT_STAT, 59 60 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25, 61 HINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL, 62 63 HINIC_PORT_CMD_SET_PORT_ENABLE = 0x29, 64 HINIC_PORT_CMD_GET_PORT_ENABLE, 65 66 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 0x2b, 67 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL, 68 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE, 69 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE, 70 HINIC_PORT_CMD_GET_RSS_CTX_TBL, 71 HINIC_PORT_CMD_SET_RSS_CTX_TBL, 72 HINIC_PORT_CMD_RSS_TEMP_MGR, 73 74 HINIC_PORT_CMD_RSS_CFG = 0x42, 75 76 HINIC_PORT_CMD_GET_PHY_TYPE = 0x44, 77 HINIC_PORT_CMD_INIT_FUNC = 0x45, 78 79 HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE = 0x4a, 80 HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE, 81 82 HINIC_PORT_CMD_GET_PORT_TYPE = 0x5b, 83 84 HINIC_PORT_CMD_GET_VPORT_ENABLE = 0x5c, 85 HINIC_PORT_CMD_SET_VPORT_ENABLE, 86 87 HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID = 0x5e, 88 89 HINIC_PORT_CMD_GET_LRO = 0x63, 90 91 HINIC_PORT_CMD_GET_DMA_CS = 0x64, 92 HINIC_PORT_CMD_SET_DMA_CS, 93 94 HINIC_PORT_CMD_GET_GLOBAL_QPN = 0x66, 95 96 HINIC_PORT_CMD_SET_PFC_MISC = 0x67, 97 HINIC_PORT_CMD_GET_PFC_MISC, 98 99 HINIC_PORT_CMD_SET_VF_RATE = 0x69, 100 HINIC_PORT_CMD_SET_VF_VLAN, 101 HINIC_PORT_CMD_CLR_VF_VLAN, 102 103 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 0x73, 104 HINIC_PORT_CMD_SET_PFC_THD = 0x75, 105 106 HINIC_PORT_CMD_LINK_STATUS_REPORT = 0xa0, 107 108 HINIC_PORT_CMD_SET_LOSSLESS_ETH = 0xa3, 109 HINIC_PORT_CMD_UPDATE_MAC = 0xa4, 110 111 HINIC_PORT_CMD_GET_PORT_INFO = 0xaa, 112 113 HINIC_PORT_CMD_SET_IPSU_MAC = 0xcb, 114 HINIC_PORT_CMD_GET_IPSU_MAC = 0xcc, 115 116 HINIC_PORT_CMD_GET_LINK_MODE = 0xD9, 117 HINIC_PORT_CMD_SET_SPEED = 0xDA, 118 HINIC_PORT_CMD_SET_AUTONEG = 0xDB, 119 120 HINIC_PORT_CMD_CLEAR_QP_RES = 0xDD, 121 HINIC_PORT_CMD_SET_SUPER_CQE = 0xDE, 122 HINIC_PORT_CMD_SET_VF_COS = 0xDF, 123 HINIC_PORT_CMD_GET_VF_COS = 0xE1, 124 125 HINIC_PORT_CMD_CABLE_PLUG_EVENT = 0xE5, 126 HINIC_PORT_CMD_LINK_ERR_EVENT = 0xE6, 127 128 HINIC_PORT_CMD_SET_COS_UP_MAP = 0xE8, 129 130 HINIC_PORT_CMD_RESET_LINK_CFG = 0xEB, 131 132 HINIC_PORT_CMD_FORCE_PKT_DROP = 0xF3, 133 HINIC_PORT_CMD_SET_LRO_TIMER = 0xF4, 134 135 HINIC_PORT_CMD_SET_VHD_CFG = 0xF7, 136 HINIC_PORT_CMD_SET_LINK_FOLLOW = 0xF8, 137 }; 138 139 /* cmd of mgmt CPU message for HW module */ 140 enum hinic_mgmt_cmd { 141 HINIC_MGMT_CMD_RESET_MGMT = 0x0, 142 HINIC_MGMT_CMD_START_FLR = 0x1, 143 HINIC_MGMT_CMD_FLUSH_DOORBELL = 0x2, 144 HINIC_MGMT_CMD_GET_IO_STATUS = 0x3, 145 HINIC_MGMT_CMD_DMA_ATTR_SET = 0x4, 146 147 HINIC_MGMT_CMD_CMDQ_CTXT_SET = 0x10, 148 HINIC_MGMT_CMD_CMDQ_CTXT_GET, 149 150 HINIC_MGMT_CMD_VAT_SET = 0x12, 151 HINIC_MGMT_CMD_VAT_GET, 152 153 HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET = 0x14, 154 HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET, 155 156 HINIC_MGMT_CMD_PPF_HT_GPA_SET = 0x23, 157 HINIC_MGMT_CMD_RES_STATE_SET = 0x24, 158 HINIC_MGMT_CMD_FUNC_CACHE_OUT = 0x25, 159 HINIC_MGMT_CMD_FFM_SET = 0x26, 160 161 HINIC_MGMT_CMD_FUNC_RES_CLEAR = 0x29, 162 163 HINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP = 0x33, 164 HINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP, 165 HINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP, 166 167 HINIC_MGMT_CMD_VF_RANDOM_ID_SET = 0x36, 168 HINIC_MGMT_CMD_FAULT_REPORT = 0x37, 169 170 HINIC_MGMT_CMD_VPD_SET = 0x40, 171 HINIC_MGMT_CMD_VPD_GET, 172 HINIC_MGMT_CMD_LABEL_SET, 173 HINIC_MGMT_CMD_LABEL_GET, 174 HINIC_MGMT_CMD_SATIC_MAC_SET, 175 HINIC_MGMT_CMD_SATIC_MAC_GET, 176 HINIC_MGMT_CMD_SYNC_TIME = 0x46, 177 HINIC_MGMT_CMD_SET_LED_STATUS = 0x4A, 178 HINIC_MGMT_CMD_L2NIC_RESET = 0x4b, 179 HINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET = 0x4d, 180 HINIC_MGMT_CMD_BIOS_NV_DATA_MGMT = 0x4E, 181 HINIC_MGMT_CMD_ACTIVATE_FW = 0x4F, 182 HINIC_MGMT_CMD_PAGESIZE_SET = 0x50, 183 HINIC_MGMT_CMD_PAGESIZE_GET = 0x51, 184 HINIC_MGMT_CMD_GET_BOARD_INFO = 0x52, 185 HINIC_MGMT_CMD_WATCHDOG_INFO = 0x56, 186 HINIC_MGMT_CMD_FMW_ACT_NTC = 0x57, 187 HINIC_MGMT_CMD_SET_VF_RANDOM_ID = 0x61, 188 HINIC_MGMT_CMD_GET_PPF_STATE = 0x63, 189 HINIC_MGMT_CMD_PCIE_DFX_NTC = 0x65, 190 HINIC_MGMT_CMD_PCIE_DFX_GET = 0x66, 191 }; 192 193 /* cmd of mgmt CPU message for HILINK module */ 194 enum hinic_hilink_cmd { 195 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3, 196 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8, 197 }; 198 199 /* uCode related commands */ 200 enum hinic_ucode_cmd { 201 HINIC_UCODE_CMD_MDY_QUEUE_CONTEXT = 0, 202 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, 203 HINIC_UCODE_CMD_ARM_SQ, 204 HINIC_UCODE_CMD_ARM_RQ, 205 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, 206 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, 207 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, 208 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, 209 HINIC_UCODE_CMD_SET_IQ_ENABLE, 210 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 211 }; 212 213 enum cfg_sub_cmd { 214 /* PPF(PF) <-> FW */ 215 HINIC_CFG_NIC_CAP = 0, 216 CFG_FW_VERSION, 217 CFG_UCODE_VERSION, 218 HINIC_CFG_MBOX_CAP = 6 219 }; 220 221 enum hinic_ack_type { 222 HINIC_ACK_TYPE_CMDQ, 223 HINIC_ACK_TYPE_SHARE_CQN, 224 HINIC_ACK_TYPE_APP_CQN, 225 226 HINIC_MOD_ACK_MAX = 15, 227 }; 228 229 enum sq_l4offload_type { 230 OFFLOAD_DISABLE = 0, 231 TCP_OFFLOAD_ENABLE = 1, 232 SCTP_OFFLOAD_ENABLE = 2, 233 UDP_OFFLOAD_ENABLE = 3, 234 }; 235 236 enum sq_vlan_offload_flag { 237 VLAN_OFFLOAD_DISABLE = 0, 238 VLAN_OFFLOAD_ENABLE = 1, 239 }; 240 241 enum sq_pkt_parsed_flag { 242 PKT_NOT_PARSED = 0, 243 PKT_PARSED = 1, 244 }; 245 246 enum sq_l3_type { 247 UNKNOWN_L3TYPE = 0, 248 IPV6_PKT = 1, 249 IPV4_PKT_NO_CHKSUM_OFFLOAD = 2, 250 IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3, 251 }; 252 253 enum sq_md_type { 254 UNKNOWN_MD_TYPE = 0, 255 }; 256 257 enum sq_l2type { 258 ETHERNET = 0, 259 }; 260 261 enum sq_tunnel_l4_type { 262 NOT_TUNNEL, 263 TUNNEL_UDP_NO_CSUM, 264 TUNNEL_UDP_CSUM, 265 }; 266 267 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 268 #define NIC_RSS_CMD_TEMP_FREE 0x02 269 270 #define HINIC_RSS_TYPE_VALID_SHIFT 23 271 #define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT 24 272 #define HINIC_RSS_TYPE_IPV6_EXT_SHIFT 25 273 #define HINIC_RSS_TYPE_TCP_IPV6_SHIFT 26 274 #define HINIC_RSS_TYPE_IPV6_SHIFT 27 275 #define HINIC_RSS_TYPE_TCP_IPV4_SHIFT 28 276 #define HINIC_RSS_TYPE_IPV4_SHIFT 29 277 #define HINIC_RSS_TYPE_UDP_IPV6_SHIFT 30 278 #define HINIC_RSS_TYPE_UDP_IPV4_SHIFT 31 279 280 #define HINIC_RSS_TYPE_SET(val, member) \ 281 (((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT) 282 283 #define HINIC_RSS_TYPE_GET(val, member) \ 284 (((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1) 285 286 enum hinic_speed { 287 HINIC_SPEED_10MB_LINK = 0, 288 HINIC_SPEED_100MB_LINK, 289 HINIC_SPEED_1000MB_LINK, 290 HINIC_SPEED_10GB_LINK, 291 HINIC_SPEED_25GB_LINK, 292 HINIC_SPEED_40GB_LINK, 293 HINIC_SPEED_100GB_LINK, 294 HINIC_SPEED_UNKNOWN = 0xFF, 295 }; 296 297 enum { 298 HINIC_IFLA_VF_LINK_STATE_AUTO, /* link state of the uplink */ 299 HINIC_IFLA_VF_LINK_STATE_ENABLE, /* link always up */ 300 HINIC_IFLA_VF_LINK_STATE_DISABLE, /* link always down */ 301 }; 302 303 #define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT 0 304 #define HINIC_AF0_P2P_IDX_SHIFT 10 305 #define HINIC_AF0_PCI_INTF_IDX_SHIFT 14 306 #define HINIC_AF0_VF_IN_PF_SHIFT 16 307 #define HINIC_AF0_FUNC_TYPE_SHIFT 24 308 309 #define HINIC_AF0_FUNC_GLOBAL_IDX_MASK 0x3FF 310 #define HINIC_AF0_P2P_IDX_MASK 0xF 311 #define HINIC_AF0_PCI_INTF_IDX_MASK 0x3 312 #define HINIC_AF0_VF_IN_PF_MASK 0xFF 313 #define HINIC_AF0_FUNC_TYPE_MASK 0x1 314 315 #define HINIC_AF0_GET(val, member) \ 316 (((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK) 317 318 #define HINIC_AF1_PPF_IDX_SHIFT 0 319 #define HINIC_AF1_AEQS_PER_FUNC_SHIFT 8 320 #define HINIC_AF1_CEQS_PER_FUNC_SHIFT 12 321 #define HINIC_AF1_IRQS_PER_FUNC_SHIFT 20 322 #define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT 24 323 #define HINIC_AF1_MGMT_INIT_STATUS_SHIFT 30 324 #define HINIC_AF1_PF_INIT_STATUS_SHIFT 31 325 326 #define HINIC_AF1_PPF_IDX_MASK 0x1F 327 #define HINIC_AF1_AEQS_PER_FUNC_MASK 0x3 328 #define HINIC_AF1_CEQS_PER_FUNC_MASK 0x7 329 #define HINIC_AF1_IRQS_PER_FUNC_MASK 0xF 330 #define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK 0x7 331 #define HINIC_AF1_MGMT_INIT_STATUS_MASK 0x1 332 #define HINIC_AF1_PF_INIT_STATUS_MASK 0x1 333 334 #define HINIC_AF1_GET(val, member) \ 335 (((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK) 336 337 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT 16 338 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK 0x3FF 339 340 #define HINIC_AF2_GET(val, member) \ 341 (((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK) 342 343 #define HINIC_AF4_OUTBOUND_CTRL_SHIFT 0 344 #define HINIC_AF4_DOORBELL_CTRL_SHIFT 1 345 #define HINIC_AF4_OUTBOUND_CTRL_MASK 0x1 346 #define HINIC_AF4_DOORBELL_CTRL_MASK 0x1 347 348 #define HINIC_AF4_GET(val, member) \ 349 (((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK) 350 351 #define HINIC_AF4_SET(val, member) \ 352 (((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT) 353 354 #define HINIC_AF4_CLEAR(val, member) \ 355 ((val) & (~(HINIC_AF4_##member##_MASK << \ 356 HINIC_AF4_##member##_SHIFT))) 357 358 #define HINIC_AF5_PF_STATUS_SHIFT 0 359 #define HINIC_AF5_PF_STATUS_MASK 0xFFFF 360 361 #define HINIC_AF5_SET(val, member) \ 362 (((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT) 363 364 #define HINIC_AF5_GET(val, member) \ 365 (((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK) 366 367 #define HINIC_AF5_CLEAR(val, member) \ 368 ((val) & (~(HINIC_AF5_##member##_MASK << \ 369 HINIC_AF5_##member##_SHIFT))) 370 371 #define HINIC_PPF_ELECTION_IDX_SHIFT 0 372 373 #define HINIC_PPF_ELECTION_IDX_MASK 0x1F 374 375 #define HINIC_PPF_ELECTION_SET(val, member) \ 376 (((val) & HINIC_PPF_ELECTION_##member##_MASK) << \ 377 HINIC_PPF_ELECTION_##member##_SHIFT) 378 379 #define HINIC_PPF_ELECTION_GET(val, member) \ 380 (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \ 381 HINIC_PPF_ELECTION_##member##_MASK) 382 383 #define HINIC_PPF_ELECTION_CLEAR(val, member) \ 384 ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \ 385 << HINIC_PPF_ELECTION_##member##_SHIFT))) 386 387 #define DB_IDX(db, db_base) \ 388 ((u32)(((unsigned long)(db) - (unsigned long)(db_base)) / \ 389 HINIC_DB_PAGE_SIZE)) 390 391 enum hinic_pcie_nosnoop { 392 HINIC_PCIE_SNOOP = 0, 393 HINIC_PCIE_NO_SNOOP = 1, 394 }; 395 396 enum hinic_pcie_tph { 397 HINIC_PCIE_TPH_DISABLE = 0, 398 HINIC_PCIE_TPH_ENABLE = 1, 399 }; 400 401 enum hinic_outbound_ctrl { 402 ENABLE_OUTBOUND = 0x0, 403 DISABLE_OUTBOUND = 0x1, 404 }; 405 406 enum hinic_doorbell_ctrl { 407 ENABLE_DOORBELL = 0x0, 408 DISABLE_DOORBELL = 0x1, 409 }; 410 411 enum hinic_pf_status { 412 HINIC_PF_STATUS_INIT = 0X0, 413 HINIC_PF_STATUS_ACTIVE_FLAG = 0x11, 414 HINIC_PF_STATUS_FLR_START_FLAG = 0x12, 415 HINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13, 416 }; 417 418 /* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */ 419 #define HINIC_DB_DWQE_SIZE 0x00080000 420 421 /* db/dwqe page size: 4K */ 422 #define HINIC_DB_PAGE_SIZE 0x00001000ULL 423 424 #define HINIC_DB_MAX_AREAS (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE) 425 426 #define HINIC_PCI_MSIX_ENTRY_SIZE 16 427 #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12 428 #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1 429 430 struct hinic_mgmt_msg_head { 431 u8 status; 432 u8 version; 433 u8 resp_aeq_num; 434 u8 rsvd0[5]; 435 }; 436 437 struct hinic_root_ctxt { 438 struct hinic_mgmt_msg_head mgmt_msg_head; 439 440 u16 func_idx; 441 u16 rsvd1; 442 u8 set_cmdq_depth; 443 u8 cmdq_depth; 444 u8 lro_en; 445 u8 rsvd2; 446 u8 ppf_idx; 447 u8 rsvd3; 448 u16 rq_depth; 449 u16 rx_buf_sz; 450 u16 sq_depth; 451 }; 452 453 #endif /* _HINIC_PORT_CMD_H_ */ 454