1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Huawei Technologies Co., Ltd 3 */ 4 5 #ifndef _HINIC_PORT_CMD_H_ 6 #define _HINIC_PORT_CMD_H_ 7 8 #define HINIC_AEQ 0 9 10 enum hinic_resp_aeq_num { 11 HINIC_AEQ0 = 0, 12 HINIC_AEQ1 = 1, 13 HINIC_AEQ2 = 2, 14 HINIC_AEQ3 = 3, 15 }; 16 17 enum hinic_mod_type { 18 HINIC_MOD_COMM = 0, /* HW communication module */ 19 HINIC_MOD_L2NIC = 1, /* L2NIC module */ 20 HINIC_MOD_CFGM = 7, /* Configuration module */ 21 HINIC_MOD_HILINK = 14, 22 HINIC_MOD_MAX = 15 23 }; 24 25 /* only used by VFD communicating with PFD to register or unregister, 26 * command mode type is HINIC_MOD_L2NIC 27 */ 28 #define HINIC_PORT_CMD_VF_REGISTER 0x0 29 #define HINIC_PORT_CMD_VF_UNREGISTER 0x1 30 31 /* cmd of mgmt CPU message for NIC module */ 32 enum hinic_port_cmd { 33 HINIC_PORT_CMD_MGMT_RESET = 0x0, 34 35 HINIC_PORT_CMD_CHANGE_MTU = 0x2, 36 37 HINIC_PORT_CMD_ADD_VLAN = 0x3, 38 HINIC_PORT_CMD_DEL_VLAN, 39 40 HINIC_PORT_CMD_SET_ETS = 0x7, 41 HINIC_PORT_CMD_GET_ETS, 42 43 HINIC_PORT_CMD_SET_MAC = 0x9, 44 HINIC_PORT_CMD_GET_MAC, 45 HINIC_PORT_CMD_DEL_MAC, 46 47 HINIC_PORT_CMD_SET_RX_MODE = 0xc, 48 HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE = 0xd, 49 50 HINIC_PORT_CMD_GET_PAUSE_INFO = 0x14, 51 HINIC_PORT_CMD_SET_PAUSE_INFO, 52 53 HINIC_PORT_CMD_GET_LINK_STATE = 0x18, 54 HINIC_PORT_CMD_SET_LRO = 0x19, 55 HINIC_PORT_CMD_SET_RX_CSUM = 0x1a, 56 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 0x1b, 57 58 HINIC_PORT_CMD_GET_PORT_STATISTICS = 0x1c, 59 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS, 60 HINIC_PORT_CMD_GET_VPORT_STAT, 61 HINIC_PORT_CMD_CLEAN_VPORT_STAT, 62 63 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25, 64 HINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL, 65 66 HINIC_PORT_CMD_SET_PORT_ENABLE = 0x29, 67 HINIC_PORT_CMD_GET_PORT_ENABLE, 68 69 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 0x2b, 70 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL, 71 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE, 72 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE, 73 HINIC_PORT_CMD_GET_RSS_CTX_TBL, 74 HINIC_PORT_CMD_SET_RSS_CTX_TBL, 75 HINIC_PORT_CMD_RSS_TEMP_MGR, 76 77 HINIC_PORT_CMD_RSS_CFG = 0x42, 78 79 HINIC_PORT_CMD_GET_PHY_TYPE = 0x44, 80 HINIC_PORT_CMD_INIT_FUNC = 0x45, 81 82 HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE = 0x4a, 83 HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE, 84 85 HINIC_PORT_CMD_GET_MGMT_VERSION = 0x58, 86 87 HINIC_PORT_CMD_GET_PORT_TYPE = 0x5b, 88 89 HINIC_PORT_CMD_GET_VPORT_ENABLE = 0x5c, 90 HINIC_PORT_CMD_SET_VPORT_ENABLE, 91 92 HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID = 0x5e, 93 94 HINIC_PORT_CMD_GET_LRO = 0x63, 95 96 HINIC_PORT_CMD_GET_DMA_CS = 0x64, 97 HINIC_PORT_CMD_SET_DMA_CS, 98 99 HINIC_PORT_CMD_GET_GLOBAL_QPN = 0x66, 100 101 HINIC_PORT_CMD_SET_PFC_MISC = 0x67, 102 HINIC_PORT_CMD_GET_PFC_MISC, 103 104 HINIC_PORT_CMD_SET_VF_RATE = 0x69, 105 HINIC_PORT_CMD_SET_VF_VLAN, 106 HINIC_PORT_CMD_CLR_VF_VLAN, 107 108 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 0x73, 109 HINIC_PORT_CMD_SET_PFC_THD = 0x75, 110 111 HINIC_PORT_CMD_LINK_STATUS_REPORT = 0xa0, 112 113 HINIC_PORT_CMD_SET_LOSSLESS_ETH = 0xa3, 114 HINIC_PORT_CMD_UPDATE_MAC = 0xa4, 115 116 HINIC_PORT_CMD_GET_PORT_INFO = 0xaa, 117 118 HINIC_PORT_CMD_UP_TC_ADD_FLOW = 0xaf, 119 HINIC_PORT_CMD_UP_TC_DEL_FLOW = 0xb0, 120 HINIC_PORT_CMD_UP_TC_GET_FLOW = 0xb1, 121 HINIC_PORT_CMD_UP_TC_FLUSH_TCAM = 0xb2, 122 HINIC_PORT_CMD_UP_TC_CTRL_TCAM_BLOCK = 0xb3, 123 HINIC_PORT_CMD_UP_TC_ENABLE = 0xb4, 124 125 HINIC_PORT_CMD_SET_IPSU_MAC = 0xcb, 126 HINIC_PORT_CMD_GET_IPSU_MAC = 0xcc, 127 128 HINIC_PORT_CMD_SET_XSFP_STATUS = 0xD4, 129 130 HINIC_PORT_CMD_GET_LINK_MODE = 0xD9, 131 HINIC_PORT_CMD_SET_SPEED = 0xDA, 132 HINIC_PORT_CMD_SET_AUTONEG = 0xDB, 133 134 HINIC_PORT_CMD_CLEAR_QP_RES = 0xDD, 135 HINIC_PORT_CMD_SET_SUPER_CQE = 0xDE, 136 HINIC_PORT_CMD_SET_VF_COS = 0xDF, 137 HINIC_PORT_CMD_GET_VF_COS = 0xE1, 138 139 HINIC_PORT_CMD_CABLE_PLUG_EVENT = 0xE5, 140 HINIC_PORT_CMD_LINK_ERR_EVENT = 0xE6, 141 142 HINIC_PORT_CMD_SET_COS_UP_MAP = 0xE8, 143 144 HINIC_PORT_CMD_RESET_LINK_CFG = 0xEB, 145 146 HINIC_PORT_CMD_FORCE_PKT_DROP = 0xF3, 147 HINIC_PORT_CMD_SET_LRO_TIMER = 0xF4, 148 149 HINIC_PORT_CMD_SET_VHD_CFG = 0xF7, 150 HINIC_PORT_CMD_SET_LINK_FOLLOW = 0xF8, 151 HINIC_PORT_CMD_Q_FILTER = 0xFC, 152 HINIC_PORT_CMD_TCAM_FILTER = 0xFE, 153 HINIC_PORT_CMD_SET_VLAN_FILTER = 0xFF 154 }; 155 156 /* cmd of mgmt CPU message for HW module */ 157 enum hinic_mgmt_cmd { 158 HINIC_MGMT_CMD_RESET_MGMT = 0x0, 159 HINIC_MGMT_CMD_START_FLR = 0x1, 160 HINIC_MGMT_CMD_FLUSH_DOORBELL = 0x2, 161 HINIC_MGMT_CMD_GET_IO_STATUS = 0x3, 162 HINIC_MGMT_CMD_DMA_ATTR_SET = 0x4, 163 164 HINIC_MGMT_CMD_CMDQ_CTXT_SET = 0x10, 165 HINIC_MGMT_CMD_CMDQ_CTXT_GET, 166 167 HINIC_MGMT_CMD_VAT_SET = 0x12, 168 HINIC_MGMT_CMD_VAT_GET, 169 170 HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET = 0x14, 171 HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET, 172 173 HINIC_MGMT_CMD_PPF_HT_GPA_SET = 0x23, 174 HINIC_MGMT_CMD_RES_STATE_SET = 0x24, 175 HINIC_MGMT_CMD_FUNC_CACHE_OUT = 0x25, 176 HINIC_MGMT_CMD_FFM_SET = 0x26, 177 178 HINIC_MGMT_CMD_FUNC_RES_CLEAR = 0x29, 179 180 HINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP = 0x33, 181 HINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP, 182 HINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP, 183 184 HINIC_MGMT_CMD_VF_RANDOM_ID_SET = 0x36, 185 HINIC_MGMT_CMD_FAULT_REPORT = 0x37, 186 187 HINIC_MGMT_CMD_VPD_SET = 0x40, 188 HINIC_MGMT_CMD_VPD_GET, 189 HINIC_MGMT_CMD_LABEL_SET, 190 HINIC_MGMT_CMD_LABEL_GET, 191 HINIC_MGMT_CMD_SATIC_MAC_SET, 192 HINIC_MGMT_CMD_SATIC_MAC_GET, 193 HINIC_MGMT_CMD_SYNC_TIME = 0x46, 194 HINIC_MGMT_CMD_SET_LED_STATUS = 0x4A, 195 HINIC_MGMT_CMD_L2NIC_RESET = 0x4b, 196 HINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET = 0x4d, 197 HINIC_MGMT_CMD_BIOS_NV_DATA_MGMT = 0x4E, 198 HINIC_MGMT_CMD_ACTIVATE_FW = 0x4F, 199 HINIC_MGMT_CMD_PAGESIZE_SET = 0x50, 200 HINIC_MGMT_CMD_PAGESIZE_GET = 0x51, 201 HINIC_MGMT_CMD_GET_BOARD_INFO = 0x52, 202 HINIC_MGMT_CMD_WATCHDOG_INFO = 0x56, 203 HINIC_MGMT_CMD_FMW_ACT_NTC = 0x57, 204 HINIC_MGMT_CMD_SET_VF_RANDOM_ID = 0x61, 205 HINIC_MGMT_CMD_GET_PPF_STATE = 0x63, 206 HINIC_MGMT_CMD_PCIE_DFX_NTC = 0x65, 207 HINIC_MGMT_CMD_PCIE_DFX_GET = 0x66, 208 }; 209 210 /* cmd of mgmt CPU message for HILINK module */ 211 enum hinic_hilink_cmd { 212 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3, 213 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8, 214 }; 215 216 /* uCode related commands */ 217 enum hinic_ucode_cmd { 218 HINIC_UCODE_CMD_MDY_QUEUE_CONTEXT = 0, 219 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, 220 HINIC_UCODE_CMD_ARM_SQ, 221 HINIC_UCODE_CMD_ARM_RQ, 222 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, 223 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, 224 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, 225 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, 226 HINIC_UCODE_CMD_SET_IQ_ENABLE, 227 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 228 }; 229 230 enum cfg_sub_cmd { 231 /* PPF(PF) <-> FW */ 232 HINIC_CFG_NIC_CAP = 0, 233 CFG_FW_VERSION, 234 CFG_UCODE_VERSION, 235 HINIC_CFG_MBOX_CAP = 6 236 }; 237 238 enum hinic_ack_type { 239 HINIC_ACK_TYPE_CMDQ, 240 HINIC_ACK_TYPE_SHARE_CQN, 241 HINIC_ACK_TYPE_APP_CQN, 242 243 HINIC_MOD_ACK_MAX = 15, 244 }; 245 246 enum sq_l4offload_type { 247 OFFLOAD_DISABLE = 0, 248 TCP_OFFLOAD_ENABLE = 1, 249 SCTP_OFFLOAD_ENABLE = 2, 250 UDP_OFFLOAD_ENABLE = 3, 251 }; 252 253 enum sq_vlan_offload_flag { 254 VLAN_OFFLOAD_DISABLE = 0, 255 VLAN_OFFLOAD_ENABLE = 1, 256 }; 257 258 enum sq_pkt_parsed_flag { 259 PKT_NOT_PARSED = 0, 260 PKT_PARSED = 1, 261 }; 262 263 enum sq_l3_type { 264 UNKNOWN_L3TYPE = 0, 265 IPV6_PKT = 1, 266 IPV4_PKT_NO_CHKSUM_OFFLOAD = 2, 267 IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3, 268 }; 269 270 enum sq_md_type { 271 UNKNOWN_MD_TYPE = 0, 272 }; 273 274 enum sq_l2type { 275 ETHERNET = 0, 276 }; 277 278 enum sq_tunnel_l4_type { 279 NOT_TUNNEL, 280 TUNNEL_UDP_NO_CSUM, 281 TUNNEL_UDP_CSUM, 282 }; 283 284 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 285 #define NIC_RSS_CMD_TEMP_FREE 0x02 286 287 #define HINIC_RSS_TYPE_VALID_SHIFT 23 288 #define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT 24 289 #define HINIC_RSS_TYPE_IPV6_EXT_SHIFT 25 290 #define HINIC_RSS_TYPE_TCP_IPV6_SHIFT 26 291 #define HINIC_RSS_TYPE_IPV6_SHIFT 27 292 #define HINIC_RSS_TYPE_TCP_IPV4_SHIFT 28 293 #define HINIC_RSS_TYPE_IPV4_SHIFT 29 294 #define HINIC_RSS_TYPE_UDP_IPV6_SHIFT 30 295 #define HINIC_RSS_TYPE_UDP_IPV4_SHIFT 31 296 297 #define HINIC_RSS_TYPE_SET(val, member) \ 298 (((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT) 299 300 #define HINIC_RSS_TYPE_GET(val, member) \ 301 (((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1) 302 303 enum hinic_speed { 304 HINIC_SPEED_10MB_LINK = 0, 305 HINIC_SPEED_100MB_LINK, 306 HINIC_SPEED_1000MB_LINK, 307 HINIC_SPEED_10GB_LINK, 308 HINIC_SPEED_25GB_LINK, 309 HINIC_SPEED_40GB_LINK, 310 HINIC_SPEED_100GB_LINK, 311 HINIC_SPEED_UNKNOWN = 0xFF, 312 }; 313 314 enum { 315 HINIC_IFLA_VF_LINK_STATE_AUTO, /* link state of the uplink */ 316 HINIC_IFLA_VF_LINK_STATE_ENABLE, /* link always up */ 317 HINIC_IFLA_VF_LINK_STATE_DISABLE, /* link always down */ 318 }; 319 320 #define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT 0 321 #define HINIC_AF0_P2P_IDX_SHIFT 10 322 #define HINIC_AF0_PCI_INTF_IDX_SHIFT 14 323 #define HINIC_AF0_VF_IN_PF_SHIFT 16 324 #define HINIC_AF0_FUNC_TYPE_SHIFT 24 325 326 #define HINIC_AF0_FUNC_GLOBAL_IDX_MASK 0x3FF 327 #define HINIC_AF0_P2P_IDX_MASK 0xF 328 #define HINIC_AF0_PCI_INTF_IDX_MASK 0x3 329 #define HINIC_AF0_VF_IN_PF_MASK 0xFF 330 #define HINIC_AF0_FUNC_TYPE_MASK 0x1 331 332 #define HINIC_AF0_GET(val, member) \ 333 (((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK) 334 335 #define HINIC_AF1_PPF_IDX_SHIFT 0 336 #define HINIC_AF1_AEQS_PER_FUNC_SHIFT 8 337 #define HINIC_AF1_CEQS_PER_FUNC_SHIFT 12 338 #define HINIC_AF1_IRQS_PER_FUNC_SHIFT 20 339 #define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT 24 340 #define HINIC_AF1_MGMT_INIT_STATUS_SHIFT 30 341 #define HINIC_AF1_PF_INIT_STATUS_SHIFT 31 342 343 #define HINIC_AF1_PPF_IDX_MASK 0x1F 344 #define HINIC_AF1_AEQS_PER_FUNC_MASK 0x3 345 #define HINIC_AF1_CEQS_PER_FUNC_MASK 0x7 346 #define HINIC_AF1_IRQS_PER_FUNC_MASK 0xF 347 #define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK 0x7 348 #define HINIC_AF1_MGMT_INIT_STATUS_MASK 0x1 349 #define HINIC_AF1_PF_INIT_STATUS_MASK 0x1 350 351 #define HINIC_AF1_GET(val, member) \ 352 (((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK) 353 354 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT 16 355 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK 0x3FF 356 357 #define HINIC_AF2_GET(val, member) \ 358 (((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK) 359 360 #define HINIC_AF4_OUTBOUND_CTRL_SHIFT 0 361 #define HINIC_AF4_DOORBELL_CTRL_SHIFT 1 362 #define HINIC_AF4_OUTBOUND_CTRL_MASK 0x1 363 #define HINIC_AF4_DOORBELL_CTRL_MASK 0x1 364 365 #define HINIC_AF4_GET(val, member) \ 366 (((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK) 367 368 #define HINIC_AF4_SET(val, member) \ 369 (((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT) 370 371 #define HINIC_AF4_CLEAR(val, member) \ 372 ((val) & (~(HINIC_AF4_##member##_MASK << \ 373 HINIC_AF4_##member##_SHIFT))) 374 375 #define HINIC_AF5_PF_STATUS_SHIFT 0 376 #define HINIC_AF5_PF_STATUS_MASK 0xFFFF 377 378 #define HINIC_AF5_SET(val, member) \ 379 (((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT) 380 381 #define HINIC_AF5_GET(val, member) \ 382 (((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK) 383 384 #define HINIC_AF5_CLEAR(val, member) \ 385 ((val) & (~(HINIC_AF5_##member##_MASK << \ 386 HINIC_AF5_##member##_SHIFT))) 387 388 #define HINIC_PPF_ELECTION_IDX_SHIFT 0 389 390 #define HINIC_PPF_ELECTION_IDX_MASK 0x1F 391 392 #define HINIC_PPF_ELECTION_SET(val, member) \ 393 (((val) & HINIC_PPF_ELECTION_##member##_MASK) << \ 394 HINIC_PPF_ELECTION_##member##_SHIFT) 395 396 #define HINIC_PPF_ELECTION_GET(val, member) \ 397 (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \ 398 HINIC_PPF_ELECTION_##member##_MASK) 399 400 #define HINIC_PPF_ELECTION_CLEAR(val, member) \ 401 ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \ 402 << HINIC_PPF_ELECTION_##member##_SHIFT))) 403 404 #define DB_IDX(db, db_base) \ 405 ((u32)(((unsigned long)(db) - (unsigned long)(db_base)) / \ 406 HINIC_DB_PAGE_SIZE)) 407 408 enum hinic_pcie_nosnoop { 409 HINIC_PCIE_SNOOP = 0, 410 HINIC_PCIE_NO_SNOOP = 1, 411 }; 412 413 enum hinic_pcie_tph { 414 HINIC_PCIE_TPH_DISABLE = 0, 415 HINIC_PCIE_TPH_ENABLE = 1, 416 }; 417 418 enum hinic_outbound_ctrl { 419 ENABLE_OUTBOUND = 0x0, 420 DISABLE_OUTBOUND = 0x1, 421 }; 422 423 enum hinic_doorbell_ctrl { 424 ENABLE_DOORBELL = 0x0, 425 DISABLE_DOORBELL = 0x1, 426 }; 427 428 enum hinic_pf_status { 429 HINIC_PF_STATUS_INIT = 0X0, 430 HINIC_PF_STATUS_ACTIVE_FLAG = 0x11, 431 HINIC_PF_STATUS_FLR_START_FLAG = 0x12, 432 HINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13, 433 }; 434 435 /* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */ 436 #define HINIC_DB_DWQE_SIZE 0x00080000 437 438 /* db page size: 4K */ 439 #define HINIC_DB_PAGE_SIZE 0x00001000ULL 440 441 #define HINIC_DB_MAX_AREAS (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE) 442 443 #define HINIC_PCI_MSIX_ENTRY_SIZE 16 444 #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12 445 #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1 446 447 struct hinic_mgmt_msg_head { 448 u8 status; 449 u8 version; 450 u8 resp_aeq_num; 451 u8 rsvd0[5]; 452 }; 453 454 struct hinic_root_ctxt { 455 struct hinic_mgmt_msg_head mgmt_msg_head; 456 457 u16 func_idx; 458 u16 rsvd1; 459 u8 set_cmdq_depth; 460 u8 cmdq_depth; 461 u8 lro_en; 462 u8 rsvd2; 463 u8 ppf_idx; 464 u8 rsvd3; 465 u16 rq_depth; 466 u16 rx_buf_sz; 467 u16 sq_depth; 468 }; 469 470 #endif /* _HINIC_PORT_CMD_H_ */ 471