1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <rte_dev.h> 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_ethdev_pci.h> 14 #include <rte_kvargs.h> 15 #include <rte_string_fns.h> 16 17 #include "vnic_intr.h" 18 #include "vnic_cq.h" 19 #include "vnic_wq.h" 20 #include "vnic_rq.h" 21 #include "vnic_enet.h" 22 #include "enic.h" 23 24 /* 25 * The set of PCI devices this driver supports 26 */ 27 #define CISCO_PCI_VENDOR_ID 0x1137 28 static const struct rte_pci_id pci_id_enic_map[] = { 29 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)}, 30 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)}, 31 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)}, 32 {.vendor_id = 0, /* sentinel */}, 33 }; 34 35 /* Supported link speeds of production VIC models */ 36 static const struct vic_speed_capa { 37 uint16_t sub_devid; 38 uint32_t capa; 39 } vic_speed_capa_map[] = { 40 { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */ 41 { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */ 42 { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */ 43 { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */ 44 { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */ 45 { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */ 46 { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */ 47 { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */ 48 { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */ 49 { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */ 50 { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */ 51 { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */ 52 { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */ 53 { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */ 54 { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 55 ETH_LINK_SPEED_40G }, /* 1440 Mezz */ 56 { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 57 ETH_LINK_SPEED_40G }, /* 1480 MLOM */ 58 { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */ 59 { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */ 60 { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */ 61 { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */ 62 { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */ 63 { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */ 64 { 0, 0 }, /* End marker */ 65 }; 66 67 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 68 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 69 #define ENIC_DEVARG_GENEVE_OPT "geneve-opt" 70 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 71 #define ENIC_DEVARG_REPRESENTOR "representor" 72 73 RTE_LOG_REGISTER(enic_pmd_logtype, pmd.net.enic, INFO); 74 75 static int 76 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev, 77 enum rte_filter_op filter_op, void *arg) 78 { 79 struct enic *enic = pmd_priv(eth_dev); 80 int ret = 0; 81 82 ENICPMD_FUNC_TRACE(); 83 if (filter_op == RTE_ETH_FILTER_NOP) 84 return 0; 85 86 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 87 return -EINVAL; 88 89 switch (filter_op) { 90 case RTE_ETH_FILTER_ADD: 91 case RTE_ETH_FILTER_UPDATE: 92 ret = enic_fdir_add_fltr(enic, 93 (struct rte_eth_fdir_filter *)arg); 94 break; 95 96 case RTE_ETH_FILTER_DELETE: 97 ret = enic_fdir_del_fltr(enic, 98 (struct rte_eth_fdir_filter *)arg); 99 break; 100 101 case RTE_ETH_FILTER_STATS: 102 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg); 103 break; 104 105 case RTE_ETH_FILTER_FLUSH: 106 dev_warning(enic, "unsupported operation %u", filter_op); 107 ret = -ENOTSUP; 108 break; 109 case RTE_ETH_FILTER_INFO: 110 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg); 111 break; 112 default: 113 dev_err(enic, "unknown operation %u", filter_op); 114 ret = -EINVAL; 115 break; 116 } 117 return ret; 118 } 119 120 static int 121 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev, 122 enum rte_filter_type filter_type, 123 enum rte_filter_op filter_op, 124 void *arg) 125 { 126 struct enic *enic = pmd_priv(dev); 127 int ret = 0; 128 129 ENICPMD_FUNC_TRACE(); 130 131 /* 132 * Currently, when Geneve with options offload is enabled, host 133 * cannot insert match-action rules. 134 */ 135 if (enic->geneve_opt_enabled) 136 return -ENOTSUP; 137 switch (filter_type) { 138 case RTE_ETH_FILTER_GENERIC: 139 if (filter_op != RTE_ETH_FILTER_GET) 140 return -EINVAL; 141 if (enic->flow_filter_mode == FILTER_FLOWMAN) 142 *(const void **)arg = &enic_fm_flow_ops; 143 else 144 *(const void **)arg = &enic_flow_ops; 145 break; 146 case RTE_ETH_FILTER_FDIR: 147 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg); 148 break; 149 default: 150 dev_warning(enic, "Filter type (%d) not supported", 151 filter_type); 152 ret = -EINVAL; 153 break; 154 } 155 156 return ret; 157 } 158 159 static void enicpmd_dev_tx_queue_release(void *txq) 160 { 161 ENICPMD_FUNC_TRACE(); 162 163 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 164 return; 165 166 enic_free_wq(txq); 167 } 168 169 static int enicpmd_dev_setup_intr(struct enic *enic) 170 { 171 int ret; 172 unsigned int index; 173 174 ENICPMD_FUNC_TRACE(); 175 176 /* Are we done with the init of all the queues? */ 177 for (index = 0; index < enic->cq_count; index++) { 178 if (!enic->cq[index].ctrl) 179 break; 180 } 181 if (enic->cq_count != index) 182 return 0; 183 for (index = 0; index < enic->wq_count; index++) { 184 if (!enic->wq[index].ctrl) 185 break; 186 } 187 if (enic->wq_count != index) 188 return 0; 189 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 190 for (index = 0; index < enic->rq_count; index++) { 191 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 192 break; 193 } 194 if (enic->rq_count != index) 195 return 0; 196 197 ret = enic_alloc_intr_resources(enic); 198 if (ret) { 199 dev_err(enic, "alloc intr failed\n"); 200 return ret; 201 } 202 enic_init_vnic_resources(enic); 203 204 ret = enic_setup_finish(enic); 205 if (ret) 206 dev_err(enic, "setup could not be finished\n"); 207 208 return ret; 209 } 210 211 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 212 uint16_t queue_idx, 213 uint16_t nb_desc, 214 unsigned int socket_id, 215 const struct rte_eth_txconf *tx_conf) 216 { 217 int ret; 218 struct enic *enic = pmd_priv(eth_dev); 219 struct vnic_wq *wq; 220 221 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 222 return -E_RTE_SECONDARY; 223 224 ENICPMD_FUNC_TRACE(); 225 RTE_ASSERT(queue_idx < enic->conf_wq_count); 226 wq = &enic->wq[queue_idx]; 227 wq->offloads = tx_conf->offloads | 228 eth_dev->data->dev_conf.txmode.offloads; 229 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 230 231 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 232 if (ret) { 233 dev_err(enic, "error in allocating wq\n"); 234 return ret; 235 } 236 237 return enicpmd_dev_setup_intr(enic); 238 } 239 240 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 241 uint16_t queue_idx) 242 { 243 struct enic *enic = pmd_priv(eth_dev); 244 245 ENICPMD_FUNC_TRACE(); 246 247 enic_start_wq(enic, queue_idx); 248 249 return 0; 250 } 251 252 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 253 uint16_t queue_idx) 254 { 255 int ret; 256 struct enic *enic = pmd_priv(eth_dev); 257 258 ENICPMD_FUNC_TRACE(); 259 260 ret = enic_stop_wq(enic, queue_idx); 261 if (ret) 262 dev_err(enic, "error in stopping wq %d\n", queue_idx); 263 264 return ret; 265 } 266 267 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 268 uint16_t queue_idx) 269 { 270 struct enic *enic = pmd_priv(eth_dev); 271 272 ENICPMD_FUNC_TRACE(); 273 274 enic_start_rq(enic, queue_idx); 275 276 return 0; 277 } 278 279 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 280 uint16_t queue_idx) 281 { 282 int ret; 283 struct enic *enic = pmd_priv(eth_dev); 284 285 ENICPMD_FUNC_TRACE(); 286 287 ret = enic_stop_rq(enic, queue_idx); 288 if (ret) 289 dev_err(enic, "error in stopping rq %d\n", queue_idx); 290 291 return ret; 292 } 293 294 static void enicpmd_dev_rx_queue_release(void *rxq) 295 { 296 ENICPMD_FUNC_TRACE(); 297 298 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 299 return; 300 301 enic_free_rq(rxq); 302 } 303 304 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev, 305 uint16_t rx_queue_id) 306 { 307 struct enic *enic = pmd_priv(dev); 308 uint32_t queue_count = 0; 309 struct vnic_cq *cq; 310 uint32_t cq_tail; 311 uint16_t cq_idx; 312 int rq_num; 313 314 rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 315 cq = &enic->cq[enic_cq_rq(enic, rq_num)]; 316 cq_idx = cq->to_clean; 317 318 cq_tail = ioread32(&cq->ctrl->cq_tail); 319 320 if (cq_tail < cq_idx) 321 cq_tail += cq->ring.desc_count; 322 323 queue_count = cq_tail - cq_idx; 324 325 return queue_count; 326 } 327 328 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 329 uint16_t queue_idx, 330 uint16_t nb_desc, 331 unsigned int socket_id, 332 const struct rte_eth_rxconf *rx_conf, 333 struct rte_mempool *mp) 334 { 335 int ret; 336 struct enic *enic = pmd_priv(eth_dev); 337 338 ENICPMD_FUNC_TRACE(); 339 340 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 341 return -E_RTE_SECONDARY; 342 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 343 eth_dev->data->rx_queues[queue_idx] = 344 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 345 346 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 347 rx_conf->rx_free_thresh); 348 if (ret) { 349 dev_err(enic, "error in allocating rq\n"); 350 return ret; 351 } 352 353 return enicpmd_dev_setup_intr(enic); 354 } 355 356 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 357 { 358 struct enic *enic = pmd_priv(eth_dev); 359 uint64_t offloads; 360 361 ENICPMD_FUNC_TRACE(); 362 363 offloads = eth_dev->data->dev_conf.rxmode.offloads; 364 if (mask & ETH_VLAN_STRIP_MASK) { 365 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 366 enic->ig_vlan_strip_en = 1; 367 else 368 enic->ig_vlan_strip_en = 0; 369 } 370 371 return enic_set_vlan_strip(enic); 372 } 373 374 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 375 { 376 int ret; 377 int mask; 378 struct enic *enic = pmd_priv(eth_dev); 379 380 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 381 return -E_RTE_SECONDARY; 382 383 ENICPMD_FUNC_TRACE(); 384 ret = enic_set_vnic_res(enic); 385 if (ret) { 386 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 387 return ret; 388 } 389 390 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 391 eth_dev->data->dev_conf.rxmode.offloads |= 392 DEV_RX_OFFLOAD_RSS_HASH; 393 394 enic->mc_count = 0; 395 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 396 DEV_RX_OFFLOAD_CHECKSUM); 397 /* All vlan offload masks to apply the current settings */ 398 mask = ETH_VLAN_STRIP_MASK | 399 ETH_VLAN_FILTER_MASK | 400 ETH_VLAN_EXTEND_MASK; 401 ret = enicpmd_vlan_offload_set(eth_dev, mask); 402 if (ret) { 403 dev_err(enic, "Failed to configure VLAN offloads\n"); 404 return ret; 405 } 406 /* 407 * Initialize RSS with the default reta and key. If the user key is 408 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 409 * default key. 410 */ 411 return enic_init_rss_nic_cfg(enic); 412 } 413 414 /* Start the device. 415 * It returns 0 on success. 416 */ 417 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 418 { 419 struct enic *enic = pmd_priv(eth_dev); 420 421 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 422 return -E_RTE_SECONDARY; 423 424 ENICPMD_FUNC_TRACE(); 425 return enic_enable(enic); 426 } 427 428 /* 429 * Stop device: disable rx and tx functions to allow for reconfiguring. 430 */ 431 static void enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 432 { 433 struct rte_eth_link link; 434 struct enic *enic = pmd_priv(eth_dev); 435 436 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 437 return; 438 439 ENICPMD_FUNC_TRACE(); 440 enic_disable(enic); 441 442 memset(&link, 0, sizeof(link)); 443 rte_eth_linkstatus_set(eth_dev, &link); 444 } 445 446 /* 447 * Stop device. 448 */ 449 static int enicpmd_dev_close(struct rte_eth_dev *eth_dev) 450 { 451 struct enic *enic = pmd_priv(eth_dev); 452 453 ENICPMD_FUNC_TRACE(); 454 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 455 return 0; 456 457 enic_remove(enic); 458 459 return 0; 460 } 461 462 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 463 __rte_unused int wait_to_complete) 464 { 465 ENICPMD_FUNC_TRACE(); 466 return enic_link_update(eth_dev); 467 } 468 469 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 470 struct rte_eth_stats *stats) 471 { 472 struct enic *enic = pmd_priv(eth_dev); 473 474 ENICPMD_FUNC_TRACE(); 475 return enic_dev_stats_get(enic, stats); 476 } 477 478 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 479 { 480 struct enic *enic = pmd_priv(eth_dev); 481 482 ENICPMD_FUNC_TRACE(); 483 return enic_dev_stats_clear(enic); 484 } 485 486 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) 487 { 488 const struct vic_speed_capa *m; 489 struct rte_pci_device *pdev; 490 uint16_t id; 491 492 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 493 id = pdev->id.subsystem_device_id; 494 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { 495 if (m->sub_devid == id) 496 return m->capa; 497 } 498 /* 1300 and later models are at least 40G */ 499 if (id >= 0x0100) 500 return ETH_LINK_SPEED_40G; 501 /* VFs have subsystem id 0, check device id */ 502 if (id == 0) { 503 /* Newer VF implies at least 40G model */ 504 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN) 505 return ETH_LINK_SPEED_40G; 506 } 507 return ETH_LINK_SPEED_10G; 508 } 509 510 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 511 struct rte_eth_dev_info *device_info) 512 { 513 struct enic *enic = pmd_priv(eth_dev); 514 515 ENICPMD_FUNC_TRACE(); 516 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 517 device_info->max_rx_queues = enic->conf_rq_count / 2; 518 device_info->max_tx_queues = enic->conf_wq_count; 519 device_info->min_rx_bufsize = ENIC_MIN_MTU; 520 /* "Max" mtu is not a typo. HW receives packet sizes up to the 521 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 522 * a hint to the driver to size receive buffers accordingly so that 523 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 524 * the user decide the buffer size via rxmode.max_rx_pkt_len, basically 525 * ignoring vNIC mtu. 526 */ 527 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 528 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS; 529 device_info->min_mtu = ENIC_MIN_MTU; 530 device_info->max_mtu = enic->max_mtu; 531 device_info->rx_offload_capa = enic->rx_offload_capa; 532 device_info->tx_offload_capa = enic->tx_offload_capa; 533 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 534 device_info->default_rxconf = (struct rte_eth_rxconf) { 535 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 536 }; 537 device_info->reta_size = enic->reta_size; 538 device_info->hash_key_size = enic->hash_key_size; 539 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 540 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 541 .nb_max = enic->config.rq_desc_count, 542 .nb_min = ENIC_MIN_RQ_DESCS, 543 .nb_align = ENIC_ALIGN_DESCS, 544 }; 545 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 546 .nb_max = enic->config.wq_desc_count, 547 .nb_min = ENIC_MIN_WQ_DESCS, 548 .nb_align = ENIC_ALIGN_DESCS, 549 .nb_seg_max = ENIC_TX_XMIT_MAX, 550 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 551 }; 552 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 553 .burst_size = ENIC_DEFAULT_RX_BURST, 554 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 555 ENIC_DEFAULT_RX_RING_SIZE), 556 .nb_queues = ENIC_DEFAULT_RX_RINGS, 557 }; 558 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 559 .burst_size = ENIC_DEFAULT_TX_BURST, 560 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 561 ENIC_DEFAULT_TX_RING_SIZE), 562 .nb_queues = ENIC_DEFAULT_TX_RINGS, 563 }; 564 device_info->speed_capa = speed_capa_from_pci_id(eth_dev); 565 566 return 0; 567 } 568 569 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) 570 { 571 static const uint32_t ptypes[] = { 572 RTE_PTYPE_L2_ETHER, 573 RTE_PTYPE_L2_ETHER_VLAN, 574 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 575 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 576 RTE_PTYPE_L4_TCP, 577 RTE_PTYPE_L4_UDP, 578 RTE_PTYPE_L4_FRAG, 579 RTE_PTYPE_L4_NONFRAG, 580 RTE_PTYPE_UNKNOWN 581 }; 582 static const uint32_t ptypes_overlay[] = { 583 RTE_PTYPE_L2_ETHER, 584 RTE_PTYPE_L2_ETHER_VLAN, 585 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 586 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 587 RTE_PTYPE_L4_TCP, 588 RTE_PTYPE_L4_UDP, 589 RTE_PTYPE_L4_FRAG, 590 RTE_PTYPE_L4_NONFRAG, 591 RTE_PTYPE_TUNNEL_GRENAT, 592 RTE_PTYPE_INNER_L2_ETHER, 593 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 594 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 595 RTE_PTYPE_INNER_L4_TCP, 596 RTE_PTYPE_INNER_L4_UDP, 597 RTE_PTYPE_INNER_L4_FRAG, 598 RTE_PTYPE_INNER_L4_NONFRAG, 599 RTE_PTYPE_UNKNOWN 600 }; 601 602 if (dev->rx_pkt_burst != enic_dummy_recv_pkts && 603 dev->rx_pkt_burst != NULL) { 604 struct enic *enic = pmd_priv(dev); 605 if (enic->overlay_offload) 606 return ptypes_overlay; 607 else 608 return ptypes; 609 } 610 return NULL; 611 } 612 613 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 614 { 615 struct enic *enic = pmd_priv(eth_dev); 616 int ret; 617 618 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 619 return -E_RTE_SECONDARY; 620 621 ENICPMD_FUNC_TRACE(); 622 623 enic->promisc = 1; 624 ret = enic_add_packet_filter(enic); 625 if (ret != 0) 626 enic->promisc = 0; 627 628 return ret; 629 } 630 631 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 632 { 633 struct enic *enic = pmd_priv(eth_dev); 634 int ret; 635 636 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 637 return -E_RTE_SECONDARY; 638 639 ENICPMD_FUNC_TRACE(); 640 enic->promisc = 0; 641 ret = enic_add_packet_filter(enic); 642 if (ret != 0) 643 enic->promisc = 1; 644 645 return ret; 646 } 647 648 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 649 { 650 struct enic *enic = pmd_priv(eth_dev); 651 int ret; 652 653 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 654 return -E_RTE_SECONDARY; 655 656 ENICPMD_FUNC_TRACE(); 657 enic->allmulti = 1; 658 ret = enic_add_packet_filter(enic); 659 if (ret != 0) 660 enic->allmulti = 0; 661 662 return ret; 663 } 664 665 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 666 { 667 struct enic *enic = pmd_priv(eth_dev); 668 int ret; 669 670 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 671 return -E_RTE_SECONDARY; 672 673 ENICPMD_FUNC_TRACE(); 674 enic->allmulti = 0; 675 ret = enic_add_packet_filter(enic); 676 if (ret != 0) 677 enic->allmulti = 1; 678 679 return ret; 680 } 681 682 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 683 struct rte_ether_addr *mac_addr, 684 __rte_unused uint32_t index, __rte_unused uint32_t pool) 685 { 686 struct enic *enic = pmd_priv(eth_dev); 687 688 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 689 return -E_RTE_SECONDARY; 690 691 ENICPMD_FUNC_TRACE(); 692 return enic_set_mac_address(enic, mac_addr->addr_bytes); 693 } 694 695 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 696 { 697 struct enic *enic = pmd_priv(eth_dev); 698 699 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 700 return; 701 702 ENICPMD_FUNC_TRACE(); 703 if (enic_del_mac_address(enic, index)) 704 dev_err(enic, "del mac addr failed\n"); 705 } 706 707 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 708 struct rte_ether_addr *addr) 709 { 710 struct enic *enic = pmd_priv(eth_dev); 711 int ret; 712 713 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 714 return -E_RTE_SECONDARY; 715 716 ENICPMD_FUNC_TRACE(); 717 ret = enic_del_mac_address(enic, 0); 718 if (ret) 719 return ret; 720 return enic_set_mac_address(enic, addr->addr_bytes); 721 } 722 723 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add) 724 { 725 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 726 727 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr); 728 ENICPMD_LOG(DEBUG, " %s address %s\n", 729 add ? "add" : "remove", mac_str); 730 } 731 732 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev, 733 struct rte_ether_addr *mc_addr_set, 734 uint32_t nb_mc_addr) 735 { 736 struct enic *enic = pmd_priv(eth_dev); 737 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 738 struct rte_ether_addr *addr; 739 uint32_t i, j; 740 int ret; 741 742 ENICPMD_FUNC_TRACE(); 743 744 /* Validate the given addresses first */ 745 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) { 746 addr = &mc_addr_set[i]; 747 if (!rte_is_multicast_ether_addr(addr) || 748 rte_is_broadcast_ether_addr(addr)) { 749 rte_ether_format_addr(mac_str, 750 RTE_ETHER_ADDR_FMT_SIZE, addr); 751 ENICPMD_LOG(ERR, " invalid multicast address %s\n", 752 mac_str); 753 return -EINVAL; 754 } 755 } 756 757 /* Flush all if requested */ 758 if (nb_mc_addr == 0 || mc_addr_set == NULL) { 759 ENICPMD_LOG(DEBUG, " flush multicast addresses\n"); 760 for (i = 0; i < enic->mc_count; i++) { 761 addr = &enic->mc_addrs[i]; 762 debug_log_add_del_addr(addr, false); 763 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 764 if (ret) 765 return ret; 766 } 767 enic->mc_count = 0; 768 return 0; 769 } 770 771 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) { 772 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n", 773 ENIC_MULTICAST_PERFECT_FILTERS); 774 return -ENOSPC; 775 } 776 /* 777 * devcmd is slow, so apply the difference instead of flushing and 778 * adding everything. 779 * 1. Delete addresses on the NIC but not on the host 780 */ 781 for (i = 0; i < enic->mc_count; i++) { 782 addr = &enic->mc_addrs[i]; 783 for (j = 0; j < nb_mc_addr; j++) { 784 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) 785 break; 786 } 787 if (j < nb_mc_addr) 788 continue; 789 debug_log_add_del_addr(addr, false); 790 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 791 if (ret) 792 return ret; 793 } 794 /* 2. Add addresses on the host but not on the NIC */ 795 for (i = 0; i < nb_mc_addr; i++) { 796 addr = &mc_addr_set[i]; 797 for (j = 0; j < enic->mc_count; j++) { 798 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j])) 799 break; 800 } 801 if (j < enic->mc_count) 802 continue; 803 debug_log_add_del_addr(addr, true); 804 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes); 805 if (ret) 806 return ret; 807 } 808 /* Keep a copy so we can flush/apply later on.. */ 809 memcpy(enic->mc_addrs, mc_addr_set, 810 nb_mc_addr * sizeof(struct rte_ether_addr)); 811 enic->mc_count = nb_mc_addr; 812 return 0; 813 } 814 815 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 816 { 817 struct enic *enic = pmd_priv(eth_dev); 818 819 ENICPMD_FUNC_TRACE(); 820 return enic_set_mtu(enic, mtu); 821 } 822 823 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 824 struct rte_eth_rss_reta_entry64 825 *reta_conf, 826 uint16_t reta_size) 827 { 828 struct enic *enic = pmd_priv(dev); 829 uint16_t i, idx, shift; 830 831 ENICPMD_FUNC_TRACE(); 832 if (reta_size != ENIC_RSS_RETA_SIZE) { 833 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 834 reta_size, ENIC_RSS_RETA_SIZE); 835 return -EINVAL; 836 } 837 838 for (i = 0; i < reta_size; i++) { 839 idx = i / RTE_RETA_GROUP_SIZE; 840 shift = i % RTE_RETA_GROUP_SIZE; 841 if (reta_conf[idx].mask & (1ULL << shift)) 842 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 843 enic->rss_cpu.cpu[i / 4].b[i % 4]); 844 } 845 846 return 0; 847 } 848 849 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 850 struct rte_eth_rss_reta_entry64 851 *reta_conf, 852 uint16_t reta_size) 853 { 854 struct enic *enic = pmd_priv(dev); 855 union vnic_rss_cpu rss_cpu; 856 uint16_t i, idx, shift; 857 858 ENICPMD_FUNC_TRACE(); 859 if (reta_size != ENIC_RSS_RETA_SIZE) { 860 dev_err(enic, "reta_update: wrong reta_size. given=%u" 861 " expected=%u\n", 862 reta_size, ENIC_RSS_RETA_SIZE); 863 return -EINVAL; 864 } 865 /* 866 * Start with the current reta and modify it per reta_conf, as we 867 * need to push the entire reta even if we only modify one entry. 868 */ 869 rss_cpu = enic->rss_cpu; 870 for (i = 0; i < reta_size; i++) { 871 idx = i / RTE_RETA_GROUP_SIZE; 872 shift = i % RTE_RETA_GROUP_SIZE; 873 if (reta_conf[idx].mask & (1ULL << shift)) 874 rss_cpu.cpu[i / 4].b[i % 4] = 875 enic_rte_rq_idx_to_sop_idx( 876 reta_conf[idx].reta[shift]); 877 } 878 return enic_set_rss_reta(enic, &rss_cpu); 879 } 880 881 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 882 struct rte_eth_rss_conf *rss_conf) 883 { 884 struct enic *enic = pmd_priv(dev); 885 886 ENICPMD_FUNC_TRACE(); 887 return enic_set_rss_conf(enic, rss_conf); 888 } 889 890 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 891 struct rte_eth_rss_conf *rss_conf) 892 { 893 struct enic *enic = pmd_priv(dev); 894 895 ENICPMD_FUNC_TRACE(); 896 if (rss_conf == NULL) 897 return -EINVAL; 898 if (rss_conf->rss_key != NULL && 899 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 900 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 901 " expected=%u+\n", 902 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 903 return -EINVAL; 904 } 905 rss_conf->rss_hf = enic->rss_hf; 906 if (rss_conf->rss_key != NULL) { 907 int i; 908 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 909 rss_conf->rss_key[i] = 910 enic->rss_key.key[i / 10].b[i % 10]; 911 } 912 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 913 } 914 return 0; 915 } 916 917 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 918 uint16_t rx_queue_id, 919 struct rte_eth_rxq_info *qinfo) 920 { 921 struct enic *enic = pmd_priv(dev); 922 struct vnic_rq *rq_sop; 923 struct vnic_rq *rq_data; 924 struct rte_eth_rxconf *conf; 925 uint16_t sop_queue_idx; 926 uint16_t data_queue_idx; 927 928 ENICPMD_FUNC_TRACE(); 929 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 930 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic); 931 rq_sop = &enic->rq[sop_queue_idx]; 932 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 933 qinfo->mp = rq_sop->mp; 934 qinfo->scattered_rx = rq_sop->data_queue_enable; 935 qinfo->nb_desc = rq_sop->ring.desc_count; 936 if (qinfo->scattered_rx) 937 qinfo->nb_desc += rq_data->ring.desc_count; 938 conf = &qinfo->conf; 939 memset(conf, 0, sizeof(*conf)); 940 conf->rx_free_thresh = rq_sop->rx_free_thresh; 941 conf->rx_drop_en = 1; 942 /* 943 * Except VLAN stripping (port setting), all the checksum offloads 944 * are always enabled. 945 */ 946 conf->offloads = enic->rx_offload_capa; 947 if (!enic->ig_vlan_strip_en) 948 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 949 /* rx_thresh and other fields are not applicable for enic */ 950 } 951 952 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 953 uint16_t tx_queue_id, 954 struct rte_eth_txq_info *qinfo) 955 { 956 struct enic *enic = pmd_priv(dev); 957 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 958 959 ENICPMD_FUNC_TRACE(); 960 qinfo->nb_desc = wq->ring.desc_count; 961 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 962 qinfo->conf.offloads = wq->offloads; 963 /* tx_thresh, and all the other fields are not applicable for enic */ 964 } 965 966 static int enicpmd_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 967 __rte_unused uint16_t queue_id, 968 struct rte_eth_burst_mode *mode) 969 { 970 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 971 struct enic *enic = pmd_priv(dev); 972 const char *info_str = NULL; 973 int ret = -EINVAL; 974 975 ENICPMD_FUNC_TRACE(); 976 if (enic->use_noscatter_vec_rx_handler) 977 info_str = "Vector AVX2 No Scatter"; 978 else if (pkt_burst == enic_noscatter_recv_pkts) 979 info_str = "Scalar No Scatter"; 980 else if (pkt_burst == enic_recv_pkts) 981 info_str = "Scalar"; 982 if (info_str) { 983 strlcpy(mode->info, info_str, sizeof(mode->info)); 984 ret = 0; 985 } 986 return ret; 987 } 988 989 static int enicpmd_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 990 __rte_unused uint16_t queue_id, 991 struct rte_eth_burst_mode *mode) 992 { 993 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 994 const char *info_str = NULL; 995 int ret = -EINVAL; 996 997 ENICPMD_FUNC_TRACE(); 998 if (pkt_burst == enic_simple_xmit_pkts) 999 info_str = "Scalar Simplified"; 1000 else if (pkt_burst == enic_xmit_pkts) 1001 info_str = "Scalar"; 1002 if (info_str) { 1003 strlcpy(mode->info, info_str, sizeof(mode->info)); 1004 ret = 0; 1005 } 1006 return ret; 1007 } 1008 1009 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 1010 uint16_t rx_queue_id) 1011 { 1012 struct enic *enic = pmd_priv(eth_dev); 1013 1014 ENICPMD_FUNC_TRACE(); 1015 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 1016 return 0; 1017 } 1018 1019 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 1020 uint16_t rx_queue_id) 1021 { 1022 struct enic *enic = pmd_priv(eth_dev); 1023 1024 ENICPMD_FUNC_TRACE(); 1025 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 1026 return 0; 1027 } 1028 1029 static int udp_tunnel_common_check(struct enic *enic, 1030 struct rte_eth_udp_tunnel *tnl) 1031 { 1032 if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN) 1033 return -ENOTSUP; 1034 if (!enic->overlay_offload) { 1035 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not " 1036 "supported\n"); 1037 return -ENOTSUP; 1038 } 1039 return 0; 1040 } 1041 1042 static int update_vxlan_port(struct enic *enic, uint16_t port) 1043 { 1044 if (vnic_dev_overlay_offload_cfg(enic->vdev, 1045 OVERLAY_CFG_VXLAN_PORT_UPDATE, 1046 port)) { 1047 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n"); 1048 return -EINVAL; 1049 } 1050 ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port); 1051 enic->vxlan_port = port; 1052 return 0; 1053 } 1054 1055 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 1056 struct rte_eth_udp_tunnel *tnl) 1057 { 1058 struct enic *enic = pmd_priv(eth_dev); 1059 int ret; 1060 1061 ENICPMD_FUNC_TRACE(); 1062 ret = udp_tunnel_common_check(enic, tnl); 1063 if (ret) 1064 return ret; 1065 /* 1066 * The NIC has 1 configurable VXLAN port number. "Adding" a new port 1067 * number replaces it. 1068 */ 1069 if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) { 1070 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n", 1071 tnl->udp_port); 1072 return -EINVAL; 1073 } 1074 return update_vxlan_port(enic, tnl->udp_port); 1075 } 1076 1077 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 1078 struct rte_eth_udp_tunnel *tnl) 1079 { 1080 struct enic *enic = pmd_priv(eth_dev); 1081 int ret; 1082 1083 ENICPMD_FUNC_TRACE(); 1084 ret = udp_tunnel_common_check(enic, tnl); 1085 if (ret) 1086 return ret; 1087 /* 1088 * Clear the previously set port number and restore the 1089 * hardware default port number. Some drivers disable VXLAN 1090 * offloads when there are no configured port numbers. But 1091 * enic does not do that as VXLAN is part of overlay offload, 1092 * which is tied to inner RSS and TSO. 1093 */ 1094 if (tnl->udp_port != enic->vxlan_port) { 1095 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n", 1096 tnl->udp_port); 1097 return -EINVAL; 1098 } 1099 return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT); 1100 } 1101 1102 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev, 1103 char *fw_version, size_t fw_size) 1104 { 1105 struct vnic_devcmd_fw_info *info; 1106 struct enic *enic; 1107 int ret; 1108 1109 ENICPMD_FUNC_TRACE(); 1110 if (fw_version == NULL || fw_size <= 0) 1111 return -EINVAL; 1112 enic = pmd_priv(eth_dev); 1113 ret = vnic_dev_fw_info(enic->vdev, &info); 1114 if (ret) 1115 return ret; 1116 snprintf(fw_version, fw_size, "%s %s", 1117 info->fw_version, info->fw_build); 1118 fw_version[fw_size - 1] = '\0'; 1119 return 0; 1120 } 1121 1122 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 1123 .dev_configure = enicpmd_dev_configure, 1124 .dev_start = enicpmd_dev_start, 1125 .dev_stop = enicpmd_dev_stop, 1126 .dev_set_link_up = NULL, 1127 .dev_set_link_down = NULL, 1128 .dev_close = enicpmd_dev_close, 1129 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 1130 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 1131 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 1132 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 1133 .link_update = enicpmd_dev_link_update, 1134 .stats_get = enicpmd_dev_stats_get, 1135 .stats_reset = enicpmd_dev_stats_reset, 1136 .queue_stats_mapping_set = NULL, 1137 .dev_infos_get = enicpmd_dev_info_get, 1138 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 1139 .mtu_set = enicpmd_mtu_set, 1140 .vlan_filter_set = NULL, 1141 .vlan_tpid_set = NULL, 1142 .vlan_offload_set = enicpmd_vlan_offload_set, 1143 .vlan_strip_queue_set = NULL, 1144 .rx_queue_start = enicpmd_dev_rx_queue_start, 1145 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 1146 .tx_queue_start = enicpmd_dev_tx_queue_start, 1147 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 1148 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 1149 .rx_queue_release = enicpmd_dev_rx_queue_release, 1150 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 1151 .tx_queue_release = enicpmd_dev_tx_queue_release, 1152 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 1153 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 1154 .rxq_info_get = enicpmd_dev_rxq_info_get, 1155 .txq_info_get = enicpmd_dev_txq_info_get, 1156 .rx_burst_mode_get = enicpmd_dev_rx_burst_mode_get, 1157 .tx_burst_mode_get = enicpmd_dev_tx_burst_mode_get, 1158 .dev_led_on = NULL, 1159 .dev_led_off = NULL, 1160 .flow_ctrl_get = NULL, 1161 .flow_ctrl_set = NULL, 1162 .priority_flow_ctrl_set = NULL, 1163 .mac_addr_add = enicpmd_add_mac_addr, 1164 .mac_addr_remove = enicpmd_remove_mac_addr, 1165 .mac_addr_set = enicpmd_set_mac_addr, 1166 .set_mc_addr_list = enicpmd_set_mc_addr_list, 1167 .filter_ctrl = enicpmd_dev_filter_ctrl, 1168 .reta_query = enicpmd_dev_rss_reta_query, 1169 .reta_update = enicpmd_dev_rss_reta_update, 1170 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 1171 .rss_hash_update = enicpmd_dev_rss_hash_update, 1172 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 1173 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 1174 .fw_version_get = enicpmd_dev_fw_version_get, 1175 }; 1176 1177 static int enic_parse_zero_one(const char *key, 1178 const char *value, 1179 void *opaque) 1180 { 1181 struct enic *enic; 1182 bool b; 1183 1184 enic = (struct enic *)opaque; 1185 if (strcmp(value, "0") == 0) { 1186 b = false; 1187 } else if (strcmp(value, "1") == 0) { 1188 b = true; 1189 } else { 1190 dev_err(enic, "Invalid value for %s" 1191 ": expected=0|1 given=%s\n", key, value); 1192 return -EINVAL; 1193 } 1194 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 1195 enic->disable_overlay = b; 1196 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 1197 enic->enable_avx2_rx = b; 1198 if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0) 1199 enic->geneve_opt_request = b; 1200 return 0; 1201 } 1202 1203 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 1204 const char *value, 1205 void *opaque) 1206 { 1207 struct enic *enic; 1208 1209 enic = (struct enic *)opaque; 1210 if (strcmp(value, "trunk") == 0) { 1211 /* Trunk mode: always tag */ 1212 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 1213 } else if (strcmp(value, "untag") == 0) { 1214 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 1215 enic->ig_vlan_rewrite_mode = 1216 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 1217 } else if (strcmp(value, "priority") == 0) { 1218 /* 1219 * Priority-tag default VLAN mode: priority tag (VLAN header 1220 * with ID=0) if VLAN = default 1221 */ 1222 enic->ig_vlan_rewrite_mode = 1223 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 1224 } else if (strcmp(value, "pass") == 0) { 1225 /* Pass through mode: do not touch tags */ 1226 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1227 } else { 1228 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 1229 ": expected=trunk|untag|priority|pass given=%s\n", 1230 value); 1231 return -EINVAL; 1232 } 1233 return 0; 1234 } 1235 1236 static int enic_check_devargs(struct rte_eth_dev *dev) 1237 { 1238 static const char *const valid_keys[] = { 1239 ENIC_DEVARG_DISABLE_OVERLAY, 1240 ENIC_DEVARG_ENABLE_AVX2_RX, 1241 ENIC_DEVARG_GENEVE_OPT, 1242 ENIC_DEVARG_IG_VLAN_REWRITE, 1243 ENIC_DEVARG_REPRESENTOR, 1244 NULL}; 1245 struct enic *enic = pmd_priv(dev); 1246 struct rte_kvargs *kvlist; 1247 1248 ENICPMD_FUNC_TRACE(); 1249 1250 enic->disable_overlay = false; 1251 enic->enable_avx2_rx = false; 1252 enic->geneve_opt_request = false; 1253 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1254 if (!dev->device->devargs) 1255 return 0; 1256 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1257 if (!kvlist) 1258 return -EINVAL; 1259 if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 1260 enic_parse_zero_one, enic) < 0 || 1261 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 1262 enic_parse_zero_one, enic) < 0 || 1263 rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT, 1264 enic_parse_zero_one, enic) < 0 || 1265 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1266 enic_parse_ig_vlan_rewrite, enic) < 0) { 1267 rte_kvargs_free(kvlist); 1268 return -EINVAL; 1269 } 1270 rte_kvargs_free(kvlist); 1271 return 0; 1272 } 1273 1274 /* Initialize the driver for PF */ 1275 static int eth_enic_dev_init(struct rte_eth_dev *eth_dev, 1276 void *init_params __rte_unused) 1277 { 1278 struct rte_pci_device *pdev; 1279 struct rte_pci_addr *addr; 1280 struct enic *enic = pmd_priv(eth_dev); 1281 int err; 1282 1283 ENICPMD_FUNC_TRACE(); 1284 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1285 eth_dev->rx_queue_count = enicpmd_dev_rx_queue_count; 1286 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1287 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1288 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1289 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1290 enic_pick_tx_handler(eth_dev); 1291 enic_pick_rx_handler(eth_dev); 1292 return 0; 1293 } 1294 /* Only the primary sets up adapter and other data in shared memory */ 1295 enic->port_id = eth_dev->data->port_id; 1296 enic->rte_dev = eth_dev; 1297 enic->dev_data = eth_dev->data; 1298 1299 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1300 rte_eth_copy_pci_info(eth_dev, pdev); 1301 enic->pdev = pdev; 1302 addr = &pdev->addr; 1303 1304 snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x", 1305 addr->domain, addr->bus, addr->devid, addr->function); 1306 1307 err = enic_check_devargs(eth_dev); 1308 if (err) 1309 return err; 1310 err = enic_probe(enic); 1311 if (!err && enic->fm) { 1312 err = enic_fm_allocate_switch_domain(enic); 1313 if (err) 1314 ENICPMD_LOG(ERR, "failed to allocate switch domain id"); 1315 } 1316 return err; 1317 } 1318 1319 static int eth_enic_dev_uninit(struct rte_eth_dev *eth_dev) 1320 { 1321 struct enic *enic = pmd_priv(eth_dev); 1322 int err; 1323 1324 ENICPMD_FUNC_TRACE(); 1325 eth_dev->device = NULL; 1326 eth_dev->intr_handle = NULL; 1327 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1328 return 0; 1329 err = rte_eth_switch_domain_free(enic->switch_domain_id); 1330 if (err) 1331 ENICPMD_LOG(WARNING, "failed to free switch domain: %d", err); 1332 return 0; 1333 } 1334 1335 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1336 struct rte_pci_device *pci_dev) 1337 { 1338 char name[RTE_ETH_NAME_MAX_LEN]; 1339 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 1340 struct rte_eth_dev *pf_ethdev; 1341 struct enic *pf_enic; 1342 int i, retval; 1343 1344 ENICPMD_FUNC_TRACE(); 1345 if (pci_dev->device.devargs) { 1346 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1347 ð_da); 1348 if (retval) 1349 return retval; 1350 } 1351 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1352 sizeof(struct enic), 1353 eth_dev_pci_specific_init, pci_dev, 1354 eth_enic_dev_init, NULL); 1355 if (retval || eth_da.nb_representor_ports < 1) 1356 return retval; 1357 1358 /* Probe VF representor */ 1359 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1360 if (pf_ethdev == NULL) 1361 return -ENODEV; 1362 /* Representors require flowman */ 1363 pf_enic = pmd_priv(pf_ethdev); 1364 if (pf_enic->fm == NULL) { 1365 ENICPMD_LOG(ERR, "VF representors require flowman"); 1366 return -ENOTSUP; 1367 } 1368 /* 1369 * For now representors imply switchdev, as firmware does not support 1370 * legacy mode SR-IOV 1371 */ 1372 pf_enic->switchdev_mode = 1; 1373 /* Calculate max VF ID before initializing representor*/ 1374 pf_enic->max_vf_id = 0; 1375 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1376 pf_enic->max_vf_id = RTE_MAX(pf_enic->max_vf_id, 1377 eth_da.representor_ports[i]); 1378 } 1379 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1380 struct enic_vf_representor representor; 1381 1382 representor.vf_id = eth_da.representor_ports[i]; 1383 representor.switch_domain_id = 1384 pmd_priv(pf_ethdev)->switch_domain_id; 1385 representor.pf = pmd_priv(pf_ethdev); 1386 snprintf(name, sizeof(name), "net_%s_representor_%d", 1387 pci_dev->device.name, eth_da.representor_ports[i]); 1388 retval = rte_eth_dev_create(&pci_dev->device, name, 1389 sizeof(struct enic_vf_representor), NULL, NULL, 1390 enic_vf_representor_init, &representor); 1391 if (retval) { 1392 ENICPMD_LOG(ERR, "failed to create enic vf representor %s", 1393 name); 1394 return retval; 1395 } 1396 } 1397 return 0; 1398 } 1399 1400 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1401 { 1402 struct rte_eth_dev *ethdev; 1403 1404 ENICPMD_FUNC_TRACE(); 1405 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1406 if (!ethdev) 1407 return -ENODEV; 1408 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1409 return rte_eth_dev_destroy(ethdev, enic_vf_representor_uninit); 1410 else 1411 return rte_eth_dev_destroy(ethdev, eth_enic_dev_uninit); 1412 } 1413 1414 static struct rte_pci_driver rte_enic_pmd = { 1415 .id_table = pci_id_enic_map, 1416 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1417 .probe = eth_enic_pci_probe, 1418 .remove = eth_enic_pci_remove, 1419 }; 1420 1421 int dev_is_enic(struct rte_eth_dev *dev) 1422 { 1423 return dev->device->driver == &rte_enic_pmd.driver; 1424 } 1425 1426 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1427 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1428 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1429 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1430 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1431 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1432 ENIC_DEVARG_GENEVE_OPT "=0|1 " 1433 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1434