1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <dev_driver.h> 10 #include <rte_pci.h> 11 #include <bus_pci_driver.h> 12 #include <ethdev_driver.h> 13 #include <ethdev_pci.h> 14 #include <rte_geneve.h> 15 #include <rte_kvargs.h> 16 #include <rte_string_fns.h> 17 18 #include "vnic_intr.h" 19 #include "vnic_cq.h" 20 #include "vnic_wq.h" 21 #include "vnic_rq.h" 22 #include "vnic_enet.h" 23 #include "enic.h" 24 #include "enic_sriov.h" 25 26 /* 27 * The set of PCI devices this driver supports 28 */ 29 #define CISCO_PCI_VENDOR_ID 0x1137 30 static const struct rte_pci_id pci_id_enic_map[] = { 31 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)}, 32 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)}, 33 {.vendor_id = 0, /* sentinel */}, 34 }; 35 36 /* Supported link speeds of production VIC models */ 37 static const struct vic_speed_capa { 38 uint16_t sub_devid; 39 uint32_t capa; 40 } vic_speed_capa_map[] = { 41 { 0x0043, RTE_ETH_LINK_SPEED_10G }, /* VIC */ 42 { 0x0047, RTE_ETH_LINK_SPEED_10G }, /* P81E PCIe */ 43 { 0x0048, RTE_ETH_LINK_SPEED_10G }, /* M81KR Mezz */ 44 { 0x004f, RTE_ETH_LINK_SPEED_10G }, /* 1280 Mezz */ 45 { 0x0084, RTE_ETH_LINK_SPEED_10G }, /* 1240 MLOM */ 46 { 0x0085, RTE_ETH_LINK_SPEED_10G }, /* 1225 PCIe */ 47 { 0x00cd, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1285 PCIe */ 48 { 0x00ce, RTE_ETH_LINK_SPEED_10G }, /* 1225T PCIe */ 49 { 0x012a, RTE_ETH_LINK_SPEED_40G }, /* M4308 */ 50 { 0x012c, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1340 MLOM */ 51 { 0x012e, RTE_ETH_LINK_SPEED_10G }, /* 1227 PCIe */ 52 { 0x0137, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1380 Mezz */ 53 { 0x014d, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1385 PCIe */ 54 { 0x015d, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1387 MLOM */ 55 { 0x0215, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | 56 RTE_ETH_LINK_SPEED_40G }, /* 1440 Mezz */ 57 { 0x0216, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | 58 RTE_ETH_LINK_SPEED_40G }, /* 1480 MLOM */ 59 { 0x0217, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G }, /* 1455 PCIe */ 60 { 0x0218, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G }, /* 1457 MLOM */ 61 { 0x0219, RTE_ETH_LINK_SPEED_40G }, /* 1485 PCIe */ 62 { 0x021a, RTE_ETH_LINK_SPEED_40G }, /* 1487 MLOM */ 63 { 0x024a, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1495 PCIe */ 64 { 0x024b, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1497 MLOM */ 65 { 0x02af, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G }, /* 1467 MLOM */ 66 { 0x02b0, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1477 MLOM */ 67 { 0x02cf, RTE_ETH_LINK_SPEED_25G }, /* 14425 MLOM */ 68 { 0x02d0, RTE_ETH_LINK_SPEED_25G }, /* 14825 Mezz */ 69 { 0x02db, RTE_ETH_LINK_SPEED_100G }, /* 15231 MLOM */ 70 { 0x02dc, RTE_ETH_LINK_SPEED_10G }, /* 15411 MLOM */ 71 { 0x02dd, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | 72 RTE_ETH_LINK_SPEED_50G }, /* 15428 MLOM */ 73 { 0x02de, RTE_ETH_LINK_SPEED_25G }, /* 15420 MLOM */ 74 { 0x02e8, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G | 75 RTE_ETH_LINK_SPEED_200G}, /* 15238 MLOM */ 76 { 0x02e0, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | 77 RTE_ETH_LINK_SPEED_50G }, /* 15427 MLOM */ 78 { 0x02df, RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G }, /* 15230 MLOM */ 79 { 0x02e1, RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_50G }, /* 15422 Mezz */ 80 { 0x02e4, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G | 81 RTE_ETH_LINK_SPEED_200G }, /* 15235 PCIe */ 82 { 0x02f2, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | 83 RTE_ETH_LINK_SPEED_50G }, /* 15425 PCIe */ 84 { 0x02f3, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G | 85 RTE_ETH_LINK_SPEED_200G }, /* 15237 MLOM */ 86 { 0, 0 }, /* End marker */ 87 }; 88 89 #define ENIC_DEVARG_CQ64 "cq64" 90 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 91 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 92 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 93 #define ENIC_DEVARG_REPRESENTOR "representor" 94 95 RTE_LOG_REGISTER_DEFAULT(enic_pmd_logtype, INFO); 96 97 static int 98 enicpmd_dev_flow_ops_get(struct rte_eth_dev *dev, 99 const struct rte_flow_ops **ops) 100 { 101 struct enic *enic = pmd_priv(dev); 102 103 ENICPMD_FUNC_TRACE(); 104 105 if (enic->flow_filter_mode == FILTER_FLOWMAN) 106 *ops = &enic_fm_flow_ops; 107 else 108 *ops = &enic_flow_ops; 109 return 0; 110 } 111 112 static void enicpmd_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 113 { 114 void *txq = dev->data->tx_queues[qid]; 115 116 ENICPMD_FUNC_TRACE(); 117 118 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 119 return; 120 121 enic_free_wq(txq); 122 } 123 124 static int enicpmd_dev_setup_intr(struct enic *enic) 125 { 126 int ret; 127 unsigned int index; 128 129 ENICPMD_FUNC_TRACE(); 130 131 /* Are we done with the init of all the queues? */ 132 for (index = 0; index < enic->cq_count; index++) { 133 if (!enic->cq[index].ctrl) 134 break; 135 } 136 if (enic->cq_count != index) 137 return 0; 138 for (index = 0; index < enic->wq_count; index++) { 139 if (!enic->wq[index].ctrl) 140 break; 141 } 142 if (enic->wq_count != index) 143 return 0; 144 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 145 for (index = 0; index < enic->rq_count; index++) { 146 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 147 break; 148 } 149 if (enic->rq_count != index) 150 return 0; 151 152 ret = enic_alloc_intr_resources(enic); 153 if (ret) { 154 dev_err(enic, "alloc intr failed\n"); 155 return ret; 156 } 157 enic_init_vnic_resources(enic); 158 159 ret = enic_setup_finish(enic); 160 if (ret) 161 dev_err(enic, "setup could not be finished\n"); 162 163 return ret; 164 } 165 166 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 167 uint16_t queue_idx, 168 uint16_t nb_desc, 169 unsigned int socket_id, 170 const struct rte_eth_txconf *tx_conf) 171 { 172 int ret; 173 struct enic *enic = pmd_priv(eth_dev); 174 struct vnic_wq *wq; 175 176 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 177 return -E_RTE_SECONDARY; 178 179 ENICPMD_FUNC_TRACE(); 180 RTE_ASSERT(queue_idx < enic->conf_wq_count); 181 wq = &enic->wq[queue_idx]; 182 wq->offloads = tx_conf->offloads | 183 eth_dev->data->dev_conf.txmode.offloads; 184 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 185 186 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 187 if (ret) { 188 dev_err(enic, "error in allocating wq\n"); 189 return ret; 190 } 191 192 return enicpmd_dev_setup_intr(enic); 193 } 194 195 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 196 uint16_t queue_idx) 197 { 198 struct enic *enic = pmd_priv(eth_dev); 199 200 ENICPMD_FUNC_TRACE(); 201 202 enic_start_wq(enic, queue_idx); 203 204 return 0; 205 } 206 207 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 208 uint16_t queue_idx) 209 { 210 int ret; 211 struct enic *enic = pmd_priv(eth_dev); 212 213 ENICPMD_FUNC_TRACE(); 214 215 ret = enic_stop_wq(enic, queue_idx); 216 if (ret) 217 dev_err(enic, "error in stopping wq %d\n", queue_idx); 218 219 return ret; 220 } 221 222 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 223 uint16_t queue_idx) 224 { 225 struct enic *enic = pmd_priv(eth_dev); 226 227 ENICPMD_FUNC_TRACE(); 228 229 enic_start_rq(enic, queue_idx); 230 231 return 0; 232 } 233 234 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 235 uint16_t queue_idx) 236 { 237 int ret; 238 struct enic *enic = pmd_priv(eth_dev); 239 240 ENICPMD_FUNC_TRACE(); 241 242 ret = enic_stop_rq(enic, queue_idx); 243 if (ret) 244 dev_err(enic, "error in stopping rq %d\n", queue_idx); 245 246 return ret; 247 } 248 249 static void enicpmd_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 250 { 251 void *rxq = dev->data->rx_queues[qid]; 252 253 ENICPMD_FUNC_TRACE(); 254 255 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 256 return; 257 258 enic_free_rq(rxq); 259 } 260 261 static uint32_t enicpmd_dev_rx_queue_count(void *rx_queue) 262 { 263 struct enic *enic; 264 struct vnic_rq *sop_rq; 265 uint32_t queue_count = 0; 266 struct vnic_cq *cq; 267 uint32_t cq_tail; 268 uint16_t cq_idx; 269 270 sop_rq = rx_queue; 271 enic = vnic_dev_priv(sop_rq->vdev); 272 cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)]; 273 cq_idx = cq->to_clean; 274 275 cq_tail = ioread32(&cq->ctrl->cq_tail); 276 277 if (cq_tail < cq_idx) 278 cq_tail += cq->ring.desc_count; 279 280 queue_count = cq_tail - cq_idx; 281 282 return queue_count; 283 } 284 285 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 286 uint16_t queue_idx, 287 uint16_t nb_desc, 288 unsigned int socket_id, 289 const struct rte_eth_rxconf *rx_conf, 290 struct rte_mempool *mp) 291 { 292 int ret; 293 struct enic *enic = pmd_priv(eth_dev); 294 295 ENICPMD_FUNC_TRACE(); 296 297 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 298 return -E_RTE_SECONDARY; 299 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 300 eth_dev->data->rx_queues[queue_idx] = 301 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 302 303 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 304 rx_conf->rx_free_thresh); 305 if (ret) { 306 dev_err(enic, "error in allocating rq\n"); 307 return ret; 308 } 309 310 return enicpmd_dev_setup_intr(enic); 311 } 312 313 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 314 { 315 struct enic *enic = pmd_priv(eth_dev); 316 uint64_t offloads; 317 318 ENICPMD_FUNC_TRACE(); 319 320 offloads = eth_dev->data->dev_conf.rxmode.offloads; 321 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 322 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 323 enic->ig_vlan_strip_en = 1; 324 else 325 enic->ig_vlan_strip_en = 0; 326 } 327 328 return enic_set_vlan_strip(enic); 329 } 330 331 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 332 { 333 int ret; 334 int mask; 335 struct enic *enic = pmd_priv(eth_dev); 336 337 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 338 return -E_RTE_SECONDARY; 339 340 ENICPMD_FUNC_TRACE(); 341 ret = enic_set_vnic_res(enic); 342 if (ret) { 343 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 344 return ret; 345 } 346 347 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 348 eth_dev->data->dev_conf.rxmode.offloads |= 349 RTE_ETH_RX_OFFLOAD_RSS_HASH; 350 351 enic->mc_count = 0; 352 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 353 RTE_ETH_RX_OFFLOAD_CHECKSUM); 354 /* All vlan offload masks to apply the current settings */ 355 mask = RTE_ETH_VLAN_STRIP_MASK | 356 RTE_ETH_VLAN_FILTER_MASK | 357 RTE_ETH_VLAN_EXTEND_MASK; 358 ret = enicpmd_vlan_offload_set(eth_dev, mask); 359 if (ret) { 360 dev_err(enic, "Failed to configure VLAN offloads\n"); 361 return ret; 362 } 363 /* 364 * Initialize RSS with the default reta and key. If the user key is 365 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 366 * default key. 367 */ 368 return enic_init_rss_nic_cfg(enic); 369 } 370 371 /* Start the device. 372 * It returns 0 on success. 373 */ 374 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 375 { 376 struct enic *enic = pmd_priv(eth_dev); 377 378 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 379 return -E_RTE_SECONDARY; 380 381 ENICPMD_FUNC_TRACE(); 382 return enic_enable(enic); 383 } 384 385 /* 386 * Stop device: disable rx and tx functions to allow for reconfiguring. 387 */ 388 static int enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 389 { 390 struct rte_eth_link link; 391 struct enic *enic = pmd_priv(eth_dev); 392 uint16_t i; 393 394 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 395 return 0; 396 397 ENICPMD_FUNC_TRACE(); 398 enic_disable(enic); 399 400 memset(&link, 0, sizeof(link)); 401 rte_eth_linkstatus_set(eth_dev, &link); 402 403 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) 404 eth_dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 405 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) 406 eth_dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 407 408 return 0; 409 } 410 411 /* 412 * Stop device. 413 */ 414 static int enicpmd_dev_close(struct rte_eth_dev *eth_dev) 415 { 416 struct enic *enic = pmd_priv(eth_dev); 417 418 ENICPMD_FUNC_TRACE(); 419 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 420 return 0; 421 422 enic_remove(enic); 423 424 return 0; 425 } 426 427 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 428 __rte_unused int wait_to_complete) 429 { 430 ENICPMD_FUNC_TRACE(); 431 return enic_link_update(eth_dev); 432 } 433 434 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 435 struct rte_eth_stats *stats) 436 { 437 struct enic *enic = pmd_priv(eth_dev); 438 439 ENICPMD_FUNC_TRACE(); 440 return enic_dev_stats_get(enic, stats); 441 } 442 443 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 444 { 445 struct enic *enic = pmd_priv(eth_dev); 446 447 ENICPMD_FUNC_TRACE(); 448 return enic_dev_stats_clear(enic); 449 } 450 451 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) 452 { 453 const struct vic_speed_capa *m; 454 struct rte_pci_device *pdev; 455 uint16_t id; 456 457 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 458 id = pdev->id.subsystem_device_id; 459 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { 460 if (m->sub_devid == id) 461 return m->capa; 462 } 463 /* 1300 and later models are at least 40G */ 464 if (id >= 0x0100) 465 return RTE_ETH_LINK_SPEED_40G; 466 /* VFs have subsystem id 0, check device id */ 467 if (id == 0) { 468 /* Newer VF implies at least 40G model */ 469 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN) 470 return RTE_ETH_LINK_SPEED_40G; 471 } 472 return RTE_ETH_LINK_SPEED_10G; 473 } 474 475 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 476 struct rte_eth_dev_info *device_info) 477 { 478 struct enic *enic = pmd_priv(eth_dev); 479 480 ENICPMD_FUNC_TRACE(); 481 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 482 device_info->max_rx_queues = enic->conf_rq_count / 2; 483 device_info->max_tx_queues = enic->conf_wq_count; 484 device_info->min_rx_bufsize = ENIC_MIN_MTU; 485 /* "Max" mtu is not a typo. HW receives packet sizes up to the 486 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 487 * a hint to the driver to size receive buffers accordingly so that 488 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 489 * the user decide the buffer size via rxmode.mtu, basically 490 * ignoring vNIC mtu. 491 */ 492 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 493 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS; 494 device_info->min_mtu = ENIC_MIN_MTU; 495 device_info->max_mtu = enic->max_mtu; 496 device_info->rx_offload_capa = enic->rx_offload_capa; 497 device_info->tx_offload_capa = enic->tx_offload_capa; 498 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 499 device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 500 device_info->default_rxconf = (struct rte_eth_rxconf) { 501 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 502 }; 503 device_info->reta_size = enic->reta_size; 504 device_info->hash_key_size = enic->hash_key_size; 505 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 506 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 507 .nb_max = enic->config.rq_desc_count, 508 .nb_min = ENIC_MIN_RQ_DESCS, 509 .nb_align = ENIC_ALIGN_DESCS, 510 }; 511 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 512 .nb_max = enic->config.wq_desc_count, 513 .nb_min = ENIC_MIN_WQ_DESCS, 514 .nb_align = ENIC_ALIGN_DESCS, 515 .nb_seg_max = ENIC_TX_XMIT_MAX, 516 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 517 }; 518 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 519 .burst_size = ENIC_DEFAULT_RX_BURST, 520 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 521 ENIC_DEFAULT_RX_RING_SIZE), 522 .nb_queues = ENIC_DEFAULT_RX_RINGS, 523 }; 524 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 525 .burst_size = ENIC_DEFAULT_TX_BURST, 526 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 527 ENIC_DEFAULT_TX_RING_SIZE), 528 .nb_queues = ENIC_DEFAULT_TX_RINGS, 529 }; 530 device_info->speed_capa = speed_capa_from_pci_id(eth_dev); 531 532 return 0; 533 } 534 535 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev, 536 size_t *no_of_elements) 537 { 538 static const uint32_t ptypes[] = { 539 RTE_PTYPE_L2_ETHER, 540 RTE_PTYPE_L2_ETHER_VLAN, 541 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 542 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 543 RTE_PTYPE_L4_TCP, 544 RTE_PTYPE_L4_UDP, 545 RTE_PTYPE_L4_FRAG, 546 RTE_PTYPE_L4_NONFRAG, 547 }; 548 static const uint32_t ptypes_overlay[] = { 549 RTE_PTYPE_L2_ETHER, 550 RTE_PTYPE_L2_ETHER_VLAN, 551 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 552 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 553 RTE_PTYPE_L4_TCP, 554 RTE_PTYPE_L4_UDP, 555 RTE_PTYPE_L4_FRAG, 556 RTE_PTYPE_L4_NONFRAG, 557 RTE_PTYPE_TUNNEL_GRENAT, 558 RTE_PTYPE_INNER_L2_ETHER, 559 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 560 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 561 RTE_PTYPE_INNER_L4_TCP, 562 RTE_PTYPE_INNER_L4_UDP, 563 RTE_PTYPE_INNER_L4_FRAG, 564 RTE_PTYPE_INNER_L4_NONFRAG, 565 }; 566 567 if (dev->rx_pkt_burst != rte_eth_pkt_burst_dummy && 568 dev->rx_pkt_burst != NULL) { 569 struct enic *enic = pmd_priv(dev); 570 if (enic->overlay_offload) { 571 *no_of_elements = RTE_DIM(ptypes_overlay); 572 return ptypes_overlay; 573 } else { 574 *no_of_elements = RTE_DIM(ptypes); 575 return ptypes; 576 } 577 } 578 return NULL; 579 } 580 581 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 582 { 583 struct enic *enic = pmd_priv(eth_dev); 584 int ret; 585 586 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 587 return -E_RTE_SECONDARY; 588 589 ENICPMD_FUNC_TRACE(); 590 591 enic->promisc = 1; 592 ret = enic_add_packet_filter(enic); 593 if (ret != 0) 594 enic->promisc = 0; 595 596 return ret; 597 } 598 599 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 600 { 601 struct enic *enic = pmd_priv(eth_dev); 602 int ret; 603 604 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 605 return -E_RTE_SECONDARY; 606 607 ENICPMD_FUNC_TRACE(); 608 enic->promisc = 0; 609 ret = enic_add_packet_filter(enic); 610 if (ret != 0) 611 enic->promisc = 1; 612 613 return ret; 614 } 615 616 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 617 { 618 struct enic *enic = pmd_priv(eth_dev); 619 int ret; 620 621 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 622 return -E_RTE_SECONDARY; 623 624 ENICPMD_FUNC_TRACE(); 625 enic->allmulti = 1; 626 ret = enic_add_packet_filter(enic); 627 if (ret != 0) 628 enic->allmulti = 0; 629 630 return ret; 631 } 632 633 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 634 { 635 struct enic *enic = pmd_priv(eth_dev); 636 int ret; 637 638 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 639 return -E_RTE_SECONDARY; 640 641 ENICPMD_FUNC_TRACE(); 642 enic->allmulti = 0; 643 ret = enic_add_packet_filter(enic); 644 if (ret != 0) 645 enic->allmulti = 1; 646 647 return ret; 648 } 649 650 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 651 struct rte_ether_addr *mac_addr, 652 __rte_unused uint32_t index, __rte_unused uint32_t pool) 653 { 654 struct enic *enic = pmd_priv(eth_dev); 655 656 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 657 return -E_RTE_SECONDARY; 658 659 ENICPMD_FUNC_TRACE(); 660 return enic_set_mac_address(enic, mac_addr->addr_bytes); 661 } 662 663 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 664 { 665 struct enic *enic = pmd_priv(eth_dev); 666 667 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 668 return; 669 670 ENICPMD_FUNC_TRACE(); 671 if (enic_del_mac_address(enic, index)) 672 dev_err(enic, "del mac addr failed\n"); 673 } 674 675 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 676 struct rte_ether_addr *addr) 677 { 678 struct enic *enic = pmd_priv(eth_dev); 679 int ret; 680 681 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 682 return -E_RTE_SECONDARY; 683 684 ENICPMD_FUNC_TRACE(); 685 ret = enic_del_mac_address(enic, 0); 686 if (ret) 687 return ret; 688 return enic_set_mac_address(enic, addr->addr_bytes); 689 } 690 691 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add) 692 { 693 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 694 695 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr); 696 ENICPMD_LOG(DEBUG, " %s address %s", 697 add ? "add" : "remove", mac_str); 698 } 699 700 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev, 701 struct rte_ether_addr *mc_addr_set, 702 uint32_t nb_mc_addr) 703 { 704 struct enic *enic = pmd_priv(eth_dev); 705 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 706 struct rte_ether_addr *addr; 707 uint32_t i, j; 708 int ret; 709 710 ENICPMD_FUNC_TRACE(); 711 712 /* Validate the given addresses first */ 713 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) { 714 addr = &mc_addr_set[i]; 715 if (!rte_is_multicast_ether_addr(addr) || 716 rte_is_broadcast_ether_addr(addr)) { 717 rte_ether_format_addr(mac_str, 718 RTE_ETHER_ADDR_FMT_SIZE, addr); 719 ENICPMD_LOG(ERR, " invalid multicast address %s", 720 mac_str); 721 return -EINVAL; 722 } 723 } 724 725 /* Flush all if requested */ 726 if (nb_mc_addr == 0 || mc_addr_set == NULL) { 727 ENICPMD_LOG(DEBUG, " flush multicast addresses"); 728 for (i = 0; i < enic->mc_count; i++) { 729 addr = &enic->mc_addrs[i]; 730 debug_log_add_del_addr(addr, false); 731 ret = enic_dev_del_addr(enic, addr->addr_bytes); 732 if (ret) 733 return ret; 734 } 735 enic->mc_count = 0; 736 return 0; 737 } 738 739 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) { 740 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d", 741 ENIC_MULTICAST_PERFECT_FILTERS); 742 return -ENOSPC; 743 } 744 /* 745 * devcmd is slow, so apply the difference instead of flushing and 746 * adding everything. 747 * 1. Delete addresses on the NIC but not on the host 748 */ 749 for (i = 0; i < enic->mc_count; i++) { 750 addr = &enic->mc_addrs[i]; 751 for (j = 0; j < nb_mc_addr; j++) { 752 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) 753 break; 754 } 755 if (j < nb_mc_addr) 756 continue; 757 debug_log_add_del_addr(addr, false); 758 ret = enic_dev_del_addr(enic, addr->addr_bytes); 759 if (ret) 760 return ret; 761 } 762 /* 2. Add addresses on the host but not on the NIC */ 763 for (i = 0; i < nb_mc_addr; i++) { 764 addr = &mc_addr_set[i]; 765 for (j = 0; j < enic->mc_count; j++) { 766 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j])) 767 break; 768 } 769 if (j < enic->mc_count) 770 continue; 771 debug_log_add_del_addr(addr, true); 772 ret = enic_dev_add_addr(enic, addr->addr_bytes); 773 if (ret) 774 return ret; 775 } 776 /* Keep a copy so we can flush/apply later on.. */ 777 memcpy(enic->mc_addrs, mc_addr_set, 778 nb_mc_addr * sizeof(struct rte_ether_addr)); 779 enic->mc_count = nb_mc_addr; 780 return 0; 781 } 782 783 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 784 { 785 struct enic *enic = pmd_priv(eth_dev); 786 787 ENICPMD_FUNC_TRACE(); 788 return enic_set_mtu(enic, mtu); 789 } 790 791 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 792 struct rte_eth_rss_reta_entry64 793 *reta_conf, 794 uint16_t reta_size) 795 { 796 struct enic *enic = pmd_priv(dev); 797 uint16_t i, idx, shift; 798 799 ENICPMD_FUNC_TRACE(); 800 if (reta_size != ENIC_RSS_RETA_SIZE) { 801 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 802 reta_size, ENIC_RSS_RETA_SIZE); 803 return -EINVAL; 804 } 805 806 for (i = 0; i < reta_size; i++) { 807 idx = i / RTE_ETH_RETA_GROUP_SIZE; 808 shift = i % RTE_ETH_RETA_GROUP_SIZE; 809 if (reta_conf[idx].mask & (1ULL << shift)) 810 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 811 enic->rss_cpu.cpu[i / 4].b[i % 4]); 812 } 813 814 return 0; 815 } 816 817 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 818 struct rte_eth_rss_reta_entry64 819 *reta_conf, 820 uint16_t reta_size) 821 { 822 struct enic *enic = pmd_priv(dev); 823 union vnic_rss_cpu rss_cpu; 824 uint16_t i, idx, shift; 825 826 ENICPMD_FUNC_TRACE(); 827 if (reta_size != ENIC_RSS_RETA_SIZE) { 828 dev_err(enic, "reta_update: wrong reta_size. given=%u" 829 " expected=%u\n", 830 reta_size, ENIC_RSS_RETA_SIZE); 831 return -EINVAL; 832 } 833 /* 834 * Start with the current reta and modify it per reta_conf, as we 835 * need to push the entire reta even if we only modify one entry. 836 */ 837 rss_cpu = enic->rss_cpu; 838 for (i = 0; i < reta_size; i++) { 839 idx = i / RTE_ETH_RETA_GROUP_SIZE; 840 shift = i % RTE_ETH_RETA_GROUP_SIZE; 841 if (reta_conf[idx].mask & (1ULL << shift)) 842 rss_cpu.cpu[i / 4].b[i % 4] = 843 enic_rte_rq_idx_to_sop_idx( 844 reta_conf[idx].reta[shift]); 845 } 846 return enic_set_rss_reta(enic, &rss_cpu); 847 } 848 849 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 850 struct rte_eth_rss_conf *rss_conf) 851 { 852 struct enic *enic = pmd_priv(dev); 853 854 ENICPMD_FUNC_TRACE(); 855 return enic_set_rss_conf(enic, rss_conf); 856 } 857 858 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 859 struct rte_eth_rss_conf *rss_conf) 860 { 861 struct enic *enic = pmd_priv(dev); 862 863 ENICPMD_FUNC_TRACE(); 864 if (rss_conf == NULL) 865 return -EINVAL; 866 if (rss_conf->rss_key != NULL && 867 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 868 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 869 " expected=%u+\n", 870 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 871 return -EINVAL; 872 } 873 rss_conf->rss_hf = enic->rss_hf; 874 if (rss_conf->rss_key != NULL) { 875 int i; 876 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 877 rss_conf->rss_key[i] = 878 enic->rss_key.key[i / 10].b[i % 10]; 879 } 880 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 881 } 882 return 0; 883 } 884 885 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 886 uint16_t rx_queue_id, 887 struct rte_eth_rxq_info *qinfo) 888 { 889 struct enic *enic = pmd_priv(dev); 890 struct vnic_rq *rq_sop; 891 struct vnic_rq *rq_data; 892 struct rte_eth_rxconf *conf; 893 uint16_t sop_queue_idx; 894 uint16_t data_queue_idx; 895 896 ENICPMD_FUNC_TRACE(); 897 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 898 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic); 899 rq_sop = &enic->rq[sop_queue_idx]; 900 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 901 qinfo->mp = rq_sop->mp; 902 qinfo->scattered_rx = rq_sop->data_queue_enable; 903 qinfo->nb_desc = rq_sop->ring.desc_count; 904 if (qinfo->scattered_rx) 905 qinfo->nb_desc += rq_data->ring.desc_count; 906 conf = &qinfo->conf; 907 memset(conf, 0, sizeof(*conf)); 908 conf->rx_free_thresh = rq_sop->rx_free_thresh; 909 conf->rx_drop_en = 1; 910 /* 911 * Except VLAN stripping (port setting), all the checksum offloads 912 * are always enabled. 913 */ 914 conf->offloads = enic->rx_offload_capa; 915 if (!enic->ig_vlan_strip_en) 916 conf->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 917 /* rx_thresh and other fields are not applicable for enic */ 918 } 919 920 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 921 uint16_t tx_queue_id, 922 struct rte_eth_txq_info *qinfo) 923 { 924 struct enic *enic = pmd_priv(dev); 925 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 926 927 ENICPMD_FUNC_TRACE(); 928 qinfo->nb_desc = wq->ring.desc_count; 929 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 930 qinfo->conf.offloads = wq->offloads; 931 /* tx_thresh, and all the other fields are not applicable for enic */ 932 } 933 934 static int enicpmd_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 935 __rte_unused uint16_t queue_id, 936 struct rte_eth_burst_mode *mode) 937 { 938 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 939 struct enic *enic = pmd_priv(dev); 940 const char *info_str = NULL; 941 int ret = -EINVAL; 942 943 ENICPMD_FUNC_TRACE(); 944 if (enic->use_noscatter_vec_rx_handler) 945 info_str = "Vector AVX2 No Scatter"; 946 else if (pkt_burst == enic_noscatter_recv_pkts) 947 info_str = "Scalar No Scatter"; 948 else if (pkt_burst == enic_recv_pkts) 949 info_str = "Scalar"; 950 else if (pkt_burst == enic_recv_pkts_64) 951 info_str = "Scalar 64B Completion"; 952 if (info_str) { 953 strlcpy(mode->info, info_str, sizeof(mode->info)); 954 ret = 0; 955 } 956 return ret; 957 } 958 959 static int enicpmd_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 960 __rte_unused uint16_t queue_id, 961 struct rte_eth_burst_mode *mode) 962 { 963 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 964 const char *info_str = NULL; 965 int ret = -EINVAL; 966 967 ENICPMD_FUNC_TRACE(); 968 if (pkt_burst == enic_simple_xmit_pkts) 969 info_str = "Scalar Simplified"; 970 else if (pkt_burst == enic_xmit_pkts) 971 info_str = "Scalar"; 972 if (info_str) { 973 strlcpy(mode->info, info_str, sizeof(mode->info)); 974 ret = 0; 975 } 976 return ret; 977 } 978 979 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 980 uint16_t rx_queue_id) 981 { 982 struct enic *enic = pmd_priv(eth_dev); 983 984 ENICPMD_FUNC_TRACE(); 985 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 986 return 0; 987 } 988 989 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 990 uint16_t rx_queue_id) 991 { 992 struct enic *enic = pmd_priv(eth_dev); 993 994 ENICPMD_FUNC_TRACE(); 995 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 996 return 0; 997 } 998 999 static int udp_tunnel_common_check(struct enic *enic, 1000 struct rte_eth_udp_tunnel *tnl) 1001 { 1002 if (tnl->prot_type != RTE_ETH_TUNNEL_TYPE_VXLAN && 1003 tnl->prot_type != RTE_ETH_TUNNEL_TYPE_GENEVE) 1004 return -ENOTSUP; 1005 if (!enic->overlay_offload) { 1006 ENICPMD_LOG(DEBUG, " overlay offload is not supported"); 1007 return -ENOTSUP; 1008 } 1009 return 0; 1010 } 1011 1012 static int update_tunnel_port(struct enic *enic, uint16_t port, bool vxlan) 1013 { 1014 uint8_t cfg; 1015 1016 cfg = vxlan ? OVERLAY_CFG_VXLAN_PORT_UPDATE : 1017 OVERLAY_CFG_GENEVE_PORT_UPDATE; 1018 if (vnic_dev_overlay_offload_cfg(enic->vdev, cfg, port)) { 1019 ENICPMD_LOG(DEBUG, " failed to update tunnel port"); 1020 return -EINVAL; 1021 } 1022 ENICPMD_LOG(DEBUG, " updated %s port to %u", 1023 vxlan ? "vxlan" : "geneve", port); 1024 if (vxlan) 1025 enic->vxlan_port = port; 1026 else 1027 enic->geneve_port = port; 1028 return 0; 1029 } 1030 1031 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 1032 struct rte_eth_udp_tunnel *tnl) 1033 { 1034 struct enic *enic = pmd_priv(eth_dev); 1035 uint16_t port; 1036 bool vxlan; 1037 int ret; 1038 1039 ENICPMD_FUNC_TRACE(); 1040 ret = udp_tunnel_common_check(enic, tnl); 1041 if (ret) 1042 return ret; 1043 vxlan = (tnl->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN); 1044 if (vxlan) 1045 port = enic->vxlan_port; 1046 else 1047 port = enic->geneve_port; 1048 /* 1049 * The NIC has 1 configurable port number per tunnel type. 1050 * "Adding" a new port number replaces it. 1051 */ 1052 if (tnl->udp_port == port || tnl->udp_port == 0) { 1053 ENICPMD_LOG(DEBUG, " %u is already configured or invalid", 1054 tnl->udp_port); 1055 return -EINVAL; 1056 } 1057 return update_tunnel_port(enic, tnl->udp_port, vxlan); 1058 } 1059 1060 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 1061 struct rte_eth_udp_tunnel *tnl) 1062 { 1063 struct enic *enic = pmd_priv(eth_dev); 1064 uint16_t port; 1065 bool vxlan; 1066 int ret; 1067 1068 ENICPMD_FUNC_TRACE(); 1069 ret = udp_tunnel_common_check(enic, tnl); 1070 if (ret) 1071 return ret; 1072 vxlan = (tnl->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN); 1073 if (vxlan) 1074 port = enic->vxlan_port; 1075 else 1076 port = enic->geneve_port; 1077 /* 1078 * Clear the previously set port number and restore the 1079 * hardware default port number. Some drivers disable VXLAN 1080 * offloads when there are no configured port numbers. But 1081 * enic does not do that as VXLAN is part of overlay offload, 1082 * which is tied to inner RSS and TSO. 1083 */ 1084 if (tnl->udp_port != port) { 1085 ENICPMD_LOG(DEBUG, " %u is not a configured tunnel port", 1086 tnl->udp_port); 1087 return -EINVAL; 1088 } 1089 port = vxlan ? RTE_VXLAN_DEFAULT_PORT : RTE_GENEVE_DEFAULT_PORT; 1090 return update_tunnel_port(enic, port, vxlan); 1091 } 1092 1093 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev, 1094 char *fw_version, size_t fw_size) 1095 { 1096 struct vnic_devcmd_fw_info *info; 1097 struct enic *enic; 1098 int ret; 1099 1100 ENICPMD_FUNC_TRACE(); 1101 1102 enic = pmd_priv(eth_dev); 1103 ret = vnic_dev_fw_info(enic->vdev, &info); 1104 if (ret) 1105 return ret; 1106 ret = snprintf(fw_version, fw_size, "%s %s", 1107 info->fw_version, info->fw_build); 1108 if (ret < 0) 1109 return -EINVAL; 1110 1111 ret += 1; /* add the size of '\0' */ 1112 if (fw_size < (size_t)ret) 1113 return ret; 1114 else 1115 return 0; 1116 } 1117 1118 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 1119 .dev_configure = enicpmd_dev_configure, 1120 .dev_start = enicpmd_dev_start, 1121 .dev_stop = enicpmd_dev_stop, 1122 .dev_set_link_up = NULL, 1123 .dev_set_link_down = NULL, 1124 .dev_close = enicpmd_dev_close, 1125 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 1126 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 1127 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 1128 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 1129 .link_update = enicpmd_dev_link_update, 1130 .stats_get = enicpmd_dev_stats_get, 1131 .stats_reset = enicpmd_dev_stats_reset, 1132 .queue_stats_mapping_set = NULL, 1133 .dev_infos_get = enicpmd_dev_info_get, 1134 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 1135 .mtu_set = enicpmd_mtu_set, 1136 .vlan_filter_set = NULL, 1137 .vlan_tpid_set = NULL, 1138 .vlan_offload_set = enicpmd_vlan_offload_set, 1139 .vlan_strip_queue_set = NULL, 1140 .rx_queue_start = enicpmd_dev_rx_queue_start, 1141 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 1142 .tx_queue_start = enicpmd_dev_tx_queue_start, 1143 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 1144 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 1145 .rx_queue_release = enicpmd_dev_rx_queue_release, 1146 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 1147 .tx_queue_release = enicpmd_dev_tx_queue_release, 1148 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 1149 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 1150 .rxq_info_get = enicpmd_dev_rxq_info_get, 1151 .txq_info_get = enicpmd_dev_txq_info_get, 1152 .rx_burst_mode_get = enicpmd_dev_rx_burst_mode_get, 1153 .tx_burst_mode_get = enicpmd_dev_tx_burst_mode_get, 1154 .dev_led_on = NULL, 1155 .dev_led_off = NULL, 1156 .flow_ctrl_get = NULL, 1157 .flow_ctrl_set = NULL, 1158 .priority_flow_ctrl_set = NULL, 1159 .mac_addr_add = enicpmd_add_mac_addr, 1160 .mac_addr_remove = enicpmd_remove_mac_addr, 1161 .mac_addr_set = enicpmd_set_mac_addr, 1162 .set_mc_addr_list = enicpmd_set_mc_addr_list, 1163 .flow_ops_get = enicpmd_dev_flow_ops_get, 1164 .reta_query = enicpmd_dev_rss_reta_query, 1165 .reta_update = enicpmd_dev_rss_reta_update, 1166 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 1167 .rss_hash_update = enicpmd_dev_rss_hash_update, 1168 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 1169 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 1170 .fw_version_get = enicpmd_dev_fw_version_get, 1171 }; 1172 1173 static int enic_parse_zero_one(const char *key, 1174 const char *value, 1175 void *opaque) 1176 { 1177 struct enic *enic; 1178 bool b; 1179 1180 enic = (struct enic *)opaque; 1181 if (strcmp(value, "0") == 0) { 1182 b = false; 1183 } else if (strcmp(value, "1") == 0) { 1184 b = true; 1185 } else { 1186 dev_err(enic, "Invalid value for %s" 1187 ": expected=0|1 given=%s\n", key, value); 1188 return -EINVAL; 1189 } 1190 if (strcmp(key, ENIC_DEVARG_CQ64) == 0) 1191 enic->cq64_request = b; 1192 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 1193 enic->disable_overlay = b; 1194 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 1195 enic->enable_avx2_rx = b; 1196 return 0; 1197 } 1198 1199 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 1200 const char *value, 1201 void *opaque) 1202 { 1203 struct enic *enic; 1204 1205 enic = (struct enic *)opaque; 1206 if (strcmp(value, "trunk") == 0) { 1207 /* Trunk mode: always tag */ 1208 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 1209 } else if (strcmp(value, "untag") == 0) { 1210 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 1211 enic->ig_vlan_rewrite_mode = 1212 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 1213 } else if (strcmp(value, "priority") == 0) { 1214 /* 1215 * Priority-tag default VLAN mode: priority tag (VLAN header 1216 * with ID=0) if VLAN = default 1217 */ 1218 enic->ig_vlan_rewrite_mode = 1219 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 1220 } else if (strcmp(value, "pass") == 0) { 1221 /* Pass through mode: do not touch tags */ 1222 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1223 } else { 1224 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 1225 ": expected=trunk|untag|priority|pass given=%s\n", 1226 value); 1227 return -EINVAL; 1228 } 1229 return 0; 1230 } 1231 1232 static int enic_check_devargs(struct rte_eth_dev *dev) 1233 { 1234 static const char *const valid_keys[] = { 1235 ENIC_DEVARG_CQ64, 1236 ENIC_DEVARG_DISABLE_OVERLAY, 1237 ENIC_DEVARG_ENABLE_AVX2_RX, 1238 ENIC_DEVARG_IG_VLAN_REWRITE, 1239 ENIC_DEVARG_REPRESENTOR, 1240 NULL}; 1241 struct enic *enic = pmd_priv(dev); 1242 struct rte_kvargs *kvlist; 1243 1244 ENICPMD_FUNC_TRACE(); 1245 1246 enic->cq64_request = true; /* Use 64B entry if available */ 1247 enic->disable_overlay = false; 1248 enic->enable_avx2_rx = false; 1249 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1250 if (!dev->device->devargs) 1251 return 0; 1252 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1253 if (!kvlist) 1254 return -EINVAL; 1255 if (rte_kvargs_process(kvlist, ENIC_DEVARG_CQ64, 1256 enic_parse_zero_one, enic) < 0 || 1257 rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 1258 enic_parse_zero_one, enic) < 0 || 1259 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 1260 enic_parse_zero_one, enic) < 0 || 1261 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1262 enic_parse_ig_vlan_rewrite, enic) < 0) { 1263 rte_kvargs_free(kvlist); 1264 return -EINVAL; 1265 } 1266 rte_kvargs_free(kvlist); 1267 return 0; 1268 } 1269 1270 /* Initialize the driver for PF */ 1271 static int eth_enic_dev_init(struct rte_eth_dev *eth_dev, 1272 void *init_params __rte_unused) 1273 { 1274 struct rte_pci_device *pdev; 1275 struct rte_pci_addr *addr; 1276 struct enic *enic = pmd_priv(eth_dev); 1277 int err; 1278 1279 ENICPMD_FUNC_TRACE(); 1280 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1281 eth_dev->rx_queue_count = enicpmd_dev_rx_queue_count; 1282 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1283 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1284 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1285 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1286 enic_pick_tx_handler(eth_dev); 1287 enic_pick_rx_handler(eth_dev); 1288 return 0; 1289 } 1290 /* Only the primary sets up adapter and other data in shared memory */ 1291 enic->port_id = eth_dev->data->port_id; 1292 enic->rte_dev = eth_dev; 1293 enic->dev_data = eth_dev->data; 1294 1295 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1296 rte_eth_copy_pci_info(eth_dev, pdev); 1297 enic->pdev = pdev; 1298 addr = &pdev->addr; 1299 1300 snprintf(enic->bdf_name, PCI_PRI_STR_SIZE, PCI_PRI_FMT, 1301 addr->domain, addr->bus, addr->devid, addr->function); 1302 1303 err = enic_check_devargs(eth_dev); 1304 if (err) 1305 return err; 1306 err = enic_probe(enic); 1307 if (!err && enic->fm) { 1308 err = enic_fm_allocate_switch_domain(enic); 1309 if (err) 1310 ENICPMD_LOG(ERR, "failed to allocate switch domain id"); 1311 } 1312 return err; 1313 } 1314 1315 static int eth_enic_dev_uninit(struct rte_eth_dev *eth_dev) 1316 { 1317 struct enic *enic = pmd_priv(eth_dev); 1318 int err; 1319 1320 ENICPMD_FUNC_TRACE(); 1321 eth_dev->device = NULL; 1322 eth_dev->intr_handle = NULL; 1323 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1324 return 0; 1325 err = rte_eth_switch_domain_free(enic->switch_domain_id); 1326 if (err) 1327 ENICPMD_LOG(WARNING, "failed to free switch domain: %d", err); 1328 return 0; 1329 } 1330 1331 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1332 struct rte_pci_device *pci_dev) 1333 { 1334 char name[RTE_ETH_NAME_MAX_LEN]; 1335 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 1336 struct rte_eth_dev *pf_ethdev; 1337 struct enic *pf_enic; 1338 int i, retval; 1339 1340 ENICPMD_FUNC_TRACE(); 1341 if (pci_dev->device.devargs) { 1342 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1343 ð_da, 1); 1344 if (retval < 0) 1345 return retval; 1346 } 1347 if (eth_da.nb_representor_ports > 0 && 1348 eth_da.type != RTE_ETH_REPRESENTOR_VF) { 1349 ENICPMD_LOG(ERR, "unsupported representor type: %s", 1350 pci_dev->device.devargs->args); 1351 return -ENOTSUP; 1352 } 1353 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1354 sizeof(struct enic), 1355 eth_dev_pci_specific_init, pci_dev, 1356 eth_enic_dev_init, NULL); 1357 if (retval || eth_da.nb_representor_ports < 1) 1358 return retval; 1359 1360 /* Probe VF representor */ 1361 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1362 if (pf_ethdev == NULL) 1363 return -ENODEV; 1364 /* Representors require flowman */ 1365 pf_enic = pmd_priv(pf_ethdev); 1366 if (pf_enic->fm == NULL) { 1367 ENICPMD_LOG(ERR, "VF representors require flowman"); 1368 return -ENOTSUP; 1369 } 1370 /* 1371 * For now representors imply switchdev, as firmware does not support 1372 * legacy mode SR-IOV 1373 */ 1374 pf_enic->switchdev_mode = 1; 1375 /* Calculate max VF ID before initializing representor*/ 1376 pf_enic->max_vf_id = 0; 1377 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1378 pf_enic->max_vf_id = RTE_MAX(pf_enic->max_vf_id, 1379 eth_da.representor_ports[i]); 1380 } 1381 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1382 struct enic_vf_representor representor; 1383 1384 representor.vf_id = eth_da.representor_ports[i]; 1385 representor.switch_domain_id = 1386 pmd_priv(pf_ethdev)->switch_domain_id; 1387 representor.pf = pmd_priv(pf_ethdev); 1388 snprintf(name, sizeof(name), "net_%s_representor_%d", 1389 pci_dev->device.name, eth_da.representor_ports[i]); 1390 retval = rte_eth_dev_create(&pci_dev->device, name, 1391 sizeof(struct enic_vf_representor), NULL, NULL, 1392 enic_vf_representor_init, &representor); 1393 if (retval) { 1394 ENICPMD_LOG(ERR, "failed to create enic vf representor %s", 1395 name); 1396 return retval; 1397 } 1398 } 1399 return 0; 1400 } 1401 1402 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1403 { 1404 struct rte_eth_dev *ethdev; 1405 1406 ENICPMD_FUNC_TRACE(); 1407 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1408 if (!ethdev) 1409 return -ENODEV; 1410 if (rte_eth_dev_is_repr(ethdev)) 1411 return rte_eth_dev_destroy(ethdev, enic_vf_representor_uninit); 1412 else 1413 return rte_eth_dev_destroy(ethdev, eth_enic_dev_uninit); 1414 } 1415 1416 static struct rte_pci_driver rte_enic_pmd = { 1417 .id_table = pci_id_enic_map, 1418 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1419 .probe = eth_enic_pci_probe, 1420 .remove = eth_enic_pci_remove, 1421 }; 1422 1423 int dev_is_enic(struct rte_eth_dev *dev) 1424 { 1425 return dev->device->driver == &rte_enic_pmd.driver; 1426 } 1427 1428 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1429 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1430 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1431 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1432 ENIC_DEVARG_CQ64 "=0|1" 1433 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1434 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1435 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1436