1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <rte_dev.h> 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_ethdev_pci.h> 14 #include <rte_kvargs.h> 15 #include <rte_string_fns.h> 16 17 #include "vnic_intr.h" 18 #include "vnic_cq.h" 19 #include "vnic_wq.h" 20 #include "vnic_rq.h" 21 #include "vnic_enet.h" 22 #include "enic.h" 23 24 int enic_pmd_logtype; 25 26 /* 27 * The set of PCI devices this driver supports 28 */ 29 #define CISCO_PCI_VENDOR_ID 0x1137 30 static const struct rte_pci_id pci_id_enic_map[] = { 31 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)}, 32 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)}, 33 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)}, 34 {.vendor_id = 0, /* sentinel */}, 35 }; 36 37 /* Supported link speeds of production VIC models */ 38 static const struct vic_speed_capa { 39 uint16_t sub_devid; 40 uint32_t capa; 41 } vic_speed_capa_map[] = { 42 { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */ 43 { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */ 44 { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */ 45 { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */ 46 { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */ 47 { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */ 48 { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */ 49 { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */ 50 { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */ 51 { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */ 52 { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */ 53 { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */ 54 { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */ 55 { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */ 56 { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 57 ETH_LINK_SPEED_40G }, /* 1440 Mezz */ 58 { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 59 ETH_LINK_SPEED_40G }, /* 1480 MLOM */ 60 { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */ 61 { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */ 62 { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */ 63 { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */ 64 { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */ 65 { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */ 66 { 0, 0 }, /* End marker */ 67 }; 68 69 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 70 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 71 #define ENIC_DEVARG_GENEVE_OPT "geneve-opt" 72 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 73 74 RTE_INIT(enicpmd_init_log) 75 { 76 enic_pmd_logtype = rte_log_register("pmd.net.enic"); 77 if (enic_pmd_logtype >= 0) 78 rte_log_set_level(enic_pmd_logtype, RTE_LOG_INFO); 79 } 80 81 static int 82 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev, 83 enum rte_filter_op filter_op, void *arg) 84 { 85 struct enic *enic = pmd_priv(eth_dev); 86 int ret = 0; 87 88 ENICPMD_FUNC_TRACE(); 89 if (filter_op == RTE_ETH_FILTER_NOP) 90 return 0; 91 92 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 93 return -EINVAL; 94 95 switch (filter_op) { 96 case RTE_ETH_FILTER_ADD: 97 case RTE_ETH_FILTER_UPDATE: 98 ret = enic_fdir_add_fltr(enic, 99 (struct rte_eth_fdir_filter *)arg); 100 break; 101 102 case RTE_ETH_FILTER_DELETE: 103 ret = enic_fdir_del_fltr(enic, 104 (struct rte_eth_fdir_filter *)arg); 105 break; 106 107 case RTE_ETH_FILTER_STATS: 108 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg); 109 break; 110 111 case RTE_ETH_FILTER_FLUSH: 112 dev_warning(enic, "unsupported operation %u", filter_op); 113 ret = -ENOTSUP; 114 break; 115 case RTE_ETH_FILTER_INFO: 116 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg); 117 break; 118 default: 119 dev_err(enic, "unknown operation %u", filter_op); 120 ret = -EINVAL; 121 break; 122 } 123 return ret; 124 } 125 126 static int 127 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev, 128 enum rte_filter_type filter_type, 129 enum rte_filter_op filter_op, 130 void *arg) 131 { 132 struct enic *enic = pmd_priv(dev); 133 int ret = 0; 134 135 ENICPMD_FUNC_TRACE(); 136 137 /* 138 * Currently, when Geneve with options offload is enabled, host 139 * cannot insert match-action rules. 140 */ 141 if (enic->geneve_opt_enabled) 142 return -ENOTSUP; 143 switch (filter_type) { 144 case RTE_ETH_FILTER_GENERIC: 145 if (filter_op != RTE_ETH_FILTER_GET) 146 return -EINVAL; 147 if (enic->flow_filter_mode == FILTER_FLOWMAN) 148 *(const void **)arg = &enic_fm_flow_ops; 149 else 150 *(const void **)arg = &enic_flow_ops; 151 break; 152 case RTE_ETH_FILTER_FDIR: 153 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg); 154 break; 155 default: 156 dev_warning(enic, "Filter type (%d) not supported", 157 filter_type); 158 ret = -EINVAL; 159 break; 160 } 161 162 return ret; 163 } 164 165 static void enicpmd_dev_tx_queue_release(void *txq) 166 { 167 ENICPMD_FUNC_TRACE(); 168 169 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 170 return; 171 172 enic_free_wq(txq); 173 } 174 175 static int enicpmd_dev_setup_intr(struct enic *enic) 176 { 177 int ret; 178 unsigned int index; 179 180 ENICPMD_FUNC_TRACE(); 181 182 /* Are we done with the init of all the queues? */ 183 for (index = 0; index < enic->cq_count; index++) { 184 if (!enic->cq[index].ctrl) 185 break; 186 } 187 if (enic->cq_count != index) 188 return 0; 189 for (index = 0; index < enic->wq_count; index++) { 190 if (!enic->wq[index].ctrl) 191 break; 192 } 193 if (enic->wq_count != index) 194 return 0; 195 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 196 for (index = 0; index < enic->rq_count; index++) { 197 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 198 break; 199 } 200 if (enic->rq_count != index) 201 return 0; 202 203 ret = enic_alloc_intr_resources(enic); 204 if (ret) { 205 dev_err(enic, "alloc intr failed\n"); 206 return ret; 207 } 208 enic_init_vnic_resources(enic); 209 210 ret = enic_setup_finish(enic); 211 if (ret) 212 dev_err(enic, "setup could not be finished\n"); 213 214 return ret; 215 } 216 217 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 218 uint16_t queue_idx, 219 uint16_t nb_desc, 220 unsigned int socket_id, 221 const struct rte_eth_txconf *tx_conf) 222 { 223 int ret; 224 struct enic *enic = pmd_priv(eth_dev); 225 struct vnic_wq *wq; 226 227 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 228 return -E_RTE_SECONDARY; 229 230 ENICPMD_FUNC_TRACE(); 231 RTE_ASSERT(queue_idx < enic->conf_wq_count); 232 wq = &enic->wq[queue_idx]; 233 wq->offloads = tx_conf->offloads | 234 eth_dev->data->dev_conf.txmode.offloads; 235 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 236 237 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 238 if (ret) { 239 dev_err(enic, "error in allocating wq\n"); 240 return ret; 241 } 242 243 return enicpmd_dev_setup_intr(enic); 244 } 245 246 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 247 uint16_t queue_idx) 248 { 249 struct enic *enic = pmd_priv(eth_dev); 250 251 ENICPMD_FUNC_TRACE(); 252 253 enic_start_wq(enic, queue_idx); 254 255 return 0; 256 } 257 258 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 259 uint16_t queue_idx) 260 { 261 int ret; 262 struct enic *enic = pmd_priv(eth_dev); 263 264 ENICPMD_FUNC_TRACE(); 265 266 ret = enic_stop_wq(enic, queue_idx); 267 if (ret) 268 dev_err(enic, "error in stopping wq %d\n", queue_idx); 269 270 return ret; 271 } 272 273 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 274 uint16_t queue_idx) 275 { 276 struct enic *enic = pmd_priv(eth_dev); 277 278 ENICPMD_FUNC_TRACE(); 279 280 enic_start_rq(enic, queue_idx); 281 282 return 0; 283 } 284 285 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 286 uint16_t queue_idx) 287 { 288 int ret; 289 struct enic *enic = pmd_priv(eth_dev); 290 291 ENICPMD_FUNC_TRACE(); 292 293 ret = enic_stop_rq(enic, queue_idx); 294 if (ret) 295 dev_err(enic, "error in stopping rq %d\n", queue_idx); 296 297 return ret; 298 } 299 300 static void enicpmd_dev_rx_queue_release(void *rxq) 301 { 302 ENICPMD_FUNC_TRACE(); 303 304 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 305 return; 306 307 enic_free_rq(rxq); 308 } 309 310 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev, 311 uint16_t rx_queue_id) 312 { 313 struct enic *enic = pmd_priv(dev); 314 uint32_t queue_count = 0; 315 struct vnic_cq *cq; 316 uint32_t cq_tail; 317 uint16_t cq_idx; 318 int rq_num; 319 320 rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 321 cq = &enic->cq[enic_cq_rq(enic, rq_num)]; 322 cq_idx = cq->to_clean; 323 324 cq_tail = ioread32(&cq->ctrl->cq_tail); 325 326 if (cq_tail < cq_idx) 327 cq_tail += cq->ring.desc_count; 328 329 queue_count = cq_tail - cq_idx; 330 331 return queue_count; 332 } 333 334 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 335 uint16_t queue_idx, 336 uint16_t nb_desc, 337 unsigned int socket_id, 338 const struct rte_eth_rxconf *rx_conf, 339 struct rte_mempool *mp) 340 { 341 int ret; 342 struct enic *enic = pmd_priv(eth_dev); 343 344 ENICPMD_FUNC_TRACE(); 345 346 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 347 return -E_RTE_SECONDARY; 348 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 349 eth_dev->data->rx_queues[queue_idx] = 350 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 351 352 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 353 rx_conf->rx_free_thresh); 354 if (ret) { 355 dev_err(enic, "error in allocating rq\n"); 356 return ret; 357 } 358 359 return enicpmd_dev_setup_intr(enic); 360 } 361 362 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 363 { 364 struct enic *enic = pmd_priv(eth_dev); 365 uint64_t offloads; 366 367 ENICPMD_FUNC_TRACE(); 368 369 offloads = eth_dev->data->dev_conf.rxmode.offloads; 370 if (mask & ETH_VLAN_STRIP_MASK) { 371 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 372 enic->ig_vlan_strip_en = 1; 373 else 374 enic->ig_vlan_strip_en = 0; 375 } 376 377 if ((mask & ETH_VLAN_FILTER_MASK) && 378 (offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 379 dev_warning(enic, 380 "Configuration of VLAN filter is not supported\n"); 381 } 382 383 if ((mask & ETH_VLAN_EXTEND_MASK) && 384 (offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)) { 385 dev_warning(enic, 386 "Configuration of extended VLAN is not supported\n"); 387 } 388 389 return enic_set_vlan_strip(enic); 390 } 391 392 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 393 { 394 int ret; 395 int mask; 396 struct enic *enic = pmd_priv(eth_dev); 397 398 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 399 return -E_RTE_SECONDARY; 400 401 ENICPMD_FUNC_TRACE(); 402 ret = enic_set_vnic_res(enic); 403 if (ret) { 404 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 405 return ret; 406 } 407 408 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 409 eth_dev->data->dev_conf.rxmode.offloads |= 410 DEV_RX_OFFLOAD_RSS_HASH; 411 412 enic->mc_count = 0; 413 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 414 DEV_RX_OFFLOAD_CHECKSUM); 415 /* All vlan offload masks to apply the current settings */ 416 mask = ETH_VLAN_STRIP_MASK | 417 ETH_VLAN_FILTER_MASK | 418 ETH_VLAN_EXTEND_MASK; 419 ret = enicpmd_vlan_offload_set(eth_dev, mask); 420 if (ret) { 421 dev_err(enic, "Failed to configure VLAN offloads\n"); 422 return ret; 423 } 424 /* 425 * Initialize RSS with the default reta and key. If the user key is 426 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 427 * default key. 428 */ 429 return enic_init_rss_nic_cfg(enic); 430 } 431 432 /* Start the device. 433 * It returns 0 on success. 434 */ 435 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 436 { 437 struct enic *enic = pmd_priv(eth_dev); 438 439 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 440 return -E_RTE_SECONDARY; 441 442 ENICPMD_FUNC_TRACE(); 443 return enic_enable(enic); 444 } 445 446 /* 447 * Stop device: disable rx and tx functions to allow for reconfiguring. 448 */ 449 static void enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 450 { 451 struct rte_eth_link link; 452 struct enic *enic = pmd_priv(eth_dev); 453 454 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 455 return; 456 457 ENICPMD_FUNC_TRACE(); 458 enic_disable(enic); 459 460 memset(&link, 0, sizeof(link)); 461 rte_eth_linkstatus_set(eth_dev, &link); 462 } 463 464 /* 465 * Stop device. 466 */ 467 static void enicpmd_dev_close(struct rte_eth_dev *eth_dev) 468 { 469 struct enic *enic = pmd_priv(eth_dev); 470 471 ENICPMD_FUNC_TRACE(); 472 enic_remove(enic); 473 } 474 475 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 476 __rte_unused int wait_to_complete) 477 { 478 ENICPMD_FUNC_TRACE(); 479 return enic_link_update(eth_dev); 480 } 481 482 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 483 struct rte_eth_stats *stats) 484 { 485 struct enic *enic = pmd_priv(eth_dev); 486 487 ENICPMD_FUNC_TRACE(); 488 return enic_dev_stats_get(enic, stats); 489 } 490 491 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 492 { 493 struct enic *enic = pmd_priv(eth_dev); 494 495 ENICPMD_FUNC_TRACE(); 496 return enic_dev_stats_clear(enic); 497 } 498 499 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) 500 { 501 const struct vic_speed_capa *m; 502 struct rte_pci_device *pdev; 503 uint16_t id; 504 505 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 506 id = pdev->id.subsystem_device_id; 507 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { 508 if (m->sub_devid == id) 509 return m->capa; 510 } 511 /* 1300 and later models are at least 40G */ 512 if (id >= 0x0100) 513 return ETH_LINK_SPEED_40G; 514 /* VFs have subsystem id 0, check device id */ 515 if (id == 0) { 516 /* Newer VF implies at least 40G model */ 517 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN) 518 return ETH_LINK_SPEED_40G; 519 } 520 return ETH_LINK_SPEED_10G; 521 } 522 523 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 524 struct rte_eth_dev_info *device_info) 525 { 526 struct enic *enic = pmd_priv(eth_dev); 527 528 ENICPMD_FUNC_TRACE(); 529 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 530 device_info->max_rx_queues = enic->conf_rq_count / 2; 531 device_info->max_tx_queues = enic->conf_wq_count; 532 device_info->min_rx_bufsize = ENIC_MIN_MTU; 533 /* "Max" mtu is not a typo. HW receives packet sizes up to the 534 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 535 * a hint to the driver to size receive buffers accordingly so that 536 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 537 * the user decide the buffer size via rxmode.max_rx_pkt_len, basically 538 * ignoring vNIC mtu. 539 */ 540 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 541 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS; 542 device_info->min_mtu = ENIC_MIN_MTU; 543 device_info->max_mtu = enic->max_mtu; 544 device_info->rx_offload_capa = enic->rx_offload_capa; 545 device_info->tx_offload_capa = enic->tx_offload_capa; 546 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 547 device_info->default_rxconf = (struct rte_eth_rxconf) { 548 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 549 }; 550 device_info->reta_size = enic->reta_size; 551 device_info->hash_key_size = enic->hash_key_size; 552 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 553 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 554 .nb_max = enic->config.rq_desc_count, 555 .nb_min = ENIC_MIN_RQ_DESCS, 556 .nb_align = ENIC_ALIGN_DESCS, 557 }; 558 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 559 .nb_max = enic->config.wq_desc_count, 560 .nb_min = ENIC_MIN_WQ_DESCS, 561 .nb_align = ENIC_ALIGN_DESCS, 562 .nb_seg_max = ENIC_TX_XMIT_MAX, 563 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 564 }; 565 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 566 .burst_size = ENIC_DEFAULT_RX_BURST, 567 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 568 ENIC_DEFAULT_RX_RING_SIZE), 569 .nb_queues = ENIC_DEFAULT_RX_RINGS, 570 }; 571 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 572 .burst_size = ENIC_DEFAULT_TX_BURST, 573 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 574 ENIC_DEFAULT_TX_RING_SIZE), 575 .nb_queues = ENIC_DEFAULT_TX_RINGS, 576 }; 577 device_info->speed_capa = speed_capa_from_pci_id(eth_dev); 578 579 return 0; 580 } 581 582 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) 583 { 584 static const uint32_t ptypes[] = { 585 RTE_PTYPE_L2_ETHER, 586 RTE_PTYPE_L2_ETHER_VLAN, 587 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 588 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 589 RTE_PTYPE_L4_TCP, 590 RTE_PTYPE_L4_UDP, 591 RTE_PTYPE_L4_FRAG, 592 RTE_PTYPE_L4_NONFRAG, 593 RTE_PTYPE_UNKNOWN 594 }; 595 static const uint32_t ptypes_overlay[] = { 596 RTE_PTYPE_L2_ETHER, 597 RTE_PTYPE_L2_ETHER_VLAN, 598 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 599 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 600 RTE_PTYPE_L4_TCP, 601 RTE_PTYPE_L4_UDP, 602 RTE_PTYPE_L4_FRAG, 603 RTE_PTYPE_L4_NONFRAG, 604 RTE_PTYPE_TUNNEL_GRENAT, 605 RTE_PTYPE_INNER_L2_ETHER, 606 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 607 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 608 RTE_PTYPE_INNER_L4_TCP, 609 RTE_PTYPE_INNER_L4_UDP, 610 RTE_PTYPE_INNER_L4_FRAG, 611 RTE_PTYPE_INNER_L4_NONFRAG, 612 RTE_PTYPE_UNKNOWN 613 }; 614 615 if (dev->rx_pkt_burst != enic_dummy_recv_pkts && 616 dev->rx_pkt_burst != NULL) { 617 struct enic *enic = pmd_priv(dev); 618 if (enic->overlay_offload) 619 return ptypes_overlay; 620 else 621 return ptypes; 622 } 623 return NULL; 624 } 625 626 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 627 { 628 struct enic *enic = pmd_priv(eth_dev); 629 int ret; 630 631 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 632 return -E_RTE_SECONDARY; 633 634 ENICPMD_FUNC_TRACE(); 635 636 enic->promisc = 1; 637 ret = enic_add_packet_filter(enic); 638 if (ret != 0) 639 enic->promisc = 0; 640 641 return ret; 642 } 643 644 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 645 { 646 struct enic *enic = pmd_priv(eth_dev); 647 int ret; 648 649 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 650 return -E_RTE_SECONDARY; 651 652 ENICPMD_FUNC_TRACE(); 653 enic->promisc = 0; 654 ret = enic_add_packet_filter(enic); 655 if (ret != 0) 656 enic->promisc = 1; 657 658 return ret; 659 } 660 661 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 662 { 663 struct enic *enic = pmd_priv(eth_dev); 664 int ret; 665 666 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 667 return -E_RTE_SECONDARY; 668 669 ENICPMD_FUNC_TRACE(); 670 enic->allmulti = 1; 671 ret = enic_add_packet_filter(enic); 672 if (ret != 0) 673 enic->allmulti = 0; 674 675 return ret; 676 } 677 678 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 679 { 680 struct enic *enic = pmd_priv(eth_dev); 681 int ret; 682 683 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 684 return -E_RTE_SECONDARY; 685 686 ENICPMD_FUNC_TRACE(); 687 enic->allmulti = 0; 688 ret = enic_add_packet_filter(enic); 689 if (ret != 0) 690 enic->allmulti = 1; 691 692 return ret; 693 } 694 695 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 696 struct rte_ether_addr *mac_addr, 697 __rte_unused uint32_t index, __rte_unused uint32_t pool) 698 { 699 struct enic *enic = pmd_priv(eth_dev); 700 701 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 702 return -E_RTE_SECONDARY; 703 704 ENICPMD_FUNC_TRACE(); 705 return enic_set_mac_address(enic, mac_addr->addr_bytes); 706 } 707 708 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 709 { 710 struct enic *enic = pmd_priv(eth_dev); 711 712 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 713 return; 714 715 ENICPMD_FUNC_TRACE(); 716 if (enic_del_mac_address(enic, index)) 717 dev_err(enic, "del mac addr failed\n"); 718 } 719 720 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 721 struct rte_ether_addr *addr) 722 { 723 struct enic *enic = pmd_priv(eth_dev); 724 int ret; 725 726 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 727 return -E_RTE_SECONDARY; 728 729 ENICPMD_FUNC_TRACE(); 730 ret = enic_del_mac_address(enic, 0); 731 if (ret) 732 return ret; 733 return enic_set_mac_address(enic, addr->addr_bytes); 734 } 735 736 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add) 737 { 738 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 739 740 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr); 741 ENICPMD_LOG(DEBUG, " %s address %s\n", 742 add ? "add" : "remove", mac_str); 743 } 744 745 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev, 746 struct rte_ether_addr *mc_addr_set, 747 uint32_t nb_mc_addr) 748 { 749 struct enic *enic = pmd_priv(eth_dev); 750 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 751 struct rte_ether_addr *addr; 752 uint32_t i, j; 753 int ret; 754 755 ENICPMD_FUNC_TRACE(); 756 757 /* Validate the given addresses first */ 758 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) { 759 addr = &mc_addr_set[i]; 760 if (!rte_is_multicast_ether_addr(addr) || 761 rte_is_broadcast_ether_addr(addr)) { 762 rte_ether_format_addr(mac_str, 763 RTE_ETHER_ADDR_FMT_SIZE, addr); 764 ENICPMD_LOG(ERR, " invalid multicast address %s\n", 765 mac_str); 766 return -EINVAL; 767 } 768 } 769 770 /* Flush all if requested */ 771 if (nb_mc_addr == 0 || mc_addr_set == NULL) { 772 ENICPMD_LOG(DEBUG, " flush multicast addresses\n"); 773 for (i = 0; i < enic->mc_count; i++) { 774 addr = &enic->mc_addrs[i]; 775 debug_log_add_del_addr(addr, false); 776 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 777 if (ret) 778 return ret; 779 } 780 enic->mc_count = 0; 781 return 0; 782 } 783 784 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) { 785 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n", 786 ENIC_MULTICAST_PERFECT_FILTERS); 787 return -ENOSPC; 788 } 789 /* 790 * devcmd is slow, so apply the difference instead of flushing and 791 * adding everything. 792 * 1. Delete addresses on the NIC but not on the host 793 */ 794 for (i = 0; i < enic->mc_count; i++) { 795 addr = &enic->mc_addrs[i]; 796 for (j = 0; j < nb_mc_addr; j++) { 797 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) 798 break; 799 } 800 if (j < nb_mc_addr) 801 continue; 802 debug_log_add_del_addr(addr, false); 803 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 804 if (ret) 805 return ret; 806 } 807 /* 2. Add addresses on the host but not on the NIC */ 808 for (i = 0; i < nb_mc_addr; i++) { 809 addr = &mc_addr_set[i]; 810 for (j = 0; j < enic->mc_count; j++) { 811 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j])) 812 break; 813 } 814 if (j < enic->mc_count) 815 continue; 816 debug_log_add_del_addr(addr, true); 817 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes); 818 if (ret) 819 return ret; 820 } 821 /* Keep a copy so we can flush/apply later on.. */ 822 memcpy(enic->mc_addrs, mc_addr_set, 823 nb_mc_addr * sizeof(struct rte_ether_addr)); 824 enic->mc_count = nb_mc_addr; 825 return 0; 826 } 827 828 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 829 { 830 struct enic *enic = pmd_priv(eth_dev); 831 832 ENICPMD_FUNC_TRACE(); 833 return enic_set_mtu(enic, mtu); 834 } 835 836 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 837 struct rte_eth_rss_reta_entry64 838 *reta_conf, 839 uint16_t reta_size) 840 { 841 struct enic *enic = pmd_priv(dev); 842 uint16_t i, idx, shift; 843 844 ENICPMD_FUNC_TRACE(); 845 if (reta_size != ENIC_RSS_RETA_SIZE) { 846 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 847 reta_size, ENIC_RSS_RETA_SIZE); 848 return -EINVAL; 849 } 850 851 for (i = 0; i < reta_size; i++) { 852 idx = i / RTE_RETA_GROUP_SIZE; 853 shift = i % RTE_RETA_GROUP_SIZE; 854 if (reta_conf[idx].mask & (1ULL << shift)) 855 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 856 enic->rss_cpu.cpu[i / 4].b[i % 4]); 857 } 858 859 return 0; 860 } 861 862 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 863 struct rte_eth_rss_reta_entry64 864 *reta_conf, 865 uint16_t reta_size) 866 { 867 struct enic *enic = pmd_priv(dev); 868 union vnic_rss_cpu rss_cpu; 869 uint16_t i, idx, shift; 870 871 ENICPMD_FUNC_TRACE(); 872 if (reta_size != ENIC_RSS_RETA_SIZE) { 873 dev_err(enic, "reta_update: wrong reta_size. given=%u" 874 " expected=%u\n", 875 reta_size, ENIC_RSS_RETA_SIZE); 876 return -EINVAL; 877 } 878 /* 879 * Start with the current reta and modify it per reta_conf, as we 880 * need to push the entire reta even if we only modify one entry. 881 */ 882 rss_cpu = enic->rss_cpu; 883 for (i = 0; i < reta_size; i++) { 884 idx = i / RTE_RETA_GROUP_SIZE; 885 shift = i % RTE_RETA_GROUP_SIZE; 886 if (reta_conf[idx].mask & (1ULL << shift)) 887 rss_cpu.cpu[i / 4].b[i % 4] = 888 enic_rte_rq_idx_to_sop_idx( 889 reta_conf[idx].reta[shift]); 890 } 891 return enic_set_rss_reta(enic, &rss_cpu); 892 } 893 894 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 895 struct rte_eth_rss_conf *rss_conf) 896 { 897 struct enic *enic = pmd_priv(dev); 898 899 ENICPMD_FUNC_TRACE(); 900 return enic_set_rss_conf(enic, rss_conf); 901 } 902 903 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 904 struct rte_eth_rss_conf *rss_conf) 905 { 906 struct enic *enic = pmd_priv(dev); 907 908 ENICPMD_FUNC_TRACE(); 909 if (rss_conf == NULL) 910 return -EINVAL; 911 if (rss_conf->rss_key != NULL && 912 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 913 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 914 " expected=%u+\n", 915 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 916 return -EINVAL; 917 } 918 rss_conf->rss_hf = enic->rss_hf; 919 if (rss_conf->rss_key != NULL) { 920 int i; 921 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 922 rss_conf->rss_key[i] = 923 enic->rss_key.key[i / 10].b[i % 10]; 924 } 925 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 926 } 927 return 0; 928 } 929 930 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 931 uint16_t rx_queue_id, 932 struct rte_eth_rxq_info *qinfo) 933 { 934 struct enic *enic = pmd_priv(dev); 935 struct vnic_rq *rq_sop; 936 struct vnic_rq *rq_data; 937 struct rte_eth_rxconf *conf; 938 uint16_t sop_queue_idx; 939 uint16_t data_queue_idx; 940 941 ENICPMD_FUNC_TRACE(); 942 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 943 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic); 944 rq_sop = &enic->rq[sop_queue_idx]; 945 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 946 qinfo->mp = rq_sop->mp; 947 qinfo->scattered_rx = rq_sop->data_queue_enable; 948 qinfo->nb_desc = rq_sop->ring.desc_count; 949 if (qinfo->scattered_rx) 950 qinfo->nb_desc += rq_data->ring.desc_count; 951 conf = &qinfo->conf; 952 memset(conf, 0, sizeof(*conf)); 953 conf->rx_free_thresh = rq_sop->rx_free_thresh; 954 conf->rx_drop_en = 1; 955 /* 956 * Except VLAN stripping (port setting), all the checksum offloads 957 * are always enabled. 958 */ 959 conf->offloads = enic->rx_offload_capa; 960 if (!enic->ig_vlan_strip_en) 961 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 962 /* rx_thresh and other fields are not applicable for enic */ 963 } 964 965 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 966 uint16_t tx_queue_id, 967 struct rte_eth_txq_info *qinfo) 968 { 969 struct enic *enic = pmd_priv(dev); 970 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 971 972 ENICPMD_FUNC_TRACE(); 973 qinfo->nb_desc = wq->ring.desc_count; 974 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 975 qinfo->conf.offloads = wq->offloads; 976 /* tx_thresh, and all the other fields are not applicable for enic */ 977 } 978 979 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 980 uint16_t rx_queue_id) 981 { 982 struct enic *enic = pmd_priv(eth_dev); 983 984 ENICPMD_FUNC_TRACE(); 985 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 986 return 0; 987 } 988 989 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 990 uint16_t rx_queue_id) 991 { 992 struct enic *enic = pmd_priv(eth_dev); 993 994 ENICPMD_FUNC_TRACE(); 995 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 996 return 0; 997 } 998 999 static int udp_tunnel_common_check(struct enic *enic, 1000 struct rte_eth_udp_tunnel *tnl) 1001 { 1002 if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN) 1003 return -ENOTSUP; 1004 if (!enic->overlay_offload) { 1005 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not " 1006 "supported\n"); 1007 return -ENOTSUP; 1008 } 1009 return 0; 1010 } 1011 1012 static int update_vxlan_port(struct enic *enic, uint16_t port) 1013 { 1014 if (vnic_dev_overlay_offload_cfg(enic->vdev, 1015 OVERLAY_CFG_VXLAN_PORT_UPDATE, 1016 port)) { 1017 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n"); 1018 return -EINVAL; 1019 } 1020 ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port); 1021 enic->vxlan_port = port; 1022 return 0; 1023 } 1024 1025 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 1026 struct rte_eth_udp_tunnel *tnl) 1027 { 1028 struct enic *enic = pmd_priv(eth_dev); 1029 int ret; 1030 1031 ENICPMD_FUNC_TRACE(); 1032 ret = udp_tunnel_common_check(enic, tnl); 1033 if (ret) 1034 return ret; 1035 /* 1036 * The NIC has 1 configurable VXLAN port number. "Adding" a new port 1037 * number replaces it. 1038 */ 1039 if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) { 1040 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n", 1041 tnl->udp_port); 1042 return -EINVAL; 1043 } 1044 return update_vxlan_port(enic, tnl->udp_port); 1045 } 1046 1047 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 1048 struct rte_eth_udp_tunnel *tnl) 1049 { 1050 struct enic *enic = pmd_priv(eth_dev); 1051 int ret; 1052 1053 ENICPMD_FUNC_TRACE(); 1054 ret = udp_tunnel_common_check(enic, tnl); 1055 if (ret) 1056 return ret; 1057 /* 1058 * Clear the previously set port number and restore the 1059 * hardware default port number. Some drivers disable VXLAN 1060 * offloads when there are no configured port numbers. But 1061 * enic does not do that as VXLAN is part of overlay offload, 1062 * which is tied to inner RSS and TSO. 1063 */ 1064 if (tnl->udp_port != enic->vxlan_port) { 1065 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n", 1066 tnl->udp_port); 1067 return -EINVAL; 1068 } 1069 return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT); 1070 } 1071 1072 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev, 1073 char *fw_version, size_t fw_size) 1074 { 1075 struct vnic_devcmd_fw_info *info; 1076 struct enic *enic; 1077 int ret; 1078 1079 ENICPMD_FUNC_TRACE(); 1080 if (fw_version == NULL || fw_size <= 0) 1081 return -EINVAL; 1082 enic = pmd_priv(eth_dev); 1083 ret = vnic_dev_fw_info(enic->vdev, &info); 1084 if (ret) 1085 return ret; 1086 snprintf(fw_version, fw_size, "%s %s", 1087 info->fw_version, info->fw_build); 1088 fw_version[fw_size - 1] = '\0'; 1089 return 0; 1090 } 1091 1092 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 1093 .dev_configure = enicpmd_dev_configure, 1094 .dev_start = enicpmd_dev_start, 1095 .dev_stop = enicpmd_dev_stop, 1096 .dev_set_link_up = NULL, 1097 .dev_set_link_down = NULL, 1098 .dev_close = enicpmd_dev_close, 1099 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 1100 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 1101 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 1102 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 1103 .link_update = enicpmd_dev_link_update, 1104 .stats_get = enicpmd_dev_stats_get, 1105 .stats_reset = enicpmd_dev_stats_reset, 1106 .queue_stats_mapping_set = NULL, 1107 .dev_infos_get = enicpmd_dev_info_get, 1108 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 1109 .mtu_set = enicpmd_mtu_set, 1110 .vlan_filter_set = NULL, 1111 .vlan_tpid_set = NULL, 1112 .vlan_offload_set = enicpmd_vlan_offload_set, 1113 .vlan_strip_queue_set = NULL, 1114 .rx_queue_start = enicpmd_dev_rx_queue_start, 1115 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 1116 .tx_queue_start = enicpmd_dev_tx_queue_start, 1117 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 1118 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 1119 .rx_queue_release = enicpmd_dev_rx_queue_release, 1120 .rx_queue_count = enicpmd_dev_rx_queue_count, 1121 .rx_descriptor_done = NULL, 1122 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 1123 .tx_queue_release = enicpmd_dev_tx_queue_release, 1124 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 1125 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 1126 .rxq_info_get = enicpmd_dev_rxq_info_get, 1127 .txq_info_get = enicpmd_dev_txq_info_get, 1128 .dev_led_on = NULL, 1129 .dev_led_off = NULL, 1130 .flow_ctrl_get = NULL, 1131 .flow_ctrl_set = NULL, 1132 .priority_flow_ctrl_set = NULL, 1133 .mac_addr_add = enicpmd_add_mac_addr, 1134 .mac_addr_remove = enicpmd_remove_mac_addr, 1135 .mac_addr_set = enicpmd_set_mac_addr, 1136 .set_mc_addr_list = enicpmd_set_mc_addr_list, 1137 .filter_ctrl = enicpmd_dev_filter_ctrl, 1138 .reta_query = enicpmd_dev_rss_reta_query, 1139 .reta_update = enicpmd_dev_rss_reta_update, 1140 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 1141 .rss_hash_update = enicpmd_dev_rss_hash_update, 1142 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 1143 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 1144 .fw_version_get = enicpmd_dev_fw_version_get, 1145 }; 1146 1147 static int enic_parse_zero_one(const char *key, 1148 const char *value, 1149 void *opaque) 1150 { 1151 struct enic *enic; 1152 bool b; 1153 1154 enic = (struct enic *)opaque; 1155 if (strcmp(value, "0") == 0) { 1156 b = false; 1157 } else if (strcmp(value, "1") == 0) { 1158 b = true; 1159 } else { 1160 dev_err(enic, "Invalid value for %s" 1161 ": expected=0|1 given=%s\n", key, value); 1162 return -EINVAL; 1163 } 1164 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 1165 enic->disable_overlay = b; 1166 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 1167 enic->enable_avx2_rx = b; 1168 if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0) 1169 enic->geneve_opt_request = b; 1170 return 0; 1171 } 1172 1173 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 1174 const char *value, 1175 void *opaque) 1176 { 1177 struct enic *enic; 1178 1179 enic = (struct enic *)opaque; 1180 if (strcmp(value, "trunk") == 0) { 1181 /* Trunk mode: always tag */ 1182 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 1183 } else if (strcmp(value, "untag") == 0) { 1184 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 1185 enic->ig_vlan_rewrite_mode = 1186 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 1187 } else if (strcmp(value, "priority") == 0) { 1188 /* 1189 * Priority-tag default VLAN mode: priority tag (VLAN header 1190 * with ID=0) if VLAN = default 1191 */ 1192 enic->ig_vlan_rewrite_mode = 1193 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 1194 } else if (strcmp(value, "pass") == 0) { 1195 /* Pass through mode: do not touch tags */ 1196 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1197 } else { 1198 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 1199 ": expected=trunk|untag|priority|pass given=%s\n", 1200 value); 1201 return -EINVAL; 1202 } 1203 return 0; 1204 } 1205 1206 static int enic_check_devargs(struct rte_eth_dev *dev) 1207 { 1208 static const char *const valid_keys[] = { 1209 ENIC_DEVARG_DISABLE_OVERLAY, 1210 ENIC_DEVARG_ENABLE_AVX2_RX, 1211 ENIC_DEVARG_GENEVE_OPT, 1212 ENIC_DEVARG_IG_VLAN_REWRITE, 1213 NULL}; 1214 struct enic *enic = pmd_priv(dev); 1215 struct rte_kvargs *kvlist; 1216 1217 ENICPMD_FUNC_TRACE(); 1218 1219 enic->disable_overlay = false; 1220 enic->enable_avx2_rx = false; 1221 enic->geneve_opt_request = false; 1222 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1223 if (!dev->device->devargs) 1224 return 0; 1225 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1226 if (!kvlist) 1227 return -EINVAL; 1228 if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 1229 enic_parse_zero_one, enic) < 0 || 1230 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 1231 enic_parse_zero_one, enic) < 0 || 1232 rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT, 1233 enic_parse_zero_one, enic) < 0 || 1234 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1235 enic_parse_ig_vlan_rewrite, enic) < 0) { 1236 rte_kvargs_free(kvlist); 1237 return -EINVAL; 1238 } 1239 rte_kvargs_free(kvlist); 1240 return 0; 1241 } 1242 1243 /* Initialize the driver 1244 * It returns 0 on success. 1245 */ 1246 static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev) 1247 { 1248 struct rte_pci_device *pdev; 1249 struct rte_pci_addr *addr; 1250 struct enic *enic = pmd_priv(eth_dev); 1251 int err; 1252 1253 ENICPMD_FUNC_TRACE(); 1254 1255 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1256 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1257 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1258 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1259 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1260 enic_pick_tx_handler(eth_dev); 1261 enic_pick_rx_handler(eth_dev); 1262 return 0; 1263 } 1264 /* Only the primary sets up adapter and other data in shared memory */ 1265 enic->port_id = eth_dev->data->port_id; 1266 enic->rte_dev = eth_dev; 1267 enic->dev_data = eth_dev->data; 1268 /* Let rte_eth_dev_close() release the port resources */ 1269 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1270 1271 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1272 rte_eth_copy_pci_info(eth_dev, pdev); 1273 enic->pdev = pdev; 1274 addr = &pdev->addr; 1275 1276 snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x", 1277 addr->domain, addr->bus, addr->devid, addr->function); 1278 1279 err = enic_check_devargs(eth_dev); 1280 if (err) 1281 return err; 1282 return enic_probe(enic); 1283 } 1284 1285 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1286 struct rte_pci_device *pci_dev) 1287 { 1288 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct enic), 1289 eth_enicpmd_dev_init); 1290 } 1291 1292 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1293 { 1294 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 1295 } 1296 1297 static struct rte_pci_driver rte_enic_pmd = { 1298 .id_table = pci_id_enic_map, 1299 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1300 .probe = eth_enic_pci_probe, 1301 .remove = eth_enic_pci_remove, 1302 }; 1303 1304 int dev_is_enic(struct rte_eth_dev *dev) 1305 { 1306 return dev->device->driver == &rte_enic_pmd.driver; 1307 } 1308 1309 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1310 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1311 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1312 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1313 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1314 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1315 ENIC_DEVARG_GENEVE_OPT "=0|1 " 1316 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1317