1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <rte_dev.h> 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_ethdev_pci.h> 14 #include <rte_kvargs.h> 15 #include <rte_string_fns.h> 16 17 #include "vnic_intr.h" 18 #include "vnic_cq.h" 19 #include "vnic_wq.h" 20 #include "vnic_rq.h" 21 #include "vnic_enet.h" 22 #include "enic.h" 23 24 /* 25 * The set of PCI devices this driver supports 26 */ 27 #define CISCO_PCI_VENDOR_ID 0x1137 28 static const struct rte_pci_id pci_id_enic_map[] = { 29 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)}, 30 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)}, 31 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)}, 32 {.vendor_id = 0, /* sentinel */}, 33 }; 34 35 /* Supported link speeds of production VIC models */ 36 static const struct vic_speed_capa { 37 uint16_t sub_devid; 38 uint32_t capa; 39 } vic_speed_capa_map[] = { 40 { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */ 41 { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */ 42 { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */ 43 { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */ 44 { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */ 45 { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */ 46 { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */ 47 { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */ 48 { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */ 49 { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */ 50 { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */ 51 { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */ 52 { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */ 53 { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */ 54 { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 55 ETH_LINK_SPEED_40G }, /* 1440 Mezz */ 56 { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 57 ETH_LINK_SPEED_40G }, /* 1480 MLOM */ 58 { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */ 59 { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */ 60 { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */ 61 { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */ 62 { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */ 63 { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */ 64 { 0, 0 }, /* End marker */ 65 }; 66 67 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 68 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 69 #define ENIC_DEVARG_GENEVE_OPT "geneve-opt" 70 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 71 72 RTE_LOG_REGISTER(enic_pmd_logtype, pmd.net.enic, INFO); 73 74 static int 75 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev, 76 enum rte_filter_op filter_op, void *arg) 77 { 78 struct enic *enic = pmd_priv(eth_dev); 79 int ret = 0; 80 81 ENICPMD_FUNC_TRACE(); 82 if (filter_op == RTE_ETH_FILTER_NOP) 83 return 0; 84 85 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 86 return -EINVAL; 87 88 switch (filter_op) { 89 case RTE_ETH_FILTER_ADD: 90 case RTE_ETH_FILTER_UPDATE: 91 ret = enic_fdir_add_fltr(enic, 92 (struct rte_eth_fdir_filter *)arg); 93 break; 94 95 case RTE_ETH_FILTER_DELETE: 96 ret = enic_fdir_del_fltr(enic, 97 (struct rte_eth_fdir_filter *)arg); 98 break; 99 100 case RTE_ETH_FILTER_STATS: 101 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg); 102 break; 103 104 case RTE_ETH_FILTER_FLUSH: 105 dev_warning(enic, "unsupported operation %u", filter_op); 106 ret = -ENOTSUP; 107 break; 108 case RTE_ETH_FILTER_INFO: 109 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg); 110 break; 111 default: 112 dev_err(enic, "unknown operation %u", filter_op); 113 ret = -EINVAL; 114 break; 115 } 116 return ret; 117 } 118 119 static int 120 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev, 121 enum rte_filter_type filter_type, 122 enum rte_filter_op filter_op, 123 void *arg) 124 { 125 struct enic *enic = pmd_priv(dev); 126 int ret = 0; 127 128 ENICPMD_FUNC_TRACE(); 129 130 /* 131 * Currently, when Geneve with options offload is enabled, host 132 * cannot insert match-action rules. 133 */ 134 if (enic->geneve_opt_enabled) 135 return -ENOTSUP; 136 switch (filter_type) { 137 case RTE_ETH_FILTER_GENERIC: 138 if (filter_op != RTE_ETH_FILTER_GET) 139 return -EINVAL; 140 if (enic->flow_filter_mode == FILTER_FLOWMAN) 141 *(const void **)arg = &enic_fm_flow_ops; 142 else 143 *(const void **)arg = &enic_flow_ops; 144 break; 145 case RTE_ETH_FILTER_FDIR: 146 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg); 147 break; 148 default: 149 dev_warning(enic, "Filter type (%d) not supported", 150 filter_type); 151 ret = -EINVAL; 152 break; 153 } 154 155 return ret; 156 } 157 158 static void enicpmd_dev_tx_queue_release(void *txq) 159 { 160 ENICPMD_FUNC_TRACE(); 161 162 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 163 return; 164 165 enic_free_wq(txq); 166 } 167 168 static int enicpmd_dev_setup_intr(struct enic *enic) 169 { 170 int ret; 171 unsigned int index; 172 173 ENICPMD_FUNC_TRACE(); 174 175 /* Are we done with the init of all the queues? */ 176 for (index = 0; index < enic->cq_count; index++) { 177 if (!enic->cq[index].ctrl) 178 break; 179 } 180 if (enic->cq_count != index) 181 return 0; 182 for (index = 0; index < enic->wq_count; index++) { 183 if (!enic->wq[index].ctrl) 184 break; 185 } 186 if (enic->wq_count != index) 187 return 0; 188 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 189 for (index = 0; index < enic->rq_count; index++) { 190 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 191 break; 192 } 193 if (enic->rq_count != index) 194 return 0; 195 196 ret = enic_alloc_intr_resources(enic); 197 if (ret) { 198 dev_err(enic, "alloc intr failed\n"); 199 return ret; 200 } 201 enic_init_vnic_resources(enic); 202 203 ret = enic_setup_finish(enic); 204 if (ret) 205 dev_err(enic, "setup could not be finished\n"); 206 207 return ret; 208 } 209 210 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 211 uint16_t queue_idx, 212 uint16_t nb_desc, 213 unsigned int socket_id, 214 const struct rte_eth_txconf *tx_conf) 215 { 216 int ret; 217 struct enic *enic = pmd_priv(eth_dev); 218 struct vnic_wq *wq; 219 220 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 221 return -E_RTE_SECONDARY; 222 223 ENICPMD_FUNC_TRACE(); 224 RTE_ASSERT(queue_idx < enic->conf_wq_count); 225 wq = &enic->wq[queue_idx]; 226 wq->offloads = tx_conf->offloads | 227 eth_dev->data->dev_conf.txmode.offloads; 228 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 229 230 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 231 if (ret) { 232 dev_err(enic, "error in allocating wq\n"); 233 return ret; 234 } 235 236 return enicpmd_dev_setup_intr(enic); 237 } 238 239 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 240 uint16_t queue_idx) 241 { 242 struct enic *enic = pmd_priv(eth_dev); 243 244 ENICPMD_FUNC_TRACE(); 245 246 enic_start_wq(enic, queue_idx); 247 248 return 0; 249 } 250 251 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 252 uint16_t queue_idx) 253 { 254 int ret; 255 struct enic *enic = pmd_priv(eth_dev); 256 257 ENICPMD_FUNC_TRACE(); 258 259 ret = enic_stop_wq(enic, queue_idx); 260 if (ret) 261 dev_err(enic, "error in stopping wq %d\n", queue_idx); 262 263 return ret; 264 } 265 266 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 267 uint16_t queue_idx) 268 { 269 struct enic *enic = pmd_priv(eth_dev); 270 271 ENICPMD_FUNC_TRACE(); 272 273 enic_start_rq(enic, queue_idx); 274 275 return 0; 276 } 277 278 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 279 uint16_t queue_idx) 280 { 281 int ret; 282 struct enic *enic = pmd_priv(eth_dev); 283 284 ENICPMD_FUNC_TRACE(); 285 286 ret = enic_stop_rq(enic, queue_idx); 287 if (ret) 288 dev_err(enic, "error in stopping rq %d\n", queue_idx); 289 290 return ret; 291 } 292 293 static void enicpmd_dev_rx_queue_release(void *rxq) 294 { 295 ENICPMD_FUNC_TRACE(); 296 297 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 298 return; 299 300 enic_free_rq(rxq); 301 } 302 303 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev, 304 uint16_t rx_queue_id) 305 { 306 struct enic *enic = pmd_priv(dev); 307 uint32_t queue_count = 0; 308 struct vnic_cq *cq; 309 uint32_t cq_tail; 310 uint16_t cq_idx; 311 int rq_num; 312 313 rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 314 cq = &enic->cq[enic_cq_rq(enic, rq_num)]; 315 cq_idx = cq->to_clean; 316 317 cq_tail = ioread32(&cq->ctrl->cq_tail); 318 319 if (cq_tail < cq_idx) 320 cq_tail += cq->ring.desc_count; 321 322 queue_count = cq_tail - cq_idx; 323 324 return queue_count; 325 } 326 327 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 328 uint16_t queue_idx, 329 uint16_t nb_desc, 330 unsigned int socket_id, 331 const struct rte_eth_rxconf *rx_conf, 332 struct rte_mempool *mp) 333 { 334 int ret; 335 struct enic *enic = pmd_priv(eth_dev); 336 337 ENICPMD_FUNC_TRACE(); 338 339 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 340 return -E_RTE_SECONDARY; 341 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 342 eth_dev->data->rx_queues[queue_idx] = 343 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 344 345 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 346 rx_conf->rx_free_thresh); 347 if (ret) { 348 dev_err(enic, "error in allocating rq\n"); 349 return ret; 350 } 351 352 return enicpmd_dev_setup_intr(enic); 353 } 354 355 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 356 { 357 struct enic *enic = pmd_priv(eth_dev); 358 uint64_t offloads; 359 360 ENICPMD_FUNC_TRACE(); 361 362 offloads = eth_dev->data->dev_conf.rxmode.offloads; 363 if (mask & ETH_VLAN_STRIP_MASK) { 364 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 365 enic->ig_vlan_strip_en = 1; 366 else 367 enic->ig_vlan_strip_en = 0; 368 } 369 370 return enic_set_vlan_strip(enic); 371 } 372 373 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 374 { 375 int ret; 376 int mask; 377 struct enic *enic = pmd_priv(eth_dev); 378 379 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 380 return -E_RTE_SECONDARY; 381 382 ENICPMD_FUNC_TRACE(); 383 ret = enic_set_vnic_res(enic); 384 if (ret) { 385 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 386 return ret; 387 } 388 389 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 390 eth_dev->data->dev_conf.rxmode.offloads |= 391 DEV_RX_OFFLOAD_RSS_HASH; 392 393 enic->mc_count = 0; 394 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 395 DEV_RX_OFFLOAD_CHECKSUM); 396 /* All vlan offload masks to apply the current settings */ 397 mask = ETH_VLAN_STRIP_MASK | 398 ETH_VLAN_FILTER_MASK | 399 ETH_VLAN_EXTEND_MASK; 400 ret = enicpmd_vlan_offload_set(eth_dev, mask); 401 if (ret) { 402 dev_err(enic, "Failed to configure VLAN offloads\n"); 403 return ret; 404 } 405 /* 406 * Initialize RSS with the default reta and key. If the user key is 407 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 408 * default key. 409 */ 410 return enic_init_rss_nic_cfg(enic); 411 } 412 413 /* Start the device. 414 * It returns 0 on success. 415 */ 416 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 417 { 418 struct enic *enic = pmd_priv(eth_dev); 419 420 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 421 return -E_RTE_SECONDARY; 422 423 ENICPMD_FUNC_TRACE(); 424 return enic_enable(enic); 425 } 426 427 /* 428 * Stop device: disable rx and tx functions to allow for reconfiguring. 429 */ 430 static void enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 431 { 432 struct rte_eth_link link; 433 struct enic *enic = pmd_priv(eth_dev); 434 435 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 436 return; 437 438 ENICPMD_FUNC_TRACE(); 439 enic_disable(enic); 440 441 memset(&link, 0, sizeof(link)); 442 rte_eth_linkstatus_set(eth_dev, &link); 443 } 444 445 /* 446 * Stop device. 447 */ 448 static void enicpmd_dev_close(struct rte_eth_dev *eth_dev) 449 { 450 struct enic *enic = pmd_priv(eth_dev); 451 452 ENICPMD_FUNC_TRACE(); 453 enic_remove(enic); 454 } 455 456 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 457 __rte_unused int wait_to_complete) 458 { 459 ENICPMD_FUNC_TRACE(); 460 return enic_link_update(eth_dev); 461 } 462 463 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 464 struct rte_eth_stats *stats) 465 { 466 struct enic *enic = pmd_priv(eth_dev); 467 468 ENICPMD_FUNC_TRACE(); 469 return enic_dev_stats_get(enic, stats); 470 } 471 472 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 473 { 474 struct enic *enic = pmd_priv(eth_dev); 475 476 ENICPMD_FUNC_TRACE(); 477 return enic_dev_stats_clear(enic); 478 } 479 480 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) 481 { 482 const struct vic_speed_capa *m; 483 struct rte_pci_device *pdev; 484 uint16_t id; 485 486 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 487 id = pdev->id.subsystem_device_id; 488 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { 489 if (m->sub_devid == id) 490 return m->capa; 491 } 492 /* 1300 and later models are at least 40G */ 493 if (id >= 0x0100) 494 return ETH_LINK_SPEED_40G; 495 /* VFs have subsystem id 0, check device id */ 496 if (id == 0) { 497 /* Newer VF implies at least 40G model */ 498 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN) 499 return ETH_LINK_SPEED_40G; 500 } 501 return ETH_LINK_SPEED_10G; 502 } 503 504 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 505 struct rte_eth_dev_info *device_info) 506 { 507 struct enic *enic = pmd_priv(eth_dev); 508 509 ENICPMD_FUNC_TRACE(); 510 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 511 device_info->max_rx_queues = enic->conf_rq_count / 2; 512 device_info->max_tx_queues = enic->conf_wq_count; 513 device_info->min_rx_bufsize = ENIC_MIN_MTU; 514 /* "Max" mtu is not a typo. HW receives packet sizes up to the 515 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 516 * a hint to the driver to size receive buffers accordingly so that 517 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 518 * the user decide the buffer size via rxmode.max_rx_pkt_len, basically 519 * ignoring vNIC mtu. 520 */ 521 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 522 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS; 523 device_info->min_mtu = ENIC_MIN_MTU; 524 device_info->max_mtu = enic->max_mtu; 525 device_info->rx_offload_capa = enic->rx_offload_capa; 526 device_info->tx_offload_capa = enic->tx_offload_capa; 527 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 528 device_info->default_rxconf = (struct rte_eth_rxconf) { 529 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 530 }; 531 device_info->reta_size = enic->reta_size; 532 device_info->hash_key_size = enic->hash_key_size; 533 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 534 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 535 .nb_max = enic->config.rq_desc_count, 536 .nb_min = ENIC_MIN_RQ_DESCS, 537 .nb_align = ENIC_ALIGN_DESCS, 538 }; 539 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 540 .nb_max = enic->config.wq_desc_count, 541 .nb_min = ENIC_MIN_WQ_DESCS, 542 .nb_align = ENIC_ALIGN_DESCS, 543 .nb_seg_max = ENIC_TX_XMIT_MAX, 544 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 545 }; 546 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 547 .burst_size = ENIC_DEFAULT_RX_BURST, 548 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 549 ENIC_DEFAULT_RX_RING_SIZE), 550 .nb_queues = ENIC_DEFAULT_RX_RINGS, 551 }; 552 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 553 .burst_size = ENIC_DEFAULT_TX_BURST, 554 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 555 ENIC_DEFAULT_TX_RING_SIZE), 556 .nb_queues = ENIC_DEFAULT_TX_RINGS, 557 }; 558 device_info->speed_capa = speed_capa_from_pci_id(eth_dev); 559 560 return 0; 561 } 562 563 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) 564 { 565 static const uint32_t ptypes[] = { 566 RTE_PTYPE_L2_ETHER, 567 RTE_PTYPE_L2_ETHER_VLAN, 568 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 569 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 570 RTE_PTYPE_L4_TCP, 571 RTE_PTYPE_L4_UDP, 572 RTE_PTYPE_L4_FRAG, 573 RTE_PTYPE_L4_NONFRAG, 574 RTE_PTYPE_UNKNOWN 575 }; 576 static const uint32_t ptypes_overlay[] = { 577 RTE_PTYPE_L2_ETHER, 578 RTE_PTYPE_L2_ETHER_VLAN, 579 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 580 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 581 RTE_PTYPE_L4_TCP, 582 RTE_PTYPE_L4_UDP, 583 RTE_PTYPE_L4_FRAG, 584 RTE_PTYPE_L4_NONFRAG, 585 RTE_PTYPE_TUNNEL_GRENAT, 586 RTE_PTYPE_INNER_L2_ETHER, 587 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 588 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 589 RTE_PTYPE_INNER_L4_TCP, 590 RTE_PTYPE_INNER_L4_UDP, 591 RTE_PTYPE_INNER_L4_FRAG, 592 RTE_PTYPE_INNER_L4_NONFRAG, 593 RTE_PTYPE_UNKNOWN 594 }; 595 596 if (dev->rx_pkt_burst != enic_dummy_recv_pkts && 597 dev->rx_pkt_burst != NULL) { 598 struct enic *enic = pmd_priv(dev); 599 if (enic->overlay_offload) 600 return ptypes_overlay; 601 else 602 return ptypes; 603 } 604 return NULL; 605 } 606 607 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 608 { 609 struct enic *enic = pmd_priv(eth_dev); 610 int ret; 611 612 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 613 return -E_RTE_SECONDARY; 614 615 ENICPMD_FUNC_TRACE(); 616 617 enic->promisc = 1; 618 ret = enic_add_packet_filter(enic); 619 if (ret != 0) 620 enic->promisc = 0; 621 622 return ret; 623 } 624 625 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 626 { 627 struct enic *enic = pmd_priv(eth_dev); 628 int ret; 629 630 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 631 return -E_RTE_SECONDARY; 632 633 ENICPMD_FUNC_TRACE(); 634 enic->promisc = 0; 635 ret = enic_add_packet_filter(enic); 636 if (ret != 0) 637 enic->promisc = 1; 638 639 return ret; 640 } 641 642 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 643 { 644 struct enic *enic = pmd_priv(eth_dev); 645 int ret; 646 647 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 648 return -E_RTE_SECONDARY; 649 650 ENICPMD_FUNC_TRACE(); 651 enic->allmulti = 1; 652 ret = enic_add_packet_filter(enic); 653 if (ret != 0) 654 enic->allmulti = 0; 655 656 return ret; 657 } 658 659 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 660 { 661 struct enic *enic = pmd_priv(eth_dev); 662 int ret; 663 664 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 665 return -E_RTE_SECONDARY; 666 667 ENICPMD_FUNC_TRACE(); 668 enic->allmulti = 0; 669 ret = enic_add_packet_filter(enic); 670 if (ret != 0) 671 enic->allmulti = 1; 672 673 return ret; 674 } 675 676 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 677 struct rte_ether_addr *mac_addr, 678 __rte_unused uint32_t index, __rte_unused uint32_t pool) 679 { 680 struct enic *enic = pmd_priv(eth_dev); 681 682 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 683 return -E_RTE_SECONDARY; 684 685 ENICPMD_FUNC_TRACE(); 686 return enic_set_mac_address(enic, mac_addr->addr_bytes); 687 } 688 689 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 690 { 691 struct enic *enic = pmd_priv(eth_dev); 692 693 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 694 return; 695 696 ENICPMD_FUNC_TRACE(); 697 if (enic_del_mac_address(enic, index)) 698 dev_err(enic, "del mac addr failed\n"); 699 } 700 701 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 702 struct rte_ether_addr *addr) 703 { 704 struct enic *enic = pmd_priv(eth_dev); 705 int ret; 706 707 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 708 return -E_RTE_SECONDARY; 709 710 ENICPMD_FUNC_TRACE(); 711 ret = enic_del_mac_address(enic, 0); 712 if (ret) 713 return ret; 714 return enic_set_mac_address(enic, addr->addr_bytes); 715 } 716 717 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add) 718 { 719 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 720 721 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr); 722 ENICPMD_LOG(DEBUG, " %s address %s\n", 723 add ? "add" : "remove", mac_str); 724 } 725 726 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev, 727 struct rte_ether_addr *mc_addr_set, 728 uint32_t nb_mc_addr) 729 { 730 struct enic *enic = pmd_priv(eth_dev); 731 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 732 struct rte_ether_addr *addr; 733 uint32_t i, j; 734 int ret; 735 736 ENICPMD_FUNC_TRACE(); 737 738 /* Validate the given addresses first */ 739 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) { 740 addr = &mc_addr_set[i]; 741 if (!rte_is_multicast_ether_addr(addr) || 742 rte_is_broadcast_ether_addr(addr)) { 743 rte_ether_format_addr(mac_str, 744 RTE_ETHER_ADDR_FMT_SIZE, addr); 745 ENICPMD_LOG(ERR, " invalid multicast address %s\n", 746 mac_str); 747 return -EINVAL; 748 } 749 } 750 751 /* Flush all if requested */ 752 if (nb_mc_addr == 0 || mc_addr_set == NULL) { 753 ENICPMD_LOG(DEBUG, " flush multicast addresses\n"); 754 for (i = 0; i < enic->mc_count; i++) { 755 addr = &enic->mc_addrs[i]; 756 debug_log_add_del_addr(addr, false); 757 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 758 if (ret) 759 return ret; 760 } 761 enic->mc_count = 0; 762 return 0; 763 } 764 765 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) { 766 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n", 767 ENIC_MULTICAST_PERFECT_FILTERS); 768 return -ENOSPC; 769 } 770 /* 771 * devcmd is slow, so apply the difference instead of flushing and 772 * adding everything. 773 * 1. Delete addresses on the NIC but not on the host 774 */ 775 for (i = 0; i < enic->mc_count; i++) { 776 addr = &enic->mc_addrs[i]; 777 for (j = 0; j < nb_mc_addr; j++) { 778 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) 779 break; 780 } 781 if (j < nb_mc_addr) 782 continue; 783 debug_log_add_del_addr(addr, false); 784 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 785 if (ret) 786 return ret; 787 } 788 /* 2. Add addresses on the host but not on the NIC */ 789 for (i = 0; i < nb_mc_addr; i++) { 790 addr = &mc_addr_set[i]; 791 for (j = 0; j < enic->mc_count; j++) { 792 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j])) 793 break; 794 } 795 if (j < enic->mc_count) 796 continue; 797 debug_log_add_del_addr(addr, true); 798 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes); 799 if (ret) 800 return ret; 801 } 802 /* Keep a copy so we can flush/apply later on.. */ 803 memcpy(enic->mc_addrs, mc_addr_set, 804 nb_mc_addr * sizeof(struct rte_ether_addr)); 805 enic->mc_count = nb_mc_addr; 806 return 0; 807 } 808 809 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 810 { 811 struct enic *enic = pmd_priv(eth_dev); 812 813 ENICPMD_FUNC_TRACE(); 814 return enic_set_mtu(enic, mtu); 815 } 816 817 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 818 struct rte_eth_rss_reta_entry64 819 *reta_conf, 820 uint16_t reta_size) 821 { 822 struct enic *enic = pmd_priv(dev); 823 uint16_t i, idx, shift; 824 825 ENICPMD_FUNC_TRACE(); 826 if (reta_size != ENIC_RSS_RETA_SIZE) { 827 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 828 reta_size, ENIC_RSS_RETA_SIZE); 829 return -EINVAL; 830 } 831 832 for (i = 0; i < reta_size; i++) { 833 idx = i / RTE_RETA_GROUP_SIZE; 834 shift = i % RTE_RETA_GROUP_SIZE; 835 if (reta_conf[idx].mask & (1ULL << shift)) 836 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 837 enic->rss_cpu.cpu[i / 4].b[i % 4]); 838 } 839 840 return 0; 841 } 842 843 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 844 struct rte_eth_rss_reta_entry64 845 *reta_conf, 846 uint16_t reta_size) 847 { 848 struct enic *enic = pmd_priv(dev); 849 union vnic_rss_cpu rss_cpu; 850 uint16_t i, idx, shift; 851 852 ENICPMD_FUNC_TRACE(); 853 if (reta_size != ENIC_RSS_RETA_SIZE) { 854 dev_err(enic, "reta_update: wrong reta_size. given=%u" 855 " expected=%u\n", 856 reta_size, ENIC_RSS_RETA_SIZE); 857 return -EINVAL; 858 } 859 /* 860 * Start with the current reta and modify it per reta_conf, as we 861 * need to push the entire reta even if we only modify one entry. 862 */ 863 rss_cpu = enic->rss_cpu; 864 for (i = 0; i < reta_size; i++) { 865 idx = i / RTE_RETA_GROUP_SIZE; 866 shift = i % RTE_RETA_GROUP_SIZE; 867 if (reta_conf[idx].mask & (1ULL << shift)) 868 rss_cpu.cpu[i / 4].b[i % 4] = 869 enic_rte_rq_idx_to_sop_idx( 870 reta_conf[idx].reta[shift]); 871 } 872 return enic_set_rss_reta(enic, &rss_cpu); 873 } 874 875 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 876 struct rte_eth_rss_conf *rss_conf) 877 { 878 struct enic *enic = pmd_priv(dev); 879 880 ENICPMD_FUNC_TRACE(); 881 return enic_set_rss_conf(enic, rss_conf); 882 } 883 884 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 885 struct rte_eth_rss_conf *rss_conf) 886 { 887 struct enic *enic = pmd_priv(dev); 888 889 ENICPMD_FUNC_TRACE(); 890 if (rss_conf == NULL) 891 return -EINVAL; 892 if (rss_conf->rss_key != NULL && 893 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 894 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 895 " expected=%u+\n", 896 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 897 return -EINVAL; 898 } 899 rss_conf->rss_hf = enic->rss_hf; 900 if (rss_conf->rss_key != NULL) { 901 int i; 902 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 903 rss_conf->rss_key[i] = 904 enic->rss_key.key[i / 10].b[i % 10]; 905 } 906 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 907 } 908 return 0; 909 } 910 911 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 912 uint16_t rx_queue_id, 913 struct rte_eth_rxq_info *qinfo) 914 { 915 struct enic *enic = pmd_priv(dev); 916 struct vnic_rq *rq_sop; 917 struct vnic_rq *rq_data; 918 struct rte_eth_rxconf *conf; 919 uint16_t sop_queue_idx; 920 uint16_t data_queue_idx; 921 922 ENICPMD_FUNC_TRACE(); 923 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 924 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic); 925 rq_sop = &enic->rq[sop_queue_idx]; 926 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 927 qinfo->mp = rq_sop->mp; 928 qinfo->scattered_rx = rq_sop->data_queue_enable; 929 qinfo->nb_desc = rq_sop->ring.desc_count; 930 if (qinfo->scattered_rx) 931 qinfo->nb_desc += rq_data->ring.desc_count; 932 conf = &qinfo->conf; 933 memset(conf, 0, sizeof(*conf)); 934 conf->rx_free_thresh = rq_sop->rx_free_thresh; 935 conf->rx_drop_en = 1; 936 /* 937 * Except VLAN stripping (port setting), all the checksum offloads 938 * are always enabled. 939 */ 940 conf->offloads = enic->rx_offload_capa; 941 if (!enic->ig_vlan_strip_en) 942 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 943 /* rx_thresh and other fields are not applicable for enic */ 944 } 945 946 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 947 uint16_t tx_queue_id, 948 struct rte_eth_txq_info *qinfo) 949 { 950 struct enic *enic = pmd_priv(dev); 951 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 952 953 ENICPMD_FUNC_TRACE(); 954 qinfo->nb_desc = wq->ring.desc_count; 955 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 956 qinfo->conf.offloads = wq->offloads; 957 /* tx_thresh, and all the other fields are not applicable for enic */ 958 } 959 960 static int enicpmd_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 961 __rte_unused uint16_t queue_id, 962 struct rte_eth_burst_mode *mode) 963 { 964 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 965 struct enic *enic = pmd_priv(dev); 966 const char *info_str = NULL; 967 int ret = -EINVAL; 968 969 ENICPMD_FUNC_TRACE(); 970 if (enic->use_noscatter_vec_rx_handler) 971 info_str = "Vector AVX2 No Scatter"; 972 else if (pkt_burst == enic_noscatter_recv_pkts) 973 info_str = "Scalar No Scatter"; 974 else if (pkt_burst == enic_recv_pkts) 975 info_str = "Scalar"; 976 if (info_str) { 977 strlcpy(mode->info, info_str, sizeof(mode->info)); 978 ret = 0; 979 } 980 return ret; 981 } 982 983 static int enicpmd_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 984 __rte_unused uint16_t queue_id, 985 struct rte_eth_burst_mode *mode) 986 { 987 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 988 const char *info_str = NULL; 989 int ret = -EINVAL; 990 991 ENICPMD_FUNC_TRACE(); 992 if (pkt_burst == enic_simple_xmit_pkts) 993 info_str = "Scalar Simplified"; 994 else if (pkt_burst == enic_xmit_pkts) 995 info_str = "Scalar"; 996 if (info_str) { 997 strlcpy(mode->info, info_str, sizeof(mode->info)); 998 ret = 0; 999 } 1000 return ret; 1001 } 1002 1003 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 1004 uint16_t rx_queue_id) 1005 { 1006 struct enic *enic = pmd_priv(eth_dev); 1007 1008 ENICPMD_FUNC_TRACE(); 1009 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 1010 return 0; 1011 } 1012 1013 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 1014 uint16_t rx_queue_id) 1015 { 1016 struct enic *enic = pmd_priv(eth_dev); 1017 1018 ENICPMD_FUNC_TRACE(); 1019 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 1020 return 0; 1021 } 1022 1023 static int udp_tunnel_common_check(struct enic *enic, 1024 struct rte_eth_udp_tunnel *tnl) 1025 { 1026 if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN) 1027 return -ENOTSUP; 1028 if (!enic->overlay_offload) { 1029 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not " 1030 "supported\n"); 1031 return -ENOTSUP; 1032 } 1033 return 0; 1034 } 1035 1036 static int update_vxlan_port(struct enic *enic, uint16_t port) 1037 { 1038 if (vnic_dev_overlay_offload_cfg(enic->vdev, 1039 OVERLAY_CFG_VXLAN_PORT_UPDATE, 1040 port)) { 1041 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n"); 1042 return -EINVAL; 1043 } 1044 ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port); 1045 enic->vxlan_port = port; 1046 return 0; 1047 } 1048 1049 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 1050 struct rte_eth_udp_tunnel *tnl) 1051 { 1052 struct enic *enic = pmd_priv(eth_dev); 1053 int ret; 1054 1055 ENICPMD_FUNC_TRACE(); 1056 ret = udp_tunnel_common_check(enic, tnl); 1057 if (ret) 1058 return ret; 1059 /* 1060 * The NIC has 1 configurable VXLAN port number. "Adding" a new port 1061 * number replaces it. 1062 */ 1063 if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) { 1064 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n", 1065 tnl->udp_port); 1066 return -EINVAL; 1067 } 1068 return update_vxlan_port(enic, tnl->udp_port); 1069 } 1070 1071 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 1072 struct rte_eth_udp_tunnel *tnl) 1073 { 1074 struct enic *enic = pmd_priv(eth_dev); 1075 int ret; 1076 1077 ENICPMD_FUNC_TRACE(); 1078 ret = udp_tunnel_common_check(enic, tnl); 1079 if (ret) 1080 return ret; 1081 /* 1082 * Clear the previously set port number and restore the 1083 * hardware default port number. Some drivers disable VXLAN 1084 * offloads when there are no configured port numbers. But 1085 * enic does not do that as VXLAN is part of overlay offload, 1086 * which is tied to inner RSS and TSO. 1087 */ 1088 if (tnl->udp_port != enic->vxlan_port) { 1089 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n", 1090 tnl->udp_port); 1091 return -EINVAL; 1092 } 1093 return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT); 1094 } 1095 1096 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev, 1097 char *fw_version, size_t fw_size) 1098 { 1099 struct vnic_devcmd_fw_info *info; 1100 struct enic *enic; 1101 int ret; 1102 1103 ENICPMD_FUNC_TRACE(); 1104 if (fw_version == NULL || fw_size <= 0) 1105 return -EINVAL; 1106 enic = pmd_priv(eth_dev); 1107 ret = vnic_dev_fw_info(enic->vdev, &info); 1108 if (ret) 1109 return ret; 1110 snprintf(fw_version, fw_size, "%s %s", 1111 info->fw_version, info->fw_build); 1112 fw_version[fw_size - 1] = '\0'; 1113 return 0; 1114 } 1115 1116 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 1117 .dev_configure = enicpmd_dev_configure, 1118 .dev_start = enicpmd_dev_start, 1119 .dev_stop = enicpmd_dev_stop, 1120 .dev_set_link_up = NULL, 1121 .dev_set_link_down = NULL, 1122 .dev_close = enicpmd_dev_close, 1123 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 1124 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 1125 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 1126 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 1127 .link_update = enicpmd_dev_link_update, 1128 .stats_get = enicpmd_dev_stats_get, 1129 .stats_reset = enicpmd_dev_stats_reset, 1130 .queue_stats_mapping_set = NULL, 1131 .dev_infos_get = enicpmd_dev_info_get, 1132 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 1133 .mtu_set = enicpmd_mtu_set, 1134 .vlan_filter_set = NULL, 1135 .vlan_tpid_set = NULL, 1136 .vlan_offload_set = enicpmd_vlan_offload_set, 1137 .vlan_strip_queue_set = NULL, 1138 .rx_queue_start = enicpmd_dev_rx_queue_start, 1139 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 1140 .tx_queue_start = enicpmd_dev_tx_queue_start, 1141 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 1142 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 1143 .rx_queue_release = enicpmd_dev_rx_queue_release, 1144 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 1145 .tx_queue_release = enicpmd_dev_tx_queue_release, 1146 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 1147 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 1148 .rxq_info_get = enicpmd_dev_rxq_info_get, 1149 .txq_info_get = enicpmd_dev_txq_info_get, 1150 .rx_burst_mode_get = enicpmd_dev_rx_burst_mode_get, 1151 .tx_burst_mode_get = enicpmd_dev_tx_burst_mode_get, 1152 .dev_led_on = NULL, 1153 .dev_led_off = NULL, 1154 .flow_ctrl_get = NULL, 1155 .flow_ctrl_set = NULL, 1156 .priority_flow_ctrl_set = NULL, 1157 .mac_addr_add = enicpmd_add_mac_addr, 1158 .mac_addr_remove = enicpmd_remove_mac_addr, 1159 .mac_addr_set = enicpmd_set_mac_addr, 1160 .set_mc_addr_list = enicpmd_set_mc_addr_list, 1161 .filter_ctrl = enicpmd_dev_filter_ctrl, 1162 .reta_query = enicpmd_dev_rss_reta_query, 1163 .reta_update = enicpmd_dev_rss_reta_update, 1164 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 1165 .rss_hash_update = enicpmd_dev_rss_hash_update, 1166 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 1167 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 1168 .fw_version_get = enicpmd_dev_fw_version_get, 1169 }; 1170 1171 static int enic_parse_zero_one(const char *key, 1172 const char *value, 1173 void *opaque) 1174 { 1175 struct enic *enic; 1176 bool b; 1177 1178 enic = (struct enic *)opaque; 1179 if (strcmp(value, "0") == 0) { 1180 b = false; 1181 } else if (strcmp(value, "1") == 0) { 1182 b = true; 1183 } else { 1184 dev_err(enic, "Invalid value for %s" 1185 ": expected=0|1 given=%s\n", key, value); 1186 return -EINVAL; 1187 } 1188 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 1189 enic->disable_overlay = b; 1190 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 1191 enic->enable_avx2_rx = b; 1192 if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0) 1193 enic->geneve_opt_request = b; 1194 return 0; 1195 } 1196 1197 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 1198 const char *value, 1199 void *opaque) 1200 { 1201 struct enic *enic; 1202 1203 enic = (struct enic *)opaque; 1204 if (strcmp(value, "trunk") == 0) { 1205 /* Trunk mode: always tag */ 1206 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 1207 } else if (strcmp(value, "untag") == 0) { 1208 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 1209 enic->ig_vlan_rewrite_mode = 1210 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 1211 } else if (strcmp(value, "priority") == 0) { 1212 /* 1213 * Priority-tag default VLAN mode: priority tag (VLAN header 1214 * with ID=0) if VLAN = default 1215 */ 1216 enic->ig_vlan_rewrite_mode = 1217 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 1218 } else if (strcmp(value, "pass") == 0) { 1219 /* Pass through mode: do not touch tags */ 1220 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1221 } else { 1222 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 1223 ": expected=trunk|untag|priority|pass given=%s\n", 1224 value); 1225 return -EINVAL; 1226 } 1227 return 0; 1228 } 1229 1230 static int enic_check_devargs(struct rte_eth_dev *dev) 1231 { 1232 static const char *const valid_keys[] = { 1233 ENIC_DEVARG_DISABLE_OVERLAY, 1234 ENIC_DEVARG_ENABLE_AVX2_RX, 1235 ENIC_DEVARG_GENEVE_OPT, 1236 ENIC_DEVARG_IG_VLAN_REWRITE, 1237 NULL}; 1238 struct enic *enic = pmd_priv(dev); 1239 struct rte_kvargs *kvlist; 1240 1241 ENICPMD_FUNC_TRACE(); 1242 1243 enic->disable_overlay = false; 1244 enic->enable_avx2_rx = false; 1245 enic->geneve_opt_request = false; 1246 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1247 if (!dev->device->devargs) 1248 return 0; 1249 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1250 if (!kvlist) 1251 return -EINVAL; 1252 if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 1253 enic_parse_zero_one, enic) < 0 || 1254 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 1255 enic_parse_zero_one, enic) < 0 || 1256 rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT, 1257 enic_parse_zero_one, enic) < 0 || 1258 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1259 enic_parse_ig_vlan_rewrite, enic) < 0) { 1260 rte_kvargs_free(kvlist); 1261 return -EINVAL; 1262 } 1263 rte_kvargs_free(kvlist); 1264 return 0; 1265 } 1266 1267 /* Initialize the driver 1268 * It returns 0 on success. 1269 */ 1270 static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev) 1271 { 1272 struct rte_pci_device *pdev; 1273 struct rte_pci_addr *addr; 1274 struct enic *enic = pmd_priv(eth_dev); 1275 int err; 1276 1277 ENICPMD_FUNC_TRACE(); 1278 1279 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1280 eth_dev->rx_queue_count = enicpmd_dev_rx_queue_count; 1281 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1282 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1283 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1284 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1285 enic_pick_tx_handler(eth_dev); 1286 enic_pick_rx_handler(eth_dev); 1287 return 0; 1288 } 1289 /* Only the primary sets up adapter and other data in shared memory */ 1290 enic->port_id = eth_dev->data->port_id; 1291 enic->rte_dev = eth_dev; 1292 enic->dev_data = eth_dev->data; 1293 /* Let rte_eth_dev_close() release the port resources */ 1294 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1295 1296 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1297 rte_eth_copy_pci_info(eth_dev, pdev); 1298 enic->pdev = pdev; 1299 addr = &pdev->addr; 1300 1301 snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x", 1302 addr->domain, addr->bus, addr->devid, addr->function); 1303 1304 err = enic_check_devargs(eth_dev); 1305 if (err) 1306 return err; 1307 return enic_probe(enic); 1308 } 1309 1310 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1311 struct rte_pci_device *pci_dev) 1312 { 1313 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct enic), 1314 eth_enicpmd_dev_init); 1315 } 1316 1317 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1318 { 1319 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 1320 } 1321 1322 static struct rte_pci_driver rte_enic_pmd = { 1323 .id_table = pci_id_enic_map, 1324 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1325 .probe = eth_enic_pci_probe, 1326 .remove = eth_enic_pci_remove, 1327 }; 1328 1329 int dev_is_enic(struct rte_eth_dev *dev) 1330 { 1331 return dev->device->driver == &rte_enic_pmd.driver; 1332 } 1333 1334 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1335 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1336 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1337 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1338 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1339 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1340 ENIC_DEVARG_GENEVE_OPT "=0|1 " 1341 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1342