1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <dev_driver.h> 10 #include <rte_pci.h> 11 #include <bus_pci_driver.h> 12 #include <ethdev_driver.h> 13 #include <ethdev_pci.h> 14 #include <rte_geneve.h> 15 #include <rte_kvargs.h> 16 #include <rte_string_fns.h> 17 18 #include "vnic_intr.h" 19 #include "vnic_cq.h" 20 #include "vnic_wq.h" 21 #include "vnic_rq.h" 22 #include "vnic_enet.h" 23 #include "enic.h" 24 25 /* 26 * The set of PCI devices this driver supports 27 */ 28 #define CISCO_PCI_VENDOR_ID 0x1137 29 static const struct rte_pci_id pci_id_enic_map[] = { 30 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)}, 31 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)}, 32 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)}, 33 {.vendor_id = 0, /* sentinel */}, 34 }; 35 36 /* Supported link speeds of production VIC models */ 37 static const struct vic_speed_capa { 38 uint16_t sub_devid; 39 uint32_t capa; 40 } vic_speed_capa_map[] = { 41 { 0x0043, RTE_ETH_LINK_SPEED_10G }, /* VIC */ 42 { 0x0047, RTE_ETH_LINK_SPEED_10G }, /* P81E PCIe */ 43 { 0x0048, RTE_ETH_LINK_SPEED_10G }, /* M81KR Mezz */ 44 { 0x004f, RTE_ETH_LINK_SPEED_10G }, /* 1280 Mezz */ 45 { 0x0084, RTE_ETH_LINK_SPEED_10G }, /* 1240 MLOM */ 46 { 0x0085, RTE_ETH_LINK_SPEED_10G }, /* 1225 PCIe */ 47 { 0x00cd, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1285 PCIe */ 48 { 0x00ce, RTE_ETH_LINK_SPEED_10G }, /* 1225T PCIe */ 49 { 0x012a, RTE_ETH_LINK_SPEED_40G }, /* M4308 */ 50 { 0x012c, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1340 MLOM */ 51 { 0x012e, RTE_ETH_LINK_SPEED_10G }, /* 1227 PCIe */ 52 { 0x0137, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1380 Mezz */ 53 { 0x014d, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1385 PCIe */ 54 { 0x015d, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_40G }, /* 1387 MLOM */ 55 { 0x0215, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | 56 RTE_ETH_LINK_SPEED_40G }, /* 1440 Mezz */ 57 { 0x0216, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | 58 RTE_ETH_LINK_SPEED_40G }, /* 1480 MLOM */ 59 { 0x0217, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G }, /* 1455 PCIe */ 60 { 0x0218, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G }, /* 1457 MLOM */ 61 { 0x0219, RTE_ETH_LINK_SPEED_40G }, /* 1485 PCIe */ 62 { 0x021a, RTE_ETH_LINK_SPEED_40G }, /* 1487 MLOM */ 63 { 0x024a, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1495 PCIe */ 64 { 0x024b, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1497 MLOM */ 65 { 0, 0 }, /* End marker */ 66 }; 67 68 #define ENIC_DEVARG_CQ64 "cq64" 69 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 70 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 71 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 72 #define ENIC_DEVARG_REPRESENTOR "representor" 73 74 RTE_LOG_REGISTER_DEFAULT(enic_pmd_logtype, INFO); 75 76 static int 77 enicpmd_dev_flow_ops_get(struct rte_eth_dev *dev, 78 const struct rte_flow_ops **ops) 79 { 80 struct enic *enic = pmd_priv(dev); 81 82 ENICPMD_FUNC_TRACE(); 83 84 if (enic->flow_filter_mode == FILTER_FLOWMAN) 85 *ops = &enic_fm_flow_ops; 86 else 87 *ops = &enic_flow_ops; 88 return 0; 89 } 90 91 static void enicpmd_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 92 { 93 void *txq = dev->data->tx_queues[qid]; 94 95 ENICPMD_FUNC_TRACE(); 96 97 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 98 return; 99 100 enic_free_wq(txq); 101 } 102 103 static int enicpmd_dev_setup_intr(struct enic *enic) 104 { 105 int ret; 106 unsigned int index; 107 108 ENICPMD_FUNC_TRACE(); 109 110 /* Are we done with the init of all the queues? */ 111 for (index = 0; index < enic->cq_count; index++) { 112 if (!enic->cq[index].ctrl) 113 break; 114 } 115 if (enic->cq_count != index) 116 return 0; 117 for (index = 0; index < enic->wq_count; index++) { 118 if (!enic->wq[index].ctrl) 119 break; 120 } 121 if (enic->wq_count != index) 122 return 0; 123 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 124 for (index = 0; index < enic->rq_count; index++) { 125 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 126 break; 127 } 128 if (enic->rq_count != index) 129 return 0; 130 131 ret = enic_alloc_intr_resources(enic); 132 if (ret) { 133 dev_err(enic, "alloc intr failed\n"); 134 return ret; 135 } 136 enic_init_vnic_resources(enic); 137 138 ret = enic_setup_finish(enic); 139 if (ret) 140 dev_err(enic, "setup could not be finished\n"); 141 142 return ret; 143 } 144 145 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 146 uint16_t queue_idx, 147 uint16_t nb_desc, 148 unsigned int socket_id, 149 const struct rte_eth_txconf *tx_conf) 150 { 151 int ret; 152 struct enic *enic = pmd_priv(eth_dev); 153 struct vnic_wq *wq; 154 155 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 156 return -E_RTE_SECONDARY; 157 158 ENICPMD_FUNC_TRACE(); 159 RTE_ASSERT(queue_idx < enic->conf_wq_count); 160 wq = &enic->wq[queue_idx]; 161 wq->offloads = tx_conf->offloads | 162 eth_dev->data->dev_conf.txmode.offloads; 163 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 164 165 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 166 if (ret) { 167 dev_err(enic, "error in allocating wq\n"); 168 return ret; 169 } 170 171 return enicpmd_dev_setup_intr(enic); 172 } 173 174 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 175 uint16_t queue_idx) 176 { 177 struct enic *enic = pmd_priv(eth_dev); 178 179 ENICPMD_FUNC_TRACE(); 180 181 enic_start_wq(enic, queue_idx); 182 183 return 0; 184 } 185 186 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 187 uint16_t queue_idx) 188 { 189 int ret; 190 struct enic *enic = pmd_priv(eth_dev); 191 192 ENICPMD_FUNC_TRACE(); 193 194 ret = enic_stop_wq(enic, queue_idx); 195 if (ret) 196 dev_err(enic, "error in stopping wq %d\n", queue_idx); 197 198 return ret; 199 } 200 201 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 202 uint16_t queue_idx) 203 { 204 struct enic *enic = pmd_priv(eth_dev); 205 206 ENICPMD_FUNC_TRACE(); 207 208 enic_start_rq(enic, queue_idx); 209 210 return 0; 211 } 212 213 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 214 uint16_t queue_idx) 215 { 216 int ret; 217 struct enic *enic = pmd_priv(eth_dev); 218 219 ENICPMD_FUNC_TRACE(); 220 221 ret = enic_stop_rq(enic, queue_idx); 222 if (ret) 223 dev_err(enic, "error in stopping rq %d\n", queue_idx); 224 225 return ret; 226 } 227 228 static void enicpmd_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 229 { 230 void *rxq = dev->data->rx_queues[qid]; 231 232 ENICPMD_FUNC_TRACE(); 233 234 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 235 return; 236 237 enic_free_rq(rxq); 238 } 239 240 static uint32_t enicpmd_dev_rx_queue_count(void *rx_queue) 241 { 242 struct enic *enic; 243 struct vnic_rq *sop_rq; 244 uint32_t queue_count = 0; 245 struct vnic_cq *cq; 246 uint32_t cq_tail; 247 uint16_t cq_idx; 248 249 sop_rq = rx_queue; 250 enic = vnic_dev_priv(sop_rq->vdev); 251 cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)]; 252 cq_idx = cq->to_clean; 253 254 cq_tail = ioread32(&cq->ctrl->cq_tail); 255 256 if (cq_tail < cq_idx) 257 cq_tail += cq->ring.desc_count; 258 259 queue_count = cq_tail - cq_idx; 260 261 return queue_count; 262 } 263 264 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 265 uint16_t queue_idx, 266 uint16_t nb_desc, 267 unsigned int socket_id, 268 const struct rte_eth_rxconf *rx_conf, 269 struct rte_mempool *mp) 270 { 271 int ret; 272 struct enic *enic = pmd_priv(eth_dev); 273 274 ENICPMD_FUNC_TRACE(); 275 276 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 277 return -E_RTE_SECONDARY; 278 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 279 eth_dev->data->rx_queues[queue_idx] = 280 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 281 282 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 283 rx_conf->rx_free_thresh); 284 if (ret) { 285 dev_err(enic, "error in allocating rq\n"); 286 return ret; 287 } 288 289 return enicpmd_dev_setup_intr(enic); 290 } 291 292 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 293 { 294 struct enic *enic = pmd_priv(eth_dev); 295 uint64_t offloads; 296 297 ENICPMD_FUNC_TRACE(); 298 299 offloads = eth_dev->data->dev_conf.rxmode.offloads; 300 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 301 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 302 enic->ig_vlan_strip_en = 1; 303 else 304 enic->ig_vlan_strip_en = 0; 305 } 306 307 return enic_set_vlan_strip(enic); 308 } 309 310 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 311 { 312 int ret; 313 int mask; 314 struct enic *enic = pmd_priv(eth_dev); 315 316 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 317 return -E_RTE_SECONDARY; 318 319 ENICPMD_FUNC_TRACE(); 320 ret = enic_set_vnic_res(enic); 321 if (ret) { 322 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 323 return ret; 324 } 325 326 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 327 eth_dev->data->dev_conf.rxmode.offloads |= 328 RTE_ETH_RX_OFFLOAD_RSS_HASH; 329 330 enic->mc_count = 0; 331 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 332 RTE_ETH_RX_OFFLOAD_CHECKSUM); 333 /* All vlan offload masks to apply the current settings */ 334 mask = RTE_ETH_VLAN_STRIP_MASK | 335 RTE_ETH_VLAN_FILTER_MASK | 336 RTE_ETH_VLAN_EXTEND_MASK; 337 ret = enicpmd_vlan_offload_set(eth_dev, mask); 338 if (ret) { 339 dev_err(enic, "Failed to configure VLAN offloads\n"); 340 return ret; 341 } 342 /* 343 * Initialize RSS with the default reta and key. If the user key is 344 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 345 * default key. 346 */ 347 return enic_init_rss_nic_cfg(enic); 348 } 349 350 /* Start the device. 351 * It returns 0 on success. 352 */ 353 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 354 { 355 struct enic *enic = pmd_priv(eth_dev); 356 357 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 358 return -E_RTE_SECONDARY; 359 360 ENICPMD_FUNC_TRACE(); 361 return enic_enable(enic); 362 } 363 364 /* 365 * Stop device: disable rx and tx functions to allow for reconfiguring. 366 */ 367 static int enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 368 { 369 struct rte_eth_link link; 370 struct enic *enic = pmd_priv(eth_dev); 371 uint16_t i; 372 373 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 374 return 0; 375 376 ENICPMD_FUNC_TRACE(); 377 enic_disable(enic); 378 379 memset(&link, 0, sizeof(link)); 380 rte_eth_linkstatus_set(eth_dev, &link); 381 382 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) 383 eth_dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 384 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) 385 eth_dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 386 387 return 0; 388 } 389 390 /* 391 * Stop device. 392 */ 393 static int enicpmd_dev_close(struct rte_eth_dev *eth_dev) 394 { 395 struct enic *enic = pmd_priv(eth_dev); 396 397 ENICPMD_FUNC_TRACE(); 398 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 399 return 0; 400 401 enic_remove(enic); 402 403 return 0; 404 } 405 406 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 407 __rte_unused int wait_to_complete) 408 { 409 ENICPMD_FUNC_TRACE(); 410 return enic_link_update(eth_dev); 411 } 412 413 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 414 struct rte_eth_stats *stats) 415 { 416 struct enic *enic = pmd_priv(eth_dev); 417 418 ENICPMD_FUNC_TRACE(); 419 return enic_dev_stats_get(enic, stats); 420 } 421 422 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 423 { 424 struct enic *enic = pmd_priv(eth_dev); 425 426 ENICPMD_FUNC_TRACE(); 427 return enic_dev_stats_clear(enic); 428 } 429 430 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) 431 { 432 const struct vic_speed_capa *m; 433 struct rte_pci_device *pdev; 434 uint16_t id; 435 436 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 437 id = pdev->id.subsystem_device_id; 438 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { 439 if (m->sub_devid == id) 440 return m->capa; 441 } 442 /* 1300 and later models are at least 40G */ 443 if (id >= 0x0100) 444 return RTE_ETH_LINK_SPEED_40G; 445 /* VFs have subsystem id 0, check device id */ 446 if (id == 0) { 447 /* Newer VF implies at least 40G model */ 448 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN) 449 return RTE_ETH_LINK_SPEED_40G; 450 } 451 return RTE_ETH_LINK_SPEED_10G; 452 } 453 454 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 455 struct rte_eth_dev_info *device_info) 456 { 457 struct enic *enic = pmd_priv(eth_dev); 458 459 ENICPMD_FUNC_TRACE(); 460 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 461 device_info->max_rx_queues = enic->conf_rq_count / 2; 462 device_info->max_tx_queues = enic->conf_wq_count; 463 device_info->min_rx_bufsize = ENIC_MIN_MTU; 464 /* "Max" mtu is not a typo. HW receives packet sizes up to the 465 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 466 * a hint to the driver to size receive buffers accordingly so that 467 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 468 * the user decide the buffer size via rxmode.mtu, basically 469 * ignoring vNIC mtu. 470 */ 471 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 472 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS; 473 device_info->min_mtu = ENIC_MIN_MTU; 474 device_info->max_mtu = enic->max_mtu; 475 device_info->rx_offload_capa = enic->rx_offload_capa; 476 device_info->tx_offload_capa = enic->tx_offload_capa; 477 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 478 device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 479 device_info->default_rxconf = (struct rte_eth_rxconf) { 480 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 481 }; 482 device_info->reta_size = enic->reta_size; 483 device_info->hash_key_size = enic->hash_key_size; 484 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 485 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 486 .nb_max = enic->config.rq_desc_count, 487 .nb_min = ENIC_MIN_RQ_DESCS, 488 .nb_align = ENIC_ALIGN_DESCS, 489 }; 490 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 491 .nb_max = enic->config.wq_desc_count, 492 .nb_min = ENIC_MIN_WQ_DESCS, 493 .nb_align = ENIC_ALIGN_DESCS, 494 .nb_seg_max = ENIC_TX_XMIT_MAX, 495 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 496 }; 497 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 498 .burst_size = ENIC_DEFAULT_RX_BURST, 499 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 500 ENIC_DEFAULT_RX_RING_SIZE), 501 .nb_queues = ENIC_DEFAULT_RX_RINGS, 502 }; 503 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 504 .burst_size = ENIC_DEFAULT_TX_BURST, 505 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 506 ENIC_DEFAULT_TX_RING_SIZE), 507 .nb_queues = ENIC_DEFAULT_TX_RINGS, 508 }; 509 device_info->speed_capa = speed_capa_from_pci_id(eth_dev); 510 511 return 0; 512 } 513 514 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) 515 { 516 static const uint32_t ptypes[] = { 517 RTE_PTYPE_L2_ETHER, 518 RTE_PTYPE_L2_ETHER_VLAN, 519 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 520 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 521 RTE_PTYPE_L4_TCP, 522 RTE_PTYPE_L4_UDP, 523 RTE_PTYPE_L4_FRAG, 524 RTE_PTYPE_L4_NONFRAG, 525 RTE_PTYPE_UNKNOWN 526 }; 527 static const uint32_t ptypes_overlay[] = { 528 RTE_PTYPE_L2_ETHER, 529 RTE_PTYPE_L2_ETHER_VLAN, 530 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 531 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 532 RTE_PTYPE_L4_TCP, 533 RTE_PTYPE_L4_UDP, 534 RTE_PTYPE_L4_FRAG, 535 RTE_PTYPE_L4_NONFRAG, 536 RTE_PTYPE_TUNNEL_GRENAT, 537 RTE_PTYPE_INNER_L2_ETHER, 538 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 539 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 540 RTE_PTYPE_INNER_L4_TCP, 541 RTE_PTYPE_INNER_L4_UDP, 542 RTE_PTYPE_INNER_L4_FRAG, 543 RTE_PTYPE_INNER_L4_NONFRAG, 544 RTE_PTYPE_UNKNOWN 545 }; 546 547 if (dev->rx_pkt_burst != rte_eth_pkt_burst_dummy && 548 dev->rx_pkt_burst != NULL) { 549 struct enic *enic = pmd_priv(dev); 550 if (enic->overlay_offload) 551 return ptypes_overlay; 552 else 553 return ptypes; 554 } 555 return NULL; 556 } 557 558 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 559 { 560 struct enic *enic = pmd_priv(eth_dev); 561 int ret; 562 563 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 564 return -E_RTE_SECONDARY; 565 566 ENICPMD_FUNC_TRACE(); 567 568 enic->promisc = 1; 569 ret = enic_add_packet_filter(enic); 570 if (ret != 0) 571 enic->promisc = 0; 572 573 return ret; 574 } 575 576 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 577 { 578 struct enic *enic = pmd_priv(eth_dev); 579 int ret; 580 581 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 582 return -E_RTE_SECONDARY; 583 584 ENICPMD_FUNC_TRACE(); 585 enic->promisc = 0; 586 ret = enic_add_packet_filter(enic); 587 if (ret != 0) 588 enic->promisc = 1; 589 590 return ret; 591 } 592 593 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 594 { 595 struct enic *enic = pmd_priv(eth_dev); 596 int ret; 597 598 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 599 return -E_RTE_SECONDARY; 600 601 ENICPMD_FUNC_TRACE(); 602 enic->allmulti = 1; 603 ret = enic_add_packet_filter(enic); 604 if (ret != 0) 605 enic->allmulti = 0; 606 607 return ret; 608 } 609 610 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 611 { 612 struct enic *enic = pmd_priv(eth_dev); 613 int ret; 614 615 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 616 return -E_RTE_SECONDARY; 617 618 ENICPMD_FUNC_TRACE(); 619 enic->allmulti = 0; 620 ret = enic_add_packet_filter(enic); 621 if (ret != 0) 622 enic->allmulti = 1; 623 624 return ret; 625 } 626 627 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 628 struct rte_ether_addr *mac_addr, 629 __rte_unused uint32_t index, __rte_unused uint32_t pool) 630 { 631 struct enic *enic = pmd_priv(eth_dev); 632 633 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 634 return -E_RTE_SECONDARY; 635 636 ENICPMD_FUNC_TRACE(); 637 return enic_set_mac_address(enic, mac_addr->addr_bytes); 638 } 639 640 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 641 { 642 struct enic *enic = pmd_priv(eth_dev); 643 644 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 645 return; 646 647 ENICPMD_FUNC_TRACE(); 648 if (enic_del_mac_address(enic, index)) 649 dev_err(enic, "del mac addr failed\n"); 650 } 651 652 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 653 struct rte_ether_addr *addr) 654 { 655 struct enic *enic = pmd_priv(eth_dev); 656 int ret; 657 658 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 659 return -E_RTE_SECONDARY; 660 661 ENICPMD_FUNC_TRACE(); 662 ret = enic_del_mac_address(enic, 0); 663 if (ret) 664 return ret; 665 return enic_set_mac_address(enic, addr->addr_bytes); 666 } 667 668 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add) 669 { 670 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 671 672 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr); 673 ENICPMD_LOG(DEBUG, " %s address %s\n", 674 add ? "add" : "remove", mac_str); 675 } 676 677 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev, 678 struct rte_ether_addr *mc_addr_set, 679 uint32_t nb_mc_addr) 680 { 681 struct enic *enic = pmd_priv(eth_dev); 682 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 683 struct rte_ether_addr *addr; 684 uint32_t i, j; 685 int ret; 686 687 ENICPMD_FUNC_TRACE(); 688 689 /* Validate the given addresses first */ 690 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) { 691 addr = &mc_addr_set[i]; 692 if (!rte_is_multicast_ether_addr(addr) || 693 rte_is_broadcast_ether_addr(addr)) { 694 rte_ether_format_addr(mac_str, 695 RTE_ETHER_ADDR_FMT_SIZE, addr); 696 ENICPMD_LOG(ERR, " invalid multicast address %s\n", 697 mac_str); 698 return -EINVAL; 699 } 700 } 701 702 /* Flush all if requested */ 703 if (nb_mc_addr == 0 || mc_addr_set == NULL) { 704 ENICPMD_LOG(DEBUG, " flush multicast addresses\n"); 705 for (i = 0; i < enic->mc_count; i++) { 706 addr = &enic->mc_addrs[i]; 707 debug_log_add_del_addr(addr, false); 708 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 709 if (ret) 710 return ret; 711 } 712 enic->mc_count = 0; 713 return 0; 714 } 715 716 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) { 717 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n", 718 ENIC_MULTICAST_PERFECT_FILTERS); 719 return -ENOSPC; 720 } 721 /* 722 * devcmd is slow, so apply the difference instead of flushing and 723 * adding everything. 724 * 1. Delete addresses on the NIC but not on the host 725 */ 726 for (i = 0; i < enic->mc_count; i++) { 727 addr = &enic->mc_addrs[i]; 728 for (j = 0; j < nb_mc_addr; j++) { 729 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) 730 break; 731 } 732 if (j < nb_mc_addr) 733 continue; 734 debug_log_add_del_addr(addr, false); 735 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 736 if (ret) 737 return ret; 738 } 739 /* 2. Add addresses on the host but not on the NIC */ 740 for (i = 0; i < nb_mc_addr; i++) { 741 addr = &mc_addr_set[i]; 742 for (j = 0; j < enic->mc_count; j++) { 743 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j])) 744 break; 745 } 746 if (j < enic->mc_count) 747 continue; 748 debug_log_add_del_addr(addr, true); 749 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes); 750 if (ret) 751 return ret; 752 } 753 /* Keep a copy so we can flush/apply later on.. */ 754 memcpy(enic->mc_addrs, mc_addr_set, 755 nb_mc_addr * sizeof(struct rte_ether_addr)); 756 enic->mc_count = nb_mc_addr; 757 return 0; 758 } 759 760 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 761 { 762 struct enic *enic = pmd_priv(eth_dev); 763 764 ENICPMD_FUNC_TRACE(); 765 return enic_set_mtu(enic, mtu); 766 } 767 768 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 769 struct rte_eth_rss_reta_entry64 770 *reta_conf, 771 uint16_t reta_size) 772 { 773 struct enic *enic = pmd_priv(dev); 774 uint16_t i, idx, shift; 775 776 ENICPMD_FUNC_TRACE(); 777 if (reta_size != ENIC_RSS_RETA_SIZE) { 778 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 779 reta_size, ENIC_RSS_RETA_SIZE); 780 return -EINVAL; 781 } 782 783 for (i = 0; i < reta_size; i++) { 784 idx = i / RTE_ETH_RETA_GROUP_SIZE; 785 shift = i % RTE_ETH_RETA_GROUP_SIZE; 786 if (reta_conf[idx].mask & (1ULL << shift)) 787 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 788 enic->rss_cpu.cpu[i / 4].b[i % 4]); 789 } 790 791 return 0; 792 } 793 794 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 795 struct rte_eth_rss_reta_entry64 796 *reta_conf, 797 uint16_t reta_size) 798 { 799 struct enic *enic = pmd_priv(dev); 800 union vnic_rss_cpu rss_cpu; 801 uint16_t i, idx, shift; 802 803 ENICPMD_FUNC_TRACE(); 804 if (reta_size != ENIC_RSS_RETA_SIZE) { 805 dev_err(enic, "reta_update: wrong reta_size. given=%u" 806 " expected=%u\n", 807 reta_size, ENIC_RSS_RETA_SIZE); 808 return -EINVAL; 809 } 810 /* 811 * Start with the current reta and modify it per reta_conf, as we 812 * need to push the entire reta even if we only modify one entry. 813 */ 814 rss_cpu = enic->rss_cpu; 815 for (i = 0; i < reta_size; i++) { 816 idx = i / RTE_ETH_RETA_GROUP_SIZE; 817 shift = i % RTE_ETH_RETA_GROUP_SIZE; 818 if (reta_conf[idx].mask & (1ULL << shift)) 819 rss_cpu.cpu[i / 4].b[i % 4] = 820 enic_rte_rq_idx_to_sop_idx( 821 reta_conf[idx].reta[shift]); 822 } 823 return enic_set_rss_reta(enic, &rss_cpu); 824 } 825 826 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 827 struct rte_eth_rss_conf *rss_conf) 828 { 829 struct enic *enic = pmd_priv(dev); 830 831 ENICPMD_FUNC_TRACE(); 832 return enic_set_rss_conf(enic, rss_conf); 833 } 834 835 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 836 struct rte_eth_rss_conf *rss_conf) 837 { 838 struct enic *enic = pmd_priv(dev); 839 840 ENICPMD_FUNC_TRACE(); 841 if (rss_conf == NULL) 842 return -EINVAL; 843 if (rss_conf->rss_key != NULL && 844 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 845 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 846 " expected=%u+\n", 847 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 848 return -EINVAL; 849 } 850 rss_conf->rss_hf = enic->rss_hf; 851 if (rss_conf->rss_key != NULL) { 852 int i; 853 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 854 rss_conf->rss_key[i] = 855 enic->rss_key.key[i / 10].b[i % 10]; 856 } 857 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 858 } 859 return 0; 860 } 861 862 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 863 uint16_t rx_queue_id, 864 struct rte_eth_rxq_info *qinfo) 865 { 866 struct enic *enic = pmd_priv(dev); 867 struct vnic_rq *rq_sop; 868 struct vnic_rq *rq_data; 869 struct rte_eth_rxconf *conf; 870 uint16_t sop_queue_idx; 871 uint16_t data_queue_idx; 872 873 ENICPMD_FUNC_TRACE(); 874 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 875 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic); 876 rq_sop = &enic->rq[sop_queue_idx]; 877 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 878 qinfo->mp = rq_sop->mp; 879 qinfo->scattered_rx = rq_sop->data_queue_enable; 880 qinfo->nb_desc = rq_sop->ring.desc_count; 881 if (qinfo->scattered_rx) 882 qinfo->nb_desc += rq_data->ring.desc_count; 883 conf = &qinfo->conf; 884 memset(conf, 0, sizeof(*conf)); 885 conf->rx_free_thresh = rq_sop->rx_free_thresh; 886 conf->rx_drop_en = 1; 887 /* 888 * Except VLAN stripping (port setting), all the checksum offloads 889 * are always enabled. 890 */ 891 conf->offloads = enic->rx_offload_capa; 892 if (!enic->ig_vlan_strip_en) 893 conf->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 894 /* rx_thresh and other fields are not applicable for enic */ 895 } 896 897 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 898 uint16_t tx_queue_id, 899 struct rte_eth_txq_info *qinfo) 900 { 901 struct enic *enic = pmd_priv(dev); 902 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 903 904 ENICPMD_FUNC_TRACE(); 905 qinfo->nb_desc = wq->ring.desc_count; 906 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 907 qinfo->conf.offloads = wq->offloads; 908 /* tx_thresh, and all the other fields are not applicable for enic */ 909 } 910 911 static int enicpmd_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 912 __rte_unused uint16_t queue_id, 913 struct rte_eth_burst_mode *mode) 914 { 915 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 916 struct enic *enic = pmd_priv(dev); 917 const char *info_str = NULL; 918 int ret = -EINVAL; 919 920 ENICPMD_FUNC_TRACE(); 921 if (enic->use_noscatter_vec_rx_handler) 922 info_str = "Vector AVX2 No Scatter"; 923 else if (pkt_burst == enic_noscatter_recv_pkts) 924 info_str = "Scalar No Scatter"; 925 else if (pkt_burst == enic_recv_pkts) 926 info_str = "Scalar"; 927 else if (pkt_burst == enic_recv_pkts_64) 928 info_str = "Scalar 64B Completion"; 929 if (info_str) { 930 strlcpy(mode->info, info_str, sizeof(mode->info)); 931 ret = 0; 932 } 933 return ret; 934 } 935 936 static int enicpmd_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 937 __rte_unused uint16_t queue_id, 938 struct rte_eth_burst_mode *mode) 939 { 940 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 941 const char *info_str = NULL; 942 int ret = -EINVAL; 943 944 ENICPMD_FUNC_TRACE(); 945 if (pkt_burst == enic_simple_xmit_pkts) 946 info_str = "Scalar Simplified"; 947 else if (pkt_burst == enic_xmit_pkts) 948 info_str = "Scalar"; 949 if (info_str) { 950 strlcpy(mode->info, info_str, sizeof(mode->info)); 951 ret = 0; 952 } 953 return ret; 954 } 955 956 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 957 uint16_t rx_queue_id) 958 { 959 struct enic *enic = pmd_priv(eth_dev); 960 961 ENICPMD_FUNC_TRACE(); 962 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 963 return 0; 964 } 965 966 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 967 uint16_t rx_queue_id) 968 { 969 struct enic *enic = pmd_priv(eth_dev); 970 971 ENICPMD_FUNC_TRACE(); 972 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 973 return 0; 974 } 975 976 static int udp_tunnel_common_check(struct enic *enic, 977 struct rte_eth_udp_tunnel *tnl) 978 { 979 if (tnl->prot_type != RTE_ETH_TUNNEL_TYPE_VXLAN && 980 tnl->prot_type != RTE_ETH_TUNNEL_TYPE_GENEVE) 981 return -ENOTSUP; 982 if (!enic->overlay_offload) { 983 ENICPMD_LOG(DEBUG, " overlay offload is not supported\n"); 984 return -ENOTSUP; 985 } 986 return 0; 987 } 988 989 static int update_tunnel_port(struct enic *enic, uint16_t port, bool vxlan) 990 { 991 uint8_t cfg; 992 993 cfg = vxlan ? OVERLAY_CFG_VXLAN_PORT_UPDATE : 994 OVERLAY_CFG_GENEVE_PORT_UPDATE; 995 if (vnic_dev_overlay_offload_cfg(enic->vdev, cfg, port)) { 996 ENICPMD_LOG(DEBUG, " failed to update tunnel port\n"); 997 return -EINVAL; 998 } 999 ENICPMD_LOG(DEBUG, " updated %s port to %u\n", 1000 vxlan ? "vxlan" : "geneve", port); 1001 if (vxlan) 1002 enic->vxlan_port = port; 1003 else 1004 enic->geneve_port = port; 1005 return 0; 1006 } 1007 1008 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 1009 struct rte_eth_udp_tunnel *tnl) 1010 { 1011 struct enic *enic = pmd_priv(eth_dev); 1012 uint16_t port; 1013 bool vxlan; 1014 int ret; 1015 1016 ENICPMD_FUNC_TRACE(); 1017 ret = udp_tunnel_common_check(enic, tnl); 1018 if (ret) 1019 return ret; 1020 vxlan = (tnl->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN); 1021 if (vxlan) 1022 port = enic->vxlan_port; 1023 else 1024 port = enic->geneve_port; 1025 /* 1026 * The NIC has 1 configurable port number per tunnel type. 1027 * "Adding" a new port number replaces it. 1028 */ 1029 if (tnl->udp_port == port || tnl->udp_port == 0) { 1030 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n", 1031 tnl->udp_port); 1032 return -EINVAL; 1033 } 1034 return update_tunnel_port(enic, tnl->udp_port, vxlan); 1035 } 1036 1037 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 1038 struct rte_eth_udp_tunnel *tnl) 1039 { 1040 struct enic *enic = pmd_priv(eth_dev); 1041 uint16_t port; 1042 bool vxlan; 1043 int ret; 1044 1045 ENICPMD_FUNC_TRACE(); 1046 ret = udp_tunnel_common_check(enic, tnl); 1047 if (ret) 1048 return ret; 1049 vxlan = (tnl->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN); 1050 if (vxlan) 1051 port = enic->vxlan_port; 1052 else 1053 port = enic->geneve_port; 1054 /* 1055 * Clear the previously set port number and restore the 1056 * hardware default port number. Some drivers disable VXLAN 1057 * offloads when there are no configured port numbers. But 1058 * enic does not do that as VXLAN is part of overlay offload, 1059 * which is tied to inner RSS and TSO. 1060 */ 1061 if (tnl->udp_port != port) { 1062 ENICPMD_LOG(DEBUG, " %u is not a configured tunnel port\n", 1063 tnl->udp_port); 1064 return -EINVAL; 1065 } 1066 port = vxlan ? RTE_VXLAN_DEFAULT_PORT : RTE_GENEVE_DEFAULT_PORT; 1067 return update_tunnel_port(enic, port, vxlan); 1068 } 1069 1070 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev, 1071 char *fw_version, size_t fw_size) 1072 { 1073 struct vnic_devcmd_fw_info *info; 1074 struct enic *enic; 1075 int ret; 1076 1077 ENICPMD_FUNC_TRACE(); 1078 1079 enic = pmd_priv(eth_dev); 1080 ret = vnic_dev_fw_info(enic->vdev, &info); 1081 if (ret) 1082 return ret; 1083 ret = snprintf(fw_version, fw_size, "%s %s", 1084 info->fw_version, info->fw_build); 1085 if (ret < 0) 1086 return -EINVAL; 1087 1088 ret += 1; /* add the size of '\0' */ 1089 if (fw_size < (size_t)ret) 1090 return ret; 1091 else 1092 return 0; 1093 } 1094 1095 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 1096 .dev_configure = enicpmd_dev_configure, 1097 .dev_start = enicpmd_dev_start, 1098 .dev_stop = enicpmd_dev_stop, 1099 .dev_set_link_up = NULL, 1100 .dev_set_link_down = NULL, 1101 .dev_close = enicpmd_dev_close, 1102 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 1103 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 1104 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 1105 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 1106 .link_update = enicpmd_dev_link_update, 1107 .stats_get = enicpmd_dev_stats_get, 1108 .stats_reset = enicpmd_dev_stats_reset, 1109 .queue_stats_mapping_set = NULL, 1110 .dev_infos_get = enicpmd_dev_info_get, 1111 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 1112 .mtu_set = enicpmd_mtu_set, 1113 .vlan_filter_set = NULL, 1114 .vlan_tpid_set = NULL, 1115 .vlan_offload_set = enicpmd_vlan_offload_set, 1116 .vlan_strip_queue_set = NULL, 1117 .rx_queue_start = enicpmd_dev_rx_queue_start, 1118 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 1119 .tx_queue_start = enicpmd_dev_tx_queue_start, 1120 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 1121 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 1122 .rx_queue_release = enicpmd_dev_rx_queue_release, 1123 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 1124 .tx_queue_release = enicpmd_dev_tx_queue_release, 1125 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 1126 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 1127 .rxq_info_get = enicpmd_dev_rxq_info_get, 1128 .txq_info_get = enicpmd_dev_txq_info_get, 1129 .rx_burst_mode_get = enicpmd_dev_rx_burst_mode_get, 1130 .tx_burst_mode_get = enicpmd_dev_tx_burst_mode_get, 1131 .dev_led_on = NULL, 1132 .dev_led_off = NULL, 1133 .flow_ctrl_get = NULL, 1134 .flow_ctrl_set = NULL, 1135 .priority_flow_ctrl_set = NULL, 1136 .mac_addr_add = enicpmd_add_mac_addr, 1137 .mac_addr_remove = enicpmd_remove_mac_addr, 1138 .mac_addr_set = enicpmd_set_mac_addr, 1139 .set_mc_addr_list = enicpmd_set_mc_addr_list, 1140 .flow_ops_get = enicpmd_dev_flow_ops_get, 1141 .reta_query = enicpmd_dev_rss_reta_query, 1142 .reta_update = enicpmd_dev_rss_reta_update, 1143 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 1144 .rss_hash_update = enicpmd_dev_rss_hash_update, 1145 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 1146 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 1147 .fw_version_get = enicpmd_dev_fw_version_get, 1148 }; 1149 1150 static int enic_parse_zero_one(const char *key, 1151 const char *value, 1152 void *opaque) 1153 { 1154 struct enic *enic; 1155 bool b; 1156 1157 enic = (struct enic *)opaque; 1158 if (strcmp(value, "0") == 0) { 1159 b = false; 1160 } else if (strcmp(value, "1") == 0) { 1161 b = true; 1162 } else { 1163 dev_err(enic, "Invalid value for %s" 1164 ": expected=0|1 given=%s\n", key, value); 1165 return -EINVAL; 1166 } 1167 if (strcmp(key, ENIC_DEVARG_CQ64) == 0) 1168 enic->cq64_request = b; 1169 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 1170 enic->disable_overlay = b; 1171 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 1172 enic->enable_avx2_rx = b; 1173 return 0; 1174 } 1175 1176 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 1177 const char *value, 1178 void *opaque) 1179 { 1180 struct enic *enic; 1181 1182 enic = (struct enic *)opaque; 1183 if (strcmp(value, "trunk") == 0) { 1184 /* Trunk mode: always tag */ 1185 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 1186 } else if (strcmp(value, "untag") == 0) { 1187 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 1188 enic->ig_vlan_rewrite_mode = 1189 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 1190 } else if (strcmp(value, "priority") == 0) { 1191 /* 1192 * Priority-tag default VLAN mode: priority tag (VLAN header 1193 * with ID=0) if VLAN = default 1194 */ 1195 enic->ig_vlan_rewrite_mode = 1196 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 1197 } else if (strcmp(value, "pass") == 0) { 1198 /* Pass through mode: do not touch tags */ 1199 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1200 } else { 1201 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 1202 ": expected=trunk|untag|priority|pass given=%s\n", 1203 value); 1204 return -EINVAL; 1205 } 1206 return 0; 1207 } 1208 1209 static int enic_check_devargs(struct rte_eth_dev *dev) 1210 { 1211 static const char *const valid_keys[] = { 1212 ENIC_DEVARG_CQ64, 1213 ENIC_DEVARG_DISABLE_OVERLAY, 1214 ENIC_DEVARG_ENABLE_AVX2_RX, 1215 ENIC_DEVARG_IG_VLAN_REWRITE, 1216 ENIC_DEVARG_REPRESENTOR, 1217 NULL}; 1218 struct enic *enic = pmd_priv(dev); 1219 struct rte_kvargs *kvlist; 1220 1221 ENICPMD_FUNC_TRACE(); 1222 1223 enic->cq64_request = true; /* Use 64B entry if available */ 1224 enic->disable_overlay = false; 1225 enic->enable_avx2_rx = false; 1226 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1227 if (!dev->device->devargs) 1228 return 0; 1229 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1230 if (!kvlist) 1231 return -EINVAL; 1232 if (rte_kvargs_process(kvlist, ENIC_DEVARG_CQ64, 1233 enic_parse_zero_one, enic) < 0 || 1234 rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 1235 enic_parse_zero_one, enic) < 0 || 1236 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 1237 enic_parse_zero_one, enic) < 0 || 1238 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1239 enic_parse_ig_vlan_rewrite, enic) < 0) { 1240 rte_kvargs_free(kvlist); 1241 return -EINVAL; 1242 } 1243 rte_kvargs_free(kvlist); 1244 return 0; 1245 } 1246 1247 /* Initialize the driver for PF */ 1248 static int eth_enic_dev_init(struct rte_eth_dev *eth_dev, 1249 void *init_params __rte_unused) 1250 { 1251 struct rte_pci_device *pdev; 1252 struct rte_pci_addr *addr; 1253 struct enic *enic = pmd_priv(eth_dev); 1254 int err; 1255 1256 ENICPMD_FUNC_TRACE(); 1257 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1258 eth_dev->rx_queue_count = enicpmd_dev_rx_queue_count; 1259 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1260 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1261 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1262 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1263 enic_pick_tx_handler(eth_dev); 1264 enic_pick_rx_handler(eth_dev); 1265 return 0; 1266 } 1267 /* Only the primary sets up adapter and other data in shared memory */ 1268 enic->port_id = eth_dev->data->port_id; 1269 enic->rte_dev = eth_dev; 1270 enic->dev_data = eth_dev->data; 1271 1272 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1273 rte_eth_copy_pci_info(eth_dev, pdev); 1274 enic->pdev = pdev; 1275 addr = &pdev->addr; 1276 1277 snprintf(enic->bdf_name, PCI_PRI_STR_SIZE, PCI_PRI_FMT, 1278 addr->domain, addr->bus, addr->devid, addr->function); 1279 1280 err = enic_check_devargs(eth_dev); 1281 if (err) 1282 return err; 1283 err = enic_probe(enic); 1284 if (!err && enic->fm) { 1285 err = enic_fm_allocate_switch_domain(enic); 1286 if (err) 1287 ENICPMD_LOG(ERR, "failed to allocate switch domain id"); 1288 } 1289 return err; 1290 } 1291 1292 static int eth_enic_dev_uninit(struct rte_eth_dev *eth_dev) 1293 { 1294 struct enic *enic = pmd_priv(eth_dev); 1295 int err; 1296 1297 ENICPMD_FUNC_TRACE(); 1298 eth_dev->device = NULL; 1299 eth_dev->intr_handle = NULL; 1300 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1301 return 0; 1302 err = rte_eth_switch_domain_free(enic->switch_domain_id); 1303 if (err) 1304 ENICPMD_LOG(WARNING, "failed to free switch domain: %d", err); 1305 return 0; 1306 } 1307 1308 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1309 struct rte_pci_device *pci_dev) 1310 { 1311 char name[RTE_ETH_NAME_MAX_LEN]; 1312 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 1313 struct rte_eth_dev *pf_ethdev; 1314 struct enic *pf_enic; 1315 int i, retval; 1316 1317 ENICPMD_FUNC_TRACE(); 1318 if (pci_dev->device.devargs) { 1319 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1320 ð_da); 1321 if (retval) 1322 return retval; 1323 } 1324 if (eth_da.nb_representor_ports > 0 && 1325 eth_da.type != RTE_ETH_REPRESENTOR_VF) { 1326 ENICPMD_LOG(ERR, "unsupported representor type: %s\n", 1327 pci_dev->device.devargs->args); 1328 return -ENOTSUP; 1329 } 1330 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1331 sizeof(struct enic), 1332 eth_dev_pci_specific_init, pci_dev, 1333 eth_enic_dev_init, NULL); 1334 if (retval || eth_da.nb_representor_ports < 1) 1335 return retval; 1336 1337 /* Probe VF representor */ 1338 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1339 if (pf_ethdev == NULL) 1340 return -ENODEV; 1341 /* Representors require flowman */ 1342 pf_enic = pmd_priv(pf_ethdev); 1343 if (pf_enic->fm == NULL) { 1344 ENICPMD_LOG(ERR, "VF representors require flowman"); 1345 return -ENOTSUP; 1346 } 1347 /* 1348 * For now representors imply switchdev, as firmware does not support 1349 * legacy mode SR-IOV 1350 */ 1351 pf_enic->switchdev_mode = 1; 1352 /* Calculate max VF ID before initializing representor*/ 1353 pf_enic->max_vf_id = 0; 1354 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1355 pf_enic->max_vf_id = RTE_MAX(pf_enic->max_vf_id, 1356 eth_da.representor_ports[i]); 1357 } 1358 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1359 struct enic_vf_representor representor; 1360 1361 representor.vf_id = eth_da.representor_ports[i]; 1362 representor.switch_domain_id = 1363 pmd_priv(pf_ethdev)->switch_domain_id; 1364 representor.pf = pmd_priv(pf_ethdev); 1365 snprintf(name, sizeof(name), "net_%s_representor_%d", 1366 pci_dev->device.name, eth_da.representor_ports[i]); 1367 retval = rte_eth_dev_create(&pci_dev->device, name, 1368 sizeof(struct enic_vf_representor), NULL, NULL, 1369 enic_vf_representor_init, &representor); 1370 if (retval) { 1371 ENICPMD_LOG(ERR, "failed to create enic vf representor %s", 1372 name); 1373 return retval; 1374 } 1375 } 1376 return 0; 1377 } 1378 1379 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1380 { 1381 struct rte_eth_dev *ethdev; 1382 1383 ENICPMD_FUNC_TRACE(); 1384 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1385 if (!ethdev) 1386 return -ENODEV; 1387 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1388 return rte_eth_dev_destroy(ethdev, enic_vf_representor_uninit); 1389 else 1390 return rte_eth_dev_destroy(ethdev, eth_enic_dev_uninit); 1391 } 1392 1393 static struct rte_pci_driver rte_enic_pmd = { 1394 .id_table = pci_id_enic_map, 1395 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1396 .probe = eth_enic_pci_probe, 1397 .remove = eth_enic_pci_remove, 1398 }; 1399 1400 int dev_is_enic(struct rte_eth_dev *dev) 1401 { 1402 return dev->device->driver == &rte_enic_pmd.driver; 1403 } 1404 1405 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1406 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1407 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1408 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1409 ENIC_DEVARG_CQ64 "=0|1" 1410 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1411 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1412 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1413