1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <rte_dev.h> 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_ethdev_pci.h> 14 #include <rte_kvargs.h> 15 #include <rte_string_fns.h> 16 17 #include "vnic_intr.h" 18 #include "vnic_cq.h" 19 #include "vnic_wq.h" 20 #include "vnic_rq.h" 21 #include "vnic_enet.h" 22 #include "enic.h" 23 24 int enicpmd_logtype_init; 25 int enicpmd_logtype_flow; 26 27 #define ENICPMD_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>") 28 29 /* 30 * The set of PCI devices this driver supports 31 */ 32 #define CISCO_PCI_VENDOR_ID 0x1137 33 static const struct rte_pci_id pci_id_enic_map[] = { 34 { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET) }, 35 { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) }, 36 {.vendor_id = 0, /* sentinel */}, 37 }; 38 39 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 40 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 41 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 42 43 RTE_INIT(enicpmd_init_log) 44 { 45 enicpmd_logtype_init = rte_log_register("pmd.net.enic.init"); 46 if (enicpmd_logtype_init >= 0) 47 rte_log_set_level(enicpmd_logtype_init, RTE_LOG_NOTICE); 48 enicpmd_logtype_flow = rte_log_register("pmd.net.enic.flow"); 49 if (enicpmd_logtype_flow >= 0) 50 rte_log_set_level(enicpmd_logtype_flow, RTE_LOG_NOTICE); 51 } 52 53 static int 54 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev, 55 enum rte_filter_op filter_op, void *arg) 56 { 57 struct enic *enic = pmd_priv(eth_dev); 58 int ret = 0; 59 60 ENICPMD_FUNC_TRACE(); 61 if (filter_op == RTE_ETH_FILTER_NOP) 62 return 0; 63 64 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 65 return -EINVAL; 66 67 switch (filter_op) { 68 case RTE_ETH_FILTER_ADD: 69 case RTE_ETH_FILTER_UPDATE: 70 ret = enic_fdir_add_fltr(enic, 71 (struct rte_eth_fdir_filter *)arg); 72 break; 73 74 case RTE_ETH_FILTER_DELETE: 75 ret = enic_fdir_del_fltr(enic, 76 (struct rte_eth_fdir_filter *)arg); 77 break; 78 79 case RTE_ETH_FILTER_STATS: 80 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg); 81 break; 82 83 case RTE_ETH_FILTER_FLUSH: 84 dev_warning(enic, "unsupported operation %u", filter_op); 85 ret = -ENOTSUP; 86 break; 87 case RTE_ETH_FILTER_INFO: 88 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg); 89 break; 90 default: 91 dev_err(enic, "unknown operation %u", filter_op); 92 ret = -EINVAL; 93 break; 94 } 95 return ret; 96 } 97 98 static int 99 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev, 100 enum rte_filter_type filter_type, 101 enum rte_filter_op filter_op, 102 void *arg) 103 { 104 int ret = 0; 105 106 ENICPMD_FUNC_TRACE(); 107 108 switch (filter_type) { 109 case RTE_ETH_FILTER_GENERIC: 110 if (filter_op != RTE_ETH_FILTER_GET) 111 return -EINVAL; 112 *(const void **)arg = &enic_flow_ops; 113 break; 114 case RTE_ETH_FILTER_FDIR: 115 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg); 116 break; 117 default: 118 dev_warning(enic, "Filter type (%d) not supported", 119 filter_type); 120 ret = -EINVAL; 121 break; 122 } 123 124 return ret; 125 } 126 127 static void enicpmd_dev_tx_queue_release(void *txq) 128 { 129 ENICPMD_FUNC_TRACE(); 130 131 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 132 return; 133 134 enic_free_wq(txq); 135 } 136 137 static int enicpmd_dev_setup_intr(struct enic *enic) 138 { 139 int ret; 140 unsigned int index; 141 142 ENICPMD_FUNC_TRACE(); 143 144 /* Are we done with the init of all the queues? */ 145 for (index = 0; index < enic->cq_count; index++) { 146 if (!enic->cq[index].ctrl) 147 break; 148 } 149 if (enic->cq_count != index) 150 return 0; 151 for (index = 0; index < enic->wq_count; index++) { 152 if (!enic->wq[index].ctrl) 153 break; 154 } 155 if (enic->wq_count != index) 156 return 0; 157 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 158 for (index = 0; index < enic->rq_count; index++) { 159 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 160 break; 161 } 162 if (enic->rq_count != index) 163 return 0; 164 165 ret = enic_alloc_intr_resources(enic); 166 if (ret) { 167 dev_err(enic, "alloc intr failed\n"); 168 return ret; 169 } 170 enic_init_vnic_resources(enic); 171 172 ret = enic_setup_finish(enic); 173 if (ret) 174 dev_err(enic, "setup could not be finished\n"); 175 176 return ret; 177 } 178 179 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 180 uint16_t queue_idx, 181 uint16_t nb_desc, 182 unsigned int socket_id, 183 const struct rte_eth_txconf *tx_conf) 184 { 185 int ret; 186 struct enic *enic = pmd_priv(eth_dev); 187 struct vnic_wq *wq; 188 189 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 190 return -E_RTE_SECONDARY; 191 192 ENICPMD_FUNC_TRACE(); 193 RTE_ASSERT(queue_idx < enic->conf_wq_count); 194 wq = &enic->wq[queue_idx]; 195 wq->offloads = tx_conf->offloads | 196 eth_dev->data->dev_conf.txmode.offloads; 197 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 198 199 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 200 if (ret) { 201 dev_err(enic, "error in allocating wq\n"); 202 return ret; 203 } 204 205 return enicpmd_dev_setup_intr(enic); 206 } 207 208 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 209 uint16_t queue_idx) 210 { 211 struct enic *enic = pmd_priv(eth_dev); 212 213 ENICPMD_FUNC_TRACE(); 214 215 enic_start_wq(enic, queue_idx); 216 217 return 0; 218 } 219 220 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 221 uint16_t queue_idx) 222 { 223 int ret; 224 struct enic *enic = pmd_priv(eth_dev); 225 226 ENICPMD_FUNC_TRACE(); 227 228 ret = enic_stop_wq(enic, queue_idx); 229 if (ret) 230 dev_err(enic, "error in stopping wq %d\n", queue_idx); 231 232 return ret; 233 } 234 235 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 236 uint16_t queue_idx) 237 { 238 struct enic *enic = pmd_priv(eth_dev); 239 240 ENICPMD_FUNC_TRACE(); 241 242 enic_start_rq(enic, queue_idx); 243 244 return 0; 245 } 246 247 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 248 uint16_t queue_idx) 249 { 250 int ret; 251 struct enic *enic = pmd_priv(eth_dev); 252 253 ENICPMD_FUNC_TRACE(); 254 255 ret = enic_stop_rq(enic, queue_idx); 256 if (ret) 257 dev_err(enic, "error in stopping rq %d\n", queue_idx); 258 259 return ret; 260 } 261 262 static void enicpmd_dev_rx_queue_release(void *rxq) 263 { 264 ENICPMD_FUNC_TRACE(); 265 266 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 267 return; 268 269 enic_free_rq(rxq); 270 } 271 272 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev, 273 uint16_t rx_queue_id) 274 { 275 struct enic *enic = pmd_priv(dev); 276 uint32_t queue_count = 0; 277 struct vnic_cq *cq; 278 uint32_t cq_tail; 279 uint16_t cq_idx; 280 int rq_num; 281 282 rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 283 cq = &enic->cq[enic_cq_rq(enic, rq_num)]; 284 cq_idx = cq->to_clean; 285 286 cq_tail = ioread32(&cq->ctrl->cq_tail); 287 288 if (cq_tail < cq_idx) 289 cq_tail += cq->ring.desc_count; 290 291 queue_count = cq_tail - cq_idx; 292 293 return queue_count; 294 } 295 296 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 297 uint16_t queue_idx, 298 uint16_t nb_desc, 299 unsigned int socket_id, 300 const struct rte_eth_rxconf *rx_conf, 301 struct rte_mempool *mp) 302 { 303 int ret; 304 struct enic *enic = pmd_priv(eth_dev); 305 306 ENICPMD_FUNC_TRACE(); 307 308 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 309 return -E_RTE_SECONDARY; 310 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 311 eth_dev->data->rx_queues[queue_idx] = 312 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 313 314 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 315 rx_conf->rx_free_thresh); 316 if (ret) { 317 dev_err(enic, "error in allocating rq\n"); 318 return ret; 319 } 320 321 return enicpmd_dev_setup_intr(enic); 322 } 323 324 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 325 { 326 struct enic *enic = pmd_priv(eth_dev); 327 uint64_t offloads; 328 329 ENICPMD_FUNC_TRACE(); 330 331 offloads = eth_dev->data->dev_conf.rxmode.offloads; 332 if (mask & ETH_VLAN_STRIP_MASK) { 333 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 334 enic->ig_vlan_strip_en = 1; 335 else 336 enic->ig_vlan_strip_en = 0; 337 } 338 339 if ((mask & ETH_VLAN_FILTER_MASK) && 340 (offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 341 dev_warning(enic, 342 "Configuration of VLAN filter is not supported\n"); 343 } 344 345 if ((mask & ETH_VLAN_EXTEND_MASK) && 346 (offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)) { 347 dev_warning(enic, 348 "Configuration of extended VLAN is not supported\n"); 349 } 350 351 return enic_set_vlan_strip(enic); 352 } 353 354 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 355 { 356 int ret; 357 int mask; 358 struct enic *enic = pmd_priv(eth_dev); 359 360 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 361 return -E_RTE_SECONDARY; 362 363 ENICPMD_FUNC_TRACE(); 364 ret = enic_set_vnic_res(enic); 365 if (ret) { 366 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 367 return ret; 368 } 369 370 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 371 DEV_RX_OFFLOAD_CHECKSUM); 372 /* All vlan offload masks to apply the current settings */ 373 mask = ETH_VLAN_STRIP_MASK | 374 ETH_VLAN_FILTER_MASK | 375 ETH_VLAN_EXTEND_MASK; 376 ret = enicpmd_vlan_offload_set(eth_dev, mask); 377 if (ret) { 378 dev_err(enic, "Failed to configure VLAN offloads\n"); 379 return ret; 380 } 381 /* 382 * Initialize RSS with the default reta and key. If the user key is 383 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 384 * default key. 385 */ 386 return enic_init_rss_nic_cfg(enic); 387 } 388 389 /* Start the device. 390 * It returns 0 on success. 391 */ 392 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 393 { 394 struct enic *enic = pmd_priv(eth_dev); 395 396 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 397 return -E_RTE_SECONDARY; 398 399 ENICPMD_FUNC_TRACE(); 400 return enic_enable(enic); 401 } 402 403 /* 404 * Stop device: disable rx and tx functions to allow for reconfiguring. 405 */ 406 static void enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 407 { 408 struct rte_eth_link link; 409 struct enic *enic = pmd_priv(eth_dev); 410 411 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 412 return; 413 414 ENICPMD_FUNC_TRACE(); 415 enic_disable(enic); 416 417 memset(&link, 0, sizeof(link)); 418 rte_eth_linkstatus_set(eth_dev, &link); 419 } 420 421 /* 422 * Stop device. 423 */ 424 static void enicpmd_dev_close(struct rte_eth_dev *eth_dev) 425 { 426 struct enic *enic = pmd_priv(eth_dev); 427 428 ENICPMD_FUNC_TRACE(); 429 enic_remove(enic); 430 } 431 432 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 433 __rte_unused int wait_to_complete) 434 { 435 struct enic *enic = pmd_priv(eth_dev); 436 437 ENICPMD_FUNC_TRACE(); 438 return enic_link_update(enic); 439 } 440 441 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 442 struct rte_eth_stats *stats) 443 { 444 struct enic *enic = pmd_priv(eth_dev); 445 446 ENICPMD_FUNC_TRACE(); 447 return enic_dev_stats_get(enic, stats); 448 } 449 450 static void enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 451 { 452 struct enic *enic = pmd_priv(eth_dev); 453 454 ENICPMD_FUNC_TRACE(); 455 enic_dev_stats_clear(enic); 456 } 457 458 static void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 459 struct rte_eth_dev_info *device_info) 460 { 461 struct enic *enic = pmd_priv(eth_dev); 462 463 ENICPMD_FUNC_TRACE(); 464 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 465 device_info->max_rx_queues = enic->conf_rq_count / 2; 466 device_info->max_tx_queues = enic->conf_wq_count; 467 device_info->min_rx_bufsize = ENIC_MIN_MTU; 468 /* "Max" mtu is not a typo. HW receives packet sizes up to the 469 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 470 * a hint to the driver to size receive buffers accordingly so that 471 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 472 * the user decide the buffer size via rxmode.max_rx_pkt_len, basically 473 * ignoring vNIC mtu. 474 */ 475 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 476 device_info->max_mac_addrs = ENIC_MAX_MAC_ADDR; 477 device_info->rx_offload_capa = enic->rx_offload_capa; 478 device_info->tx_offload_capa = enic->tx_offload_capa; 479 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 480 device_info->default_rxconf = (struct rte_eth_rxconf) { 481 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 482 }; 483 device_info->reta_size = enic->reta_size; 484 device_info->hash_key_size = enic->hash_key_size; 485 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 486 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 487 .nb_max = enic->config.rq_desc_count, 488 .nb_min = ENIC_MIN_RQ_DESCS, 489 .nb_align = ENIC_ALIGN_DESCS, 490 }; 491 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 492 .nb_max = enic->config.wq_desc_count, 493 .nb_min = ENIC_MIN_WQ_DESCS, 494 .nb_align = ENIC_ALIGN_DESCS, 495 .nb_seg_max = ENIC_TX_XMIT_MAX, 496 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 497 }; 498 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 499 .burst_size = ENIC_DEFAULT_RX_BURST, 500 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 501 ENIC_DEFAULT_RX_RING_SIZE), 502 .nb_queues = ENIC_DEFAULT_RX_RINGS, 503 }; 504 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 505 .burst_size = ENIC_DEFAULT_TX_BURST, 506 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 507 ENIC_DEFAULT_TX_RING_SIZE), 508 .nb_queues = ENIC_DEFAULT_TX_RINGS, 509 }; 510 } 511 512 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) 513 { 514 static const uint32_t ptypes[] = { 515 RTE_PTYPE_L2_ETHER, 516 RTE_PTYPE_L2_ETHER_VLAN, 517 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 518 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 519 RTE_PTYPE_L4_TCP, 520 RTE_PTYPE_L4_UDP, 521 RTE_PTYPE_L4_FRAG, 522 RTE_PTYPE_L4_NONFRAG, 523 RTE_PTYPE_UNKNOWN 524 }; 525 526 if (dev->rx_pkt_burst == enic_recv_pkts || 527 dev->rx_pkt_burst == enic_noscatter_recv_pkts) 528 return ptypes; 529 return NULL; 530 } 531 532 static void enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 533 { 534 struct enic *enic = pmd_priv(eth_dev); 535 536 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 537 return; 538 539 ENICPMD_FUNC_TRACE(); 540 541 enic->promisc = 1; 542 enic_add_packet_filter(enic); 543 } 544 545 static void enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 546 { 547 struct enic *enic = pmd_priv(eth_dev); 548 549 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 550 return; 551 552 ENICPMD_FUNC_TRACE(); 553 enic->promisc = 0; 554 enic_add_packet_filter(enic); 555 } 556 557 static void enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 558 { 559 struct enic *enic = pmd_priv(eth_dev); 560 561 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 562 return; 563 564 ENICPMD_FUNC_TRACE(); 565 enic->allmulti = 1; 566 enic_add_packet_filter(enic); 567 } 568 569 static void enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 570 { 571 struct enic *enic = pmd_priv(eth_dev); 572 573 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 574 return; 575 576 ENICPMD_FUNC_TRACE(); 577 enic->allmulti = 0; 578 enic_add_packet_filter(enic); 579 } 580 581 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 582 struct ether_addr *mac_addr, 583 __rte_unused uint32_t index, __rte_unused uint32_t pool) 584 { 585 struct enic *enic = pmd_priv(eth_dev); 586 587 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 588 return -E_RTE_SECONDARY; 589 590 ENICPMD_FUNC_TRACE(); 591 return enic_set_mac_address(enic, mac_addr->addr_bytes); 592 } 593 594 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 595 { 596 struct enic *enic = pmd_priv(eth_dev); 597 598 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 599 return; 600 601 ENICPMD_FUNC_TRACE(); 602 if (enic_del_mac_address(enic, index)) 603 dev_err(enic, "del mac addr failed\n"); 604 } 605 606 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 607 struct ether_addr *addr) 608 { 609 struct enic *enic = pmd_priv(eth_dev); 610 int ret; 611 612 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 613 return -E_RTE_SECONDARY; 614 615 ENICPMD_FUNC_TRACE(); 616 ret = enic_del_mac_address(enic, 0); 617 if (ret) 618 return ret; 619 return enic_set_mac_address(enic, addr->addr_bytes); 620 } 621 622 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 623 { 624 struct enic *enic = pmd_priv(eth_dev); 625 626 ENICPMD_FUNC_TRACE(); 627 return enic_set_mtu(enic, mtu); 628 } 629 630 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 631 struct rte_eth_rss_reta_entry64 632 *reta_conf, 633 uint16_t reta_size) 634 { 635 struct enic *enic = pmd_priv(dev); 636 uint16_t i, idx, shift; 637 638 ENICPMD_FUNC_TRACE(); 639 if (reta_size != ENIC_RSS_RETA_SIZE) { 640 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 641 reta_size, ENIC_RSS_RETA_SIZE); 642 return -EINVAL; 643 } 644 645 for (i = 0; i < reta_size; i++) { 646 idx = i / RTE_RETA_GROUP_SIZE; 647 shift = i % RTE_RETA_GROUP_SIZE; 648 if (reta_conf[idx].mask & (1ULL << shift)) 649 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 650 enic->rss_cpu.cpu[i / 4].b[i % 4]); 651 } 652 653 return 0; 654 } 655 656 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 657 struct rte_eth_rss_reta_entry64 658 *reta_conf, 659 uint16_t reta_size) 660 { 661 struct enic *enic = pmd_priv(dev); 662 union vnic_rss_cpu rss_cpu; 663 uint16_t i, idx, shift; 664 665 ENICPMD_FUNC_TRACE(); 666 if (reta_size != ENIC_RSS_RETA_SIZE) { 667 dev_err(enic, "reta_update: wrong reta_size. given=%u" 668 " expected=%u\n", 669 reta_size, ENIC_RSS_RETA_SIZE); 670 return -EINVAL; 671 } 672 /* 673 * Start with the current reta and modify it per reta_conf, as we 674 * need to push the entire reta even if we only modify one entry. 675 */ 676 rss_cpu = enic->rss_cpu; 677 for (i = 0; i < reta_size; i++) { 678 idx = i / RTE_RETA_GROUP_SIZE; 679 shift = i % RTE_RETA_GROUP_SIZE; 680 if (reta_conf[idx].mask & (1ULL << shift)) 681 rss_cpu.cpu[i / 4].b[i % 4] = 682 enic_rte_rq_idx_to_sop_idx( 683 reta_conf[idx].reta[shift]); 684 } 685 return enic_set_rss_reta(enic, &rss_cpu); 686 } 687 688 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 689 struct rte_eth_rss_conf *rss_conf) 690 { 691 struct enic *enic = pmd_priv(dev); 692 693 ENICPMD_FUNC_TRACE(); 694 return enic_set_rss_conf(enic, rss_conf); 695 } 696 697 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 698 struct rte_eth_rss_conf *rss_conf) 699 { 700 struct enic *enic = pmd_priv(dev); 701 702 ENICPMD_FUNC_TRACE(); 703 if (rss_conf == NULL) 704 return -EINVAL; 705 if (rss_conf->rss_key != NULL && 706 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 707 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 708 " expected=%u+\n", 709 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 710 return -EINVAL; 711 } 712 rss_conf->rss_hf = enic->rss_hf; 713 if (rss_conf->rss_key != NULL) { 714 int i; 715 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 716 rss_conf->rss_key[i] = 717 enic->rss_key.key[i / 10].b[i % 10]; 718 } 719 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 720 } 721 return 0; 722 } 723 724 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 725 uint16_t rx_queue_id, 726 struct rte_eth_rxq_info *qinfo) 727 { 728 struct enic *enic = pmd_priv(dev); 729 struct vnic_rq *rq_sop; 730 struct vnic_rq *rq_data; 731 struct rte_eth_rxconf *conf; 732 uint16_t sop_queue_idx; 733 uint16_t data_queue_idx; 734 735 ENICPMD_FUNC_TRACE(); 736 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 737 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id); 738 rq_sop = &enic->rq[sop_queue_idx]; 739 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 740 qinfo->mp = rq_sop->mp; 741 qinfo->scattered_rx = rq_sop->data_queue_enable; 742 qinfo->nb_desc = rq_sop->ring.desc_count; 743 if (qinfo->scattered_rx) 744 qinfo->nb_desc += rq_data->ring.desc_count; 745 conf = &qinfo->conf; 746 memset(conf, 0, sizeof(*conf)); 747 conf->rx_free_thresh = rq_sop->rx_free_thresh; 748 conf->rx_drop_en = 1; 749 /* 750 * Except VLAN stripping (port setting), all the checksum offloads 751 * are always enabled. 752 */ 753 conf->offloads = enic->rx_offload_capa; 754 if (!enic->ig_vlan_strip_en) 755 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 756 /* rx_thresh and other fields are not applicable for enic */ 757 } 758 759 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 760 uint16_t tx_queue_id, 761 struct rte_eth_txq_info *qinfo) 762 { 763 struct enic *enic = pmd_priv(dev); 764 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 765 766 ENICPMD_FUNC_TRACE(); 767 qinfo->nb_desc = wq->ring.desc_count; 768 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 769 qinfo->conf.offloads = wq->offloads; 770 /* tx_thresh, and all the other fields are not applicable for enic */ 771 } 772 773 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 774 uint16_t rx_queue_id) 775 { 776 struct enic *enic = pmd_priv(eth_dev); 777 778 ENICPMD_FUNC_TRACE(); 779 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 780 return 0; 781 } 782 783 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 784 uint16_t rx_queue_id) 785 { 786 struct enic *enic = pmd_priv(eth_dev); 787 788 ENICPMD_FUNC_TRACE(); 789 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 790 return 0; 791 } 792 793 static int udp_tunnel_common_check(struct enic *enic, 794 struct rte_eth_udp_tunnel *tnl) 795 { 796 if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN) 797 return -ENOTSUP; 798 if (!enic->overlay_offload) { 799 PMD_INIT_LOG(DEBUG, " vxlan (overlay offload) is not " 800 "supported\n"); 801 return -ENOTSUP; 802 } 803 return 0; 804 } 805 806 static int update_vxlan_port(struct enic *enic, uint16_t port) 807 { 808 if (vnic_dev_overlay_offload_cfg(enic->vdev, 809 OVERLAY_CFG_VXLAN_PORT_UPDATE, 810 port)) { 811 PMD_INIT_LOG(DEBUG, " failed to update vxlan port\n"); 812 return -EINVAL; 813 } 814 PMD_INIT_LOG(DEBUG, " updated vxlan port to %u\n", port); 815 enic->vxlan_port = port; 816 return 0; 817 } 818 819 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 820 struct rte_eth_udp_tunnel *tnl) 821 { 822 struct enic *enic = pmd_priv(eth_dev); 823 int ret; 824 825 ENICPMD_FUNC_TRACE(); 826 ret = udp_tunnel_common_check(enic, tnl); 827 if (ret) 828 return ret; 829 /* 830 * The NIC has 1 configurable VXLAN port number. "Adding" a new port 831 * number replaces it. 832 */ 833 if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) { 834 PMD_INIT_LOG(DEBUG, " %u is already configured or invalid\n", 835 tnl->udp_port); 836 return -EINVAL; 837 } 838 return update_vxlan_port(enic, tnl->udp_port); 839 } 840 841 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 842 struct rte_eth_udp_tunnel *tnl) 843 { 844 struct enic *enic = pmd_priv(eth_dev); 845 int ret; 846 847 ENICPMD_FUNC_TRACE(); 848 ret = udp_tunnel_common_check(enic, tnl); 849 if (ret) 850 return ret; 851 /* 852 * Clear the previously set port number and restore the 853 * hardware default port number. Some drivers disable VXLAN 854 * offloads when there are no configured port numbers. But 855 * enic does not do that as VXLAN is part of overlay offload, 856 * which is tied to inner RSS and TSO. 857 */ 858 if (tnl->udp_port != enic->vxlan_port) { 859 PMD_INIT_LOG(DEBUG, " %u is not a configured vxlan port\n", 860 tnl->udp_port); 861 return -EINVAL; 862 } 863 return update_vxlan_port(enic, ENIC_DEFAULT_VXLAN_PORT); 864 } 865 866 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 867 .dev_configure = enicpmd_dev_configure, 868 .dev_start = enicpmd_dev_start, 869 .dev_stop = enicpmd_dev_stop, 870 .dev_set_link_up = NULL, 871 .dev_set_link_down = NULL, 872 .dev_close = enicpmd_dev_close, 873 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 874 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 875 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 876 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 877 .link_update = enicpmd_dev_link_update, 878 .stats_get = enicpmd_dev_stats_get, 879 .stats_reset = enicpmd_dev_stats_reset, 880 .queue_stats_mapping_set = NULL, 881 .dev_infos_get = enicpmd_dev_info_get, 882 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 883 .mtu_set = enicpmd_mtu_set, 884 .vlan_filter_set = NULL, 885 .vlan_tpid_set = NULL, 886 .vlan_offload_set = enicpmd_vlan_offload_set, 887 .vlan_strip_queue_set = NULL, 888 .rx_queue_start = enicpmd_dev_rx_queue_start, 889 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 890 .tx_queue_start = enicpmd_dev_tx_queue_start, 891 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 892 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 893 .rx_queue_release = enicpmd_dev_rx_queue_release, 894 .rx_queue_count = enicpmd_dev_rx_queue_count, 895 .rx_descriptor_done = NULL, 896 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 897 .tx_queue_release = enicpmd_dev_tx_queue_release, 898 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 899 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 900 .rxq_info_get = enicpmd_dev_rxq_info_get, 901 .txq_info_get = enicpmd_dev_txq_info_get, 902 .dev_led_on = NULL, 903 .dev_led_off = NULL, 904 .flow_ctrl_get = NULL, 905 .flow_ctrl_set = NULL, 906 .priority_flow_ctrl_set = NULL, 907 .mac_addr_add = enicpmd_add_mac_addr, 908 .mac_addr_remove = enicpmd_remove_mac_addr, 909 .mac_addr_set = enicpmd_set_mac_addr, 910 .filter_ctrl = enicpmd_dev_filter_ctrl, 911 .reta_query = enicpmd_dev_rss_reta_query, 912 .reta_update = enicpmd_dev_rss_reta_update, 913 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 914 .rss_hash_update = enicpmd_dev_rss_hash_update, 915 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 916 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 917 }; 918 919 static int enic_parse_zero_one(const char *key, 920 const char *value, 921 void *opaque) 922 { 923 struct enic *enic; 924 bool b; 925 926 enic = (struct enic *)opaque; 927 if (strcmp(value, "0") == 0) { 928 b = false; 929 } else if (strcmp(value, "1") == 0) { 930 b = true; 931 } else { 932 dev_err(enic, "Invalid value for %s" 933 ": expected=0|1 given=%s\n", key, value); 934 return -EINVAL; 935 } 936 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 937 enic->disable_overlay = b; 938 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 939 enic->enable_avx2_rx = b; 940 return 0; 941 } 942 943 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 944 const char *value, 945 void *opaque) 946 { 947 struct enic *enic; 948 949 enic = (struct enic *)opaque; 950 if (strcmp(value, "trunk") == 0) { 951 /* Trunk mode: always tag */ 952 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 953 } else if (strcmp(value, "untag") == 0) { 954 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 955 enic->ig_vlan_rewrite_mode = 956 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 957 } else if (strcmp(value, "priority") == 0) { 958 /* 959 * Priority-tag default VLAN mode: priority tag (VLAN header 960 * with ID=0) if VLAN = default 961 */ 962 enic->ig_vlan_rewrite_mode = 963 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 964 } else if (strcmp(value, "pass") == 0) { 965 /* Pass through mode: do not touch tags */ 966 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 967 } else { 968 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 969 ": expected=trunk|untag|priority|pass given=%s\n", 970 value); 971 return -EINVAL; 972 } 973 return 0; 974 } 975 976 static int enic_check_devargs(struct rte_eth_dev *dev) 977 { 978 static const char *const valid_keys[] = { 979 ENIC_DEVARG_DISABLE_OVERLAY, 980 ENIC_DEVARG_ENABLE_AVX2_RX, 981 ENIC_DEVARG_IG_VLAN_REWRITE, 982 NULL}; 983 struct enic *enic = pmd_priv(dev); 984 struct rte_kvargs *kvlist; 985 986 ENICPMD_FUNC_TRACE(); 987 988 enic->disable_overlay = false; 989 enic->enable_avx2_rx = false; 990 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 991 if (!dev->device->devargs) 992 return 0; 993 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 994 if (!kvlist) 995 return -EINVAL; 996 if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 997 enic_parse_zero_one, enic) < 0 || 998 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 999 enic_parse_zero_one, enic) < 0 || 1000 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1001 enic_parse_ig_vlan_rewrite, enic) < 0) { 1002 rte_kvargs_free(kvlist); 1003 return -EINVAL; 1004 } 1005 rte_kvargs_free(kvlist); 1006 return 0; 1007 } 1008 1009 struct enic *enicpmd_list_head = NULL; 1010 /* Initialize the driver 1011 * It returns 0 on success. 1012 */ 1013 static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev) 1014 { 1015 struct rte_pci_device *pdev; 1016 struct rte_pci_addr *addr; 1017 struct enic *enic = pmd_priv(eth_dev); 1018 int err; 1019 1020 ENICPMD_FUNC_TRACE(); 1021 1022 enic->port_id = eth_dev->data->port_id; 1023 enic->rte_dev = eth_dev; 1024 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1025 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1026 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1027 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1028 1029 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1030 rte_eth_copy_pci_info(eth_dev, pdev); 1031 enic->pdev = pdev; 1032 addr = &pdev->addr; 1033 1034 snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x", 1035 addr->domain, addr->bus, addr->devid, addr->function); 1036 1037 err = enic_check_devargs(eth_dev); 1038 if (err) 1039 return err; 1040 return enic_probe(enic); 1041 } 1042 1043 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1044 struct rte_pci_device *pci_dev) 1045 { 1046 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct enic), 1047 eth_enicpmd_dev_init); 1048 } 1049 1050 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1051 { 1052 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 1053 } 1054 1055 static struct rte_pci_driver rte_enic_pmd = { 1056 .id_table = pci_id_enic_map, 1057 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 1058 RTE_PCI_DRV_IOVA_AS_VA, 1059 .probe = eth_enic_pci_probe, 1060 .remove = eth_enic_pci_remove, 1061 }; 1062 1063 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1064 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1065 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1066 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1067 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1068 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1069 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1070