1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <rte_dev.h> 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_ethdev_pci.h> 14 #include <rte_kvargs.h> 15 #include <rte_string_fns.h> 16 17 #include "vnic_intr.h" 18 #include "vnic_cq.h" 19 #include "vnic_wq.h" 20 #include "vnic_rq.h" 21 #include "vnic_enet.h" 22 #include "enic.h" 23 24 int enicpmd_logtype_init; 25 int enicpmd_logtype_flow; 26 27 #define ENICPMD_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>") 28 29 /* 30 * The set of PCI devices this driver supports 31 */ 32 #define CISCO_PCI_VENDOR_ID 0x1137 33 static const struct rte_pci_id pci_id_enic_map[] = { 34 { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET) }, 35 { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) }, 36 {.vendor_id = 0, /* sentinel */}, 37 }; 38 39 /* Supported link speeds of production VIC models */ 40 static const struct vic_speed_capa { 41 uint16_t sub_devid; 42 uint32_t capa; 43 } vic_speed_capa_map[] = { 44 { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */ 45 { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */ 46 { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */ 47 { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */ 48 { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */ 49 { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */ 50 { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */ 51 { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */ 52 { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */ 53 { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */ 54 { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */ 55 { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */ 56 { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */ 57 { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */ 58 { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 59 ETH_LINK_SPEED_40G }, /* 1440 Mezz */ 60 { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 61 ETH_LINK_SPEED_40G }, /* 1480 MLOM */ 62 { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */ 63 { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */ 64 { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */ 65 { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */ 66 { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */ 67 { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */ 68 { 0, 0 }, /* End marker */ 69 }; 70 71 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 72 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 73 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 74 75 RTE_INIT(enicpmd_init_log) 76 { 77 enicpmd_logtype_init = rte_log_register("pmd.net.enic.init"); 78 if (enicpmd_logtype_init >= 0) 79 rte_log_set_level(enicpmd_logtype_init, RTE_LOG_NOTICE); 80 enicpmd_logtype_flow = rte_log_register("pmd.net.enic.flow"); 81 if (enicpmd_logtype_flow >= 0) 82 rte_log_set_level(enicpmd_logtype_flow, RTE_LOG_NOTICE); 83 } 84 85 static int 86 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev, 87 enum rte_filter_op filter_op, void *arg) 88 { 89 struct enic *enic = pmd_priv(eth_dev); 90 int ret = 0; 91 92 ENICPMD_FUNC_TRACE(); 93 if (filter_op == RTE_ETH_FILTER_NOP) 94 return 0; 95 96 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 97 return -EINVAL; 98 99 switch (filter_op) { 100 case RTE_ETH_FILTER_ADD: 101 case RTE_ETH_FILTER_UPDATE: 102 ret = enic_fdir_add_fltr(enic, 103 (struct rte_eth_fdir_filter *)arg); 104 break; 105 106 case RTE_ETH_FILTER_DELETE: 107 ret = enic_fdir_del_fltr(enic, 108 (struct rte_eth_fdir_filter *)arg); 109 break; 110 111 case RTE_ETH_FILTER_STATS: 112 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg); 113 break; 114 115 case RTE_ETH_FILTER_FLUSH: 116 dev_warning(enic, "unsupported operation %u", filter_op); 117 ret = -ENOTSUP; 118 break; 119 case RTE_ETH_FILTER_INFO: 120 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg); 121 break; 122 default: 123 dev_err(enic, "unknown operation %u", filter_op); 124 ret = -EINVAL; 125 break; 126 } 127 return ret; 128 } 129 130 static int 131 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev, 132 enum rte_filter_type filter_type, 133 enum rte_filter_op filter_op, 134 void *arg) 135 { 136 int ret = 0; 137 138 ENICPMD_FUNC_TRACE(); 139 140 switch (filter_type) { 141 case RTE_ETH_FILTER_GENERIC: 142 if (filter_op != RTE_ETH_FILTER_GET) 143 return -EINVAL; 144 *(const void **)arg = &enic_flow_ops; 145 break; 146 case RTE_ETH_FILTER_FDIR: 147 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg); 148 break; 149 default: 150 dev_warning(enic, "Filter type (%d) not supported", 151 filter_type); 152 ret = -EINVAL; 153 break; 154 } 155 156 return ret; 157 } 158 159 static void enicpmd_dev_tx_queue_release(void *txq) 160 { 161 ENICPMD_FUNC_TRACE(); 162 163 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 164 return; 165 166 enic_free_wq(txq); 167 } 168 169 static int enicpmd_dev_setup_intr(struct enic *enic) 170 { 171 int ret; 172 unsigned int index; 173 174 ENICPMD_FUNC_TRACE(); 175 176 /* Are we done with the init of all the queues? */ 177 for (index = 0; index < enic->cq_count; index++) { 178 if (!enic->cq[index].ctrl) 179 break; 180 } 181 if (enic->cq_count != index) 182 return 0; 183 for (index = 0; index < enic->wq_count; index++) { 184 if (!enic->wq[index].ctrl) 185 break; 186 } 187 if (enic->wq_count != index) 188 return 0; 189 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 190 for (index = 0; index < enic->rq_count; index++) { 191 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 192 break; 193 } 194 if (enic->rq_count != index) 195 return 0; 196 197 ret = enic_alloc_intr_resources(enic); 198 if (ret) { 199 dev_err(enic, "alloc intr failed\n"); 200 return ret; 201 } 202 enic_init_vnic_resources(enic); 203 204 ret = enic_setup_finish(enic); 205 if (ret) 206 dev_err(enic, "setup could not be finished\n"); 207 208 return ret; 209 } 210 211 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 212 uint16_t queue_idx, 213 uint16_t nb_desc, 214 unsigned int socket_id, 215 const struct rte_eth_txconf *tx_conf) 216 { 217 int ret; 218 struct enic *enic = pmd_priv(eth_dev); 219 struct vnic_wq *wq; 220 221 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 222 return -E_RTE_SECONDARY; 223 224 ENICPMD_FUNC_TRACE(); 225 RTE_ASSERT(queue_idx < enic->conf_wq_count); 226 wq = &enic->wq[queue_idx]; 227 wq->offloads = tx_conf->offloads | 228 eth_dev->data->dev_conf.txmode.offloads; 229 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 230 231 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 232 if (ret) { 233 dev_err(enic, "error in allocating wq\n"); 234 return ret; 235 } 236 237 return enicpmd_dev_setup_intr(enic); 238 } 239 240 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 241 uint16_t queue_idx) 242 { 243 struct enic *enic = pmd_priv(eth_dev); 244 245 ENICPMD_FUNC_TRACE(); 246 247 enic_start_wq(enic, queue_idx); 248 249 return 0; 250 } 251 252 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 253 uint16_t queue_idx) 254 { 255 int ret; 256 struct enic *enic = pmd_priv(eth_dev); 257 258 ENICPMD_FUNC_TRACE(); 259 260 ret = enic_stop_wq(enic, queue_idx); 261 if (ret) 262 dev_err(enic, "error in stopping wq %d\n", queue_idx); 263 264 return ret; 265 } 266 267 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 268 uint16_t queue_idx) 269 { 270 struct enic *enic = pmd_priv(eth_dev); 271 272 ENICPMD_FUNC_TRACE(); 273 274 enic_start_rq(enic, queue_idx); 275 276 return 0; 277 } 278 279 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 280 uint16_t queue_idx) 281 { 282 int ret; 283 struct enic *enic = pmd_priv(eth_dev); 284 285 ENICPMD_FUNC_TRACE(); 286 287 ret = enic_stop_rq(enic, queue_idx); 288 if (ret) 289 dev_err(enic, "error in stopping rq %d\n", queue_idx); 290 291 return ret; 292 } 293 294 static void enicpmd_dev_rx_queue_release(void *rxq) 295 { 296 ENICPMD_FUNC_TRACE(); 297 298 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 299 return; 300 301 enic_free_rq(rxq); 302 } 303 304 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev, 305 uint16_t rx_queue_id) 306 { 307 struct enic *enic = pmd_priv(dev); 308 uint32_t queue_count = 0; 309 struct vnic_cq *cq; 310 uint32_t cq_tail; 311 uint16_t cq_idx; 312 int rq_num; 313 314 rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 315 cq = &enic->cq[enic_cq_rq(enic, rq_num)]; 316 cq_idx = cq->to_clean; 317 318 cq_tail = ioread32(&cq->ctrl->cq_tail); 319 320 if (cq_tail < cq_idx) 321 cq_tail += cq->ring.desc_count; 322 323 queue_count = cq_tail - cq_idx; 324 325 return queue_count; 326 } 327 328 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 329 uint16_t queue_idx, 330 uint16_t nb_desc, 331 unsigned int socket_id, 332 const struct rte_eth_rxconf *rx_conf, 333 struct rte_mempool *mp) 334 { 335 int ret; 336 struct enic *enic = pmd_priv(eth_dev); 337 338 ENICPMD_FUNC_TRACE(); 339 340 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 341 return -E_RTE_SECONDARY; 342 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 343 eth_dev->data->rx_queues[queue_idx] = 344 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 345 346 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 347 rx_conf->rx_free_thresh); 348 if (ret) { 349 dev_err(enic, "error in allocating rq\n"); 350 return ret; 351 } 352 353 return enicpmd_dev_setup_intr(enic); 354 } 355 356 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 357 { 358 struct enic *enic = pmd_priv(eth_dev); 359 uint64_t offloads; 360 361 ENICPMD_FUNC_TRACE(); 362 363 offloads = eth_dev->data->dev_conf.rxmode.offloads; 364 if (mask & ETH_VLAN_STRIP_MASK) { 365 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 366 enic->ig_vlan_strip_en = 1; 367 else 368 enic->ig_vlan_strip_en = 0; 369 } 370 371 if ((mask & ETH_VLAN_FILTER_MASK) && 372 (offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 373 dev_warning(enic, 374 "Configuration of VLAN filter is not supported\n"); 375 } 376 377 if ((mask & ETH_VLAN_EXTEND_MASK) && 378 (offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)) { 379 dev_warning(enic, 380 "Configuration of extended VLAN is not supported\n"); 381 } 382 383 return enic_set_vlan_strip(enic); 384 } 385 386 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 387 { 388 int ret; 389 int mask; 390 struct enic *enic = pmd_priv(eth_dev); 391 392 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 393 return -E_RTE_SECONDARY; 394 395 ENICPMD_FUNC_TRACE(); 396 ret = enic_set_vnic_res(enic); 397 if (ret) { 398 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 399 return ret; 400 } 401 402 enic->mc_count = 0; 403 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 404 DEV_RX_OFFLOAD_CHECKSUM); 405 /* All vlan offload masks to apply the current settings */ 406 mask = ETH_VLAN_STRIP_MASK | 407 ETH_VLAN_FILTER_MASK | 408 ETH_VLAN_EXTEND_MASK; 409 ret = enicpmd_vlan_offload_set(eth_dev, mask); 410 if (ret) { 411 dev_err(enic, "Failed to configure VLAN offloads\n"); 412 return ret; 413 } 414 /* 415 * Initialize RSS with the default reta and key. If the user key is 416 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 417 * default key. 418 */ 419 return enic_init_rss_nic_cfg(enic); 420 } 421 422 /* Start the device. 423 * It returns 0 on success. 424 */ 425 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 426 { 427 struct enic *enic = pmd_priv(eth_dev); 428 429 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 430 return -E_RTE_SECONDARY; 431 432 ENICPMD_FUNC_TRACE(); 433 return enic_enable(enic); 434 } 435 436 /* 437 * Stop device: disable rx and tx functions to allow for reconfiguring. 438 */ 439 static void enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 440 { 441 struct rte_eth_link link; 442 struct enic *enic = pmd_priv(eth_dev); 443 444 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 445 return; 446 447 ENICPMD_FUNC_TRACE(); 448 enic_disable(enic); 449 450 memset(&link, 0, sizeof(link)); 451 rte_eth_linkstatus_set(eth_dev, &link); 452 } 453 454 /* 455 * Stop device. 456 */ 457 static void enicpmd_dev_close(struct rte_eth_dev *eth_dev) 458 { 459 struct enic *enic = pmd_priv(eth_dev); 460 461 ENICPMD_FUNC_TRACE(); 462 enic_remove(enic); 463 } 464 465 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 466 __rte_unused int wait_to_complete) 467 { 468 struct enic *enic = pmd_priv(eth_dev); 469 470 ENICPMD_FUNC_TRACE(); 471 return enic_link_update(enic); 472 } 473 474 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 475 struct rte_eth_stats *stats) 476 { 477 struct enic *enic = pmd_priv(eth_dev); 478 479 ENICPMD_FUNC_TRACE(); 480 return enic_dev_stats_get(enic, stats); 481 } 482 483 static void enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 484 { 485 struct enic *enic = pmd_priv(eth_dev); 486 487 ENICPMD_FUNC_TRACE(); 488 enic_dev_stats_clear(enic); 489 } 490 491 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) 492 { 493 const struct vic_speed_capa *m; 494 struct rte_pci_device *pdev; 495 uint16_t id; 496 497 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 498 id = pdev->id.subsystem_device_id; 499 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { 500 if (m->sub_devid == id) 501 return m->capa; 502 } 503 /* 1300 and later models are at least 40G */ 504 if (id >= 0x0100) 505 return ETH_LINK_SPEED_40G; 506 return ETH_LINK_SPEED_10G; 507 } 508 509 static void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 510 struct rte_eth_dev_info *device_info) 511 { 512 struct enic *enic = pmd_priv(eth_dev); 513 514 ENICPMD_FUNC_TRACE(); 515 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 516 device_info->max_rx_queues = enic->conf_rq_count / 2; 517 device_info->max_tx_queues = enic->conf_wq_count; 518 device_info->min_rx_bufsize = ENIC_MIN_MTU; 519 /* "Max" mtu is not a typo. HW receives packet sizes up to the 520 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 521 * a hint to the driver to size receive buffers accordingly so that 522 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 523 * the user decide the buffer size via rxmode.max_rx_pkt_len, basically 524 * ignoring vNIC mtu. 525 */ 526 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 527 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS; 528 device_info->min_mtu = ENIC_MIN_MTU; 529 device_info->max_mtu = enic->max_mtu; 530 device_info->rx_offload_capa = enic->rx_offload_capa; 531 device_info->tx_offload_capa = enic->tx_offload_capa; 532 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 533 device_info->default_rxconf = (struct rte_eth_rxconf) { 534 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 535 }; 536 device_info->reta_size = enic->reta_size; 537 device_info->hash_key_size = enic->hash_key_size; 538 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 539 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 540 .nb_max = enic->config.rq_desc_count, 541 .nb_min = ENIC_MIN_RQ_DESCS, 542 .nb_align = ENIC_ALIGN_DESCS, 543 }; 544 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 545 .nb_max = enic->config.wq_desc_count, 546 .nb_min = ENIC_MIN_WQ_DESCS, 547 .nb_align = ENIC_ALIGN_DESCS, 548 .nb_seg_max = ENIC_TX_XMIT_MAX, 549 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 550 }; 551 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 552 .burst_size = ENIC_DEFAULT_RX_BURST, 553 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 554 ENIC_DEFAULT_RX_RING_SIZE), 555 .nb_queues = ENIC_DEFAULT_RX_RINGS, 556 }; 557 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 558 .burst_size = ENIC_DEFAULT_TX_BURST, 559 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 560 ENIC_DEFAULT_TX_RING_SIZE), 561 .nb_queues = ENIC_DEFAULT_TX_RINGS, 562 }; 563 device_info->speed_capa = speed_capa_from_pci_id(eth_dev); 564 } 565 566 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) 567 { 568 static const uint32_t ptypes[] = { 569 RTE_PTYPE_L2_ETHER, 570 RTE_PTYPE_L2_ETHER_VLAN, 571 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 572 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 573 RTE_PTYPE_L4_TCP, 574 RTE_PTYPE_L4_UDP, 575 RTE_PTYPE_L4_FRAG, 576 RTE_PTYPE_L4_NONFRAG, 577 RTE_PTYPE_UNKNOWN 578 }; 579 static const uint32_t ptypes_overlay[] = { 580 RTE_PTYPE_L2_ETHER, 581 RTE_PTYPE_L2_ETHER_VLAN, 582 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 583 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 584 RTE_PTYPE_L4_TCP, 585 RTE_PTYPE_L4_UDP, 586 RTE_PTYPE_L4_FRAG, 587 RTE_PTYPE_L4_NONFRAG, 588 RTE_PTYPE_TUNNEL_GRENAT, 589 RTE_PTYPE_INNER_L2_ETHER, 590 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 591 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 592 RTE_PTYPE_INNER_L4_TCP, 593 RTE_PTYPE_INNER_L4_UDP, 594 RTE_PTYPE_INNER_L4_FRAG, 595 RTE_PTYPE_INNER_L4_NONFRAG, 596 RTE_PTYPE_UNKNOWN 597 }; 598 599 if (dev->rx_pkt_burst != enic_dummy_recv_pkts && 600 dev->rx_pkt_burst != NULL) { 601 struct enic *enic = pmd_priv(dev); 602 if (enic->overlay_offload) 603 return ptypes_overlay; 604 else 605 return ptypes; 606 } 607 return NULL; 608 } 609 610 static void enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 611 { 612 struct enic *enic = pmd_priv(eth_dev); 613 614 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 615 return; 616 617 ENICPMD_FUNC_TRACE(); 618 619 enic->promisc = 1; 620 enic_add_packet_filter(enic); 621 } 622 623 static void enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 624 { 625 struct enic *enic = pmd_priv(eth_dev); 626 627 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 628 return; 629 630 ENICPMD_FUNC_TRACE(); 631 enic->promisc = 0; 632 enic_add_packet_filter(enic); 633 } 634 635 static void enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 636 { 637 struct enic *enic = pmd_priv(eth_dev); 638 639 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 640 return; 641 642 ENICPMD_FUNC_TRACE(); 643 enic->allmulti = 1; 644 enic_add_packet_filter(enic); 645 } 646 647 static void enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 648 { 649 struct enic *enic = pmd_priv(eth_dev); 650 651 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 652 return; 653 654 ENICPMD_FUNC_TRACE(); 655 enic->allmulti = 0; 656 enic_add_packet_filter(enic); 657 } 658 659 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 660 struct rte_ether_addr *mac_addr, 661 __rte_unused uint32_t index, __rte_unused uint32_t pool) 662 { 663 struct enic *enic = pmd_priv(eth_dev); 664 665 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 666 return -E_RTE_SECONDARY; 667 668 ENICPMD_FUNC_TRACE(); 669 return enic_set_mac_address(enic, mac_addr->addr_bytes); 670 } 671 672 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 673 { 674 struct enic *enic = pmd_priv(eth_dev); 675 676 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 677 return; 678 679 ENICPMD_FUNC_TRACE(); 680 if (enic_del_mac_address(enic, index)) 681 dev_err(enic, "del mac addr failed\n"); 682 } 683 684 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 685 struct rte_ether_addr *addr) 686 { 687 struct enic *enic = pmd_priv(eth_dev); 688 int ret; 689 690 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 691 return -E_RTE_SECONDARY; 692 693 ENICPMD_FUNC_TRACE(); 694 ret = enic_del_mac_address(enic, 0); 695 if (ret) 696 return ret; 697 return enic_set_mac_address(enic, addr->addr_bytes); 698 } 699 700 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add) 701 { 702 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 703 704 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr); 705 PMD_INIT_LOG(DEBUG, " %s address %s\n", 706 add ? "add" : "remove", mac_str); 707 } 708 709 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev, 710 struct rte_ether_addr *mc_addr_set, 711 uint32_t nb_mc_addr) 712 { 713 struct enic *enic = pmd_priv(eth_dev); 714 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 715 struct rte_ether_addr *addr; 716 uint32_t i, j; 717 int ret; 718 719 ENICPMD_FUNC_TRACE(); 720 721 /* Validate the given addresses first */ 722 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) { 723 addr = &mc_addr_set[i]; 724 if (!rte_is_multicast_ether_addr(addr) || 725 rte_is_broadcast_ether_addr(addr)) { 726 rte_ether_format_addr(mac_str, 727 RTE_ETHER_ADDR_FMT_SIZE, addr); 728 PMD_INIT_LOG(ERR, " invalid multicast address %s\n", 729 mac_str); 730 return -EINVAL; 731 } 732 } 733 734 /* Flush all if requested */ 735 if (nb_mc_addr == 0 || mc_addr_set == NULL) { 736 PMD_INIT_LOG(DEBUG, " flush multicast addresses\n"); 737 for (i = 0; i < enic->mc_count; i++) { 738 addr = &enic->mc_addrs[i]; 739 debug_log_add_del_addr(addr, false); 740 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 741 if (ret) 742 return ret; 743 } 744 enic->mc_count = 0; 745 return 0; 746 } 747 748 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) { 749 PMD_INIT_LOG(ERR, " too many multicast addresses: max=%d\n", 750 ENIC_MULTICAST_PERFECT_FILTERS); 751 return -ENOSPC; 752 } 753 /* 754 * devcmd is slow, so apply the difference instead of flushing and 755 * adding everything. 756 * 1. Delete addresses on the NIC but not on the host 757 */ 758 for (i = 0; i < enic->mc_count; i++) { 759 addr = &enic->mc_addrs[i]; 760 for (j = 0; j < nb_mc_addr; j++) { 761 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) 762 break; 763 } 764 if (j < nb_mc_addr) 765 continue; 766 debug_log_add_del_addr(addr, false); 767 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 768 if (ret) 769 return ret; 770 } 771 /* 2. Add addresses on the host but not on the NIC */ 772 for (i = 0; i < nb_mc_addr; i++) { 773 addr = &mc_addr_set[i]; 774 for (j = 0; j < enic->mc_count; j++) { 775 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j])) 776 break; 777 } 778 if (j < enic->mc_count) 779 continue; 780 debug_log_add_del_addr(addr, true); 781 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes); 782 if (ret) 783 return ret; 784 } 785 /* Keep a copy so we can flush/apply later on.. */ 786 memcpy(enic->mc_addrs, mc_addr_set, 787 nb_mc_addr * sizeof(struct rte_ether_addr)); 788 enic->mc_count = nb_mc_addr; 789 return 0; 790 } 791 792 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 793 { 794 struct enic *enic = pmd_priv(eth_dev); 795 796 ENICPMD_FUNC_TRACE(); 797 return enic_set_mtu(enic, mtu); 798 } 799 800 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 801 struct rte_eth_rss_reta_entry64 802 *reta_conf, 803 uint16_t reta_size) 804 { 805 struct enic *enic = pmd_priv(dev); 806 uint16_t i, idx, shift; 807 808 ENICPMD_FUNC_TRACE(); 809 if (reta_size != ENIC_RSS_RETA_SIZE) { 810 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 811 reta_size, ENIC_RSS_RETA_SIZE); 812 return -EINVAL; 813 } 814 815 for (i = 0; i < reta_size; i++) { 816 idx = i / RTE_RETA_GROUP_SIZE; 817 shift = i % RTE_RETA_GROUP_SIZE; 818 if (reta_conf[idx].mask & (1ULL << shift)) 819 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 820 enic->rss_cpu.cpu[i / 4].b[i % 4]); 821 } 822 823 return 0; 824 } 825 826 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 827 struct rte_eth_rss_reta_entry64 828 *reta_conf, 829 uint16_t reta_size) 830 { 831 struct enic *enic = pmd_priv(dev); 832 union vnic_rss_cpu rss_cpu; 833 uint16_t i, idx, shift; 834 835 ENICPMD_FUNC_TRACE(); 836 if (reta_size != ENIC_RSS_RETA_SIZE) { 837 dev_err(enic, "reta_update: wrong reta_size. given=%u" 838 " expected=%u\n", 839 reta_size, ENIC_RSS_RETA_SIZE); 840 return -EINVAL; 841 } 842 /* 843 * Start with the current reta and modify it per reta_conf, as we 844 * need to push the entire reta even if we only modify one entry. 845 */ 846 rss_cpu = enic->rss_cpu; 847 for (i = 0; i < reta_size; i++) { 848 idx = i / RTE_RETA_GROUP_SIZE; 849 shift = i % RTE_RETA_GROUP_SIZE; 850 if (reta_conf[idx].mask & (1ULL << shift)) 851 rss_cpu.cpu[i / 4].b[i % 4] = 852 enic_rte_rq_idx_to_sop_idx( 853 reta_conf[idx].reta[shift]); 854 } 855 return enic_set_rss_reta(enic, &rss_cpu); 856 } 857 858 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 859 struct rte_eth_rss_conf *rss_conf) 860 { 861 struct enic *enic = pmd_priv(dev); 862 863 ENICPMD_FUNC_TRACE(); 864 return enic_set_rss_conf(enic, rss_conf); 865 } 866 867 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 868 struct rte_eth_rss_conf *rss_conf) 869 { 870 struct enic *enic = pmd_priv(dev); 871 872 ENICPMD_FUNC_TRACE(); 873 if (rss_conf == NULL) 874 return -EINVAL; 875 if (rss_conf->rss_key != NULL && 876 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 877 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 878 " expected=%u+\n", 879 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 880 return -EINVAL; 881 } 882 rss_conf->rss_hf = enic->rss_hf; 883 if (rss_conf->rss_key != NULL) { 884 int i; 885 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 886 rss_conf->rss_key[i] = 887 enic->rss_key.key[i / 10].b[i % 10]; 888 } 889 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 890 } 891 return 0; 892 } 893 894 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 895 uint16_t rx_queue_id, 896 struct rte_eth_rxq_info *qinfo) 897 { 898 struct enic *enic = pmd_priv(dev); 899 struct vnic_rq *rq_sop; 900 struct vnic_rq *rq_data; 901 struct rte_eth_rxconf *conf; 902 uint16_t sop_queue_idx; 903 uint16_t data_queue_idx; 904 905 ENICPMD_FUNC_TRACE(); 906 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 907 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id); 908 rq_sop = &enic->rq[sop_queue_idx]; 909 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 910 qinfo->mp = rq_sop->mp; 911 qinfo->scattered_rx = rq_sop->data_queue_enable; 912 qinfo->nb_desc = rq_sop->ring.desc_count; 913 if (qinfo->scattered_rx) 914 qinfo->nb_desc += rq_data->ring.desc_count; 915 conf = &qinfo->conf; 916 memset(conf, 0, sizeof(*conf)); 917 conf->rx_free_thresh = rq_sop->rx_free_thresh; 918 conf->rx_drop_en = 1; 919 /* 920 * Except VLAN stripping (port setting), all the checksum offloads 921 * are always enabled. 922 */ 923 conf->offloads = enic->rx_offload_capa; 924 if (!enic->ig_vlan_strip_en) 925 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 926 /* rx_thresh and other fields are not applicable for enic */ 927 } 928 929 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 930 uint16_t tx_queue_id, 931 struct rte_eth_txq_info *qinfo) 932 { 933 struct enic *enic = pmd_priv(dev); 934 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 935 936 ENICPMD_FUNC_TRACE(); 937 qinfo->nb_desc = wq->ring.desc_count; 938 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 939 qinfo->conf.offloads = wq->offloads; 940 /* tx_thresh, and all the other fields are not applicable for enic */ 941 } 942 943 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 944 uint16_t rx_queue_id) 945 { 946 struct enic *enic = pmd_priv(eth_dev); 947 948 ENICPMD_FUNC_TRACE(); 949 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 950 return 0; 951 } 952 953 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 954 uint16_t rx_queue_id) 955 { 956 struct enic *enic = pmd_priv(eth_dev); 957 958 ENICPMD_FUNC_TRACE(); 959 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 960 return 0; 961 } 962 963 static int udp_tunnel_common_check(struct enic *enic, 964 struct rte_eth_udp_tunnel *tnl) 965 { 966 if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN) 967 return -ENOTSUP; 968 if (!enic->overlay_offload) { 969 PMD_INIT_LOG(DEBUG, " vxlan (overlay offload) is not " 970 "supported\n"); 971 return -ENOTSUP; 972 } 973 return 0; 974 } 975 976 static int update_vxlan_port(struct enic *enic, uint16_t port) 977 { 978 if (vnic_dev_overlay_offload_cfg(enic->vdev, 979 OVERLAY_CFG_VXLAN_PORT_UPDATE, 980 port)) { 981 PMD_INIT_LOG(DEBUG, " failed to update vxlan port\n"); 982 return -EINVAL; 983 } 984 PMD_INIT_LOG(DEBUG, " updated vxlan port to %u\n", port); 985 enic->vxlan_port = port; 986 return 0; 987 } 988 989 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 990 struct rte_eth_udp_tunnel *tnl) 991 { 992 struct enic *enic = pmd_priv(eth_dev); 993 int ret; 994 995 ENICPMD_FUNC_TRACE(); 996 ret = udp_tunnel_common_check(enic, tnl); 997 if (ret) 998 return ret; 999 /* 1000 * The NIC has 1 configurable VXLAN port number. "Adding" a new port 1001 * number replaces it. 1002 */ 1003 if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) { 1004 PMD_INIT_LOG(DEBUG, " %u is already configured or invalid\n", 1005 tnl->udp_port); 1006 return -EINVAL; 1007 } 1008 return update_vxlan_port(enic, tnl->udp_port); 1009 } 1010 1011 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 1012 struct rte_eth_udp_tunnel *tnl) 1013 { 1014 struct enic *enic = pmd_priv(eth_dev); 1015 int ret; 1016 1017 ENICPMD_FUNC_TRACE(); 1018 ret = udp_tunnel_common_check(enic, tnl); 1019 if (ret) 1020 return ret; 1021 /* 1022 * Clear the previously set port number and restore the 1023 * hardware default port number. Some drivers disable VXLAN 1024 * offloads when there are no configured port numbers. But 1025 * enic does not do that as VXLAN is part of overlay offload, 1026 * which is tied to inner RSS and TSO. 1027 */ 1028 if (tnl->udp_port != enic->vxlan_port) { 1029 PMD_INIT_LOG(DEBUG, " %u is not a configured vxlan port\n", 1030 tnl->udp_port); 1031 return -EINVAL; 1032 } 1033 return update_vxlan_port(enic, ENIC_DEFAULT_VXLAN_PORT); 1034 } 1035 1036 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev, 1037 char *fw_version, size_t fw_size) 1038 { 1039 struct vnic_devcmd_fw_info *info; 1040 struct enic *enic; 1041 int ret; 1042 1043 ENICPMD_FUNC_TRACE(); 1044 if (fw_version == NULL || fw_size <= 0) 1045 return -EINVAL; 1046 enic = pmd_priv(eth_dev); 1047 ret = vnic_dev_fw_info(enic->vdev, &info); 1048 if (ret) 1049 return ret; 1050 snprintf(fw_version, fw_size, "%s %s", 1051 info->fw_version, info->fw_build); 1052 fw_version[fw_size - 1] = '\0'; 1053 return 0; 1054 } 1055 1056 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 1057 .dev_configure = enicpmd_dev_configure, 1058 .dev_start = enicpmd_dev_start, 1059 .dev_stop = enicpmd_dev_stop, 1060 .dev_set_link_up = NULL, 1061 .dev_set_link_down = NULL, 1062 .dev_close = enicpmd_dev_close, 1063 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 1064 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 1065 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 1066 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 1067 .link_update = enicpmd_dev_link_update, 1068 .stats_get = enicpmd_dev_stats_get, 1069 .stats_reset = enicpmd_dev_stats_reset, 1070 .queue_stats_mapping_set = NULL, 1071 .dev_infos_get = enicpmd_dev_info_get, 1072 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 1073 .mtu_set = enicpmd_mtu_set, 1074 .vlan_filter_set = NULL, 1075 .vlan_tpid_set = NULL, 1076 .vlan_offload_set = enicpmd_vlan_offload_set, 1077 .vlan_strip_queue_set = NULL, 1078 .rx_queue_start = enicpmd_dev_rx_queue_start, 1079 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 1080 .tx_queue_start = enicpmd_dev_tx_queue_start, 1081 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 1082 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 1083 .rx_queue_release = enicpmd_dev_rx_queue_release, 1084 .rx_queue_count = enicpmd_dev_rx_queue_count, 1085 .rx_descriptor_done = NULL, 1086 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 1087 .tx_queue_release = enicpmd_dev_tx_queue_release, 1088 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 1089 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 1090 .rxq_info_get = enicpmd_dev_rxq_info_get, 1091 .txq_info_get = enicpmd_dev_txq_info_get, 1092 .dev_led_on = NULL, 1093 .dev_led_off = NULL, 1094 .flow_ctrl_get = NULL, 1095 .flow_ctrl_set = NULL, 1096 .priority_flow_ctrl_set = NULL, 1097 .mac_addr_add = enicpmd_add_mac_addr, 1098 .mac_addr_remove = enicpmd_remove_mac_addr, 1099 .mac_addr_set = enicpmd_set_mac_addr, 1100 .set_mc_addr_list = enicpmd_set_mc_addr_list, 1101 .filter_ctrl = enicpmd_dev_filter_ctrl, 1102 .reta_query = enicpmd_dev_rss_reta_query, 1103 .reta_update = enicpmd_dev_rss_reta_update, 1104 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 1105 .rss_hash_update = enicpmd_dev_rss_hash_update, 1106 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 1107 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 1108 .fw_version_get = enicpmd_dev_fw_version_get, 1109 }; 1110 1111 static int enic_parse_zero_one(const char *key, 1112 const char *value, 1113 void *opaque) 1114 { 1115 struct enic *enic; 1116 bool b; 1117 1118 enic = (struct enic *)opaque; 1119 if (strcmp(value, "0") == 0) { 1120 b = false; 1121 } else if (strcmp(value, "1") == 0) { 1122 b = true; 1123 } else { 1124 dev_err(enic, "Invalid value for %s" 1125 ": expected=0|1 given=%s\n", key, value); 1126 return -EINVAL; 1127 } 1128 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 1129 enic->disable_overlay = b; 1130 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 1131 enic->enable_avx2_rx = b; 1132 return 0; 1133 } 1134 1135 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 1136 const char *value, 1137 void *opaque) 1138 { 1139 struct enic *enic; 1140 1141 enic = (struct enic *)opaque; 1142 if (strcmp(value, "trunk") == 0) { 1143 /* Trunk mode: always tag */ 1144 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 1145 } else if (strcmp(value, "untag") == 0) { 1146 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 1147 enic->ig_vlan_rewrite_mode = 1148 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 1149 } else if (strcmp(value, "priority") == 0) { 1150 /* 1151 * Priority-tag default VLAN mode: priority tag (VLAN header 1152 * with ID=0) if VLAN = default 1153 */ 1154 enic->ig_vlan_rewrite_mode = 1155 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 1156 } else if (strcmp(value, "pass") == 0) { 1157 /* Pass through mode: do not touch tags */ 1158 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1159 } else { 1160 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 1161 ": expected=trunk|untag|priority|pass given=%s\n", 1162 value); 1163 return -EINVAL; 1164 } 1165 return 0; 1166 } 1167 1168 static int enic_check_devargs(struct rte_eth_dev *dev) 1169 { 1170 static const char *const valid_keys[] = { 1171 ENIC_DEVARG_DISABLE_OVERLAY, 1172 ENIC_DEVARG_ENABLE_AVX2_RX, 1173 ENIC_DEVARG_IG_VLAN_REWRITE, 1174 NULL}; 1175 struct enic *enic = pmd_priv(dev); 1176 struct rte_kvargs *kvlist; 1177 1178 ENICPMD_FUNC_TRACE(); 1179 1180 enic->disable_overlay = false; 1181 enic->enable_avx2_rx = false; 1182 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1183 if (!dev->device->devargs) 1184 return 0; 1185 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1186 if (!kvlist) 1187 return -EINVAL; 1188 if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 1189 enic_parse_zero_one, enic) < 0 || 1190 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 1191 enic_parse_zero_one, enic) < 0 || 1192 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1193 enic_parse_ig_vlan_rewrite, enic) < 0) { 1194 rte_kvargs_free(kvlist); 1195 return -EINVAL; 1196 } 1197 rte_kvargs_free(kvlist); 1198 return 0; 1199 } 1200 1201 /* Initialize the driver 1202 * It returns 0 on success. 1203 */ 1204 static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev) 1205 { 1206 struct rte_pci_device *pdev; 1207 struct rte_pci_addr *addr; 1208 struct enic *enic = pmd_priv(eth_dev); 1209 int err; 1210 1211 ENICPMD_FUNC_TRACE(); 1212 1213 enic->port_id = eth_dev->data->port_id; 1214 enic->rte_dev = eth_dev; 1215 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1216 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1217 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1218 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1219 /* Let rte_eth_dev_close() release the port resources */ 1220 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1221 1222 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1223 rte_eth_copy_pci_info(eth_dev, pdev); 1224 enic->pdev = pdev; 1225 addr = &pdev->addr; 1226 1227 snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x", 1228 addr->domain, addr->bus, addr->devid, addr->function); 1229 1230 err = enic_check_devargs(eth_dev); 1231 if (err) 1232 return err; 1233 return enic_probe(enic); 1234 } 1235 1236 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1237 struct rte_pci_device *pci_dev) 1238 { 1239 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct enic), 1240 eth_enicpmd_dev_init); 1241 } 1242 1243 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1244 { 1245 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 1246 } 1247 1248 static struct rte_pci_driver rte_enic_pmd = { 1249 .id_table = pci_id_enic_map, 1250 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 1251 RTE_PCI_DRV_IOVA_AS_VA, 1252 .probe = eth_enic_pci_probe, 1253 .remove = eth_enic_pci_remove, 1254 }; 1255 1256 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1257 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1258 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1259 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1260 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1261 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1262 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1263