1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #ifndef _VNIC_RESOURCE_H_ 7 #define _VNIC_RESOURCE_H_ 8 9 #define VNIC_RES_MAGIC 0x766E6963L /* 'vnic' */ 10 #define VNIC_RES_VERSION 0x00000000L 11 #define MGMTVNIC_MAGIC 0x544d474dL /* 'MGMT' */ 12 #define MGMTVNIC_VERSION 0x00000000L 13 14 /* The MAC address assigned to the CFG vNIC is fixed. */ 15 #define MGMTVNIC_MAC { 0x02, 0x00, 0x54, 0x4d, 0x47, 0x4d } 16 17 /* vNIC resource types */ 18 enum vnic_res_type { 19 RES_TYPE_EOL, /* End-of-list */ 20 RES_TYPE_WQ, /* Work queues */ 21 RES_TYPE_RQ, /* Receive queues */ 22 RES_TYPE_CQ, /* Completion queues */ 23 RES_TYPE_MEM, /* Window to dev memory */ 24 RES_TYPE_NIC_CFG, /* Enet NIC config registers */ 25 RES_TYPE_RSS_KEY, /* Enet RSS secret key */ 26 RES_TYPE_RSS_CPU, /* Enet RSS indirection table */ 27 RES_TYPE_TX_STATS, /* Netblock Tx statistic regs */ 28 RES_TYPE_RX_STATS, /* Netblock Rx statistic regs */ 29 RES_TYPE_INTR_CTRL, /* Interrupt ctrl table */ 30 RES_TYPE_INTR_TABLE, /* MSI/MSI-X Interrupt table */ 31 RES_TYPE_INTR_PBA, /* MSI/MSI-X PBA table */ 32 RES_TYPE_INTR_PBA_LEGACY, /* Legacy intr status */ 33 RES_TYPE_DEBUG, /* Debug-only info */ 34 RES_TYPE_DEV, /* Device-specific region */ 35 RES_TYPE_DEVCMD, /* Device command region */ 36 RES_TYPE_PASS_THRU_PAGE, /* Pass-thru page */ 37 RES_TYPE_SUBVNIC, /* subvnic resource type */ 38 RES_TYPE_MQ_WQ, /* MQ Work queues */ 39 RES_TYPE_MQ_RQ, /* MQ Receive queues */ 40 RES_TYPE_MQ_CQ, /* MQ Completion queues */ 41 RES_TYPE_DEPRECATED1, /* Old version of devcmd 2 */ 42 RES_TYPE_DEPRECATED2, /* Old version of devcmd 2 */ 43 RES_TYPE_DEVCMD2, /* Device control region */ 44 RES_TYPE_RDMA_WQ, /* RDMA WQ */ 45 RES_TYPE_RDMA_RQ, /* RDMA RQ */ 46 RES_TYPE_RDMA_CQ, /* RDMA CQ */ 47 RES_TYPE_RDMA_RKEY_TABLE, /* RDMA RKEY table */ 48 RES_TYPE_RDMA_RQ_HEADER_TABLE, /* RDMA RQ Header Table */ 49 RES_TYPE_RDMA_RQ_TABLE, /* RDMA RQ Table */ 50 RES_TYPE_RDMA_RD_RESP_HEADER_TABLE, /* RDMA Read Response Header Table */ 51 RES_TYPE_RDMA_RD_RESP_TABLE, /* RDMA Read Response Table */ 52 RES_TYPE_RDMA_QP_STATS_TABLE, /* RDMA per QP stats table */ 53 RES_TYPE_WQ_MREGS, /* XXX snic proto only */ 54 RES_TYPE_GRPMBR_INTR, /* Group member interrupt control */ 55 RES_TYPE_DPKT, /* Direct Packet memory region */ 56 RES_TYPE_RDMA2_DATA_WQ, /* RDMA datapath command WQ */ 57 RES_TYPE_RDMA2_REG_WQ, /* RDMA registration command WQ */ 58 RES_TYPE_RDMA2_CQ, /* RDMA datapath CQ */ 59 RES_TYPE_MQ_RDMA2_DATA_WQ, /* RDMA datapath command WQ */ 60 RES_TYPE_MQ_RDMA2_REG_WQ, /* RDMA registration command WQ */ 61 RES_TYPE_MQ_RDMA2_CQ, /* RDMA datapath CQ */ 62 RES_TYPE_PTP, /* PTP registers */ 63 RES_TYPE_INTR_CTRL2, /* Extended INTR CTRL registers */ 64 RES_TYPE_SRIOV_INTR, /* VF intr */ 65 RES_TYPE_VF_WQ, /* VF WQ */ 66 RES_TYPE_VF_RQ, /* VF RQ */ 67 RES_TYPE_VF_CQ, /* VF CQ */ 68 RES_TYPE_ADMIN_WQ, /* admin channel WQ */ 69 RES_TYPE_ADMIN_RQ, /* admin channel RQ */ 70 RES_TYPE_ADMIN_CQ, /* admin channel CQ */ 71 RES_TYPE_MAX, /* Count of resource types */ 72 }; 73 74 struct vnic_resource_header { 75 uint32_t magic; 76 uint32_t version; 77 }; 78 79 struct mgmt_barmap_hdr { 80 uint32_t magic; /* magic number */ 81 uint32_t version; /* header format version */ 82 uint16_t lif; /* loopback lif for mgmt frames */ 83 uint16_t pci_slot; /* installed pci slot */ 84 char serial[16]; /* card serial number */ 85 }; 86 87 struct vnic_resource { 88 uint8_t type; 89 uint8_t bar; 90 uint8_t pad[2]; 91 uint32_t bar_offset; 92 uint32_t count; 93 }; 94 95 #endif /* _VNIC_RESOURCE_H_ */ 96